diff options
author | TatWai Chong <tatwai.chong@arm.com> | 2020-06-14 00:42:39 -0700 |
---|---|---|
committer | TatWai Chong <tatwai.chong@arm.com> | 2020-06-22 12:50:57 -0700 |
commit | cd3f6c5ec96ff6d8240a07e7084ae5de700dc9c7 (patch) | |
tree | 79c5d837f6ba94761433ea31210281ec99e68d2c /src | |
parent | 50ef1718db4adc541347dd5a9259fdd8663d96b3 (diff) | |
download | vixl-cd3f6c5ec96ff6d8240a07e7084ae5de700dc9c7.tar.gz |
[sve] Fix the index specifier decoding error in the gather load helper.
In the simulation of the scalar-plus-vector form of gather loads,
the helper hasn't considered shift specifiers in the decoding, so
64-bit unscaled/scaled offset forms haven't been generated and tested.
Change-Id: If4539de5a1b4e6760780fdbaefd56dc84dd47413
Diffstat (limited to 'src')
-rw-r--r-- | src/aarch64/logic-aarch64.cc | 4 | ||||
-rw-r--r-- | src/aarch64/simulator-aarch64.cc | 21 | ||||
-rw-r--r-- | src/aarch64/simulator-aarch64.h | 3 |
3 files changed, 18 insertions, 10 deletions
diff --git a/src/aarch64/logic-aarch64.cc b/src/aarch64/logic-aarch64.cc index 3ac41e2f..9684355a 100644 --- a/src/aarch64/logic-aarch64.cc +++ b/src/aarch64/logic-aarch64.cc @@ -7262,14 +7262,14 @@ void Simulator::SVEFaultTolerantLoadHelper(VectorFormat vform, } void Simulator::SVEGatherLoadScalarPlusVectorHelper(const Instruction* instr, - VectorFormat vform) { + VectorFormat vform, + SVEOffsetModifier mod) { bool is_signed = instr->ExtractBit(14) == 0; bool is_ff = instr->ExtractBit(13) == 1; // Note that these instructions don't use the Dtype encoding. int msize_in_bytes_log2 = instr->ExtractBits(24, 23); int scale = instr->ExtractBit(21) * msize_in_bytes_log2; uint64_t base = ReadXRegister(instr->GetRn()); - SVEOffsetModifier mod = (instr->ExtractBit(22) == 1) ? SVE_SXTW : SVE_UXTW; LogicSVEAddressVector addr(base, &ReadVRegister(instr->GetRm()), vform, diff --git a/src/aarch64/simulator-aarch64.cc b/src/aarch64/simulator-aarch64.cc index 9b69fcea..d0fa2b90 100644 --- a/src/aarch64/simulator-aarch64.cc +++ b/src/aarch64/simulator-aarch64.cc @@ -9540,7 +9540,8 @@ void Simulator::VisitSVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsets( break; } - SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnS); + SVEOffsetModifier mod = (instr->ExtractBit(22) == 1) ? SVE_SXTW : SVE_UXTW; + SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnS, mod); } void Simulator::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets( @@ -9563,7 +9564,8 @@ void Simulator::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets( break; } - SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnS); + SVEOffsetModifier mod = (instr->ExtractBit(22) == 1) ? SVE_SXTW : SVE_UXTW; + SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnS, mod); } void Simulator::VisitSVE32BitGatherLoad_VectorPlusImm( @@ -9619,7 +9621,8 @@ void Simulator::VisitSVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsets( break; } - SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnS); + SVEOffsetModifier mod = (instr->ExtractBit(22) == 1) ? SVE_SXTW : SVE_UXTW; + SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnS, mod); } void Simulator::VisitSVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsets( @@ -9805,7 +9808,8 @@ void Simulator::VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets( break; } - SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnD); + SVEOffsetModifier mod = (instr->ExtractBit(22) == 1) ? SVE_SXTW : SVE_UXTW; + SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnD, mod); } void Simulator::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets( @@ -9838,7 +9842,7 @@ void Simulator::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets( break; } - SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnD); + SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnD, SVE_LSL); } void Simulator::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets( @@ -9865,7 +9869,9 @@ void Simulator::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets( break; } - SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnD); + SVEGatherLoadScalarPlusVectorHelper(instr, + kFormatVnD, + NO_SVE_OFFSET_MODIFIER); } void Simulator::VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets( @@ -9907,7 +9913,8 @@ void Simulator::VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets( break; } - SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnD); + SVEOffsetModifier mod = (instr->ExtractBit(22) == 1) ? SVE_SXTW : SVE_UXTW; + SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnD, mod); } void Simulator::VisitSVE64BitGatherLoad_VectorPlusImm( diff --git a/src/aarch64/simulator-aarch64.h b/src/aarch64/simulator-aarch64.h index bfb1c500..1a89dff7 100644 --- a/src/aarch64/simulator-aarch64.h +++ b/src/aarch64/simulator-aarch64.h @@ -4362,7 +4362,8 @@ class Simulator : public DecoderVisitor { FlagsUpdate flags = SetFlags); void SVEGatherLoadScalarPlusVectorHelper(const Instruction* instr, - VectorFormat vform); + VectorFormat vform, + SVEOffsetModifier mod); // Store each active zt<i>[lane] to `addr.GetElementAddress(lane, ...)`. // |