diff options
| author | Martyn Capewell <martyn.capewell@arm.com> | 2020-07-02 14:30:50 +0100 |
|---|---|---|
| committer | Martyn Capewell <martyn.capewell@arm.com> | 2020-07-02 17:16:26 +0100 |
| commit | ecca4b1c75222ca840707f00ea39df1ddb657b3b (patch) | |
| tree | 87368a4d76cef9be3fe8306597e2e9a280f4f809 /src | |
| parent | 4606adc3f68d4e8ca1366d39894b025aec197d0f (diff) | |
| download | vixl-ecca4b1c75222ca840707f00ea39df1ddb657b3b.tar.gz | |
Disallow x31/xzr for SVE prefetch scalar offset register
The architecture disallows rm = x31/xzr for prefetch, so assert this in the
assembler.
Change-Id: I26e14688bde624d38eee40167fb3ada88acaaec7
Diffstat (limited to 'src')
| -rw-r--r-- | src/aarch64/assembler-sve-aarch64.cc | 1 | ||||
| -rw-r--r-- | src/aarch64/disasm-aarch64.cc | 40 | ||||
| -rw-r--r-- | src/aarch64/simulator-aarch64.cc | 4 |
3 files changed, 25 insertions, 20 deletions
diff --git a/src/aarch64/assembler-sve-aarch64.cc b/src/aarch64/assembler-sve-aarch64.cc index a09691af..59ee2979 100644 --- a/src/aarch64/assembler-sve-aarch64.cc +++ b/src/aarch64/assembler-sve-aarch64.cc @@ -4577,6 +4577,7 @@ void Assembler::SVEContiguousPrefetchScalarPlusScalarHelper( break; } + VIXL_ASSERT(!addr.GetScalarOffset().IsZero()); Emit(op | SVEImmPrefetchOperation(prfop) | PgLow8(pg) | RnSP(addr.GetScalarBase()) | Rm(addr.GetScalarOffset())); } diff --git a/src/aarch64/disasm-aarch64.cc b/src/aarch64/disasm-aarch64.cc index a2bf53ee..4e2bca35 100644 --- a/src/aarch64/disasm-aarch64.cc +++ b/src/aarch64/disasm-aarch64.cc @@ -6367,25 +6367,27 @@ void Disassembler::VisitSVEContiguousPrefetch_ScalarPlusScalar( const char *mnemonic = "unimplemented"; const char *form = "(SVEContiguousPrefetch_ScalarPlusScalar)"; - switch (instr->Mask(SVEContiguousPrefetch_ScalarPlusScalarMask)) { - case PRFB_i_p_br_s: - mnemonic = "prfb"; - form = "'prefSVEOp, 'Pgl, ['Xns, 'Rm]"; - break; - case PRFD_i_p_br_s: - mnemonic = "prfd"; - form = "'prefSVEOp, 'Pgl, ['Xns, 'Rm, lsl #3]"; - break; - case PRFH_i_p_br_s: - mnemonic = "prfh"; - form = "'prefSVEOp, 'Pgl, ['Xns, 'Rm, lsl #1]"; - break; - case PRFW_i_p_br_s: - mnemonic = "prfw"; - form = "'prefSVEOp, 'Pgl, ['Xns, 'Rm, lsl #2]"; - break; - default: - break; + if (instr->GetRm() != kZeroRegCode) { + switch (instr->Mask(SVEContiguousPrefetch_ScalarPlusScalarMask)) { + case PRFB_i_p_br_s: + mnemonic = "prfb"; + form = "'prefSVEOp, 'Pgl, ['Xns, 'Rm]"; + break; + case PRFD_i_p_br_s: + mnemonic = "prfd"; + form = "'prefSVEOp, 'Pgl, ['Xns, 'Rm, lsl #3]"; + break; + case PRFH_i_p_br_s: + mnemonic = "prfh"; + form = "'prefSVEOp, 'Pgl, ['Xns, 'Rm, lsl #1]"; + break; + case PRFW_i_p_br_s: + mnemonic = "prfw"; + form = "'prefSVEOp, 'Pgl, ['Xns, 'Rm, lsl #2]"; + break; + default: + break; + } } Format(instr, mnemonic, form); } diff --git a/src/aarch64/simulator-aarch64.cc b/src/aarch64/simulator-aarch64.cc index 52aac1d3..40e3a9fa 100644 --- a/src/aarch64/simulator-aarch64.cc +++ b/src/aarch64/simulator-aarch64.cc @@ -9657,13 +9657,15 @@ void Simulator::VisitSVEContiguousPrefetch_ScalarPlusImm( void Simulator::VisitSVEContiguousPrefetch_ScalarPlusScalar( const Instruction* instr) { - USE(instr); switch (instr->Mask(SVEContiguousPrefetch_ScalarPlusScalarMask)) { // Ignore prefetch hint instructions. case PRFB_i_p_br_s: case PRFD_i_p_br_s: case PRFH_i_p_br_s: case PRFW_i_p_br_s: + if (instr->GetRm() == kZeroRegCode) { + VIXL_UNIMPLEMENTED(); + } break; default: VIXL_UNIMPLEMENTED(); |