Add missing aliases for SVE 0.0 moves.

Change-Id: I608c610da7de42328ed3984dabb56cf1401d7a15

2 files changed, 16 insertions, 2 deletions

diff --git a/src/aarch64/assembler-sve-aarch64.cc b/src/aarch64/assembler-sve-aarch64.cc
index 0a2033d8..c33e8552 100644
--- a/src/aarch64/assembler-sve-aarch64.cc
+++ b/src/aarch64/assembler-sve-aarch64.cc
@@ -6364,10 +6364,20 @@ void Assembler::orn(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
 
 
 void Assembler::fmov(const ZRegister& zd, const PRegisterM& pg, double imm) {
-  fcpy(zd, pg, imm);
+  if (IsPositiveZero(imm)) {
+    cpy(zd, pg, 0);
+  } else {
+    fcpy(zd, pg, imm);
+  }
 }
 
-void Assembler::fmov(const ZRegister& zd, double imm) { fdup(zd, imm); }
+void Assembler::fmov(const ZRegister& zd, double imm) {
+  if (IsPositiveZero(imm)) {
+    dup(zd, imm);
+  } else {
+    fdup(zd, imm);
+  }
+}
 
 void Assembler::mov(const PRegister& pd, const PRegister& pn) {
   // If the inputs carry a lane size, they must match.
diff --git a/src/utils-vixl.h b/src/utils-vixl.h
index 1e7d3e60..0ae6dfc0 100644
--- a/src/utils-vixl.h
+++ b/src/utils-vixl.h
@@ -389,6 +389,10 @@ VIXL_DEPRECATED("Float16Classify", inline int float16classify(uint16_t value)) {
 
 bool IsZero(Float16 value);
 
+inline bool IsPositiveZero(double value) {
+  return (value == 0.0) && (copysign(1.0, value) > 0.0);
+}
+
 inline bool IsNaN(float value) { return std::isnan(value); }
 
 inline bool IsNaN(double value) { return std::isnan(value); }