diff options
author | Martyn Capewell <martyn.capewell@arm.com> | 2020-07-29 16:54:04 +0100 |
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committer | Martyn Capewell <martyn.capewell@arm.com> | 2020-07-29 16:55:37 +0100 |
commit | f84b4643727572209374b58fdd88ef6c34913704 (patch) | |
tree | 62eca789689e05c52f160620782fa8e68f1265ac /src | |
parent | aaf02c54f1f68153d769db26577317e1d4f46c1b (diff) | |
download | vixl-f84b4643727572209374b58fdd88ef6c34913704.tar.gz |
Revert optimisation for add/sub immediates
Removed due to some cases showing worse performance.
Reverts:
960606b686f59d468f97dfa93b5dba5b2b38cc8f
f3f5d246129febc518cfa99003ee66c5008202c5
Change-Id: I5b9585d112424d97e372bd264d084cb9caf92b5f
Diffstat (limited to 'src')
-rw-r--r-- | src/aarch64/macro-assembler-aarch64.cc | 66 |
1 files changed, 25 insertions, 41 deletions
diff --git a/src/aarch64/macro-assembler-aarch64.cc b/src/aarch64/macro-assembler-aarch64.cc index b5ffb1f4..1e81a8d7 100644 --- a/src/aarch64/macro-assembler-aarch64.cc +++ b/src/aarch64/macro-assembler-aarch64.cc @@ -1427,16 +1427,12 @@ void MacroAssembler::Add(const Register& rd, const Operand& operand, FlagsUpdate S) { VIXL_ASSERT(allow_macro_instructions_); - if (operand.IsImmediate()) { - int64_t min = rd.IsX() ? std::numeric_limits<int64_t>::min() - : std::numeric_limits<int32_t>::min(); - int64_t imm = operand.GetImmediate(); - if ((imm < 0) && (imm > min)) { - AddSubMacro(rd, rn, -imm, S, SUB); - return; - } + if (operand.IsImmediate() && (operand.GetImmediate() < 0) && + IsImmAddSub(-operand.GetImmediate())) { + AddSubMacro(rd, rn, -operand.GetImmediate(), S, SUB); + } else { + AddSubMacro(rd, rn, operand, S, ADD); } - AddSubMacro(rd, rn, operand, S, ADD); } @@ -1452,16 +1448,12 @@ void MacroAssembler::Sub(const Register& rd, const Operand& operand, FlagsUpdate S) { VIXL_ASSERT(allow_macro_instructions_); - if (operand.IsImmediate()) { - int64_t min = rd.IsX() ? std::numeric_limits<int64_t>::min() - : std::numeric_limits<int32_t>::min(); - int64_t imm = operand.GetImmediate(); - if ((imm < 0) && (imm > min)) { - AddSubMacro(rd, rn, -imm, S, ADD); - return; - } + if (operand.IsImmediate() && (operand.GetImmediate() < 0) && + IsImmAddSub(-operand.GetImmediate())) { + AddSubMacro(rd, rn, -operand.GetImmediate(), S, ADD); + } else { + AddSubMacro(rd, rn, operand, S, SUB); } - AddSubMacro(rd, rn, operand, S, SUB); } @@ -1782,30 +1774,22 @@ void MacroAssembler::AddSubMacro(const Register& rd, // `rd`) because we don't need it after it is evaluated. Register temp = temps.AcquireSameSizeAs(rn); if (operand.IsImmediate()) { - int64_t imm = operand.GetImmediate(); - int64_t divisor = 1 << ImmAddSub_width; - if ((S == LeaveFlags) && IsUint12(imm / divisor)) { - // Unsigned immediates requiring up to 24 bits are emitted as two adds - // or subs. - AddSub(rd, rn, imm % divisor, S, op); - AddSub(rd, rd, (imm / divisor) << ImmAddSub_width, S, op); - } else { - PreShiftImmMode mode = kAnyShift; - - // If the destination or source register is the stack pointer, we can - // only pre-shift the immediate right by values supported in the add/sub - // extend encoding. - if (rd.IsSP()) { - // If the destination is SP and flags will be set, we can't pre-shift - // the immediate at all. - mode = (S == SetFlags) ? kNoShift : kLimitShiftForSP; - } else if (rn.IsSP()) { - mode = kLimitShiftForSP; - } - - Operand imm_operand = MoveImmediateForShiftedOp(temp, imm, mode); - AddSub(rd, rn, imm_operand, S, op); + PreShiftImmMode mode = kAnyShift; + + // If the destination or source register is the stack pointer, we can + // only pre-shift the immediate right by values supported in the add/sub + // extend encoding. + if (rd.IsSP()) { + // If the destination is SP and flags will be set, we can't pre-shift + // the immediate at all. + mode = (S == SetFlags) ? kNoShift : kLimitShiftForSP; + } else if (rn.IsSP()) { + mode = kLimitShiftForSP; } + + Operand imm_operand = + MoveImmediateForShiftedOp(temp, operand.GetImmediate(), mode); + AddSub(rd, rn, imm_operand, S, op); } else { Mov(temp, operand); AddSub(rd, rn, temp, S, op); |