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| author | Jacob Bramley <jacob.bramley@arm.com> | 2017-02-02 11:45:11 +0000 |
|---|---|---|
| committer | Jacob Bramley <jacob.bramley@arm.com> | 2017-02-02 13:31:40 +0000 |
| commit | bc38deb7addf1255df3b8f5f28b7949b761692d1 (patch) | |
| tree | ea01ba76b0cd3d0abc07d574bfc06778d5e1953a /test/aarch64 | |
| parent | 85919f840e8ddd06573def57eb587cc77661e7d0 (diff) | |
| download | vixl-bc38deb7addf1255df3b8f5f28b7949b761692d1.tar.gz | |
Fix Operand::IsPlainRegister.
- Operand(w0, UXTW) is not a plain register in a 64-bit context. The Operand
class doesn't know the context, so it must return false for UXTW and SXTW.
- Operand(x0, UXTX, 1) is not a plain register.
This patch also adds tests to check and demonstrate the behaviour.
Change-Id: I85a56a2d9d9ec6fce814f0e57a4f87dd7f21fd6c
Diffstat (limited to 'test/aarch64')
| -rw-r--r-- | test/aarch64/test-assembler-aarch64.cc | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/test/aarch64/test-assembler-aarch64.cc b/test/aarch64/test-assembler-aarch64.cc index 50e78005..f083b35a 100644 --- a/test/aarch64/test-assembler-aarch64.cc +++ b/test/aarch64/test-assembler-aarch64.cc @@ -23316,5 +23316,44 @@ TEST(static_register_types) { } +TEST(is_plain_register) { + SETUP(); + + VIXL_CHECK(Operand(x0).IsPlainRegister()); + VIXL_CHECK(Operand(x1, LSL, 0).IsPlainRegister()); + VIXL_CHECK(Operand(x2, LSR, 0).IsPlainRegister()); + VIXL_CHECK(Operand(x3, ASR, 0).IsPlainRegister()); + VIXL_CHECK(Operand(x4, ROR, 0).IsPlainRegister()); + VIXL_CHECK(Operand(x5, UXTX).IsPlainRegister()); + VIXL_CHECK(Operand(x6, SXTX).IsPlainRegister()); + VIXL_CHECK(Operand(w7).IsPlainRegister()); + VIXL_CHECK(Operand(w8, LSL, 0).IsPlainRegister()); + VIXL_CHECK(Operand(w9, LSR, 0).IsPlainRegister()); + VIXL_CHECK(Operand(w10, ASR, 0).IsPlainRegister()); + VIXL_CHECK(Operand(w11, ROR, 0).IsPlainRegister()); + + VIXL_CHECK(!Operand(x0, LSL, 1).IsPlainRegister()); + VIXL_CHECK(!Operand(x1, LSR, 2).IsPlainRegister()); + VIXL_CHECK(!Operand(x2, ASR, 3).IsPlainRegister()); + VIXL_CHECK(!Operand(x3, ROR, 4).IsPlainRegister()); + VIXL_CHECK(!Operand(x5, UXTX, 1).IsPlainRegister()); + VIXL_CHECK(!Operand(x6, SXTX, 2).IsPlainRegister()); + VIXL_CHECK(!Operand(w7, LSL, 1).IsPlainRegister()); + VIXL_CHECK(!Operand(w8, LSR, 2).IsPlainRegister()); + VIXL_CHECK(!Operand(w9, ASR, 3).IsPlainRegister()); + VIXL_CHECK(!Operand(w10, ROR, 4).IsPlainRegister()); + VIXL_CHECK(!Operand(w11, UXTB).IsPlainRegister()); + VIXL_CHECK(!Operand(w12, SXTB).IsPlainRegister()); + VIXL_CHECK(!Operand(w13, UXTH).IsPlainRegister()); + VIXL_CHECK(!Operand(w14, SXTH).IsPlainRegister()); + // UXTW and SXTW could be treated as plain registers in 32-bit contexts, but + // the Operand class doesn't know the context so it has to return false. + VIXL_CHECK(!Operand(w15, UXTW).IsPlainRegister()); + VIXL_CHECK(!Operand(w16, SXTW).IsPlainRegister()); + + TEARDOWN(); +} + + } // namespace aarch64 } // namespace vixl |