Add specialised W and X Register classes.

These allow for the register type to be determined at compile time, so that the
it can be used for overload resolution.

Note that this does break the API in the case of the ternary operator. The
following pattern will no longer work:

    Register r0 = (condition) ? x0 : w0;

The workaround is to explicitly cast each register:

    Register r0 = (condition) ? Register(x0) : Register(w0);

Some existing overload situation may also fail with the new scheme; in general,
resolutions can be added by simply providing specific WRegister and XRegister
implementations, which typically can fall through to the existing Register
implementation with an explicit cast.

In the future, we expect an extension which will make WRegister and XRegister
POD types.

Change-Id: I6da8e3f87161f23de7c13e3c5142d4fc40532090

2 files changed, 46 insertions, 7 deletions

diff --git a/test/aarch64/test-assembler-aarch64.cc b/test/aarch64/test-assembler-aarch64.cc
index 78f06436..6a8e6526 100644
--- a/test/aarch64/test-assembler-aarch64.cc
+++ b/test/aarch64/test-assembler-aarch64.cc
@@ -7091,9 +7091,9 @@ template <typename T>
 void LoadIntValueHelper(T values[], int card) {
   SETUP();
 
-  const bool is_32bits = (sizeof(T) == 4);
-  const Register& tgt1 = is_32bits ? w1 : x1;
-  const Register& tgt2 = is_32bits ? w2 : x2;
+  const bool is_32bit = (sizeof(T) == 4);
+  Register tgt1 = is_32bit ? Register(w1) : Register(x1);
+  Register tgt2 = is_32bit ? Register(w2) : Register(x2);
 
   START();
   __ Mov(x0, 0);
@@ -7142,8 +7142,8 @@ void LoadFPValueHelper(T values[], int card) {
 
   const bool is_32bits = (sizeof(T) == 4);
   const FPRegister& fp_tgt = is_32bits ? s2 : d2;
-  const Register& tgt1 = is_32bits ? w1 : x1;
-  const Register& tgt2 = is_32bits ? w2 : x2;
+  const Register& tgt1 = is_32bits ? Register(w1) : Register(x1);
+  const Register& tgt2 = is_32bits ? Register(w2) : Register(x2);
 
   START();
   __ Mov(x0, 0);
@@ -22624,5 +22624,44 @@ TEST(nop) {
 }
 
 
+TEST(static_register_types) {
+  SETUP();
+  START();
+
+  // [WX]Register implicitly casts to Register.
+  XRegister x_x0(0);
+  WRegister w_w0(0);
+  Register r_x0 = x_x0;
+  Register r_w0 = w_w0;
+  VIXL_CHECK(r_x0.Is(x_x0));
+  VIXL_CHECK(x_x0.Is(r_x0));
+  VIXL_CHECK(r_w0.Is(w_w0));
+  VIXL_CHECK(w_w0.Is(r_w0));
+
+  // Register explicitly casts to [WX]Register.
+  Register r_x1(1, kXRegSize);
+  Register r_w1(1, kWRegSize);
+  XRegister x_x1(r_x1);
+  WRegister w_w1(r_w1);
+  VIXL_CHECK(r_x1.Is(x_x1));
+  VIXL_CHECK(x_x1.Is(r_x1));
+  VIXL_CHECK(r_w1.Is(w_w1));
+  VIXL_CHECK(w_w1.Is(r_w1));
+
+  // [WX]Register implicitly casts to CPURegister.
+  XRegister x_x2(2);
+  WRegister w_w2(2);
+  CPURegister cpu_x2 = x_x2;
+  CPURegister cpu_w2 = w_w2;
+  VIXL_CHECK(cpu_x2.Is(x_x2));
+  VIXL_CHECK(x_x2.Is(cpu_x2));
+  VIXL_CHECK(cpu_w2.Is(w_w2));
+  VIXL_CHECK(w_w2.Is(cpu_w2));
+
+  END();
+  TEARDOWN();
+}
+
+
 }  // namespace aarch64
 }  // namespace vixl
diff --git a/test/aarch64/test-simulator-aarch64.cc b/test/aarch64/test-simulator-aarch64.cc
index 09705d6b..56d17e96 100644
--- a/test/aarch64/test-simulator-aarch64.cc
+++ b/test/aarch64/test-simulator-aarch64.cc
@@ -821,7 +821,7 @@ static void TestFPToFixed_Helper(TestFPToFixedHelper_t helper,
   const int n_index_shift =
       (n_size == kDRegSize) ? kDRegSizeInBytesLog2 : kSRegSizeInBytesLog2;
 
-  Register rd = (d_size == kXRegSize) ? x10 : w10;
+  Register rd = (d_size == kXRegSize) ? Register(x10) : Register(w10);
   FPRegister fn = (n_size == kDRegSize) ? d1 : s1;
 
   __ Mov(out, results);
@@ -870,7 +870,7 @@ static void TestFPToInt_Helper(TestFPToIntHelper_t helper, uintptr_t inputs,
   const int n_index_shift =
       (n_size == kDRegSize) ? kDRegSizeInBytesLog2 : kSRegSizeInBytesLog2;
 
-  Register rd = (d_size == kXRegSize) ? x10 : w10;
+  Register rd = (d_size == kXRegSize) ? Register(x10) : Register(w10);
   FPRegister fn = (n_size == kDRegSize) ? d1 : s1;
 
   __ Mov(out, results);