Add support for SQRDMLAH and SQRDMLSH.

Change-Id: I2b490d877e7e9db77608b84ab0b92aa972a54a6d

2 files changed, 167 insertions, 0 deletions

diff --git a/test/aarch64/test-assembler-aarch64.cc b/test/aarch64/test-assembler-aarch64.cc
index 0491a4e3..9cbe2f64 100644
--- a/test/aarch64/test-assembler-aarch64.cc
+++ b/test/aarch64/test-assembler-aarch64.cc
@@ -17256,6 +17256,135 @@ TEST(neon_byelement_sqdmulh_sqrdmulh) {
   TEARDOWN();
 }
 
+TEST(neon_3same_sqrdmlah) {
+  SETUP();
+
+  START();
+
+  __ Movi(v0.V2D(), 0x0000000000000000, 0x0000040004008000);
+  __ Movi(v1.V2D(), 0x0000000000000000, 0x0000002000108000);
+  __ Movi(v2.V2D(), 0x0400000080000000, 0x0400000080000000);
+  __ Movi(v3.V2D(), 0x0000002080000000, 0x0000001080000000);
+
+  __ Movi(v16.V2D(), 0x0000040004008000, 0x0000040004008000);
+  __ Movi(v17.V2D(), 0x0000000000000000, 0x0000002000108000);
+  __ Movi(v18.V2D(), 0x0400000080000000, 0x0400000080000000);
+  __ Movi(v19.V2D(), 0x0000002080000000, 0x0000001080000000);
+
+  __ Sqrdmlah(v16.V4H(), v0.V4H(), v1.V4H());
+  __ Sqrdmlah(v17.V4S(), v2.V4S(), v3.V4S());
+  __ Sqrdmlah(h18, h0, h1);
+  __ Sqrdmlah(s19, s2, s3);
+
+  END();
+
+// TODO: test on real hardware when available
+#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
+  RUN();
+  ASSERT_EQUAL_128(0, 0x0000040104010000, q16);
+  ASSERT_EQUAL_128(0x000000017fffffff, 0x000000217fffffff, q17);
+  ASSERT_EQUAL_128(0, 0x7fff, q18);
+  ASSERT_EQUAL_128(0, 0, q19);
+#endif
+  TEARDOWN();
+}
+
+TEST(neon_byelement_sqrdmlah) {
+  SETUP();
+
+  START();
+
+  __ Movi(v0.V2D(), 0x0000000000000000, 0x0000040004008000);
+  __ Movi(v1.V2D(), 0x0000000000000000, 0x0000002000108000);
+  __ Movi(v2.V2D(), 0x0400000080000000, 0x0400000080000000);
+  __ Movi(v3.V2D(), 0x0000002080000000, 0x0000001080000000);
+
+  __ Movi(v16.V2D(), 0x0000040004008000, 0x0000040004008000);
+  __ Movi(v17.V2D(), 0x0000000000000000, 0x0000002000108000);
+  __ Movi(v18.V2D(), 0x0400000080000000, 0x0400000080000000);
+  __ Movi(v19.V2D(), 0x0000002080000000, 0x0000001080000000);
+
+  __ Sqrdmlah(v16.V4H(), v0.V4H(), v1.H(), 1);
+  __ Sqrdmlah(v17.V4S(), v2.V4S(), v3.S(), 1);
+  __ Sqrdmlah(h18, h0, v1.H(), 0);
+  __ Sqrdmlah(s19, s2, v3.S(), 0);
+
+  END();
+
+#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
+  RUN();
+  ASSERT_EQUAL_128(0, 0x0000040104018000, q16);
+  ASSERT_EQUAL_128(0x00000001fffffff0, 0x0000002100107ff0, q17);
+  ASSERT_EQUAL_128(0, 0x7fff, q18);
+  ASSERT_EQUAL_128(0, 0, q19);
+#endif
+  TEARDOWN();
+}
+
+TEST(neon_3same_sqrdmlsh) {
+  SETUP();
+
+  START();
+
+  __ Movi(v0.V2D(), 0x0000000000000000, 0x0000040004000500);
+  __ Movi(v1.V2D(), 0x0000000000000000, 0x0000002000100080);
+  __ Movi(v2.V2D(), 0x0400000080000000, 0x0400000080000000);
+  __ Movi(v3.V2D(), 0x0000002080000000, 0x0000001080000000);
+
+  __ Movi(v16.V2D(), 0x4000400040004000, 0x4000400040004000);
+  __ Movi(v17.V2D(), 0x4000400040004000, 0x4000400040004000);
+  __ Movi(v18.V2D(), 0x4000400040004000, 0x4000400040004000);
+  __ Movi(v19.V2D(), 0x4000400040004000, 0x4000400040004000);
+
+  __ Sqrdmlsh(v16.V4H(), v0.V4H(), v1.V4H());
+  __ Sqrdmlsh(v17.V4S(), v2.V4S(), v3.V4S());
+  __ Sqrdmlsh(h18, h0, h1);
+  __ Sqrdmlsh(s19, s2, s3);
+
+  END();
+
+#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
+  RUN();
+  ASSERT_EQUAL_128(0, 0x40003fff40003ffb, q16);
+  ASSERT_EQUAL_128(0x40003fffc0004000, 0x40004000c0004000, q17);
+  ASSERT_EQUAL_128(0, 0x3ffb, q18);
+  ASSERT_EQUAL_128(0, 0xc0004000, q19);
+#endif
+  TEARDOWN();
+}
+
+TEST(neon_byelement_sqrdmlsh) {
+  SETUP();
+
+  START();
+
+  __ Movi(v0.V2D(), 0x0000000000000000, 0x0000040004008000);
+  __ Movi(v1.V2D(), 0x0000000000000000, 0x0000002000108000);
+  __ Movi(v2.V2D(), 0x0400000080000000, 0x0400000080000000);
+  __ Movi(v3.V2D(), 0x0000002080000000, 0x0000001080000000);
+
+  __ Movi(v16.V2D(), 0x4000400040004000, 0x4000400040004000);
+  __ Movi(v17.V2D(), 0x4000400040004000, 0x4000400040004000);
+  __ Movi(v18.V2D(), 0x4000400040004000, 0x4000400040004000);
+  __ Movi(v19.V2D(), 0x4000400040004000, 0x4000400040004000);
+
+  __ Sqrdmlsh(v16.V4H(), v0.V4H(), v1.H(), 1);
+  __ Sqrdmlsh(v17.V4S(), v2.V4S(), v3.S(), 1);
+  __ Sqrdmlsh(h18, h0, v1.H(), 0);
+  __ Sqrdmlsh(s19, s2, v3.S(), 0);
+
+  END();
+
+#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
+  RUN();
+  ASSERT_EQUAL_128(0, 0x4000400040004010, q16);
+  ASSERT_EQUAL_128(0x4000400040004010, 0x4000400040004010, q17);
+  ASSERT_EQUAL_128(0, 0xc000, q18);
+  ASSERT_EQUAL_128(0, 0xc0004000, q19);
+#endif
+  TEARDOWN();
+}
+
 
 TEST(neon_2regmisc_saddlp) {
   SETUP();
diff --git a/test/aarch64/test-disasm-aarch64.cc b/test/aarch64/test-disasm-aarch64.cc
index f18c4427..616e3555 100644
--- a/test/aarch64/test-disasm-aarch64.cc
+++ b/test/aarch64/test-disasm-aarch64.cc
@@ -4504,6 +4504,18 @@ TEST(neon_3same) {
   NEON_FORMAT_LIST_HS(DISASM_INST)
 #undef DISASM_INST
 
+#define DISASM_INST(M, S)                   \
+  COMPARE_MACRO(Sqrdmlah(v1.M, v2.M, v3.M), \
+                "sqrdmlah v1." S ", v2." S ", v3." S);
+  NEON_FORMAT_LIST_HS(DISASM_INST)
+#undef DISASM_INST
+
+#define DISASM_INST(M, S)                   \
+  COMPARE_MACRO(Sqrdmlsh(v1.M, v2.M, v3.M), \
+                "sqrdmlsh v1." S ", v2." S ", v3." S);
+  NEON_FORMAT_LIST_HS(DISASM_INST)
+#undef DISASM_INST
+
   COMPARE_MACRO(And(v6.V8B(), v7.V8B(), v8.V8B()), "and v6.8b, v7.8b, v8.8b");
   COMPARE_MACRO(And(v6.V16B(), v7.V16B(), v8.V16B()),
                 "and v6.16b, v7.16b, v8.16b");
@@ -4776,6 +4788,10 @@ TEST(neon_scalar_3same) {
   COMPARE_MACRO(Sqdmulh(v15.H(), v16.H(), v17.H()), "sqdmulh h15, h16, h17");
   COMPARE_MACRO(Sqrdmulh(v12.S(), v13.S(), v14.S()), "sqrdmulh s12, s13, s14");
   COMPARE_MACRO(Sqrdmulh(v15.H(), v16.H(), v17.H()), "sqrdmulh h15, h16, h17");
+  COMPARE_MACRO(Sqrdmlah(v12.S(), v13.S(), v14.S()), "sqrdmlah s12, s13, s14");
+  COMPARE_MACRO(Sqrdmlah(v15.H(), v16.H(), v17.H()), "sqrdmlah h15, h16, h17");
+  COMPARE_MACRO(Sqrdmlsh(v12.S(), v13.S(), v14.S()), "sqrdmlsh s12, s13, s14");
+  COMPARE_MACRO(Sqrdmlsh(v15.H(), v16.H(), v17.H()), "sqrdmlsh h15, h16, h17");
 
 #define DISASM_INST(M, R) \
   COMPARE_MACRO(Uqadd(v6.M, v7.M, v8.M), "uqadd " R "6, " R "7, " R "8");
@@ -4885,6 +4901,28 @@ TEST(neon_byelement) {
   COMPARE_MACRO(Sqrdmulh(h0, h1, v2.H(), 0), "sqrdmulh h0, h1, v2.h[0]");
   COMPARE_MACRO(Sqrdmulh(s0, s1, v2.S(), 0), "sqrdmulh s0, s1, v2.s[0]");
 
+  COMPARE_MACRO(Sqrdmlah(v0.V4H(), v1.V4H(), v2.H(), 0),
+                "sqrdmlah v0.4h, v1.4h, v2.h[0]");
+  COMPARE_MACRO(Sqrdmlah(v2.V8H(), v3.V8H(), v15.H(), 7),
+                "sqrdmlah v2.8h, v3.8h, v15.h[7]");
+  COMPARE_MACRO(Sqrdmlah(v0.V2S(), v1.V2S(), v2.S(), 0),
+                "sqrdmlah v0.2s, v1.2s, v2.s[0]");
+  COMPARE_MACRO(Sqrdmlah(v2.V4S(), v3.V4S(), v15.S(), 3),
+                "sqrdmlah v2.4s, v3.4s, v15.s[3]");
+  COMPARE_MACRO(Sqrdmlah(h0, h1, v2.H(), 0), "sqrdmlah h0, h1, v2.h[0]");
+  COMPARE_MACRO(Sqrdmlah(s0, s1, v2.S(), 0), "sqrdmlah s0, s1, v2.s[0]");
+
+  COMPARE_MACRO(Sqrdmlsh(v0.V4H(), v1.V4H(), v2.H(), 0),
+                "sqrdmlsh v0.4h, v1.4h, v2.h[0]");
+  COMPARE_MACRO(Sqrdmlsh(v2.V8H(), v3.V8H(), v15.H(), 7),
+                "sqrdmlsh v2.8h, v3.8h, v15.h[7]");
+  COMPARE_MACRO(Sqrdmlsh(v0.V2S(), v1.V2S(), v2.S(), 0),
+                "sqrdmlsh v0.2s, v1.2s, v2.s[0]");
+  COMPARE_MACRO(Sqrdmlsh(v2.V4S(), v3.V4S(), v15.S(), 3),
+                "sqrdmlsh v2.4s, v3.4s, v15.s[3]");
+  COMPARE_MACRO(Sqrdmlsh(h0, h1, v2.H(), 0), "sqrdmlsh h0, h1, v2.h[0]");
+  COMPARE_MACRO(Sqrdmlsh(s0, s1, v2.S(), 0), "sqrdmlsh s0, s1, v2.s[0]");
+
   COMPARE_MACRO(Smull(v0.V4S(), v1.V4H(), v2.H(), 0),
                 "smull v0.4s, v1.4h, v2.h[0]");
   COMPARE_MACRO(Smull2(v2.V4S(), v3.V8H(), v4.H(), 7),