diff options
-rw-r--r-- | src/aarch32/operands-aarch32.h | 2 | ||||
-rw-r--r-- | src/aarch64/assembler-aarch64.cc | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/aarch32/operands-aarch32.h b/src/aarch32/operands-aarch32.h index 2b452958..9a143d42 100644 --- a/src/aarch32/operands-aarch32.h +++ b/src/aarch32/operands-aarch32.h @@ -293,7 +293,7 @@ class NeonImmediate { bool IsInteger32() const { return immediate_type_.Is(I32); } bool IsInteger64() const { return immediate_type_.Is(I64); } - bool IsInteger() const { return IsInteger32() | IsInteger64(); } + bool IsInteger() const { return IsInteger32() || IsInteger64(); } bool IsFloat() const { return immediate_type_.Is(F32); } bool IsDouble() const { return immediate_type_.Is(F64); } bool IsFloatZero() const { diff --git a/src/aarch64/assembler-aarch64.cc b/src/aarch64/assembler-aarch64.cc index e98de89b..534e1d9b 100644 --- a/src/aarch64/assembler-aarch64.cc +++ b/src/aarch64/assembler-aarch64.cc @@ -2735,7 +2735,7 @@ void Assembler::fmov(const VRegister& vd, float imm) { Emit(FMOV_s_imm | Rd(vd) | ImmFP32(imm)); } else { VIXL_ASSERT(CPUHas(CPUFeatures::kNEON)); - VIXL_ASSERT(vd.Is2S() | vd.Is4S()); + VIXL_ASSERT(vd.Is2S() || vd.Is4S()); Instr op = NEONModifiedImmediate_MOVI; Instr q = vd.Is4S() ? NEON_Q : 0; uint32_t encoded_imm = FP32ToImm8(imm); @@ -2752,7 +2752,7 @@ void Assembler::fmov(const VRegister& vd, Float16 imm) { Emit(FMOV_h_imm | Rd(vd) | ImmFP16(imm)); } else { VIXL_ASSERT(CPUHas(CPUFeatures::kNEON, CPUFeatures::kNEONHalf)); - VIXL_ASSERT(vd.Is4H() | vd.Is8H()); + VIXL_ASSERT(vd.Is4H() || vd.Is8H()); Instr q = vd.Is8H() ? NEON_Q : 0; uint32_t encoded_imm = FP16ToImm8(imm); Emit(q | NEONModifiedImmediate_FMOV | ImmNEONabcdefgh(encoded_imm) | |