diff options
| -rw-r--r-- | src/aarch64/assembler-aarch64.cc | 1 | ||||
| -rw-r--r-- | src/aarch64/constants-aarch64.h | 1 | ||||
| -rw-r--r-- | src/aarch64/cpu-features-auditor-aarch64.cc | 3 | ||||
| -rw-r--r-- | src/aarch64/disasm-aarch64.cc | 4 | ||||
| -rw-r--r-- | src/aarch64/simulator-aarch64.cc | 1 | ||||
| -rw-r--r-- | src/cpu-features.h | 2 | ||||
| -rw-r--r-- | test/aarch64/test-assembler-aarch64.cc | 17 | ||||
| -rw-r--r-- | test/aarch64/test-disasm-aarch64.cc | 3 | ||||
| -rw-r--r-- | test/test-api.cc | 3 |
9 files changed, 34 insertions, 1 deletions
diff --git a/src/aarch64/assembler-aarch64.cc b/src/aarch64/assembler-aarch64.cc index 1c3ea65b..094bf86d 100644 --- a/src/aarch64/assembler-aarch64.cc +++ b/src/aarch64/assembler-aarch64.cc @@ -1883,6 +1883,7 @@ void Assembler::sys(int op, const Register& xt) { void Assembler::dc(DataCacheOp op, const Register& rt) { if (op == CVAP) VIXL_ASSERT(CPUHas(CPUFeatures::kDCPoP)); + if (op == CVADP) VIXL_ASSERT(CPUHas(CPUFeatures::kDCCVADP)); sys(op, rt); } diff --git a/src/aarch64/constants-aarch64.h b/src/aarch64/constants-aarch64.h index bbee5d82..f1361c36 100644 --- a/src/aarch64/constants-aarch64.h +++ b/src/aarch64/constants-aarch64.h @@ -421,6 +421,7 @@ enum DataCacheOp { CVAC = CacheOpEncoder<3, 7, 10, 1>::value, CVAU = CacheOpEncoder<3, 7, 11, 1>::value, CVAP = CacheOpEncoder<3, 7, 12, 1>::value, + CVADP = CacheOpEncoder<3, 7, 13, 1>::value, CIVAC = CacheOpEncoder<3, 7, 14, 1>::value, ZVA = CacheOpEncoder<3, 7, 4, 1>::value }; diff --git a/src/aarch64/cpu-features-auditor-aarch64.cc b/src/aarch64/cpu-features-auditor-aarch64.cc index b579507e..3fa4e54c 100644 --- a/src/aarch64/cpu-features-auditor-aarch64.cc +++ b/src/aarch64/cpu-features-auditor-aarch64.cc @@ -1098,6 +1098,9 @@ void CPUFeaturesAuditor::VisitSystem(const Instruction* instr) { case CVAP: scope.Record(CPUFeatures::kDCPoP); break; + case CVADP: + scope.Record(CPUFeatures::kDCCVADP); + break; case IVAU: case CVAC: case CVAU: diff --git a/src/aarch64/disasm-aarch64.cc b/src/aarch64/disasm-aarch64.cc index 28fec6bc..43654f38 100644 --- a/src/aarch64/disasm-aarch64.cc +++ b/src/aarch64/disasm-aarch64.cc @@ -2251,6 +2251,10 @@ void Disassembler::VisitSystem(const Instruction *instr) { mnemonic = "dc"; form = "cvap, 'Xt"; break; + case CVADP: + mnemonic = "dc"; + form = "cvadp, 'Xt"; + break; case CIVAC: mnemonic = "dc"; form = "civac, 'Xt"; diff --git a/src/aarch64/simulator-aarch64.cc b/src/aarch64/simulator-aarch64.cc index b682d07c..e7f9e9ce 100644 --- a/src/aarch64/simulator-aarch64.cc +++ b/src/aarch64/simulator-aarch64.cc @@ -3795,6 +3795,7 @@ void Simulator::SysOp_W(int op, int64_t val) { case CVAC: case CVAU: case CVAP: + case CVADP: case CIVAC: { // Perform a dummy memory access to ensure that we have read access // to the specified address. diff --git a/src/cpu-features.h b/src/cpu-features.h index fffef44f..25c49d7e 100644 --- a/src/cpu-features.h +++ b/src/cpu-features.h @@ -67,6 +67,8 @@ namespace vixl { V(kRAS, "RAS", NULL) \ /* Data cache clean to the point of persistence: DC CVAP. */ \ V(kDCPoP, "DCPoP", "dcpop") \ + /* Data cache clean to the point of deep persistence: DC CVADP. */ \ + V(kDCCVADP, "DCCVADP", NULL) \ /* Cryptographic support instructions. */ \ V(kSHA3, "SHA3", "sha3") \ V(kSHA512, "SHA512", "sha512") \ diff --git a/test/aarch64/test-assembler-aarch64.cc b/test/aarch64/test-assembler-aarch64.cc index 0a57ade6..5def1293 100644 --- a/test/aarch64/test-assembler-aarch64.cc +++ b/test/aarch64/test-assembler-aarch64.cc @@ -22885,6 +22885,23 @@ TEST(system_dcpop) { TEARDOWN(); } +TEST(system_dccvadp) { + SETUP_WITH_FEATURES(CPUFeatures::kDCCVADP); + const char* msg = "DCCVADP test!"; + uintptr_t msg_addr = reinterpret_cast<uintptr_t>(msg); + + START(); + __ Mov(x20, msg_addr); + __ Dc(CVADP, x20); + END(); + +#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64 + RUN(); + ASSERT_EQUAL_64(msg_addr, x20); +#endif + + TEARDOWN(); +} TEST(neon_2regmisc_xtn) { SETUP_WITH_FEATURES(CPUFeatures::kNEON); diff --git a/test/aarch64/test-disasm-aarch64.cc b/test/aarch64/test-disasm-aarch64.cc index 65909bf3..cdddf860 100644 --- a/test/aarch64/test-disasm-aarch64.cc +++ b/test/aarch64/test-disasm-aarch64.cc @@ -3274,6 +3274,8 @@ TEST(system_sys) { COMPARE(sys(0x3, 0x7, 0xa, 0x1, x2), "dc cvac, x2"); COMPARE(sys(0x3, 0x7, 0xb, 0x1, x3), "dc cvau, x3"); COMPARE(sys(0x3, 0x7, 0xe, 0x1, x4), "dc civac, x4"); + COMPARE(sys(0x3, 0x7, 0xc, 0x1, x5), "dc cvap, x5"); + COMPARE(sys(0x3, 0x7, 0xd, 0x1, x6), "dc cvadp, x6"); COMPARE(sys(0x3, 0x7, 0x4, 0x1, x0), "dc zva, x0"); COMPARE(sys(0x0, 0x0, 0x0, 0x0, x0), "sys #0, C0, C0, #0, x0"); COMPARE(sys(0x1, 0x2, 0x5, 0x2, x5), "sys #1, C2, C5, #2, x5"); @@ -3303,6 +3305,7 @@ TEST(system_dc) { COMPARE(dc(CVAU, x3), "dc cvau, x3"); COMPARE(dc(CVAP, x4), "dc cvap, x4"); COMPARE(dc(CIVAC, x5), "dc civac, x5"); + COMPARE(dc(CVADP, x6), "dc cvadp, x6"); COMPARE(dc(ZVA, x0), "dc zva, x0"); COMPARE(dc(ZVA, xzr), "dc zva, xzr"); diff --git a/test/test-api.cc b/test/test-api.cc index d3a62019..219d4dfb 100644 --- a/test/test-api.cc +++ b/test/test-api.cc @@ -386,7 +386,8 @@ TEST(CPUFeatures_format) { // Armv8.1 "Atomics, LORegions, RDM, " // Armv8.2 - "SVE, DotProduct, FPHalf, NEONHalf, RAS, DCPoP, SHA3, SHA512, SM3, SM4, " + "SVE, DotProduct, FPHalf, NEONHalf, RAS, DCPoP, DCCVADP, SHA3, SHA512, " + "SM3, SM4, " // Armv8.3 "PAuth, PAuthQARMA, PAuthGeneric, PAuthGenericQARMA, JSCVT, Fcma, RCpc, " // Armv8.4 |