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Bug: http://b/217563632
Bug: http://b/215753485
This was found by upcoming clang-r445002 update.
external/vixl/src/aarch64/assembler-aarch64.cc:2738:17: error: use of
bitwise '|' with boolean operands [-Werror,-Wbitwise-instead-of-logical]
VIXL_ASSERT(vd.Is2S() | vd.Is4S());
external/vixl/src/aarch64/assembler-aarch64.cc:2755:17: error: use of
bitwise '|' with boolean operands [-Werror,-Wbitwise-instead-of-logical]
VIXL_ASSERT(vd.Is4H() | vd.Is8H());
external/vixl/src/aarch32/operands-aarch32.h:296:35: warning: use of
bitwise '|' with boolean operands [-Wbitwise-instead-of-logical]
bool IsInteger() const { return IsInteger32() | IsInteger64(); }
Test: Build with new clang
Change-Id: I5b77e90881a0cc7ff0266c69f035abc2d3266a7e
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The simulation of while was computing differences using 64-bit variables, which
didn't handle the overflow cases correctly for W-sized registers. Fix and add a
regression test.
Note: this is a cherry-pick patch from VIXL usptream;
it affects VIXL simulator only, no impact for the ART
release build.
Author: Martyn Capewell.
Commiter: Artem Serov.
Change-Id: I681f6ecb137d52830a58816fa34545342e6eb6bf
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This merge corresponds to VIXL 5.1.0. It provides a way to
configure VIXL simulator stack size; without it the stack
overflowed in some ART gtests. Also improves the use of
inclusive language.
acdea50a Remove "dummy" from test and tools
d42989cf Remove use of "dummy"
c4ef66e9 Make the stack size configurable.
f73036ba Fix FPRoundInt's handling of INT64_MAX.
a26a26cb Don't simulate invalid logical immediate instructions
6f755e6a Fix undefined behaviour in Halve
d02f4372 Simplify the command-line disassembly example UI.
e522c6e6 Add a command-line disassembly example.
46ce31f6 Add email address for bug reporting
63ceff5b Define values for unallocated prefetch modes
4c550938 Fix lint.py error regex.
Test: mma test-art-host-vixl
Test: test.py --host --optimizing --jit --gtest
Test: test.py --target --optimizing --jit
Test: run-gtests.sh
Change-Id: I7312fb29ed5445e52790b0d5bad20cc4d5348aa0
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This reverts commit 0a75ba66aa15ea1cdb3f57d0efd4ce7e7c14d45f.
Test: mma test-art-host-vixl
Test: test.py --host --optimizing --jit --gtest
Test: test.py --target --optimizing --jit
Test: run-gtests.sh
Change-Id: I052ab4d3243b0b9bee4c52d00ba4ef1d93a8d32c
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Replace "dummy" with "placeholder".
Change-Id: I9af7f56c93b49c1a6428414601af1dec475ca3b8
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Also fix the implementation of stack guards, and make these configurable
too.
Change-Id: Ic62ee326ed725616322ca8fa26d38b9a089d5043
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This fixes a bug caused by an implicit conversion from `int64_t` to
`double`, as well as several related warnings (from recent versions of
Clang) in the "frint" tests.
Change-Id: Ie5dccbf7a86c5e3a608570bd0ffc566bf3813380
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Logical immediate instructions using an immediate encoding that should be
reserved were being simulated. Prevent this by asserting the immediate is
valid.
Change-Id: Ic0388f3f941914d9fae92e0961c2ebf10c3a5d0b
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Revert "ART: Fix breaking changes from recent VIXL update."
Revert submission 1331125-VIXL_UPDATE_SVE
Reason for revert: broken build git_master-art-host/art-gtest-heap-poisoning @ 6936943
Reverted Changes:
Ic10af84a0:Merge remote-tracking branch 'aosp/upstream-master...
I752a0b0ba:ART: Fix breaking changes from recent VIXL update....
Bug: 171879890
Change-Id: I6f0f5d1e176e2069301685eeb95a3c76364226ff
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The Halve function relied on shifting a signed value right. Replace with a
well-defined bitfield extraction.
Change-Id: I980d64ee92b68b5d4e213a2f338d810ec3999df7
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Change-Id: I8461bc4c7b50d487334f3a022b614047f132ad61
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The assembler API provides prefetch functions that accept an enumeration for
the prefetch mode, but that relies on C++ undefined behaviour when used with
integer mode specifiers absent from the enumeration. This patch adds those
unallocated values.
Change-Id: I03fce9158deed2dda43ed35e5c6cbc93a4c3f9af
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Enables support of ARM Scalabe Vector Extension.
e66b0909 Optimise single handler tables in the decoder.
8ed83527 [sve] Disallow dup with shift on byte-sized lanes
32a7cd97 Fix infinite loops in some native tests.
b8da04db Remove undefined behaviour in add/sub immediate
f84b4643 Revert optimisation for add/sub immediates
aaf02c54 Fix initialisation order for ID register fields.
f3f5d246 Fix add/sub immediate for min-int case
f48172ba Add missing aliases for SVE 0.0 moves.
b9616b36 Fix and enable CanTakeSVEMovprfx.
8c4ceb6a Support more than 64 CPU features.
caa40eec Fix CPUFeature iterator behaviour.
28ff5975 Add an example that dumps CPU feature information.
31d432b2 Add support for AT_HWCAP2.
3d8d3942 Add CPUFeatures up to Armv8.6.
960606b6 Emit pairs of add/sub for larger immediates
4635261c Use segments in SVE indexed fmul simulation
3eb24e95 Fix numerous issues related to CAS* instructions.
102e7a5e Make assembler more strict about SVE prefetch arguments
ebc3b8f5 Use PgLow8 rather than Pg<12, 10>.
7b5819c3 Always assert that 'pg' does not have a lane size.
ecca4b1c Disallow x31/xzr for SVE prefetch scalar offset register
4606adc3 Fix simulation of FCMNE.
5a5e71f3 Require an immediate (0.0) for compare-with-zero instructions.
a8461cf9 Prefer to use 'rd' as a scratch.
32f8fe13 Fix CPURegister::GetArchitecturalName().
dfb93b5e Fix simulation of FTSMUL.
8caa873b Fix the `sve_fmla_fmls` test.
a3d6110c Fix simulation of BRKNS.
3980b742 Make the 'sve_punpk' test VL-agnostic.
7c8c1f0f Update FPCR test.
df01bce3 Merge branch 'sve'
75892bd1 [sve] Restore LaneSize to predicate logical operations.
9927c4f6 [sve] Improve disasm substitution for sign-extending loads
f67b1af0 [sve] Remove generated comments from the disassembler
5e2df59a [sve] Remove extra spaces from load/store register lists.
29936957 [sve] Remove redundant 'USE' macros.
89820250 [sve] Ternary substitution for disassembler
1f1ab9b9 Merge branch 'master' into sve
15d78439 [sve] Make modifiers lower case in disassembly
5f3928c0 [sve] Implement 32-bit scatter store (scalar plus vector mode).
fa098bcf [sve] Implement 64-bit scatter store (scalar plus vector mode).
a5112344 [sve] Complete remaining gather loads.
cd3f6c5e [sve] Fix the index specifier decoding error in the gather load helper.
cb0cfc31 Remove some unnecessary casts in `LoadStoreMemOperand`.
50ef1718 [sve] Relax the lane size restriction of register in MacroAssembler.
7b9a5f12 Use Register for macro assembler ldpsw
4fc4bec4 [sve] Add a strlen example using ldff1b.
6ebcc8a2 Ensure stable build directory name under Python 3
5f9b3800 [sve] Implement ContiguousNonFaultLoad
d154a44f Don't template 'Rx' on the register type.
0d754e91 [sve] Trace writes to FFR.
7d3a329d [sve] Remove a bad assertion.
1c45cfeb [sve] Rename IsScalar to IsPlainScalar.
7db8210d [sve] Implement fmov aliases.
ae3902af [sve] Implement logical immediate aliases.
83ebf7cb Remove redundant tests.
e2de6070 [sve] Implement aliases for mov immediate
9ccc4d23 [sve] Implement aliases for mov from register
a24d95ca [sve] Implement predicate logical instruction aliases
b56cf22f [sve] Implement scatter str, vector plus immediate form
a3c11462 Remove stray assembler method declarations
fd0fc206 Merge branch 'master' into sve
2b66cd62 Fix the 'sh' field for ADD/SUB immediate.
fe7cb100 Compatibility fixes for scons using Python 3
1af34f12 [sve] Implement gather load first-fault data to 64-bit vector (vector index).
6537a9a7 [sve] Implement gather load first-fault data to 32-bit vector (vector index).
823509b1 Merge branch 'master' into sve
504d5e9e Fix clang-format errors.
3db2c498 [sve] Implement prefetch instructions.
8667956f Remove undefined casts to PrefetchOperation.
113d9199 [sve] Implement gather load data to 32-bit vector (vector index).
1a5dcd21 Merge "Merge branch 'master' into sve" into sve
d9859c0e Merge branch 'master' into sve
85e1510e [sve] Implement load and broadcast data to vector.
b944bff2 [sve] Assert destination register is X for count-like instructions
991ee198 [simulator] Remove instruction instrumentation support.
2fe55ec6 Update clang tools to 4.0.
fa3f6bf6 [sve] Implement indexed sdot and udot.
3e2fb505 [sve] Implement ContiguousNonTemporalStore
72765d1b [sve] Implement ContiguousNonTemporalLoad
452ad8b9 [sve] Implement LoadAndBroadcastQuadword
b2a19fae Remove bitfields from the CPURegister API.
8d4bbd20 Merge branch 'master' into sve
d1463742 Document that the DecoderVisitor interface is unstable.
5b0e0044 Merge branch 'master' into sve
c750151e [sve] Fix indexed floating point multiply simulation
48522f53 [sve] Implement AddressGeneration
e4886e50 [sve] Implement FPComplexMulAddIndex
75f1c436 [sve] Implement FPComplexMulAdd
818379d9 Document security considerations.
b4a25f6e [sve] Implement fsqrt.
f60f6dc8 [sve] Implement frecpx.
2cb1b611 [sve] Implement fcvt.
0b1afa89 [sve] Implement FPComplexAddition
f804b606 [sve] Implement PermuteVectorPredicated
fd660b58 [sve] Add token to disassembler for predicate register
83e86612 [sve] Implement predicated shifts by immediate
76c094af [sve] Implement BitwiseShiftByVector and WideElements.
147b0ba7 [sve] Fix immediate shifts for LSL
3bf2d166 [sve] Fix premature truncation of shift amount
acd32aad Consistently use snake_case for variable names.
70d62899 Show output of --list when it fails.
e377513a [sve] Implement SVEFPCompareWithZero instructions.
47c2684c [sve] Implement SVEFPCompareVectors instructions.
f07b8cee [sve] Implement SVEFPUnaryOpPredicated instructions (FRINT).
a2c1bb70 [sve] Implement SVEFPMulAddIndex instructions.
f8d29f13 [sve] Implement SVEFPMulAdd instructions.
364a068f Test fewer targets.
5f9905bf [sve] Support unary instructions in MovprfxHelperScope.
efd9dc76 [sve] Implement remaining FPArithmeticUnpredicated instructions
13050cae [sve] Implement FPUnaryOpUnpredicated
894962f4 [sve] Implement FPFastReduction
afd9335e [sve] Fix insr disassembly
a2fadc26 [sve] Implement predicated FP arithmetic immediate instructions
37f28184 [sve] Implement remaining predicated FP arithmetic instructions
ac07af1f [sve] Implement SVEPermuteVectorExtract
dcdbd757 [sve] Implement vector-plus-immediate loads.
85a9c104 [sve] Add support for ldff1*.
36e6c56f Remove the dependency on 'sed'.
4a9829fb [sve] Implement FADDA
191e757e Move to a C++14 baseline.
5fb2ad66 [sve] Implement FTMAD
2e954295 [sve] Fix unpack instructions when src aliases dst
afe21a8b [sve] Add SVE tests to cpufeatures tests.
31cd6a0f [sve] Implement part of SVEFPUnaryOpPredicated instructions.
db7437cc [sve] Implement part of SVEFPUnaryOpPredicated instructions.
50e9f552 [sve] Implement floating point multiply by index
15f8901d [sve] Implement SVEPermuteVectorInterleaving
662db65f [sve] Fix cpplint complaint about non-const reference
5d87229d [sve] Implement SVEPartitionBreak instructions.
7fd6fd53 [sve] Implement SVEPermutePredicate instructions
03bfc30d [sve] Improve predicate register substitution.
e0eb40b5 Merge branch 'master' into sve
843495bd Merge branch 'master' into sve
ee1108d4 Define AA64PRF0::kRAS.
67c969d4 Fix access to AA64MMFR2 on Arm8.0 targets.
0442b3db [sve] Restructure form selection for structured accesses.
7eb3e219 [sve] Update simulator tracing for SVE.
423e5428 [sve] Make pre-SVE register tracing consistent.
4378263d [sve] Implement SVEIntMiscUnpredicated
77b6d986 [sve] Implement SVEReverseWithinElements
38303d9a [sve] Implement SVEPropagateBreak instructions.
728e5653 Merge branch 'master' into sve
a3e8b176 [sve] implement the predicated rdffr and rdffrs.
4023d7aa [sve] Implement setffr, wrffr and rdffr(unpredicated).
d47d6c41 [sve] Fix decoding bitwise shift (wide) instructions in disassembler.
d0dbe586 Fix DEFINE_ASM_FUNC for namespacing.
ac79f620 Remove non-zero register asserts from Csinc/Csinv/Csneg
8188ddfd [sve] Implement saturating inc/dec vector by element count instructions
91d5ba34 [sve] Implement saturating inc/dec register by element count
e5ab0fe5 [sve] Implement ld2, ld3 and ld4 (immediate).
e483ce56 [sve] Implement ld2, ld3 and ld4 (scalar).
d4dd9c2a [sve] Implement st2, st3 and st4 (immediate).
bc4a54f0 [sve] Implement st2, st3 and st4 (scalar).
29a0c43e [sve] Implement SVEBitwiseShiftUnpredicated instructions.
7a0d3678 [sve] Implement predicated fmax and fmin.
7e8d7838 [sve] Fix decoding tsz in disassembler
17b2e540 Add missing ID register feature detection.
579c92d0 [sve] Implement inc/dec register by element count instructions
74f84f6c [sve] Implement count elements instructions
aae2cf01 [sve] Remove some duplicate cases in the disassembler
f3fae203 [sve] Tidy up register disassembly
378fc895 [sve] Clean up SVESdotUdotHelper.
6ebbba62 [sve] Fix the behaviour of SVE_MUL_VL.
889984cb [sve] Add missing DISASM tests for 'adr'.
0f62eab5 Implement CPY and FCPY (immediate).
9cc3f148 [sve] Predicated select for z registers
d316c5e2 [sve] Implement predicated fdiv and fdivr.
fe536047 [sve] Implement unpredicated fadd, fsub and fmul.
d255bdb3 New decoder with smaller instruction classes.
4d2a4e97 [sve] Implement SVEIntMulAddUnpredicated instructions.
b2d8d1fd [sve] Implement the SVEIntReduction group.
06feb1d6 Merge branch 'master' into sve
33c99f91 Give EqualMemory a zero_offset.
e4983d43 [sve] Fix the insr test.
b40aa695 [sve] Fix and extend the cterm test.
bcc97931 [sve] Fix the encoding of sdiv/udiv.
0093bb9f [sve] Implement CPY_z_r and CPY_z_v.
6b245ba8 [sve] Fix disassembly of DUP_z_r.
b28f6178 [sve] Fix handling of overflow in {sq,uq}{add,sub}.
d9f929c5 [sve] Convert 'Add(..., -1)' to 'Sub(..., 1)'.
6f111bc8 [sve] Implement andv, eorv and orv.
61a271ea Merge branch 'master' into sve
c0066278 [sve] Add an unpredicated 'Neg' macro.
6995bfd2 [sve] Implement the SVEIntWideImmUnpredicated group.
6205eb45 [sve] Implement contiguous ld1 loads.
bc21a0d1 [sve] Implement the IntUnaryArithmetic group.
e668b200 [sve] Implement contiguous st1 stores.
199339db [sve] Implement simple Z and P loads and stores.
4f28df7f [sve] Implement permute vector unpredicated instructions group.
1314c46c [sve] Implement 'Adr(Register, SVEMemOperand)'.
9e5da2af [sve] Implement the SVEStackAllocation group.
66e6671d Add SVEMemOperand.
845246bf [sve] Add support for the SVEIntArithmeticUnpredicated group.
13634762 [sve] Add support for the SVEIntBinaryArithmeticPredicated group.
d4e0b1be Merge branch 'master' into sve
f5659ff6 Enable P register logging.
e8289200 Test various vector lengths.
d961a0c3 [sve] Implement `cntp`.
0ce75844 [sve] Implement most 'SVEPredicateMisc' instructions.
4d6c680d Use macro lists for repetive visitors.
d9002964 Merge branch 'master' into sve
302729ce [sve] Add support for the SVEIntCompare{Signed|Unsigned}Imm group.
c844bb27 [sve] Add support for the SVEIntCompareScalars group.
935b15be Fix ClearForWrite with Z registers.
cd8148c2 [sve] Add support for `index`.
d1686cbb [sve] Add support for INCP and DECP.
6069fd45 Introduce IntegerOperand.
96713fe6 [sve] Add support for the SVEIntCompareVectors group.
fad4dffa Enable Z register tracing.
4b6167bd Merge branch 'master' into sve
9d0f264b Make CPURegister::X() return a Register.
a1885a51 Implement unpredicated bitwise operations with immediate.
e87e11e1 Merge branch 'master' into sve
afd17aa5 [sve] Add SVE condition aliases.
f4fa8226 [sve] Implement SVEPredicateLogical instruction group.
ae2fc3bf [sve] Add support for movprfx.
9ec0cbee [sve] Add 128-bit vector element type.
cfb94218 [sve] Implement bitwise logical unpredicated instructions.
72d2e56a [sve] Basic SVE Z register tracing.
61a75f97 [sve] Make PRegister* types derive from PRegister.
fbdd3b77 [sve] Merge ZRegisterNoLaneSize into ZRegister.
22023dfa [sve] Add support for the IntMulAddPredicated group.
f9658283 Merge branch 'master' into sve
2a249921 [sve] Fix a comment in the test infrastructure.
9d06c4d6 [sve] Enable simulation of the test framework.
e546c4a5 [sve] Enable simulation of RegisterDump::Dump().
81878560 [sve] Implement AcquireGoverningP().
2eaecf15 [sve] P register test utilities.
ee9123c8 [sve] Add P register support to UseScratchRegisterList.
9a570dd7 [sve] Add tests for some UseScratchRegisterScope tools.
0e90ead1 [sve] Rework CPURegister and related classes.
22430a4d Merge branch 'master' into sve
03c0b515 [sve] Z register tools for assembler tests.
dc47bded [sve] Support ZRegister in UseScratchRegisterScope.
119bd21a Merge branch 'master' into sve
99aa1859 Merge branch 'master' into sve
f20f247d [sve] Add predicate condition testing functions in the simulator.
cf730b6c [sve] Get rid of DEBUG-only NORETURN visitors.
e0590ccf [sve] Add P register infrastructure for simulation.
bbb13c6b Merge branch 'master' into sve
e3d059b7 [sve] Add Z register infrastructure for simulation.
d77a8e42 [sve] Add Z and P register support to RegisterDump.
44777d49 [sve] Remove MacroAssembler::Dupm.
bdd38cb1 [sve] Add macro assembler skeleton
b4f387ab Add disassembler test skeleton
63db3c15 Fix types of asm governing predicates
d7b90956 Update .gitreview for the 'sve' branch.
25197201 Split assembler tests
00aa898a [sve] Implement basic register support.
e91d1ec0 Add SVE simulator skeleton
4fbccad0 Merge branch 'master' into sve
c7406fab Split disassembler tests
a9abe595 Add SVE disassembler skeleton.
6847c2fc Add SVE assembler skeleton and dummy [ZP]Register classes
aaba1a48 SVE instruction constants
b545d6ca Implement SVE decoder and skeleton components
Test: mma test-art-host-vixl
Test: test.py --host --optimizing --jit --gtest
Test: test.py --target --optimizing --jit
Test: run-gtests.sh
Change-Id: Ic10af84a026fe83d788f587b6d1fc2240be915fb
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Previously, the decoder applied a mask-and-value optimisation only if a decoding
table had two entries in it, with an explicit "otherwise" case. This patch makes
the optimisation also work when the case is implicit.
Change-Id: Iacbf96940e1c078fdcb4ad162f483b0d690b4108
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The Arm ARM states dup-immediate with shift on byte-sized lanes is an undefined
encoding, so add assertions in the assembler to disallow this, and handle
the encoding appropriately in the disassembler and simulator.
Change-Id: Ibce08d2577e2b780dbb7e4fa478d2f8d18e99a39
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The macro assembler support for add/sub immediate could attempt to negate the
minimum int64_t value, which is undefined behaviour. Check the value before
negation.
Change-Id: If5c12515fbef490318a90930e7a362876b0e6dc5
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Removed due to some cases showing worse performance.
Reverts:
960606b686f59d468f97dfa93b5dba5b2b38cc8f
f3f5d246129febc518cfa99003ee66c5008202c5
Change-Id: I5b9585d112424d97e372bd264d084cb9caf92b5f
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Making the constructor `constexpr` gives these "constant" rather than
"dynamic" initialisation, which guarantees that they'll be initialised
before any other dynamically-initialised static variables.
This makes it safe to make static variable initialisers dependent on the
result of `CPUFeatures::InferFromOS()` and similar functions.
Change-Id: Ib65e92273c7ac03d07e17cbe844b598ef3bc60ac
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960606b removed a check for the encodability of a value within an add/sub
instruction, which allowed negation of min-int to pass through undetected.
This caused incorrect code generation, as the value wasn't inverted, but the
operation was.
Change-Id: I9c436a42a67aabca4873972c173ea104ef36f40e
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Change-Id: I608c610da7de42328ed3984dabb56cf1401d7a15
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Change-Id: I9afc03fb9e11546b9e6caf04497339bf45b285b6
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After recent patches, we have exactly 64 CPU features. This patch makes
the mechanism flexible so that we can support more features in the
future.
Several operators on CPUFeatures had to be re-written as part of this,
so this patch replaces the default-argument implementations with a more
flexible template-based approach, which can accept more than four
features. Existing usage remains unaffected.
Change-Id: If91a3adb62669aa827464e857a90eb93a64db7a6
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The `++` operators should return iterators, not values.
This also updates tests to match, and makes wider use of C++11
range-based `for` loops, where they simplify code.
Change-Id: I2c8ef422e851d6b16c8de2890ae16fc69817a738
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Change-Id: I3c893a6c1e3b25756999025a21ae310e5b3e199c
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This adds support for all relevant features described in the latest
Armv8.6 XML.
Note that this removes the CPUFeatures::All() part of the
`API_CPUFeatures_format` test. It added little value to the test, and
was a burden to update when new features are added.
Change-Id: I276a0970be94c3adf2d0100874df0b82c7424a9b
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For immediates between 12 and 24 bits in size, a pair of add or sub instructions
can be used instead of mov, avoiding the need to allocate a temporary.
Change-Id: I114b4667dcc1bda094652e01d88069d012249dca
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The value used for the second operand in indexed multiplies differs for each
segment (128-bit part) of a vector, but the simulator wasn't doing this for
FP multiplies. Fix and update the tests.
Change-Id: I9cc37ebef9d216243a23bedebea256826e1016cb
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1. There was no test for 64-bit CASP.
2. The tests had some faulty code for obtaining aligned pointers. The
natural alignment is sufficient anyway, so this patch removes the
broken alignment code, and varies the addresses used to strengthen
the test slightly.
For the new CASP test, this patch uses the C++11 `alignas` specifier.
3. The simulation of CASP variants accessed memory in the wrong order.
With this patch, the first-specified register in each pair accesses
the lowest address.
4. We now check that `rs` and `rt` have the same format. Likewise for
`rs2` and `rt2` in the CASP variants.
5. Register trace is improved: the `rs` (and `rs2`) update is traced as
a memory read so we should suppress the log on the register write.
This is what we do for normal loads.
Change-Id: I213c4b3de32305a8072fdc45357b67cbbf85ba9c
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Add assertions to the assembler to prevent the use of unsupported addressing
modes for prfb/h/w/d.
Change-Id: Ie12991eb2e29661eb266fc495e9164246371d10e
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This is just a clean-up. We have the helper, so we should use it.
Change-Id: I8ee2c7929aef6ad737d7079eee62ffe3f7618857
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We did this for PgLow8, but not for 4-bit 'pg' fields.
In practice, we plan to relax this in the future, permitting lane sizes
where they match the rest of the instruction, but this patch makes our
checks consistent in the meantime.
Change-Id: Ie791027f217eabab305dbd22b8c0e77926c9d3b8
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The architecture disallows rm = x31/xzr for prefetch, so assert this in the
assembler.
Change-Id: I26e14688bde624d38eee40167fb3ada88acaaec7
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FCMNE can return true when the comparison is unordered.
Change-Id: Ic1fa9a83cd9bde23faf2b13b69d3a7e9d1426a12
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This matches conventions elsewhere in the API, and allows for immediate
synthesis. Immediate synthesis is not included in this patch.
Change-Id: If4bdc9cfd9d4bb83a9c015ef363291c1ff08a64a
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This is generally useful, but in particular reduces scratch register
pressure in code sequences using ComputeAddress. For example:
MemOperand addr(...);
UseScratchRegisterScope temps(&masm);
Register computed = temps.AcquireX();
__ ComputeAddress(computed, addr);
Before this patch, that sequence usually required two scratch registers;
one for `computed`, and one for immediate synthesis inside
`ComputeAddress`. With this patch, the same code sequence only needs one
scratch register.
Change-Id: I9c93e6cab51bdacf36046d4d770dc81d1a65a34c
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The `code_` field is a `uint8_t`, which is treated by stream formatters
as a `char`. This caused strange output from error messages in test
failure.
Change-Id: I16302e6bbd8977bb376d28c7b7cb2091f9891aba
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We tried to set the sign bit before multiplying, but this produced the
wrong result when the input is already negative.
Change-Id: I7b44070409ca265b1fae34792ebe43e5e53ce646
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In this instruction, `pg` should be ignored when setting flags.
Also, simplify the test.
Change-Id: I9b8a73bdd0aaaebbecbccd1c446e17cd9d38ce8f
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In predicated operations, a lane size is required to use the governing predicate
correctly, and to reject instructions that don't support the lane size.
Consequently, this patch restores the lane size requirement on predicated
logical operations with predicate operands.
Change-Id: Ida32cc412a88c09454533dd8a5f12f46632d9750
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Change 'tlss substitution to consider element size and memory size, which
simplifies the code in the visitors.
Change-Id: I0f34f206c6c68d0ddc6b4b115b982268f4dd89be
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After implementation, these comments are not so useful, so remove the remaining
ones for consistency.
Change-Id: If47c5dffe13d27b92e8199b77dfbb2d5662e7327
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This makes our SVE disassembly consistent with our NEON disassembly.
Change-Id: Iede57b6396e36913c879130101cdd487dbf63b8f
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Change-Id: I3398f3fc3c737f3f4a4a15dce453dcfea0f5a670
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Introduce a ternary substitution placeholder in the disassembler, making some
addressing modes and merging/zeroing forms simpler.
Change-Id: I75d0c3cf40c73dd2e1ebce30c3753fd79368326d
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Change-Id: If2ce450e490dd1ad4fcaba78985af84cc847986f
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Make addressing mode modifiers MUL VL and LSL lower case to match the others.
Change-Id: I3388710128ac1dd4c3df503d4a5779e3ddf2936c
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Include st1b, st1h, st1w and st1d.
Change-Id: I868c47a984723ea94ddc78f65f8c68680209c19c
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Include st1b, st1h, st1w and st1d.
Change-Id: If7a5cd01ab8cc9dae813da81fc3cd9e34d9bc7b4
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Implement remaining 64-bit gather loads including unpacking, unscaled and
scaled offset form.
Change-Id: I208de1fabfe40f7095f9848c3ebf9de82a5f7416
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In the simulation of the scalar-plus-vector form of gather loads,
the helper hasn't considered shift specifiers in the decoding, so
64-bit unscaled/scaled offset forms haven't been generated and tested.
Change-Id: If4539de5a1b4e6760780fdbaefd56dc84dd47413
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