From 84ee144ecd16f0ee52c24a6273430f37c92322ad Mon Sep 17 00:00:00 2001
From: Alexander Gilday <alexander.gilday@arm.com>
Date: Tue, 6 Nov 2018 15:28:07 +0000
Subject: Add support for AXFLAG and XAFLAG instructions.

Change-Id: I95867fa8adb6eeefe49dc5e0f56ed51b4d060a1d
---
 test/aarch64/test-assembler-aarch64.cc | 64 ++++++++++++++++++++++++++++++++++
 test/aarch64/test-disasm-aarch64.cc    |  2 ++
 2 files changed, 66 insertions(+)

(limited to 'test/aarch64')

diff --git a/test/aarch64/test-assembler-aarch64.cc b/test/aarch64/test-assembler-aarch64.cc
index 38fee97e..8f0a87fb 100644
--- a/test/aarch64/test-assembler-aarch64.cc
+++ b/test/aarch64/test-assembler-aarch64.cc
@@ -15058,6 +15058,70 @@ TEST(cfinv) {
 }
 
 
+TEST(axflag_xaflag) {
+  // The AXFLAG and XAFLAG instructions are designed for converting the FP
+  // conditional flags from Arm format to an alternate format efficiently.
+  // There are only 4 cases which are relevant for this conversion but we test
+  // the behaviour for all 16 cases anyway. The 4 important cases are labelled
+  // below.
+  StatusFlags expected_x[16] = {NoFlag,
+                                ZFlag,
+                                CFlag,  // Greater than
+                                ZFlag,  // Unordered
+                                ZFlag,
+                                ZFlag,
+                                ZCFlag,  // Equal to
+                                ZFlag,
+                                NoFlag,  // Less than
+                                ZFlag,
+                                CFlag,
+                                ZFlag,
+                                ZFlag,
+                                ZFlag,
+                                ZCFlag,
+                                ZFlag};
+  StatusFlags expected_a[16] = {NFlag,  // Less than
+                                NFlag,
+                                CFlag,  // Greater than
+                                CFlag,
+                                CVFlag,  // Unordered
+                                CVFlag,
+                                ZCFlag,  // Equal to
+                                ZCFlag,
+                                NFlag,
+                                NFlag,
+                                CFlag,
+                                CFlag,
+                                CVFlag,
+                                CVFlag,
+                                ZCFlag,
+                                ZCFlag};
+
+  for (unsigned i = 0; i < 16; i++) {
+    SETUP_WITH_FEATURES(CPUFeatures::kAXFlag);
+
+    START();
+    __ Mov(x0, i << Flags_offset);
+    __ Msr(NZCV, x0);
+    __ Axflag();
+    __ Mrs(x1, NZCV);
+    __ Msr(NZCV, x0);
+    __ Xaflag();
+    __ Mrs(x2, NZCV);
+    END();
+
+#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
+    RUN();
+    ASSERT_EQUAL_32(expected_x[i], w1);
+    ASSERT_EQUAL_32(expected_a[i], w2);
+#else
+    USE(expected_x, expected_a);
+#endif  // VIXL_INCLUDE_SIMULATOR_AARCH64
+    TEARDOWN();
+  }
+}
+
+
 TEST(system_msr) {
   // All FPCR fields that must be implemented: AHP, DN, FZ, RMode
   const uint64_t fpcr_core = 0x07c00000;
diff --git a/test/aarch64/test-disasm-aarch64.cc b/test/aarch64/test-disasm-aarch64.cc
index 0d7642fd..5fb98d2c 100644
--- a/test/aarch64/test-disasm-aarch64.cc
+++ b/test/aarch64/test-disasm-aarch64.cc
@@ -3212,6 +3212,8 @@ TEST(system_pstate) {
   SETUP();
 
   COMPARE(cfinv(), "cfinv");
+  COMPARE(axflag(), "axflag");
+  COMPARE(xaflag(), "xaflag");
 
   CLEANUP();
 }
-- 
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