[Zucchini] Cleanup before adding ARM support for ELF files.

This CL performs some code cleanup to prepare for main CL that adds
ARM support for ELF files (https://crrev.com/c/2922822):
* Rename ARM32 / Arm32 to AArch32.
* Replace DISALLOW_COPY_AND_ASSIGN for affected files.

Bug: 918867
Change-Id: I0e96b66fb29e9d1a35f9d7fac65755fbeda4831f
Reviewed-on: https://chromium-review.googlesource.com/c/chromium/src/+/3044420
Commit-Queue: Samuel Huang <huangs@chromium.org>
Commit-Queue: Etienne Pierre-Doray <etiennep@chromium.org>
Reviewed-by: Etienne Pierre-Doray <etiennep@chromium.org>
Cr-Commit-Position: refs/heads/master@{#904357}
NOKEYCHECK=True
GitOrigin-RevId: 33679d241940ef6221b68d3e5daef606d7dd767d

8 files changed, 122 insertions, 117 deletions

diff --git a/arm_utils.cc b/arm_utils.cc
index 1eb01c3..2a915a8 100644
--- a/arm_utils.cc
+++ b/arm_utils.cc
@@ -16,9 +16,9 @@ inline bool IsMisaligned(rva_t rva, ArmAlign align) {
 
 }  // namespace
 
-/******** Arm32Rel32Translator ********/
+/******** AArch32Rel32Translator ********/
 
-Arm32Rel32Translator::Arm32Rel32Translator() = default;
+AArch32Rel32Translator::AArch32Rel32Translator() = default;
 
 // The mapping between ARM instruction "Code" to "Displacement" involves complex
 // bit manipulation. The comments below annotate bits mappings using a string.
@@ -30,7 +30,7 @@ Arm32Rel32Translator::Arm32Rel32Translator() = default;
 // * Lowercase letters denote bit fields with orders preserved.
 
 // static
-ArmAlign Arm32Rel32Translator::DecodeA24(uint32_t code32, arm_disp_t* disp) {
+ArmAlign AArch32Rel32Translator::DecodeA24(uint32_t code32, arm_disp_t* disp) {
   // Handle multiple instructions. Let cccc != 1111:
   // B encoding A1:
   //   Code:         cccc1010 Siiiiiii iiiiiiii iiiiiiii
@@ -56,7 +56,7 @@ ArmAlign Arm32Rel32Translator::DecodeA24(uint32_t code32, arm_disp_t* disp) {
 }
 
 // static
-bool Arm32Rel32Translator::EncodeA24(arm_disp_t disp, uint32_t* code32) {
+bool AArch32Rel32Translator::EncodeA24(arm_disp_t disp, uint32_t* code32) {
   uint32_t t = *code32;
   uint8_t bits = GetUnsignedBits<24, 27>(t);
   if (bits == 0xA || bits == 0xB) {
@@ -81,9 +81,9 @@ bool Arm32Rel32Translator::EncodeA24(arm_disp_t disp, uint32_t* code32) {
 }
 
 // static
-bool Arm32Rel32Translator::ReadA24(rva_t instr_rva,
-                                   uint32_t code32,
-                                   rva_t* target_rva) {
+bool AArch32Rel32Translator::ReadA24(rva_t instr_rva,
+                                     uint32_t code32,
+                                     rva_t* target_rva) {
   constexpr ArmAlign kInstrAlign = kArmAlign4;
   if (IsMisaligned(instr_rva, kInstrAlign))
     return false;
@@ -96,9 +96,9 @@ bool Arm32Rel32Translator::ReadA24(rva_t instr_rva,
 }
 
 // static
-bool Arm32Rel32Translator::WriteA24(rva_t instr_rva,
-                                    rva_t target_rva,
-                                    uint32_t* code32) {
+bool AArch32Rel32Translator::WriteA24(rva_t instr_rva,
+                                      rva_t target_rva,
+                                      uint32_t* code32) {
   constexpr ArmAlign kInstrAlign = kArmAlign4;
   if (IsMisaligned(instr_rva, kInstrAlign))
     return false;
@@ -113,7 +113,7 @@ bool Arm32Rel32Translator::WriteA24(rva_t instr_rva,
 }
 
 // static
-ArmAlign Arm32Rel32Translator::DecodeT8(uint16_t code16, arm_disp_t* disp) {
+ArmAlign AArch32Rel32Translator::DecodeT8(uint16_t code16, arm_disp_t* disp) {
   if ((code16 & 0xF000) == 0xD000 && (code16 & 0x0F00) != 0x0F00) {
     // B encoding T1:
     //   Code:         1101cccc Siiiiiii
@@ -125,7 +125,7 @@ ArmAlign Arm32Rel32Translator::DecodeT8(uint16_t code16, arm_disp_t* disp) {
 }
 
 // static
-bool Arm32Rel32Translator::EncodeT8(arm_disp_t disp, uint16_t* code16) {
+bool AArch32Rel32Translator::EncodeT8(arm_disp_t disp, uint16_t* code16) {
   uint16_t t = *code16;
   if ((t & 0xF000) == 0xD000 && (t & 0x0F00) != 0x0F00) {
     if (disp % 2)  // Require 2-byte alignment.
@@ -140,9 +140,9 @@ bool Arm32Rel32Translator::EncodeT8(arm_disp_t disp, uint16_t* code16) {
 }
 
 // static
-bool Arm32Rel32Translator::ReadT8(rva_t instr_rva,
-                                  uint16_t code16,
-                                  rva_t* target_rva) {
+bool AArch32Rel32Translator::ReadT8(rva_t instr_rva,
+                                    uint16_t code16,
+                                    rva_t* target_rva) {
   constexpr ArmAlign kInstrAlign = kArmAlign2;
   if (IsMisaligned(instr_rva, kInstrAlign))
     return false;
@@ -155,9 +155,9 @@ bool Arm32Rel32Translator::ReadT8(rva_t instr_rva,
 }
 
 // static
-bool Arm32Rel32Translator::WriteT8(rva_t instr_rva,
-                                   rva_t target_rva,
-                                   uint16_t* code16) {
+bool AArch32Rel32Translator::WriteT8(rva_t instr_rva,
+                                     rva_t target_rva,
+                                     uint16_t* code16) {
   constexpr ArmAlign kInstrAlign = kArmAlign2;
   constexpr ArmAlign kTargetAlign = kArmAlign2;
   if (IsMisaligned(instr_rva, kInstrAlign) ||
@@ -170,7 +170,7 @@ bool Arm32Rel32Translator::WriteT8(rva_t instr_rva,
 }
 
 // static
-ArmAlign Arm32Rel32Translator::DecodeT11(uint16_t code16, arm_disp_t* disp) {
+ArmAlign AArch32Rel32Translator::DecodeT11(uint16_t code16, arm_disp_t* disp) {
   if ((code16 & 0xF800) == 0xE000) {
     // B encoding T2:
     //   Code:         11100Sii iiiiiiii
@@ -182,7 +182,7 @@ ArmAlign Arm32Rel32Translator::DecodeT11(uint16_t code16, arm_disp_t* disp) {
 }
 
 // static
-bool Arm32Rel32Translator::EncodeT11(arm_disp_t disp, uint16_t* code16) {
+bool AArch32Rel32Translator::EncodeT11(arm_disp_t disp, uint16_t* code16) {
   uint16_t t = *code16;
   if ((t & 0xF800) == 0xE000) {
     if (disp % 2)  // Require 2-byte alignment.
@@ -197,9 +197,9 @@ bool Arm32Rel32Translator::EncodeT11(arm_disp_t disp, uint16_t* code16) {
 }
 
 // static
-bool Arm32Rel32Translator::ReadT11(rva_t instr_rva,
-                                   uint16_t code16,
-                                   rva_t* target_rva) {
+bool AArch32Rel32Translator::ReadT11(rva_t instr_rva,
+                                     uint16_t code16,
+                                     rva_t* target_rva) {
   constexpr ArmAlign kInstrAlign = kArmAlign2;
   if (IsMisaligned(instr_rva, kInstrAlign))
     return false;
@@ -212,9 +212,9 @@ bool Arm32Rel32Translator::ReadT11(rva_t instr_rva,
 }
 
 // static
-bool Arm32Rel32Translator::WriteT11(rva_t instr_rva,
-                                    rva_t target_rva,
-                                    uint16_t* code16) {
+bool AArch32Rel32Translator::WriteT11(rva_t instr_rva,
+                                      rva_t target_rva,
+                                      uint16_t* code16) {
   constexpr ArmAlign kInstrAlign = kArmAlign2;
   constexpr ArmAlign kTargetAlign = kArmAlign2;
   if (IsMisaligned(instr_rva, kInstrAlign) ||
@@ -227,7 +227,7 @@ bool Arm32Rel32Translator::WriteT11(rva_t instr_rva,
 }
 
 // static
-ArmAlign Arm32Rel32Translator::DecodeT20(uint32_t code32, arm_disp_t* disp) {
+ArmAlign AArch32Rel32Translator::DecodeT20(uint32_t code32, arm_disp_t* disp) {
   if ((code32 & 0xF800D000) == 0xF0008000 &&
       (code32 & 0x03C00000) != 0x03C00000) {
     // B encoding T3. Note the reversal of "(J1)" and "(J2)".
@@ -247,7 +247,7 @@ ArmAlign Arm32Rel32Translator::DecodeT20(uint32_t code32, arm_disp_t* disp) {
 }
 
 // static
-bool Arm32Rel32Translator::EncodeT20(arm_disp_t disp, uint32_t* code32) {
+bool AArch32Rel32Translator::EncodeT20(arm_disp_t disp, uint32_t* code32) {
   uint32_t t = *code32;
   if ((t & 0xF800D000) == 0xF0008000 && (t & 0x03C00000) != 0x03C00000) {
     if (disp % 2)  // Require 2-byte alignment.
@@ -268,9 +268,9 @@ bool Arm32Rel32Translator::EncodeT20(arm_disp_t disp, uint32_t* code32) {
 }
 
 // static
-bool Arm32Rel32Translator::ReadT20(rva_t instr_rva,
-                                   uint32_t code32,
-                                   rva_t* target_rva) {
+bool AArch32Rel32Translator::ReadT20(rva_t instr_rva,
+                                     uint32_t code32,
+                                     rva_t* target_rva) {
   constexpr ArmAlign kInstrAlign = kArmAlign2;
   if (IsMisaligned(instr_rva, kInstrAlign))
     return false;
@@ -283,9 +283,9 @@ bool Arm32Rel32Translator::ReadT20(rva_t instr_rva,
 }
 
 // static
-bool Arm32Rel32Translator::WriteT20(rva_t instr_rva,
-                                    rva_t target_rva,
-                                    uint32_t* code32) {
+bool AArch32Rel32Translator::WriteT20(rva_t instr_rva,
+                                      rva_t target_rva,
+                                      uint32_t* code32) {
   constexpr ArmAlign kInstrAlign = kArmAlign2;
   constexpr ArmAlign kTargetAlign = kArmAlign2;
   if (IsMisaligned(instr_rva, kInstrAlign) ||
@@ -298,7 +298,7 @@ bool Arm32Rel32Translator::WriteT20(rva_t instr_rva,
 }
 
 // static
-ArmAlign Arm32Rel32Translator::DecodeT24(uint32_t code32, arm_disp_t* disp) {
+ArmAlign AArch32Rel32Translator::DecodeT24(uint32_t code32, arm_disp_t* disp) {
   uint32_t bits = code32 & 0xF800D000;
   if (bits == 0xF0009000 || bits == 0xF000D000 || bits == 0xF000C000) {
     // Let I1 = J1 ^ S ^ 1, I2 = J2 ^ S ^ 1.
@@ -335,7 +335,7 @@ ArmAlign Arm32Rel32Translator::DecodeT24(uint32_t code32, arm_disp_t* disp) {
 }
 
 // static
-bool Arm32Rel32Translator::EncodeT24(arm_disp_t disp, uint32_t* code32) {
+bool AArch32Rel32Translator::EncodeT24(arm_disp_t disp, uint32_t* code32) {
   uint32_t t = *code32;
   uint32_t bits = t & 0xF800D000;
   if (bits == 0xF0009000 || bits == 0xF000D000 || bits == 0xF000C000) {
@@ -365,9 +365,9 @@ bool Arm32Rel32Translator::EncodeT24(arm_disp_t disp, uint32_t* code32) {
 }
 
 // static
-bool Arm32Rel32Translator::ReadT24(rva_t instr_rva,
-                                   uint32_t code32,
-                                   rva_t* target_rva) {
+bool AArch32Rel32Translator::ReadT24(rva_t instr_rva,
+                                     uint32_t code32,
+                                     rva_t* target_rva) {
   constexpr ArmAlign kInstrAlign = kArmAlign2;
   if (IsMisaligned(instr_rva, kInstrAlign))
     return false;
@@ -380,9 +380,9 @@ bool Arm32Rel32Translator::ReadT24(rva_t instr_rva,
 }
 
 // static
-bool Arm32Rel32Translator::WriteT24(rva_t instr_rva,
-                                    rva_t target_rva,
-                                    uint32_t* code32) {
+bool AArch32Rel32Translator::WriteT24(rva_t instr_rva,
+                                      rva_t target_rva,
+                                      uint32_t* code32) {
   constexpr ArmAlign kInstrAlign = kArmAlign2;
   if (IsMisaligned(instr_rva, kInstrAlign))
     return false;
diff --git a/arm_utils.h b/arm_utils.h
index 6d8e784..63c7538 100644
--- a/arm_utils.h
+++ b/arm_utils.h
@@ -9,14 +9,13 @@
 #include <stdint.h>
 
 #include "base/check_op.h"
-#include "base/macros.h"
 #include "components/zucchini/address_translator.h"
 #include "components/zucchini/buffer_view.h"
 
 namespace zucchini {
 
 // References:
-// * ARM32 (32-bit ARM, AKA AArch32):
+// * AArch32 (32-bit ARM, AKA ARM32):
 //     https://static.docs.arm.com/ddi0406/c/DDI0406C_C_arm_architecture_reference_manual.pdf
 // * AArch64 (64-bit ARM):
 //     https://static.docs.arm.com/ddi0487/da/DDI0487D_a_armv8_arm.pdf
@@ -130,7 +129,7 @@ inline int GetThumb2InstructionSize(uint16_t code16) {
 
 // A translator for ARM mode and THUMB2 mode with static functions that
 // translate among |code|, |disp|, and |target_rva|.
-class Arm32Rel32Translator {
+class AArch32Rel32Translator {
  public:
   // Rel32 address types enumeration.
   enum AddrType : uint8_t {
@@ -150,7 +149,10 @@ class Arm32Rel32Translator {
     NUM_ADDR_TYPE
   };
 
-  Arm32Rel32Translator();
+  AArch32Rel32Translator();
+  AArch32Rel32Translator(const AArch32Rel32Translator&) = delete;
+  const AArch32Rel32Translator& operator=(const AArch32Rel32Translator&) =
+      delete;
 
   // Fetches the 32-bit ARM instruction |code| at |view[idx]|.
   static inline uint32_t FetchArmCode32(ConstBufferView view, offset_t idx) {
@@ -324,9 +326,6 @@ class Arm32Rel32Translator {
                                        EncodeT24,
                                        ReadT24,
                                        WriteT24>;
-
- private:
-  DISALLOW_COPY_AND_ASSIGN(Arm32Rel32Translator);
 };
 
 // Translator for AArch64, which is simpler than 32-bit ARM. Although pointers
@@ -345,6 +344,9 @@ class AArch64Rel32Translator {
   // Although RVA for 64-bit architecture can be 64-bit in length, we make the
   // bold assumption that for ELF images that RVA will stay nicely in 32-bit!
   AArch64Rel32Translator();
+  AArch64Rel32Translator(const AArch64Rel32Translator&) = delete;
+  const AArch64Rel32Translator& operator=(const AArch64Rel32Translator&) =
+      delete;
 
   static inline uint32_t FetchCode32(ConstBufferView view, offset_t idx) {
     return view.read<uint32_t>(idx);
@@ -357,7 +359,7 @@ class AArch64Rel32Translator {
   }
 
   // Conversion functions for |code32| from/to |disp| or |target_rva|, similar
-  // to the counterparts in Arm32Rel32Translator.
+  // to the counterparts in AArch32Rel32Translator.
   static ArmAlign DecodeImmd14(uint32_t code32, arm_disp_t* disp);
   static bool EncodeImmd14(arm_disp_t disp, uint32_t* code32);
   static bool ReadImmd14(rva_t instr_rva, uint32_t code32, rva_t* target_rva);
@@ -410,9 +412,6 @@ class AArch64Rel32Translator {
                                           EncodeImmd26,
                                           ReadImmd26,
                                           WriteImmd26>;
-
- private:
-  DISALLOW_COPY_AND_ASSIGN(AArch64Rel32Translator);
 };
 
 }  // namespace zucchini
diff --git a/arm_utils_unittest.cc b/arm_utils_unittest.cc
index 56aa1f9..8109c92 100644
--- a/arm_utils_unittest.cc
+++ b/arm_utils_unittest.cc
@@ -121,8 +121,8 @@ static bool SplitBits(const std::string& pattern,
   return true;
 }
 
-// ARM32 or AArch64 instruction specification for tests. May be 16-bit or 32-bit
-// (determined by INT_T).
+// AArch32 or AArch64 instruction specification for tests. May be 16-bit or
+// 32-bit (determined by INT_T).
 template <typename INT_T>
 struct ArmRelInstruction {
   ArmRelInstruction(const std::string& code_pattern_in, INT_T code)
@@ -307,10 +307,10 @@ TEST(ArmUtilsTest, SplitBits) {
   run_test("BAD", "AAAAaaaa BBBB01..", 0xFC02);  // Constant mismatch.
 }
 
-TEST(Arm32Rel32Translator, Fetch) {
+TEST(AArch32Rel32Translator, Fetch) {
   std::vector<uint8_t> bytes = {0x10, 0x32, 0x54, 0x76, 0x98, 0xBA, 0xDC, 0xFE};
   ConstBufferView region(&bytes[0], bytes.size());
-  Arm32Rel32Translator translator;
+  AArch32Rel32Translator translator;
   EXPECT_EQ(0x76543210U, translator.FetchArmCode32(region, 0U));
   EXPECT_EQ(0xFEDCBA98U, translator.FetchArmCode32(region, 4U));
 
@@ -321,7 +321,7 @@ TEST(Arm32Rel32Translator, Fetch) {
   EXPECT_EQ(0xBA98FEDCU, translator.FetchThumb2Code32(region, 4U));
 }
 
-TEST(Arm32Rel32Translator, Store) {
+TEST(AArch32Rel32Translator, Store) {
   std::vector<uint8_t> expected = {
       0xFF, 0xFF, 0xFF, 0xFF,  // Padding.
       0x10, 0x32, 0x54, 0x76,  // ARM 32-bit.
@@ -336,7 +336,7 @@ TEST(Arm32Rel32Translator, Store) {
   MutableBufferView region(&bytes[0], bytes.size());
   CHECK_EQ(expected.size(), bytes.size());
 
-  Arm32Rel32Translator translator;
+  AArch32Rel32Translator translator;
   translator.StoreArmCode32(region, 4U, 0x76543210U);
   translator.StoreThumb2Code16(region, 10U, 0x8642U);
   translator.StoreThumb2Code32(region, 14U, 0xFEDCBA98U);
@@ -346,10 +346,11 @@ TEST(Arm32Rel32Translator, Store) {
 
 // Detailed test of Encode/Decode: Check valid and invalid |disp| for various
 // clean slate |code| cases. Also check |disp| and |code| binary components,
-// which in Arm32Rel32Translator comments.
-TEST(Arm32Rel32Translator, EncodeDecode) {
+// which in AArch32Rel32Translator comments.
+TEST(AArch32Rel32Translator, EncodeDecode) {
   // A24 tests.
-  ArmTranslatorEncodeDecodeTest<Arm32Rel32Translator::AddrTraits_A24> test_A24;
+  ArmTranslatorEncodeDecodeTest<AArch32Rel32Translator::AddrTraits_A24>
+      test_A24;
   for (int cond = 0; cond <= 0x0E; ++cond) {
     ArmRelInstruction<uint32_t> B_A1_cond("cccc1010 Siiiiiii iiiiiiii iiiiiiii",
                                           kCleanSlateB_A1 | (cond << 28));
@@ -368,7 +369,7 @@ TEST(Arm32Rel32Translator, EncodeDecode) {
                {1, -1, 0x41, 0x43, 0x02000000, -0x02000002});
 
   // T8 tests.
-  ArmTranslatorEncodeDecodeTest<Arm32Rel32Translator::AddrTraits_T8> test_T8;
+  ArmTranslatorEncodeDecodeTest<AArch32Rel32Translator::AddrTraits_T8> test_T8;
   for (int cond = 0; cond <= 0x0E; ++cond) {
     ArmRelInstruction<uint16_t> B_T1_cond("1101cccc Siiiiiii",
                                           kCleanSlateB_T1 | (cond << 8));
@@ -383,14 +384,16 @@ TEST(Arm32Rel32Translator, EncodeDecode) {
               {0x00FE, -0x0100, 0, 2, 4, 0x40, 0x41, 0x0100, -0x0102});
 
   // T11 tests.
-  ArmTranslatorEncodeDecodeTest<Arm32Rel32Translator::AddrTraits_T11> test_T11;
+  ArmTranslatorEncodeDecodeTest<AArch32Rel32Translator::AddrTraits_T11>
+      test_T11;
   ArmRelInstruction<uint16_t> B_T2("11100Sii iiiiiiii", kCleanSlateB_T2);
   test_T11.Run("SSSSSSSS SSSSSSSS SSSSSiii iiiiiii0", {"S", "i"}, {B_T2},
                {0x07FE, -0x0800, 0, 2, -2, 4, 0x40, 0x42},
                {1, -1, 0x41, 0x43, 0x0800, -0x0802});
 
   // T20 tests.
-  ArmTranslatorEncodeDecodeTest<Arm32Rel32Translator::AddrTraits_T20> test_T20;
+  ArmTranslatorEncodeDecodeTest<AArch32Rel32Translator::AddrTraits_T20>
+      test_T20;
   for (int cond = 0; cond <= 0x0E; ++cond) {
     ArmRelInstruction<uint32_t> B_T3_cond(
         "11110Scc cciiiiii 10(J1)0(J2)jjj jjjjjjjj",
@@ -409,7 +412,8 @@ TEST(Arm32Rel32Translator, EncodeDecode) {
                 0x00100000, -0x00100002});
 
   // T24 tests.
-  ArmTranslatorEncodeDecodeTest<Arm32Rel32Translator::AddrTraits_T24> test_T24;
+  ArmTranslatorEncodeDecodeTest<AArch32Rel32Translator::AddrTraits_T24>
+      test_T24;
   // "Clean slate" means J1 = J2 = 1, so we include 0x00002800.
   ArmRelInstruction<uint32_t> B_T4("11110Sii iiiiiiii 10(J1)1(J2)jjj jjjjjjjj",
                                    kCleanSlateB_T4);
@@ -431,7 +435,7 @@ TEST(Arm32Rel32Translator, EncodeDecode) {
       {1, -1, 2, -2, 0x41, 0x42, 0x43, 0x00FFFFFE, 0x01000000, -0x01000002});
 }
 
-TEST(Arm32Rel32Translator, WriteRead) {
+TEST(AArch32Rel32Translator, WriteRead) {
   std::vector<rva_t> aligned4;
   std::vector<rva_t> misaligned4;
   std::vector<rva_t> aligned2;
@@ -450,7 +454,7 @@ TEST(Arm32Rel32Translator, WriteRead) {
   auto pcThumb2 = [](rva_t instr_rva) -> rva_t { return instr_rva + 4; };
 
   // A24 tests.
-  ArmTranslatorWriteReadTest<Arm32Rel32Translator::AddrTraits_A24> test_A24;
+  ArmTranslatorWriteReadTest<AArch32Rel32Translator::AddrTraits_A24> test_A24;
   for (uint32_t clean_slate_code : {kCleanSlateB_A1, kCleanSlateBL_A1}) {
     test_A24.Accept(clean_slate_code, aligned4, aligned4);
     test_A24.Reject(clean_slate_code, aligned4, misaligned4);
@@ -475,7 +479,7 @@ TEST(Arm32Rel32Translator, WriteRead) {
                    pcArm(0x16FFFFFE + 2), pcArm(0x16FFFFFE + 4)});
 
   // T8 tests.
-  ArmTranslatorWriteReadTest<Arm32Rel32Translator::AddrTraits_T8> test_T8;
+  ArmTranslatorWriteReadTest<AArch32Rel32Translator::AddrTraits_T8> test_T8;
   test_T8.Accept(kCleanSlateB_T1, aligned2, aligned2);
   test_T8.Reject(kCleanSlateB_T1, aligned2, misaligned2);
   test_T8.Reject(kCleanSlateB_T1, misaligned2, aligned2);
@@ -487,7 +491,7 @@ TEST(Arm32Rel32Translator, WriteRead) {
                  {pcThumb2(0x10000400 - 2), pcThumb2(0x100005FE + 2)});
 
   // T11 tests.
-  ArmTranslatorWriteReadTest<Arm32Rel32Translator::AddrTraits_T11> test_T11;
+  ArmTranslatorWriteReadTest<AArch32Rel32Translator::AddrTraits_T11> test_T11;
   test_T11.Accept(kCleanSlateB_T2, aligned2, aligned2);
   test_T11.Reject(kCleanSlateB_T2, aligned2, misaligned2);
   test_T11.Reject(kCleanSlateB_T2, misaligned2, aligned2);
@@ -499,7 +503,7 @@ TEST(Arm32Rel32Translator, WriteRead) {
                   {pcThumb2(0x10002800 - 2), pcThumb2(0x100037FE + 2)});
 
   // T20 tests.
-  ArmTranslatorWriteReadTest<Arm32Rel32Translator::AddrTraits_T20> test_T20;
+  ArmTranslatorWriteReadTest<AArch32Rel32Translator::AddrTraits_T20> test_T20;
   test_T20.Accept(kCleanSlateB_T3, aligned2, aligned2);
   test_T20.Reject(kCleanSlateB_T3, aligned2, misaligned2);
   test_T20.Reject(kCleanSlateB_T3, misaligned2, aligned2);
@@ -511,7 +515,7 @@ TEST(Arm32Rel32Translator, WriteRead) {
                   {pcThumb2(0x10200000 - 2), pcThumb2(0x103FFFFE + 2)});
 
   // T24 tests.
-  ArmTranslatorWriteReadTest<Arm32Rel32Translator::AddrTraits_T24> test_T24;
+  ArmTranslatorWriteReadTest<AArch32Rel32Translator::AddrTraits_T24> test_T24;
   for (uint32_t clean_slate_code : {kCleanSlateB_T4, kCleanSlateBL_T1}) {
     test_T24.Accept(clean_slate_code, aligned2, aligned2);
     test_T24.Reject(clean_slate_code, aligned2, misaligned2);
@@ -537,12 +541,12 @@ TEST(Arm32Rel32Translator, WriteRead) {
 }
 
 // Typical usage in |target_rva| extraction.
-TEST(Arm32Rel32Translator, Main) {
+TEST(AArch32Rel32Translator, Main) {
   // ARM mode (32-bit).
   // 00103050: 00 01 02 EA    B     00183458 ; B encoding A1 (cond = AL).
   {
     rva_t instr_rva = 0x00103050U;
-    Arm32Rel32Translator translator;
+    AArch32Rel32Translator translator;
     std::vector<uint8_t> bytes = {0x00, 0x01, 0x02, 0xEA};
     MutableBufferView region(&bytes[0], bytes.size());
     uint32_t code = translator.FetchArmCode32(region, 0U);
@@ -572,7 +576,7 @@ TEST(Arm32Rel32Translator, Main) {
   // 001030A2: F3 E7          B     0010308C ; B encoding T2.
   {
     rva_t instr_rva = 0x001030A2U;
-    Arm32Rel32Translator translator;
+    AArch32Rel32Translator translator;
     std::vector<uint8_t> bytes = {0xF3, 0xE7};
     MutableBufferView region(&bytes[0], bytes.size());
     uint16_t code = translator.FetchThumb2Code16(region, 0U);
@@ -603,7 +607,7 @@ TEST(Arm32Rel32Translator, Main) {
   // 001030A2: 00 F0 01 FA    BL    001034A8 ; BL encoding T1.
   {
     rva_t instr_rva = 0x001030A2U;
-    Arm32Rel32Translator translator;
+    AArch32Rel32Translator translator;
     std::vector<uint8_t> bytes = {0x00, 0xF0, 0x01, 0xFA};
     MutableBufferView region(&bytes[0], bytes.size());
     uint32_t code = translator.FetchThumb2Code32(region, 0U);
@@ -630,12 +634,12 @@ TEST(Arm32Rel32Translator, Main) {
   }
 }
 
-TEST(Arm32Rel32Translator, BLXComplication) {
+TEST(AArch32Rel32Translator, BLXComplication) {
   auto run_test = [](rva_t instr_rva,
                      std::vector<uint8_t> bytes,  // Pass by value.
                      uint32_t expected_code, arm_disp_t expected_disp,
                      uint32_t clean_slate_code, rva_t expected_target_rva) {
-    Arm32Rel32Translator translator;
+    AArch32Rel32Translator translator;
     MutableBufferView region(&bytes[0], bytes.size());
     uint32_t code = translator.FetchThumb2Code32(region, 0U);
     EXPECT_EQ(expected_code, code);
diff --git a/disassembler_elf.h b/disassembler_elf.h
index 60d524c..17e7523 100644
--- a/disassembler_elf.h
+++ b/disassembler_elf.h
@@ -12,7 +12,6 @@
 #include <string>
 #include <vector>
 
-#include "base/macros.h"
 #include "components/zucchini/address_translator.h"
 #include "components/zucchini/buffer_view.h"
 #include "components/zucchini/disassembler.h"
@@ -35,6 +34,7 @@ struct Elf32Traits {
 };
 
 // Architecture-specific definitions.
+
 struct Elf32IntelTraits : public Elf32Traits {
   static constexpr ExecutableType kExeType = kExeTypeElfX86;
   static const char kExeTypeString[];
@@ -72,6 +72,8 @@ class DisassemblerElf : public Disassembler {
   // of an executable. Returns true iff the check passes.
   static bool QuickDetect(ConstBufferView image);
 
+  DisassemblerElf(const DisassemblerElf&) = delete;
+  const DisassemblerElf& operator=(const DisassemblerElf&) = delete;
   ~DisassemblerElf() override;
 
   // Disassembler:
@@ -150,9 +152,6 @@ class DisassemblerElf : public Disassembler {
 
   // Sorted file offsets of abs32 locations.
   std::vector<offset_t> abs32_locations_;
-
- private:
-  DISALLOW_COPY_AND_ASSIGN(DisassemblerElf);
 };
 
 // Disassembler for ELF with Intel architectures.
@@ -162,6 +161,8 @@ class DisassemblerElfIntel : public DisassemblerElf<Traits> {
   enum ReferenceType : uint8_t { kReloc, kAbs32, kRel32, kTypeCount };
 
   DisassemblerElfIntel();
+  DisassemblerElfIntel(const DisassemblerElfIntel&) = delete;
+  const DisassemblerElfIntel& operator=(const DisassemblerElfIntel&) = delete;
   ~DisassemblerElfIntel() override;
 
   // Disassembler:
@@ -181,8 +182,6 @@ class DisassemblerElfIntel : public DisassemblerElf<Traits> {
   // Sorted file offsets of rel32 locations.
   // Using std::deque to reduce peak memory footprint.
   std::deque<offset_t> rel32_locations_;
-
-  DISALLOW_COPY_AND_ASSIGN(DisassemblerElfIntel);
 };
 
 using DisassemblerElfX86 = DisassemblerElfIntel<Elf32IntelTraits>;
diff --git a/image_utils.h b/image_utils.h
index 3bd7a79..d948a91 100644
--- a/image_utils.h
+++ b/image_utils.h
@@ -150,7 +150,7 @@ enum ExecutableType : uint32_t {
   kExeTypeWin32X64 = ExeTypeToUint32("Px64"),
   kExeTypeElfX86 = ExeTypeToUint32("Ex86"),
   kExeTypeElfX64 = ExeTypeToUint32("Ex64"),
-  kExeTypeElfArm32 = ExeTypeToUint32("EA32"),
+  kExeTypeElfAArch32 = ExeTypeToUint32("EA32"),
   kExeTypeElfAArch64 = ExeTypeToUint32("EA64"),
   kExeTypeDex = ExeTypeToUint32("DEX "),
   kExeTypeZtf = ExeTypeToUint32("ZTF "),
@@ -163,7 +163,7 @@ constexpr ExecutableType CastToExecutableType(uint32_t possible_exe_type) {
     case kExeTypeWin32X64:    // Falls through.
     case kExeTypeElfX86:      // Falls through.
     case kExeTypeElfX64:      // Falls through.
-    case kExeTypeElfArm32:    // Falls through.
+    case kExeTypeElfAArch32:  // Falls through.
     case kExeTypeElfAArch64:  // Falls through.
     case kExeTypeDex:         // Falls through.
     case kExeTypeZtf:         // Falls through.
diff --git a/reference_bytes_mixer.h b/reference_bytes_mixer.h
index f8e351e..05407f1 100644
--- a/reference_bytes_mixer.h
+++ b/reference_bytes_mixer.h
@@ -10,7 +10,6 @@
 #include <memory>
 #include <vector>
 
-#include "base/macros.h"
 #include "components/zucchini/buffer_view.h"
 #include "components/zucchini/image_utils.h"
 
@@ -60,6 +59,8 @@ class Disassembler;
 class ReferenceBytesMixer {
  public:
   ReferenceBytesMixer();
+  ReferenceBytesMixer(const ReferenceBytesMixer&) = delete;
+  const ReferenceBytesMixer& operator=(const ReferenceBytesMixer&) = delete;
   virtual ~ReferenceBytesMixer();
 
   // Returns a new ReferenceBytesMixer instance that's owned by the caller.
@@ -81,9 +82,6 @@ class ReferenceBytesMixer {
                               offset_t old_offset,
                               ConstBufferView new_view,
                               offset_t new_offset);
-
- private:
-  DISALLOW_COPY_AND_ASSIGN(ReferenceBytesMixer);
 };
 
 }  // namespace zucchini
diff --git a/rel32_utils.h b/rel32_utils.h
index 4f7e0f3..db41d4a 100644
--- a/rel32_utils.h
+++ b/rel32_utils.h
@@ -10,7 +10,6 @@
 #include <memory>
 
 #include "base/logging.h"
-#include "base/macros.h"
 #include "components/zucchini/address_translator.h"
 #include "components/zucchini/arm_utils.h"
 #include "components/zucchini/buffer_view.h"
@@ -34,6 +33,8 @@ class Rel32ReaderX86 : public ReferenceReader {
                  offset_t hi,
                  const std::deque<offset_t>* locations,
                  const AddressTranslator& translator);
+  Rel32ReaderX86(const Rel32ReaderX86&) = delete;
+  const Rel32ReaderX86& operator=(const Rel32ReaderX86&) = delete;
   ~Rel32ReaderX86() override;
 
   // Returns the next reference, or absl::nullopt if exhausted.
@@ -46,8 +47,6 @@ class Rel32ReaderX86 : public ReferenceReader {
   const offset_t hi_;
   const std::deque<offset_t>::const_iterator last_;
   std::deque<offset_t>::const_iterator current_;
-
-  DISALLOW_COPY_AND_ASSIGN(Rel32ReaderX86);
 };
 
 // Writer for x86 / x64 rel32 References.
@@ -58,6 +57,8 @@ class Rel32WriterX86 : public ReferenceWriter {
   // |target_offset_to_rva_| and |location_offset_to_rva_| for address
   // translation, and therefore must outlive |*this|.
   Rel32WriterX86(MutableBufferView image, const AddressTranslator& translator);
+  Rel32WriterX86(const Rel32WriterX86&) = delete;
+  const Rel32WriterX86& operator=(const Rel32WriterX86&) = delete;
   ~Rel32WriterX86() override;
 
   void PutNext(Reference ref) override;
@@ -66,8 +67,6 @@ class Rel32WriterX86 : public ReferenceWriter {
   MutableBufferView image_;
   AddressTranslator::OffsetToRvaCache target_offset_to_rva_;
   AddressTranslator::OffsetToRvaCache location_offset_to_rva_;
-
-  DISALLOW_COPY_AND_ASSIGN(Rel32WriterX86);
 };
 
 // Reader that emits x86 / x64 References (locations and target) of a spcific
@@ -91,6 +90,9 @@ class Rel32ReaderArm : public ReferenceReader {
     rel32_end_ = rel32_locations.end();
   }
 
+  Rel32ReaderArm(const Rel32ReaderArm&) = delete;
+  const Rel32ReaderArm& operator=(const Rel32ReaderArm&) = delete;
+
   absl::optional<Reference> GetNext() override {
     while (cur_it_ < rel32_end_ && *cur_it_ < hi_) {
       offset_t location = *(cur_it_++);
@@ -113,8 +115,6 @@ class Rel32ReaderArm : public ReferenceReader {
   std::deque<offset_t>::const_iterator cur_it_;
   std::deque<offset_t>::const_iterator rel32_end_;
   offset_t hi_;
-
-  DISALLOW_COPY_AND_ASSIGN(Rel32ReaderArm);
 };
 
 // Writer for ARM rel32 References of a specific type.
@@ -127,6 +127,9 @@ class Rel32WriterArm : public ReferenceWriter {
                  MutableBufferView mutable_view)
       : mutable_view_(mutable_view), offset_to_rva_(translator) {}
 
+  Rel32WriterArm(const Rel32WriterArm&) = delete;
+  const Rel32WriterArm& operator=(const Rel32WriterArm&) = delete;
+
   void PutNext(Reference ref) override {
     CODE_T code = ADDR_TRAITS::Fetch(mutable_view_, ref.location);
     rva_t instr_rva = offset_to_rva_.Convert(ref.location);
@@ -143,8 +146,6 @@ class Rel32WriterArm : public ReferenceWriter {
  private:
   MutableBufferView mutable_view_;
   AddressTranslator::OffsetToRvaCache offset_to_rva_;
-
-  DISALLOW_COPY_AND_ASSIGN(Rel32WriterArm);
 };
 
 // Type for specialized versions of ArmCopyDisp().
diff --git a/rel32_utils_unittest.cc b/rel32_utils_unittest.cc
index 32fd7ae..f4a6bde 100644
--- a/rel32_utils_unittest.cc
+++ b/rel32_utils_unittest.cc
@@ -146,7 +146,7 @@ TEST(Rel32UtilsTest, Rel32WriterX86) {
             bytes);
 }
 
-TEST(Rel32UtilsTest, Rel32ReaderArm_Arm32) {
+TEST(Rel32UtilsTest, Rel32ReaderArm_AArch32) {
   constexpr offset_t kTestImageSize = 0x00100000U;
   constexpr rva_t kRvaBegin = 0x00030000U;
   TestAddressTranslator translator(kTestImageSize, kRvaBegin);
@@ -169,7 +169,7 @@ TEST(Rel32UtilsTest, Rel32ReaderArm_Arm32) {
 
   // Generate everything.
   auto reader1 =
-      std::make_unique<Rel32ReaderArm<Arm32Rel32Translator::AddrTraits_A24>>(
+      std::make_unique<Rel32ReaderArm<AArch32Rel32Translator::AddrTraits_A24>>(
           translator, region, rel32_locations_A24, 0x0000U, 0x0020U);
   CheckReader({{0x0008U, 0x0010U},
                {0x0010U, 0x0014U},
@@ -179,19 +179,19 @@ TEST(Rel32UtilsTest, Rel32ReaderArm_Arm32) {
 
   // Exclude last.
   auto reader2 =
-      std::make_unique<Rel32ReaderArm<Arm32Rel32Translator::AddrTraits_A24>>(
+      std::make_unique<Rel32ReaderArm<AArch32Rel32Translator::AddrTraits_A24>>(
           translator, region, rel32_locations_A24, 0x0000U, 0x001CU);
   CheckReader({{0x0008U, 0x0010U}, {0x0010U, 0x0014U}, {0x0018U, 0x0010U}},
               std::move(reader2));
 
   // Only find one.
   auto reader3 =
-      std::make_unique<Rel32ReaderArm<Arm32Rel32Translator::AddrTraits_A24>>(
+      std::make_unique<Rel32ReaderArm<AArch32Rel32Translator::AddrTraits_A24>>(
           translator, region, rel32_locations_A24, 0x000CU, 0x0018U);
   CheckReader({{0x0010U, 0x0014U}}, std::move(reader3));
 }
 
-TEST(Rel32UtilsTest, Rel32WriterArm_Arm32_Easy) {
+TEST(Rel32UtilsTest, Rel32WriterArm_AArch32_Easy) {
   constexpr offset_t kTestImageSize = 0x00100000U;
   constexpr rva_t kRvaBegin = 0x00030000U;
   TestAddressTranslator translator(kTestImageSize, kRvaBegin);
@@ -207,7 +207,7 @@ TEST(Rel32UtilsTest, Rel32WriterArm_Arm32_Easy) {
   MutableBufferView region(&bytes[0], bytes.size());
 
   auto writer1 =
-      std::make_unique<Rel32WriterArm<Arm32Rel32Translator::AddrTraits_T8>>(
+      std::make_unique<Rel32WriterArm<AArch32Rel32Translator::AddrTraits_T8>>(
           translator, region);
   writer1->PutNext({0x0002U, 0x0004U});
   EXPECT_EQ(0xFF, bytes[0x02]);  // 00030002: B   00030004 ; T8
@@ -218,7 +218,7 @@ TEST(Rel32UtilsTest, Rel32WriterArm_Arm32_Easy) {
   EXPECT_EQ(0xDE, bytes[0x03]);
 
   auto writer2 =
-      std::make_unique<Rel32WriterArm<Arm32Rel32Translator::AddrTraits_T11>>(
+      std::make_unique<Rel32WriterArm<AArch32Rel32Translator::AddrTraits_T11>>(
           translator, region);
   writer2->PutNext({0x0008U, 0x0008U});
   EXPECT_EQ(0xFE, bytes[0x08]);  // 00030008: B   00030008 ; T11
@@ -228,7 +228,7 @@ TEST(Rel32UtilsTest, Rel32WriterArm_Arm32_Easy) {
   EXPECT_EQ(0xE0, bytes[0x09]);
 
   auto writer3 =
-      std::make_unique<Rel32WriterArm<Arm32Rel32Translator::AddrTraits_T20>>(
+      std::make_unique<Rel32WriterArm<AArch32Rel32Translator::AddrTraits_T20>>(
           translator, region);
   writer3->PutNext({0x000CU, 0x000AU});
   EXPECT_EQ(0xBF, bytes[0x0C]);  // 0003000C: B   0003000A ; T20
@@ -242,7 +242,7 @@ TEST(Rel32UtilsTest, Rel32WriterArm_Arm32_Easy) {
   EXPECT_EQ(0x80, bytes[0x0F]);
 }
 
-TEST(Rel32UtilsTest, Rel32WriterArm_Arm32_Hard) {
+TEST(Rel32UtilsTest, Rel32WriterArm_AArch32_Hard) {
   constexpr offset_t kTestImageSize = 0x10000000U;
   constexpr rva_t kRvaBegin = 0x0C030000U;
   TestAddressTranslator translator(kTestImageSize, kRvaBegin);
@@ -258,7 +258,7 @@ TEST(Rel32UtilsTest, Rel32WriterArm_Arm32_Hard) {
   MutableBufferView region(&bytes[0], bytes.size());
 
   auto writer =
-      std::make_unique<Rel32WriterArm<Arm32Rel32Translator::AddrTraits_T24>>(
+      std::make_unique<Rel32WriterArm<AArch32Rel32Translator::AddrTraits_T24>>(
           translator, region);
   writer->PutNext({0x0002U, 0x0000U});
   EXPECT_EQ(0xFF, bytes[0x02]);  // 0C030002: B   0C030000 ; T24
@@ -303,7 +303,7 @@ TEST(Rel32UtilsTest, Rel32WriterArm_Arm32_Hard) {
 
 // Test BLX encoding A2, which is an ARM instruction that switches to THUMB2,
 // and therefore should have 2-byte alignment.
-TEST(Rel32UtilsTest, Arm32SwitchToThumb2) {
+TEST(Rel32UtilsTest, AArch32SwitchToThumb2) {
   constexpr offset_t kTestImageSize = 0x10000000U;
   constexpr rva_t kRvaBegin = 0x08030000U;
   TestAddressTranslator translator(kTestImageSize, kRvaBegin);
@@ -315,7 +315,7 @@ TEST(Rel32UtilsTest, Arm32SwitchToThumb2) {
   MutableBufferView region(&bytes[0], bytes.size());
 
   auto writer =
-      std::make_unique<Rel32WriterArm<Arm32Rel32Translator::AddrTraits_A24>>(
+      std::make_unique<Rel32WriterArm<AArch32Rel32Translator::AddrTraits_A24>>(
           translator, region);
 
   // To location that's 4-byte aligned.
@@ -340,11 +340,12 @@ TEST(Rel32UtilsTest, Arm32SwitchToThumb2) {
   EXPECT_EQ(0xFA, bytes[0x07]);
 }
 
-TEST(Rel32UtilsTest, ArmCopyDisp_Arm32) {
+TEST(Rel32UtilsTest, ArmCopyDisp_AArch32) {
   std::vector<uint8_t> expect_fail;
 
   // Successful A24.
-  ArmCopyDispFun copier_A24 = ArmCopyDisp<Arm32Rel32Translator::AddrTraits_A24>;
+  ArmCopyDispFun copier_A24 =
+      ArmCopyDisp<AArch32Rel32Translator::AddrTraits_A24>;
   CheckCopy({0x12, 0x34, 0x56, 0xEB},  // 00000100: BL     0158D150
             {0xA0, 0xC0, 0x0E, 0x2A},  // 00000100: BCS    003B0388
             {0x12, 0x34, 0x56, 0x2A},  // 00000100: BCS    0158D150
@@ -352,7 +353,7 @@ TEST(Rel32UtilsTest, ArmCopyDisp_Arm32) {
             copier_A24);
 
   // Successful T8.
-  ArmCopyDispFun copier_T8 = ArmCopyDisp<Arm32Rel32Translator::AddrTraits_T8>;
+  ArmCopyDispFun copier_T8 = ArmCopyDisp<AArch32Rel32Translator::AddrTraits_T8>;
   CheckCopy({0x12, 0xD5},  // 00000100: BPL    00000128
             {0xAB, 0xD8},  // 00000100: BHI    0000005A
             {0x12, 0xD8},  // 00000100: BHI    00000128
@@ -360,7 +361,8 @@ TEST(Rel32UtilsTest, ArmCopyDisp_Arm32) {
             copier_T8);
 
   // Successful T11.
-  ArmCopyDispFun copier_T11 = ArmCopyDisp<Arm32Rel32Translator::AddrTraits_T11>;
+  ArmCopyDispFun copier_T11 =
+      ArmCopyDisp<AArch32Rel32Translator::AddrTraits_T11>;
   CheckCopy({0xF5, 0xE0},  // 00000100: B      000002EE
             {0x12, 0xE7},  // 00000100: B      FFFFFF28
             {0xF5, 0xE0},  // 00000100: B      000002EE
@@ -371,7 +373,8 @@ TEST(Rel32UtilsTest, ArmCopyDisp_Arm32) {
   CheckCopy(expect_fail, expect_fail, {0xF5, 0xE0}, {0x12, 0xE7}, copier_T8);
 
   // Successful T20.
-  ArmCopyDispFun copier_T20 = ArmCopyDisp<Arm32Rel32Translator::AddrTraits_T20>;
+  ArmCopyDispFun copier_T20 =
+      ArmCopyDisp<AArch32Rel32Translator::AddrTraits_T20>;
   CheckCopy({0x41, 0xF2, 0xA5, 0x88},  // 00000100: BLS.W   0008124E
             {0x04, 0xF3, 0x3C, 0xA2},  // 00000100: BGT.W   0004457C
             {0x01, 0xF3, 0xA5, 0x88},  // 00000100: BGT.W   0008124E
@@ -388,7 +391,8 @@ TEST(Rel32UtilsTest, ArmCopyDisp_Arm32) {
             {0x84, 0xF3, 0x3C, 0xA2}, copier_A24);
 
   // T24: Mix B encoding T4 and BL encoding T1.
-  ArmCopyDispFun copier_T24 = ArmCopyDisp<Arm32Rel32Translator::AddrTraits_T24>;
+  ArmCopyDispFun copier_T24 =
+      ArmCopyDisp<AArch32Rel32Translator::AddrTraits_T24>;
   CheckCopy({0xFF, 0xF7, 0xFF, 0xFF},  // 00000100: BL      00000102
             {0x00, 0xF0, 0x00, 0x90},  // 00000100: B.W     00C00104
             {0xFF, 0xF7, 0xFF, 0xBF},  // 00000100: B.W     00000102