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| author | Simon Hosie <simon.hosie@arm.com> | 2014-05-01 23:28:45 -0700 |
|---|---|---|
| committer | Simon Hosie <simon.hosie@arm.com> | 2014-05-07 15:03:01 -0700 |
| commit | 1d9c887c58d115975e01c9d500595f503803dc8c (patch) | |
| tree | 7238184201d2cca382d88f93fd26c68c9ed3f817 /cpu_ref/rsCpuIntrinsics_advsimd_YuvToRGB.S | |
| parent | 9bd08e84ba2c9bd0708de5600877162126c4467c (diff) | |
| download | rs-1d9c887c58d115975e01c9d500595f503803dc8c.tar.gz | |
YuvToRGB sub-rectangle handling.
Fix some difficult edge cases when processing only a portion of the image.
Also fix a register-marshalling bug in AArch64 assembly.
Change-Id: I8cd67f394fb42b216b2c3c7401e90eb2b86fca3d
Diffstat (limited to 'cpu_ref/rsCpuIntrinsics_advsimd_YuvToRGB.S')
| -rw-r--r-- | cpu_ref/rsCpuIntrinsics_advsimd_YuvToRGB.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/cpu_ref/rsCpuIntrinsics_advsimd_YuvToRGB.S b/cpu_ref/rsCpuIntrinsics_advsimd_YuvToRGB.S index 9232a796..632ef7a4 100644 --- a/cpu_ref/rsCpuIntrinsics_advsimd_YuvToRGB.S +++ b/cpu_ref/rsCpuIntrinsics_advsimd_YuvToRGB.S @@ -165,7 +165,7 @@ 1: tbz x2, #0, 1f ld1 {v8.b}[1], [x1], #1 .if \interleaved - ld1 {v16.b}[1], [x3], #1 + ld1 {v16.h}[0], [x3], #2 .else ld1 {v16.b}[0], [x3], #1 ld1 {v17.b}[0], [x4], #1 @@ -247,7 +247,7 @@ END(rsdIntrinsicYuv2_K) * size_t xend); // x4 */ ENTRY(rsdIntrinsicYuv_K) - bic x5, x4, #1 + bic x5, x3, #1 add x0, x0, x5, LSL #2 add x1, x1, x5 add x3, x2, x5 @@ -273,7 +273,7 @@ END(rsdIntrinsicYuv_K) * size_t xend); // x4 */ ENTRY(rsdIntrinsicYuvR_K) - bic x5, x4, #1 + bic x5, x3, #1 add x0, x0, x5, LSL #2 add x1, x1, x5 add x3, x2, x5 |