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| author | Simon Hosie <simon.hosie@arm.com> | 2014-09-19 23:08:21 -0700 |
|---|---|---|
| committer | Jason Sams <jsams@google.com> | 2014-10-09 00:15:32 +0000 |
| commit | 9732e859ff5d1911915eb83411c9b1ae991c7523 (patch) | |
| tree | 3f3f5287112a1d63ac89676a462c221b0fd8f80e /cpu_ref/rsCpuIntrinsics_advsimd_YuvToRGB.S | |
| parent | 5ac3f46cf69d4abe377a266b96d0927d864c9868 (diff) | |
| download | rs-9732e859ff5d1911915eb83411c9b1ae991c7523.tar.gz | |
Tail-store fixes to AArch64 YuvToRGB assembly.
bug 17923388
Change-Id: I692cf3b38b0cf57404024170874070d5f2b95480
Diffstat (limited to 'cpu_ref/rsCpuIntrinsics_advsimd_YuvToRGB.S')
| -rw-r--r-- | cpu_ref/rsCpuIntrinsics_advsimd_YuvToRGB.S | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/cpu_ref/rsCpuIntrinsics_advsimd_YuvToRGB.S b/cpu_ref/rsCpuIntrinsics_advsimd_YuvToRGB.S index 632ef7a4..63868634 100644 --- a/cpu_ref/rsCpuIntrinsics_advsimd_YuvToRGB.S +++ b/cpu_ref/rsCpuIntrinsics_advsimd_YuvToRGB.S @@ -176,12 +176,17 @@ * same time as loading only part of a register. So the data is loaded * linearly and unpacked manually at this point if necessary. */ -1: uzp1 v8.16b, v8.16b, v9.16b +1: mov v18.8b, v8.8b + uzp1 v8.8b, v18.8b, v9.8b + uzp2 v9.8b, v18.8b, v9.8b .if \interleaved + mov v18.8b, v16.8b .if \swapuv - uzp1 v16.16b, v17.16b, v16.16b + uzp1 v16.8b, v17.8b, v18.8b + uzp2 v17.8b, v17.8b, v18.8b .else - uzp1 v16.16b, v16.16b, v17.16b + uzp1 v16.8b, v18.8b, v17.8b + uzp2 v17.8b, v18.8b, v17.8b .endif .endif @@ -225,7 +230,7 @@ ENTRY(rsdIntrinsicYuv2_K) add x1, x1, x4 add x4, x3, x6 add x3, x2, x6 - sub x2, x5, x6, LSL #2 + sub x2, x5, x6, LSL #1 sub x6, sp, #32 sub sp, sp, #64 |