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| author | Yichi Chen <yichichen@google.com> | 2021-05-26 23:35:56 +0800 |
|---|---|---|
| committer | Yichi Chen <yichichen@google.com> | 2021-05-27 21:18:12 +0800 |
| commit | fe189f7ded1e4b612245cd36b685b0e242682a17 (patch) | |
| tree | 01303aee6051304a15ee6bb497d154d832a26ce2 | |
| parent | e3a678186d514650cca2e0464c26cb10912e4e72 (diff) | |
| download | gchips-fe189f7ded1e4b612245cd36b685b0e242682a17.tar.gz | |
Gralloc: allow INTERNAL_Y8 and INTERNAL_YV12 access by Camera
The INTERNAL_Y8 and INTERNAL_YV12 are used by Camera in recording use
cases. The patch enables the linear support in camera.
Bug: 185281551
Test: Recording with INTERNAL_Y8 buffer allocation
Change-Id: Ida5b15736454ee8bc842e0ad8a3ec9eafb93f49a
| -rw-r--r-- | gralloc4/src/core/format_info.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gralloc4/src/core/format_info.cpp b/gralloc4/src/core/format_info.cpp index 1a8c92e..f3371f2 100644 --- a/gralloc4/src/core/format_info.cpp +++ b/gralloc4/src/core/format_info.cpp @@ -132,13 +132,13 @@ const format_ip_support_t formats_ip_support[] = { { .id = MALI_GRALLOC_FORMAT_INTERNAL_RGBX_8888, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN|F_AFBC, .gpu_wr = F_LIN|F_AFBC, .dpu_rd = F_LIN|F_AFBC, .dpu_wr = F_LIN, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_NONE, }, { .id = MALI_GRALLOC_FORMAT_INTERNAL_RGBA_1010102, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN|F_AFBC, .gpu_wr = F_LIN|F_AFBC, .dpu_rd = F_LIN|F_AFBC, .dpu_wr = F_LIN, .dpu_aeu_wr = F_AFBC, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_NONE, }, { .id = MALI_GRALLOC_FORMAT_INTERNAL_RGBA_16161616, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN|F_AFBC, .gpu_wr = F_LIN|F_AFBC, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_NONE, }, - { .id = MALI_GRALLOC_FORMAT_INTERNAL_Y8, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_NONE, .gpu_wr = F_NONE, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_NONE, }, + { .id = MALI_GRALLOC_FORMAT_INTERNAL_Y8, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_NONE, .gpu_wr = F_NONE, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_LIN, }, { .id = MALI_GRALLOC_FORMAT_INTERNAL_Y16, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_NONE, .gpu_wr = F_NONE, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_NONE, }, /* 420 (8-bit) */ { .id = MALI_GRALLOC_FORMAT_INTERNAL_YUV420_8BIT_I, .cpu_rd = F_NONE, .cpu_wr = F_NONE, .gpu_rd = F_AFBC, .gpu_wr = F_NONE, .dpu_rd = F_AFBC, .dpu_wr = F_NONE, .dpu_aeu_wr = F_AFBC, .vpu_rd = F_AFBC, .vpu_wr = F_AFBC, .cam_wr = F_NONE, }, { .id = MALI_GRALLOC_FORMAT_INTERNAL_NV12, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN|F_AFBC, .gpu_wr = F_LIN, .dpu_rd = F_LIN, .dpu_wr = F_LIN, .dpu_aeu_wr = F_NONE, .vpu_rd = F_LIN, .vpu_wr = F_LIN, .cam_wr = F_NONE, }, { .id = MALI_GRALLOC_FORMAT_INTERNAL_NV21, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN, .gpu_wr = F_LIN, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_LIN, .vpu_wr = F_LIN, .cam_wr = F_LIN, }, - { .id = MALI_GRALLOC_FORMAT_INTERNAL_YV12, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN, .gpu_wr = F_LIN, .dpu_rd = F_LIN, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_LIN, .vpu_wr = F_LIN, .cam_wr = F_NONE, }, + { .id = MALI_GRALLOC_FORMAT_INTERNAL_YV12, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN, .gpu_wr = F_LIN, .dpu_rd = F_LIN, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_LIN, .vpu_wr = F_LIN, .cam_wr = F_LIN, }, /* 422 (8-bit) */ { .id = MALI_GRALLOC_FORMAT_INTERNAL_YUV422_8BIT, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN|F_AFBC, .gpu_wr = F_LIN|F_AFBC, .dpu_rd = F_LIN|F_AFBC, .dpu_wr = F_NONE, .dpu_aeu_wr = F_AFBC, .vpu_rd = F_LIN, .vpu_wr = F_LIN, .cam_wr = F_LIN, }, { .id = MALI_GRALLOC_FORMAT_INTERNAL_NV16, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN|F_AFBC, .gpu_wr = F_LIN, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_NONE, }, |