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| author | TreeHugger Robot <treehugger-gerrit@google.com> | 2022-04-01 20:13:59 +0000 |
|---|---|---|
| committer | Android (Google) Code Review <android-gerrit@google.com> | 2022-04-01 20:13:59 +0000 |
| commit | 3edca1b242672d1d09e6921d71aa51fbe932170f (patch) | |
| tree | 929657bbe13088a06a8b9a27007b8e211acf3f96 | |
| parent | d8e708be1cd43bc8ec264b1a89d529a7e23e3922 (diff) | |
| parent | 618dced0130f011038a8b999fc8924a898a3f31c (diff) | |
| download | gchips-3edca1b242672d1d09e6921d71aa51fbe932170f.tar.gz | |
Merge changes from topic "b224879205" into tm-dev
* changes:
Align the format structs.
Allow Camera to write to P010.
| -rw-r--r-- | gralloc4/src/core/format_info.cpp | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/gralloc4/src/core/format_info.cpp b/gralloc4/src/core/format_info.cpp index c6f707c..abb271a 100644 --- a/gralloc4/src/core/format_info.cpp +++ b/gralloc4/src/core/format_info.cpp @@ -111,8 +111,8 @@ const format_info_t formats[] = { { ID(HAL_PIXEL_FORMAT_EXYNOS_YCbCr_420_SPN_10B_SBWC_L80), .npln = 2, .ncmp = { 1, 2, 0 }, .bps = 10, .bpp_afbc = { 0, 0, 0 }, .bpp = { 16, 32, 0 }, .hsub = 2, .vsub = 2, .align_w = 2, .align_h = 2, ALIGN_W_CPU_DEFAULT, .tile_size = 1, .has_alpha = false, .is_rgb = false, .is_yuv = true, .afbc = false, .linear = true, .yuv_transform = false, .flex = true, .planes_contiguous = false }, /* Google Formats */ - { ID(HAL_PIXEL_FORMAT_GOOGLE_NV12_SP), .npln = 2, .ncmp = { 1, 2, 0 }, .bps = 8, .bpp_afbc = { 0, 0, 0 }, .bpp = { 8, 16, 0 }, .hsub = 2, .vsub = 2, .align_w = 64, .align_h = 8, .align_w_cpu = 64, .tile_size = 1, .has_alpha = false, .is_rgb = false, .is_yuv = true, .afbc = false, .linear = true, .yuv_transform = false, .flex = true, .planes_contiguous = true }, - { ID(HAL_PIXEL_FORMAT_GOOGLE_NV12_SP_10B), .npln = 2, .ncmp = { 1, 2, 0 }, .bps = 10, .bpp_afbc = { 0, 0, 0 }, .bpp = { 16, 32, 0 }, .hsub = 2, .vsub = 2, .align_w = 64, .align_h = 8, .align_w_cpu = 64, .tile_size = 1, .has_alpha = false, .is_rgb = false, .is_yuv = true, .afbc = false, .linear = true, .yuv_transform = false, .flex = true, .planes_contiguous = true }, + { ID(HAL_PIXEL_FORMAT_GOOGLE_NV12_SP), .npln = 2, .ncmp = { 1, 2, 0 }, .bps = 8, .bpp_afbc = { 0, 0, 0 }, .bpp = { 8, 16, 0 }, .hsub = 2, .vsub = 2, .align_w = 64, .align_h = 8, .align_w_cpu = 64, .tile_size = 1, .has_alpha = false, .is_rgb = false, .is_yuv = true, .afbc = false, .linear = true, .yuv_transform = false, .flex = true, .planes_contiguous = true }, + { ID(HAL_PIXEL_FORMAT_GOOGLE_NV12_SP_10B), .npln = 2, .ncmp = { 1, 2, 0 }, .bps = 10, .bpp_afbc = { 0, 0, 0 }, .bpp = { 16, 32, 0 }, .hsub = 2, .vsub = 2, .align_w = 64, .align_h = 8, .align_w_cpu = 64, .tile_size = 1, .has_alpha = false, .is_rgb = false, .is_yuv = true, .afbc = false, .linear = true, .yuv_transform = false, .flex = true, .planes_contiguous = true }, { ID(HAL_PIXEL_FORMAT_GOOGLE_R_8), .npln = 1, .ncmp = { 1, 0, 0 }, .bps = 8, .bpp_afbc = { 8, 0, 0 }, .bpp = { 8, 0, 0 }, .hsub = 0, .vsub = 0, .align_w = 16, .align_h = 16, .align_w_cpu = 16, .tile_size = 1, .has_alpha = false, .is_rgb = true, .is_yuv = false, .afbc = true, .linear = true, .yuv_transform = false, .flex = true, .planes_contiguous = false }, { ID(HAL_PIXEL_FORMAT_GOOGLE_RG_88), .npln = 1, .ncmp = { 2, 0, 0 }, .bps = 8, .bpp_afbc = { 16, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 0, .vsub = 0, .align_w = 16, .align_h = 16, .align_w_cpu = 16, .tile_size = 1, .has_alpha = false, .is_rgb = true, .is_yuv = false, .afbc = true, .linear = true, .yuv_transform = false, .flex = true, .planes_contiguous = false }, /* END ALIGNED SECTION */ @@ -131,22 +131,22 @@ const format_ip_support_t formats_ip_support[] = { { .id = MALI_GRALLOC_FORMAT_INTERNAL_RGBA_8888, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN|F_AFBC, .gpu_wr = F_LIN|F_AFBC, .dpu_rd = F_LIN|F_AFBC, .dpu_wr = F_LIN, .dpu_aeu_wr = F_AFBC, .vpu_rd = F_LIN, .vpu_wr = F_NONE, .cam_wr = F_LIN, }, { .id = MALI_GRALLOC_FORMAT_INTERNAL_BGRA_8888, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN, .gpu_wr = F_LIN, .dpu_rd = F_LIN, .dpu_wr = F_LIN, .dpu_aeu_wr = F_NONE, .vpu_rd = F_LIN, .vpu_wr = F_NONE, .cam_wr = F_NONE, }, { .id = MALI_GRALLOC_FORMAT_INTERNAL_RGBX_8888, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN|F_AFBC, .gpu_wr = F_LIN|F_AFBC, .dpu_rd = F_LIN|F_AFBC, .dpu_wr = F_LIN, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_NONE, }, - { .id = MALI_GRALLOC_FORMAT_INTERNAL_RGBA_1010102, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN|F_AFBC, .gpu_wr = F_LIN|F_AFBC, .dpu_rd = F_LIN|F_AFBC, .dpu_wr = F_LIN, .dpu_aeu_wr = F_AFBC, .vpu_rd = F_LIN, .vpu_wr = F_NONE, .cam_wr = F_NONE, }, + { .id = MALI_GRALLOC_FORMAT_INTERNAL_RGBA_1010102, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN|F_AFBC, .gpu_wr = F_LIN|F_AFBC, .dpu_rd = F_LIN|F_AFBC, .dpu_wr = F_LIN, .dpu_aeu_wr = F_AFBC, .vpu_rd = F_LIN, .vpu_wr = F_NONE, .cam_wr = F_NONE, }, { .id = MALI_GRALLOC_FORMAT_INTERNAL_RGBA_16161616, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN|F_AFBC, .gpu_wr = F_LIN|F_AFBC, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_NONE, }, - { .id = MALI_GRALLOC_FORMAT_INTERNAL_Y8, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_NONE, .gpu_wr = F_NONE, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_LIN, }, + { .id = MALI_GRALLOC_FORMAT_INTERNAL_Y8, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_NONE, .gpu_wr = F_NONE, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_LIN, }, { .id = MALI_GRALLOC_FORMAT_INTERNAL_Y16, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_NONE, .gpu_wr = F_NONE, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_NONE, }, /* 420 (8-bit) */ { .id = MALI_GRALLOC_FORMAT_INTERNAL_YUV420_8BIT_I, .cpu_rd = F_NONE, .cpu_wr = F_NONE, .gpu_rd = F_AFBC, .gpu_wr = F_NONE, .dpu_rd = F_AFBC, .dpu_wr = F_NONE, .dpu_aeu_wr = F_AFBC, .vpu_rd = F_AFBC, .vpu_wr = F_AFBC, .cam_wr = F_NONE, }, { .id = MALI_GRALLOC_FORMAT_INTERNAL_NV12, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN|F_AFBC, .gpu_wr = F_LIN, .dpu_rd = F_LIN, .dpu_wr = F_LIN, .dpu_aeu_wr = F_NONE, .vpu_rd = F_LIN, .vpu_wr = F_LIN, .cam_wr = F_NONE, }, { .id = MALI_GRALLOC_FORMAT_INTERNAL_NV21, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN, .gpu_wr = F_LIN, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_LIN, .vpu_wr = F_LIN, .cam_wr = F_LIN, }, - { .id = MALI_GRALLOC_FORMAT_INTERNAL_YV12, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN, .gpu_wr = F_LIN, .dpu_rd = F_LIN, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_LIN, .vpu_wr = F_LIN, .cam_wr = F_LIN, }, + { .id = MALI_GRALLOC_FORMAT_INTERNAL_YV12, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN, .gpu_wr = F_LIN, .dpu_rd = F_LIN, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_LIN, .vpu_wr = F_LIN, .cam_wr = F_LIN, }, /* 422 (8-bit) */ { .id = MALI_GRALLOC_FORMAT_INTERNAL_YUV422_8BIT, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN|F_AFBC, .gpu_wr = F_LIN|F_AFBC, .dpu_rd = F_LIN|F_AFBC, .dpu_wr = F_NONE, .dpu_aeu_wr = F_AFBC, .vpu_rd = F_LIN, .vpu_wr = F_LIN, .cam_wr = F_LIN, }, { .id = MALI_GRALLOC_FORMAT_INTERNAL_NV16, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN|F_AFBC, .gpu_wr = F_LIN, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_NONE, }, /* 420 (10-bit) */ { .id = MALI_GRALLOC_FORMAT_INTERNAL_YUV420_10BIT_I, .cpu_rd = F_NONE, .cpu_wr = F_NONE, .gpu_rd = F_AFBC, .gpu_wr = F_AFBC, .dpu_rd = F_AFBC, .dpu_wr = F_NONE, .dpu_aeu_wr = F_AFBC, .vpu_rd = F_AFBC, .vpu_wr = F_AFBC, .cam_wr = F_NONE, }, { .id = MALI_GRALLOC_FORMAT_INTERNAL_Y0L2, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN, .gpu_wr = F_LIN, .dpu_rd = F_LIN, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_LIN, .vpu_wr = F_LIN, .cam_wr = F_NONE, }, - { .id = MALI_GRALLOC_FORMAT_INTERNAL_P010, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN, .gpu_wr = F_LIN, .dpu_rd = F_LIN, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_LIN, .vpu_wr = F_LIN, .cam_wr = F_NONE, }, + { .id = MALI_GRALLOC_FORMAT_INTERNAL_P010, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN, .gpu_wr = F_LIN, .dpu_rd = F_LIN, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_LIN, .vpu_wr = F_LIN, .cam_wr = F_LIN, }, /* 422 (10-bit) */ { .id = MALI_GRALLOC_FORMAT_INTERNAL_Y210, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN|F_AFBC, .gpu_wr = F_LIN|F_AFBC, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_NONE, }, { .id = MALI_GRALLOC_FORMAT_INTERNAL_P210, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN, .gpu_wr = F_LIN, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_NONE, }, @@ -155,9 +155,9 @@ const format_ip_support_t formats_ip_support[] = { { .id = MALI_GRALLOC_FORMAT_INTERNAL_Y410, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN, .gpu_wr = F_LIN|F_AFBC, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_NONE, }, /* Other */ { .id = MALI_GRALLOC_FORMAT_INTERNAL_RAW16, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN, .gpu_wr = F_NONE, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_LIN, }, - { .id = MALI_GRALLOC_FORMAT_INTERNAL_RAW12, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_NONE, .gpu_wr = F_NONE, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_LIN, }, - { .id = MALI_GRALLOC_FORMAT_INTERNAL_RAW10, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN, .gpu_wr = F_NONE, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_LIN, }, - { .id = MALI_GRALLOC_FORMAT_INTERNAL_BLOB, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN, .gpu_wr = F_LIN, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_LIN, }, + { .id = MALI_GRALLOC_FORMAT_INTERNAL_RAW12, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_NONE, .gpu_wr = F_NONE, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_LIN, }, + { .id = MALI_GRALLOC_FORMAT_INTERNAL_RAW10, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN, .gpu_wr = F_NONE, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_LIN, }, + { .id = MALI_GRALLOC_FORMAT_INTERNAL_BLOB, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_LIN, .gpu_wr = F_LIN, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_LIN, }, /* Depth and Stencil */ { .id = MALI_GRALLOC_FORMAT_INTERNAL_DEPTH_16, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_NONE, .gpu_wr = F_NONE, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_NONE, }, { .id = MALI_GRALLOC_FORMAT_INTERNAL_DEPTH_24, .cpu_rd = F_LIN, .cpu_wr = F_LIN, .gpu_rd = F_NONE, .gpu_wr = F_NONE, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr = F_NONE, }, |