diff options
| author | Weizhung Ding <weizhungding@google.com> | 2023-02-24 15:57:41 +0800 |
|---|---|---|
| committer | Weizhung Ding <weizhungding@google.com> | 2023-03-01 21:37:39 +0800 |
| commit | 52d41bf24f37938f11459118b4bfab854e2a07ba (patch) | |
| tree | 2db58b423cd7d6f804e24406fd02f6b5e4330518 /gralloc4/src | |
| parent | 61f2aeeff364cc645cdbf4a0c52748964d63db02 (diff) | |
| download | gchips-52d41bf24f37938f11459118b4bfab854e2a07ba.tar.gz | |
gralloc4: update config for R_8 format
Bug: 269535480
Test: no error log with R_8 format
Change-Id: I3fc0bb26ca8939e01972ce7f8daeac048f731813
Diffstat (limited to 'gralloc4/src')
| -rw-r--r-- | gralloc4/src/core/format_info.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gralloc4/src/core/format_info.cpp b/gralloc4/src/core/format_info.cpp index 08608fb..b993f16 100644 --- a/gralloc4/src/core/format_info.cpp +++ b/gralloc4/src/core/format_info.cpp @@ -208,7 +208,7 @@ const format_ip_support_t formats_ip_support[] = { /* BEGIN ALIGNED SECTION */ { .id = HAL_PIXEL_FORMAT_GOOGLE_NV12_SP, .cpu_wr = F_LIN, .cpu_rd = F_LIN, .gpu_wr = F_LIN, .gpu_rd = F_LIN, .dpu_wr = F_LIN, .dpu_rd = F_LIN, .dpu_aeu_wr = F_NONE, .vpu_wr = F_LIN, .vpu_rd = F_LIN, .cam_wr = F_LIN }, { .id = HAL_PIXEL_FORMAT_GOOGLE_NV12_SP_10B, .cpu_wr = F_LIN, .cpu_rd = F_LIN, .gpu_wr = F_LIN, .gpu_rd = F_LIN, .dpu_wr = F_LIN, .dpu_rd = F_LIN, .dpu_aeu_wr = F_NONE, .vpu_wr = F_LIN, .vpu_rd = F_LIN, .cam_wr = F_LIN }, - { .id = HAL_PIXEL_FORMAT_GOOGLE_R_8, .cpu_wr = F_LIN, .cpu_rd = F_LIN, .gpu_wr = F_LIN|F_AFBC, .gpu_rd = F_LIN|F_AFBC, .dpu_wr = F_NONE, .dpu_rd = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_wr = F_NONE, .vpu_rd = F_NONE, .cam_wr = F_LIN }, + { .id = HAL_PIXEL_FORMAT_GOOGLE_R_8, .cpu_wr = F_LIN, .cpu_rd = F_LIN, .gpu_wr = F_LIN|F_AFBC, .gpu_rd = F_LIN|F_AFBC, .dpu_wr = F_NONE, .dpu_rd = F_LIN, .dpu_aeu_wr = F_NONE, .vpu_wr = F_NONE, .vpu_rd = F_NONE, .cam_wr = F_LIN }, { .id = HAL_PIXEL_FORMAT_GOOGLE_RG_88, .cpu_wr = F_LIN, .cpu_rd = F_LIN, .gpu_wr = F_LIN|F_AFBC, .gpu_rd = F_LIN|F_AFBC, .dpu_wr = F_NONE, .dpu_rd = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_wr = F_NONE, .vpu_rd = F_NONE, .cam_wr = F_LIN }, /* END ALIGNED SECTION */ }; |