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| author | Weizhung Ding <weizhungding@google.com> | 2023-03-04 00:23:35 +0000 |
|---|---|---|
| committer | Android (Google) Code Review <android-gerrit@google.com> | 2023-03-04 00:23:35 +0000 |
| commit | c96b8b571c7a9aeedbbda7984cfadd6b18d00bf4 (patch) | |
| tree | bda231699753a245a3c9bcb65ee450b07fe9aaa7 /gralloc4/src | |
| parent | 9bfada9ffeaa78b2e99bb40e179ca259676bf601 (diff) | |
| parent | 52d41bf24f37938f11459118b4bfab854e2a07ba (diff) | |
| download | gchips-c96b8b571c7a9aeedbbda7984cfadd6b18d00bf4.tar.gz | |
Merge "gralloc4: update config for R_8 format" into udc-dev
Diffstat (limited to 'gralloc4/src')
| -rw-r--r-- | gralloc4/src/core/format_info.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gralloc4/src/core/format_info.cpp b/gralloc4/src/core/format_info.cpp index 08608fb..b993f16 100644 --- a/gralloc4/src/core/format_info.cpp +++ b/gralloc4/src/core/format_info.cpp @@ -208,7 +208,7 @@ const format_ip_support_t formats_ip_support[] = { /* BEGIN ALIGNED SECTION */ { .id = HAL_PIXEL_FORMAT_GOOGLE_NV12_SP, .cpu_wr = F_LIN, .cpu_rd = F_LIN, .gpu_wr = F_LIN, .gpu_rd = F_LIN, .dpu_wr = F_LIN, .dpu_rd = F_LIN, .dpu_aeu_wr = F_NONE, .vpu_wr = F_LIN, .vpu_rd = F_LIN, .cam_wr = F_LIN }, { .id = HAL_PIXEL_FORMAT_GOOGLE_NV12_SP_10B, .cpu_wr = F_LIN, .cpu_rd = F_LIN, .gpu_wr = F_LIN, .gpu_rd = F_LIN, .dpu_wr = F_LIN, .dpu_rd = F_LIN, .dpu_aeu_wr = F_NONE, .vpu_wr = F_LIN, .vpu_rd = F_LIN, .cam_wr = F_LIN }, - { .id = HAL_PIXEL_FORMAT_GOOGLE_R_8, .cpu_wr = F_LIN, .cpu_rd = F_LIN, .gpu_wr = F_LIN|F_AFBC, .gpu_rd = F_LIN|F_AFBC, .dpu_wr = F_NONE, .dpu_rd = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_wr = F_NONE, .vpu_rd = F_NONE, .cam_wr = F_LIN }, + { .id = HAL_PIXEL_FORMAT_GOOGLE_R_8, .cpu_wr = F_LIN, .cpu_rd = F_LIN, .gpu_wr = F_LIN|F_AFBC, .gpu_rd = F_LIN|F_AFBC, .dpu_wr = F_NONE, .dpu_rd = F_LIN, .dpu_aeu_wr = F_NONE, .vpu_wr = F_NONE, .vpu_rd = F_NONE, .cam_wr = F_LIN }, { .id = HAL_PIXEL_FORMAT_GOOGLE_RG_88, .cpu_wr = F_LIN, .cpu_rd = F_LIN, .gpu_wr = F_LIN|F_AFBC, .gpu_rd = F_LIN|F_AFBC, .dpu_wr = F_NONE, .dpu_rd = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_wr = F_NONE, .vpu_rd = F_NONE, .cam_wr = F_LIN }, /* END ALIGNED SECTION */ }; |