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| author | joenchen <joenchen@google.com> | 2022-10-13 00:38:45 +0000 |
|---|---|---|
| committer | joenchen <joenchen@google.com> | 2022-10-13 00:42:05 +0000 |
| commit | f7b32279702003b4661b7b0e45c527f81282013a (patch) | |
| tree | 8328d71fc5989239869fd69cc5db525ee17634da /libhwc2.1 | |
| parent | f78d738e276f95186a9fb9c9f7ea0836b2686992 (diff) | |
| download | gs101-f7b32279702003b4661b7b0e45c527f81282013a.tar.gz | |
libhwc2.1: support TDM based resource allocation
To support TDM based resource allocation, MPP structure
is required to be extended.
Bug: 191421040
Test: boot to home
Signed-off-by: YongWook Shin <yongwook.shin@samsung.com>
Change-Id: I0328aa074defff174bc18dc8a2d0318556dbab34
Diffstat (limited to 'libhwc2.1')
| -rw-r--r-- | libhwc2.1/ExynosHWCModule.h | 36 |
1 files changed, 12 insertions, 24 deletions
diff --git a/libhwc2.1/ExynosHWCModule.h b/libhwc2.1/ExynosHWCModule.h index f7aca6a..a20c398 100644 --- a/libhwc2.1/ExynosHWCModule.h +++ b/libhwc2.1/ExynosHWCModule.h @@ -40,18 +40,6 @@ enum { HWC_DISPLAY_NONE_BIT = 0 }; -/* - * pre_assign_info: all display_descriptors that want to reserve - */ -struct exynos_mpp_t { - int physicalType; - int logicalType; - char name[16]; - uint32_t physical_index; - uint32_t logical_index; - uint32_t pre_assign_info; -}; - #define MAX_NAME_SIZE 32 struct exynos_display_t { uint32_t type; @@ -129,12 +117,12 @@ static const dpp_channel_map_t idma_channel_map[] = { }; static const exynos_mpp_t available_otf_mpp_units[] = { - {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF0", 0, 0, HWC_DISPLAY_PRIMARY_BIT}, - {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF1", 1, 0, HWC_DISPLAY_PRIMARY_BIT}, - {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF2", 2, 0, HWC_DISPLAY_SECONDARY_BIT}, - {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS0", 0, 0, HWC_DISPLAY_PRIMARY_BIT}, - {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS1", 1, 0, HWC_DISPLAY_PRIMARY_BIT}, - {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS2", 2, 0, HWC_DISPLAY_PRIMARY_BIT} + {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF0", 0, 0, HWC_DISPLAY_PRIMARY_BIT, 0, 0}, + {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF1", 1, 0, HWC_DISPLAY_PRIMARY_BIT, 0, 0}, + {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF2", 2, 0, HWC_DISPLAY_SECONDARY_BIT, 0, 0}, + {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS0", 0, 0, HWC_DISPLAY_PRIMARY_BIT, 0, 0}, + {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS1", 1, 0, HWC_DISPLAY_PRIMARY_BIT, 0, 0}, + {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS2", 2, 0, HWC_DISPLAY_PRIMARY_BIT, 0, 0} }; } // namespace gs101 @@ -142,12 +130,12 @@ static const exynos_mpp_t available_otf_mpp_units[] = { const exynos_mpp_t AVAILABLE_M2M_MPP_UNITS[] = { #ifndef DISABLE_M2M_MPPS - {MPP_G2D, MPP_LOGICAL_G2D_YUV, "G2D0-YUV_PRI", 0, 0, HWC_DISPLAY_PRIMARY_BIT}, - {MPP_G2D, MPP_LOGICAL_G2D_YUV, "G2D0-YUV_PRI", 0, 1, HWC_DISPLAY_PRIMARY_BIT}, - {MPP_G2D, MPP_LOGICAL_G2D_YUV, "G2D0-YUV_EXT", 0, 2, HWC_DISPLAY_EXTERNAL_BIT}, - {MPP_G2D, MPP_LOGICAL_G2D_RGB, "G2D0-RGB_PRI", 0, 3, HWC_DISPLAY_PRIMARY_BIT}, - {MPP_G2D, MPP_LOGICAL_G2D_RGB, "G2D0-RGB_EXT", 0, 4, HWC_DISPLAY_EXTERNAL_BIT}, - {MPP_G2D, MPP_LOGICAL_G2D_COMBO, "G2D0-COMBO_VIR", 0, 5, HWC_DISPLAY_VIRTUAL_BIT} + {MPP_G2D, MPP_LOGICAL_G2D_YUV, "G2D0-YUV_PRI", 0, 0, HWC_DISPLAY_PRIMARY_BIT, 0, 0}, + {MPP_G2D, MPP_LOGICAL_G2D_YUV, "G2D0-YUV_PRI", 0, 1, HWC_DISPLAY_PRIMARY_BIT, 0, 0}, + {MPP_G2D, MPP_LOGICAL_G2D_YUV, "G2D0-YUV_EXT", 0, 2, HWC_DISPLAY_EXTERNAL_BIT, 0, 0}, + {MPP_G2D, MPP_LOGICAL_G2D_RGB, "G2D0-RGB_PRI", 0, 3, HWC_DISPLAY_PRIMARY_BIT, 0, 0}, + {MPP_G2D, MPP_LOGICAL_G2D_RGB, "G2D0-RGB_EXT", 0, 4, HWC_DISPLAY_EXTERNAL_BIT, 0, 0}, + {MPP_G2D, MPP_LOGICAL_G2D_COMBO, "G2D0-COMBO_VIR", 0, 5, HWC_DISPLAY_VIRTUAL_BIT, 0, 0} #endif }; |