From 5e6f5ecf9a194854e579aee0f202ad3c2db75a01 Mon Sep 17 00:00:00 2001 From: joenchen Date: Mon, 13 Feb 2023 01:25:37 +0000 Subject: libhwc2.1: reserve DPP_VGRFS2 for the outer display MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The camera preview is YUV layer and mirrored from inner to outer display, and the outer display’s orientation is different with the inner display. Therefore, HWC reserves the DPP_VGRFS2 for the outer display. Bug: 267449852 Test: use the camera apk + dual concurrent display Change-Id: Id477e73e811fd9cc6b15602691797537cabf3d7e --- libhwc2.1/ExynosHWCModule.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libhwc2.1/ExynosHWCModule.h b/libhwc2.1/ExynosHWCModule.h index 19c9a12..d816bdc 100644 --- a/libhwc2.1/ExynosHWCModule.h +++ b/libhwc2.1/ExynosHWCModule.h @@ -40,10 +40,10 @@ static const dpp_channel_map_t idma_channel_map[] = { static const exynos_mpp_t available_otf_mpp_units[] = { {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF0", 0, 0, HWC_DISPLAY_PRIMARY_BIT, 0, 0}, {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF1", 1, 0, HWC_DISPLAY_PRIMARY_BIT, 0, 0}, - {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF2", 2, 0, HWC_DISPLAY_SECONDARY_BIT, 0, 0}, + {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF2", 2, 0, HWC_DISPLAY_PRIMARY_BIT, 0, 0}, {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS0", 0, 0, HWC_DISPLAY_PRIMARY_BIT, 0, 0}, {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS1", 1, 0, HWC_DISPLAY_PRIMARY_BIT, 0, 0}, - {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS2", 2, 0, HWC_DISPLAY_PRIMARY_BIT, 0, 0} + {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS2", 2, 0, HWC_DISPLAY_SECONDARY_BIT, 0, 0} }; } // namespace gs201 -- cgit v1.2.3