spi: changed clock divider to match 100MHz SPI CLK

Signed-off-by: Jacob Pan <jacob.jun.pan@intel.com>

3 files changed, 4 insertions, 2 deletions

diff --git a/VERSION b/VERSION
index cdec7b6..fba0a4b 100644
--- a/VERSION
+++ b/VERSION
@@ -1,3 +1,4 @@
+0.8 changed default spi clock to 100mhz Aug 12, 2009
 0.7 build e820 table and add SPI controller selection. June 4, 2009
 0.6 optimized spi uart and initrd relocation performance. May 26, 2009
 0.5 add arch parameter. March 12, 2009
diff --git a/bootstub.c b/bootstub.c
index d05daba..03e623e 100644
--- a/bootstub.c
+++ b/bootstub.c
@@ -130,7 +130,7 @@ int bootstub(void)
 {
 	setup_idt();
 	setup_gdt();
-	bs_printk("Bootstub Version: 0.7 ...\n");
+	bs_printk("Bootstub Version: 0.8 ...\n");
 	setup_boot_params((struct boot_params *)BOOT_PARAMS_OFFSET, 
 		(struct setup_header *)SETUP_HEADER_OFFSET);
 	bs_printk("Jump to kernel 32bit entry ...\n");
diff --git a/spi-uart.c b/spi-uart.c
index b49e11e..49f06e9 100644
--- a/spi-uart.c
+++ b/spi-uart.c
@@ -52,7 +52,8 @@ static void spi_init()
 	/* set a default baud rate, 115200 */
 	/* feng, need make sure SPIC and MAXIM3110 match */
 	//spi_enable_clk(32);
-	pspi->baudr = 0xd8;
+	/* 100MHz SPI clock / 115200 BAUD rate */
+	pspi->baudr = 0x364;
 
 	/* need set the transmit threshhol? */
 	/* pspi->txftlr = 0x3; */