Better structure changing for spi-uart

5 files changed, 237 insertions, 215 deletions

diff --git a/Makefile b/Makefile
index bd3cfeb..083025e 100644
--- a/Makefile
+++ b/Makefile
@@ -1,4 +1,4 @@
-OBJ=bootstub.o head.o
+OBJ=bootstub.o spi-uart.o head.o
 
 all: bootstub
 
@@ -14,6 +14,9 @@ bootstub.elf:bootstub.lds $(OBJ)
 bootstub.o:bootstub.c
 	gcc -c bootstub.c
 
+spi-uart.o:spi-uart.c
+	gcc -c spi-uart.c
+
 head.o:head.S
 	gcc -c head.S
 
diff --git a/bootstub.c b/bootstub.c
index aed8f4e..1b16903 100644
--- a/bootstub.c
+++ b/bootstub.c
@@ -106,142 +106,14 @@ static int get_32bit_entry(unsigned char *ptr)
 	return (((unsigned int)ptr+511)/512)*512;
 }
 
-/* 
- *	SPI0 debug printk support
- * LNC can only use SPI0(0xff128000) for debug output, and it can only
- * print out single string, not supporting variable parameter
- */
-
-static spi_inited = 0;
-static struct mrst_spi_reg *pspi = 0;
-
-static void spi_init()
-{
-	u32 ctrlr0;
-
-	pspi = (struct mrst_spi_reg *)MRST_REGBASE_SPI0;
-
-	/* disable SPI controller first */
-	pspi->ssienr = 0x0;
-
-	/* set control param, 16 bits, transmit only mode */
-	ctrlr0 = pspi->ctrlr0;
-
-	ctrlr0 &= 0xfcc0;
-	ctrlr0 |= (0xf | (FRF_SPI << SPI_FRF_OFFSET)
-		       | (TMOD_TO << SPI_TMOD_OFFSET));
-	pspi->ctrlr0 = ctrlr0;
-	
-	/* set a default baud rate, 115200 */
-	/* feng, need make sure SPIC and MAXIM3110 match */
-	//spi_enable_clk(32);
-	pspi->baudr = 0x2;
-
-	/* need set the transmit threshhol? */
-	pspi->txftlr = 0x3;
-
-	/* disable all INT for early phase */
-	pspi->imr &= 0xffffff00;
-	
-	/* select one slave SPI device */
-	pspi->ser = 0x1;
-
-	/* enable the HW, this should be the last step for HW init */
-	pspi->ssienr |= 0x1;
-
-	spi_inited = 1;
-}
-
-/* set the ratio rate, INT */
-static void max3110_write_config(void)
-{
-	u16 config;
-
-	/* 115200, TM not set, no parity, 8bit word */
-	config = 0xc000; 	
-	pspi->dr[0] = config;
-}
-
-/* transfer char to a eligibal word and send to max3110 */
-static int max3110_write_data(char c)
-{
-	u16 data;
-	u8  config;
-
-	data = 0x8000 | c;
-	pspi->dr[0] = data;
-}
-
-/* slave select should be called in the read/write function */
-static int spi_max3110_putc(char c)
-{
-	unsigned int timeout;
-	u32 sr;
-	u32 test;
-
-#define MRST_SPI_TIMEOUT	0x200000
-
-	/* read RX FIFO out if there is any */
-	while ((pspi->sr & SR_RF_NOT_EMPT) && pspi->rxflr ) {
-		timeout = MRST_SPI_TIMEOUT;
-		while (timeout--) {
-			 if (!(pspi->sr & SR_BUSY))
-				break;
-		}
-
-		if (timeout == 0xffffffff)
-			return -1;
-		test = pspi->dr[0];
-	}
-
-	timeout = MRST_SPI_TIMEOUT;
-	/* early putc need make sure the TX FIFO is empty */
-	while (timeout--) {
-		sr = pspi->sr;
-		if ( (sr & SR_BUSY) || !(sr & SR_TF_EMPT))
-			continue;
-		else
-			break;
-	}
-
-	if (timeout == 0xffffffff) {
-		return -1;
-	}
-
-	max3110_write_data(c);
-
-	return 0;
-}
-
-
-void bs_spi_printk(const char *str)
-{
-	u32 ctrlr0;
-
-	if (!spi_inited)
-		spi_init();
-
-	if (!str)
-		return;
-
-	/* 
-	 * here we assume only 1 write_config is enough,
-	 * if not will call it for each putc 
-	 */
-	max3110_write_config();
-
-	while (*str) {
-		if (*str == '\n')
-			spi_max3110_putc('\r');
-		spi_max3110_putc(*str++);
-	}
-}
-
 int bootstub(void)
 {
-	bs_spi_printk("Bootstub Version: \n");
+	bs_spi_printk("Bootstub Version: 0.1 ...\n");
+	bs_spi_printk("Setting null idt table ...\n");
 	setup_idt();
+	bs_spi_printk("Setting gdt table ...\n");
 	setup_gdt();
+	bs_spi_printk("Setting boot_params structure ...\n");
 	setup_boot_params((struct boot_params *)BOOT_PARAMS_OFFSET, 
 		(struct setup_header *)SETUP_HEADER_OFFSET);
 	return get_32bit_entry((unsigned char *)BZIMAGE_OFFSET);
diff --git a/bootstub.h b/bootstub.h
index 4eb3ba8..2598a5c 100644
--- a/bootstub.h
+++ b/bootstub.h
@@ -29,85 +29,3 @@
          ((u64)(limit & 0x0000ffff)))
 
 #endif
-
-/* code for MRST early printk */
-typedef volatile unsigned short vu16;
-typedef volatile unsigned int	vu32;
-
-#define MRST_REGBASE_SPI0	0xff128000
-#define MRST_REGBASE_SPI1	0xff128400
-#define MRST_REGBASE_SPI2	0xff128800
-
-struct mrst_spi_reg {
-	vu32 ctrlr0;	/* control reg 0 */
-	vu32 ctrlr1;	/* control reg 1 */
-	vu32 ssienr;	/* SSI enable reg */
-	vu32 mwcr;	/* Microwire control reg */
-
-	vu32 ser;	/* slave enable reg */
-	vu32 baudr;
-	vu32 txftlr;
-	vu32 rxftlr;
-
-	vu32 txflr;
-	vu32 rxflr;
-	vu32 sr;
-	vu32 imr;
-
-	vu32 isr;
-	vu32 risr;
-	vu32 txoicr;
-	vu32 rxoicr;
-
-	vu32 rxuicr;
-	vu32 msticr;
-	vu32 icr;
-	vu32 dmacr;
-
-	vu32 dmatdlr;
-	vu32 dmardlr;
-	vu32 idr;
-	vu32 ssi_comp_version;
-
-	vu32 dr[16];	/* 16 bits access for each 32bit space */
-};
-
-/* bit fields in CTRLR0 */
-#define SPI_DFS_OFFSET			0
-#define SPI_FRF_OFFSET			4
-#define FRF_SPI				0x0
-#define FRF_SSP				0x1
-#define FRF_MICROWIRE			0x2
-#define FRF_RESV			0x3
-#define SPI_SCPH_OFFSET			6
-#define SPI_SCOL_OFFSET			7
-#define SPI_TMOD_OFFSET			8
-#define	TMOD_TR				0x0		/* xmit & recv */
-#define	TMOD_TO				0x1		/* xmit only */
-#define	TMOD_RO				0x2		/* recv only */
-#define	TMOD_EPROMREAD			0x3		/* eeprom read mode */
-
-#define SPI_SLVOE_OFFSET		10
-#define SPI_SRL_OFFSET			11
-#define SPI_CFS_OFFSET			12
-
-/* bit fields in SR, 7 bits */
-#define SR_MASK				0x7f		/* cover 7 bits */
-#define SR_BUSY				(1 << 0)	
-#define SR_TF_NOT_FULL			(1 << 1)
-#define SR_TF_EMPT			(1 << 2)	
-#define SR_RF_NOT_EMPT			(1 << 3)	
-#define SR_RF_FULL			(1 << 4)	
-#define SR_TX_ERR			(1 << 5)	
-#define SR_DCOL				(1 << 6)	
-
-/* bit fields in ISR, IMR, RISR, 7 bits */
-#define SPI_INT_TXEI			(1 << 0)
-#define SPI_INT_TXOI			(1 << 1)
-#define SPI_INT_RXUI			(1 << 2)
-#define SPI_INT_RXOI			(1 << 3)
-#define SPI_INT_RXFI			(1 << 4)
-#define SPI_INT_MSTI			(1 << 5)
-
-extern void bs_spi_printk(const char *str);
-
diff --git a/spi-uart.c b/spi-uart.c
new file mode 100644
index 0000000..d291af6
--- /dev/null
+++ b/spi-uart.c
@@ -0,0 +1,141 @@
+/*
+ * spi-uart debug routings 
+ * Copyright (C) 2008, Feng Tang <feng.tang@intel.com> Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include "spi-uart.h"
+
+#define MRST_SPI_TIMEOUT	0x200000
+static spi_inited = 0;
+static struct mrst_spi_reg *pspi = 0;
+
+static void spi_init()
+{
+	u32 ctrlr0;
+
+	pspi = (struct mrst_spi_reg *)MRST_REGBASE_SPI0;
+
+	/* disable SPI controller first */
+	pspi->ssienr = 0x0;
+
+	/* set control param, 16 bits, transmit only mode */
+	ctrlr0 = pspi->ctrlr0;
+
+	ctrlr0 &= 0xfcc0;
+	ctrlr0 |= (0xf | (FRF_SPI << SPI_FRF_OFFSET)
+		       | (TMOD_TO << SPI_TMOD_OFFSET));
+	pspi->ctrlr0 = ctrlr0;
+	
+	/* set a default baud rate, 115200 */
+	/* feng, need make sure SPIC and MAXIM3110 match */
+	//spi_enable_clk(32);
+	pspi->baudr = 0x2;
+
+	/* need set the transmit threshhol? */
+	pspi->txftlr = 0x3;
+
+	/* disable all INT for early phase */
+	pspi->imr &= 0xffffff00;
+	
+	/* select one slave SPI device */
+	pspi->ser = 0x1;
+
+	/* enable the HW, this should be the last step for HW init */
+	pspi->ssienr |= 0x1;
+
+	spi_inited = 1;
+}
+
+/* set the ratio rate, INT */
+static void max3110_write_config(void)
+{
+	u16 config;
+
+	/* 115200, TM not set, no parity, 8bit word */
+	config = 0xc000; 	
+	pspi->dr[0] = config;
+}
+
+/* transfer char to a eligibal word and send to max3110 */
+static int max3110_write_data(char c)
+{
+	u16 data;
+	u8  config;
+
+	data = 0x8000 | c;
+	pspi->dr[0] = data;
+}
+
+/* slave select should be called in the read/write function */
+static int spi_max3110_putc(char c)
+{
+	unsigned int timeout;
+	u32 sr;
+	u32 test;
+
+	/* read RX FIFO out if there is any */
+	while ((pspi->sr & SR_RF_NOT_EMPT) && pspi->rxflr ) {
+		timeout = MRST_SPI_TIMEOUT;
+		while (timeout--) {
+			 if (!(pspi->sr & SR_BUSY))
+				break;
+		}
+
+		if (timeout == 0xffffffff)
+			return -1;
+		test = pspi->dr[0];
+	}
+
+	timeout = MRST_SPI_TIMEOUT;
+	/* early putc need make sure the TX FIFO is empty */
+	while (timeout--) {
+		sr = pspi->sr;
+		if ( (sr & SR_BUSY) || !(sr & SR_TF_EMPT))
+			continue;
+		else
+			break;
+	}
+
+	if (timeout == 0xffffffff)
+		return -1;
+
+	max3110_write_data(c);
+
+	return 0;
+}
+
+
+void bs_spi_printk(const char *str)
+{
+	if (!spi_inited)
+		spi_init();
+
+	if (!str)
+		return;
+
+	/* 
+	 * here we assume only 1 write_config is enough,
+	 * if not will call it for each putc 
+	 */
+	max3110_write_config();
+
+	while (*str) {
+		if (*str == '\n')
+			spi_max3110_putc('\r');
+		spi_max3110_putc(*str++);
+	}
+}
diff --git a/spi-uart.h b/spi-uart.h
new file mode 100644
index 0000000..82060b6
--- /dev/null
+++ b/spi-uart.h
@@ -0,0 +1,88 @@
+/* define spi-uart debug constrains */
+/* code for MRST early printk */
+#ifndef _SPI_UART
+#define _SPI_UART
+
+#include "types.h"
+
+typedef volatile unsigned short vu16;
+typedef volatile unsigned int	vu32;
+
+#define MRST_REGBASE_SPI0	0xff128000
+#define MRST_REGBASE_SPI1	0xff128400
+#define MRST_REGBASE_SPI2	0xff128800
+
+struct mrst_spi_reg {
+	vu32 ctrlr0;	/* control reg 0 */
+	vu32 ctrlr1;	/* control reg 1 */
+	vu32 ssienr;	/* SSI enable reg */
+	vu32 mwcr;	/* Microwire control reg */
+
+	vu32 ser;	/* slave enable reg */
+	vu32 baudr;
+	vu32 txftlr;
+	vu32 rxftlr;
+
+	vu32 txflr;
+	vu32 rxflr;
+	vu32 sr;
+	vu32 imr;
+
+	vu32 isr;
+	vu32 risr;
+	vu32 txoicr;
+	vu32 rxoicr;
+
+	vu32 rxuicr;
+	vu32 msticr;
+	vu32 icr;
+	vu32 dmacr;
+
+	vu32 dmatdlr;
+	vu32 dmardlr;
+	vu32 idr;
+	vu32 ssi_comp_version;
+
+	vu32 dr[16];	/* 16 bits access for each 32bit space */
+};
+
+/* bit fields in CTRLR0 */
+#define SPI_DFS_OFFSET			0
+#define SPI_FRF_OFFSET			4
+#define FRF_SPI				0x0
+#define FRF_SSP				0x1
+#define FRF_MICROWIRE			0x2
+#define FRF_RESV			0x3
+#define SPI_SCPH_OFFSET			6
+#define SPI_SCOL_OFFSET			7
+#define SPI_TMOD_OFFSET			8
+#define	TMOD_TR				0x0		/* xmit & recv */
+#define	TMOD_TO				0x1		/* xmit only */
+#define	TMOD_RO				0x2		/* recv only */
+#define	TMOD_EPROMREAD			0x3		/* eeprom read mode */
+
+#define SPI_SLVOE_OFFSET		10
+#define SPI_SRL_OFFSET			11
+#define SPI_CFS_OFFSET			12
+
+/* bit fields in SR, 7 bits */
+#define SR_MASK				0x7f		/* cover 7 bits */
+#define SR_BUSY				(1 << 0)	
+#define SR_TF_NOT_FULL			(1 << 1)
+#define SR_TF_EMPT			(1 << 2)	
+#define SR_RF_NOT_EMPT			(1 << 3)	
+#define SR_RF_FULL			(1 << 4)	
+#define SR_TX_ERR			(1 << 5)	
+#define SR_DCOL				(1 << 6)	
+
+/* bit fields in ISR, IMR, RISR, 7 bits */
+#define SPI_INT_TXEI			(1 << 0)
+#define SPI_INT_TXOI			(1 << 1)
+#define SPI_INT_RXUI			(1 << 2)
+#define SPI_INT_RXOI			(1 << 3)
+#define SPI_INT_RXFI			(1 << 4)
+#define SPI_INT_MSTI			(1 << 5)
+
+extern void bs_spi_printk(const char *str);
+
+#endif