diff options
| author | Iliyan Malchev <malchev@google.com> | 2013-03-08 15:35:06 -0800 |
|---|---|---|
| committer | Iliyan Malchev <malchev@google.com> | 2013-03-14 13:28:06 -0700 |
| commit | f0edc3f155a136d87beccd5ecef75c2d4b6f6b64 (patch) | |
| tree | 446f3242e288dae3fad3918eac8b1962a26a36f9 | |
| parent | be611249f346eed84f935d2d4a1889d66b5da30f (diff) | |
| download | msm8960-f0edc3f155a136d87beccd5ecef75c2d4b6f6b64.tar.gz | |
msm8960: use CAF ion.h and msm_ion.h, update CAF headers
Change-Id: I79c22500e97f08384e6f6b5583791b36995e2043
Signed-off-by: Iliyan Malchev <malchev@google.com>
59 files changed, 10539 insertions, 889 deletions
diff --git a/kernel-headers/linux/ion.h b/kernel-headers/linux/ion.h new file mode 100644 index 0000000..4f501e8 --- /dev/null +++ b/kernel-headers/linux/ion.h @@ -0,0 +1,74 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef _LINUX_ION_H +#define _LINUX_ION_H +#include <linux/ioctl.h> +#include <linux/types.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct ion_handle; +enum ion_heap_type { + ION_HEAP_TYPE_SYSTEM, + ION_HEAP_TYPE_SYSTEM_CONTIG, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ION_HEAP_TYPE_CARVEOUT, + ION_HEAP_TYPE_DMA, + ION_HEAP_TYPE_CUSTOM, + ION_NUM_HEAPS, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#define ION_HEAP_SYSTEM_MASK (1 << ION_HEAP_TYPE_SYSTEM) +#define ION_HEAP_SYSTEM_CONTIG_MASK (1 << ION_HEAP_TYPE_SYSTEM_CONTIG) +#define ION_HEAP_CARVEOUT_MASK (1 << ION_HEAP_TYPE_CARVEOUT) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ION_HEAP_TYPE_DMA_MASK (1 << ION_HEAP_TYPE_DMA) +#define ION_FLAG_CACHED 1 +struct ion_allocation_data { + size_t len; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + size_t align; + unsigned int heap_mask; + unsigned int flags; + struct ion_handle *handle; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct ion_fd_data { + struct ion_handle *handle; + int fd; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct ion_handle_data { + struct ion_handle *handle; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct ion_custom_data { + unsigned int cmd; + unsigned long arg; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ION_IOC_MAGIC 'I' +#define ION_IOC_ALLOC _IOWR(ION_IOC_MAGIC, 0, struct ion_allocation_data) +#define ION_IOC_FREE _IOWR(ION_IOC_MAGIC, 1, struct ion_handle_data) +#define ION_IOC_MAP _IOWR(ION_IOC_MAGIC, 2, struct ion_fd_data) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ION_IOC_SHARE _IOWR(ION_IOC_MAGIC, 4, struct ion_fd_data) +#define ION_IOC_IMPORT _IOWR(ION_IOC_MAGIC, 5, struct ion_fd_data) +#define ION_IOC_CUSTOM _IOWR(ION_IOC_MAGIC, 6, struct ion_custom_data) +#endif +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + diff --git a/kernel-headers/linux/mfd/msm-adie-codec.h b/kernel-headers/linux/mfd/msm-adie-codec.h index 63fe193..e4c9e61 100644 --- a/kernel-headers/linux/mfd/msm-adie-codec.h +++ b/kernel-headers/linux/mfd/msm-adie-codec.h @@ -107,3 +107,4 @@ struct adie_codec_operations { }; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #endif + diff --git a/kernel-headers/linux/mfd/wcd9xxx/Kbuild b/kernel-headers/linux/mfd/wcd9xxx/Kbuild new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/kernel-headers/linux/mfd/wcd9xxx/Kbuild diff --git a/kernel-headers/linux/mfd/wcd9xxx/core.h b/kernel-headers/linux/mfd/wcd9xxx/core.h new file mode 100644 index 0000000..0d1a892 --- /dev/null +++ b/kernel-headers/linux/mfd/wcd9xxx/core.h @@ -0,0 +1,181 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef __MFD_TABLA_CORE_H__ +#define __MFD_TABLA_CORE_H__ +#include <linux/interrupt.h> +#include <linux/pm_qos.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_NUM_IRQ_REGS 3 +#define WCD9XXX_SLIM_NUM_PORT_REG 3 +#define WCD9XXX_INTERFACE_TYPE_SLIMBUS 0x00 +#define WCD9XXX_INTERFACE_TYPE_I2C 0x01 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_VERSION_1_0 0 +#define TABLA_VERSION_1_1 1 +#define TABLA_VERSION_2_0 2 +#define TABLA_IS_1_X(ver) (((ver == TABLA_VERSION_1_0) || (ver == TABLA_VERSION_1_1)) ? 1 : 0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_IS_2_0(ver) ((ver == TABLA_VERSION_2_0) ? 1 : 0) +#define SITAR_VERSION_1P0 0 +#define SITAR_VERSION_1P1 1 +#define SITAR_IS_1P0(ver) ((ver == SITAR_VERSION_1P0) ? 1 : 0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_IS_1P1(ver) ((ver == SITAR_VERSION_1P1) ? 1 : 0) +enum { + TABLA_IRQ_SLIMBUS = 0, + TABLA_IRQ_MBHC_REMOVAL, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + TABLA_IRQ_MBHC_SHORT_TERM, + TABLA_IRQ_MBHC_PRESS, + TABLA_IRQ_MBHC_RELEASE, + TABLA_IRQ_MBHC_POTENTIAL, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + TABLA_IRQ_MBHC_INSERTION, + TABLA_IRQ_BG_PRECHARGE, + TABLA_IRQ_PA1_STARTUP, + TABLA_IRQ_PA2_STARTUP, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + TABLA_IRQ_PA3_STARTUP, + TABLA_IRQ_PA4_STARTUP, + TABLA_IRQ_PA5_STARTUP, + TABLA_IRQ_MICBIAS1_PRECHARGE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + TABLA_IRQ_MICBIAS2_PRECHARGE, + TABLA_IRQ_MICBIAS3_PRECHARGE, + TABLA_IRQ_HPH_PA_OCPL_FAULT, + TABLA_IRQ_HPH_PA_OCPR_FAULT, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + TABLA_IRQ_EAR_PA_OCPL_FAULT, + TABLA_IRQ_HPH_L_PA_STARTUP, + TABLA_IRQ_HPH_R_PA_STARTUP, + TABLA_IRQ_EAR_PA_STARTUP, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + TABLA_NUM_IRQS, +}; +enum { + SITAR_IRQ_SLIMBUS = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SITAR_IRQ_MBHC_REMOVAL, + SITAR_IRQ_MBHC_SHORT_TERM, + SITAR_IRQ_MBHC_PRESS, + SITAR_IRQ_MBHC_RELEASE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SITAR_IRQ_MBHC_POTENTIAL, + SITAR_IRQ_MBHC_INSERTION, + SITAR_IRQ_BG_PRECHARGE, + SITAR_IRQ_PA1_STARTUP, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SITAR_IRQ_PA2_STARTUP, + SITAR_IRQ_PA3_STARTUP, + SITAR_IRQ_PA4_STARTUP, + SITAR_IRQ_PA5_STARTUP, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SITAR_IRQ_MICBIAS1_PRECHARGE, + SITAR_IRQ_MICBIAS2_PRECHARGE, + SITAR_IRQ_MICBIAS3_PRECHARGE, + SITAR_IRQ_HPH_PA_OCPL_FAULT, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SITAR_IRQ_HPH_PA_OCPR_FAULT, + SITAR_IRQ_EAR_PA_OCPL_FAULT, + SITAR_IRQ_HPH_L_PA_STARTUP, + SITAR_IRQ_HPH_R_PA_STARTUP, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SITAR_IRQ_EAR_PA_STARTUP, + SITAR_NUM_IRQS, +}; +enum { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + TAIKO_IRQ_SLIMBUS = 0, + TAIKO_IRQ_MBHC_REMOVAL, + TAIKO_IRQ_MBHC_SHORT_TERM, + TAIKO_IRQ_MBHC_PRESS, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + TAIKO_IRQ_MBHC_RELEASE, + TAIKO_IRQ_MBHC_POTENTIAL, + TAIKO_IRQ_MBHC_INSERTION, + TAIKO_IRQ_BG_PRECHARGE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + TAIKO_IRQ_PA1_STARTUP, + TAIKO_IRQ_PA2_STARTUP, + TAIKO_IRQ_PA3_STARTUP, + TAIKO_IRQ_PA4_STARTUP, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + TAIKO_IRQ_PA5_STARTUP, + TAIKO_IRQ_MICBIAS1_PRECHARGE, + TAIKO_IRQ_MICBIAS2_PRECHARGE, + TAIKO_IRQ_MICBIAS3_PRECHARGE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + TAIKO_IRQ_HPH_PA_OCPL_FAULT, + TAIKO_IRQ_HPH_PA_OCPR_FAULT, + TAIKO_IRQ_EAR_PA_OCPL_FAULT, + TAIKO_IRQ_HPH_L_PA_STARTUP, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + TAIKO_IRQ_HPH_R_PA_STARTUP, + TAIKO_IRQ_EAR_PA_STARTUP, + TAIKO_NUM_IRQS, +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum wcd9xxx_pm_state { + WCD9XXX_PM_SLEEPABLE, + WCD9XXX_PM_AWAKE, + WCD9XXX_PM_ASLEEP, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct wcd9xxx { + struct device *dev; + struct slim_device *slim; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct slim_device *slim_slave; + struct mutex io_lock; + struct mutex xfer_lock; + struct mutex irq_lock; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + u8 version; + unsigned int irq_base; + unsigned int irq; + u8 irq_masks_cur[WCD9XXX_NUM_IRQ_REGS]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + u8 irq_masks_cache[WCD9XXX_NUM_IRQ_REGS]; + u8 irq_level[WCD9XXX_NUM_IRQ_REGS]; + int reset_gpio; + int (*read_dev)(struct wcd9xxx *wcd9xxx, unsigned short reg, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int bytes, void *dest, bool interface_reg); + int (*write_dev)(struct wcd9xxx *wcd9xxx, unsigned short reg, + int bytes, void *src, bool interface_reg); + u32 num_of_supplies; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct regulator_bulk_data *supplies; + enum wcd9xxx_pm_state pm_state; + struct mutex pm_lock; + wait_queue_head_t pm_wq; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct pm_qos_request pm_qos_req; + int wlock_holders; + int num_rx_port; + int num_tx_port; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + u8 idbyte[4]; +}; +enum wcd9xxx_pm_state wcd9xxx_pm_cmpxchg(struct wcd9xxx *wcd9xxx, + enum wcd9xxx_pm_state o, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + enum wcd9xxx_pm_state n); +#endif + diff --git a/kernel-headers/linux/mfd/wcd9xxx/pdata.h b/kernel-headers/linux/mfd/wcd9xxx/pdata.h new file mode 100644 index 0000000..6e2eddf --- /dev/null +++ b/kernel-headers/linux/mfd/wcd9xxx/pdata.h @@ -0,0 +1,146 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef __MFD_TABLA_PDATA_H__ +#define __MFD_TABLA_PDATA_H__ +#include <linux/slimbus/slimbus.h> +#define MICBIAS_EXT_BYP_CAP 0x00 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MICBIAS_NO_EXT_BYP_CAP 0x01 +#define SITAR_LDOH_1P95_V 0x0 +#define SITAR_LDOH_2P35_V 0x1 +#define SITAR_LDOH_2P75_V 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_LDOH_2P85_V 0x3 +#define SITAR_CFILT1_SEL 0x0 +#define SITAR_CFILT2_SEL 0x1 +#define SITAR_CFILT3_SEL 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_LDOH_1P95_V 0x0 +#define TABLA_LDOH_2P35_V 0x1 +#define TABLA_LDOH_2P75_V 0x2 +#define TABLA_LDOH_2P85_V 0x3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_CFILT1_SEL 0x0 +#define TABLA_CFILT2_SEL 0x1 +#define TABLA_CFILT3_SEL 0x2 +#define TAIKO_CFILT1_SEL 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_CFILT2_SEL 0x1 +#define TAIKO_CFILT3_SEL 0x2 +#define TAIKO_LDOH_1P95_V 0x0 +#define TAIKO_LDOH_2P35_V 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_LDOH_2P75_V 0x2 +#define TAIKO_LDOH_2P85_V 0x3 +#define MAX_AMIC_CHANNEL 7 +#define TABLA_OCP_300_MA 0x0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_OCP_350_MA 0x2 +#define TABLA_OCP_365_MA 0x3 +#define TABLA_OCP_150_MA 0x4 +#define TABLA_OCP_190_MA 0x6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_OCP_220_MA 0x7 +#define TABLA_DCYCLE_255 0x0 +#define TABLA_DCYCLE_511 0x1 +#define TABLA_DCYCLE_767 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_DCYCLE_1023 0x3 +#define TABLA_DCYCLE_1279 0x4 +#define TABLA_DCYCLE_1535 0x5 +#define TABLA_DCYCLE_1791 0x6 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_DCYCLE_2047 0x7 +#define TABLA_DCYCLE_2303 0x8 +#define TABLA_DCYCLE_2559 0x9 +#define TABLA_DCYCLE_2815 0xA +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_DCYCLE_3071 0xB +#define TABLA_DCYCLE_3327 0xC +#define TABLA_DCYCLE_3583 0xD +#define TABLA_DCYCLE_3839 0xE +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_DCYCLE_4095 0xF +struct wcd9xxx_amic { + u8 legacy_mode:MAX_AMIC_CHANNEL; + u8 txfe_enable:MAX_AMIC_CHANNEL; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + u8 txfe_buff:MAX_AMIC_CHANNEL; + u8 use_pdata:MAX_AMIC_CHANNEL; +}; +struct wcd9xxx_micbias_setting { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + u8 ldoh_v; + u32 cfilt1_mv; + u32 cfilt2_mv; + u32 cfilt3_mv; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + u8 bias1_cfilt_sel; + u8 bias2_cfilt_sel; + u8 bias3_cfilt_sel; + u8 bias4_cfilt_sel; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + u8 bias1_cap_mode; + u8 bias2_cap_mode; + u8 bias3_cap_mode; + u8 bias4_cap_mode; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct wcd9xxx_ocp_setting { + unsigned int use_pdata:1; + unsigned int num_attempts:4; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int run_time:4; + unsigned int wait_time:4; + unsigned int hph_ocp_limit:3; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MAX_REGULATOR 7 +#define WCD9XXX_CDC_VDDA_CP_CUR_MAX 500000 +#define WCD9XXX_CDC_VDDA_RX_CUR_MAX 20000 +#define WCD9XXX_CDC_VDDA_TX_CUR_MAX 20000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_VDDIO_CDC_CUR_MAX 5000 +#define WCD9XXX_VDDD_CDC_D_CUR_MAX 5000 +#define WCD9XXX_VDDD_CDC_A_CUR_MAX 5000 +struct wcd9xxx_regulator { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + const char *name; + int min_uV; + int max_uV; + int optimum_uA; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct regulator *regulator; +}; +struct wcd9xxx_pdata { + int irq; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int irq_base; + int num_irqs; + int reset_gpio; + struct wcd9xxx_amic amic_settings; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct slim_device slimbus_slave_device; + struct wcd9xxx_micbias_setting micbias; + struct wcd9xxx_ocp_setting ocp; + struct wcd9xxx_regulator regulator[MAX_REGULATOR]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#endif + diff --git a/kernel-headers/linux/mfd/wcd9xxx/wcd9304_registers.h b/kernel-headers/linux/mfd/wcd9xxx/wcd9304_registers.h new file mode 100644 index 0000000..8635550 --- /dev/null +++ b/kernel-headers/linux/mfd/wcd9xxx/wcd9304_registers.h @@ -0,0 +1,984 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef SITAR_CODEC_DIGITAL_H +#define SITAR_CODEC_DIGITAL_H +#define SITAR_A_PIN_CTL_OE0 (0x10) +#define SITAR_A_PIN_CTL_OE0__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_PIN_CTL_OE1 (0x11) +#define SITAR_A_PIN_CTL_OE1__POR (0x00000000) +#define SITAR_A_PIN_CTL_DATA0 (0x12) +#define SITAR_A_PIN_CTL_DATA0__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_PIN_CTL_DATA1 (0x13) +#define SITAR_A_PIN_CTL_DATA1__POR (0x00000000) +#define SITAR_A_HDRIVE_GENERIC (0x18) +#define SITAR_A_HDRIVE_GENERIC__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_HDRIVE_OVERRIDE (0x19) +#define SITAR_A_HDRIVE_OVERRIDE__POR (0x00000008) +#define SITAR_A_ANA_CSR_WAIT_STATE (0x20) +#define SITAR_A_ANA_CSR_WAIT_STATE__POR (0x00000044) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_PROCESS_MONITOR_CTL0 (0x40) +#define SITAR_A_PROCESS_MONITOR_CTL0__POR (0x00000080) +#define SITAR_A_PROCESS_MONITOR_CTL1 (0x41) +#define SITAR_A_PROCESS_MONITOR_CTL1__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_PROCESS_MONITOR_CTL2 (0x42) +#define SITAR_A_PROCESS_MONITOR_CTL2__POR (0x00000000) +#define SITAR_A_PROCESS_MONITOR_CTL3 (0x43) +#define SITAR_A_PROCESS_MONITOR_CTL3__POR (0x00000001) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_QFUSE_CTL (0x48) +#define SITAR_A_QFUSE_CTL__POR (0x00000000) +#define SITAR_A_QFUSE_STATUS (0x49) +#define SITAR_A_QFUSE_STATUS__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_QFUSE_DATA_OUT0 (0x4A) +#define SITAR_A_QFUSE_DATA_OUT0__POR (0x00000000) +#define SITAR_A_QFUSE_DATA_OUT1 (0x4B) +#define SITAR_A_QFUSE_DATA_OUT1__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_QFUSE_DATA_OUT2 (0x4C) +#define SITAR_A_QFUSE_DATA_OUT2__POR (0x00000000) +#define SITAR_A_QFUSE_DATA_OUT3 (0x4D) +#define SITAR_A_QFUSE_DATA_OUT3__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_QFUSE_DATA_OUT4 (0x4E) +#define SITAR_A_QFUSE_DATA_OUT4__POR (0x00000000) +#define SITAR_A_QFUSE_DATA_OUT5 (0x4F) +#define SITAR_A_QFUSE_DATA_OUT5__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_QFUSE_DATA_OUT6 (0x50) +#define SITAR_A_QFUSE_DATA_OUT6__POR (0x00000000) +#define SITAR_A_QFUSE_DATA_OUT7 (0x51) +#define SITAR_A_QFUSE_DATA_OUT7__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CTL (0x80) +#define SITAR_A_CDC_CTL__POR (0x00000000) +#define SITAR_A_LEAKAGE_CTL (0x88) +#define SITAR_A_LEAKAGE_CTL__POR (0x00000004) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_INTR_MODE (0x90) +#define SITAR_A_INTR_MODE__POR (0x00000000) +#define SITAR_A_INTR_MASK0 (0x94) +#define SITAR_A_INTR_MASK0__POR (0x000000ff) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_INTR_MASK1 (0x95) +#define SITAR_A_INTR_MASK1__POR (0x000000ff) +#define SITAR_A_INTR_MASK2 (0x96) +#define SITAR_A_INTR_MASK2__POR (0x000000ff) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_INTR_STATUS0 (0x98) +#define SITAR_A_INTR_STATUS0__POR (0x00000000) +#define SITAR_A_INTR_STATUS1 (0x99) +#define SITAR_A_INTR_STATUS1__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_INTR_STATUS2 (0x9A) +#define SITAR_A_INTR_STATUS2__POR (0x00000000) +#define SITAR_A_INTR_CLEAR0 (0x9C) +#define SITAR_A_INTR_CLEAR0__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_INTR_CLEAR1 (0x9D) +#define SITAR_A_INTR_CLEAR1__POR (0x00000000) +#define SITAR_A_INTR_CLEAR2 (0x9E) +#define SITAR_A_INTR_CLEAR2__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_INTR_LEVEL0 (0xA0) +#define SITAR_A_INTR_LEVEL0__POR (0x00000001) +#define SITAR_A_INTR_LEVEL1 (0xA1) +#define SITAR_A_INTR_LEVEL1__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_INTR_LEVEL2 (0xA2) +#define SITAR_A_INTR_LEVEL2__POR (0x00000000) +#define SITAR_A_INTR_TEST0 (0xA4) +#define SITAR_A_INTR_TEST0__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_INTR_TEST1 (0xA5) +#define SITAR_A_INTR_TEST1__POR (0x00000000) +#define SITAR_A_INTR_TEST2 (0xA6) +#define SITAR_A_INTR_TEST2__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_INTR_SET0 (0xA8) +#define SITAR_A_INTR_SET0__POR (0x00000000) +#define SITAR_A_INTR_SET1 (0xA9) +#define SITAR_A_INTR_SET1__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_INTR_SET2 (0xAA) +#define SITAR_A_INTR_SET2__POR (0x00000000) +#define SITAR_A_CDC_TX_I2S_SCK_MODE (0xC0) +#define SITAR_A_CDC_TX_I2S_SCK_MODE__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_TX_I2S_WS_MODE (0xC1) +#define SITAR_A_CDC_TX_I2S_WS_MODE__POR (0x00000000) +#define SITAR_A_CDC_DMIC_DATA0_MODE (0xC4) +#define SITAR_A_CDC_DMIC_DATA0_MODE__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_DMIC_CLK0_MODE (0xC5) +#define SITAR_A_CDC_DMIC_CLK0_MODE__POR (0x00000000) +#define SITAR_A_CDC_DMIC_DATA1_MODE (0xC6) +#define SITAR_A_CDC_DMIC_DATA1_MODE__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_DMIC_CLK1_MODE (0xC7) +#define SITAR_A_CDC_DMIC_CLK1_MODE__POR (0x00000000) +#define SITAR_A_CDC_TX_I2S_SD0_MODE (0xC8) +#define SITAR_A_CDC_TX_I2S_SD0_MODE__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_INTR_MODE (0xC9) +#define SITAR_A_CDC_INTR_MODE__POR (0x00000000) +#define SITAR_A_CDC_RX_I2S_SD0_MODE (0xCA) +#define SITAR_A_CDC_RX_I2S_SD0_MODE__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_RX_I2S_SD1_MODE (0xCB) +#define SITAR_A_CDC_RX_I2S_SD1_MODE__POR (0x00000000) +#define SITAR_A_BIAS_REF_CTL (0x100) +#define SITAR_A_BIAS_REF_CTL__POR (0x0000001c) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_BIAS_CENTRAL_BG_CTL (0x101) +#define SITAR_A_BIAS_CENTRAL_BG_CTL__POR (0x00000050) +#define SITAR_A_BIAS_PRECHRG_CTL (0x102) +#define SITAR_A_BIAS_PRECHRG_CTL__POR (0x00000007) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_BIAS_CURR_CTL_1 (0x103) +#define SITAR_A_BIAS_CURR_CTL_1__POR (0x00000052) +#define SITAR_A_BIAS_CURR_CTL_2 (0x104) +#define SITAR_A_BIAS_CURR_CTL_2__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_BIAS_OSC_BG_CTL (0x105) +#define SITAR_A_BIAS_OSC_BG_CTL__POR (0x00000016) +#define SITAR_A_CLK_BUFF_EN1 (0x108) +#define SITAR_A_CLK_BUFF_EN1__POR (0x00000004) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CLK_BUFF_EN2 (0x109) +#define SITAR_A_CLK_BUFF_EN2__POR (0x00000002) +#define SITAR_A_LDO_H_MODE_1 (0x110) +#define SITAR_A_LDO_H_MODE_1__POR (0x00000065) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_LDO_H_MODE_2 (0x111) +#define SITAR_A_LDO_H_MODE_2__POR (0x000000a8) +#define SITAR_A_LDO_H_LOOP_CTL (0x112) +#define SITAR_A_LDO_H_LOOP_CTL__POR (0x0000006b) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_LDO_H_COMP_1 (0x113) +#define SITAR_A_LDO_H_COMP_1__POR (0x00000084) +#define SITAR_A_LDO_H_COMP_2 (0x114) +#define SITAR_A_LDO_H_COMP_2__POR (0x000000e0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_LDO_H_BIAS_1 (0x115) +#define SITAR_A_LDO_H_BIAS_1__POR (0x0000006d) +#define SITAR_A_LDO_H_BIAS_2 (0x116) +#define SITAR_A_LDO_H_BIAS_2__POR (0x000000a5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_LDO_H_BIAS_3 (0x117) +#define SITAR_A_LDO_H_BIAS_3__POR (0x00000060) +#define SITAR_A_MICB_CFILT_1_CTL (0x128) +#define SITAR_A_MICB_CFILT_1_CTL__POR (0x00000040) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_MICB_CFILT_1_VAL (0x129) +#define SITAR_A_MICB_CFILT_1_VAL__POR (0x00000080) +#define SITAR_A_MICB_CFILT_1_PRECHRG (0x12A) +#define SITAR_A_MICB_CFILT_1_PRECHRG__POR (0x00000038) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_MICB_1_CTL (0x12B) +#define SITAR_A_MICB_1_CTL__POR (0x00000016) +#define SITAR_A_MICB_1_INT_RBIAS (0x12C) +#define SITAR_A_MICB_1_INT_RBIAS__POR (0x00000024) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_MICB_1_MBHC (0x12D) +#define SITAR_A_MICB_1_MBHC__POR (0x00000001) +#define SITAR_A_MICB_CFILT_2_CTL (0x12E) +#define SITAR_A_MICB_CFILT_2_CTL__POR (0x00000040) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_MICB_CFILT_2_VAL (0x12F) +#define SITAR_A_MICB_CFILT_2_VAL__POR (0x00000080) +#define SITAR_A_MICB_CFILT_2_PRECHRG (0x130) +#define SITAR_A_MICB_CFILT_2_PRECHRG__POR (0x00000038) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_MICB_2_CTL (0x131) +#define SITAR_A_MICB_2_CTL__POR (0x00000016) +#define SITAR_A_MICB_2_INT_RBIAS (0x132) +#define SITAR_A_MICB_2_INT_RBIAS__POR (0x00000024) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_MICB_2_MBHC (0x133) +#define SITAR_A_MICB_2_MBHC__POR (0x00000002) +#define SITAR_A_TX_COM_BIAS (0x14C) +#define SITAR_A_TX_COM_BIAS__POR (0x000000e0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_MBHC_SCALING_MUX_1 (0x14E) +#define SITAR_A_MBHC_SCALING_MUX_1__POR (0x00000000) +#define SITAR_A_MBHC_SCALING_MUX_2 (0x14F) +#define SITAR_A_MBHC_SCALING_MUX_2__POR (0x00000080) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_TX_SUP_SWITCH_CTRL_1 (0x151) +#define SITAR_A_TX_SUP_SWITCH_CTRL_1__POR (0x00000000) +#define SITAR_A_TX_SUP_SWITCH_CTRL_2 (0x152) +#define SITAR_A_TX_SUP_SWITCH_CTRL_2__POR (0x00000080) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_TX_1_2_EN (0x153) +#define SITAR_A_TX_1_2_EN__POR (0x00000000) +#define SITAR_A_TX_1_2_TEST_EN (0x154) +#define SITAR_A_TX_1_2_TEST_EN__POR (0x000000cc) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_TX_1_2_ADC_CH1 (0x155) +#define SITAR_A_TX_1_2_ADC_CH1__POR (0x00000044) +#define SITAR_A_TX_1_2_ADC_CH2 (0x156) +#define SITAR_A_TX_1_2_ADC_CH2__POR (0x00000044) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_TX_1_2_ATEST_REFCTRL (0x157) +#define SITAR_A_TX_1_2_ATEST_REFCTRL__POR (0x00000000) +#define SITAR_A_TX_1_2_TEST_CTL (0x158) +#define SITAR_A_TX_1_2_TEST_CTL__POR (0x00000038) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_TX_1_2_TEST_BLOCK_EN (0x159) +#define SITAR_A_TX_1_2_TEST_BLOCK_EN__POR (0x000000fc) +#define SITAR_A_TX_1_2_TXFE_CLKDIV (0x15A) +#define SITAR_A_TX_1_2_TXFE_CLKDIV__POR (0x000000ee) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_TX_1_2_SAR_ERR_CH1 (0x15B) +#define SITAR_A_TX_1_2_SAR_ERR_CH1__POR (0x00000000) +#define SITAR_A_TX_1_2_SAR_ERR_CH2 (0x15C) +#define SITAR_A_TX_1_2_SAR_ERR_CH2__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_TX_3_EN (0x15D) +#define SITAR_A_TX_3_EN__POR (0x00000000) +#define SITAR_A_TX_3_TEST_EN (0x15E) +#define SITAR_A_TX_3_TEST_EN__POR (0x000000cc) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_TX_3_ADC (0x15F) +#define SITAR_A_TX_3_ADC__POR (0x00000044) +#define SITAR_A_TX_3_MBHC_ATEST_REFCTRL (0x161) +#define SITAR_A_TX_3_MBHC_ATEST_REFCTRL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_TX_3_TEST_CTL (0x162) +#define SITAR_A_TX_3_TEST_CTL__POR (0x00000038) +#define SITAR_A_TX_3_TEST_BLOCK_EN (0x163) +#define SITAR_A_TX_3_TEST_BLOCK_EN__POR (0x000000fc) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_TX_3_TXFE_CKDIV (0x164) +#define SITAR_A_TX_3_TXFE_CKDIV__POR (0x000000ee) +#define SITAR_A_TX_3_SAR_ERR (0x165) +#define SITAR_A_TX_3_SAR_ERR__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_TX_4_MBHC_EN (0x171) +#define SITAR_A_TX_4_MBHC_EN__POR (0x0000000c) +#define SITAR_A_TX_4_MBHC_ADC (0x173) +#define SITAR_A_TX_4_MBHC_ADC__POR (0x00000044) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_TX_4_MBHC_TEST_CTL (0x174) +#define SITAR_A_TX_4_MBHC_TEST_CTL__POR (0x00000038) +#define SITAR_A_TX_4_MBHC_SAR_ERR (0x175) +#define SITAR_A_TX_4_MBHC_SAR_ERR__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_TX_4_TXFE_CLKDIV (0x176) +#define SITAR_A_TX_4_TXFE_CLKDIV__POR (0x0000001c) +#define SITAR_A_AUX_COM_CTL (0x180) +#define SITAR_A_AUX_COM_CTL__POR (0x00000034) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_AUX_COM_ATEST (0x181) +#define SITAR_A_AUX_COM_ATEST__POR (0x00000000) +#define SITAR_A_AUX_L_EN (0x182) +#define SITAR_A_AUX_L_EN__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_AUX_L_GAIN (0x183) +#define SITAR_A_AUX_L_GAIN__POR (0x0000001f) +#define SITAR_A_AUX_L_PA_CONN (0x184) +#define SITAR_A_AUX_L_PA_CONN__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_AUX_L_PA_CONN_INV (0x185) +#define SITAR_A_AUX_L_PA_CONN_INV__POR (0x00000000) +#define SITAR_A_AUX_R_EN (0x186) +#define SITAR_A_AUX_R_EN__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_AUX_R_GAIN (0x187) +#define SITAR_A_AUX_R_GAIN__POR (0x0000001f) +#define SITAR_A_AUX_R_PA_CONN (0x188) +#define SITAR_A_AUX_R_PA_CONN__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_AUX_R_PA_CONN_INV (0x189) +#define SITAR_A_AUX_R_PA_CONN_INV__POR (0x00000000) +#define SITAR_A_CP_EN (0x192) +#define SITAR_A_CP_EN__POR (0x000000e6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CP_CLK (0x193) +#define SITAR_A_CP_CLK__POR (0x00000029) +#define SITAR_A_CP_STATIC (0x194) +#define SITAR_A_CP_STATIC__POR (0x00000010) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CP_DCC1 (0x195) +#define SITAR_A_CP_DCC1__POR (0x00000052) +#define SITAR_A_CP_DCC3 (0x196) +#define SITAR_A_CP_DCC3__POR (0x00000001) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CP_ATEST (0x197) +#define SITAR_A_CP_ATEST__POR (0x00000000) +#define SITAR_A_CP_DTEST (0x198) +#define SITAR_A_CP_DTEST__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_COM_TIMER_DIV (0x19E) +#define SITAR_A_RX_COM_TIMER_DIV__POR (0x000000e8) +#define SITAR_A_RX_COM_OCP_CTL (0x19F) +#define SITAR_A_RX_COM_OCP_CTL__POR (0x0000001f) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_COM_OCP_COUNT (0x1A0) +#define SITAR_A_RX_COM_OCP_COUNT__POR (0x00000077) +#define SITAR_A_RX_COM_DAC_CTL (0x1A1) +#define SITAR_A_RX_COM_DAC_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_COM_BIAS (0x1A2) +#define SITAR_A_RX_COM_BIAS__POR (0x00000000) +#define SITAR_A_RX_HPH_BIAS_PA (0x1A6) +#define SITAR_A_RX_HPH_BIAS_PA__POR (0x00000057) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_HPH_BIAS_LDO (0x1A7) +#define SITAR_A_RX_HPH_BIAS_LDO__POR (0x00000056) +#define SITAR_A_RX_HPH_BIAS_CNP (0x1A8) +#define SITAR_A_RX_HPH_BIAS_CNP__POR (0x0000008a) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_HPH_BIAS_WG (0x1A9) +#define SITAR_A_RX_HPH_BIAS_WG__POR (0x00000060) +#define SITAR_A_RX_HPH_OCP_CTL (0x1AA) +#define SITAR_A_RX_HPH_OCP_CTL__POR (0x000000e8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_HPH_CNP_EN (0x1AB) +#define SITAR_A_RX_HPH_CNP_EN__POR (0x00000080) +#define SITAR_A_RX_HPH_CNP_WG_CTL (0x1AC) +#define SITAR_A_RX_HPH_CNP_WG_CTL__POR (0x000000dc) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_HPH_CNP_WG_TIME (0x1AD) +#define SITAR_A_RX_HPH_CNP_WG_TIME__POR (0x00000028) +#define SITAR_A_RX_HPH_L_GAIN (0x1AE) +#define SITAR_A_RX_HPH_L_GAIN__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_HPH_L_TEST (0x1AF) +#define SITAR_A_RX_HPH_L_TEST__POR (0x00000001) +#define SITAR_A_RX_HPH_L_PA_CTL (0x1B0) +#define SITAR_A_RX_HPH_L_PA_CTL__POR (0x00000040) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_HPH_L_DAC_CTL (0x1B1) +#define SITAR_A_RX_HPH_L_DAC_CTL__POR (0x00000000) +#define SITAR_A_RX_HPH_L_ATEST (0x1B2) +#define SITAR_A_RX_HPH_L_ATEST__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_HPH_L_STATUS (0x1B3) +#define SITAR_A_RX_HPH_L_STATUS__POR (0x00000004) +#define SITAR_A_RX_HPH_R_GAIN (0x1B4) +#define SITAR_A_RX_HPH_R_GAIN__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_HPH_R_TEST (0x1B5) +#define SITAR_A_RX_HPH_R_TEST__POR (0x00000001) +#define SITAR_A_RX_HPH_R_PA_CTL (0x1B6) +#define SITAR_A_RX_HPH_R_PA_CTL__POR (0x00000040) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_HPH_R_DAC_CTL (0x1B7) +#define SITAR_A_RX_HPH_R_DAC_CTL__POR (0x00000000) +#define SITAR_A_RX_HPH_R_ATEST (0x1B8) +#define SITAR_A_RX_HPH_R_ATEST__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_HPH_R_STATUS (0x1B9) +#define SITAR_A_RX_HPH_R_STATUS__POR (0x00000004) +#define SITAR_A_RX_EAR_BIAS_PA (0x1BA) +#define SITAR_A_RX_EAR_BIAS_PA__POR (0x000000a6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_EAR_BIAS_CMBUFF (0x1BB) +#define SITAR_A_RX_EAR_BIAS_CMBUFF__POR (0x000000a0) +#define SITAR_A_RX_EAR_EN (0x1BC) +#define SITAR_A_RX_EAR_EN__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_EAR_GAIN (0x1BD) +#define SITAR_A_RX_EAR_GAIN__POR (0x00000002) +#define SITAR_A_RX_EAR_CMBUFF (0x1BE) +#define SITAR_A_RX_EAR_CMBUFF__POR (0x00000004) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_EAR_ICTL (0x1BF) +#define SITAR_A_RX_EAR_ICTL__POR (0x00000040) +#define SITAR_A_RX_EAR_CCOMP (0x1C0) +#define SITAR_A_RX_EAR_CCOMP__POR (0x00000008) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_EAR_VCM (0x1C1) +#define SITAR_A_RX_EAR_VCM__POR (0x00000003) +#define SITAR_A_RX_EAR_CNP (0x1C2) +#define SITAR_A_RX_EAR_CNP__POR (0x000000f2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_EAR_ATEST (0x1C3) +#define SITAR_A_RX_EAR_ATEST__POR (0x00000000) +#define SITAR_A_RX_EAR_STATUS (0x1C5) +#define SITAR_A_RX_EAR_STATUS__POR (0x00000004) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_LINE_BIAS_PA (0x1C6) +#define SITAR_A_RX_LINE_BIAS_PA__POR (0x000000aa) +#define SITAR_A_RX_LINE_BIAS_LDO (0x1C7) +#define SITAR_A_RX_LINE_BIAS_LDO__POR (0x00000086) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_LINE_BIAS_CNP1 (0x1C8) +#define SITAR_A_RX_LINE_BIAS_CNP1__POR (0x00000060) +#define SITAR_A_RX_LINE_COM (0x1C9) +#define SITAR_A_RX_LINE_COM__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_LINE_CNP_EN (0x1CA) +#define SITAR_A_RX_LINE_CNP_EN__POR (0x00000080) +#define SITAR_A_RX_LINE_CNP_WG_CTL (0x1CB) +#define SITAR_A_RX_LINE_CNP_WG_CTL__POR (0x000000dc) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_LINE_CNP_WG_TIME (0x1CC) +#define SITAR_A_RX_LINE_CNP_WG_TIME__POR (0x00000028) +#define SITAR_A_RX_LINE_1_GAIN (0x1CD) +#define SITAR_A_RX_LINE_1_GAIN__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_LINE_1_TEST (0x1CE) +#define SITAR_A_RX_LINE_1_TEST__POR (0x00000001) +#define SITAR_A_RX_LINE_1_DAC_CTL (0x1CF) +#define SITAR_A_RX_LINE_1_DAC_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_LINE_1_STATUS (0x1D0) +#define SITAR_A_RX_LINE_1_STATUS__POR (0x00000004) +#define SITAR_A_RX_LINE_2_GAIN (0x1D1) +#define SITAR_A_RX_LINE_2_GAIN__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_LINE_2_TEST (0x1D2) +#define SITAR_A_RX_LINE_2_TEST__POR (0x00000001) +#define SITAR_A_RX_LINE_2_DAC_CTL (0x1D3) +#define SITAR_A_RX_LINE_2_DAC_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_LINE_2_STATUS (0x1D4) +#define SITAR_A_RX_LINE_2_STATUS__POR (0x00000004) +#define SITAR_A_RX_LINE_BIAS_CNP2 (0x1E1) +#define SITAR_A_RX_LINE_BIAS_CNP2__POR (0x0000008a) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_LINE_OCP_CTL (0x1E2) +#define SITAR_A_RX_LINE_OCP_CTL__POR (0x000000e8) +#define SITAR_A_RX_LINE_1_PA_CTL (0x1E3) +#define SITAR_A_RX_LINE_1_PA_CTL__POR (0x00000040) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RX_LINE_2_PA_CTL (0x1E4) +#define SITAR_A_RX_LINE_2_PA_CTL__POR (0x00000040) +#define SITAR_A_RX_LINE_CNP_DBG (0x1EC) +#define SITAR_A_RX_LINE_CNP_DBG__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_MBHC_HPH (0x1ED) +#define SITAR_A_MBHC_HPH__POR (0x00000048) +#define SITAR_A_RC_OSC_FREQ (0x1F7) +#define SITAR_A_RC_OSC_FREQ__POR (0x00000046) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RC_OSC_TEST (0x1F8) +#define SITAR_A_RC_OSC_TEST__POR (0x0000000a) +#define SITAR_A_RC_OSC_STATUS (0x1F9) +#define SITAR_A_RC_OSC_STATUS__POR (0x0000001c) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_RC_OSC_TUNER (0x1FA) +#define SITAR_A_RC_OSC_TUNER__POR (0x00000000) +#define SITAR_A_CDC_ANC1_CTL (0x200) +#define SITAR_A_CDC_ANC1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_ANC1_SHIFT (0x201) +#define SITAR_A_CDC_ANC1_SHIFT__POR (0x00000000) +#define SITAR_A_CDC_ANC1_IIR_B1_CTL (0x202) +#define SITAR_A_CDC_ANC1_IIR_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_ANC1_IIR_B2_CTL (0x203) +#define SITAR_A_CDC_ANC1_IIR_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_ANC1_IIR_B3_CTL (0x204) +#define SITAR_A_CDC_ANC1_IIR_B3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_ANC1_IIR_B4_CTL (0x205) +#define SITAR_A_CDC_ANC1_IIR_B4_CTL__POR (0x00000000) +#define SITAR_A_CDC_ANC1_LPF_B1_CTL (0x206) +#define SITAR_A_CDC_ANC1_LPF_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_ANC1_LPF_B2_CTL (0x207) +#define SITAR_A_CDC_ANC1_LPF_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_ANC1_LPF_B3_CTL (0x208) +#define SITAR_A_CDC_ANC1_LPF_B3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_ANC1_SPARE (0x209) +#define SITAR_A_CDC_ANC1_SPARE__POR (0x00000000) +#define SITAR_A_CDC_ANC1_SMLPF_CTL (0x20A) +#define SITAR_A_CDC_ANC1_SMLPF_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_ANC1_DCFLT_CTL (0x20B) +#define SITAR_A_CDC_ANC1_DCFLT_CTL__POR (0x00000000) +#define SITAR_A_CDC_TX1_VOL_CTL_TIMER (0x220) +#define SITAR_A_CDC_TX1_VOL_CTL_TIMER__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_TX1_VOL_CTL_GAIN (0x221) +#define SITAR_A_CDC_TX1_VOL_CTL_GAIN__POR (0x00000000) +#define SITAR_A_CDC_TX2_VOL_CTL_GAIN (0x229) +#define SITAR_A_CDC_TX2_VOL_CTL_GAIN__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_TX3_VOL_CTL_GAIN (0x231) +#define SITAR_A_CDC_TX3_VOL_CTL_GAIN__POR (0x00000000) +#define SITAR_A_CDC_TX4_VOL_CTL_GAIN (0x239) +#define SITAR_A_CDC_TX4_VOL_CTL_GAIN__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_TX5_VOL_CTL_GAIN (0x241) +#define SITAR_A_CDC_TX5_VOL_CTL_GAIN__POR (0x00000000) +#define SITAR_A_CDC_TX1_VOL_CTL_CFG (0x222) +#define SITAR_A_CDC_TX1_VOL_CTL_CFG__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_TX2_VOL_CTL_CFG (0x22A) +#define SITAR_A_CDC_TX2_VOL_CTL_CFG__POR (0x00000000) +#define SITAR_A_CDC_TX3_VOL_CTL_CFG (0x232) +#define SITAR_A_CDC_TX3_VOL_CTL_CFG__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_TX4_VOL_CTL_CFG (0x23A) +#define SITAR_A_CDC_TX4_VOL_CTL_CFG__POR (0x00000000) +#define SITAR_A_CDC_TX1_MUX_CTL (0x223) +#define SITAR_A_CDC_TX1_MUX_CTL__POR (0x00000008) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_TX1_CLK_FS_CTL (0x00000224) +#define SITAR_A_CDC_TX1_CLK_FS_CTL__POR (0x00000003) +#define SITAR_A_CDC_TX2_CLK_FS_CTL (0x0000022C) +#define SITAR_A_CDC_TX2_CLK_FS_CTL__POR (0x00000003) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_TX3_CLK_FS_CTL (0x00000234) +#define SITAR_A_CDC_TX3_CLK_FS_CTL__POR (0x00000003) +#define SITAR_A_CDC_TX4_CLK_FS_CTL (0x0000023C) +#define SITAR_A_CDC_TX4_CLK_FS_CTL__POR (0x00000003) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_TX1_DMIC_CTL (0x225) +#define SITAR_A_CDC_TX1_DMIC_CTL__POR (0x00000000) +#define SITAR_A_CDC_TX2_MUX_CTL (0x22B) +#define SITAR_A_CDC_TX2_MUX_CTL__POR (0x00000008) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_TX3_MUX_CTL (0x233) +#define SITAR_A_CDC_TX3_MUX_CTL__POR (0x00000008) +#define SITAR_A_CDC_TX4_MUX_CTL (0x23B) +#define SITAR_A_CDC_TX4_MUX_CTL__POR (0x00000008) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_TX5_MUX_CTL (0x243) +#define SITAR_A_CDC_TX5_MUX_CTL__POR (0x00000008) +#define SITAR_A_CDC_SRC1_PDA_CFG (0x2A0) +#define SITAR_A_CDC_SRC1_PDA_CFG__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_SRC1_FS_CTL (0x2A1) +#define SITAR_A_CDC_SRC1_FS_CTL__POR (0x0000001b) +#define SITAR_A_CDC_RX1_B1_CTL (0x000002B0) +#define SITAR_A_CDC_RX1_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_RX2_B1_CTL (0x000002B8) +#define SITAR_A_CDC_RX2_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_RX3_B1_CTL (0x000002C0) +#define SITAR_A_CDC_RX3_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_RX1_B2_CTL (0x000002B1) +#define SITAR_A_CDC_RX1_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_RX2_B2_CTL (0x000002B9) +#define SITAR_A_CDC_RX2_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_RX3_B2_CTL (0x000002C1) +#define SITAR_A_CDC_RX3_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_RX1_B3_CTL (0x000002B2) +#define SITAR_A_CDC_RX1_B3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_RX2_B3_CTL (0x000002BA) +#define SITAR_A_CDC_RX2_B3_CTL__POR (0x00000000) +#define SITAR_A_CDC_RX3_B3_CTL (0x000002C2) +#define SITAR_A_CDC_RX3_B3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_RX1_B4_CTL (0x000002B3) +#define SITAR_A_CDC_RX1_B4_CTL__POR (0x00000000) +#define SITAR_A_CDC_RX2_B4_CTL (0x000002BB) +#define SITAR_A_CDC_RX2_B4_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_RX3_B4_CTL (0x000002C3) +#define SITAR_A_CDC_RX3_B4_CTL__POR (0x00000000) +#define SITAR_A_CDC_RX1_B5_CTL (0x000002B4) +#define SITAR_A_CDC_RX1_B5_CTL__POR (0x00000078) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_RX2_B5_CTL (0x000002BC) +#define SITAR_A_CDC_RX2_B5_CTL__POR (0x00000078) +#define SITAR_A_CDC_RX3_B5_CTL (0x000002C4) +#define SITAR_A_CDC_RX3_B5_CTL__POR (0x00000078) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_RX1_B6_CTL (0x000002B5) +#define SITAR_A_CDC_RX1_B6_CTL__POR (0x00000080) +#define SITAR_A_CDC_RX2_B6_CTL (0x000002BD) +#define SITAR_A_CDC_RX2_B6_CTL__POR (0x00000080) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_RX3_B6_CTL (0x000002C5) +#define SITAR_A_CDC_RX3_B6_CTL__POR (0x00000080) +#define SITAR_A_CDC_RX1_VOL_CTL_B1_CTL (0x2B6) +#define SITAR_A_CDC_RX1_VOL_CTL_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_RX1_VOL_CTL_B2_CTL (0x2B7) +#define SITAR_A_CDC_RX1_VOL_CTL_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_RX2_VOL_CTL_B2_CTL (0x2BF) +#define SITAR_A_CDC_RX2_VOL_CTL_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_RX3_VOL_CTL_B2_CTL (0x2C7) +#define SITAR_A_CDC_RX3_VOL_CTL_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLK_ANC_RESET_CTL (0x300) +#define SITAR_A_CDC_CLK_ANC_RESET_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CLK_RX_RESET_CTL (0x301) +#define SITAR_A_CDC_CLK_RX_RESET_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLK_TX_RESET_B1_CTL (0x302) +#define SITAR_A_CDC_CLK_TX_RESET_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CLK_TX_RESET_B2_CTL (0x303) +#define SITAR_A_CDC_CLK_TX_RESET_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLK_DMIC_CTL (0x304) +#define SITAR_A_CDC_CLK_DMIC_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CLK_RX_I2S_CTL (0x305) +#define SITAR_A_CDC_CLK_RX_I2S_CTL__POR (0x00000003) +#define SITAR_A_CDC_CLK_TX_I2S_CTL (0x306) +#define SITAR_A_CDC_CLK_TX_I2S_CTL__POR (0x00000003) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CLK_OTHR_RESET_CTL (0x307) +#define SITAR_A_CDC_CLK_OTHR_RESET_CTL__POR (0x00000010) +#define SITAR_A_CDC_CLK_TX_CLK_EN_B1_CTL (0x308) +#define SITAR_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CLK_OTHR_CTL (0x30A) +#define SITAR_A_CDC_CLK_OTHR_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLK_RDAC_CLK_EN_CTL (0x30B) +#define SITAR_A_CDC_CLK_RDAC_CLK_EN_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CLK_ANC_CLK_EN_CTL (0x30C) +#define SITAR_A_CDC_CLK_ANC_CLK_EN_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLK_RX_B1_CTL (0x30D) +#define SITAR_A_CDC_CLK_RX_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CLK_RX_B2_CTL (0x30E) +#define SITAR_A_CDC_CLK_RX_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLK_MCLK_CTL (0x30F) +#define SITAR_A_CDC_CLK_MCLK_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CLK_PDM_CTL (0x310) +#define SITAR_A_CDC_CLK_PDM_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLK_SD_CTL (0x311) +#define SITAR_A_CDC_CLK_SD_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CLK_LP_CTL (0x312) +#define SITAR_A_CDC_CLK_LP_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLSG_FREQ_THRESH_B1_CTL (0x320) +#define SITAR_A_CDC_CLSG_FREQ_THRESH_B1_CTL__POR (0x00000007) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CLSG_FREQ_THRESH_B2_CTL (0x321) +#define SITAR_A_CDC_CLSG_FREQ_THRESH_B2_CTL__POR (0x00000013) +#define SITAR_A_CDC_CLSG_FREQ_THRESH_B3_CTL (0x322) +#define SITAR_A_CDC_CLSG_FREQ_THRESH_B3_CTL__POR (0x0000001b) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CLSG_FREQ_THRESH_B4_CTL (0x323) +#define SITAR_A_CDC_CLSG_FREQ_THRESH_B4_CTL__POR (0x0000007f) +#define SITAR_A_CDC_CLSG_GAIN_THRESH_CTL (0x324) +#define SITAR_A_CDC_CLSG_GAIN_THRESH_CTL__POR (0x00000026) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CLSG_TIMER_B1_CFG (0x325) +#define SITAR_A_CDC_CLSG_TIMER_B1_CFG__POR (0x0000000a) +#define SITAR_A_CDC_CLSG_TIMER_B2_CFG (0x326) +#define SITAR_A_CDC_CLSG_TIMER_B2_CFG__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CLSG_CTL (0x327) +#define SITAR_A_CDC_CLSG_CTL__POR (0x00000013) +#define SITAR_A_CDC_IIR1_GAIN_B1_CTL (0x340) +#define SITAR_A_CDC_IIR1_GAIN_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_IIR1_GAIN_B2_CTL (0x341) +#define SITAR_A_CDC_IIR1_GAIN_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR1_GAIN_B3_CTL (0x342) +#define SITAR_A_CDC_IIR1_GAIN_B3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_IIR1_GAIN_B4_CTL (0x343) +#define SITAR_A_CDC_IIR1_GAIN_B4_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR1_GAIN_B5_CTL (0x344) +#define SITAR_A_CDC_IIR1_GAIN_B5_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_IIR1_GAIN_B6_CTL (0x345) +#define SITAR_A_CDC_IIR1_GAIN_B6_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR1_GAIN_B7_CTL (0x346) +#define SITAR_A_CDC_IIR1_GAIN_B7_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_IIR1_GAIN_B8_CTL (0x347) +#define SITAR_A_CDC_IIR1_GAIN_B8_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR1_CTL (0x348) +#define SITAR_A_CDC_IIR1_CTL__POR (0x00000040) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_IIR1_GAIN_TIMER_CTL (0x349) +#define SITAR_A_CDC_IIR1_GAIN_TIMER_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR1_COEF_B1_CTL (0x34A) +#define SITAR_A_CDC_IIR1_COEF_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_IIR1_COEF_B2_CTL (0x34B) +#define SITAR_A_CDC_IIR1_COEF_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR1_COEF_B3_CTL (0x34C) +#define SITAR_A_CDC_IIR1_COEF_B3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_IIR1_COEF_B4_CTL (0x34D) +#define SITAR_A_CDC_IIR1_COEF_B4_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR1_COEF_B5_CTL (0x34E) +#define SITAR_A_CDC_IIR1_COEF_B5_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_IIR2_GAIN_B1_CTL (0x350) +#define SITAR_A_CDC_IIR2_GAIN_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR2_GAIN_B2_CTL (0x351) +#define SITAR_A_CDC_IIR2_GAIN_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_IIR2_GAIN_B3_CTL (0x352) +#define SITAR_A_CDC_IIR2_GAIN_B3_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR2_GAIN_B4_CTL (0x353) +#define SITAR_A_CDC_IIR2_GAIN_B4_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_IIR2_GAIN_B5_CTL (0x354) +#define SITAR_A_CDC_IIR2_GAIN_B5_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR2_GAIN_B6_CTL (0x355) +#define SITAR_A_CDC_IIR2_GAIN_B6_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_IIR2_GAIN_B7_CTL (0x356) +#define SITAR_A_CDC_IIR2_GAIN_B7_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR2_GAIN_B8_CTL (0x357) +#define SITAR_A_CDC_IIR2_GAIN_B8_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_IIR2_CTL (0x358) +#define SITAR_A_CDC_IIR2_CTL__POR (0x00000040) +#define SITAR_A_CDC_IIR2_GAIN_TIMER_CTL (0x359) +#define SITAR_A_CDC_IIR2_GAIN_TIMER_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_IIR2_COEF_B1_CTL (0x35A) +#define SITAR_A_CDC_IIR2_COEF_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR2_COEF_B2_CTL (0x35B) +#define SITAR_A_CDC_IIR2_COEF_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_IIR2_COEF_B3_CTL (0x35C) +#define SITAR_A_CDC_IIR2_COEF_B3_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR2_COEF_B4_CTL (0x35D) +#define SITAR_A_CDC_IIR2_COEF_B4_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_IIR2_COEF_B5_CTL (0x35E) +#define SITAR_A_CDC_IIR2_COEF_B5_CTL__POR (0x00000000) +#define SITAR_A_CDC_TOP_GAIN_UPDATE (0x360) +#define SITAR_A_CDC_TOP_GAIN_UPDATE__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_TOP_RDAC_DOUT_CTL (0x361) +#define SITAR_A_CDC_TOP_RDAC_DOUT_CTL__POR (0x00000000) +#define SITAR_A_CDC_DEBUG_B1_CTL (0x368) +#define SITAR_A_CDC_DEBUG_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_DEBUG_B2_CTL (0x369) +#define SITAR_A_CDC_DEBUG_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_DEBUG_B3_CTL (0x36A) +#define SITAR_A_CDC_DEBUG_B3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_DEBUG_B4_CTL (0x36B) +#define SITAR_A_CDC_DEBUG_B4_CTL__POR (0x00000000) +#define SITAR_A_CDC_DEBUG_B5_CTL (0x36C) +#define SITAR_A_CDC_DEBUG_B5_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_DEBUG_B6_CTL (0x36D) +#define SITAR_A_CDC_DEBUG_B6_CTL__POR (0x00000000) +#define SITAR_A_CDC_DEBUG_B7_CTL (0x36E) +#define SITAR_A_CDC_DEBUG_B7_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_COMP1_B1_CTL (0x370) +#define SITAR_A_CDC_COMP1_B1_CTL__POR (0x00000030) +#define SITAR_A_CDC_COMP1_B2_CTL (0x371) +#define SITAR_A_CDC_COMP1_B2_CTL__POR (0x000000b5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_COMP1_B3_CTL (0x372) +#define SITAR_A_CDC_COMP1_B3_CTL__POR (0x00000028) +#define SITAR_A_CDC_COMP1_B4_CTL (0x373) +#define SITAR_A_CDC_COMP1_B4_CTL__POR (0x0000003c) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_COMP1_B5_CTL (0x374) +#define SITAR_A_CDC_COMP1_B5_CTL__POR (0x0000001f) +#define SITAR_A_CDC_COMP1_B6_CTL (0x375) +#define SITAR_A_CDC_COMP1_B6_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_COMP1_SHUT_DOWN_STATUS (0x376) +#define SITAR_A_CDC_COMP1_SHUT_DOWN_STATUS__POR (0x00000003) +#define SITAR_A_CDC_COMP1_FS_CFG (0x377) +#define SITAR_A_CDC_COMP1_FS_CFG__POR (0x0000001b) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CONN_RX1_B1_CTL (0x380) +#define SITAR_A_CDC_CONN_RX1_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_RX1_B2_CTL (0x381) +#define SITAR_A_CDC_CONN_RX1_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CONN_RX1_B3_CTL (0x382) +#define SITAR_A_CDC_CONN_RX1_B3_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_RX2_B1_CTL (0x383) +#define SITAR_A_CDC_CONN_RX2_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CONN_RX2_B2_CTL (0x384) +#define SITAR_A_CDC_CONN_RX2_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_RX2_B3_CTL (0x385) +#define SITAR_A_CDC_CONN_RX2_B3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CONN_RX3_B1_CTL (0x386) +#define SITAR_A_CDC_CONN_RX3_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_RX3_B2_CTL (0x387) +#define SITAR_A_CDC_CONN_RX3_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CONN_RX3_B3_CTL (0x388) +#define SITAR_A_CDC_CONN_RX3_B3_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_ANC_B1_CTL (0x391) +#define SITAR_A_CDC_CONN_ANC_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CONN_ANC_B2_CTL (0x392) +#define SITAR_A_CDC_CONN_ANC_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_TX_B1_CTL (0x393) +#define SITAR_A_CDC_CONN_TX_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CONN_TX_B2_CTL (0x394) +#define SITAR_A_CDC_CONN_TX_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_EQ1_B1_CTL (0x397) +#define SITAR_A_CDC_CONN_EQ1_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CONN_EQ1_B2_CTL (0x398) +#define SITAR_A_CDC_CONN_EQ1_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_EQ1_B3_CTL (0x399) +#define SITAR_A_CDC_CONN_EQ1_B3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CONN_EQ1_B4_CTL (0x39A) +#define SITAR_A_CDC_CONN_EQ1_B4_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_EQ2_B1_CTL (0x39B) +#define SITAR_A_CDC_CONN_EQ2_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CONN_EQ2_B2_CTL (0x39C) +#define SITAR_A_CDC_CONN_EQ2_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_EQ2_B3_CTL (0x39D) +#define SITAR_A_CDC_CONN_EQ2_B3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CONN_EQ2_B4_CTL (0x39E) +#define SITAR_A_CDC_CONN_EQ2_B4_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_SRC1_B1_CTL (0x39F) +#define SITAR_A_CDC_CONN_SRC1_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CONN_SRC1_B2_CTL (0x3A0) +#define SITAR_A_CDC_CONN_SRC1_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_SRC2_B1_CTL (0x3A1) +#define SITAR_A_CDC_CONN_SRC2_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CONN_SRC2_B2_CTL (0x3A2) +#define SITAR_A_CDC_CONN_SRC2_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_TX_SB_B1_CTL (0x3A3) +#define SITAR_A_CDC_CONN_TX_SB_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CONN_TX_SB_B2_CTL (0x3A4) +#define SITAR_A_CDC_CONN_TX_SB_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_TX_SB_B3_CTL (0x3A5) +#define SITAR_A_CDC_CONN_TX_SB_B3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CONN_TX_SB_B4_CTL (0x3A6) +#define SITAR_A_CDC_CONN_TX_SB_B4_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_TX_SB_B5_CTL (0x3A7) +#define SITAR_A_CDC_CONN_TX_SB_B5_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CONN_RX_SB_B1_CTL (0x3AE) +#define SITAR_A_CDC_CONN_RX_SB_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_RX_SB_B2_CTL (0x3AF) +#define SITAR_A_CDC_CONN_RX_SB_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_CONN_CLSG_CTL (0x3B0) +#define SITAR_A_CDC_CONN_CLSG_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_SPARE (0x3B1) +#define SITAR_A_CDC_CONN_SPARE__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_MBHC_EN_CTL (0x3C0) +#define SITAR_A_CDC_MBHC_EN_CTL__POR (0x00000000) +#define SITAR_A_CDC_MBHC_FIR_B1_CFG (0x3C1) +#define SITAR_A_CDC_MBHC_FIR_B1_CFG__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_MBHC_FIR_B2_CFG (0x3C2) +#define SITAR_A_CDC_MBHC_FIR_B2_CFG__POR (0x00000006) +#define SITAR_A_CDC_MBHC_TIMER_B1_CTL (0x3C3) +#define SITAR_A_CDC_MBHC_TIMER_B1_CTL__POR (0x00000003) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_MBHC_TIMER_B2_CTL (0x3C4) +#define SITAR_A_CDC_MBHC_TIMER_B2_CTL__POR (0x00000009) +#define SITAR_A_CDC_MBHC_TIMER_B3_CTL (0x3C5) +#define SITAR_A_CDC_MBHC_TIMER_B3_CTL__POR (0x0000001e) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_MBHC_TIMER_B4_CTL (0x3C6) +#define SITAR_A_CDC_MBHC_TIMER_B4_CTL__POR (0x00000045) +#define SITAR_A_CDC_MBHC_TIMER_B5_CTL (0x3C7) +#define SITAR_A_CDC_MBHC_TIMER_B5_CTL__POR (0x00000004) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_MBHC_TIMER_B6_CTL (0x3C8) +#define SITAR_A_CDC_MBHC_TIMER_B6_CTL__POR (0x00000078) +#define SITAR_A_CDC_MBHC_B1_STATUS (0x3C9) +#define SITAR_A_CDC_MBHC_B1_STATUS__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_MBHC_B2_STATUS (0x3CA) +#define SITAR_A_CDC_MBHC_B2_STATUS__POR (0x00000000) +#define SITAR_A_CDC_MBHC_B3_STATUS (0x3CB) +#define SITAR_A_CDC_MBHC_B3_STATUS__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_MBHC_B4_STATUS (0x3CC) +#define SITAR_A_CDC_MBHC_B4_STATUS__POR (0x00000000) +#define SITAR_A_CDC_MBHC_B5_STATUS (0x3CD) +#define SITAR_A_CDC_MBHC_B5_STATUS__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_MBHC_B1_CTL (0x3CE) +#define SITAR_A_CDC_MBHC_B1_CTL__POR (0x000000c0) +#define SITAR_A_CDC_MBHC_B2_CTL (0x3CF) +#define SITAR_A_CDC_MBHC_B2_CTL__POR (0x0000005d) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_MBHC_VOLT_B1_CTL (0x3D0) +#define SITAR_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_MBHC_VOLT_B2_CTL (0x3D1) +#define SITAR_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_MBHC_VOLT_B3_CTL (0x3D2) +#define SITAR_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00000000) +#define SITAR_A_CDC_MBHC_VOLT_B4_CTL (0x3D3) +#define SITAR_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_MBHC_VOLT_B5_CTL (0x3D4) +#define SITAR_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00000000) +#define SITAR_A_CDC_MBHC_VOLT_B6_CTL (0x3D5) +#define SITAR_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_MBHC_VOLT_B7_CTL (0x3D6) +#define SITAR_A_CDC_MBHC_VOLT_B7_CTL__POR (0x000000ff) +#define SITAR_A_CDC_MBHC_VOLT_B8_CTL (0x3D7) +#define SITAR_A_CDC_MBHC_VOLT_B8_CTL__POR (0x00000007) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_MBHC_VOLT_B9_CTL (0x3D8) +#define SITAR_A_CDC_MBHC_VOLT_B9_CTL__POR (0x000000ff) +#define SITAR_A_CDC_MBHC_VOLT_B10_CTL (0x3D9) +#define SITAR_A_CDC_MBHC_VOLT_B10_CTL__POR (0x0000007f) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_MBHC_VOLT_B11_CTL (0x3DA) +#define SITAR_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00000000) +#define SITAR_A_CDC_MBHC_VOLT_B12_CTL (0x3DB) +#define SITAR_A_CDC_MBHC_VOLT_B12_CTL__POR (0x00000080) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_MBHC_CLK_CTL (0x3DC) +#define SITAR_A_CDC_MBHC_CLK_CTL__POR (0x00000000) +#define SITAR_A_CDC_MBHC_INT_CTL (0x3DD) +#define SITAR_A_CDC_MBHC_INT_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_A_CDC_MBHC_DEBUG_CTL (0x3DE) +#define SITAR_A_CDC_MBHC_DEBUG_CTL__POR (0x00000000) +#define SITAR_A_CDC_MBHC_SPARE (0x3DF) +#define SITAR_A_CDC_MBHC_SPARE__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_SLIM_PGD_PORT_INT_EN0 (0x30) +#define SITAR_SLIM_PGD_PORT_INT_STATUS0 (0x34) +#define SITAR_SLIM_PGD_PORT_INT_CLR0 (0x38) +#define SITAR_SLIM_PGD_PORT_INT_SOURCE0 (0x60) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SITAR_PACKED_REG_SIZE sizeof(u32) +#define SITAR_CODEC_PACK_ENTRY(reg, mask, val) ((val & 0xff)| ((mask & 0xff) << 8)|((reg & 0xffff) << 16)) +#define SITAR_CODEC_UNPACK_ENTRY(packed, reg, mask, val) do { ((reg) = ((packed >> 16) & (0xffff))); ((mask) = ((packed >> 8) & (0xff))); ((val) = ((packed) & (0xff))); } while (0); +#endif +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + diff --git a/kernel-headers/linux/mfd/wcd9xxx/wcd9310_registers.h b/kernel-headers/linux/mfd/wcd9xxx/wcd9310_registers.h new file mode 100644 index 0000000..31c9252 --- /dev/null +++ b/kernel-headers/linux/mfd/wcd9xxx/wcd9310_registers.h @@ -0,0 +1,1381 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef TABLA_CODEC_DIGITAL_H +#define TABLA_CODEC_DIGITAL_H +#include <linux/mfd/wcd9xxx/wcd9xxx_registers.h> +#define TABLA_A_CHIP_CTL WCD9XXX_A_CHIP_CTL +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CHIP_CTL__POR WCD9XXX_A_CHIP_CTL__POR +#define TABLA_A_CHIP_STATUS WCD9XXX_A_CHIP_STATUS +#define TABLA_A_CHIP_STATUS__POR WCD9XXX_A_CHIP_STATUS__POR +#define TABLA_A_CHIP_ID_BYTE_0 WCD9XXX_A_CHIP_ID_BYTE_0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CHIP_ID_BYTE_0__POR WCD9XXX_A_CHIP_ID_BYTE_0__POR +#define TABLA_A_CHIP_ID_BYTE_1 WCD9XXX_A_CHIP_ID_BYTE_1 +#define TABLA_A_CHIP_ID_BYTE_1__POR WCD9XXX_A_CHIP_ID_BYTE_1__POR +#define TABLA_A_CHIP_ID_BYTE_2 WCD9XXX_A_CHIP_ID_BYTE_2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CHIP_ID_BYTE_2__POR WCD9XXX_A_CHIP_ID_BYTE_2__POR +#define TABLA_A_CHIP_ID_BYTE_3 WCD9XXX_A_CHIP_ID_BYTE_3 +#define TABLA_A_CHIP_ID_BYTE_3__POR WCD9XXX_A_CHIP_ID_BYTE_3__POR +#define TABLA_A_CHIP_VERSION WCD9XXX_A_CHIP_VERSION +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CHIP_VERSION__POR WCD9XXX_A_CHIP_VERSION__POR +#define TABLA_A_SB_VERSION WCD9XXX_A_SB_VERSION +#define TABLA_A_SB_VERSION__POR WCD9XXX_A_SB_VERSION__POR +#define TABLA_A_SLAVE_ID_1 WCD9XXX_A_SLAVE_ID_1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_SLAVE_ID_1__POR WCD9XXX_A_SLAVE_ID_1__POR +#define TABLA_A_SLAVE_ID_2 WCD9XXX_A_SLAVE_ID_2 +#define TABLA_A_SLAVE_ID_2__POR WCD9XXX_A_SLAVE_ID_2__POR +#define TABLA_A_SLAVE_ID_3 WCD9XXX_A_SLAVE_ID_3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_SLAVE_ID_3__POR WCD9XXX_A_SLAVE_ID_3__POR +#define TABLA_A_PIN_CTL_OE0 (0x10) +#define TABLA_A_PIN_CTL_OE0__POR (0x00000000) +#define TABLA_A_PIN_CTL_OE1 (0x11) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_PIN_CTL_OE1__POR (0x00000000) +#define TABLA_A_PIN_CTL_DATA0 (0x12) +#define TABLA_A_PIN_CTL_DATA0__POR (0x00000000) +#define TABLA_A_PIN_CTL_DATA1 (0x13) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_PIN_CTL_DATA1__POR (0x00000000) +#define TABLA_A_HDRIVE_GENERIC (0x18) +#define TABLA_A_HDRIVE_GENERIC__POR (0x00000000) +#define TABLA_A_HDRIVE_OVERRIDE (0x19) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_HDRIVE_OVERRIDE__POR (0x00000008) +#define TABLA_A_ANA_CSR_WAIT_STATE (0x20) +#define TABLA_A_ANA_CSR_WAIT_STATE__POR (0x00000044) +#define TABLA_A_PROCESS_MONITOR_CTL0 (0x40) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_PROCESS_MONITOR_CTL0__POR (0x00000080) +#define TABLA_A_PROCESS_MONITOR_CTL1 (0x41) +#define TABLA_A_PROCESS_MONITOR_CTL1__POR (0x00000000) +#define TABLA_A_PROCESS_MONITOR_CTL2 (0x42) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_PROCESS_MONITOR_CTL2__POR (0x00000000) +#define TABLA_A_PROCESS_MONITOR_CTL3 (0x43) +#define TABLA_A_PROCESS_MONITOR_CTL3__POR (0x00000001) +#define TABLA_A_QFUSE_CTL (0x48) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_QFUSE_CTL__POR (0x00000000) +#define TABLA_A_QFUSE_STATUS (0x49) +#define TABLA_A_QFUSE_STATUS__POR (0x00000000) +#define TABLA_A_QFUSE_DATA_OUT0 (0x4A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_QFUSE_DATA_OUT0__POR (0x00000000) +#define TABLA_A_QFUSE_DATA_OUT1 (0x4B) +#define TABLA_A_QFUSE_DATA_OUT1__POR (0x00000000) +#define TABLA_A_QFUSE_DATA_OUT2 (0x4C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_QFUSE_DATA_OUT2__POR (0x00000000) +#define TABLA_A_QFUSE_DATA_OUT3 (0x4D) +#define TABLA_A_QFUSE_DATA_OUT3__POR (0x00000000) +#define TABLA_A_CDC_CTL WCD9XXX_A_CDC_CTL +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CTL__POR WCD9XXX_A_CDC_CTL__POR +#define TABLA_A_LEAKAGE_CTL WCD9XXX_A_LEAKAGE_CTL +#define TABLA_A_LEAKAGE_CTL__POR WCD9XXX_A_LEAKAGE_CTL__POR +#define TABLA_A_INTR_MODE (0x90) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_INTR_MODE__POR (0x00000000) +#define TABLA_A_INTR_MASK0 (0x94) +#define TABLA_A_INTR_MASK0__POR (0x000000ff) +#define TABLA_A_INTR_MASK1 (0x95) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_INTR_MASK1__POR (0x000000ff) +#define TABLA_A_INTR_MASK2 (0x96) +#define TABLA_A_INTR_MASK2__POR (0x000000ff) +#define TABLA_A_INTR_STATUS0 (0x98) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_INTR_STATUS0__POR (0x00000000) +#define TABLA_A_INTR_STATUS1 (0x99) +#define TABLA_A_INTR_STATUS1__POR (0x00000000) +#define TABLA_A_INTR_STATUS2 (0x9A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_INTR_STATUS2__POR (0x00000000) +#define TABLA_A_INTR_CLEAR0 (0x9C) +#define TABLA_A_INTR_CLEAR0__POR (0x00000000) +#define TABLA_A_INTR_CLEAR1 (0x9D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_INTR_CLEAR1__POR (0x00000000) +#define TABLA_A_INTR_CLEAR2 (0x9E) +#define TABLA_A_INTR_CLEAR2__POR (0x00000000) +#define TABLA_A_INTR_LEVEL0 (0xA0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_INTR_LEVEL0__POR (0x00000001) +#define TABLA_A_INTR_LEVEL1 (0xA1) +#define TABLA_A_INTR_LEVEL1__POR (0x00000000) +#define TABLA_A_INTR_LEVEL2 (0xA2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_INTR_LEVEL2__POR (0x00000000) +#define TABLA_A_INTR_TEST0 (0xA4) +#define TABLA_A_INTR_TEST0__POR (0x00000000) +#define TABLA_A_INTR_TEST1 (0xA5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_INTR_TEST1__POR (0x00000000) +#define TABLA_A_INTR_TEST2 (0xA6) +#define TABLA_A_INTR_TEST2__POR (0x00000000) +#define TABLA_A_INTR_SET0 (0xA8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_INTR_SET0__POR (0x00000000) +#define TABLA_A_INTR_SET1 (0xA9) +#define TABLA_A_INTR_SET1__POR (0x00000000) +#define TABLA_A_INTR_SET2 (0xAA) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_INTR_SET2__POR (0x00000000) +#define TABLA_A_CDC_TX_I2S_SCK_MODE (0xC0) +#define TABLA_A_CDC_TX_I2S_SCK_MODE__POR (0x00000000) +#define TABLA_A_CDC_TX_I2S_WS_MODE (0xC1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX_I2S_WS_MODE__POR (0x00000000) +#define TABLA_A_CDC_DMIC_DATA0_MODE (0xC4) +#define TABLA_A_CDC_DMIC_DATA0_MODE__POR (0x00000000) +#define TABLA_A_CDC_DMIC_CLK0_MODE (0xC5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_DMIC_CLK0_MODE__POR (0x00000000) +#define TABLA_A_CDC_DMIC_DATA1_MODE (0xC6) +#define TABLA_A_CDC_DMIC_DATA1_MODE__POR (0x00000000) +#define TABLA_A_CDC_DMIC_CLK1_MODE (0xC7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_DMIC_CLK1_MODE__POR (0x00000000) +#define TABLA_A_CDC_RX_I2S_SCK_MODE (0xC8) +#define TABLA_A_CDC_RX_I2S_SCK_MODE__POR (0x00000000) +#define TABLA_A_CDC_RX_I2S_WS_MODE (0xC9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX_I2S_WS_MODE__POR (0x00000000) +#define TABLA_A_CDC_DMIC_DATA2_MODE (0xCA) +#define TABLA_A_CDC_DMIC_DATA2_MODE__POR (0x00000000) +#define TABLA_A_CDC_DMIC_CLK2_MODE (0xCB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_DMIC_CLK2_MODE__POR (0x00000000) +#define TABLA_A_CDC_INTR_MODE (0xCC) +#define TABLA_A_CDC_INTR_MODE__POR (0x00000000) +#define TABLA_A_BIAS_REF_CTL (0x0100) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_BIAS_REF_CTL__POR (0x0000001C) +#define TABLA_A_BIAS_CENTRAL_BG_CTL (0x0101) +#define TABLA_A_BIAS_CENTRAL_BG_CTL__POR (0x00000050) +#define TABLA_A_BIAS_PRECHRG_CTL (0x0102) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_BIAS_PRECHRG_CTL__POR (0x00000007) +#define TABLA_A_BIAS_CURR_CTL_1 (0x0103) +#define TABLA_A_BIAS_CURR_CTL_1__POR (0x00000052) +#define TABLA_A_BIAS_CURR_CTL_2 (0x0104) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_BIAS_CURR_CTL_2__POR (0x00000000) +#define TABLA_A_BIAS_CONFIG_MODE_BG_CTL (0x0105) +#define TABLA_A_BIAS_CONFIG_MODE_BG_CTL__POR (0x00000016) +#define TABLA_A_BIAS_BG_STATUS (0x0106) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_BIAS_BG_STATUS__POR (0x00000000) +#define TABLA_A_CLK_BUFF_EN1 (0x0108) +#define TABLA_A_CLK_BUFF_EN1__POR (0x00000004) +#define TABLA_A_CLK_BUFF_EN2 (0x0109) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CLK_BUFF_EN2__POR (0x00000002) +#define TABLA_A_LDO_H_MODE_1 (0x0110) +#define TABLA_A_LDO_H_MODE_1__POR (0x00000065) +#define TABLA_A_LDO_H_MODE_2 (0x0111) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_LDO_H_MODE_2__POR (0x000000A8) +#define TABLA_A_LDO_H_LOOP_CTL (0x0112) +#define TABLA_A_LDO_H_LOOP_CTL__POR (0x0000006B) +#define TABLA_A_LDO_H_COMP_1 (0x0113) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_LDO_H_COMP_1__POR (0x00000084) +#define TABLA_A_LDO_H_COMP_2 (0x0114) +#define TABLA_A_LDO_H_COMP_2__POR (0x000000E0) +#define TABLA_A_LDO_H_BIAS_1 (0x0115) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_LDO_H_BIAS_1__POR (0x0000006D) +#define TABLA_A_LDO_H_BIAS_2 (0x0116) +#define TABLA_A_LDO_H_BIAS_2__POR (0x000000A5) +#define TABLA_A_LDO_H_BIAS_3 (0x0117) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_LDO_H_BIAS_3__POR (0x00000060) +#define TABLA_A_LDO_L_MODE_1 (0x0118) +#define TABLA_A_LDO_L_MODE_1__POR (0x00000028) +#define TABLA_A_LDO_L_MODE_2 (0x0119) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_LDO_L_MODE_2__POR (0x000000A8) +#define TABLA_A_LDO_L_LOOP_CTL (0x011A) +#define TABLA_A_LDO_L_LOOP_CTL__POR (0x0000006D) +#define TABLA_A_LDO_L_COMP_1 (0x011B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_LDO_L_COMP_1__POR (0x00000031) +#define TABLA_A_LDO_L_COMP_2 (0x011C) +#define TABLA_A_LDO_L_COMP_2__POR (0x000000A0) +#define TABLA_A_LDO_L_BIAS_1 (0x011D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_LDO_L_BIAS_1__POR (0x0000006D) +#define TABLA_A_LDO_L_BIAS_2 (0x011E) +#define TABLA_A_LDO_L_BIAS_2__POR (0x00000065) +#define TABLA_A_LDO_L_BIAS_3 (0x011F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_LDO_L_BIAS_3__POR (0x00000050) +#define TABLA_A_MICB_CFILT_1_CTL (0x0128) +#define TABLA_A_MICB_CFILT_1_CTL__POR (0x00000040) +#define TABLA_A_MICB_CFILT_1_VAL (0x0129) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_MICB_CFILT_1_VAL__POR (0x00000080) +#define TABLA_A_MICB_CFILT_1_PRECHRG (0x012A) +#define TABLA_A_MICB_CFILT_1_PRECHRG__POR (0x00000038) +#define TABLA_A_MICB_1_CTL (0x012B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_MICB_1_CTL__POR (0x00000016) +#define TABLA_A_MICB_1_INT_RBIAS (0x012C) +#define TABLA_A_MICB_1_INT_RBIAS__POR (0x00000000) +#define TABLA_A_MICB_1_MBHC (0x012D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_MICB_1_MBHC__POR (0x00000001) +#define TABLA_A_MICB_CFILT_2_CTL (0x012E) +#define TABLA_A_MICB_CFILT_2_CTL__POR (0x00000040) +#define TABLA_A_MICB_CFILT_2_VAL (0x012F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_MICB_CFILT_2_VAL__POR (0x00000080) +#define TABLA_A_MICB_CFILT_2_PRECHRG (0x0130) +#define TABLA_A_MICB_CFILT_2_PRECHRG__POR (0x00000038) +#define TABLA_A_MICB_2_CTL (0x0131) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_MICB_2_CTL__POR (0x00000016) +#define TABLA_A_MICB_2_INT_RBIAS (0x0132) +#define TABLA_A_MICB_2_INT_RBIAS__POR (0x00000000) +#define TABLA_A_MICB_2_MBHC (0x0133) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_MICB_2_MBHC__POR (0x00000000) +#define TABLA_A_MICB_CFILT_3_CTL (0x0134) +#define TABLA_A_MICB_CFILT_3_CTL__POR (0x00000040) +#define TABLA_A_MICB_CFILT_3_VAL (0x0135) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_MICB_CFILT_3_VAL__POR (0x00000080) +#define TABLA_A_MICB_CFILT_3_PRECHRG (0x0136) +#define TABLA_A_MICB_CFILT_3_PRECHRG__POR (0x00000038) +#define TABLA_A_MICB_3_CTL (0x0137) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_MICB_3_CTL__POR (0x00000016) +#define TABLA_A_MICB_3_INT_RBIAS (0x0138) +#define TABLA_A_MICB_3_INT_RBIAS__POR (0x00000000) +#define TABLA_A_MICB_3_MBHC (0x0139) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_MICB_3_MBHC__POR (0x00000000) +#define TABLA_1_A_MICB_4_CTL (0x013A) +#define TABLA_2_A_MICB_4_CTL (0x013D) +#define TABLA_A_MICB_4_CTL__POR (0x00000016) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_1_A_MICB_4_INT_RBIAS (0x013B) +#define TABLA_2_A_MICB_4_INT_RBIAS (0x013E) +#define TABLA_A_MICB_4_INT_RBIAS__POR (0x00000000) +#define TABLA_1_A_MICB_4_MBHC (0x013C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_2_A_MICB_4_MBHC (0x013F) +#define TABLA_A_MICB_4_MBHC__POR (0x00000001) +#define TABLA_A_TX_COM_BIAS (0x014C) +#define TABLA_A_TX_COM_BIAS__POR (0x000000E0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_MBHC_SCALING_MUX_1 (0x014E) +#define TABLA_A_MBHC_SCALING_MUX_1__POR (0x00000000) +#define TABLA_A_MBHC_SCALING_MUX_2 (0x014F) +#define TABLA_A_MBHC_SCALING_MUX_2__POR (0x00000080) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_TX_SUP_SWITCH_CTRL_1 (0x0151) +#define TABLA_A_TX_SUP_SWITCH_CTRL_1__POR (0x00000000) +#define TABLA_A_TX_SUP_SWITCH_CTRL_2 (0x0152) +#define TABLA_A_TX_SUP_SWITCH_CTRL_2__POR (0x00000080) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_TX_1_2_EN (0x0153) +#define TABLA_A_TX_1_2_EN__POR (0x00000000) +#define TABLA_A_TX_1_2_TEST_EN (0x0154) +#define TABLA_A_TX_1_2_TEST_EN__POR (0x000000CC) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_TX_1_2_ADC_CH1 (0x0155) +#define TABLA_A_TX_1_2_ADC_CH1__POR (0x00000044) +#define TABLA_A_TX_1_2_ADC_CH2 (0x0156) +#define TABLA_A_TX_1_2_ADC_CH2__POR (0x00000044) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_TX_1_2_ATEST_REFCTRL (0x0157) +#define TABLA_A_TX_1_2_ATEST_REFCTRL__POR (0x00000000) +#define TABLA_A_TX_1_2_TEST_CTL (0x0158) +#define TABLA_A_TX_1_2_TEST_CTL__POR (0x00000038) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_TX_1_2_TEST_BLOCK_EN (0x0159) +#define TABLA_A_TX_1_2_TEST_BLOCK_EN__POR (0x000000FF) +#define TABLA_A_TX_1_2_TXFE_CLKDIV (0x015A) +#define TABLA_A_TX_1_2_TXFE_CLKDIV__POR (0x000000EE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_TX_1_2_SAR_ERR_CH1 (0x015B) +#define TABLA_A_TX_1_2_SAR_ERR_CH1__POR (0x00000000) +#define TABLA_A_TX_1_2_SAR_ERR_CH2 (0x015C) +#define TABLA_A_TX_1_2_SAR_ERR_CH2__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_TX_3_4_EN (0x015D) +#define TABLA_A_TX_3_4_EN__POR (0x00000000) +#define TABLA_A_TX_3_4_TEST_EN (0x015E) +#define TABLA_A_TX_3_4_TEST_EN__POR (0x000000CC) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_TX_3_4_ADC_CH3 (0x015F) +#define TABLA_A_TX_3_4_ADC_CH3__POR (0x00000044) +#define TABLA_A_TX_3_4_ADC_CH4 (0x0160) +#define TABLA_A_TX_3_4_ADC_CH4__POR (0x00000044) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_TX_3_4_ATEST_REFCTRL (0x0161) +#define TABLA_A_TX_3_4_ATEST_REFCTRL__POR (0x00000000) +#define TABLA_A_TX_3_4_TEST_CTL (0x0162) +#define TABLA_A_TX_3_4_TEST_CTL__POR (0x00000038) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_TX_3_4_TEST_BLOCK_EN (0x0163) +#define TABLA_A_TX_3_4_TEST_BLOCK_EN__POR (0x000000FF) +#define TABLA_A_TX_3_4_TXFE_CKDIV (0x0164) +#define TABLA_A_TX_3_4_TXFE_CKDIV__POR (0x000000EE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_TX_3_4_SAR_ERR_CH3 (0x0165) +#define TABLA_A_TX_3_4_SAR_ERR_CH3__POR (0x00000000) +#define TABLA_A_TX_3_4_SAR_ERR_CH4 (0x0166) +#define TABLA_A_TX_3_4_SAR_ERR_CH4__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_TX_5_6_EN (0x0167) +#define TABLA_A_TX_5_6_EN__POR (0x00000011) +#define TABLA_A_TX_5_6_TEST_EN (0x0168) +#define TABLA_A_TX_5_6_TEST_EN__POR (0x000000CC) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_TX_5_6_ADC_CH5 (0x0169) +#define TABLA_A_TX_5_6_ADC_CH5__POR (0x00000044) +#define TABLA_A_TX_5_6_ADC_CH6 (0x016A) +#define TABLA_A_TX_5_6_ADC_CH6__POR (0x00000044) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_TX_5_6_ATEST_REFCTRL (0x016B) +#define TABLA_A_TX_5_6_ATEST_REFCTRL__POR (0x00000000) +#define TABLA_A_TX_5_6_TEST_CTL (0x016C) +#define TABLA_A_TX_5_6_TEST_CTL__POR (0x00000038) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_TX_5_6_TEST_BLOCK_EN (0x016D) +#define TABLA_A_TX_5_6_TEST_BLOCK_EN__POR (0x000000FF) +#define TABLA_A_TX_5_6_TXFE_CKDIV (0x016E) +#define TABLA_A_TX_5_6_TXFE_CKDIV__POR (0x000000EE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_TX_5_6_SAR_ERR_CH5 (0x016F) +#define TABLA_A_TX_5_6_SAR_ERR_CH5__POR (0x00000000) +#define TABLA_A_TX_5_6_SAR_ERR_CH6 (0x0170) +#define TABLA_A_TX_5_6_SAR_ERR_CH6__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_TX_7_MBHC_EN (0x0171) +#define TABLA_A_TX_7_MBHC_EN__POR (0x0000000C) +#define TABLA_A_TX_7_MBHC_ATEST_REFCTRL (0x0172) +#define TABLA_A_TX_7_MBHC_ATEST_REFCTRL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_TX_7_MBHC_ADC (0x0173) +#define TABLA_A_TX_7_MBHC_ADC__POR (0x00000044) +#define TABLA_A_TX_7_MBHC_TEST_CTL (0x0174) +#define TABLA_A_TX_7_MBHC_TEST_CTL__POR (0x00000038) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_TX_7_MBHC_SAR_ERR (0x0175) +#define TABLA_A_TX_7_MBHC_SAR_ERR__POR (0x00000000) +#define TABLA_A_TX_7_TXFE_CLKDIV (0x0176) +#define TABLA_A_TX_7_TXFE_CLKDIV__POR (0x0000001C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_AUX_COM_CTL (0x0180) +#define TABLA_A_AUX_COM_CTL__POR (0x00000034) +#define TABLA_A_AUX_COM_ATEST (0x0181) +#define TABLA_A_AUX_COM_ATEST__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_AUX_L_EN (0x0182) +#define TABLA_A_AUX_L_EN__POR (0x00000000) +#define TABLA_A_AUX_L_GAIN (0x0183) +#define TABLA_A_AUX_L_GAIN__POR (0x0000001F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_AUX_L_PA_CONN (0x0184) +#define TABLA_A_AUX_L_PA_CONN__POR (0x00000000) +#define TABLA_A_AUX_L_PA_CONN_INV (0x0185) +#define TABLA_A_AUX_L_PA_CONN_INV__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_AUX_R_EN (0x0186) +#define TABLA_A_AUX_R_EN__POR (0x00000000) +#define TABLA_A_AUX_R_GAIN (0x0187) +#define TABLA_A_AUX_R_GAIN__POR (0x0000001F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_AUX_R_PA_CONN (0x0188) +#define TABLA_A_AUX_R_PA_CONN__POR (0x00000000) +#define TABLA_A_AUX_R_PA_CONN_INV (0x0189) +#define TABLA_A_AUX_R_PA_CONN_INV__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CP_EN (0x0192) +#define TABLA_A_CP_EN__POR (0x000000E6) +#define TABLA_A_CP_CLK (0x0193) +#define TABLA_A_CP_CLK__POR (0x00000029) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CP_STATIC (0x0194) +#define TABLA_A_CP_STATIC__POR (0x00000010) +#define TABLA_A_CP_DCC1 (0x0195) +#define TABLA_A_CP_DCC1__POR (0x00000052) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CP_DCC3 (0x0196) +#define TABLA_A_CP_DCC3__POR (0x00000001) +#define TABLA_A_CP_ATEST (0x0197) +#define TABLA_A_CP_ATEST__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CP_DTEST (0x0198) +#define TABLA_A_CP_DTEST__POR (0x00000000) +#define TABLA_A_RX_COM_TIMER_DIV (0x019E) +#define TABLA_A_RX_COM_TIMER_DIV__POR (0x000000E8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_COM_OCP_CTL (0x019F) +#define TABLA_A_RX_COM_OCP_CTL__POR (0x0000001F) +#define TABLA_A_RX_COM_OCP_COUNT (0x01A0) +#define TABLA_A_RX_COM_OCP_COUNT__POR (0x00000077) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_COM_DAC_CTL (0x01A1) +#define TABLA_A_RX_COM_DAC_CTL__POR (0x00000000) +#define TABLA_A_RX_COM_BIAS (0x01A2) +#define TABLA_A_RX_COM_BIAS__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_HPH_BIAS_PA (0x01A6) +#define TABLA_A_RX_HPH_BIAS_PA__POR (0x000000AA) +#define TABLA_A_RX_HPH_BIAS_LDO (0x01A7) +#define TABLA_A_RX_HPH_BIAS_LDO__POR (0x00000086) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_HPH_BIAS_CNP (0x01A8) +#define TABLA_A_RX_HPH_BIAS_CNP__POR (0x0000008A) +#define TABLA_A_RX_HPH_BIAS_WG (0x01A9) +#define TABLA_A_RX_HPH_BIAS_WG__POR (0x00000060) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_HPH_OCP_CTL (0x01AA) +#define TABLA_A_RX_HPH_OCP_CTL__POR (0x000000E8) +#define TABLA_A_RX_HPH_CNP_EN (0x01AB) +#define TABLA_A_RX_HPH_CNP_EN__POR (0x00000080) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_HPH_CNP_WG_CTL (0x01AC) +#define TABLA_A_RX_HPH_CNP_WG_CTL__POR (0x000000DC) +#define TABLA_A_RX_HPH_CNP_WG_TIME (0x01AD) +#define TABLA_A_RX_HPH_CNP_WG_TIME__POR (0x00000028) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_HPH_L_GAIN (0x01AE) +#define TABLA_A_RX_HPH_L_GAIN__POR (0x00000000) +#define TABLA_A_RX_HPH_L_TEST (0x01AF) +#define TABLA_A_RX_HPH_L_TEST__POR (0x00000001) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_HPH_L_PA_CTL (0x01B0) +#define TABLA_A_RX_HPH_L_PA_CTL__POR (0x00000040) +#define TABLA_A_RX_HPH_L_DAC_CTL (0x01B1) +#define TABLA_A_RX_HPH_L_DAC_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_HPH_L_ATEST (0x01B2) +#define TABLA_A_RX_HPH_L_ATEST__POR (0x00000000) +#define TABLA_A_RX_HPH_L_STATUS (0x01B3) +#define TABLA_A_RX_HPH_L_STATUS__POR (0x00000004) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_HPH_R_GAIN (0x01B4) +#define TABLA_A_RX_HPH_R_GAIN__POR (0x00000000) +#define TABLA_A_RX_HPH_R_TEST (0x01B5) +#define TABLA_A_RX_HPH_R_TEST__POR (0x00000001) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_HPH_R_PA_CTL (0x01B6) +#define TABLA_A_RX_HPH_R_PA_CTL__POR (0x00000040) +#define TABLA_A_RX_HPH_R_DAC_CTL (0x01B7) +#define TABLA_A_RX_HPH_R_DAC_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_HPH_R_ATEST (0x01B8) +#define TABLA_A_RX_HPH_R_ATEST__POR (0x00000000) +#define TABLA_A_RX_HPH_R_STATUS (0x01B9) +#define TABLA_A_RX_HPH_R_STATUS__POR (0x00000004) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_EAR_BIAS_PA (0x01BA) +#define TABLA_A_RX_EAR_BIAS_PA__POR (0x000000AA) +#define TABLA_A_RX_EAR_BIAS_CMBUFF (0x01BB) +#define TABLA_A_RX_EAR_BIAS_CMBUFF__POR (0x000000A0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_EAR_EN (0x01BC) +#define TABLA_A_RX_EAR_EN__POR (0x00000000) +#define TABLA_A_RX_EAR_GAIN (0x01BD) +#define TABLA_A_RX_EAR_GAIN__POR (0x00000008) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_EAR_CMBUFF (0x01BE) +#define TABLA_A_RX_EAR_CMBUFF__POR (0x00000000) +#define TABLA_A_RX_EAR_ICTL (0x01BF) +#define TABLA_A_RX_EAR_ICTL__POR (0x00000040) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_EAR_CCOMP (0x01C0) +#define TABLA_A_RX_EAR_CCOMP__POR (0x00000008) +#define TABLA_A_RX_EAR_VCM (0x01C1) +#define TABLA_A_RX_EAR_VCM__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_EAR_CNP (0x01C2) +#define TABLA_A_RX_EAR_CNP__POR (0x00000080) +#define TABLA_A_RX_EAR_ATEST (0x01C3) +#define TABLA_A_RX_EAR_ATEST__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_EAR_STATUS (0x01C5) +#define TABLA_A_RX_EAR_STATUS__POR (0x00000004) +#define TABLA_A_RX_LINE_BIAS_PA (0x01C6) +#define TABLA_A_RX_LINE_BIAS_PA__POR (0x000000AA) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_LINE_BIAS_DAC (0x01C7) +#define TABLA_A_RX_LINE_BIAS_DAC__POR (0x000000A0) +#define TABLA_A_RX_LINE_BIAS_CNP (0x01C8) +#define TABLA_A_RX_LINE_BIAS_CNP__POR (0x0000003A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_LINE_COM (0x01C9) +#define TABLA_A_RX_LINE_COM__POR (0x00000000) +#define TABLA_A_RX_LINE_CNP_EN (0x01CA) +#define TABLA_A_RX_LINE_CNP_EN__POR (0x00000080) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_LINE_CNP_WG_CTL (0x01CB) +#define TABLA_A_RX_LINE_CNP_WG_CTL__POR (0x0000001C) +#define TABLA_A_RX_LINE_CNP_WG_TIME (0x01CC) +#define TABLA_A_RX_LINE_CNP_WG_TIME__POR (0x00000064) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_LINE_1_GAIN (0x01CD) +#define TABLA_A_RX_LINE_1_GAIN__POR (0x00000000) +#define TABLA_A_RX_LINE_1_TEST (0x01CE) +#define TABLA_A_RX_LINE_1_TEST__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_LINE_1_DAC_CTL (0x01CF) +#define TABLA_A_RX_LINE_1_DAC_CTL__POR (0x0000000C) +#define TABLA_A_RX_LINE_1_STATUS (0x01D0) +#define TABLA_A_RX_LINE_1_STATUS__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_LINE_2_GAIN (0x01D1) +#define TABLA_A_RX_LINE_2_GAIN__POR (0x00000000) +#define TABLA_A_RX_LINE_2_TEST (0x01D2) +#define TABLA_A_RX_LINE_2_TEST__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_LINE_2_DAC_CTL (0x01D3) +#define TABLA_A_RX_LINE_2_DAC_CTL__POR (0x0000000C) +#define TABLA_A_RX_LINE_2_STATUS (0x01D4) +#define TABLA_A_RX_LINE_2_STATUS__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_LINE_3_GAIN (0x01D5) +#define TABLA_A_RX_LINE_3_GAIN__POR (0x00000000) +#define TABLA_A_RX_LINE_3_TEST (0x01D6) +#define TABLA_A_RX_LINE_3_TEST__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_LINE_3_DAC_CTL (0x01D7) +#define TABLA_A_RX_LINE_3_DAC_CTL__POR (0x0000000C) +#define TABLA_A_RX_LINE_3_STATUS (0x01D8) +#define TABLA_A_RX_LINE_3_STATUS__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_LINE_4_GAIN (0x01D9) +#define TABLA_A_RX_LINE_4_GAIN__POR (0x00000000) +#define TABLA_A_RX_LINE_4_TEST (0x01DA) +#define TABLA_A_RX_LINE_4_TEST__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_LINE_4_DAC_CTL (0x01DB) +#define TABLA_A_RX_LINE_4_DAC_CTL__POR (0x0000000C) +#define TABLA_A_RX_LINE_4_STATUS (0x01DC) +#define TABLA_A_RX_LINE_4_STATUS__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_LINE_5_GAIN (0x01DD) +#define TABLA_A_RX_LINE_5_GAIN__POR (0x00000000) +#define TABLA_A_RX_LINE_5_TEST (0x01DE) +#define TABLA_A_RX_LINE_5_TEST__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_LINE_5_DAC_CTL (0x01DF) +#define TABLA_A_RX_LINE_5_DAC_CTL__POR (0x0000000C) +#define TABLA_A_RX_LINE_5_STATUS (0x01E0) +#define TABLA_A_RX_LINE_5_STATUS__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_RX_LINE_CNP_DBG (0x01EC) +#define TABLA_A_RX_LINE_CNP_DBG__POR (0x00000000) +#define TABLA_A_MBHC_HPH (0x01ED) +#define TABLA_A_MBHC_HPH__POR (0x00000048) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CONFIG_MODE_FREQ (0x01F7) +#define TABLA_A_CONFIG_MODE_FREQ__POR (0x00000047) +#define TABLA_A_CONFIG_MODE_TEST (0x01F8) +#define TABLA_A_CONFIG_MODE_TEST__POR (0x0000000A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CONFIG_MODE_STATUS (0x01F9) +#define TABLA_A_CONFIG_MODE_STATUS__POR (0x0000001C) +#define TABLA_A_CONFIG_MODE_TUNER (0x01FA) +#define TABLA_A_CONFIG_MODE_TUNER__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_ANC1_CTL (0x00000200) +#define TABLA_A_CDC_ANC1_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_CTL (0x00000280) +#define TABLA_A_CDC_ANC2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_ANC1_SHIFT (0x00000201) +#define TABLA_A_CDC_ANC1_SHIFT__POR (0x00000000) +#define TABLA_A_CDC_ANC2_SHIFT (0x00000281) +#define TABLA_A_CDC_ANC2_SHIFT__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_ANC1_FILT1_B1_CTL (0x00000202) +#define TABLA_A_CDC_ANC1_FILT1_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT1_B1_CTL (0x00000282) +#define TABLA_A_CDC_ANC2_FILT1_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_ANC1_FILT1_B2_CTL (0x00000203) +#define TABLA_A_CDC_ANC1_FILT1_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT1_B2_CTL (0x00000283) +#define TABLA_A_CDC_ANC2_FILT1_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_ANC1_FILT1_B3_CTL (0x00000204) +#define TABLA_A_CDC_ANC1_FILT1_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT1_B3_CTL (0x00000284) +#define TABLA_A_CDC_ANC2_FILT1_B3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_ANC1_FILT1_B4_CTL (0x00000205) +#define TABLA_A_CDC_ANC1_FILT1_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT1_B4_CTL (0x00000285) +#define TABLA_A_CDC_ANC2_FILT1_B4_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_ANC1_FILT2_B1_CTL (0x00000206) +#define TABLA_A_CDC_ANC1_FILT2_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT2_B1_CTL (0x00000286) +#define TABLA_A_CDC_ANC2_FILT2_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_ANC1_FILT2_B2_CTL (0x00000207) +#define TABLA_A_CDC_ANC1_FILT2_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT2_B2_CTL (0x00000287) +#define TABLA_A_CDC_ANC2_FILT2_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_ANC1_FILT2_B3_CTL (0x00000208) +#define TABLA_A_CDC_ANC1_FILT2_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT2_B3_CTL (0x00000288) +#define TABLA_A_CDC_ANC2_FILT2_B3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_ANC1_SPARE (0x00000209) +#define TABLA_A_CDC_ANC1_SPARE__POR (0x00000000) +#define TABLA_A_CDC_ANC2_SPARE (0x00000289) +#define TABLA_A_CDC_ANC2_SPARE__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_ANC1_FILT3_CTL (0x0000020A) +#define TABLA_A_CDC_ANC1_FILT3_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT3_CTL (0x0000028A) +#define TABLA_A_CDC_ANC2_FILT3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_ANC1_FILT4_CTL (0x0000020B) +#define TABLA_A_CDC_ANC1_FILT4_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT4_CTL (0x0000028B) +#define TABLA_A_CDC_ANC2_FILT4_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX1_VOL_CTL_TIMER (0x00000220) +#define TABLA_A_CDC_TX1_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX2_VOL_CTL_TIMER (0x00000228) +#define TABLA_A_CDC_TX2_VOL_CTL_TIMER__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX3_VOL_CTL_TIMER (0x00000230) +#define TABLA_A_CDC_TX3_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX4_VOL_CTL_TIMER (0x00000238) +#define TABLA_A_CDC_TX4_VOL_CTL_TIMER__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX5_VOL_CTL_TIMER (0x00000240) +#define TABLA_A_CDC_TX5_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX6_VOL_CTL_TIMER (0x00000248) +#define TABLA_A_CDC_TX6_VOL_CTL_TIMER__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX7_VOL_CTL_TIMER (0x00000250) +#define TABLA_A_CDC_TX7_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX8_VOL_CTL_TIMER (0x00000258) +#define TABLA_A_CDC_TX8_VOL_CTL_TIMER__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX9_VOL_CTL_TIMER (0x00000260) +#define TABLA_A_CDC_TX9_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX10_VOL_CTL_TIMER (0x00000268) +#define TABLA_A_CDC_TX10_VOL_CTL_TIMER__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX1_VOL_CTL_GAIN (0x00000221) +#define TABLA_A_CDC_TX1_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX2_VOL_CTL_GAIN (0x00000229) +#define TABLA_A_CDC_TX2_VOL_CTL_GAIN__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX3_VOL_CTL_GAIN (0x00000231) +#define TABLA_A_CDC_TX3_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX4_VOL_CTL_GAIN (0x00000239) +#define TABLA_A_CDC_TX4_VOL_CTL_GAIN__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX5_VOL_CTL_GAIN (0x00000241) +#define TABLA_A_CDC_TX5_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX6_VOL_CTL_GAIN (0x00000249) +#define TABLA_A_CDC_TX6_VOL_CTL_GAIN__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX7_VOL_CTL_GAIN (0x00000251) +#define TABLA_A_CDC_TX7_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX8_VOL_CTL_GAIN (0x00000259) +#define TABLA_A_CDC_TX8_VOL_CTL_GAIN__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX9_VOL_CTL_GAIN (0x00000261) +#define TABLA_A_CDC_TX9_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX10_VOL_CTL_GAIN (0x00000269) +#define TABLA_A_CDC_TX10_VOL_CTL_GAIN__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX1_VOL_CTL_CFG (0x00000222) +#define TABLA_A_CDC_TX1_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX2_VOL_CTL_CFG (0x0000022A) +#define TABLA_A_CDC_TX2_VOL_CTL_CFG__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX3_VOL_CTL_CFG (0x00000232) +#define TABLA_A_CDC_TX3_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX4_VOL_CTL_CFG (0x0000023A) +#define TABLA_A_CDC_TX4_VOL_CTL_CFG__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX5_VOL_CTL_CFG (0x00000242) +#define TABLA_A_CDC_TX5_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX6_VOL_CTL_CFG (0x0000024A) +#define TABLA_A_CDC_TX6_VOL_CTL_CFG__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX7_VOL_CTL_CFG (0x00000252) +#define TABLA_A_CDC_TX7_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX8_VOL_CTL_CFG (0x0000025A) +#define TABLA_A_CDC_TX8_VOL_CTL_CFG__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX9_VOL_CTL_CFG (0x00000262) +#define TABLA_A_CDC_TX9_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX10_VOL_CTL_CFG (0x0000026A) +#define TABLA_A_CDC_TX10_VOL_CTL_CFG__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX1_MUX_CTL (0x00000223) +#define TABLA_A_CDC_TX1_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX2_MUX_CTL (0x0000022B) +#define TABLA_A_CDC_TX2_MUX_CTL__POR (0x00000008) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX3_MUX_CTL (0x00000233) +#define TABLA_A_CDC_TX3_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX4_MUX_CTL (0x0000023B) +#define TABLA_A_CDC_TX4_MUX_CTL__POR (0x00000008) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX5_MUX_CTL (0x00000243) +#define TABLA_A_CDC_TX5_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX6_MUX_CTL (0x0000024B) +#define TABLA_A_CDC_TX6_MUX_CTL__POR (0x00000008) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX7_MUX_CTL (0x00000253) +#define TABLA_A_CDC_TX7_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX8_MUX_CTL (0x0000025B) +#define TABLA_A_CDC_TX8_MUX_CTL__POR (0x00000008) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX9_MUX_CTL (0x00000263) +#define TABLA_A_CDC_TX9_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX10_MUX_CTL (0x0000026B) +#define TABLA_A_CDC_TX10_MUX_CTL__POR (0x00000008) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX1_CLK_FS_CTL (0x00000224) +#define TABLA_A_CDC_TX1_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX2_CLK_FS_CTL (0x0000022C) +#define TABLA_A_CDC_TX2_CLK_FS_CTL__POR (0x00000003) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX3_CLK_FS_CTL (0x00000234) +#define TABLA_A_CDC_TX3_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX4_CLK_FS_CTL (0x0000023C) +#define TABLA_A_CDC_TX4_CLK_FS_CTL__POR (0x00000003) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX5_CLK_FS_CTL (0x00000244) +#define TABLA_A_CDC_TX5_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX6_CLK_FS_CTL (0x0000024C) +#define TABLA_A_CDC_TX6_CLK_FS_CTL__POR (0x00000003) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX7_CLK_FS_CTL (0x00000254) +#define TABLA_A_CDC_TX7_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX8_CLK_FS_CTL (0x0000025C) +#define TABLA_A_CDC_TX8_CLK_FS_CTL__POR (0x00000003) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX9_CLK_FS_CTL (0x00000264) +#define TABLA_A_CDC_TX9_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX10_CLK_FS_CTL (0x0000026C) +#define TABLA_A_CDC_TX10_CLK_FS_CTL__POR (0x00000003) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX1_DMIC_CTL (0x00000225) +#define TABLA_A_CDC_TX1_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX2_DMIC_CTL (0x0000022D) +#define TABLA_A_CDC_TX2_DMIC_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX3_DMIC_CTL (0x00000235) +#define TABLA_A_CDC_TX3_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX4_DMIC_CTL (0x0000023D) +#define TABLA_A_CDC_TX4_DMIC_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX5_DMIC_CTL (0x00000245) +#define TABLA_A_CDC_TX5_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX6_DMIC_CTL (0x0000024D) +#define TABLA_A_CDC_TX6_DMIC_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX7_DMIC_CTL (0x00000255) +#define TABLA_A_CDC_TX7_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX8_DMIC_CTL (0x0000025D) +#define TABLA_A_CDC_TX8_DMIC_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TX9_DMIC_CTL (0x00000265) +#define TABLA_A_CDC_TX9_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX10_DMIC_CTL (0x0000026D) +#define TABLA_A_CDC_TX10_DMIC_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_SRC1_PDA_CFG (0x000002A0) +#define TABLA_A_CDC_SRC1_PDA_CFG__POR (0x00000000) +#define TABLA_A_CDC_SRC2_PDA_CFG (0x000002A8) +#define TABLA_A_CDC_SRC2_PDA_CFG__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_SRC1_FS_CTL (0x000002A1) +#define TABLA_A_CDC_SRC1_FS_CTL__POR (0x0000001b) +#define TABLA_A_CDC_SRC2_FS_CTL (0x000002A9) +#define TABLA_A_CDC_SRC2_FS_CTL__POR (0x0000001b) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX1_B1_CTL (0x000002B0) +#define TABLA_A_CDC_RX1_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX2_B1_CTL (0x000002B8) +#define TABLA_A_CDC_RX2_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX3_B1_CTL (0x000002C0) +#define TABLA_A_CDC_RX3_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX4_B1_CTL (0x000002C8) +#define TABLA_A_CDC_RX4_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX5_B1_CTL (0x000002D0) +#define TABLA_A_CDC_RX5_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX6_B1_CTL (0x000002D8) +#define TABLA_A_CDC_RX6_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX7_B1_CTL (0x000002E0) +#define TABLA_A_CDC_RX7_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX1_B2_CTL (0x000002B1) +#define TABLA_A_CDC_RX1_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX2_B2_CTL (0x000002B9) +#define TABLA_A_CDC_RX2_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX3_B2_CTL (0x000002C1) +#define TABLA_A_CDC_RX3_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX4_B2_CTL (0x000002C9) +#define TABLA_A_CDC_RX4_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX5_B2_CTL (0x000002D1) +#define TABLA_A_CDC_RX5_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX6_B2_CTL (0x000002D9) +#define TABLA_A_CDC_RX6_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX7_B2_CTL (0x000002E1) +#define TABLA_A_CDC_RX7_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX1_B3_CTL (0x000002B2) +#define TABLA_A_CDC_RX1_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX2_B3_CTL (0x000002BA) +#define TABLA_A_CDC_RX2_B3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX3_B3_CTL (0x000002C2) +#define TABLA_A_CDC_RX3_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX4_B3_CTL (0x000002CA) +#define TABLA_A_CDC_RX4_B3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX5_B3_CTL (0x000002D2) +#define TABLA_A_CDC_RX5_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX6_B3_CTL (0x000002DA) +#define TABLA_A_CDC_RX6_B3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX7_B3_CTL (0x000002E2) +#define TABLA_A_CDC_RX7_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX1_B4_CTL (0x000002B3) +#define TABLA_A_CDC_RX1_B4_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX2_B4_CTL (0x000002BB) +#define TABLA_A_CDC_RX2_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX3_B4_CTL (0x000002C3) +#define TABLA_A_CDC_RX3_B4_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX4_B4_CTL (0x000002CB) +#define TABLA_A_CDC_RX4_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX5_B4_CTL (0x000002D3) +#define TABLA_A_CDC_RX5_B4_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX6_B4_CTL (0x000002DB) +#define TABLA_A_CDC_RX6_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX7_B4_CTL (0x000002E3) +#define TABLA_A_CDC_RX7_B4_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX1_B5_CTL (0x000002B4) +#define TABLA_A_CDC_RX1_B5_CTL__POR (0x00000060) +#define TABLA_A_CDC_RX2_B5_CTL (0x000002BC) +#define TABLA_A_CDC_RX2_B5_CTL__POR (0x00000060) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX3_B5_CTL (0x000002C4) +#define TABLA_A_CDC_RX3_B5_CTL__POR (0x00000060) +#define TABLA_A_CDC_RX4_B5_CTL (0x000002CC) +#define TABLA_A_CDC_RX4_B5_CTL__POR (0x00000060) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX5_B5_CTL (0x000002D4) +#define TABLA_A_CDC_RX5_B5_CTL__POR (0x00000060) +#define TABLA_A_CDC_RX6_B5_CTL (0x000002DC) +#define TABLA_A_CDC_RX6_B5_CTL__POR (0x00000060) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX7_B5_CTL (0x000002E4) +#define TABLA_A_CDC_RX7_B5_CTL__POR (0x00000060) +#define TABLA_A_CDC_RX1_B6_CTL (0x000002B5) +#define TABLA_A_CDC_RX1_B6_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX2_B6_CTL (0x000002BD) +#define TABLA_A_CDC_RX2_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX3_B6_CTL (0x000002C5) +#define TABLA_A_CDC_RX3_B6_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX4_B6_CTL (0x000002CD) +#define TABLA_A_CDC_RX4_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX5_B6_CTL (0x000002D5) +#define TABLA_A_CDC_RX5_B6_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX6_B6_CTL (0x000002DD) +#define TABLA_A_CDC_RX6_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX7_B6_CTL (0x000002E5) +#define TABLA_A_CDC_RX7_B6_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX1_VOL_CTL_B1_CTL (0x000002B6) +#define TABLA_A_CDC_RX1_VOL_CTL_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX2_VOL_CTL_B1_CTL (0x000002BE) +#define TABLA_A_CDC_RX2_VOL_CTL_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX3_VOL_CTL_B1_CTL (0x000002C6) +#define TABLA_A_CDC_RX3_VOL_CTL_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX4_VOL_CTL_B1_CTL (0x000002CE) +#define TABLA_A_CDC_RX4_VOL_CTL_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX5_VOL_CTL_B1_CTL (0x000002D6) +#define TABLA_A_CDC_RX5_VOL_CTL_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX6_VOL_CTL_B1_CTL (0x000002DE) +#define TABLA_A_CDC_RX6_VOL_CTL_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX7_VOL_CTL_B1_CTL (0x000002E6) +#define TABLA_A_CDC_RX7_VOL_CTL_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX1_VOL_CTL_B2_CTL (0x000002B7) +#define TABLA_A_CDC_RX1_VOL_CTL_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX2_VOL_CTL_B2_CTL (0x000002BF) +#define TABLA_A_CDC_RX2_VOL_CTL_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX3_VOL_CTL_B2_CTL (0x000002C7) +#define TABLA_A_CDC_RX3_VOL_CTL_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX4_VOL_CTL_B2_CTL (0x000002CF) +#define TABLA_A_CDC_RX4_VOL_CTL_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX5_VOL_CTL_B2_CTL (0x000002D7) +#define TABLA_A_CDC_RX5_VOL_CTL_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_RX6_VOL_CTL_B2_CTL (0x000002DF) +#define TABLA_A_CDC_RX6_VOL_CTL_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX7_VOL_CTL_B2_CTL (0x000002E7) +#define TABLA_A_CDC_RX7_VOL_CTL_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CLK_ANC_RESET_CTL (0x00000300) +#define TABLA_A_CDC_CLK_ANC_RESET_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_RX_RESET_CTL (0x00000301) +#define TABLA_A_CDC_CLK_RX_RESET_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CLK_TX_RESET_B1_CTL (0x00000302) +#define TABLA_A_CDC_CLK_TX_RESET_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_TX_RESET_B2_CTL (0x00000303) +#define TABLA_A_CDC_CLK_TX_RESET_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CLK_DMIC_CTL (0x00000304) +#define TABLA_A_CDC_CLK_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_RX_I2S_CTL (0x00000305) +#define TABLA_A_CDC_CLK_RX_I2S_CTL__POR (0x00000003) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CLK_TX_I2S_CTL (0x00000306) +#define TABLA_A_CDC_CLK_TX_I2S_CTL__POR (0x00000003) +#define TABLA_A_CDC_CLK_OTHR_RESET_CTL (0x00000307) +#define TABLA_A_CDC_CLK_OTHR_RESET_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL (0x00000308) +#define TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_TX_CLK_EN_B2_CTL (0x00000309) +#define TABLA_A_CDC_CLK_TX_CLK_EN_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CLK_OTHR_CTL (0x0000030A) +#define TABLA_A_CDC_CLK_OTHR_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_RDAC_CLK_EN_CTL (0x0000030B) +#define TABLA_A_CDC_CLK_RDAC_CLK_EN_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CLK_ANC_CLK_EN_CTL (0x0000030C) +#define TABLA_A_CDC_CLK_ANC_CLK_EN_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_RX_B1_CTL (0x0000030D) +#define TABLA_A_CDC_CLK_RX_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CLK_RX_B2_CTL (0x0000030E) +#define TABLA_A_CDC_CLK_RX_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_MCLK_CTL (0x0000030F) +#define TABLA_A_CDC_CLK_MCLK_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CLK_PDM_CTL (0x00000310) +#define TABLA_A_CDC_CLK_PDM_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_SD_CTL (0x00000311) +#define TABLA_A_CDC_CLK_SD_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B1_CTL (0x00000320) +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B1_CTL__POR (0x00000007) +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B2_CTL (0x00000321) +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B2_CTL__POR (0x00000013) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B3_CTL (0x00000322) +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B3_CTL__POR (0x00000053) +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B4_CTL (0x00000323) +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B4_CTL__POR (0x0000007f) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CLSG_GAIN_THRESH_CTL (0x00000324) +#define TABLA_A_CDC_CLSG_GAIN_THRESH_CTL__POR (0x00000026) +#define TABLA_A_CDC_CLSG_TIMER_B1_CFG (0x00000325) +#define TABLA_A_CDC_CLSG_TIMER_B1_CFG__POR (0x0000000a) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CLSG_TIMER_B2_CFG (0x00000326) +#define TABLA_A_CDC_CLSG_TIMER_B2_CFG__POR (0x00000000) +#define TABLA_A_CDC_CLSG_CTL (0x00000327) +#define TABLA_A_CDC_CLSG_CTL__POR (0x00000013) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_IIR1_GAIN_B1_CTL (0x00000340) +#define TABLA_A_CDC_IIR1_GAIN_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B1_CTL (0x00000350) +#define TABLA_A_CDC_IIR2_GAIN_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_IIR1_GAIN_B2_CTL (0x00000341) +#define TABLA_A_CDC_IIR1_GAIN_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B2_CTL (0x00000351) +#define TABLA_A_CDC_IIR2_GAIN_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_IIR1_GAIN_B3_CTL (0x00000342) +#define TABLA_A_CDC_IIR1_GAIN_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B3_CTL (0x00000352) +#define TABLA_A_CDC_IIR2_GAIN_B3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_IIR1_GAIN_B4_CTL (0x00000343) +#define TABLA_A_CDC_IIR1_GAIN_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B4_CTL (0x00000353) +#define TABLA_A_CDC_IIR2_GAIN_B4_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_IIR1_GAIN_B5_CTL (0x00000344) +#define TABLA_A_CDC_IIR1_GAIN_B5_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B5_CTL (0x00000354) +#define TABLA_A_CDC_IIR2_GAIN_B5_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_IIR1_GAIN_B6_CTL (0x00000345) +#define TABLA_A_CDC_IIR1_GAIN_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B6_CTL (0x00000355) +#define TABLA_A_CDC_IIR2_GAIN_B6_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_IIR1_GAIN_B7_CTL (0x00000346) +#define TABLA_A_CDC_IIR1_GAIN_B7_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B7_CTL (0x00000356) +#define TABLA_A_CDC_IIR2_GAIN_B7_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_IIR1_GAIN_B8_CTL (0x00000347) +#define TABLA_A_CDC_IIR1_GAIN_B8_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B8_CTL (0x00000357) +#define TABLA_A_CDC_IIR2_GAIN_B8_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_IIR1_CTL (0x00000348) +#define TABLA_A_CDC_IIR1_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_CTL (0x00000358) +#define TABLA_A_CDC_IIR2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_IIR1_GAIN_TIMER_CTL (0x00000349) +#define TABLA_A_CDC_IIR1_GAIN_TIMER_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_TIMER_CTL (0x00000359) +#define TABLA_A_CDC_IIR2_GAIN_TIMER_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_IIR1_COEF_B1_CTL (0x0000034A) +#define TABLA_A_CDC_IIR1_COEF_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_COEF_B1_CTL (0x0000035A) +#define TABLA_A_CDC_IIR2_COEF_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_IIR1_COEF_B2_CTL (0x0000034B) +#define TABLA_A_CDC_IIR1_COEF_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_COEF_B2_CTL (0x0000035B) +#define TABLA_A_CDC_IIR2_COEF_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_IIR1_COEF_B3_CTL (0x0000034C) +#define TABLA_A_CDC_IIR1_COEF_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_COEF_B3_CTL (0x0000035C) +#define TABLA_A_CDC_IIR2_COEF_B3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_IIR1_COEF_B4_CTL (0x0000034D) +#define TABLA_A_CDC_IIR1_COEF_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_COEF_B4_CTL (0x0000035D) +#define TABLA_A_CDC_IIR2_COEF_B4_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_IIR1_COEF_B5_CTL (0x0000034E) +#define TABLA_A_CDC_IIR1_COEF_B5_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_COEF_B5_CTL (0x0000035E) +#define TABLA_A_CDC_IIR2_COEF_B5_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_TOP_GAIN_UPDATE (0x00000360) +#define TABLA_A_CDC_TOP_GAIN_UPDATE__POR (0x00000000) +#define TABLA_A_CDC_DEBUG_B1_CTL (0x00000368) +#define TABLA_A_CDC_DEBUG_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_DEBUG_B2_CTL (0x00000369) +#define TABLA_A_CDC_DEBUG_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_DEBUG_B3_CTL (0x0000036A) +#define TABLA_A_CDC_DEBUG_B3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_DEBUG_B4_CTL (0x0000036B) +#define TABLA_A_CDC_DEBUG_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_DEBUG_B5_CTL (0x0000036C) +#define TABLA_A_CDC_DEBUG_B5_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_DEBUG_B6_CTL (0x0000036D) +#define TABLA_A_CDC_DEBUG_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_COMP1_B1_CTL (0x00000370) +#define TABLA_A_CDC_COMP1_B1_CTL__POR (0x00000030) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_COMP1_B2_CTL (0x00000371) +#define TABLA_A_CDC_COMP1_B2_CTL__POR (0x000000B5) +#define TABLA_A_CDC_COMP1_B3_CTL (0x00000372) +#define TABLA_A_CDC_COMP1_B3_CTL__POR (0x00000028) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_COMP1_B4_CTL (0x00000373) +#define TABLA_A_CDC_COMP1_B4_CTL__POR (0x0000003C) +#define TABLA_A_CDC_COMP1_B5_CTL (0x00000374) +#define TABLA_A_CDC_COMP1_B5_CTL__POR (0x0000001F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_COMP1_B6_CTL (0x00000375) +#define TABLA_A_CDC_COMP1_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_COMP1_SHUT_DOWN_STATUS (0x00000376) +#define TABLA_A_CDC_COMP1_SHUT_DOWN_STATUS__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_COMP1_FS_CFG (0x00000377) +#define TABLA_A_CDC_COMP1_FS_CFG__POR (0x0000001B) +#define TABLA_A_CDC_COMP2_B1_CTL (0x00000378) +#define TABLA_A_CDC_COMP2_B1_CTL__POR (0x00000030) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_COMP2_B2_CTL (0x00000379) +#define TABLA_A_CDC_COMP2_B2_CTL__POR (0x000000B5) +#define TABLA_A_CDC_COMP2_B3_CTL (0x0000037A) +#define TABLA_A_CDC_COMP2_B3_CTL__POR (0x00000028) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_COMP2_B4_CTL (0x0000037B) +#define TABLA_A_CDC_COMP2_B4_CTL__POR (0x0000003C) +#define TABLA_A_CDC_COMP2_B5_CTL (0x0000037C) +#define TABLA_A_CDC_COMP2_B5_CTL__POR (0x0000001F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_COMP2_B6_CTL (0x0000037D) +#define TABLA_A_CDC_COMP2_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_COMP2_SHUT_DOWN_STATUS (0x0000037E) +#define TABLA_A_CDC_COMP2_SHUT_DOWN_STATUS__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_COMP2_FS_CFG (0x0000037F) +#define TABLA_A_CDC_COMP2_FS_CFG__POR (0x0000001B) +#define TABLA_A_CDC_CONN_RX1_B1_CTL (0x00000380) +#define TABLA_A_CDC_CONN_RX1_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_RX1_B2_CTL (0x00000381) +#define TABLA_A_CDC_CONN_RX1_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX1_B3_CTL (0x00000382) +#define TABLA_A_CDC_CONN_RX1_B3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_RX2_B1_CTL (0x00000383) +#define TABLA_A_CDC_CONN_RX2_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX2_B2_CTL (0x00000384) +#define TABLA_A_CDC_CONN_RX2_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_RX2_B3_CTL (0x00000385) +#define TABLA_A_CDC_CONN_RX2_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX3_B1_CTL (0x00000386) +#define TABLA_A_CDC_CONN_RX3_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_RX3_B2_CTL (0x00000387) +#define TABLA_A_CDC_CONN_RX3_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX3_B3_CTL (0x00000388) +#define TABLA_A_CDC_CONN_RX3_B3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_RX4_B1_CTL (0x00000389) +#define TABLA_A_CDC_CONN_RX4_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX4_B2_CTL (0x0000038A) +#define TABLA_A_CDC_CONN_RX4_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_RX5_B1_CTL (0x0000038B) +#define TABLA_A_CDC_CONN_RX5_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX5_B2_CTL (0x0000038C) +#define TABLA_A_CDC_CONN_RX5_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_RX6_B1_CTL (0x0000038D) +#define TABLA_A_CDC_CONN_RX6_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX6_B2_CTL (0x0000038E) +#define TABLA_A_CDC_CONN_RX6_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_RX7_B1_CTL (0x0000038F) +#define TABLA_A_CDC_CONN_RX7_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX7_B2_CTL (0x00000390) +#define TABLA_A_CDC_CONN_RX7_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_ANC_B1_CTL (0x00000391) +#define TABLA_A_CDC_CONN_ANC_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_ANC_B2_CTL (0x00000392) +#define TABLA_A_CDC_CONN_ANC_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_TX_B1_CTL (0x00000393) +#define TABLA_A_CDC_CONN_TX_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_B2_CTL (0x00000394) +#define TABLA_A_CDC_CONN_TX_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_TX_B3_CTL (0x00000395) +#define TABLA_A_CDC_CONN_TX_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_B4_CTL (0x00000396) +#define TABLA_A_CDC_CONN_TX_B4_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_EQ1_B1_CTL (0x00000397) +#define TABLA_A_CDC_CONN_EQ1_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_EQ1_B2_CTL (0x00000398) +#define TABLA_A_CDC_CONN_EQ1_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_EQ1_B3_CTL (0x00000399) +#define TABLA_A_CDC_CONN_EQ1_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_EQ1_B4_CTL (0x0000039A) +#define TABLA_A_CDC_CONN_EQ1_B4_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_EQ2_B1_CTL (0x0000039B) +#define TABLA_A_CDC_CONN_EQ2_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_EQ2_B2_CTL (0x0000039C) +#define TABLA_A_CDC_CONN_EQ2_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_EQ2_B3_CTL (0x0000039D) +#define TABLA_A_CDC_CONN_EQ2_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_EQ2_B4_CTL (0x0000039E) +#define TABLA_A_CDC_CONN_EQ2_B4_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_SRC1_B1_CTL (0x0000039F) +#define TABLA_A_CDC_CONN_SRC1_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_SRC1_B2_CTL (0x000003A0) +#define TABLA_A_CDC_CONN_SRC1_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_SRC2_B1_CTL (0x000003A1) +#define TABLA_A_CDC_CONN_SRC2_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_SRC2_B2_CTL (0x000003A2) +#define TABLA_A_CDC_CONN_SRC2_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_TX_SB_B1_CTL (0x000003A3) +#define TABLA_A_CDC_CONN_TX_SB_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B2_CTL (0x000003A4) +#define TABLA_A_CDC_CONN_TX_SB_B2_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_TX_SB_B3_CTL (0x000003A5) +#define TABLA_A_CDC_CONN_TX_SB_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B4_CTL (0x000003A6) +#define TABLA_A_CDC_CONN_TX_SB_B4_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_TX_SB_B5_CTL (0x000003A7) +#define TABLA_A_CDC_CONN_TX_SB_B5_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B6_CTL (0x000003A8) +#define TABLA_A_CDC_CONN_TX_SB_B6_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_TX_SB_B7_CTL (0x000003A9) +#define TABLA_A_CDC_CONN_TX_SB_B7_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B8_CTL (0x000003AA) +#define TABLA_A_CDC_CONN_TX_SB_B8_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_TX_SB_B9_CTL (0x000003AB) +#define TABLA_A_CDC_CONN_TX_SB_B9_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B10_CTL (0x000003AC) +#define TABLA_A_CDC_CONN_TX_SB_B10_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_TX_SB_B11_CTL (0x000003AD) +#define TABLA_A_CDC_CONN_TX_SB_B11_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX_SB_B1_CTL (0x000003AE) +#define TABLA_A_CDC_CONN_RX_SB_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_RX_SB_B2_CTL (0x000003AF) +#define TABLA_A_CDC_CONN_RX_SB_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_CLSG_CTL (0x000003B0) +#define TABLA_A_CDC_CONN_CLSG_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_CONN_SPARE (0x000003B1) +#define TABLA_A_CDC_CONN_SPARE__POR (0x00000000) +#define TABLA_A_CDC_MBHC_EN_CTL (0x000003C0) +#define TABLA_A_CDC_MBHC_EN_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_MBHC_FEATURE_B1_CFG (0x000003C1) +#define TABLA_A_CDC_MBHC_FEATURE_B1_CFG__POR (0x00000000) +#define TABLA_A_CDC_MBHC_FEATURE_B2_CFG (0x000003C2) +#define TABLA_A_CDC_MBHC_FEATURE_B2_CFG__POR (0x00000006) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_MBHC_TIMER_B1_CTL (0x000003C3) +#define TABLA_A_CDC_MBHC_TIMER_B1_CTL__POR (0x00000003) +#define TABLA_A_CDC_MBHC_TIMER_B2_CTL (0x000003C4) +#define TABLA_A_CDC_MBHC_TIMER_B2_CTL__POR (0x00000009) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_MBHC_TIMER_B3_CTL (0x000003C5) +#define TABLA_A_CDC_MBHC_TIMER_B3_CTL__POR (0x0000001e) +#define TABLA_A_CDC_MBHC_TIMER_B4_CTL (0x000003C6) +#define TABLA_A_CDC_MBHC_TIMER_B4_CTL__POR (0x00000045) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_MBHC_TIMER_B5_CTL (0x000003C7) +#define TABLA_A_CDC_MBHC_TIMER_B5_CTL__POR (0x00000004) +#define TABLA_A_CDC_MBHC_TIMER_B6_CTL (0x000003C8) +#define TABLA_A_CDC_MBHC_TIMER_B6_CTL__POR (0x00000078) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_MBHC_B1_STATUS (0x000003C9) +#define TABLA_A_CDC_MBHC_B1_STATUS__POR (0x00000000) +#define TABLA_A_CDC_MBHC_B2_STATUS (0x000003CA) +#define TABLA_A_CDC_MBHC_B2_STATUS__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_MBHC_B3_STATUS (0x000003CB) +#define TABLA_A_CDC_MBHC_B3_STATUS__POR (0x00000000) +#define TABLA_A_CDC_MBHC_B4_STATUS (0x000003CC) +#define TABLA_A_CDC_MBHC_B4_STATUS__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_MBHC_B5_STATUS (0x000003CD) +#define TABLA_A_CDC_MBHC_B5_STATUS__POR (0x00000000) +#define TABLA_A_CDC_MBHC_B1_CTL (0x000003CE) +#define TABLA_A_CDC_MBHC_B1_CTL__POR (0x000000c0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_MBHC_B2_CTL (0x000003CF) +#define TABLA_A_CDC_MBHC_B2_CTL__POR (0x0000005d) +#define TABLA_A_CDC_MBHC_VOLT_B1_CTL (0x000003D0) +#define TABLA_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_MBHC_VOLT_B2_CTL (0x000003D1) +#define TABLA_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_VOLT_B3_CTL (0x000003D2) +#define TABLA_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_MBHC_VOLT_B4_CTL (0x000003D3) +#define TABLA_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_VOLT_B5_CTL (0x000003D4) +#define TABLA_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_MBHC_VOLT_B6_CTL (0x000003D5) +#define TABLA_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_VOLT_B7_CTL (0x000003D6) +#define TABLA_A_CDC_MBHC_VOLT_B7_CTL__POR (0x000000ff) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_MBHC_VOLT_B8_CTL (0x000003D7) +#define TABLA_A_CDC_MBHC_VOLT_B8_CTL__POR (0x00000007) +#define TABLA_A_CDC_MBHC_VOLT_B9_CTL (0x000003D8) +#define TABLA_A_CDC_MBHC_VOLT_B9_CTL__POR (0x000000ff) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_MBHC_VOLT_B10_CTL (0x000003D9) +#define TABLA_A_CDC_MBHC_VOLT_B10_CTL__POR (0x0000007f) +#define TABLA_A_CDC_MBHC_VOLT_B11_CTL (0x000003DA) +#define TABLA_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_MBHC_VOLT_B12_CTL (0x000003DB) +#define TABLA_A_CDC_MBHC_VOLT_B12_CTL__POR (0x00000080) +#define TABLA_A_CDC_MBHC_CLK_CTL (0x000003DC) +#define TABLA_A_CDC_MBHC_CLK_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_MBHC_INT_CTL (0x000003DD) +#define TABLA_A_CDC_MBHC_INT_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_DEBUG_CTL (0x000003DE) +#define TABLA_A_CDC_MBHC_DEBUG_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_A_CDC_MBHC_SPARE (0x000003DF) +#define TABLA_A_CDC_MBHC_SPARE__POR (0x00000000) +#define TABLA_SLIM_PGD_PORT_INT_EN0 (0x30) +#define TABLA_SLIM_PGD_PORT_INT_STATUS0 (0x34) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_SLIM_PGD_PORT_INT_CLR0 (0x38) +#define TABLA_SLIM_PGD_PORT_INT_SOURCE0 (0x60) +#define TABLA_PACKED_REG_SIZE sizeof(u32) +#define TABLA_CODEC_PACK_ENTRY(reg, mask, val) ((val & 0xff)| ((mask & 0xff) << 8)|((reg & 0xffff) << 16)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_CODEC_UNPACK_ENTRY(packed, reg, mask, val) do { ((reg) = ((packed >> 16) & (0xffff))); ((mask) = ((packed >> 8) & (0xff))); ((val) = ((packed) & (0xff))); } while (0); +#endif + diff --git a/kernel-headers/linux/mfd/wcd9xxx/wcd9320_registers.h b/kernel-headers/linux/mfd/wcd9xxx/wcd9320_registers.h new file mode 100644 index 0000000..c1f70da --- /dev/null +++ b/kernel-headers/linux/mfd/wcd9xxx/wcd9320_registers.h @@ -0,0 +1,1677 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef WCD9320_REGISTERS_H +#define WCD9320_REGISTERS_H +#include <linux/mfd/wcd9xxx/wcd9xxx_registers.h> +#define TAIKO_A_CHIP_CTL WCD9XXX_A_CHIP_CTL +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CHIP_CTL__POR WCD9XXX_A_CHIP_CTL__POR +#define TAIKO_A_CHIP_STATUS WCD9XXX_A_CHIP_STATUS +#define TAIKO_A_CHIP_STATUS__POR WCD9XXX_A_CHIP_STATUS__POR +#define TAIKO_A_CHIP_ID_BYTE_0 WCD9XXX_A_CHIP_ID_BYTE_0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CHIP_ID_BYTE_0__POR WCD9XXX_A_CHIP_ID_BYTE_0__POR +#define TAIKO_A_CHIP_ID_BYTE_1 WCD9XXX_A_CHIP_ID_BYTE_1 +#define TAIKO_A_CHIP_ID_BYTE_1__POR WCD9XXX_A_CHIP_ID_BYTE_1__POR +#define TAIKO_A_CHIP_ID_BYTE_2 WCD9XXX_A_CHIP_ID_BYTE_2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CHIP_ID_BYTE_2__POR WCD9XXX_A_CHIP_ID_BYTE_2__POR +#define TAIKO_A_CHIP_ID_BYTE_3 WCD9XXX_A_CHIP_ID_BYTE_3 +#define TAIKO_A_CHIP_ID_BYTE_3__POR WCD9XXX_A_CHIP_ID_BYTE_3__POR +#define TAIKO_A_CHIP_VERSION WCD9XXX_A_CHIP_VERSION +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CHIP_VERSION__POR WCD9XXX_A_CHIP_VERSION__POR +#define TAIKO_A_SB_VERSION WCD9XXX_A_SB_VERSION +#define TAIKO_A_SB_VERSION__POR WCD9XXX_A_SB_VERSION__POR +#define TAIKO_A_SLAVE_ID_1 WCD9XXX_A_SLAVE_ID_1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SLAVE_ID_1__POR WCD9XXX_A_SLAVE_ID_1__POR +#define TAIKO_A_SLAVE_ID_2 WCD9XXX_A_SLAVE_ID_2 +#define TAIKO_A_SLAVE_ID_2__POR WCD9XXX_A_SLAVE_ID_2__POR +#define TAIKO_A_SLAVE_ID_3 WCD9XXX_A_SLAVE_ID_3 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SLAVE_ID_3__POR WCD9XXX_A_SLAVE_ID_3__POR +#define TAIKO_A_PIN_CTL_OE0 (0x010) +#define TAIKO_A_PIN_CTL_OE0__POR (0x00) +#define TAIKO_A_PIN_CTL_OE1 (0x011) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_PIN_CTL_OE1__POR (0x00) +#define TAIKO_A_PIN_CTL_DATA0 (0x012) +#define TAIKO_A_PIN_CTL_DATA0__POR (0x00) +#define TAIKO_A_PIN_CTL_DATA1 (0x013) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_PIN_CTL_DATA1__POR (0x00) +#define TAIKO_A_HDRIVE_GENERIC (0x018) +#define TAIKO_A_HDRIVE_GENERIC__POR (0x00) +#define TAIKO_A_HDRIVE_OVERRIDE (0x019) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_HDRIVE_OVERRIDE__POR (0x08) +#define TAIKO_A_ANA_CSR_WAIT_STATE (0x020) +#define TAIKO_A_ANA_CSR_WAIT_STATE__POR (0x44) +#define TAIKO_A_PROCESS_MONITOR_CTL0 (0x040) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_PROCESS_MONITOR_CTL0__POR (0x80) +#define TAIKO_A_PROCESS_MONITOR_CTL1 (0x041) +#define TAIKO_A_PROCESS_MONITOR_CTL1__POR (0x00) +#define TAIKO_A_PROCESS_MONITOR_CTL2 (0x042) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_PROCESS_MONITOR_CTL2__POR (0x00) +#define TAIKO_A_PROCESS_MONITOR_CTL3 (0x043) +#define TAIKO_A_PROCESS_MONITOR_CTL3__POR (0x01) +#define TAIKO_A_QFUSE_CTL (0x048) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_QFUSE_CTL__POR (0x00) +#define TAIKO_A_QFUSE_STATUS (0x049) +#define TAIKO_A_QFUSE_STATUS__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT0 (0x04A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_QFUSE_DATA_OUT0__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT1 (0x04B) +#define TAIKO_A_QFUSE_DATA_OUT1__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT2 (0x04C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_QFUSE_DATA_OUT2__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT3 (0x04D) +#define TAIKO_A_QFUSE_DATA_OUT3__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT4 (0x04E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_QFUSE_DATA_OUT4__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT5 (0x04F) +#define TAIKO_A_QFUSE_DATA_OUT5__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT6 (0x050) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_QFUSE_DATA_OUT6__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT7 (0x051) +#define TAIKO_A_QFUSE_DATA_OUT7__POR (0x00) +#define TAIKO_A_CDC_CTL WCD9XXX_A_CDC_CTL +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CTL__POR WCD9XXX_A_CDC_CTL__POR +#define TAIKO_A_LEAKAGE_CTL WCD9XXX_A_LEAKAGE_CTL +#define TAIKO_A_LEAKAGE_CTL__POR WCD9XXX_A_LEAKAGE_CTL__POR +#define TAIKO_A_INTR_MODE (0x090) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_MODE__POR (0x00) +#define TAIKO_A_INTR_MASK0 (0x094) +#define TAIKO_A_INTR_MASK0__POR (0xFF) +#define TAIKO_A_INTR_MASK1 (0x095) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_MASK1__POR (0xFF) +#define TAIKO_A_INTR_MASK2 (0x096) +#define TAIKO_A_INTR_MASK2__POR (0x3F) +#define TAIKO_A_INTR_MASK3 (0x097) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_MASK3__POR (0x3F) +#define TAIKO_A_INTR_STATUS0 (0x098) +#define TAIKO_A_INTR_STATUS0__POR (0x00) +#define TAIKO_A_INTR_STATUS1 (0x099) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_STATUS1__POR (0x00) +#define TAIKO_A_INTR_STATUS2 (0x09A) +#define TAIKO_A_INTR_STATUS2__POR (0x00) +#define TAIKO_A_INTR_STATUS3 (0x09B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_STATUS3__POR (0x00) +#define TAIKO_A_INTR_CLEAR0 (0x09C) +#define TAIKO_A_INTR_CLEAR0__POR (0x00) +#define TAIKO_A_INTR_CLEAR1 (0x09D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_CLEAR1__POR (0x00) +#define TAIKO_A_INTR_CLEAR2 (0x09E) +#define TAIKO_A_INTR_CLEAR2__POR (0x00) +#define TAIKO_A_INTR_CLEAR3 (0x09F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_CLEAR3__POR (0x00) +#define TAIKO_A_INTR_LEVEL0 (0x0A0) +#define TAIKO_A_INTR_LEVEL0__POR (0x01) +#define TAIKO_A_INTR_LEVEL1 (0x0A1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_LEVEL1__POR (0x00) +#define TAIKO_A_INTR_LEVEL2 (0x0A2) +#define TAIKO_A_INTR_LEVEL2__POR (0x00) +#define TAIKO_A_INTR_LEVEL3 (0x0A3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_LEVEL3__POR (0x00) +#define TAIKO_A_INTR_TEST0 (0x0A4) +#define TAIKO_A_INTR_TEST0__POR (0x00) +#define TAIKO_A_INTR_TEST1 (0x0A5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_TEST1__POR (0x00) +#define TAIKO_A_INTR_TEST2 (0x0A6) +#define TAIKO_A_INTR_TEST2__POR (0x00) +#define TAIKO_A_INTR_TEST3 (0x0A7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_TEST3__POR (0x00) +#define TAIKO_A_INTR_SET0 (0x0A8) +#define TAIKO_A_INTR_SET0__POR (0x00) +#define TAIKO_A_INTR_SET1 (0x0A9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_SET1__POR (0x00) +#define TAIKO_A_INTR_SET2 (0x0AA) +#define TAIKO_A_INTR_SET2__POR (0x00) +#define TAIKO_A_INTR_SET3 (0x0AB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_SET3__POR (0x00) +#define TAIKO_A_INTR_DESTN0 (0x0AC) +#define TAIKO_A_INTR_DESTN0__POR (0x00) +#define TAIKO_A_INTR_DESTN1 (0x0AD) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_DESTN1__POR (0x00) +#define TAIKO_A_INTR_DESTN2 (0x0AE) +#define TAIKO_A_INTR_DESTN2__POR (0x00) +#define TAIKO_A_INTR_DESTN3 (0x0AF) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_INTR_DESTN3__POR (0x00) +#define TAIKO_A_CDC_TX_I2S_SCK_MODE (0x0C0) +#define TAIKO_A_CDC_TX_I2S_SCK_MODE__POR (0x00) +#define TAIKO_A_CDC_TX_I2S_WS_MODE (0x0C1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX_I2S_WS_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_DATA0_MODE (0x0C4) +#define TAIKO_A_CDC_DMIC_DATA0_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_CLK0_MODE (0x0C5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_DMIC_CLK0_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_DATA1_MODE (0x0C6) +#define TAIKO_A_CDC_DMIC_DATA1_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_CLK1_MODE (0x0C7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_DMIC_CLK1_MODE__POR (0x00) +#define TAIKO_A_CDC_RX_I2S_SCK_MODE (0x0C8) +#define TAIKO_A_CDC_RX_I2S_SCK_MODE__POR (0x00) +#define TAIKO_A_CDC_RX_I2S_WS_MODE (0x0C9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX_I2S_WS_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_DATA2_MODE (0x0CA) +#define TAIKO_A_CDC_DMIC_DATA2_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_CLK2_MODE (0x0CB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_DMIC_CLK2_MODE__POR (0x00) +#define TAIKO_A_CDC_INTR1_MODE (0x0CC) +#define TAIKO_A_CDC_INTR1_MODE__POR (0x00) +#define TAIKO_A_CDC_SB_NRZ_SEL_MODE (0x0CD) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_SB_NRZ_SEL_MODE__POR (0x00) +#define TAIKO_A_CDC_INTR2_MODE (0x0CE) +#define TAIKO_A_CDC_INTR2_MODE__POR (0x00) +#define TAIKO_A_CDC_RF_PA_ON_MODE (0x0CF) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RF_PA_ON_MODE__POR (0x00) +#define TAIKO_A_BIAS_REF_CTL (0x100) +#define TAIKO_A_BIAS_REF_CTL__POR (0x1C) +#define TAIKO_A_BIAS_CENTRAL_BG_CTL (0x101) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_BIAS_CENTRAL_BG_CTL__POR (0x50) +#define TAIKO_A_BIAS_PRECHRG_CTL (0x102) +#define TAIKO_A_BIAS_PRECHRG_CTL__POR (0x07) +#define TAIKO_A_BIAS_CURR_CTL_1 (0x103) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_BIAS_CURR_CTL_1__POR (0x52) +#define TAIKO_A_BIAS_CURR_CTL_2 (0x104) +#define TAIKO_A_BIAS_CURR_CTL_2__POR (0x00) +#define TAIKO_A_BIAS_OSC_BG_CTL (0x105) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_BIAS_OSC_BG_CTL__POR (0x16) +#define TAIKO_A_CLK_BUFF_EN1 (0x108) +#define TAIKO_A_CLK_BUFF_EN1__POR (0x04) +#define TAIKO_A_CLK_BUFF_EN2 (0x109) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CLK_BUFF_EN2__POR (0x02) +#define TAIKO_A_LDO_H_MODE_1 (0x110) +#define TAIKO_A_LDO_H_MODE_1__POR (0x65) +#define TAIKO_A_LDO_H_MODE_2 (0x111) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_LDO_H_MODE_2__POR (0xA8) +#define TAIKO_A_LDO_H_LOOP_CTL (0x112) +#define TAIKO_A_LDO_H_LOOP_CTL__POR (0x6B) +#define TAIKO_A_LDO_H_COMP_1 (0x113) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_LDO_H_COMP_1__POR (0x84) +#define TAIKO_A_LDO_H_COMP_2 (0x114) +#define TAIKO_A_LDO_H_COMP_2__POR (0xE0) +#define TAIKO_A_LDO_H_BIAS_1 (0x115) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_LDO_H_BIAS_1__POR (0x6D) +#define TAIKO_A_LDO_H_BIAS_2 (0x116) +#define TAIKO_A_LDO_H_BIAS_2__POR (0xA5) +#define TAIKO_A_LDO_H_BIAS_3 (0x117) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_LDO_H_BIAS_3__POR (0x60) +#define TAIKO_A_VBAT_CLK (0x118) +#define TAIKO_A_VBAT_CLK__POR (0x03) +#define TAIKO_A_VBAT_LOOP (0x119) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_VBAT_LOOP__POR (0x02) +#define TAIKO_A_VBAT_REF (0x11A) +#define TAIKO_A_VBAT_REF__POR (0x20) +#define TAIKO_A_VBAT_ADC_TEST (0x11B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_VBAT_ADC_TEST__POR (0x00) +#define TAIKO_A_VBAT_FE (0x11C) +#define TAIKO_A_VBAT_FE__POR (0x48) +#define TAIKO_A_VBAT_BIAS_1 (0x11D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_VBAT_BIAS_1__POR (0x03) +#define TAIKO_A_VBAT_BIAS_2 (0x11E) +#define TAIKO_A_VBAT_BIAS_2__POR (0x00) +#define TAIKO_A_VBAT_ADC_DATA_MSB (0x11F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_VBAT_ADC_DATA_MSB__POR (0x00) +#define TAIKO_A_VBAT_ADC_DATA_LSB (0x120) +#define TAIKO_A_VBAT_ADC_DATA_LSB__POR (0x00) +#define TAIKO_A_MICB_CFILT_1_CTL (0x128) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MICB_CFILT_1_CTL__POR (0x40) +#define TAIKO_A_MICB_CFILT_1_VAL (0x129) +#define TAIKO_A_MICB_CFILT_1_VAL__POR (0x80) +#define TAIKO_A_MICB_CFILT_1_PRECHRG (0x12A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MICB_CFILT_1_PRECHRG__POR (0x38) +#define TAIKO_A_MICB_1_CTL (0x12B) +#define TAIKO_A_MICB_1_CTL__POR (0x16) +#define TAIKO_A_MICB_1_INT_RBIAS (0x12C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MICB_1_INT_RBIAS__POR (0x24) +#define TAIKO_A_MICB_1_MBHC (0x12D) +#define TAIKO_A_MICB_1_MBHC__POR (0x01) +#define TAIKO_A_MICB_CFILT_2_CTL (0x12E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MICB_CFILT_2_CTL__POR (0x40) +#define TAIKO_A_MICB_CFILT_2_VAL (0x12F) +#define TAIKO_A_MICB_CFILT_2_VAL__POR (0x80) +#define TAIKO_A_MICB_CFILT_2_PRECHRG (0x130) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MICB_CFILT_2_PRECHRG__POR (0x38) +#define TAIKO_A_MICB_2_CTL (0x131) +#define TAIKO_A_MICB_2_CTL__POR (0x16) +#define TAIKO_A_MICB_2_INT_RBIAS (0x132) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MICB_2_INT_RBIAS__POR (0x24) +#define TAIKO_A_MICB_2_MBHC (0x133) +#define TAIKO_A_MICB_2_MBHC__POR (0x02) +#define TAIKO_A_MICB_CFILT_3_CTL (0x134) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MICB_CFILT_3_CTL__POR (0x40) +#define TAIKO_A_MICB_CFILT_3_VAL (0x135) +#define TAIKO_A_MICB_CFILT_3_VAL__POR (0x80) +#define TAIKO_A_MICB_CFILT_3_PRECHRG (0x136) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MICB_CFILT_3_PRECHRG__POR (0x38) +#define TAIKO_A_MICB_3_CTL (0x137) +#define TAIKO_A_MICB_3_CTL__POR (0x16) +#define TAIKO_A_MICB_3_INT_RBIAS (0x138) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MICB_3_INT_RBIAS__POR (0x24) +#define TAIKO_A_MICB_3_MBHC (0x139) +#define TAIKO_A_MICB_3_MBHC__POR (0x00) +#define TAIKO_A_MICB_4_CTL (0x13D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MICB_4_CTL__POR (0x16) +#define TAIKO_A_MICB_4_INT_RBIAS (0x13E) +#define TAIKO_A_MICB_4_INT_RBIAS__POR (0x24) +#define TAIKO_A_MICB_4_MBHC (0x13F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MICB_4_MBHC__POR (0x01) +#define TAIKO_A_MBHC_INSERT_DETECT (0x14A) +#define TAIKO_A_MBHC_INSERT_DETECT__POR (0x00) +#define TAIKO_A_MBHC_INSERT_DET_STATUS (0x14B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MBHC_INSERT_DET_STATUS__POR (0x00) +#define TAIKO_A_TX_COM_BIAS (0x14C) +#define TAIKO_A_TX_COM_BIAS__POR (0xF0) +#define TAIKO_A_MBHC_SCALING_MUX_1 (0x14E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MBHC_SCALING_MUX_1__POR (0x00) +#define TAIKO_A_MBHC_SCALING_MUX_2 (0x14F) +#define TAIKO_A_MBHC_SCALING_MUX_2__POR (0x80) +#define TAIKO_A_MAD_ANA_CTRL (0x150) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MAD_ANA_CTRL__POR (0xF1) +#define TAIKO_A_TX_SUP_SWITCH_CTRL_1 (0x151) +#define TAIKO_A_TX_SUP_SWITCH_CTRL_1__POR (0x00) +#define TAIKO_A_TX_SUP_SWITCH_CTRL_2 (0x152) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_SUP_SWITCH_CTRL_2__POR (0x80) +#define TAIKO_A_TX_1_2_EN (0x153) +#define TAIKO_A_TX_1_2_EN__POR (0x00) +#define TAIKO_A_TX_1_2_TEST_EN (0x154) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_1_2_TEST_EN__POR (0xCC) +#define TAIKO_A_TX_1_2_ADC_CH1 (0x155) +#define TAIKO_A_TX_1_2_ADC_CH1__POR (0x44) +#define TAIKO_A_TX_1_2_ADC_CH2 (0x156) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_1_2_ADC_CH2__POR (0x44) +#define TAIKO_A_TX_1_2_ATEST_REFCTRL (0x157) +#define TAIKO_A_TX_1_2_ATEST_REFCTRL__POR (0x00) +#define TAIKO_A_TX_1_2_TEST_CTL (0x158) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_1_2_TEST_CTL__POR (0x38) +#define TAIKO_A_TX_1_2_TEST_BLOCK_EN (0x159) +#define TAIKO_A_TX_1_2_TEST_BLOCK_EN__POR (0xFC) +#define TAIKO_A_TX_1_2_TXFE_CLKDIV (0x15A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_1_2_TXFE_CLKDIV__POR (0x55) +#define TAIKO_A_TX_1_2_SAR_ERR_CH1 (0x15B) +#define TAIKO_A_TX_1_2_SAR_ERR_CH1__POR (0x00) +#define TAIKO_A_TX_1_2_SAR_ERR_CH2 (0x15C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_1_2_SAR_ERR_CH2__POR (0x00) +#define TAIKO_A_TX_3_4_EN (0x15D) +#define TAIKO_A_TX_3_4_EN__POR (0x00) +#define TAIKO_A_TX_3_4_TEST_EN (0x15E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_3_4_TEST_EN__POR (0xCC) +#define TAIKO_A_TX_3_4_ADC_CH3 (0x15F) +#define TAIKO_A_TX_3_4_ADC_CH3__POR (0x44) +#define TAIKO_A_TX_3_4_ADC_CH4 (0x160) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_3_4_ADC_CH4__POR (0x44) +#define TAIKO_A_TX_3_4_ATEST_REFCTRL (0x161) +#define TAIKO_A_TX_3_4_ATEST_REFCTRL__POR (0x00) +#define TAIKO_A_TX_3_4_TEST_CTL (0x162) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_3_4_TEST_CTL__POR (0x38) +#define TAIKO_A_TX_3_4_TEST_BLOCK_EN (0x163) +#define TAIKO_A_TX_3_4_TEST_BLOCK_EN__POR (0xFC) +#define TAIKO_A_TX_3_4_TXFE_CKDIV (0x164) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_3_4_TXFE_CKDIV__POR (0x55) +#define TAIKO_A_TX_3_4_SAR_ERR_CH3 (0x165) +#define TAIKO_A_TX_3_4_SAR_ERR_CH3__POR (0x00) +#define TAIKO_A_TX_3_4_SAR_ERR_CH4 (0x166) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_3_4_SAR_ERR_CH4__POR (0x00) +#define TAIKO_A_TX_5_6_EN (0x167) +#define TAIKO_A_TX_5_6_EN__POR (0x11) +#define TAIKO_A_TX_5_6_TEST_EN (0x168) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_5_6_TEST_EN__POR (0xCC) +#define TAIKO_A_TX_5_6_ADC_CH5 (0x169) +#define TAIKO_A_TX_5_6_ADC_CH5__POR (0x44) +#define TAIKO_A_TX_5_6_ADC_CH6 (0x16A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_5_6_ADC_CH6__POR (0x44) +#define TAIKO_A_TX_5_6_ATEST_REFCTRL (0x16B) +#define TAIKO_A_TX_5_6_ATEST_REFCTRL__POR (0x00) +#define TAIKO_A_TX_5_6_TEST_CTL (0x16C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_5_6_TEST_CTL__POR (0x38) +#define TAIKO_A_TX_5_6_TEST_BLOCK_EN (0x16D) +#define TAIKO_A_TX_5_6_TEST_BLOCK_EN__POR (0xFC) +#define TAIKO_A_TX_5_6_TXFE_CKDIV (0x16E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_5_6_TXFE_CKDIV__POR (0x55) +#define TAIKO_A_TX_5_6_SAR_ERR_CH5 (0x16F) +#define TAIKO_A_TX_5_6_SAR_ERR_CH5__POR (0x00) +#define TAIKO_A_TX_5_6_SAR_ERR_CH6 (0x170) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_5_6_SAR_ERR_CH6__POR (0x00) +#define TAIKO_A_TX_7_MBHC_EN (0x171) +#define TAIKO_A_TX_7_MBHC_EN__POR (0x0C) +#define TAIKO_A_TX_7_MBHC_ATEST_REFCTRL (0x172) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_7_MBHC_ATEST_REFCTRL__POR (0x00) +#define TAIKO_A_TX_7_MBHC_ADC (0x173) +#define TAIKO_A_TX_7_MBHC_ADC__POR (0x44) +#define TAIKO_A_TX_7_MBHC_TEST_CTL (0x174) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_7_MBHC_TEST_CTL__POR (0x38) +#define TAIKO_A_TX_7_MBHC_SAR_ERR (0x175) +#define TAIKO_A_TX_7_MBHC_SAR_ERR__POR (0x00) +#define TAIKO_A_TX_7_TXFE_CLKDIV (0x176) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_TX_7_TXFE_CLKDIV__POR (0x0B) +#define TAIKO_A_BUCK_MODE_1 (0x181) +#define TAIKO_A_BUCK_MODE_1__POR (0x21) +#define TAIKO_A_BUCK_MODE_2 (0x182) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_BUCK_MODE_2__POR (0xFF) +#define TAIKO_A_BUCK_MODE_3 (0x183) +#define TAIKO_A_BUCK_MODE_3__POR (0xCC) +#define TAIKO_A_BUCK_MODE_4 (0x184) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_BUCK_MODE_4__POR (0x3A) +#define TAIKO_A_BUCK_MODE_5 (0x185) +#define TAIKO_A_BUCK_MODE_5__POR (0x00) +#define TAIKO_A_BUCK_CTRL_VCL_1 (0x186) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_BUCK_CTRL_VCL_1__POR (0x48) +#define TAIKO_A_BUCK_CTRL_VCL_2 (0x187) +#define TAIKO_A_BUCK_CTRL_VCL_2__POR (0xA3) +#define TAIKO_A_BUCK_CTRL_VCL_3 (0x188) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_BUCK_CTRL_VCL_3__POR (0x82) +#define TAIKO_A_BUCK_CTRL_CCL_1 (0x189) +#define TAIKO_A_BUCK_CTRL_CCL_1__POR (0xAB) +#define TAIKO_A_BUCK_CTRL_CCL_2 (0x18A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_BUCK_CTRL_CCL_2__POR (0xDC) +#define TAIKO_A_BUCK_CTRL_CCL_3 (0x18B) +#define TAIKO_A_BUCK_CTRL_CCL_3__POR (0x6A) +#define TAIKO_A_BUCK_CTRL_CCL_4 (0x18C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_BUCK_CTRL_CCL_4__POR (0x58) +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_1 (0x18D) +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_1__POR (0x50) +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_2 (0x18E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_2__POR (0x64) +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_3 (0x18F) +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_3__POR (0x77) +#define TAIKO_A_BUCK_TMUX_A_D (0x190) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_BUCK_TMUX_A_D__POR (0x00) +#define TAIKO_A_NCP_BUCKREF (0x191) +#define TAIKO_A_NCP_BUCKREF__POR (0x00) +#define TAIKO_A_NCP_EN (0x192) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_NCP_EN__POR (0xFE) +#define TAIKO_A_NCP_CLK (0x193) +#define TAIKO_A_NCP_CLK__POR (0x94) +#define TAIKO_A_NCP_STATIC (0x194) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_NCP_STATIC__POR (0x28) +#define TAIKO_A_NCP_VTH_LOW (0x195) +#define TAIKO_A_NCP_VTH_LOW__POR (0x88) +#define TAIKO_A_NCP_VTH_HIGH (0x196) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_NCP_VTH_HIGH__POR (0xA0) +#define TAIKO_A_NCP_ATEST (0x197) +#define TAIKO_A_NCP_ATEST__POR (0x00) +#define TAIKO_A_NCP_DTEST (0x198) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_NCP_DTEST__POR (0x00) +#define TAIKO_A_NCP_DLY1 (0x199) +#define TAIKO_A_NCP_DLY1__POR (0x06) +#define TAIKO_A_NCP_DLY2 (0x19A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_NCP_DLY2__POR (0x06) +#define TAIKO_A_RX_AUX_SW_CTL (0x19B) +#define TAIKO_A_RX_AUX_SW_CTL__POR (0x00) +#define TAIKO_A_RX_PA_AUX_IN_CONN (0x19C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_PA_AUX_IN_CONN__POR (0x00) +#define TAIKO_A_RX_COM_TIMER_DIV (0x19E) +#define TAIKO_A_RX_COM_TIMER_DIV__POR (0xE8) +#define TAIKO_A_RX_COM_OCP_CTL (0x19F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_COM_OCP_CTL__POR (0x1F) +#define TAIKO_A_RX_COM_OCP_COUNT (0x1A0) +#define TAIKO_A_RX_COM_OCP_COUNT__POR (0x77) +#define TAIKO_A_RX_COM_DAC_CTL (0x1A1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_COM_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_COM_BIAS (0x1A2) +#define TAIKO_A_RX_COM_BIAS__POR (0x00) +#define TAIKO_A_RX_HPH_AUTO_CHOP (0x1A4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_HPH_AUTO_CHOP__POR (0x38) +#define TAIKO_A_RX_HPH_CHOP_CTL (0x1A5) +#define TAIKO_A_RX_HPH_CHOP_CTL__POR (0xB4) +#define TAIKO_A_RX_HPH_BIAS_PA (0x1A6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_HPH_BIAS_PA__POR (0xAA) +#define TAIKO_A_RX_HPH_BIAS_LDO (0x1A7) +#define TAIKO_A_RX_HPH_BIAS_LDO__POR (0x87) +#define TAIKO_A_RX_HPH_BIAS_CNP (0x1A8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_HPH_BIAS_CNP__POR (0x8A) +#define TAIKO_A_RX_HPH_BIAS_WG_OCP (0x1A9) +#define TAIKO_A_RX_HPH_BIAS_WG_OCP__POR (0x2A) +#define TAIKO_A_RX_HPH_OCP_CTL (0x1AA) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_HPH_OCP_CTL__POR (0x68) +#define TAIKO_A_RX_HPH_CNP_EN (0x1AB) +#define TAIKO_A_RX_HPH_CNP_EN__POR (0x80) +#define TAIKO_A_RX_HPH_CNP_WG_CTL (0x1AC) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_HPH_CNP_WG_CTL__POR (0xDE) +#define TAIKO_A_RX_HPH_CNP_WG_TIME (0x1AD) +#define TAIKO_A_RX_HPH_CNP_WG_TIME__POR (0x2A) +#define TAIKO_A_RX_HPH_L_GAIN (0x1AE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_HPH_L_GAIN__POR (0x00) +#define TAIKO_A_RX_HPH_L_TEST (0x1AF) +#define TAIKO_A_RX_HPH_L_TEST__POR (0x00) +#define TAIKO_A_RX_HPH_L_PA_CTL (0x1B0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_HPH_L_PA_CTL__POR (0x40) +#define TAIKO_A_RX_HPH_L_DAC_CTL (0x1B1) +#define TAIKO_A_RX_HPH_L_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_HPH_L_ATEST (0x1B2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_HPH_L_ATEST__POR (0x00) +#define TAIKO_A_RX_HPH_L_STATUS (0x1B3) +#define TAIKO_A_RX_HPH_L_STATUS__POR (0x00) +#define TAIKO_A_RX_HPH_R_GAIN (0x1B4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_HPH_R_GAIN__POR (0x00) +#define TAIKO_A_RX_HPH_R_TEST (0x1B5) +#define TAIKO_A_RX_HPH_R_TEST__POR (0x00) +#define TAIKO_A_RX_HPH_R_PA_CTL (0x1B6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_HPH_R_PA_CTL__POR (0x40) +#define TAIKO_A_RX_HPH_R_DAC_CTL (0x1B7) +#define TAIKO_A_RX_HPH_R_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_HPH_R_ATEST (0x1B8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_HPH_R_ATEST__POR (0x00) +#define TAIKO_A_RX_HPH_R_STATUS (0x1B9) +#define TAIKO_A_RX_HPH_R_STATUS__POR (0x00) +#define TAIKO_A_RX_EAR_BIAS_PA (0x1BA) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_EAR_BIAS_PA__POR (0xA6) +#define TAIKO_A_RX_EAR_BIAS_CMBUFF (0x1BB) +#define TAIKO_A_RX_EAR_BIAS_CMBUFF__POR (0xA0) +#define TAIKO_A_RX_EAR_EN (0x1BC) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_EAR_EN__POR (0x00) +#define TAIKO_A_RX_EAR_GAIN (0x1BD) +#define TAIKO_A_RX_EAR_GAIN__POR (0x02) +#define TAIKO_A_RX_EAR_CMBUFF (0x1BE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_EAR_CMBUFF__POR (0x04) +#define TAIKO_A_RX_EAR_ICTL (0x1BF) +#define TAIKO_A_RX_EAR_ICTL__POR (0x40) +#define TAIKO_A_RX_EAR_CCOMP (0x1C0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_EAR_CCOMP__POR (0x08) +#define TAIKO_A_RX_EAR_VCM (0x1C1) +#define TAIKO_A_RX_EAR_VCM__POR (0x03) +#define TAIKO_A_RX_EAR_CNP (0x1C2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_EAR_CNP__POR (0xF2) +#define TAIKO_A_RX_EAR_DAC_CTL_ATEST (0x1C3) +#define TAIKO_A_RX_EAR_DAC_CTL_ATEST__POR (0x00) +#define TAIKO_A_RX_EAR_STATUS (0x1C5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_EAR_STATUS__POR (0x04) +#define TAIKO_A_RX_LINE_BIAS_PA (0x1C6) +#define TAIKO_A_RX_LINE_BIAS_PA__POR (0xA8) +#define TAIKO_A_RX_BUCK_BIAS1 (0x1C7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_BUCK_BIAS1__POR (0x42) +#define TAIKO_A_RX_BUCK_BIAS2 (0x1C8) +#define TAIKO_A_RX_BUCK_BIAS2__POR (0x84) +#define TAIKO_A_RX_LINE_COM (0x1C9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_LINE_COM__POR (0x80) +#define TAIKO_A_RX_LINE_CNP_EN (0x1CA) +#define TAIKO_A_RX_LINE_CNP_EN__POR (0x00) +#define TAIKO_A_RX_LINE_CNP_WG_CTL (0x1CB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_LINE_CNP_WG_CTL__POR (0x00) +#define TAIKO_A_RX_LINE_CNP_WG_TIME (0x1CC) +#define TAIKO_A_RX_LINE_CNP_WG_TIME__POR (0x04) +#define TAIKO_A_RX_LINE_1_GAIN (0x1CD) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_LINE_1_GAIN__POR (0x00) +#define TAIKO_A_RX_LINE_1_TEST (0x1CE) +#define TAIKO_A_RX_LINE_1_TEST__POR (0x00) +#define TAIKO_A_RX_LINE_1_DAC_CTL (0x1CF) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_LINE_1_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_LINE_1_STATUS (0x1D0) +#define TAIKO_A_RX_LINE_1_STATUS__POR (0x00) +#define TAIKO_A_RX_LINE_2_GAIN (0x1D1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_LINE_2_GAIN__POR (0x00) +#define TAIKO_A_RX_LINE_2_TEST (0x1D2) +#define TAIKO_A_RX_LINE_2_TEST__POR (0x00) +#define TAIKO_A_RX_LINE_2_DAC_CTL (0x1D3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_LINE_2_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_LINE_2_STATUS (0x1D4) +#define TAIKO_A_RX_LINE_2_STATUS__POR (0x00) +#define TAIKO_A_RX_LINE_3_GAIN (0x1D5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_LINE_3_GAIN__POR (0x00) +#define TAIKO_A_RX_LINE_3_TEST (0x1D6) +#define TAIKO_A_RX_LINE_3_TEST__POR (0x00) +#define TAIKO_A_RX_LINE_3_DAC_CTL (0x1D7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_LINE_3_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_LINE_3_STATUS (0x1D8) +#define TAIKO_A_RX_LINE_3_STATUS__POR (0x00) +#define TAIKO_A_RX_LINE_4_GAIN (0x1D9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_LINE_4_GAIN__POR (0x00) +#define TAIKO_A_RX_LINE_4_TEST (0x1DA) +#define TAIKO_A_RX_LINE_4_TEST__POR (0x00) +#define TAIKO_A_RX_LINE_4_DAC_CTL (0x1DB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_LINE_4_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_LINE_4_STATUS (0x1DC) +#define TAIKO_A_RX_LINE_4_STATUS__POR (0x00) +#define TAIKO_A_RX_LINE_CNP_DBG (0x1DD) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RX_LINE_CNP_DBG__POR (0x00) +#define TAIKO_A_SPKR_DRV_EN (0x1DF) +#define TAIKO_A_SPKR_DRV_EN__POR (0x6F) +#define TAIKO_A_SPKR_DRV_GAIN (0x1E0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_DRV_GAIN__POR (0x00) +#define TAIKO_A_SPKR_DRV_DAC_CTL (0x1E1) +#define TAIKO_A_SPKR_DRV_DAC_CTL__POR (0x04) +#define TAIKO_A_SPKR_DRV_OCP_CTL (0x1E2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_DRV_OCP_CTL__POR (0x98) +#define TAIKO_A_SPKR_DRV_CLIP_DET (0x1E3) +#define TAIKO_A_SPKR_DRV_CLIP_DET__POR (0x48) +#define TAIKO_A_SPKR_DRV_IEC (0x1E4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_DRV_IEC__POR (0x20) +#define TAIKO_A_SPKR_DRV_DBG_DAC (0x1E5) +#define TAIKO_A_SPKR_DRV_DBG_DAC__POR (0x05) +#define TAIKO_A_SPKR_DRV_DBG_PA (0x1E6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_DRV_DBG_PA__POR (0x18) +#define TAIKO_A_SPKR_DRV_DBG_PWRSTG (0x1E7) +#define TAIKO_A_SPKR_DRV_DBG_PWRSTG__POR (0x00) +#define TAIKO_A_SPKR_DRV_BIAS_LDO (0x1E8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_DRV_BIAS_LDO__POR (0x45) +#define TAIKO_A_SPKR_DRV_BIAS_INT (0x1E9) +#define TAIKO_A_SPKR_DRV_BIAS_INT__POR (0xA5) +#define TAIKO_A_SPKR_DRV_BIAS_PA (0x1EA) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_DRV_BIAS_PA__POR (0x55) +#define TAIKO_A_SPKR_DRV_STATUS_OCP (0x1EB) +#define TAIKO_A_SPKR_DRV_STATUS_OCP__POR (0x00) +#define TAIKO_A_SPKR_DRV_STATUS_PA (0x1EC) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_DRV_STATUS_PA__POR (0x00) +#define TAIKO_A_SPKR_PROT_EN (0x1ED) +#define TAIKO_A_SPKR_PROT_EN__POR (0x00) +#define TAIKO_A_SPKR_PROT_ADC_EN (0x1EE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_PROT_ADC_EN__POR (0x44) +#define TAIKO_A_SPKR_PROT_ISENSE_BIAS (0x1EF) +#define TAIKO_A_SPKR_PROT_ISENSE_BIAS__POR (0x44) +#define TAIKO_A_SPKR_PROT_VSENSE_BIAS (0x1F0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_PROT_VSENSE_BIAS__POR (0x44) +#define TAIKO_A_SPKR_PROT_ADC_ATEST_REFCTRL (0x1F1) +#define TAIKO_A_SPKR_PROT_ADC_ATEST_REFCTRL__POR (0x00) +#define TAIKO_A_SPKR_PROT_ADC_TEST_CTL (0x1F2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_PROT_ADC_TEST_CTL__POR (0x38) +#define TAIKO_A_SPKR_PROT_TEST_BLOCK_EN (0x1F3) +#define TAIKO_A_SPKR_PROT_TEST_BLOCK_EN__POR (0xFC) +#define TAIKO_A_SPKR_PROT_ATEST (0x1F4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_PROT_ATEST__POR (0x00) +#define TAIKO_A_SPKR_PROT_V_SAR_ERR (0x1F5) +#define TAIKO_A_SPKR_PROT_V_SAR_ERR__POR (0x00) +#define TAIKO_A_SPKR_PROT_I_SAR_ERR (0x1F6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_PROT_I_SAR_ERR__POR (0x00) +#define TAIKO_A_SPKR_PROT_LDO_CTRL (0x1F7) +#define TAIKO_A_SPKR_PROT_LDO_CTRL__POR (0x00) +#define TAIKO_A_SPKR_PROT_ISENSE_CTRL (0x1F8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_SPKR_PROT_ISENSE_CTRL__POR (0x00) +#define TAIKO_A_SPKR_PROT_VSENSE_CTRL (0x1F9) +#define TAIKO_A_SPKR_PROT_VSENSE_CTRL__POR (0x00) +#define TAIKO_A_RC_OSC_FREQ (0x1FA) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RC_OSC_FREQ__POR (0x46) +#define TAIKO_A_RC_OSC_TEST (0x1FB) +#define TAIKO_A_RC_OSC_TEST__POR (0x0A) +#define TAIKO_A_RC_OSC_STATUS (0x1FC) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_RC_OSC_STATUS__POR (0x18) +#define TAIKO_A_RC_OSC_TUNER (0x1FD) +#define TAIKO_A_RC_OSC_TUNER__POR (0x00) +#define TAIKO_A_MBHC_HPH (0x1FE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_MBHC_HPH__POR (0x44) +#define TAIKO_A_CDC_ANC1_B1_CTL (0x200) +#define TAIKO_A_CDC_ANC1_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_B1_CTL (0x280) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_SHIFT (0x201) +#define TAIKO_A_CDC_ANC1_SHIFT__POR (0x00) +#define TAIKO_A_CDC_ANC2_SHIFT (0x281) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_SHIFT__POR (0x00) +#define TAIKO_A_CDC_ANC1_IIR_B1_CTL (0x202) +#define TAIKO_A_CDC_ANC1_IIR_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_IIR_B1_CTL (0x282) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_IIR_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_IIR_B2_CTL (0x203) +#define TAIKO_A_CDC_ANC1_IIR_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_IIR_B2_CTL (0x283) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_IIR_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_IIR_B3_CTL (0x204) +#define TAIKO_A_CDC_ANC1_IIR_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_IIR_B3_CTL (0x284) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_IIR_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_LPF_B1_CTL (0x206) +#define TAIKO_A_CDC_ANC1_LPF_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_LPF_B1_CTL (0x286) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_LPF_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_LPF_B2_CTL (0x207) +#define TAIKO_A_CDC_ANC1_LPF_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_LPF_B2_CTL (0x287) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_LPF_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_SPARE (0x209) +#define TAIKO_A_CDC_ANC1_SPARE__POR (0x00) +#define TAIKO_A_CDC_ANC2_SPARE (0x289) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_SPARE__POR (0x00) +#define TAIKO_A_CDC_ANC1_SMLPF_CTL (0x20A) +#define TAIKO_A_CDC_ANC1_SMLPF_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_SMLPF_CTL (0x28A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_SMLPF_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_DCFLT_CTL (0x20B) +#define TAIKO_A_CDC_ANC1_DCFLT_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_DCFLT_CTL (0x28B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_DCFLT_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_GAIN_CTL (0x20C) +#define TAIKO_A_CDC_ANC1_GAIN_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_GAIN_CTL (0x28C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_GAIN_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_B2_CTL (0x20D) +#define TAIKO_A_CDC_ANC1_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_B2_CTL (0x28D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_ANC2_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_TX1_VOL_CTL_TIMER (0x220) +#define TAIKO_A_CDC_TX1_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX2_VOL_CTL_TIMER (0x228) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX2_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX3_VOL_CTL_TIMER (0x230) +#define TAIKO_A_CDC_TX3_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX4_VOL_CTL_TIMER (0x238) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX4_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX5_VOL_CTL_TIMER (0x240) +#define TAIKO_A_CDC_TX5_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX6_VOL_CTL_TIMER (0x248) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX6_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX7_VOL_CTL_TIMER (0x250) +#define TAIKO_A_CDC_TX7_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX8_VOL_CTL_TIMER (0x258) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX8_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX9_VOL_CTL_TIMER (0x260) +#define TAIKO_A_CDC_TX9_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX10_VOL_CTL_TIMER (0x268) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX10_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX1_VOL_CTL_GAIN (0x221) +#define TAIKO_A_CDC_TX1_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX2_VOL_CTL_GAIN (0x229) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX2_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX3_VOL_CTL_GAIN (0x231) +#define TAIKO_A_CDC_TX3_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX4_VOL_CTL_GAIN (0x239) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX4_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX5_VOL_CTL_GAIN (0x241) +#define TAIKO_A_CDC_TX5_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX6_VOL_CTL_GAIN (0x249) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX6_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX7_VOL_CTL_GAIN (0x251) +#define TAIKO_A_CDC_TX7_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX8_VOL_CTL_GAIN (0x259) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX8_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX9_VOL_CTL_GAIN (0x261) +#define TAIKO_A_CDC_TX9_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX10_VOL_CTL_GAIN (0x269) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX10_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX1_VOL_CTL_CFG (0x222) +#define TAIKO_A_CDC_TX1_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX2_VOL_CTL_CFG (0x22A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX2_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX3_VOL_CTL_CFG (0x232) +#define TAIKO_A_CDC_TX3_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX4_VOL_CTL_CFG (0x23A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX4_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX5_VOL_CTL_CFG (0x242) +#define TAIKO_A_CDC_TX5_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX6_VOL_CTL_CFG (0x24A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX6_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX7_VOL_CTL_CFG (0x252) +#define TAIKO_A_CDC_TX7_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX8_VOL_CTL_CFG (0x25A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX8_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX9_VOL_CTL_CFG (0x262) +#define TAIKO_A_CDC_TX9_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX10_VOL_CTL_CFG (0x26A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX10_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX1_MUX_CTL (0x223) +#define TAIKO_A_CDC_TX1_MUX_CTL__POR (0x00) +#define TAIKO_A_CDC_TX2_MUX_CTL (0x22B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX2_MUX_CTL__POR (0x00) +#define TAIKO_A_CDC_TX3_MUX_CTL (0x233) +#define TAIKO_A_CDC_TX3_MUX_CTL__POR (0x00) +#define TAIKO_A_CDC_TX4_MUX_CTL (0x23B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX4_MUX_CTL__POR (0x00) +#define TAIKO_A_CDC_TX5_MUX_CTL (0x243) +#define TAIKO_A_CDC_TX5_MUX_CTL__POR (0x00) +#define TAIKO_A_CDC_TX6_MUX_CTL (0x24B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX6_MUX_CTL__POR (0x00) +#define TAIKO_A_CDC_TX7_MUX_CTL (0x253) +#define TAIKO_A_CDC_TX7_MUX_CTL__POR (0x00) +#define TAIKO_A_CDC_TX8_MUX_CTL (0x25B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX8_MUX_CTL__POR (0x00) +#define TAIKO_A_CDC_TX9_MUX_CTL (0x263) +#define TAIKO_A_CDC_TX9_MUX_CTL__POR (0x00) +#define TAIKO_A_CDC_TX10_MUX_CTL (0x26B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX10_MUX_CTL__POR (0x00) +#define TAIKO_A_CDC_TX1_CLK_FS_CTL (0x224) +#define TAIKO_A_CDC_TX1_CLK_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_TX2_CLK_FS_CTL (0x22C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX2_CLK_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_TX3_CLK_FS_CTL (0x234) +#define TAIKO_A_CDC_TX3_CLK_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_TX4_CLK_FS_CTL (0x23C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX4_CLK_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_TX5_CLK_FS_CTL (0x244) +#define TAIKO_A_CDC_TX5_CLK_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_TX6_CLK_FS_CTL (0x24C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX6_CLK_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_TX7_CLK_FS_CTL (0x254) +#define TAIKO_A_CDC_TX7_CLK_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_TX8_CLK_FS_CTL (0x25C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX8_CLK_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_TX9_CLK_FS_CTL (0x264) +#define TAIKO_A_CDC_TX9_CLK_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_TX10_CLK_FS_CTL (0x26C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX10_CLK_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_TX1_DMIC_CTL (0x225) +#define TAIKO_A_CDC_TX1_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX2_DMIC_CTL (0x22D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX2_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX3_DMIC_CTL (0x235) +#define TAIKO_A_CDC_TX3_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX4_DMIC_CTL (0x23D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX4_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX5_DMIC_CTL (0x245) +#define TAIKO_A_CDC_TX5_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX6_DMIC_CTL (0x24D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX6_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX7_DMIC_CTL (0x255) +#define TAIKO_A_CDC_TX7_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX8_DMIC_CTL (0x25D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX8_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX9_DMIC_CTL (0x265) +#define TAIKO_A_CDC_TX9_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX10_DMIC_CTL (0x26D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_TX10_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B1_CTL (0x278) +#define TAIKO_A_CDC_DEBUG_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B2_CTL (0x279) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_DEBUG_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B3_CTL (0x27A) +#define TAIKO_A_CDC_DEBUG_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B4_CTL (0x27B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_DEBUG_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B5_CTL (0x27C) +#define TAIKO_A_CDC_DEBUG_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B6_CTL (0x27D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_DEBUG_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B7_CTL (0x27E) +#define TAIKO_A_CDC_DEBUG_B7_CTL__POR (0x00) +#define TAIKO_A_CDC_SRC1_PDA_CFG (0x2A0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_SRC1_PDA_CFG__POR (0x00) +#define TAIKO_A_CDC_SRC2_PDA_CFG (0x2A8) +#define TAIKO_A_CDC_SRC2_PDA_CFG__POR (0x00) +#define TAIKO_A_CDC_SRC1_FS_CTL (0x2A1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_SRC1_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_SRC2_FS_CTL (0x2A9) +#define TAIKO_A_CDC_SRC2_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_B1_CTL (0x2B0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX1_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_B1_CTL (0x2B8) +#define TAIKO_A_CDC_RX2_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_B1_CTL (0x2C0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX3_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_B1_CTL (0x2C8) +#define TAIKO_A_CDC_RX4_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_B1_CTL (0x2D0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX5_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_B1_CTL (0x2D8) +#define TAIKO_A_CDC_RX6_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_B1_CTL (0x2E0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX7_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_B2_CTL (0x2B1) +#define TAIKO_A_CDC_RX1_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_B2_CTL (0x2B9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX2_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_B2_CTL (0x2C1) +#define TAIKO_A_CDC_RX3_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_B2_CTL (0x2C9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX4_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_B2_CTL (0x2D1) +#define TAIKO_A_CDC_RX5_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_B2_CTL (0x2D9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX6_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_B2_CTL (0x2E1) +#define TAIKO_A_CDC_RX7_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_B3_CTL (0x2B2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX1_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_B3_CTL (0x2BA) +#define TAIKO_A_CDC_RX2_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_B3_CTL (0x2C2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX3_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_B3_CTL (0x2CA) +#define TAIKO_A_CDC_RX4_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_B3_CTL (0x2D2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX5_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_B3_CTL (0x2DA) +#define TAIKO_A_CDC_RX6_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_B3_CTL (0x2E2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX7_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_B4_CTL (0x2B3) +#define TAIKO_A_CDC_RX1_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_B4_CTL (0x2BB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX2_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_B4_CTL (0x2C3) +#define TAIKO_A_CDC_RX3_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_B4_CTL (0x2CB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX4_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_B4_CTL (0x2D3) +#define TAIKO_A_CDC_RX5_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_B4_CTL (0x2DB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX6_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_B4_CTL (0x2E3) +#define TAIKO_A_CDC_RX7_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_B5_CTL (0x2B4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX1_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_B5_CTL (0x2BC) +#define TAIKO_A_CDC_RX2_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_B5_CTL (0x2C4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX3_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_B5_CTL (0x2CC) +#define TAIKO_A_CDC_RX4_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_B5_CTL (0x2D4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX5_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_B5_CTL (0x2DC) +#define TAIKO_A_CDC_RX6_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_B5_CTL (0x2E4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX7_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_B6_CTL (0x2B5) +#define TAIKO_A_CDC_RX1_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_B6_CTL (0x2BD) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX2_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_B6_CTL (0x2C5) +#define TAIKO_A_CDC_RX3_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_B6_CTL (0x2CD) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX4_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_B6_CTL (0x2D5) +#define TAIKO_A_CDC_RX5_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_B6_CTL (0x2DD) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX6_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_B6_CTL (0x2E5) +#define TAIKO_A_CDC_RX7_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_VOL_CTL_B1_CTL (0x2B6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX1_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_VOL_CTL_B1_CTL (0x2BE) +#define TAIKO_A_CDC_RX2_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_VOL_CTL_B1_CTL (0x2C6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX3_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_VOL_CTL_B1_CTL (0x2CE) +#define TAIKO_A_CDC_RX4_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_VOL_CTL_B1_CTL (0x2D6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX5_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_VOL_CTL_B1_CTL (0x2DE) +#define TAIKO_A_CDC_RX6_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_VOL_CTL_B1_CTL (0x2E6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX7_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_VOL_CTL_B2_CTL (0x2B7) +#define TAIKO_A_CDC_RX1_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_VOL_CTL_B2_CTL (0x2BF) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX2_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_VOL_CTL_B2_CTL (0x2C7) +#define TAIKO_A_CDC_RX3_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_VOL_CTL_B2_CTL (0x2CF) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX4_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_VOL_CTL_B2_CTL (0x2D7) +#define TAIKO_A_CDC_RX5_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_VOL_CTL_B2_CTL (0x2DF) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_RX6_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_VOL_CTL_B2_CTL (0x2E7) +#define TAIKO_A_CDC_RX7_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_VBAT_CFG (0x2E8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_VBAT_CFG__POR (0x1A) +#define TAIKO_A_CDC_VBAT_ADC_CAL1 (0x2E9) +#define TAIKO_A_CDC_VBAT_ADC_CAL1__POR (0x00) +#define TAIKO_A_CDC_VBAT_ADC_CAL2 (0x2EA) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_VBAT_ADC_CAL2__POR (0x00) +#define TAIKO_A_CDC_VBAT_ADC_CAL3 (0x2EB) +#define TAIKO_A_CDC_VBAT_ADC_CAL3__POR (0x04) +#define TAIKO_A_CDC_VBAT_PK_EST1 (0x2EC) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_VBAT_PK_EST1__POR (0xE0) +#define TAIKO_A_CDC_VBAT_PK_EST2 (0x2ED) +#define TAIKO_A_CDC_VBAT_PK_EST2__POR (0x01) +#define TAIKO_A_CDC_VBAT_PK_EST3 (0x2EE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_VBAT_PK_EST3__POR (0x40) +#define TAIKO_A_CDC_VBAT_RF_PROC1 (0x2EF) +#define TAIKO_A_CDC_VBAT_RF_PROC1__POR (0x2A) +#define TAIKO_A_CDC_VBAT_RF_PROC2 (0x2F0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_VBAT_RF_PROC2__POR (0x86) +#define TAIKO_A_CDC_VBAT_TAC1 (0x2F1) +#define TAIKO_A_CDC_VBAT_TAC1__POR (0x70) +#define TAIKO_A_CDC_VBAT_TAC2 (0x2F2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_VBAT_TAC2__POR (0x18) +#define TAIKO_A_CDC_VBAT_TAC3 (0x2F3) +#define TAIKO_A_CDC_VBAT_TAC3__POR (0x18) +#define TAIKO_A_CDC_VBAT_TAC4 (0x2F4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_VBAT_TAC4__POR (0x03) +#define TAIKO_A_CDC_VBAT_GAIN_UPD1 (0x2F5) +#define TAIKO_A_CDC_VBAT_GAIN_UPD1__POR (0x01) +#define TAIKO_A_CDC_VBAT_GAIN_UPD2 (0x2F6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_VBAT_GAIN_UPD2__POR (0x00) +#define TAIKO_A_CDC_VBAT_GAIN_UPD3 (0x2F7) +#define TAIKO_A_CDC_VBAT_GAIN_UPD3__POR (0x64) +#define TAIKO_A_CDC_VBAT_GAIN_UPD4 (0x2F8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_VBAT_GAIN_UPD4__POR (0x01) +#define TAIKO_A_CDC_VBAT_DEBUG1 (0x2F9) +#define TAIKO_A_CDC_VBAT_DEBUG1__POR (0x00) +#define TAIKO_A_CDC_CLK_ANC_RESET_CTL (0x300) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLK_ANC_RESET_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_RX_RESET_CTL (0x301) +#define TAIKO_A_CDC_CLK_RX_RESET_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_TX_RESET_B1_CTL (0x302) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLK_TX_RESET_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_TX_RESET_B2_CTL (0x303) +#define TAIKO_A_CDC_CLK_TX_RESET_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_DMIC_B1_CTL (0x304) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLK_DMIC_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_DMIC_B2_CTL (0x305) +#define TAIKO_A_CDC_CLK_DMIC_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_RX_I2S_CTL (0x306) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLK_RX_I2S_CTL__POR (0x03) +#define TAIKO_A_CDC_CLK_TX_I2S_CTL (0x307) +#define TAIKO_A_CDC_CLK_TX_I2S_CTL__POR (0x03) +#define TAIKO_A_CDC_CLK_OTHR_RESET_B1_CTL (0x308) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLK_OTHR_RESET_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_OTHR_RESET_B2_CTL (0x309) +#define TAIKO_A_CDC_CLK_OTHR_RESET_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_TX_CLK_EN_B1_CTL (0x30A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_TX_CLK_EN_B2_CTL (0x30B) +#define TAIKO_A_CDC_CLK_TX_CLK_EN_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_OTHR_CTL (0x30C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLK_OTHR_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_RDAC_CLK_EN_CTL (0x30D) +#define TAIKO_A_CDC_CLK_RDAC_CLK_EN_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_ANC_CLK_EN_CTL (0x30E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLK_ANC_CLK_EN_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_RX_B1_CTL (0x30F) +#define TAIKO_A_CDC_CLK_RX_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_RX_B2_CTL (0x310) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLK_RX_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_MCLK_CTL (0x311) +#define TAIKO_A_CDC_CLK_MCLK_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_PDM_CTL (0x312) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLK_PDM_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_SD_CTL (0x313) +#define TAIKO_A_CDC_CLK_SD_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_POWER_CTL (0x314) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLK_POWER_CTL__POR (0x00) +#define TAIKO_A_CDC_CLSH_B1_CTL (0x320) +#define TAIKO_A_CDC_CLSH_B1_CTL__POR (0xE4) +#define TAIKO_A_CDC_CLSH_B2_CTL (0x321) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLSH_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLSH_B3_CTL (0x322) +#define TAIKO_A_CDC_CLSH_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CLSH_BUCK_NCP_VARS (0x323) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLSH_BUCK_NCP_VARS__POR (0x00) +#define TAIKO_A_CDC_CLSH_IDLE_HPH_THSD (0x324) +#define TAIKO_A_CDC_CLSH_IDLE_HPH_THSD__POR (0x12) +#define TAIKO_A_CDC_CLSH_IDLE_EAR_THSD (0x325) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLSH_IDLE_EAR_THSD__POR (0x0C) +#define TAIKO_A_CDC_CLSH_FCLKONLY_HPH_THSD (0x326) +#define TAIKO_A_CDC_CLSH_FCLKONLY_HPH_THSD__POR (0x18) +#define TAIKO_A_CDC_CLSH_FCLKONLY_EAR_THSD (0x327) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLSH_FCLKONLY_EAR_THSD__POR (0x23) +#define TAIKO_A_CDC_CLSH_K_ADDR (0x328) +#define TAIKO_A_CDC_CLSH_K_ADDR__POR (0x00) +#define TAIKO_A_CDC_CLSH_K_DATA (0x329) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLSH_K_DATA__POR (0xA4) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_L (0x32A) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_L__POR (0xD7) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_U (0x32B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_U__POR (0x05) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_L (0x32C) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_L__POR (0x60) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_U (0x32D) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_U__POR (0x09) +#define TAIKO_A_CDC_CLSH_V_PA_HD_EAR (0x32E) +#define TAIKO_A_CDC_CLSH_V_PA_HD_EAR__POR (0x00) +#define TAIKO_A_CDC_CLSH_V_PA_HD_HPH (0x32F) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLSH_V_PA_HD_HPH__POR (0x00) +#define TAIKO_A_CDC_CLSH_V_PA_MIN_EAR (0x330) +#define TAIKO_A_CDC_CLSH_V_PA_MIN_EAR__POR (0x00) +#define TAIKO_A_CDC_CLSH_V_PA_MIN_HPH (0x331) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CLSH_V_PA_MIN_HPH__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B1_CTL (0x340) +#define TAIKO_A_CDC_IIR1_GAIN_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B1_CTL (0x350) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_GAIN_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B2_CTL (0x341) +#define TAIKO_A_CDC_IIR1_GAIN_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B2_CTL (0x351) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_GAIN_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B3_CTL (0x342) +#define TAIKO_A_CDC_IIR1_GAIN_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B3_CTL (0x352) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_GAIN_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B4_CTL (0x343) +#define TAIKO_A_CDC_IIR1_GAIN_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B4_CTL (0x353) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_GAIN_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B5_CTL (0x344) +#define TAIKO_A_CDC_IIR1_GAIN_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B5_CTL (0x354) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_GAIN_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B6_CTL (0x345) +#define TAIKO_A_CDC_IIR1_GAIN_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B6_CTL (0x355) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_GAIN_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B7_CTL (0x346) +#define TAIKO_A_CDC_IIR1_GAIN_B7_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B7_CTL (0x356) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_GAIN_B7_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B8_CTL (0x347) +#define TAIKO_A_CDC_IIR1_GAIN_B8_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B8_CTL (0x357) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_GAIN_B8_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_CTL (0x348) +#define TAIKO_A_CDC_IIR1_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_CTL (0x358) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_TIMER_CTL (0x349) +#define TAIKO_A_CDC_IIR1_GAIN_TIMER_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_TIMER_CTL (0x359) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_GAIN_TIMER_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_COEF_B1_CTL (0x34A) +#define TAIKO_A_CDC_IIR1_COEF_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_COEF_B1_CTL (0x35A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_COEF_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_COEF_B2_CTL (0x34B) +#define TAIKO_A_CDC_IIR1_COEF_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_COEF_B2_CTL (0x35B) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_IIR2_COEF_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_TOP_GAIN_UPDATE (0x360) +#define TAIKO_A_CDC_TOP_GAIN_UPDATE__POR (0x00) +#define TAIKO_A_CDC_COMP0_B1_CTL (0x368) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP0_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP1_B1_CTL (0x370) +#define TAIKO_A_CDC_COMP1_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP2_B1_CTL (0x378) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP2_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP0_B2_CTL (0x369) +#define TAIKO_A_CDC_COMP0_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP1_B2_CTL (0x371) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP1_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP2_B2_CTL (0x379) +#define TAIKO_A_CDC_COMP2_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP0_B3_CTL (0x36A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP0_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP1_B3_CTL (0x372) +#define TAIKO_A_CDC_COMP1_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP2_B3_CTL (0x37A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP2_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP0_B4_CTL (0x36B) +#define TAIKO_A_CDC_COMP0_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP1_B4_CTL (0x373) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP1_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP2_B4_CTL (0x37B) +#define TAIKO_A_CDC_COMP2_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP0_B5_CTL (0x36C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP0_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP1_B5_CTL (0x374) +#define TAIKO_A_CDC_COMP1_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP2_B5_CTL (0x37C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP2_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP0_B6_CTL (0x36D) +#define TAIKO_A_CDC_COMP0_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP1_B6_CTL (0x375) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP1_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP2_B6_CTL (0x37D) +#define TAIKO_A_CDC_COMP2_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP0_SHUT_DOWN_STATUS (0x36E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP0_SHUT_DOWN_STATUS__POR (0x00) +#define TAIKO_A_CDC_COMP1_SHUT_DOWN_STATUS (0x376) +#define TAIKO_A_CDC_COMP1_SHUT_DOWN_STATUS__POR (0x00) +#define TAIKO_A_CDC_COMP2_SHUT_DOWN_STATUS (0x37E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP2_SHUT_DOWN_STATUS__POR (0x00) +#define TAIKO_A_CDC_COMP0_FS_CFG (0x36F) +#define TAIKO_A_CDC_COMP0_FS_CFG__POR (0x00) +#define TAIKO_A_CDC_COMP1_FS_CFG (0x377) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_COMP1_FS_CFG__POR (0x00) +#define TAIKO_A_CDC_COMP2_FS_CFG (0x37F) +#define TAIKO_A_CDC_COMP2_FS_CFG__POR (0x00) +#define TAIKO_A_CDC_CONN_RX1_B1_CTL (0x380) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_RX1_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX1_B2_CTL (0x381) +#define TAIKO_A_CDC_CONN_RX1_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX1_B3_CTL (0x382) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_RX1_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX2_B1_CTL (0x383) +#define TAIKO_A_CDC_CONN_RX2_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX2_B2_CTL (0x384) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_RX2_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX2_B3_CTL (0x385) +#define TAIKO_A_CDC_CONN_RX2_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX3_B1_CTL (0x386) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_RX3_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX3_B2_CTL (0x387) +#define TAIKO_A_CDC_CONN_RX3_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX4_B1_CTL (0x388) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_RX4_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX4_B2_CTL (0x389) +#define TAIKO_A_CDC_CONN_RX4_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX5_B1_CTL (0x38A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_RX5_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX5_B2_CTL (0x38B) +#define TAIKO_A_CDC_CONN_RX5_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX6_B1_CTL (0x38C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_RX6_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX6_B2_CTL (0x38D) +#define TAIKO_A_CDC_CONN_RX6_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX7_B1_CTL (0x38E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_RX7_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX7_B2_CTL (0x38F) +#define TAIKO_A_CDC_CONN_RX7_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX7_B3_CTL (0x390) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_RX7_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_ANC_B1_CTL (0x391) +#define TAIKO_A_CDC_CONN_ANC_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_ANC_B2_CTL (0x392) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_ANC_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_B1_CTL (0x393) +#define TAIKO_A_CDC_CONN_TX_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_B2_CTL (0x394) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_TX_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_B3_CTL (0x395) +#define TAIKO_A_CDC_CONN_TX_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_B4_CTL (0x396) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_TX_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ1_B1_CTL (0x397) +#define TAIKO_A_CDC_CONN_EQ1_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ1_B2_CTL (0x398) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_EQ1_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ1_B3_CTL (0x399) +#define TAIKO_A_CDC_CONN_EQ1_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ1_B4_CTL (0x39A) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_EQ1_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ2_B1_CTL (0x39B) +#define TAIKO_A_CDC_CONN_EQ2_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ2_B2_CTL (0x39C) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_EQ2_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ2_B3_CTL (0x39D) +#define TAIKO_A_CDC_CONN_EQ2_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ2_B4_CTL (0x39E) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_EQ2_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_SRC1_B1_CTL (0x39F) +#define TAIKO_A_CDC_CONN_SRC1_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_SRC1_B2_CTL (0x3A0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_SRC1_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_SRC2_B1_CTL (0x3A1) +#define TAIKO_A_CDC_CONN_SRC2_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_SRC2_B2_CTL (0x3A2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_SRC2_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B1_CTL (0x3A3) +#define TAIKO_A_CDC_CONN_TX_SB_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B2_CTL (0x3A4) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_TX_SB_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B3_CTL (0x3A5) +#define TAIKO_A_CDC_CONN_TX_SB_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B4_CTL (0x3A6) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_TX_SB_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B5_CTL (0x3A7) +#define TAIKO_A_CDC_CONN_TX_SB_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B6_CTL (0x3A8) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_TX_SB_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B7_CTL (0x3A9) +#define TAIKO_A_CDC_CONN_TX_SB_B7_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B8_CTL (0x3AA) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_TX_SB_B8_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B9_CTL (0x3AB) +#define TAIKO_A_CDC_CONN_TX_SB_B9_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B10_CTL (0x3AC) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_TX_SB_B10_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B11_CTL (0x3AD) +#define TAIKO_A_CDC_CONN_TX_SB_B11_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX_SB_B1_CTL (0x3AE) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_RX_SB_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX_SB_B2_CTL (0x3AF) +#define TAIKO_A_CDC_CONN_RX_SB_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_CLSH_CTL (0x3B0) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_CLSH_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_MISC (0x3B1) +#define TAIKO_A_CDC_CONN_MISC__POR (0x01) +#define TAIKO_A_CDC_CONN_MAD (0x3B2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_CONN_MAD__POR (0x01) +#define TAIKO_A_CDC_MBHC_EN_CTL (0x3C0) +#define TAIKO_A_CDC_MBHC_EN_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_FIR_B1_CFG (0x3C1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_FIR_B1_CFG__POR (0x00) +#define TAIKO_A_CDC_MBHC_FIR_B2_CFG (0x3C2) +#define TAIKO_A_CDC_MBHC_FIR_B2_CFG__POR (0x06) +#define TAIKO_A_CDC_MBHC_TIMER_B1_CTL (0x3C3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_TIMER_B1_CTL__POR (0x03) +#define TAIKO_A_CDC_MBHC_TIMER_B2_CTL (0x3C4) +#define TAIKO_A_CDC_MBHC_TIMER_B2_CTL__POR (0x09) +#define TAIKO_A_CDC_MBHC_TIMER_B3_CTL (0x3C5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_TIMER_B3_CTL__POR (0x1E) +#define TAIKO_A_CDC_MBHC_TIMER_B4_CTL (0x3C6) +#define TAIKO_A_CDC_MBHC_TIMER_B4_CTL__POR (0x45) +#define TAIKO_A_CDC_MBHC_TIMER_B5_CTL (0x3C7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_TIMER_B5_CTL__POR (0x04) +#define TAIKO_A_CDC_MBHC_TIMER_B6_CTL (0x3C8) +#define TAIKO_A_CDC_MBHC_TIMER_B6_CTL__POR (0x78) +#define TAIKO_A_CDC_MBHC_B1_STATUS (0x3C9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_B1_STATUS__POR (0x00) +#define TAIKO_A_CDC_MBHC_B2_STATUS (0x3CA) +#define TAIKO_A_CDC_MBHC_B2_STATUS__POR (0x00) +#define TAIKO_A_CDC_MBHC_B3_STATUS (0x3CB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_B3_STATUS__POR (0x00) +#define TAIKO_A_CDC_MBHC_B4_STATUS (0x3CC) +#define TAIKO_A_CDC_MBHC_B4_STATUS__POR (0x00) +#define TAIKO_A_CDC_MBHC_B5_STATUS (0x3CD) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_B5_STATUS__POR (0x00) +#define TAIKO_A_CDC_MBHC_B1_CTL (0x3CE) +#define TAIKO_A_CDC_MBHC_B1_CTL__POR (0xC0) +#define TAIKO_A_CDC_MBHC_B2_CTL (0x3CF) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_B2_CTL__POR (0x5D) +#define TAIKO_A_CDC_MBHC_VOLT_B1_CTL (0x3D0) +#define TAIKO_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B2_CTL (0x3D1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B3_CTL (0x3D2) +#define TAIKO_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B4_CTL (0x3D3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B5_CTL (0x3D4) +#define TAIKO_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B6_CTL (0x3D5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B7_CTL (0x3D6) +#define TAIKO_A_CDC_MBHC_VOLT_B7_CTL__POR (0xFF) +#define TAIKO_A_CDC_MBHC_VOLT_B8_CTL (0x3D7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_VOLT_B8_CTL__POR (0x07) +#define TAIKO_A_CDC_MBHC_VOLT_B9_CTL (0x3D8) +#define TAIKO_A_CDC_MBHC_VOLT_B9_CTL__POR (0xFF) +#define TAIKO_A_CDC_MBHC_VOLT_B10_CTL (0x3D9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_VOLT_B10_CTL__POR (0x7F) +#define TAIKO_A_CDC_MBHC_VOLT_B11_CTL (0x3DA) +#define TAIKO_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B12_CTL (0x3DB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_VOLT_B12_CTL__POR (0x80) +#define TAIKO_A_CDC_MBHC_CLK_CTL (0x3DC) +#define TAIKO_A_CDC_MBHC_CLK_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_INT_CTL (0x3DD) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_INT_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_DEBUG_CTL (0x3DE) +#define TAIKO_A_CDC_MBHC_DEBUG_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_SPARE (0x3DF) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MBHC_SPARE__POR (0x00) +#define TAIKO_A_CDC_MAD_MAIN_CTL_1 (0x3E0) +#define TAIKO_A_CDC_MAD_MAIN_CTL_1__POR (0x00) +#define TAIKO_A_CDC_MAD_MAIN_CTL_2 (0x3E1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_MAIN_CTL_2__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_1 (0x3E2) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_1__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_2 (0x3E3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_AUDIO_CTL_2__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_3 (0x3E4) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_3__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_4 (0x3E5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_AUDIO_CTL_4__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_5 (0x3E6) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_5__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_6 (0x3E7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_AUDIO_CTL_6__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_7 (0x3E8) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_7__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_8 (0x3E9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_AUDIO_CTL_8__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_PTR (0x3EA) +#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_PTR__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_VAL (0x3EB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_VAL__POR (0x40) +#define TAIKO_A_CDC_MAD_ULTR_CTL_1 (0x3EC) +#define TAIKO_A_CDC_MAD_ULTR_CTL_1__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_2 (0x3ED) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_ULTR_CTL_2__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_3 (0x3EE) +#define TAIKO_A_CDC_MAD_ULTR_CTL_3__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_4 (0x3EF) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_ULTR_CTL_4__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_5 (0x3F0) +#define TAIKO_A_CDC_MAD_ULTR_CTL_5__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_6 (0x3F1) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_ULTR_CTL_6__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_7 (0x3F2) +#define TAIKO_A_CDC_MAD_ULTR_CTL_7__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_1 (0x3F3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_BEACON_CTL_1__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_2 (0x3F4) +#define TAIKO_A_CDC_MAD_BEACON_CTL_2__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_3 (0x3F5) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_BEACON_CTL_3__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_4 (0x3F6) +#define TAIKO_A_CDC_MAD_BEACON_CTL_4__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_5 (0x3F7) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_BEACON_CTL_5__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_6 (0x3F8) +#define TAIKO_A_CDC_MAD_BEACON_CTL_6__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_7 (0x3F9) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_BEACON_CTL_7__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_8 (0x3FA) +#define TAIKO_A_CDC_MAD_BEACON_CTL_8__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_PTR (0x3FB) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_PTR__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_VAL (0x3FC) +#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_VAL__POR (0x00) +#define TAIKO_SLIM_PGD_PORT_INT_EN0 (0x30) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_SLIM_PGD_PORT_INT_STATUS0 (0x34) +#define TAIKO_SLIM_PGD_PORT_INT_CLR0 (0x38) +#define TAIKO_SLIM_PGD_PORT_INT_SOURCE0 (0x60) +#define TAIKO_PACKED_REG_SIZE sizeof(u32) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_CODEC_PACK_ENTRY(reg, mask, val) ((val & 0xff)| ((mask & 0xff) << 8)|((reg & 0xffff) << 16)) +#define TAIKO_CODEC_UNPACK_ENTRY(packed, reg, mask, val) do { ((reg) = ((packed >> 16) & (0xffff))); ((mask) = ((packed >> 8) & (0xff))); ((val) = ((packed) & (0xff))); } while (0); +#endif + diff --git a/kernel-headers/linux/mfd/wcd9xxx/wcd9xxx-slimslave.h b/kernel-headers/linux/mfd/wcd9xxx/wcd9xxx-slimslave.h new file mode 100644 index 0000000..e05e8b3 --- /dev/null +++ b/kernel-headers/linux/mfd/wcd9xxx/wcd9xxx-slimslave.h @@ -0,0 +1,84 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef __WCD9310_SLIMSLAVE_H_ +#define __WCD9310_SLIMSLAVE_H_ +#include <linux/slimbus/slimbus.h> +#include <linux/mfd/wcd9xxx/core.h> +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum { + SLIM_TX_1 = 128, + SLIM_TX_2 = 129, + SLIM_TX_3 = 130, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SLIM_TX_4 = 131, + SLIM_TX_5 = 132, + SLIM_TX_6 = 133, + SLIM_TX_7 = 134, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SLIM_TX_8 = 135, + SLIM_TX_9 = 136, + SLIM_TX_10 = 137, + SLIM_RX_1 = 138, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SLIM_RX_2 = 139, + SLIM_RX_3 = 140, + SLIM_RX_4 = 141, + SLIM_RX_5 = 142, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + SLIM_RX_6 = 143, + SLIM_RX_7 = 144, + SLIM_MAX = 145 +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS 10 +#define TAIKO_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS 16 +#define SLIM_MAX_TX_PORTS TAIKO_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS +#define TABLA_SB_PGD_OFFSET_OF_RX_SLAVE_DEV_PORTS TABLA_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TAIKO_SB_PGD_OFFSET_OF_RX_SLAVE_DEV_PORTS TAIKO_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS +#define TABLA_SB_PGD_MAX_NUMBER_OF_RX_SLAVE_DEV_PORTS 7 +#define TAIKO_SB_PGD_MAX_NUMBER_OF_RX_SLAVE_DEV_PORTS 13 +#define SLIM_MAX_RX_PORTS TAIKO_SB_PGD_MAX_NUMBER_OF_RX_SLAVE_DEV_PORTS +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_SB_PGD_RX_PORT_MULTI_CHANNEL_0_START_PORT_ID TABLA_SB_PGD_OFFSET_OF_RX_SLAVE_DEV_PORTS +#define TAIKO_SB_PGD_RX_PORT_MULTI_CHANNEL_0_START_PORT_ID TAIKO_SB_PGD_OFFSET_OF_RX_SLAVE_DEV_PORTS +#define TABLA_SB_PGD_RX_PORT_MULTI_CHANNEL_0_END_PORT_ID 16 +#define TAIKO_SB_PGD_RX_PORT_MULTI_CHANNEL_0_END_PORT_ID 31 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define TABLA_SB_PGD_TX_PORT_MULTI_CHANNEL_1_END_PORT_ID 9 +#define TAIKO_SB_PGD_TX_PORT_MULTI_CHANNEL_1_END_PORT_ID 15 +#define SB_PGD_PORT_BASE 0x000 +#define SB_PGD_PORT_CFG_BYTE_ADDR(offset, port_num) (SB_PGD_PORT_BASE + offset + (1 * port_num)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SB_PGD_TX_PORT_MULTI_CHANNEL_0(port_num) (SB_PGD_PORT_BASE + 0x100 + 4*port_num) +#define SB_PGD_TX_PORT_MULTI_CHANNEL_0_START_PORT_ID 0 +#define SB_PGD_TX_PORT_MULTI_CHANNEL_0_END_PORT_ID 7 +#define SB_PGD_TX_PORT_MULTI_CHANNEL_1(port_num) (SB_PGD_PORT_BASE + 0x101 + 4*port_num) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SB_PGD_TX_PORT_MULTI_CHANNEL_1_START_PORT_ID 8 +#define SB_PGD_RX_PORT_MULTI_CHANNEL_0(offset, port_num) (SB_PGD_PORT_BASE + offset + (4 * port_num)) +#define SLAVE_PORT_WATER_MARK_VALUE 2 +#define SLAVE_PORT_WATER_MARK_SHIFT 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SLAVE_PORT_ENABLE 1 +#define SLAVE_PORT_DISABLE 0 +#define BASE_CH_NUM 128 +#endif +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + diff --git a/kernel-headers/linux/mfd/wcd9xxx/wcd9xxx_registers.h b/kernel-headers/linux/mfd/wcd9xxx/wcd9xxx_registers.h new file mode 100644 index 0000000..04de85d --- /dev/null +++ b/kernel-headers/linux/mfd/wcd9xxx/wcd9xxx_registers.h @@ -0,0 +1,55 @@ +/**************************************************************************** + **************************************************************************** + *** + *** This header was automatically generated from a Linux kernel header + *** of the same name, to make information necessary for userspace to + *** call into the kernel available to libc. It contains only constants, + *** structures, and macros generated from the original header, and thus, + *** contains no copyrightable information. + *** + *** To edit the content of this header, modify the corresponding + *** source file (e.g. under external/kernel-headers/original/) then + *** run bionic/libc/kernel/tools/update_all.py + *** + *** Any manual change here will be lost the next time this script will + *** be run. You've been warned! + *** + **************************************************************************** + ****************************************************************************/ +#ifndef WCD9XXX_CODEC_DIGITAL_H +#define WCD9XXX_CODEC_DIGITAL_H +#define WCD9XXX_A_CHIP_CTL (0x00) +#define WCD9XXX_A_CHIP_CTL__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CHIP_STATUS (0x01) +#define WCD9XXX_A_CHIP_STATUS__POR (0x00000000) +#define WCD9XXX_A_CHIP_ID_BYTE_0 (0x04) +#define WCD9XXX_A_CHIP_ID_BYTE_0__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CHIP_ID_BYTE_1 (0x05) +#define WCD9XXX_A_CHIP_ID_BYTE_1__POR (0x00000000) +#define WCD9XXX_A_CHIP_ID_BYTE_2 (0x06) +#define WCD9XXX_A_CHIP_ID_BYTE_2__POR (0x00000000) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CHIP_ID_BYTE_3 (0x07) +#define WCD9XXX_A_CHIP_ID_BYTE_3__POR (0x00000001) +#define WCD9XXX_A_CHIP_VERSION (0x08) +#define WCD9XXX_A_CHIP_VERSION__POR (0x00000020) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_SB_VERSION (0x09) +#define WCD9XXX_A_SB_VERSION__POR (0x00000010) +#define WCD9XXX_A_SLAVE_ID_1 (0x0C) +#define WCD9XXX_A_SLAVE_ID_1__POR (0x00000077) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_SLAVE_ID_2 (0x0D) +#define WCD9XXX_A_SLAVE_ID_2__POR (0x00000066) +#define WCD9XXX_A_SLAVE_ID_3 (0x0E) +#define WCD9XXX_A_SLAVE_ID_3__POR (0x00000055) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define WCD9XXX_A_CDC_CTL (0x80) +#define WCD9XXX_A_CDC_CTL__POR (0x00000000) +#define WCD9XXX_A_LEAKAGE_CTL (0x88) +#define WCD9XXX_A_LEAKAGE_CTL__POR (0x00000004) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#endif + diff --git a/kernel-headers/linux/msm_adsp.h b/kernel-headers/linux/msm_adsp.h index 7c3fd14..c3b9b6b 100644 --- a/kernel-headers/linux/msm_adsp.h +++ b/kernel-headers/linux/msm_adsp.h @@ -38,23 +38,19 @@ struct adsp_event_t { /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t *data; }; -#define ADSP_IOCTL_ENABLE _IOR(ADSP_IOCTL_MAGIC, 1, unsigned) -#define ADSP_IOCTL_DISABLE _IOR(ADSP_IOCTL_MAGIC, 2, unsigned) +#define ADSP_IOCTL_ENABLE _IOR(ADSP_IOCTL_MAGIC, 1, unsigned) +#define ADSP_IOCTL_DISABLE _IOR(ADSP_IOCTL_MAGIC, 2, unsigned) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ -#define ADSP_IOCTL_DISABLE_ACK _IOR(ADSP_IOCTL_MAGIC, 3, unsigned) -#define ADSP_IOCTL_WRITE_COMMAND _IOR(ADSP_IOCTL_MAGIC, 4, struct adsp_command_t *) -#define ADSP_IOCTL_GET_EVENT _IOWR(ADSP_IOCTL_MAGIC, 5, struct adsp_event_data_t *) -#define ADSP_IOCTL_SET_CLKRATE _IOR(ADSP_IOCTL_MAGIC, 6, unsigned) +#define ADSP_IOCTL_DISABLE_ACK _IOR(ADSP_IOCTL_MAGIC, 3, unsigned) +#define ADSP_IOCTL_WRITE_COMMAND _IOR(ADSP_IOCTL_MAGIC, 4, struct adsp_command_t *) +#define ADSP_IOCTL_GET_EVENT _IOWR(ADSP_IOCTL_MAGIC, 5, struct adsp_event_data_t *) +#define ADSP_IOCTL_SET_CLKRATE _IOR(ADSP_IOCTL_MAGIC, 6, unsigned) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ -#define ADSP_IOCTL_DISABLE_EVENT_RSP _IOR(ADSP_IOCTL_MAGIC, 10, unsigned) -struct adsp_pmem_info { - int fd; - void *vaddr; +#define ADSP_IOCTL_DISABLE_EVENT_RSP _IOR(ADSP_IOCTL_MAGIC, 10, unsigned) +#define ADSP_IOCTL_REGISTER_PMEM _IOW(ADSP_IOCTL_MAGIC, 13, unsigned) +#define ADSP_IOCTL_UNREGISTER_PMEM _IOW(ADSP_IOCTL_MAGIC, 14, unsigned) +#define ADSP_IOCTL_ABORT_EVENT_READ _IOW(ADSP_IOCTL_MAGIC, 15, unsigned) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ -}; -#define ADSP_IOCTL_REGISTER_PMEM _IOW(ADSP_IOCTL_MAGIC, 13, unsigned) -#define ADSP_IOCTL_UNREGISTER_PMEM _IOW(ADSP_IOCTL_MAGIC, 14, unsigned) -#define ADSP_IOCTL_ABORT_EVENT_READ _IOW(ADSP_IOCTL_MAGIC, 15, unsigned) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ -#define ADSP_IOCTL_LINK_TASK _IOW(ADSP_IOCTL_MAGIC, 16, unsigned) +#define ADSP_IOCTL_LINK_TASK _IOW(ADSP_IOCTL_MAGIC, 16, unsigned) #endif + diff --git a/kernel-headers/linux/msm_audio.h b/kernel-headers/linux/msm_audio.h index 4c9a1ab..2b42efc 100644 --- a/kernel-headers/linux/msm_audio.h +++ b/kernel-headers/linux/msm_audio.h @@ -343,3 +343,4 @@ struct msm_acdb_cmd_device { /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #endif + diff --git a/kernel-headers/linux/msm_audio_aac.h b/kernel-headers/linux/msm_audio_aac.h index 218ac45..30ac21b 100644 --- a/kernel-headers/linux/msm_audio_aac.h +++ b/kernel-headers/linux/msm_audio_aac.h @@ -24,56 +24,58 @@ #define AUDIO_GET_AAC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, (AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned) #define AUDIO_SET_AAC_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, (AUDIO_MAX_COMMON_IOCTL_NUM+3), struct msm_audio_aac_enc_config) #define AUDIO_GET_AAC_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, (AUDIO_MAX_COMMON_IOCTL_NUM+4), struct msm_audio_aac_enc_config) -#define AUDIO_AAC_FORMAT_ADTS -1 +#define AUDIO_SET_AAC_MIX_CONFIG _IOR(AUDIO_IOCTL_MAGIC, (AUDIO_MAX_COMMON_IOCTL_NUM+5), unsigned) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_AAC_FORMAT_ADTS -1 #define AUDIO_AAC_FORMAT_RAW 0x0000 #define AUDIO_AAC_FORMAT_PSUEDO_RAW 0x0001 #define AUDIO_AAC_FORMAT_LOAS 0x0002 -#define AUDIO_AAC_FORMAT_ADIF 0x0003 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_AAC_FORMAT_ADIF 0x0003 #define AUDIO_AAC_OBJECT_LC 0x0002 #define AUDIO_AAC_OBJECT_LTP 0x0004 #define AUDIO_AAC_OBJECT_ERLC 0x0011 -#define AUDIO_AAC_OBJECT_BSAC 0x0016 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_AAC_OBJECT_BSAC 0x0016 #define AUDIO_AAC_SEC_DATA_RES_ON 0x0001 #define AUDIO_AAC_SEC_DATA_RES_OFF 0x0000 #define AUDIO_AAC_SCA_DATA_RES_ON 0x0001 -#define AUDIO_AAC_SCA_DATA_RES_OFF 0x0000 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_AAC_SCA_DATA_RES_OFF 0x0000 #define AUDIO_AAC_SPEC_DATA_RES_ON 0x0001 #define AUDIO_AAC_SPEC_DATA_RES_OFF 0x0000 #define AUDIO_AAC_SBR_ON_FLAG_ON 0x0001 -#define AUDIO_AAC_SBR_ON_FLAG_OFF 0x0000 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_AAC_SBR_ON_FLAG_OFF 0x0000 #define AUDIO_AAC_SBR_PS_ON_FLAG_ON 0x0001 #define AUDIO_AAC_SBR_PS_ON_FLAG_OFF 0x0000 #define AUDIO_AAC_DUAL_MONO_PL_PR 0 -#define AUDIO_AAC_DUAL_MONO_SL_SR 1 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define AUDIO_AAC_DUAL_MONO_SL_SR 1 #define AUDIO_AAC_DUAL_MONO_SL_PR 2 #define AUDIO_AAC_DUAL_MONO_PL_SR 3 struct msm_audio_aac_config { - signed short format; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + signed short format; unsigned short audio_object; unsigned short ep_config; unsigned short aac_section_data_resilience_flag; - unsigned short aac_scalefactor_data_resilience_flag; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned short aac_scalefactor_data_resilience_flag; unsigned short aac_spectral_data_resilience_flag; unsigned short sbr_on_flag; unsigned short sbr_ps_on_flag; - unsigned short dual_mono_mode; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned short dual_mono_mode; unsigned short channel_configuration; }; struct msm_audio_aac_enc_config { - uint32_t channels; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t channels; uint32_t sample_rate; uint32_t bit_rate; uint32_t stream_format; -}; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; #endif + diff --git a/kernel-headers/linux/msm_audio_acdb.h b/kernel-headers/linux/msm_audio_acdb.h index a2d42bf..831e265 100644 --- a/kernel-headers/linux/msm_audio_acdb.h +++ b/kernel-headers/linux/msm_audio_acdb.h @@ -68,3 +68,4 @@ struct sidetone_cal { /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define AUDIO_MAX_RTAC_IOCTL (AUDIO_MAX_ACDB_IOCTL+20) #endif + diff --git a/kernel-headers/linux/msm_audio_wma.h b/kernel-headers/linux/msm_audio_wma.h index 8d2e4db..fc89cb6 100644 --- a/kernel-headers/linux/msm_audio_wma.h +++ b/kernel-headers/linux/msm_audio_wma.h @@ -46,3 +46,4 @@ struct msm_audio_wma_config_v2 { }; #endif /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + diff --git a/kernel-headers/linux/msm_audio_wmapro.h b/kernel-headers/linux/msm_audio_wmapro.h index 9fb19da..3e5d7c6 100644 --- a/kernel-headers/linux/msm_audio_wmapro.h +++ b/kernel-headers/linux/msm_audio_wmapro.h @@ -38,3 +38,4 @@ struct msm_audio_wmapro_config { /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #endif + diff --git a/kernel-headers/linux/msm_charm.h b/kernel-headers/linux/msm_charm.h index f73a8f1..d1fa00e 100644 --- a/kernel-headers/linux/msm_charm.h +++ b/kernel-headers/linux/msm_charm.h @@ -29,10 +29,18 @@ #define RAM_DUMP_DONE _IOW(CHARM_CODE, 6, int) #define WAIT_FOR_RESTART _IOR(CHARM_CODE, 7, int) #define GET_DLOAD_STATUS _IOR(CHARM_CODE, 8, int) -enum charm_boot_type { +#define IMAGE_UPGRADE _IOW(CHARM_CODE, 9, int) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define SHUTDOWN_CHARM _IOW(CHARM_CODE, 10, int) +enum charm_boot_type { CHARM_NORMAL_BOOT = 0, CHARM_RAM_DUMPS, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; -#endif +enum image_upgrade_type { + APQ_CONTROLLED_UPGRADE = 0, + MDM_CONTROLLED_UPGRADE, /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +#endif + diff --git a/kernel-headers/linux/msm_dsps.h b/kernel-headers/linux/msm_dsps.h index e56b319..1978328 100644 --- a/kernel-headers/linux/msm_dsps.h +++ b/kernel-headers/linux/msm_dsps.h @@ -28,3 +28,4 @@ /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define DSPS_IOCTL_RESET _IO(DSPS_IOCTL_MAGIC, 5) #endif + diff --git a/kernel-headers/linux/msm_hw3d.h b/kernel-headers/linux/msm_hw3d.h index 684896e..e69de29 100644 --- a/kernel-headers/linux/msm_hw3d.h +++ b/kernel-headers/linux/msm_hw3d.h @@ -1,48 +0,0 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - *** To edit the content of this header, modify the corresponding - *** source file (e.g. under external/kernel-headers/original/) then - *** run bionic/libc/kernel/tools/update_all.py - *** - *** Any manual change here will be lost the next time this script will - *** be run. You've been warned! - *** - **************************************************************************** - ****************************************************************************/ -#ifndef _MSM_HW3D_H_ -#define _MSM_HW3D_H_ -#include <linux/fs.h> -#include <linux/ioctl.h> -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ -struct hw3d_region; -#define HW3D_IOCTL_MAGIC 'h' -#define HW3D_WAIT_FOR_REVOKE _IO(HW3D_IOCTL_MAGIC, 0x80) -#define HW3D_WAIT_FOR_INTERRUPT _IO(HW3D_IOCTL_MAGIC, 0x81) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ -#define HW3D_GET_REGIONS _IOR(HW3D_IOCTL_MAGIC, 0x82, struct hw3d_region *) -#define HW3D_REGION_OFFSET(id) ((((uint32_t)(id)) & 0xf) << 28) -#define HW3D_REGION_ID(addr) (((uint32_t)(addr) >> 28) & 0xf) -#define HW3D_OFFSET_IN_REGION(addr) ((uint32_t)(addr) & ~(0xfUL << 28)) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ -enum { - HW3D_EBI = 0, - HW3D_SMI = 1, - HW3D_REGS = 2, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ - HW3D_NUM_REGIONS = HW3D_REGS + 1, -}; -struct hw3d_region { - unsigned long phys; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ - unsigned long map_offset; - unsigned long len; -}; -#endif -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ diff --git a/kernel-headers/linux/msm_ion.h b/kernel-headers/linux/msm_ion.h index 5e85ea1..7451e89 100644 --- a/kernel-headers/linux/msm_ion.h +++ b/kernel-headers/linux/msm_ion.h @@ -16,22 +16,22 @@ *** **************************************************************************** ****************************************************************************/ -#ifndef __LINUX_MSM_ION_H__ -#define __LINUX_MSM_ION_H__ +#ifndef _LINUX_MSM_ION_H +#define _LINUX_MSM_ION_H #include <linux/ion.h> -enum msm_ion_heap_types { +#define ION_HEAP_TYPE_MSM_START (ION_HEAP_TYPE_CUSTOM + 1) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ - ION_HEAP_TYPE_IOMMU = ION_HEAP_TYPE_CUSTOM + 1, - ION_HEAP_TYPE_CP = ION_HEAP_TYPE_CUSTOM + 2, -}; +#define ION_HEAP_TYPE_IOMMU (ION_HEAP_TYPE_MSM_START) +#define ION_HEAP_TYPE_CP (ION_HEAP_TYPE_IOMMU + 1) enum ion_heap_ids { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ INVALID_HEAP_ID = -1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ION_CP_MM_HEAP_ID = 8, ION_CP_MFC_HEAP_ID = 12, ION_CP_WB_HEAP_ID = 16, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ION_CAMERA_HEAP_ID = 20, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + ION_ADSP_HEAP_ID = 22, ION_SF_HEAP_ID = 24, ION_IOMMU_HEAP_ID = 25, ION_QSECOM_HEAP_ID = 27, @@ -61,27 +61,27 @@ enum cp_mem_usage { #define ION_HEAP_CP_MASK (1 << ION_HEAP_TYPE_CP) #define ION_SECURE (1 << ION_HEAP_ID_RESERVED) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ION_FORCE_CONTIGUOUS (1 << 30) #define ION_HEAP(bit) (1 << (bit)) +#define ION_ADSP_HEAP_NAME "adsp" #define ION_VMALLOC_HEAP_NAME "vmalloc" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_AUDIO_HEAP_NAME "audio" #define ION_SF_HEAP_NAME "sf" -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_MM_HEAP_NAME "mm" #define ION_CAMERA_HEAP_NAME "camera_preview" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_IOMMU_HEAP_NAME "iommu" #define ION_MFC_HEAP_NAME "mfc" -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_WB_HEAP_NAME "wb" #define ION_MM_FIRMWARE_HEAP_NAME "mm_fw" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ION_QSECOM_HEAP_NAME "qsecom" #define ION_FMEM_HEAP_NAME "fmem" +#define ION_SET_CACHED(__cache) (__cache | ION_FLAG_CACHED) +#define ION_SET_UNCACHED(__cache) (__cache & ~ION_FLAG_CACHED) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ -#define CACHED 1 -#define UNCACHED 0 -#define ION_CACHE_SHIFT 0 -#define ION_SET_CACHE(__cache) ((__cache) << ION_CACHE_SHIFT) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ -#define ION_IS_CACHED(__flags) ((__flags) & (1 << ION_CACHE_SHIFT)) +#define ION_IS_CACHED(__flags) ((__flags) & ION_FLAG_CACHED) struct ion_flush_data { struct ion_handle *handle; int fd; @@ -96,10 +96,11 @@ struct ion_flag_data { unsigned long flags; }; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ -#define ION_IOC_CLEAN_CACHES _IOWR(ION_IOC_MAGIC, 20, struct ion_flush_data) -#define ION_IOC_INV_CACHES _IOWR(ION_IOC_MAGIC, 21, struct ion_flush_data) -#define ION_IOC_CLEAN_INV_CACHES _IOWR(ION_IOC_MAGIC, 22, struct ion_flush_data) -#define ION_IOC_GET_FLAGS _IOWR(ION_IOC_MAGIC, 23, struct ion_flag_data) +#define ION_IOC_MSM_MAGIC 'M' +#define ION_IOC_CLEAN_CACHES _IOWR(ION_IOC_MSM_MAGIC, 0, struct ion_flush_data) +#define ION_IOC_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 1, struct ion_flush_data) +#define ION_IOC_CLEAN_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 2, struct ion_flush_data) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define ION_IOC_GET_FLAGS _IOWR(ION_IOC_MSM_MAGIC, 3, struct ion_flag_data) #endif diff --git a/kernel-headers/linux/msm_kgsl.h b/kernel-headers/linux/msm_kgsl.h index 9ba7401..3ca3c8d 100644 --- a/kernel-headers/linux/msm_kgsl.h +++ b/kernel-headers/linux/msm_kgsl.h @@ -31,371 +31,395 @@ #define KGSL_CONTEXT_PER_CONTEXT_TS 0x00000040 #define KGSL_CONTEXT_USER_GENERATED_TS 0x00000080 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_CONTEXT_NO_FAULT_TOLERANCE 0x00000200 #define KGSL_CONTEXT_INVALID 0xffffffff #define KGSL_MEMFLAGS_GPUREADONLY 0x01000000 #define KGSL_MEMTYPE_MASK 0x0000FF00 -#define KGSL_MEMTYPE_SHIFT 8 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMTYPE_SHIFT 8 #define KGSL_MEMTYPE_OBJECTANY 0 #define KGSL_MEMTYPE_FRAMEBUFFER 1 #define KGSL_MEMTYPE_RENDERBUFFER 2 -#define KGSL_MEMTYPE_ARRAYBUFFER 3 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMTYPE_ARRAYBUFFER 3 #define KGSL_MEMTYPE_ELEMENTARRAYBUFFER 4 #define KGSL_MEMTYPE_VERTEXARRAYBUFFER 5 #define KGSL_MEMTYPE_TEXTURE 6 -#define KGSL_MEMTYPE_SURFACE 7 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMTYPE_SURFACE 7 #define KGSL_MEMTYPE_EGL_SURFACE 8 #define KGSL_MEMTYPE_GL 9 #define KGSL_MEMTYPE_CL 10 -#define KGSL_MEMTYPE_CL_BUFFER_MAP 11 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMTYPE_CL_BUFFER_MAP 11 #define KGSL_MEMTYPE_CL_BUFFER_NOMAP 12 #define KGSL_MEMTYPE_CL_IMAGE_MAP 13 #define KGSL_MEMTYPE_CL_IMAGE_NOMAP 14 -#define KGSL_MEMTYPE_CL_KERNEL_STACK 15 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMTYPE_CL_KERNEL_STACK 15 #define KGSL_MEMTYPE_COMMAND 16 #define KGSL_MEMTYPE_2D 17 #define KGSL_MEMTYPE_EGL_IMAGE 18 -#define KGSL_MEMTYPE_EGL_SHADOW 19 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMTYPE_EGL_SHADOW 19 #define KGSL_MEMTYPE_MULTISAMPLE 20 #define KGSL_MEMTYPE_KERNEL 255 #define KGSL_MEMALIGN_MASK 0x00FF0000 -#define KGSL_MEMALIGN_SHIFT 16 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_MEMALIGN_SHIFT 16 #define KGSL_FLAGS_NORMALMODE 0x00000000 #define KGSL_FLAGS_SAFEMODE 0x00000001 #define KGSL_FLAGS_INITIALIZED0 0x00000002 -#define KGSL_FLAGS_INITIALIZED 0x00000004 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_FLAGS_INITIALIZED 0x00000004 #define KGSL_FLAGS_STARTED 0x00000008 #define KGSL_FLAGS_ACTIVE 0x00000010 #define KGSL_FLAGS_RESERVED0 0x00000020 -#define KGSL_FLAGS_RESERVED1 0x00000040 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_FLAGS_RESERVED1 0x00000040 #define KGSL_FLAGS_RESERVED2 0x00000080 #define KGSL_FLAGS_SOFT_RESET 0x00000100 #define KGSL_FLAGS_PER_CONTEXT_TIMESTAMPS 0x00000200 -#define KGSL_CLK_SRC 0x00000001 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_CLK_SRC 0x00000001 #define KGSL_CLK_CORE 0x00000002 #define KGSL_CLK_IFACE 0x00000004 #define KGSL_CLK_MEM 0x00000008 -#define KGSL_CLK_MEM_IFACE 0x00000010 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_CLK_MEM_IFACE 0x00000010 #define KGSL_CLK_AXI 0x00000020 #define KGSL_SYNCOBJ_SERVER_TIMEOUT 2000 enum kgsl_ctx_reset_stat { - KGSL_CTX_STAT_NO_ERROR = 0x00000000, /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + KGSL_CTX_STAT_NO_ERROR = 0x00000000, KGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT = 0x00000001, KGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT = 0x00000002, KGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT = 0x00000003 -}; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; #define KGSL_CONVERT_TO_MBPS(val) (val*1000*1000U) enum kgsl_deviceid { KGSL_DEVICE_3D0 = 0x00000000, - KGSL_DEVICE_2D0 = 0x00000001, /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + KGSL_DEVICE_2D0 = 0x00000001, KGSL_DEVICE_2D1 = 0x00000002, KGSL_DEVICE_MAX = 0x00000003 }; -enum kgsl_user_mem_type { /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum kgsl_user_mem_type { KGSL_USER_MEM_TYPE_PMEM = 0x00000000, KGSL_USER_MEM_TYPE_ASHMEM = 0x00000001, KGSL_USER_MEM_TYPE_ADDR = 0x00000002, - KGSL_USER_MEM_TYPE_ION = 0x00000003, /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + KGSL_USER_MEM_TYPE_ION = 0x00000003, KGSL_USER_MEM_TYPE_MAX = 0x00000004, }; struct kgsl_devinfo { - unsigned int device_id; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int device_id; unsigned int chip_id; unsigned int mmu_enabled; unsigned int gmem_gpubaseaddr; - unsigned int gpu_id; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int gpu_id; unsigned int gmem_sizebytes; }; struct kgsl_devmemstore { - volatile unsigned int soptimestamp; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + volatile unsigned int soptimestamp; unsigned int sbz; volatile unsigned int eoptimestamp; unsigned int sbz2; - volatile unsigned int ts_cmp_enable; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + volatile unsigned int ts_cmp_enable; unsigned int sbz3; volatile unsigned int ref_wait_ts; unsigned int sbz4; - unsigned int current_context; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int current_context; unsigned int sbz5; }; #define KGSL_MEMSTORE_OFFSET(ctxt_id, field) ((ctxt_id)*sizeof(struct kgsl_devmemstore) + offsetof(struct kgsl_devmemstore, field)) -enum kgsl_timestamp_type { /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum kgsl_timestamp_type { KGSL_TIMESTAMP_CONSUMED = 0x00000001, KGSL_TIMESTAMP_RETIRED = 0x00000002, KGSL_TIMESTAMP_QUEUED = 0x00000003, -}; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; enum kgsl_property_type { KGSL_PROP_DEVICE_INFO = 0x00000001, KGSL_PROP_DEVICE_SHADOW = 0x00000002, - KGSL_PROP_DEVICE_POWER = 0x00000003, /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + KGSL_PROP_DEVICE_POWER = 0x00000003, KGSL_PROP_SHMEM = 0x00000004, KGSL_PROP_SHMEM_APERTURES = 0x00000005, KGSL_PROP_MMU_ENABLE = 0x00000006, - KGSL_PROP_INTERRUPT_WAITS = 0x00000007, /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + KGSL_PROP_INTERRUPT_WAITS = 0x00000007, KGSL_PROP_VERSION = 0x00000008, KGSL_PROP_GPU_RESET_STAT = 0x00000009, KGSL_PROP_PWRCTRL = 0x0000000E, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + KGSL_PROP_FAULT_TOLERANCE = 0x00000011, }; +#define KGSL_FT_DISABLE 0x00000001 +#define KGSL_FT_REPLAY 0x00000002 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_FT_SKIPIB 0x00000004 +#define KGSL_FT_SKIPFRAME 0x00000008 +#define KGSL_FT_DEFAULT_POLICY (KGSL_FT_REPLAY + KGSL_FT_SKIPIB) +#define KGSL_FT_PAGEFAULT_INT_ENABLE 0x00000001 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define KGSL_FT_PAGEFAULT_GPUHALT_ENABLE 0x00000002 +#define KGSL_FT_PAGEFAULT_LOG_ONE_PER_PAGE 0x00000004 +#define KGSL_FT_PAGEFAULT_LOG_ONE_PER_INT 0x00000008 +#define KGSL_FT_PAGEFAULT_DEFAULT_POLICY (KGSL_FT_PAGEFAULT_INT_ENABLE + KGSL_FT_PAGEFAULT_LOG_ONE_PER_PAGE) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct kgsl_ft_config { + unsigned int ft_policy; + unsigned int ft_pf_policy; + unsigned int ft_pm_dump; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned int ft_detect_ms; + unsigned int ft_dos_timeout_ms; +}; struct kgsl_shadowprop { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int gpuaddr; unsigned int size; unsigned int flags; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_version { unsigned int drv_major; unsigned int drv_minor; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int dev_major; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int dev_minor; }; struct kgsl_ibdesc { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int gpuaddr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ void *hostptr; unsigned int sizedwords; unsigned int ctrl; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define KGSL_IOC_TYPE 0x09 struct kgsl_device_getproperty { unsigned int type; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ void *value; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int sizebytes; }; #define IOCTL_KGSL_DEVICE_GETPROPERTY _IOWR(KGSL_IOC_TYPE, 0x2, struct kgsl_device_getproperty) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_device_waittimestamp { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int timestamp; unsigned int timeout; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define IOCTL_KGSL_DEVICE_WAITTIMESTAMP _IOW(KGSL_IOC_TYPE, 0x6, struct kgsl_device_waittimestamp) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_device_waittimestamp_ctxtid { unsigned int context_id; unsigned int timestamp; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int timeout; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_DEVICE_WAITTIMESTAMP_CTXTID _IOW(KGSL_IOC_TYPE, 0x7, struct kgsl_device_waittimestamp_ctxtid) struct kgsl_ringbuffer_issueibcmds { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int drawctxt_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int ibdesc_addr; unsigned int numibs; unsigned int timestamp; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_RINGBUFFER_ISSUEIBCMDS _IOWR(KGSL_IOC_TYPE, 0x10, struct kgsl_ringbuffer_issueibcmds) struct kgsl_cmdstream_readtimestamp { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int timestamp; }; #define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_OLD _IOR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP _IOWR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_cmdstream_freememontimestamp { unsigned int gpuaddr; unsigned int type; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int timestamp; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP _IOW(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp) #define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_OLD _IOR(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_drawctxt_create { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int flags; unsigned int drawctxt_id; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define IOCTL_KGSL_DRAWCTXT_CREATE _IOWR(KGSL_IOC_TYPE, 0x13, struct kgsl_drawctxt_create) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_drawctxt_destroy { unsigned int drawctxt_id; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define IOCTL_KGSL_DRAWCTXT_DESTROY _IOW(KGSL_IOC_TYPE, 0x14, struct kgsl_drawctxt_destroy) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_map_user_mem { int fd; unsigned int gpuaddr; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int len; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int offset; unsigned int hostptr; enum kgsl_user_mem_type memtype; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_MAP_USER_MEM _IOWR(KGSL_IOC_TYPE, 0x15, struct kgsl_map_user_mem) struct kgsl_cmdstream_readtimestamp_ctxtid { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int context_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int type; unsigned int timestamp; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_CTXTID _IOWR(KGSL_IOC_TYPE, 0x16, struct kgsl_cmdstream_readtimestamp_ctxtid) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_cmdstream_freememontimestamp_ctxtid { unsigned int context_id; unsigned int gpuaddr; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int timestamp; }; #define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_CTXTID _IOW(KGSL_IOC_TYPE, 0x17, struct kgsl_cmdstream_freememontimestamp_ctxtid) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_sharedmem_from_pmem { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int pmem_fd; unsigned int gpuaddr; unsigned int len; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int offset; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_SHAREDMEM_FROM_PMEM _IOWR(KGSL_IOC_TYPE, 0x20, struct kgsl_sharedmem_from_pmem) struct kgsl_sharedmem_free { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int gpuaddr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_SHAREDMEM_FREE _IOW(KGSL_IOC_TYPE, 0x21, struct kgsl_sharedmem_free) struct kgsl_cff_user_event { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned char cff_opcode; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int op1; unsigned int op2; unsigned int op3; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int op4; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int op5; unsigned int __pad[2]; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define IOCTL_KGSL_CFF_USER_EVENT _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_cff_user_event) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_gmem_desc { unsigned int x; unsigned int y; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int width; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int height; unsigned int pitch; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_buffer_desc { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ void *hostptr; unsigned int gpuaddr; int size; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int format; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int pitch; unsigned int enabled; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_bind_gmem_shadow { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int drawctxt_id; struct kgsl_gmem_desc gmem_desc; unsigned int shadow_x; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int shadow_y; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_buffer_desc shadow_buffer; unsigned int buffer_id; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW _IOW(KGSL_IOC_TYPE, 0x22, struct kgsl_bind_gmem_shadow) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_sharedmem_from_vmalloc { unsigned int gpuaddr; unsigned int hostptr; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC _IOWR(KGSL_IOC_TYPE, 0x23, struct kgsl_sharedmem_from_vmalloc) #define IOCTL_KGSL_SHAREDMEM_FLUSH_CACHE _IOW(KGSL_IOC_TYPE, 0x24, struct kgsl_sharedmem_free) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_drawctxt_set_bin_base_offset { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int drawctxt_id; unsigned int offset; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define IOCTL_KGSL_DRAWCTXT_SET_BIN_BASE_OFFSET _IOW(KGSL_IOC_TYPE, 0x25, struct kgsl_drawctxt_set_bin_base_offset) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum kgsl_cmdwindow_type { KGSL_CMDWINDOW_MIN = 0x00000000, KGSL_CMDWINDOW_2D = 0x00000000, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ KGSL_CMDWINDOW_3D = 0x00000001, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ KGSL_CMDWINDOW_MMU = 0x00000002, KGSL_CMDWINDOW_ARBITER = 0x000000FF, KGSL_CMDWINDOW_MAX = 0x000000FF, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_cmdwindow_write { enum kgsl_cmdwindow_type target; unsigned int addr; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_CMDWINDOW_WRITE _IOW(KGSL_IOC_TYPE, 0x2e, struct kgsl_cmdwindow_write) struct kgsl_gpumem_alloc { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned long gpuaddr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ size_t size; unsigned int flags; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define IOCTL_KGSL_GPUMEM_ALLOC _IOWR(KGSL_IOC_TYPE, 0x2f, struct kgsl_gpumem_alloc) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_cff_syncmem { unsigned int gpuaddr; unsigned int len; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int __pad[2]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_CFF_SYNCMEM _IOW(KGSL_IOC_TYPE, 0x30, struct kgsl_cff_syncmem) struct kgsl_timestamp_event { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int timestamp; unsigned int context_id; void *priv; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ size_t len; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define IOCTL_KGSL_TIMESTAMP_EVENT_OLD _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_timestamp_event) #define KGSL_TIMESTAMP_EVENT_GENLOCK 1 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_timestamp_event_genlock { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int handle; }; #define KGSL_TIMESTAMP_EVENT_FENCE 2 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct kgsl_timestamp_event_fence { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int fence_fd; }; #define IOCTL_KGSL_SETPROPERTY _IOW(KGSL_IOC_TYPE, 0x32, struct kgsl_device_getproperty) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define IOCTL_KGSL_TIMESTAMP_EVENT _IOWR(KGSL_IOC_TYPE, 0x33, struct kgsl_timestamp_event) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #endif diff --git a/kernel-headers/linux/msm_mdp.h b/kernel-headers/linux/msm_mdp.h index 72e9072..1ec4553 100644 --- a/kernel-headers/linux/msm_mdp.h +++ b/kernel-headers/linux/msm_mdp.h @@ -67,211 +67,216 @@ #define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, struct mdp_display_commit) +#define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 165, unsigned int) +#define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) #define FB_TYPE_3D_PANEL 0x10101010 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_IMGTYPE2_START 0x10000 #define MSMFB_DRIVER_VERSION 0xF9E8D701 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum { NOTIFY_UPDATE_START, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ NOTIFY_UPDATE_STOP, }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum { MDP_RGB_565, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_XRGB_8888, MDP_Y_CBCR_H2V2, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_Y_CBCR_H2V2_ADRENO, MDP_ARGB_8888, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_RGB_888, MDP_Y_CRCB_H2V2, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_YCRYCB_H2V1, MDP_Y_CRCB_H2V1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_Y_CBCR_H2V1, MDP_Y_CRCB_H1V2, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_Y_CBCR_H1V2, MDP_RGBA_8888, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_BGRA_8888, MDP_RGBX_8888, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_Y_CRCB_H2V2_TILE, MDP_Y_CBCR_H2V2_TILE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_Y_CR_CB_H2V2, MDP_Y_CR_CB_GH2V2, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_Y_CB_CR_H2V2, MDP_Y_CRCB_H1V1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_Y_CBCR_H1V1, MDP_YCRCB_H1V1, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_YCBCR_H1V1, MDP_BGR_565, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_IMGTYPE_LIMIT, MDP_RGB_BORDERFILL, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_FB_FORMAT = MDP_IMGTYPE2_START, MDP_IMGTYPE_LIMIT2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; enum { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ PMEM_IMG, FB_IMG, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; enum { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ HSIC_HUE = 0, HSIC_SAT, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ HSIC_INT, HSIC_CON, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ NUM_HSIC_PARAM, }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDSS_MDP_ROT_ONLY 0x80 #define MDSS_MDP_RIGHT_MIXER 0x100 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_ROT_NOP 0 #define MDP_FLIP_LR 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_FLIP_UD 0x2 #define MDP_ROT_90 0x4 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR) #define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_DITHER 0x8 #define MDP_BLUR 0x10 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_BLEND_FG_PREMULT 0x20000 #define MDP_DEINTERLACE 0x80000000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_SHARPENING 0x40000000 #define MDP_NO_DMA_BARRIER_START 0x20000000 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_NO_DMA_BARRIER_END 0x10000000 #define MDP_NO_BLIT 0x08000000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_BLIT_WITH_DMA_BARRIERS 0x000 #define MDP_BLIT_WITH_NO_DMA_BARRIERS (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_BLIT_SRC_GEM 0x04000000 #define MDP_BLIT_DST_GEM 0x02000000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_BLIT_NON_CACHED 0x01000000 #define MDP_OV_PIPE_SHARE 0x00800000 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_DEINTERLACE_ODD 0x00400000 #define MDP_OV_PLAY_NOWAIT 0x00200000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_SOURCE_ROTATED_90 0x00100000 #define MDP_OVERLAY_PP_CFG_EN 0x00080000 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_BACKEND_COMPOSITION 0x00040000 #define MDP_BORDERFILL_SUPPORTED 0x00010000 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_SECURE_OVERLAY_SESSION 0x00008000 #define MDP_MEMORY_ID_TYPE_FB 0x00001000 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_TRANSP_NOP 0xffffffff #define MDP_ALPHA_NOP 0xff +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_FB_PAGE_PROTECTION_NONCACHED (0) #define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) #define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) #define MDP_FB_PAGE_PROTECTION_INVALID (5) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) struct mdp_rect { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t x; uint32_t y; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t w; uint32_t h; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct mdp_img { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t width; uint32_t height; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t format; uint32_t offset; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int memory_id; uint32_t priv; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define MDP_CCS_RGB2YUV 0 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_CCS_YUV2RGB 1 #define MDP_CCS_SIZE 9 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_BV_SIZE 3 struct mdp_ccs { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int direction; uint16_t ccs[MDP_CCS_SIZE]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t bv[MDP_BV_SIZE]; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_csc { int id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t csc_mv[9]; uint32_t csc_pre_bv[3]; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t csc_post_bv[3]; uint32_t csc_pre_lv[6]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t csc_post_lv[6]; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_BLIT_REQ_VERSION 2 struct mdp_blit_req { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_img src; struct mdp_img dst; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_rect src_rect; struct mdp_rect dst_rect; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t alpha; uint32_t transp_mask; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t flags; int sharpening_strength; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct mdp_blit_req_list { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t count; struct mdp_blit_req req[]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define MSMFB_DATA_VERSION 2 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msmfb_data { uint32_t offset; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int memory_id; int id; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t flags; uint32_t priv; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t iova; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MSMFB_NEW_REQUEST -1 struct msmfb_overlay_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t id; struct msmfb_data data; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t version_key; struct msmfb_data plane1_data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msmfb_data plane2_data; struct msmfb_data dst_data; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct msmfb_img { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t width; uint32_t height; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t format; }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 struct msmfb_writeback_data { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msmfb_data buf_info; struct msmfb_img img; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +#define MDP_PP_OPS_ENABLE 0x1 #define MDP_PP_OPS_READ 0x2 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_PP_OPS_WRITE 0x4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_PP_OPS_DISABLE 0x8 struct mdp_qseed_cfg { uint32_t table_num; uint32_t ops; @@ -284,174 +289,214 @@ struct mdp_qseed_cfg_data { uint32_t block; struct mdp_qseed_cfg qseed_data; }; -#define MDP_OVERLAY_PP_CSC_CFG 0x1 +struct mdp_sharp_cfg { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t flags; + uint32_t strength; + uint32_t edge_thr; + uint32_t smooth_thr; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t noise_thr; +}; +#define MDP_OVERLAY_PP_CSC_CFG 0x1 #define MDP_OVERLAY_PP_QSEED_CFG 0x2 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define MDP_OVERLAY_PP_PA_CFG 0x4 +#define MDP_OVERLAY_PP_IGC_CFG 0x8 +#define MDP_OVERLAY_PP_SHARP_CFG 0x10 #define MDP_CSC_FLAG_ENABLE 0x1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MDP_CSC_FLAG_YUV_IN 0x2 #define MDP_CSC_FLAG_YUV_OUT 0x4 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_csc_cfg { uint32_t flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t csc_mv[9]; uint32_t csc_pre_bv[3]; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t csc_post_bv[3]; uint32_t csc_pre_lv[6]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t csc_post_lv[6]; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_csc_cfg_data { uint32_t block; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_csc_cfg csc_data; }; +struct mdp_pa_cfg { + uint32_t flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t hue_adj; + uint32_t sat_adj; + uint32_t val_adj; + uint32_t cont_adj; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct mdp_igc_lut_data { + uint32_t block; + uint32_t len, ops; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t *c0_c1_data; + uint32_t *c2_data; +}; struct mdp_overlay_pp_params { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t config_ops; struct mdp_csc_cfg csc_cfg; struct mdp_qseed_cfg qseed_cfg[2]; + struct mdp_pa_cfg pa_cfg; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct mdp_igc_lut_data igc_cfg; + struct mdp_sharp_cfg sharp_cfg; }; struct mdp_overlay { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msmfb_img src; struct mdp_rect src_rect; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_rect dst_rect; uint32_t z_order; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t is_fg; uint32_t alpha; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t transp_mask; uint32_t flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t id; uint32_t user_data[8]; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_overlay_pp_params overlay_pp_cfg; }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msmfb_overlay_3d { uint32_t is_3d; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t width; uint32_t height; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct msmfb_overlay_blt { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t enable; uint32_t offset; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t width; uint32_t height; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t bpp; }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_histogram { uint32_t frame_cnt; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t bin_cnt; uint32_t *r; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t *g; uint32_t *b; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; enum { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_BLOCK_RESERVED = 0, MDP_BLOCK_OVERLAY_0, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_BLOCK_OVERLAY_1, MDP_BLOCK_VG_1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_BLOCK_VG_2, MDP_BLOCK_RGB_1, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_BLOCK_RGB_2, MDP_BLOCK_DMA_P, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_BLOCK_DMA_S, MDP_BLOCK_DMA_E, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MDP_BLOCK_OVERLAY_2, + MDP_LOGICAL_BLOCK_DISP_0 = 0x1000, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_LOGICAL_BLOCK_DISP_1, + MDP_LOGICAL_BLOCK_DISP_2, MDP_BLOCK_MAX, }; -struct mdp_histogram_start_req { /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct mdp_histogram_start_req { uint32_t block; uint8_t frame_cnt; uint8_t bit_mask; - uint8_t num_bins; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t num_bins; }; struct mdp_histogram_data { uint32_t block; - uint8_t bin_cnt; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint8_t bin_cnt; uint32_t *c0; uint32_t *c1; uint32_t *c2; - uint32_t *extra_info; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t *extra_info; }; struct mdp_pcc_coeff { uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; -}; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; struct mdp_pcc_cfg_data { uint32_t block; uint32_t ops; - struct mdp_pcc_coeff r, g, b; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct mdp_pcc_coeff r, g, b; }; enum { mdp_lut_igc, - mdp_lut_pgc, /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + mdp_lut_pgc, mdp_lut_hist, mdp_lut_max, }; -struct mdp_igc_lut_data { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ - uint32_t block; - uint32_t len, ops; - uint32_t *c0_c1_data; - uint32_t *c2_data; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ -}; struct mdp_ar_gc_lut_data { uint32_t x_start; uint32_t slope; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t offset; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct mdp_pgc_lut_data { uint32_t block; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t num_r_stages; uint8_t num_g_stages; uint8_t num_b_stages; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_ar_gc_lut_data *r_data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_ar_gc_lut_data *g_data; struct mdp_ar_gc_lut_data *b_data; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_hist_lut_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t block; uint32_t ops; uint32_t len; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t *data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct mdp_lut_cfg_data { uint32_t lut_type; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ union { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_igc_lut_data igc_lut_data; struct mdp_pgc_lut_data pgc_lut_data; struct mdp_hist_lut_data hist_lut_data; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ } data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct mdp_bl_scale_data { uint32_t min_lvl; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t scale; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct mdp_calib_config_data { + uint32_t ops; + uint32_t addr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t data; +}; +struct mdp_pa_cfg_data { + uint32_t block; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct mdp_pa_cfg pa_data; }; enum { mdp_op_pcc_cfg, @@ -461,45 +506,70 @@ enum { mdp_op_qseed_cfg, mdp_bl_scale_cfg, /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + mdp_op_calib_cfg, + mdp_op_pa_cfg, mdp_op_max, }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msmfb_mdp_pp { uint32_t op; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ union { struct mdp_pcc_cfg_data pcc_cfg_data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_csc_cfg_data csc_cfg_data; struct mdp_lut_cfg_data lut_cfg_data; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct mdp_qseed_cfg_data qseed_cfg_data; struct mdp_bl_scale_data bl_scale_data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct mdp_calib_config_data calib_cfg; + struct mdp_pa_cfg_data pa_cfg_data; } data; }; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +enum { + metadata_op_none, + metadata_op_base_blend, + metadata_op_frame_rate, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + metadata_op_max +}; +struct mdp_blend_cfg { + uint32_t is_premultiplied; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct msmfb_metadata { + uint32_t op; + uint32_t flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + union { + struct mdp_blend_cfg blend_cfg; + uint32_t panel_frame_rate; + } data; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; #define MDP_MAX_FENCE_FD 10 #define MDP_BUF_SYNC_FLAG_WAIT 1 struct mdp_buf_sync { - uint32_t flags; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t flags; uint32_t acq_fen_fd_cnt; int *acq_fen_fd; int *rel_fen_fd; -}; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; struct mdp_buf_fence { uint32_t flags; uint32_t acq_fen_fd_cnt; - int acq_fen_fd[MDP_MAX_FENCE_FD]; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int acq_fen_fd[MDP_MAX_FENCE_FD]; int rel_fen_fd[MDP_MAX_FENCE_FD]; }; #define MDP_DISPLAY_COMMIT_OVERLAY 0x00000001 -struct mdp_display_commit { /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct mdp_display_commit { uint32_t flags; uint32_t wait_for_finish; struct fb_var_screeninfo var; - struct mdp_buf_fence buf_fence; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct mdp_page_protection { @@ -527,4 +597,13 @@ enum { ROTATOR_SUBSYSTEM_ID, /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +enum { + MDP_WRITEBACK_MIRROR_OFF, + MDP_WRITEBACK_MIRROR_ON, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + MDP_WRITEBACK_MIRROR_PAUSE, + MDP_WRITEBACK_MIRROR_RESUME, +}; #endif +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + diff --git a/kernel-headers/linux/msm_q6vdec.h b/kernel-headers/linux/msm_q6vdec.h index d1281b0..68a2404 100644 --- a/kernel-headers/linux/msm_q6vdec.h +++ b/kernel-headers/linux/msm_q6vdec.h @@ -33,6 +33,11 @@ /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VDEC_IOCTL_FREEBUFFERS _IOW(VDEC_IOCTL_MAGIC, 9, struct vdec_buf_info) #define VDEC_IOCTL_GETDECATTRIBUTES _IOR(VDEC_IOCTL_MAGIC, 10, struct vdec_dec_attributes) +#define VDEC_IOCTL_GETVERSION _IOR(VDEC_IOCTL_MAGIC, 11, struct vdec_version) +#define VDEC_IOCTL_SETPROPERTY _IOW (VDEC_IOCTL_MAGIC, 12, struct vdec_property_info) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_IOCTL_GETPROPERTY _IOR (VDEC_IOCTL_MAGIC, 13, struct vdec_property_info) +#define VDEC_IOCTL_PERFORMANCE_CHANGE_REQ _IOW(VDEC_IOCTL_MAGIC, 14, unsigned int) enum { VDEC_FRAME_DECODE_OK, /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ @@ -67,165 +72,241 @@ enum { VDEC_QUEUE_BADSTATE, /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +enum { + VDEC_COLOR_FORMAT_NV21 = 0x01, + VDEC_COLOR_FORMAT_NV21_YAMOTO = 0x02 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + }; +enum vdec_property_id { + VDEC_FOURCC, + VDEC_PROFILE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_LEVEL, + VDEC_DIMENSIONS, + VDEC_CWIN, + VDEC_INPUT_BUF_REQ, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_OUTPUT_BUF_REQ, + VDEC_LUMA_CHROMA_STRIDE, + VDEC_NUM_DAL_PORTS, + VDEC_PRIORITY, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + VDEC_FRAME_ALIGNMENT +}; +enum { + PERF_REQUEST_SET_MIN = 0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + PERF_REQUEST_LOWER, + PERF_REQUEST_RAISE, + PERF_REQUEST_SET_MAX +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct vdec_input_buf_info { u32 offset; u32 data; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int timestamp_lo; int timestamp_hi; int avsync_state; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct vdec_buf_desc { u32 bufsize; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 num_min_buffers; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 num_max_buffers; }; struct vdec_buf_req { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 max_input_queue_size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct vdec_buf_desc input; struct vdec_buf_desc output; struct vdec_buf_desc dec_req1; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct vdec_buf_desc dec_req2; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct vdec_region_info { u32 src_id; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 offset; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 size; }; struct vdec_config { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 fourcc; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 width; u32 height; u32 order; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 notify_enable; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 vc1_rowbase; u32 h264_startcode_detect; u32 h264_nal_len_size; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 postproc_flag; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 fruc_enable; - u32 reserved; + u32 color_format; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct vdec_vc1_panscan_regions { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int num; int width[4]; int height[4]; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int xoffset[4]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int yoffset[4]; }; struct vdec_cropping_window { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 x1; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 y1; u32 x2; u32 y2; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct vdec_frame_info { u32 status; u32 offset; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 data1; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 data2; int timestamp_lo; int timestamp_hi; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int cal_timestamp_lo; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int cal_timestamp_hi; u32 dec_width; u32 dec_height; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct vdec_cropping_window cwin; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 picture_type[2]; u32 picture_format; u32 vc1_rangeY; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 vc1_rangeUV; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 picture_resolution; u32 frame_disp_repeat; u32 repeat_first_field; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 top_field_first; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 interframe_interp; struct vdec_vc1_panscan_regions panscan; u32 concealed_macblk_num; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 flags; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 performance_stats; u32 data3; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct vdec_buf_info { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 buf_type; struct vdec_region_info region; u32 num_buf; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 islast; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct vdec_buffer { u32 pmem_id; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct vdec_buf_info buf; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct vdec_sequence { u8 *header; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 len; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct vdec_config_sps { struct vdec_config cfg; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct vdec_sequence seq; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define VDEC_MSG_REUSEINPUTBUFFER 1 #define VDEC_MSG_FRAMEDONE 2 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct vdec_msg { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 id; union { u32 buf_id; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct vdec_frame_info vfr_info; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; }; struct vdec_init { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct vdec_config_sps sps_cfg; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct vdec_buf_req *buf_req; }; struct vdec_input_buf { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 pmem_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct vdec_input_buf_info buffer; struct vdec_queue_status *queue_status; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct vdec_queue_status { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 status; }; struct vdec_dec_attributes { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 fourcc; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 profile; u32 level; u32 dec_pic_width; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ u32 dec_pic_height; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct vdec_buf_desc input; struct vdec_buf_desc output; struct vdec_buf_desc dec_req1; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct vdec_buf_desc dec_req2; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct vdec_version { + u32 major; + u32 minor; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct dal_vdec_rectangle { + u32 width; + u32 height; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct stride_type { + u32 luma; + u32 chroma; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct frame_alignment_type { + u32 luma_width; + u32 luma_height; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + u32 chroma_width; + u32 chroma_height; + u32 chroma_offset; +}; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +union vdec_property { + u32 fourcc; + u32 profile; + u32 level; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct dal_vdec_rectangle dim; + struct vdec_cropping_window cw; + struct vdec_buf_desc input_req; + struct vdec_buf_desc output_req; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct stride_type stride; + u32 num_dal_ports; + u32 priority; + struct frame_alignment_type frame_alignment; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + u32 def_type; +}; +struct vdec_property_info { + enum vdec_property_id id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + union vdec_property property; }; #endif + diff --git a/kernel-headers/linux/msm_q6venc.h b/kernel-headers/linux/msm_q6venc.h index a214de5..ef9a44f 100755 --- a/kernel-headers/linux/msm_q6venc.h +++ b/kernel-headers/linux/msm_q6venc.h @@ -114,57 +114,57 @@ enum venc_mem_region_enum { VENC_PMEM_SMI }; struct venc_buf_type { - unsigned int region; + u32 region; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ - unsigned int phys; - unsigned int size; + u32 phys; + u32 size; int offset; }; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct venc_qp_range { - unsigned int min_qp; - unsigned int max_qp; + u32 min_qp; + u32 max_qp; }; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct venc_frame_rate { - unsigned int frame_rate_num; - unsigned int frame_rate_den; + u32 frame_rate_num; + u32 frame_rate_den; }; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct venc_slice_info { - unsigned int slice_mode; - unsigned int units_per_slice; + u32 slice_mode; + u32 units_per_slice; }; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct venc_extra_data { - unsigned int slice_extra_data_flag; - unsigned int slice_client_data1; - unsigned int slice_client_data2; + u32 slice_extra_data_flag; + u32 slice_client_data1; + u32 slice_client_data2; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ - unsigned int slice_client_data3; - unsigned int none_extra_data_flag; - unsigned int none_client_data1; - unsigned int none_client_data2; + u32 slice_client_data3; + u32 none_extra_data_flag; + u32 none_client_data1; + u32 none_client_data2; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ - unsigned int none_client_data3; + u32 none_client_data3; }; struct venc_common_config { - unsigned int standard; + u32 standard; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ - unsigned int input_frame_height; - unsigned int input_frame_width; - unsigned int output_frame_height; - unsigned int output_frame_width; + u32 input_frame_height; + u32 input_frame_width; + u32 output_frame_height; + u32 output_frame_width; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ - unsigned int rotation_angle; - unsigned int intra_period; - unsigned int rate_control; + u32 rotation_angle; + u32 intra_period; + u32 rate_control; struct venc_frame_rate frame_rate; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ - unsigned int bitrate; + u32 bitrate; struct venc_qp_range qp_range; - unsigned int iframe_qp; - unsigned int pframe_qp; + u32 iframe_qp; + u32 pframe_qp; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct venc_slice_info slice_config; struct venc_extra_data extra_data; @@ -179,50 +179,50 @@ struct venc_nonio_buf_config { struct venc_buf_type vlc_buf; }; struct venc_mpeg4_config { - unsigned int profile; + u32 profile; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ - unsigned int level; - unsigned int time_resolution; - unsigned int ac_prediction; - unsigned int hec_interval; + u32 level; + u32 time_resolution; + u32 ac_prediction; + u32 hec_interval; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ - unsigned int data_partition; - unsigned int short_header; - unsigned int rvlc_enable; + u32 data_partition; + u32 short_header; + u32 rvlc_enable; }; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct venc_h263_config { - unsigned int profile; - unsigned int level; + u32 profile; + u32 level; }; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct venc_h264_config { - unsigned int profile; - unsigned int level; - unsigned int max_nal; + u32 profile; + u32 level; + u32 max_nal; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ - unsigned int idr_period; + u32 idr_period; }; struct venc_pmem { int src; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int fd; - unsigned int offset; + u32 offset; void *virt; void *phys; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ - unsigned int size; + u32 size; }; struct venc_buffer { unsigned char *ptr_buffer; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ - unsigned int size; - unsigned int len; - unsigned int offset; + u32 size; + u32 len; + u32 offset; long long time_stamp; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ - unsigned int flags; - unsigned int client_data; + u32 flags; + u32 client_data; }; struct venc_buffers { /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ @@ -233,7 +233,7 @@ struct venc_buffers { /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct venc_buffer_flush { - unsigned int flush_mode; + u32 flush_mode; }; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ union venc_msg_data { @@ -242,11 +242,11 @@ union venc_msg_data { }; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct venc_msg { - unsigned int status_code; - unsigned int msg_code; - union venc_msg_data msg_data; + u32 status_code; + u32 msg_code; + u32 msg_data_size; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ - unsigned int msg_data_size; + union venc_msg_data msg_data; }; union venc_codec_config { struct venc_mpeg4_config mpeg4_params; @@ -278,6 +278,11 @@ struct venc_seq_config { /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct venc_q6_config q6_config; }; +struct venc_version { + u32 major; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + u32 minor; +}; #define VENC_IOCTL_MAGIC 'V' #define VENC_IOCTL_CMD_READ_NEXT_MSG _IOWR(VENC_IOCTL_MAGIC, 1, struct venc_msg) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ @@ -302,4 +307,6 @@ struct venc_seq_config { #define VENC_IOCTL_SET_TARGET_BITRATE _IOW(VENC_IOCTL_MAGIC, 17, int) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VENC_IOCTL_SET_QP_RANGE _IOW(VENC_IOCTL_MAGIC, 18, struct venc_qp_range) +#define VENC_IOCTL_GET_VERSION _IOR(VENC_IOCTL_MAGIC, 19, struct venc_version) #endif + diff --git a/kernel-headers/linux/msm_rmnet.h b/kernel-headers/linux/msm_rmnet.h index 0ca2dfc..f985682 100644 --- a/kernel-headers/linux/msm_rmnet.h +++ b/kernel-headers/linux/msm_rmnet.h @@ -39,15 +39,18 @@ enum rmnet_ioctl_cmds_e { RMNET_IOCTL_GET_OPMODE = 0x000089F7, RMNET_IOCTL_OPEN = 0x000089F8, RMNET_IOCTL_CLOSE = 0x000089F9, - RMNET_IOCTL_MAX + RMNET_IOCTL_FLOW_ENABLE = 0x000089FA, /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + RMNET_IOCTL_FLOW_DISABLE = 0x000089FB, + RMNET_IOCTL_MAX }; #define QMI_QOS_HDR_S __attribute((__packed__)) qmi_qos_hdr_s +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct QMI_QOS_HDR_S { unsigned char version; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned char flags; unsigned long flow_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #endif -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + diff --git a/kernel-headers/linux/msm_rotator.h b/kernel-headers/linux/msm_rotator.h index d731b76..2e57191 100644 --- a/kernel-headers/linux/msm_rotator.h +++ b/kernel-headers/linux/msm_rotator.h @@ -73,3 +73,4 @@ struct msm_rotator_platform_data { /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #endif + diff --git a/kernel-headers/linux/msm_vidc_dec.h b/kernel-headers/linux/msm_vidc_dec.h index 074b7c3..66b2a30 100644 --- a/kernel-headers/linux/msm_vidc_dec.h +++ b/kernel-headers/linux/msm_vidc_dec.h @@ -81,88 +81,98 @@ #define VDEC_EXTRADATA_VUI 0x020 #define VDEC_EXTRADATA_VC1 0x040 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_EXTRADATA_EXT_DATA 0x0800 +#define VDEC_EXTRADATA_USER_DATA 0x1000 +#define VDEC_EXTRADATA_EXT_BUFFER 0x2000 #define VDEC_CMDBASE 0x800 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VDEC_CMD_SET_INTF_VERSION (VDEC_CMDBASE) #define VDEC_IOCTL_MAGIC 'v' struct vdec_ioctl_msg { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ void __user *in; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ void __user *out; }; #define VDEC_IOCTL_GET_PROFILE_LEVEL_SUPPORTED _IOWR(VDEC_IOCTL_MAGIC, 0, struct vdec_ioctl_msg) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VDEC_IOCTL_GET_INTERLACE_FORMAT _IOR(VDEC_IOCTL_MAGIC, 1, struct vdec_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VDEC_IOCTL_GET_CURRENT_PROFILE_LEVEL _IOWR(VDEC_IOCTL_MAGIC, 2, struct vdec_ioctl_msg) #define VDEC_IOCTL_SET_OUTPUT_FORMAT _IOWR(VDEC_IOCTL_MAGIC, 3, struct vdec_ioctl_msg) #define VDEC_IOCTL_GET_OUTPUT_FORMAT _IOWR(VDEC_IOCTL_MAGIC, 4, struct vdec_ioctl_msg) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VDEC_IOCTL_SET_CODEC _IOW(VDEC_IOCTL_MAGIC, 5, struct vdec_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VDEC_IOCTL_GET_CODEC _IOR(VDEC_IOCTL_MAGIC, 6, struct vdec_ioctl_msg) #define VDEC_IOCTL_SET_PICRES _IOW(VDEC_IOCTL_MAGIC, 7, struct vdec_ioctl_msg) #define VDEC_IOCTL_GET_PICRES _IOR(VDEC_IOCTL_MAGIC, 8, struct vdec_ioctl_msg) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VDEC_IOCTL_SET_EXTRADATA _IOW(VDEC_IOCTL_MAGIC, 9, struct vdec_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VDEC_IOCTL_GET_EXTRADATA _IOR(VDEC_IOCTL_MAGIC, 10, struct vdec_ioctl_msg) #define VDEC_IOCTL_SET_SEQUENCE_HEADER _IOW(VDEC_IOCTL_MAGIC, 11, struct vdec_ioctl_msg) #define VDEC_IOCTL_SET_BUFFER_REQ _IOW(VDEC_IOCTL_MAGIC, 12, struct vdec_ioctl_msg) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VDEC_IOCTL_GET_BUFFER_REQ _IOR(VDEC_IOCTL_MAGIC, 13, struct vdec_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VDEC_IOCTL_ALLOCATE_BUFFER _IOWR(VDEC_IOCTL_MAGIC, 14, struct vdec_ioctl_msg) #define VDEC_IOCTL_FREE_BUFFER _IOW(VDEC_IOCTL_MAGIC, 15, struct vdec_ioctl_msg) #define VDEC_IOCTL_SET_BUFFER _IOW(VDEC_IOCTL_MAGIC, 16, struct vdec_ioctl_msg) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VDEC_IOCTL_FILL_OUTPUT_BUFFER _IOW(VDEC_IOCTL_MAGIC, 17, struct vdec_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VDEC_IOCTL_DECODE_FRAME _IOW(VDEC_IOCTL_MAGIC, 18, struct vdec_ioctl_msg) #define VDEC_IOCTL_LOAD_RESOURCES _IO(VDEC_IOCTL_MAGIC, 19) #define VDEC_IOCTL_CMD_START _IO(VDEC_IOCTL_MAGIC, 20) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VDEC_IOCTL_CMD_STOP _IO(VDEC_IOCTL_MAGIC, 21) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VDEC_IOCTL_CMD_PAUSE _IO(VDEC_IOCTL_MAGIC, 22) #define VDEC_IOCTL_CMD_RESUME _IO(VDEC_IOCTL_MAGIC, 23) #define VDEC_IOCTL_CMD_FLUSH _IOW(VDEC_IOCTL_MAGIC, 24, struct vdec_ioctl_msg) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VDEC_IOCTL_GET_NEXT_MSG _IOR(VDEC_IOCTL_MAGIC, 25, struct vdec_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VDEC_IOCTL_STOP_NEXT_MSG _IO(VDEC_IOCTL_MAGIC, 26) #define VDEC_IOCTL_GET_NUMBER_INSTANCES _IOR(VDEC_IOCTL_MAGIC, 27, struct vdec_ioctl_msg) #define VDEC_IOCTL_SET_PICTURE_ORDER _IOW(VDEC_IOCTL_MAGIC, 28, struct vdec_ioctl_msg) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VDEC_IOCTL_SET_FRAME_RATE _IOW(VDEC_IOCTL_MAGIC, 29, struct vdec_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VDEC_IOCTL_SET_H264_MV_BUFFER _IOW(VDEC_IOCTL_MAGIC, 30, struct vdec_ioctl_msg) #define VDEC_IOCTL_FREE_H264_MV_BUFFER _IOW(VDEC_IOCTL_MAGIC, 31, struct vdec_ioctl_msg) #define VDEC_IOCTL_GET_MV_BUFFER_SIZE _IOR(VDEC_IOCTL_MAGIC, 32, struct vdec_ioctl_msg) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VDEC_IOCTL_SET_IDR_ONLY_DECODING _IO(VDEC_IOCTL_MAGIC, 33) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VDEC_IOCTL_SET_CONT_ON_RECONFIG _IO(VDEC_IOCTL_MAGIC, 34) #define VDEC_IOCTL_SET_DISABLE_DMX _IOW(VDEC_IOCTL_MAGIC, 35, struct vdec_ioctl_msg) #define VDEC_IOCTL_GET_DISABLE_DMX _IOR(VDEC_IOCTL_MAGIC, 36, struct vdec_ioctl_msg) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VDEC_IOCTL_GET_DISABLE_DMX_SUPPORT _IOR(VDEC_IOCTL_MAGIC, 37, struct vdec_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VDEC_IOCTL_SET_PERF_CLK _IOR(VDEC_IOCTL_MAGIC, 38, struct vdec_ioctl_msg) +#define VDEC_IOCTL_SET_META_BUFFERS _IOW(VDEC_IOCTL_MAGIC, 39, struct vdec_ioctl_msg) +#define VDEC_IOCTL_FREE_META_BUFFERS _IO(VDEC_IOCTL_MAGIC, 40) +#define VDEC_IOCTL_GET_ENABLE_SEC_METADATA _IOR(VDEC_IOCTL_MAGIC, 41, struct vdec_ioctl_msg) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum vdec_picture { PICTURE_TYPE_I, PICTURE_TYPE_P, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ PICTURE_TYPE_B, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ PICTURE_TYPE_BI, PICTURE_TYPE_SKIP, PICTURE_TYPE_IDR, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ PICTURE_TYPE_UNKNOWN +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; enum vdec_buffer { VDEC_BUFFER_TYPE_INPUT, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ VDEC_BUFFER_TYPE_OUTPUT +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct vdec_allocatorproperty { enum vdec_buffer buffer_type; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t mincount; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t maxcount; uint32_t actualcount; size_t buffer_size; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t alignment; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t buf_poolid; + size_t meta_buffer_size; }; struct vdec_bufferpayload { /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ @@ -487,6 +497,11 @@ struct vdec_aspectratioinfo { uint32_t par_height; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +struct vdec_sep_metadatainfo { + void __user *metabufaddr; + uint32_t size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; struct vdec_output_frameinfo { void __user *bufferaddr; size_t offset; @@ -502,38 +517,49 @@ struct vdec_output_frameinfo { enum vdec_interlaced_format interlaced_format; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct vdec_aspectratioinfo aspect_ratio_info; + struct vdec_sep_metadatainfo metadata_info; }; union vdec_msgdata { - struct vdec_output_frameinfo output_frame; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + struct vdec_output_frameinfo output_frame; void *input_frame_clientdata; }; struct vdec_msginfo { - uint32_t status_code; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + uint32_t status_code; uint32_t msgcode; union vdec_msgdata msgdata; size_t msgdatasize; -}; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; struct vdec_framerate { unsigned long fps_denominator; unsigned long fps_numerator; -}; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; struct vdec_h264_mv{ size_t size; int count; - int pmem_fd; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int pmem_fd; int offset; }; struct vdec_mv_buff_size{ - int width; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int width; int height; int size; int alignment; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct vdec_meta_buffers { + size_t size; + int count; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int pmem_fd; + int pmem_fd_iommu; + int offset; }; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #endif + diff --git a/kernel-headers/linux/msm_vidc_enc.h b/kernel-headers/linux/msm_vidc_enc.h index 9d9bc6d..2014a3f 100644 --- a/kernel-headers/linux/msm_vidc_enc.h +++ b/kernel-headers/linux/msm_vidc_enc.h @@ -151,280 +151,282 @@ #define VEN_INPUTFMT_NV21 2 #define VEN_INPUTFMT_NV12_16M2KA 3 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_INPUTFMT_NV21_16M2KA 4 #define VEN_ROTATION_0 1 #define VEN_ROTATION_90 2 #define VEN_ROTATION_180 3 -#define VEN_ROTATION_270 4 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_ROTATION_270 4 #define VEN_TIMEOUT_INFINITE 0xffffffff #define VEN_IR_OFF 1 #define VEN_IR_CYCLIC 2 -#define VEN_IR_RANDOM 3 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IR_RANDOM 3 #define VEN_IOCTLBASE_NENC 0x800 #define VEN_IOCTLBASE_ENC 0x850 struct venc_ioctl_msg{ - void __user *in; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + void __user *in; void __user *out; }; #define VEN_IOCTL_SET_INTF_VERSION _IOW(VEN_IOCTLBASE_NENC, 0, struct venc_ioctl_msg) -#define VEN_IOCTL_CMD_READ_NEXT_MSG _IOWR(VEN_IOCTLBASE_NENC, 1, struct venc_ioctl_msg) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_CMD_READ_NEXT_MSG _IOWR(VEN_IOCTLBASE_NENC, 1, struct venc_ioctl_msg) #define VEN_IOCTL_CMD_STOP_READ_MSG _IO(VEN_IOCTLBASE_NENC, 2) #define VEN_IOCTL_SET_INPUT_BUFFER_REQ _IOW(VEN_IOCTLBASE_NENC, 3, struct venc_ioctl_msg) #define VEN_IOCTL_GET_INPUT_BUFFER_REQ _IOR(VEN_IOCTLBASE_NENC, 4, struct venc_ioctl_msg) -#define VEN_IOCTL_CMD_ALLOC_INPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 5, struct venc_ioctl_msg) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_CMD_ALLOC_INPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 5, struct venc_ioctl_msg) #define VEN_IOCTL_SET_INPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 6, struct venc_ioctl_msg) #define VEN_IOCTL_CMD_FREE_INPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 7, struct venc_ioctl_msg) #define VEN_IOCTL_SET_OUTPUT_BUFFER_REQ _IOW(VEN_IOCTLBASE_NENC, 8, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_OUTPUT_BUFFER_REQ _IOR(VEN_IOCTLBASE_NENC, 9, struct venc_ioctl_msg) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_GET_OUTPUT_BUFFER_REQ _IOR(VEN_IOCTLBASE_NENC, 9, struct venc_ioctl_msg) #define VEN_IOCTL_CMD_ALLOC_OUTPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 10, struct venc_ioctl_msg) #define VEN_IOCTL_SET_OUTPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 11, struct venc_ioctl_msg) #define VEN_IOCTL_CMD_FREE_OUTPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 12, struct venc_ioctl_msg) -#define VEN_IOCTL_CMD_START _IO(VEN_IOCTLBASE_NENC, 13) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_CMD_START _IO(VEN_IOCTLBASE_NENC, 13) #define VEN_IOCTL_CMD_ENCODE_FRAME _IOW(VEN_IOCTLBASE_NENC, 14, struct venc_ioctl_msg) #define VEN_IOCTL_CMD_FILL_OUTPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 15, struct venc_ioctl_msg) #define VEN_IOCTL_CMD_FLUSH _IOW(VEN_IOCTLBASE_NENC, 16, struct venc_ioctl_msg) -#define VEN_IOCTL_CMD_PAUSE _IO(VEN_IOCTLBASE_NENC, 17) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_CMD_PAUSE _IO(VEN_IOCTLBASE_NENC, 17) #define VEN_IOCTL_CMD_RESUME _IO(VEN_IOCTLBASE_NENC, 18) #define VEN_IOCTL_CMD_STOP _IO(VEN_IOCTLBASE_NENC, 19) #define VEN_IOCTL_SET_RECON_BUFFER _IOW(VEN_IOCTLBASE_NENC, 20, struct venc_ioctl_msg) -#define VEN_IOCTL_FREE_RECON_BUFFER _IOW(VEN_IOCTLBASE_NENC, 21, struct venc_ioctl_msg) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_FREE_RECON_BUFFER _IOW(VEN_IOCTLBASE_NENC, 21, struct venc_ioctl_msg) #define VEN_IOCTL_GET_RECON_BUFFER_SIZE _IOW(VEN_IOCTLBASE_NENC, 22, struct venc_ioctl_msg) #define VEN_IOCTL_SET_BASE_CFG _IOW(VEN_IOCTLBASE_ENC, 1, struct venc_ioctl_msg) #define VEN_IOCTL_GET_BASE_CFG _IOR(VEN_IOCTLBASE_ENC, 2, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_LIVE_MODE _IOW(VEN_IOCTLBASE_ENC, 3, struct venc_ioctl_msg) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_SET_LIVE_MODE _IOW(VEN_IOCTLBASE_ENC, 3, struct venc_ioctl_msg) #define VEN_IOCTL_GET_LIVE_MODE _IOR(VEN_IOCTLBASE_ENC, 4, struct venc_ioctl_msg) #define VEN_IOCTL_SET_CODEC_PROFILE _IOW(VEN_IOCTLBASE_ENC, 5, struct venc_ioctl_msg) #define VEN_IOCTL_GET_CODEC_PROFILE _IOR(VEN_IOCTLBASE_ENC, 6, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_PROFILE_LEVEL _IOW(VEN_IOCTLBASE_ENC, 7, struct venc_ioctl_msg) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_SET_PROFILE_LEVEL _IOW(VEN_IOCTLBASE_ENC, 7, struct venc_ioctl_msg) #define VEN_IOCTL_GET_PROFILE_LEVEL _IOR(VEN_IOCTLBASE_ENC, 8, struct venc_ioctl_msg) #define VEN_IOCTL_SET_SHORT_HDR _IOW(VEN_IOCTLBASE_ENC, 9, struct venc_ioctl_msg) #define VEN_IOCTL_GET_SHORT_HDR _IOR(VEN_IOCTLBASE_ENC, 10, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_SESSION_QP _IOW(VEN_IOCTLBASE_ENC, 11, struct venc_ioctl_msg) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_SET_SESSION_QP _IOW(VEN_IOCTLBASE_ENC, 11, struct venc_ioctl_msg) #define VEN_IOCTL_GET_SESSION_QP _IOR(VEN_IOCTLBASE_ENC, 12, struct venc_ioctl_msg) #define VEN_IOCTL_SET_INTRA_PERIOD _IOW(VEN_IOCTLBASE_ENC, 13, struct venc_ioctl_msg) #define VEN_IOCTL_GET_INTRA_PERIOD _IOR(VEN_IOCTLBASE_ENC, 14, struct venc_ioctl_msg) -#define VEN_IOCTL_CMD_REQUEST_IFRAME _IO(VEN_IOCTLBASE_ENC, 15) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_CMD_REQUEST_IFRAME _IO(VEN_IOCTLBASE_ENC, 15) #define VEN_IOCTL_GET_CAPABILITY _IOR(VEN_IOCTLBASE_ENC, 16, struct venc_ioctl_msg) #define VEN_IOCTL_GET_SEQUENCE_HDR _IOR(VEN_IOCTLBASE_ENC, 17, struct venc_ioctl_msg) #define VEN_IOCTL_SET_ENTROPY_CFG _IOW(VEN_IOCTLBASE_ENC, 18, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_ENTROPY_CFG _IOR(VEN_IOCTLBASE_ENC, 19, struct venc_ioctl_msg) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_GET_ENTROPY_CFG _IOR(VEN_IOCTLBASE_ENC, 19, struct venc_ioctl_msg) #define VEN_IOCTL_SET_DEBLOCKING_CFG _IOW(VEN_IOCTLBASE_ENC, 20, struct venc_ioctl_msg) #define VEN_IOCTL_GET_DEBLOCKING_CFG _IOR(VEN_IOCTLBASE_ENC, 21, struct venc_ioctl_msg) #define VEN_IOCTL_SET_INTRA_REFRESH _IOW(VEN_IOCTLBASE_ENC, 22, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_INTRA_REFRESH _IOR(VEN_IOCTLBASE_ENC, 23, struct venc_ioctl_msg) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_GET_INTRA_REFRESH _IOR(VEN_IOCTLBASE_ENC, 23, struct venc_ioctl_msg) #define VEN_IOCTL_SET_MULTI_SLICE_CFG _IOW(VEN_IOCTLBASE_ENC, 24, struct venc_ioctl_msg) #define VEN_IOCTL_GET_MULTI_SLICE_CFG _IOR(VEN_IOCTLBASE_ENC, 25, struct venc_ioctl_msg) #define VEN_IOCTL_SET_RATE_CTRL_CFG _IOW(VEN_IOCTLBASE_ENC, 26, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_RATE_CTRL_CFG _IOR(VEN_IOCTLBASE_ENC, 27, struct venc_ioctl_msg) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_GET_RATE_CTRL_CFG _IOR(VEN_IOCTLBASE_ENC, 27, struct venc_ioctl_msg) #define VEN_IOCTL_SET_VOP_TIMING_CFG _IOW(VEN_IOCTLBASE_ENC, 28, struct venc_ioctl_msg) #define VEN_IOCTL_GET_VOP_TIMING_CFG _IOR(VEN_IOCTLBASE_ENC, 29, struct venc_ioctl_msg) #define VEN_IOCTL_SET_FRAME_RATE _IOW(VEN_IOCTLBASE_ENC, 30, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_FRAME_RATE _IOR(VEN_IOCTLBASE_ENC, 31, struct venc_ioctl_msg) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_GET_FRAME_RATE _IOR(VEN_IOCTLBASE_ENC, 31, struct venc_ioctl_msg) #define VEN_IOCTL_SET_TARGET_BITRATE _IOW(VEN_IOCTLBASE_ENC, 32, struct venc_ioctl_msg) #define VEN_IOCTL_GET_TARGET_BITRATE _IOR(VEN_IOCTLBASE_ENC, 33, struct venc_ioctl_msg) #define VEN_IOCTL_SET_ROTATION _IOW(VEN_IOCTLBASE_ENC, 34, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_ROTATION _IOR(VEN_IOCTLBASE_ENC, 35, struct venc_ioctl_msg) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_GET_ROTATION _IOR(VEN_IOCTLBASE_ENC, 35, struct venc_ioctl_msg) #define VEN_IOCTL_SET_HEC _IOW(VEN_IOCTLBASE_ENC, 36, struct venc_ioctl_msg) #define VEN_IOCTL_GET_HEC _IOR(VEN_IOCTLBASE_ENC, 37, struct venc_ioctl_msg) #define VEN_IOCTL_SET_DATA_PARTITION _IOW(VEN_IOCTLBASE_ENC, 38, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_DATA_PARTITION _IOR(VEN_IOCTLBASE_ENC, 39, struct venc_ioctl_msg) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_GET_DATA_PARTITION _IOR(VEN_IOCTLBASE_ENC, 39, struct venc_ioctl_msg) #define VEN_IOCTL_SET_RVLC _IOW(VEN_IOCTLBASE_ENC, 40, struct venc_ioctl_msg) #define VEN_IOCTL_GET_RVLC _IOR(VEN_IOCTLBASE_ENC, 41, struct venc_ioctl_msg) #define VEN_IOCTL_SET_AC_PREDICTION _IOW(VEN_IOCTLBASE_ENC, 42, struct venc_ioctl_msg) -#define VEN_IOCTL_GET_AC_PREDICTION _IOR(VEN_IOCTLBASE_ENC, 43, struct venc_ioctl_msg) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_GET_AC_PREDICTION _IOR(VEN_IOCTLBASE_ENC, 43, struct venc_ioctl_msg) #define VEN_IOCTL_SET_QP_RANGE _IOW(VEN_IOCTLBASE_ENC, 44, struct venc_ioctl_msg) #define VEN_IOCTL_GET_QP_RANGE _IOR(VEN_IOCTLBASE_ENC, 45, struct venc_ioctl_msg) #define VEN_IOCTL_GET_NUMBER_INSTANCES _IOR(VEN_IOCTLBASE_ENC, 46, struct venc_ioctl_msg) -#define VEN_IOCTL_SET_METABUFFER_MODE _IOW(VEN_IOCTLBASE_ENC, 47, struct venc_ioctl_msg) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_SET_METABUFFER_MODE _IOW(VEN_IOCTLBASE_ENC, 47, struct venc_ioctl_msg) #define VEN_IOCTL_SET_EXTRADATA _IOW(VEN_IOCTLBASE_ENC, 48, struct venc_ioctl_msg) #define VEN_IOCTL_GET_EXTRADATA _IOR(VEN_IOCTLBASE_ENC, 49, struct venc_ioctl_msg) #define VEN_IOCTL_SET_SLICE_DELIVERY_MODE _IO(VEN_IOCTLBASE_ENC, 50) -#define VEN_IOCTL_SET_SPS_PPS_FOR_IDR _IOW(VEN_IOCTLBASE_ENC, 51, struct venc_ioctl_msg) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define VEN_IOCTL_SET_SPS_PPS_FOR_IDR _IOW(VEN_IOCTLBASE_ENC, 51, struct venc_ioctl_msg) #define VEN_IOCTL_SET_VUI_BITSTREAM_RESTRICT_FLAG _IO(VEN_IOCTLBASE_ENC, 52) struct venc_switch{ unsigned char status; -}; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; struct venc_allocatorproperty{ unsigned long mincount; unsigned long maxcount; - unsigned long actualcount; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long actualcount; unsigned long datasize; unsigned long suffixsize; unsigned long alignment; - unsigned long bufpoolid; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long bufpoolid; }; struct venc_bufferpayload{ unsigned char *pbuffer; - size_t sz; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + size_t sz; int fd; unsigned int offset; unsigned int maped_size; - unsigned long filled_len; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long filled_len; }; struct venc_buffer{ unsigned char *ptrbuffer; - unsigned long sz; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long sz; unsigned long len; unsigned long offset; long long timestamp; - unsigned long flags; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long flags; void *clientdata; }; struct venc_basecfg{ - unsigned long input_width; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long input_width; unsigned long input_height; unsigned long dvs_width; unsigned long dvs_height; - unsigned long codectype; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long codectype; unsigned long fps_num; unsigned long fps_den; unsigned long targetbitrate; - unsigned long inputformat; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long inputformat; }; struct venc_profile{ unsigned long profile; -}; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; struct ven_profilelevel{ unsigned long level; }; -struct venc_sessionqp{ /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct venc_sessionqp{ unsigned long iframeqp; unsigned long pframqp; }; -struct venc_qprange{ /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct venc_qprange{ unsigned long maxqp; unsigned long minqp; }; -struct venc_intraperiod{ /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct venc_intraperiod{ unsigned long num_pframes; unsigned long num_bframes; }; -struct venc_seqheader{ /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct venc_seqheader{ unsigned char *hdrbufptr; unsigned long bufsize; unsigned long hdrlen; -}; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; struct venc_capability{ unsigned long codec_types; unsigned long maxframe_width; - unsigned long maxframe_height; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long maxframe_height; unsigned long maxtarget_bitrate; unsigned long maxframe_rate; unsigned long input_formats; - unsigned char dvs; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned char dvs; }; struct venc_entropycfg{ unsigned longentropysel; - unsigned long cabacmodel; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long cabacmodel; }; struct venc_dbcfg{ unsigned long db_mode; - unsigned long slicealpha_offset; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long slicealpha_offset; unsigned long slicebeta_offset; }; struct venc_intrarefresh{ - unsigned long irmode; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long irmode; unsigned long mbcount; }; struct venc_multiclicecfg{ - unsigned long mslice_mode; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long mslice_mode; unsigned long mslice_size; }; struct venc_bufferflush{ - unsigned long flush_mode; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long flush_mode; }; struct venc_ratectrlcfg{ unsigned long rcmode; -}; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; struct venc_voptimingcfg{ unsigned long voptime_resolution; }; -struct venc_framerate{ /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct venc_framerate{ unsigned long fps_denominator; unsigned long fps_numerator; }; -struct venc_targetbitrate{ /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct venc_targetbitrate{ unsigned long target_bitrate; }; struct venc_rotation{ - unsigned long rotation; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long rotation; }; struct venc_timeout{ unsigned long millisec; -}; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; struct venc_headerextension{ unsigned long header_extension; }; -struct venc_msg{ /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct venc_msg{ unsigned long statuscode; unsigned long msgcode; struct venc_buffer buf; - unsigned long msgdata_size; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long msgdata_size; }; struct venc_recon_addr{ unsigned char *pbuffer; - unsigned long buffer_size; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + unsigned long buffer_size; unsigned long pmem_fd; unsigned long offset; }; -struct venc_recon_buff_size{ /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +struct venc_recon_buff_size{ int width; int height; int size; - int alignment; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + int alignment; }; #endif + diff --git a/kernel-headers/media/msm_camera.h b/kernel-headers/media/msm_camera.h index 332ac8a..d499d67 100644 --- a/kernel-headers/media/msm_camera.h +++ b/kernel-headers/media/msm_camera.h @@ -31,7 +31,7 @@ #include <linux/time.h> #endif /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ -#include <linux/ion.h> +#include <linux/msm_ion.h> #define BIT(nr) (1UL << (nr)) #define MSM_CAM_IOCTL_MAGIC 'm' #define MSM_CAM_IOCTL_GET_SENSOR_INFO _IOR(MSM_CAM_IOCTL_MAGIC, 1, struct msm_camsensor_info *) @@ -1003,7 +1003,7 @@ enum msm_v4l2_iso_mode { /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum msm_v4l2_wb_mode { MSM_V4L2_WB_OFF, - MSM_V4L2_WB_AUTO , + MSM_V4L2_WB_AUTO, MSM_V4L2_WB_CUSTOM, /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MSM_V4L2_WB_INCANDESCENT, @@ -1086,7 +1086,7 @@ struct sensor_3d_exp_cfg { uint16_t gain_adjust; }; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ -struct sensor_3d_cali_data_t{ +struct sensor_3d_cali_data_t { unsigned char left_p_matrix[3][4][8]; unsigned char right_p_matrix[3][4][8]; unsigned char square_len[8]; @@ -1123,748 +1123,748 @@ struct sensor_init_cfg { /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define ROLLOFF_CALDATA_SIZE (17 * 13) -typedef struct -{ -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +typedef struct { unsigned short mesh_rolloff_table_size; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t r_gain[ROLLOFF_CALDATA_SIZE]; uint8_t gr_gain[ROLLOFF_CALDATA_SIZE]; uint8_t gb_gain[ROLLOFF_CALDATA_SIZE]; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t b_gain[ROLLOFF_CALDATA_SIZE]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t red_ref[17]; } rolloff_caldata_array_type; struct sensor_calib_data { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t r_over_g; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t b_over_g; uint16_t gr_over_gb; uint16_t macro_2_inf; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t inf_2_macro; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t stroke_amt; uint16_t af_pos_1m; uint16_t af_pos_inf; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ rolloff_caldata_array_type rolloff; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; enum msm_sensor_resolution_t { MSM_SENSOR_RES_FULL, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MSM_SENSOR_RES_QTR, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MSM_SENSOR_RES_2, MSM_SENSOR_RES_3, MSM_SENSOR_RES_4, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MSM_SENSOR_RES_5, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MSM_SENSOR_RES_6, MSM_SENSOR_RES_7, MSM_SENSOR_INVALID_RES, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msm_sensor_output_info_t { uint16_t x_output; uint16_t y_output; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t line_length_pclk; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t frame_length_lines; uint32_t vt_pixel_clk; uint32_t op_pixel_clk; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t binning_factor; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct sensor_output_info_t { struct msm_sensor_output_info_t *output_info; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t num_info; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct mirror_flip { int32_t x_mirror; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int32_t y_flip; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct cord { uint32_t x; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t y; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct msm_eeprom_data_t { void *eeprom_data; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t index; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct msm_camera_csid_vc_cfg { uint8_t cid; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t dt; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t decode_format; }; struct csi_lane_params_t { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t csi_lane_assign; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t csi_lane_mask; uint8_t csi_if; uint8_t csid_core; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t csid_version; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define CSI_EMBED_DATA 0x12 #define CSI_RESERVED_DATA_0 0x13 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define CSI_YUV422_8 0x1E +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define CSI_RAW8 0x2A #define CSI_RAW10 0x2B #define CSI_RAW12 0x2C -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define CSI_DECODE_6BIT 0 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define CSI_DECODE_8BIT 1 #define CSI_DECODE_10BIT 2 #define CSI_DECODE_DPCM_10_8_10 5 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ISPIF_STREAM(intf, action, vfe) (((intf)<<ISPIF_S_STREAM_SHIFT)+ (action)+((vfe)<<ISPIF_VFE_INTF_SHIFT)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ISPIF_ON_FRAME_BOUNDARY (0x01 << 0) #define ISPIF_OFF_FRAME_BOUNDARY (0x01 << 1) #define ISPIF_OFF_IMMEDIATELY (0x01 << 2) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ISPIF_S_STREAM_SHIFT 4 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define ISPIF_VFE_INTF_SHIFT 12 #define PIX_0 (0x01 << 0) #define RDI_0 (0x01 << 1) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define PIX_1 (0x01 << 2) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define RDI_1 (0x01 << 3) #define RDI_2 (0x01 << 4) enum msm_ispif_vfe_intf { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ VFE0, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ VFE1, VFE_MAX, }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum msm_ispif_intftype { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ PIX0, RDI0, PIX1, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ RDI1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ RDI2, INTF_MAX, }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum msm_ispif_vc { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ VC0, VC1, VC2, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ VC3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; enum msm_ispif_cid { CID0, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ CID1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ CID2, CID3, CID4, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ CID5, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ CID6, CID7, CID8, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ CID9, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ CID10, CID11, CID12, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ CID13, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ CID14, CID15, }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msm_ispif_params { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t intftype; uint16_t cid_mask; uint8_t csid; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t vfe_intf; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct msm_ispif_params_list { uint32_t len; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msm_ispif_params params[4]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; enum ispif_cfg_type_t { ISPIF_INIT, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ISPIF_SET_CFG, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ISPIF_SET_ON_FRAME_BOUNDARY, ISPIF_SET_OFF_FRAME_BOUNDARY, ISPIF_SET_OFF_IMMEDIATELY, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ISPIF_RELEASE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct ispif_cfg_data { enum ispif_cfg_type_t cfgtype; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ union { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t csid_version; int cmd; struct msm_ispif_params_list ispif_params; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ } cfg; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct sensor_cfg_data { int cfgtype; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int mode; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int rs; uint8_t max_steps; union { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int8_t effect; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t lens_shading; uint16_t prevl_pf; uint16_t prevp_pl; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t pictl_pf; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t pictp_pl; uint32_t pict_max_exp_lc; uint16_t p_fps; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t iso_type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct sensor_init_cfg init_info; struct sensor_pict_fps gfps; struct exp_gain_cfg exp_gain; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct focus_cfg focus; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct fps_cfg fps; struct wb_info_cfg wb_info; struct sensor_3d_exp_cfg sensor_3d_exp; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct sensor_calib_data calib_info; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct sensor_output_info_t output_info; struct msm_eeprom_data_t eeprom_data; struct csi_lane_params_t csi_lane_params; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t antibanding; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t contrast; uint8_t saturation; uint8_t sharpness; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int8_t brightness; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int ae_mode; uint8_t wb_val; int8_t exp_compensation; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct cord aec_cord; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int is_autoflash; struct mirror_flip mirror_flip; } cfg; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct damping_params_t { uint32_t damping_step; uint32_t damping_delay; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t hw_params; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; enum actuator_type { ACTUATOR_VCM, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ACTUATOR_PIEZO, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; enum msm_actuator_data_type { MSM_ACTUATOR_BYTE_DATA = 1, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MSM_ACTUATOR_WORD_DATA, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; enum msm_actuator_addr_type { MSM_ACTUATOR_BYTE_ADDR = 1, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MSM_ACTUATOR_WORD_ADDR, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; enum msm_actuator_write_type { MSM_ACTUATOR_WRITE_HW_DAMP, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MSM_ACTUATOR_WRITE_DAC, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct msm_actuator_reg_params_t { enum msm_actuator_write_type reg_write_type; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t hw_mask; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t reg_addr; uint16_t hw_shift; uint16_t data_shift; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct reg_settings_t { uint16_t reg_addr; uint16_t reg_data; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct region_params_t { uint16_t step_bound[2]; uint16_t code_per_step; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msm_actuator_move_params_t { int8_t dir; int8_t sign_dir; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int16_t dest_step_pos; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int32_t num_steps; struct damping_params_t *ringing_params; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msm_actuator_tuning_params_t { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int16_t initial_code; uint16_t pwd_step; uint16_t region_size; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t total_steps; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct region_params_t *region_params; }; struct msm_actuator_params_t { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum actuator_type act_type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t reg_tbl_size; uint16_t data_size; uint16_t init_setting_size; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t i2c_addr; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum msm_actuator_addr_type i2c_addr_type; enum msm_actuator_data_type i2c_data_type; struct msm_actuator_reg_params_t *reg_tbl_params; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct reg_settings_t *init_settings; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct msm_actuator_set_info_t { struct msm_actuator_params_t actuator_params; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msm_actuator_tuning_params_t af_tuning_params; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; struct msm_actuator_get_info_t { uint32_t focal_length_num; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t focal_length_den; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t f_number_num; uint32_t f_number_den; uint32_t f_pix_num; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t f_pix_den; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t total_f_dist_num; uint32_t total_f_dist_den; uint32_t hor_view_angle_num; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t hor_view_angle_den; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t ver_view_angle_num; uint32_t ver_view_angle_den; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum af_camera_name { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ACTUATOR_MAIN_CAM_0, ACTUATOR_MAIN_CAM_1, ACTUATOR_MAIN_CAM_2, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ACTUATOR_MAIN_CAM_3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ACTUATOR_MAIN_CAM_4, ACTUATOR_MAIN_CAM_5, ACTUATOR_WEB_CAM_0, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ACTUATOR_WEB_CAM_1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ACTUATOR_WEB_CAM_2, }; struct msm_actuator_cfg_data { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int cfgtype; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t is_af_supported; union { struct msm_actuator_move_params_t move; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msm_actuator_set_info_t set_info; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msm_actuator_get_info_t get_info; enum af_camera_name cam_name; } cfg; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msm_eeprom_support { uint16_t is_supported; uint16_t size; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t index; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t qvalue; }; struct msm_calib_wb { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t r_over_g; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t b_over_g; uint16_t gr_over_gb; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msm_calib_af { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t macro_dac; uint16_t inf_dac; uint16_t start_dac; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msm_calib_lsc { uint16_t r_gain[221]; uint16_t b_gain[221]; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t gr_gain[221]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t gb_gain[221]; }; struct pixel_t { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int x; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int y; }; struct msm_calib_dpc { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t validcount; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct pixel_t snapshot_coord[128]; struct pixel_t preview_coord[128]; struct pixel_t video_coord[128]; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msm_camera_eeprom_info_t { struct msm_eeprom_support af; struct msm_eeprom_support wb; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msm_eeprom_support lsc; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msm_eeprom_support dpc; }; struct msm_eeprom_cfg_data { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int cfgtype; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t is_eeprom_supported; union { struct msm_eeprom_data_t get_data; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msm_camera_eeprom_info_t get_info; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ } cfg; }; struct sensor_large_data { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int cfgtype; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ union { struct sensor_3d_cali_data_t sensor_3d_cali_data; } data; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum sensor_type_t { BAYER, YUV, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ JPEG_SOC, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; enum flash_type { LED_FLASH, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ STROBE_FLASH, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; enum strobe_flash_ctrl_type { STROBE_FLASH_CTRL_INIT, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ STROBE_FLASH_CTRL_CHARGE, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ STROBE_FLASH_CTRL_RELEASE }; struct strobe_flash_ctrl_data { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum strobe_flash_ctrl_type type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int charge_en; }; struct msm_camera_info { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int num_cameras; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t has_3d_support[MSM_MAX_CAMERA_SENSORS]; uint8_t is_internal_cam[MSM_MAX_CAMERA_SENSORS]; uint32_t s_mount_angle[MSM_MAX_CAMERA_SENSORS]; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ const char *video_dev_name[MSM_MAX_CAMERA_SENSORS]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum sensor_type_t sensor_type[MSM_MAX_CAMERA_SENSORS]; }; struct msm_cam_config_dev_info { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int num_config_nodes; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ const char *config_dev_name[MSM_MAX_CAMERA_CONFIGS]; int config_dev_id[MSM_MAX_CAMERA_CONFIGS]; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msm_mctl_node_info { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int num_mctl_nodes; const char *mctl_node_name[MSM_MAX_CAMERA_SENSORS]; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct flash_ctrl_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int flashtype; union { int led_state; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct strobe_flash_ctrl_data strobe_ctrl; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ } ctrl_data; }; #define GET_NAME 0 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define GET_PREVIEW_LINE_PER_FRAME 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define GET_PREVIEW_PIXELS_PER_LINE 2 #define GET_SNAPSHOT_LINE_PER_FRAME 3 #define GET_SNAPSHOT_PIXELS_PER_LINE 4 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define GET_SNAPSHOT_FPS 5 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define GET_SNAPSHOT_MAX_EP_LINE_CNT 6 struct msm_camsensor_info { char name[MAX_SENSOR_NAME]; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t flash_enabled; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t strobe_flash_enabled; uint8_t actuator_enabled; uint8_t ispif_supported; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int8_t total_steps; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t support_3d; enum flash_type flashtype; enum sensor_type_t sensor_type; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t pxlcode; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t camera_type; int mount_angle; uint32_t max_width; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t max_height; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #define V4L2_SINGLE_PLANE 0 #define V4L2_MULTI_PLANE_Y 0 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define V4L2_MULTI_PLANE_CBCR 1 +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define V4L2_MULTI_PLANE_CB 1 #define V4L2_MULTI_PLANE_CR 2 struct plane_data { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int plane_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t offset; unsigned long size; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct img_plane_info { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t width; uint32_t height; uint32_t pixelformat; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t buffer_type; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint8_t output_port; uint32_t ext_mode; uint8_t num_planes; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct plane_data plane[MAX_PLANES]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t sp_y_offset; uint32_t inst_handle; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define QCAMERA_NAME "qcamera" +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define QCAMERA_SERVER_NAME "qcamera_server" #define QCAMERA_DEVICE_GROUP_ID 1 #define QCAMERA_VNODE_GROUP_ID 2 -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum msm_cam_subdev_type { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ CSIPHY_DEV, CSID_DEV, CSIC_DEV, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ISPIF_DEV, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ VFE_DEV, AXI_DEV, VPE_DEV, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ SENSOR_DEV, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ ACTUATOR_DEV, EEPROM_DEV, GESTURE_DEV, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ IRQ_ROUTER_DEV, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ CPP_DEV, CCI_DEV, }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msm_mctl_set_sdev_data { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t revision; enum msm_cam_subdev_type sdev_type; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MSM_CAM_V4L2_IOCTL_GET_CAMERA_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MSM_CAM_V4L2_IOCTL_GET_CONFIG_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t) #define MSM_CAM_V4L2_IOCTL_GET_MCTL_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct msm_camera_v4l2_ioctl_t) #define MSM_CAM_V4L2_IOCTL_CTRL_CMD_DONE _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct msm_camera_v4l2_ioctl_t) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MSM_CAM_V4L2_IOCTL_GET_EVENT_PAYLOAD _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct msm_camera_v4l2_ioctl_t) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MSM_CAM_IOCTL_SEND_EVENT _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct v4l2_event) #define MSM_CAM_V4L2_IOCTL_CFG_VPE _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_vpe_cfg_cmd) #define MSM_CAM_V4L2_IOCTL_PRIVATE_S_CTRL _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_camera_v4l2_ioctl_t) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MSM_CAM_V4L2_IOCTL_PRIVATE_G_CTRL _IOWR('V', BASE_VIDIOC_PRIVATE + 9, struct msm_camera_v4l2_ioctl_t) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VIDIOC_MSM_VPE_INIT _IO('V', BASE_VIDIOC_PRIVATE + 15) #define VIDIOC_MSM_VPE_RELEASE _IO('V', BASE_VIDIOC_PRIVATE + 16) #define VIDIOC_MSM_VPE_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 17, struct msm_mctl_pp_params *) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VIDIOC_MSM_AXI_INIT _IO('V', BASE_VIDIOC_PRIVATE + 18) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VIDIOC_MSM_AXI_RELEASE _IO('V', BASE_VIDIOC_PRIVATE + 19) #define VIDIOC_MSM_AXI_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 20, void *) #define VIDIOC_MSM_AXI_IRQ _IOWR('V', BASE_VIDIOC_PRIVATE + 21, void *) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VIDIOC_MSM_AXI_BUF_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 22, void *) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VIDIOC_MSM_VFE_INIT _IO('V', BASE_VIDIOC_PRIVATE + 22) #define VIDIOC_MSM_VFE_RELEASE _IO('V', BASE_VIDIOC_PRIVATE + 23) struct msm_camera_v4l2_ioctl_t { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ void __user *ioctl_ptr; uint32_t len; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msm_camera_vfe_params_t { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t operation_mode; uint32_t capture_count; uint32_t skip_abort; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint16_t port_info; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t inst_handle; uint16_t cmd_type; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum msm_camss_irq_idx { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ CAMERA_SS_IRQ_0, CAMERA_SS_IRQ_1, CAMERA_SS_IRQ_2, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ CAMERA_SS_IRQ_3, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ CAMERA_SS_IRQ_4, CAMERA_SS_IRQ_5, CAMERA_SS_IRQ_6, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ CAMERA_SS_IRQ_7, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ CAMERA_SS_IRQ_8, CAMERA_SS_IRQ_9, CAMERA_SS_IRQ_10, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ CAMERA_SS_IRQ_11, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ CAMERA_SS_IRQ_12, CAMERA_SS_IRQ_MAX }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ enum msm_cam_hw_idx { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MSM_CAM_HW_MICRO, MSM_CAM_HW_CCI, MSM_CAM_HW_CSI0, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MSM_CAM_HW_CSI1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MSM_CAM_HW_CSI2, MSM_CAM_HW_CSI3, MSM_CAM_HW_ISPIF, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MSM_CAM_HW_CPP, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MSM_CAM_HW_VFE0, MSM_CAM_HW_VFE1, MSM_CAM_HW_JPEG0, -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MSM_CAM_HW_JPEG1, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MSM_CAM_HW_JPEG2, MSM_CAM_HW_MAX }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msm_camera_irq_cfg { +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t cam_hw_mask; uint8_t irq_idx; uint8_t num_hwcore; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define MSM_IRQROUTER_CFG_COMPIRQ _IOWR('V', BASE_VIDIOC_PRIVATE, void __user *) #define MAX_NUM_CPP_STRIPS 8 enum msm_cpp_frame_type { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MSM_CPP_OFFLINE_FRAME, +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ MSM_CPP_REALTIME_FRAME, }; struct msm_cpp_frame_strip_info { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int scale_v_en; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int scale_h_en; int upscale_v_en; int upscale_h_en; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int src_start_x; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int src_end_x; int src_start_y; int src_end_y; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int pad_bottom; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int pad_top; int pad_right; int pad_left; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int v_init_phase; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int h_init_phase; int h_phase_step; int v_phase_step; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int prescale_crop_width_first_pixel; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int prescale_crop_width_last_pixel; int prescale_crop_height_first_line; int prescale_crop_height_last_line; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int postscale_crop_height_first_line; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int postscale_crop_height_last_line; int postscale_crop_width_first_pixel; int postscale_crop_width_last_pixel; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int dst_start_x; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int dst_end_x; int dst_start_y; int dst_end_y; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int bytes_per_pixel; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int source_address; unsigned int destination_address; unsigned int src_stride; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ unsigned int dst_stride; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int rotate_270; int horizontal_flip; int vertical_flip; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int scale_output_width; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int scale_output_height; }; struct msm_cpp_frame_info_t { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ int32_t frame_id; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t inst_id; uint32_t client_id; enum msm_cpp_frame_type frame_type; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t num_strips; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ struct msm_cpp_frame_strip_info *strip_info; }; struct msm_ver_num_info { -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t main; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ uint32_t minor; uint32_t rev; }; -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VIDIOC_MSM_CPP_CFG _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_v4l2_ioctl_t) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define VIDIOC_MSM_CPP_GET_EVENTPAYLOAD _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t) #define VIDIOC_MSM_CPP_GET_INST_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t) #define V4L2_EVENT_CPP_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 0) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define CLR_IMG_MODE(handle) (handle &= 0xFF00FFFF) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define SET_IMG_MODE(handle, data) (handle |= ((0x1 << 23) | ((data & 0x7F) << 16))) #define GET_IMG_MODE(handle) ((handle & 0x800000) ? ((handle & 0x7F0000) >> 16) : 0xFF) #define CLR_MCTLPP_INST_IDX(handle) (handle &= 0xFFFF00FF) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define SET_MCTLPP_INST_IDX(handle, data) (handle |= ((0x1 << 15) | ((data & 0x7F) << 8))) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define GET_MCTLPP_INST_IDX(handle) ((handle & 0x8000) ? ((handle & 0x7F00) >> 8) : 0xFF) #define CLR_VIDEO_INST_IDX(handle) (handle &= 0xFFFFFF00) #define GET_VIDEO_INST_IDX(handle) ((handle & 0x80) ? (handle & 0x7F) : 0xFF) -/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #define SET_VIDEO_INST_IDX(handle, data) (handle |= (0x1 << 7) | (data & 0x7F)) +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #endif + diff --git a/kernel-headers/media/msm_gemini.h b/kernel-headers/media/msm_gemini.h index d914165..6a6f6a8 100644 --- a/kernel-headers/media/msm_gemini.h +++ b/kernel-headers/media/msm_gemini.h @@ -98,3 +98,4 @@ struct msm_gemini_hw_cmds { /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; #endif + diff --git a/kernel-headers/media/msm_gestures.h b/kernel-headers/media/msm_gestures.h index d1e2c28..47163a7 100644 --- a/kernel-headers/media/msm_gestures.h +++ b/kernel-headers/media/msm_gestures.h @@ -59,3 +59,4 @@ struct msm_ges_evt { int evt_len; }; #endif + diff --git a/kernel-headers/media/msm_isp.h b/kernel-headers/media/msm_isp.h index 93e2659..f7163dd 100644 --- a/kernel-headers/media/msm_isp.h +++ b/kernel-headers/media/msm_isp.h @@ -427,3 +427,4 @@ struct msm_frame_info { }; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ #endif + diff --git a/kernel-headers/media/msm_mercury.h b/kernel-headers/media/msm_mercury.h index 3a4599c..ca40ede 100644 --- a/kernel-headers/media/msm_mercury.h +++ b/kernel-headers/media/msm_mercury.h @@ -104,3 +104,4 @@ struct msm_mercury_hw_cmds { struct msm_mercury_hw_cmd hw_cmd[1]; }; #endif + diff --git a/original-kernel-headers/linux/ion.h b/original-kernel-headers/linux/ion.h new file mode 100644 index 0000000..7fee5ff --- /dev/null +++ b/original-kernel-headers/linux/ion.h @@ -0,0 +1,610 @@ +/* + * include/linux/ion.h + * + * Copyright (C) 2011 Google, Inc. + * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _LINUX_ION_H +#define _LINUX_ION_H + +#include <linux/ioctl.h> +#include <linux/types.h> + +struct ion_handle; +/** + * enum ion_heap_types - list of all possible types of heaps + * @ION_HEAP_TYPE_SYSTEM: memory allocated via vmalloc + * @ION_HEAP_TYPE_SYSTEM_CONTIG: memory allocated via kmalloc + * @ION_HEAP_TYPE_CARVEOUT: memory allocated from a prereserved + * carveout heap, allocations are physically + * contiguous + * @ION_HEAP_TYPE_IOMMU: IOMMU memory + * @ION_HEAP_TYPE_CP: memory allocated from a prereserved + * carveout heap, allocations are physically + * contiguous. Used for content protection. + * @ION_HEAP_TYPE_DMA: memory allocated via DMA API + * @ION_HEAP_END: helper for iterating over heaps + */ +enum ion_heap_type { + ION_HEAP_TYPE_SYSTEM, + ION_HEAP_TYPE_SYSTEM_CONTIG, + ION_HEAP_TYPE_CARVEOUT, + ION_HEAP_TYPE_DMA, + ION_HEAP_TYPE_CUSTOM, /* must be last so device specific heaps always + are at the end of this enum */ + ION_NUM_HEAPS, +}; + +#define ION_HEAP_SYSTEM_MASK (1 << ION_HEAP_TYPE_SYSTEM) +#define ION_HEAP_SYSTEM_CONTIG_MASK (1 << ION_HEAP_TYPE_SYSTEM_CONTIG) +#define ION_HEAP_CARVEOUT_MASK (1 << ION_HEAP_TYPE_CARVEOUT) +#define ION_HEAP_TYPE_DMA_MASK (1 << ION_HEAP_TYPE_DMA) + +/** + * heap flags - the lower 16 bits are used by core ion, the upper 16 + * bits are reserved for use by the heaps themselves. + */ +#define ION_FLAG_CACHED 1 /* mappings of this buffer should be + cached, ion will do cache + maintenance when the buffer is + mapped for dma */ + +#ifdef __KERNEL__ +#include <linux/err.h> +#include <mach/ion.h> +struct ion_device; +struct ion_heap; +struct ion_mapper; +struct ion_client; +struct ion_buffer; + +/* This should be removed some day when phys_addr_t's are fully + plumbed in the kernel, and all instances of ion_phys_addr_t should + be converted to phys_addr_t. For the time being many kernel interfaces + do not accept phys_addr_t's that would have to */ +#define ion_phys_addr_t unsigned long +#define ion_virt_addr_t unsigned long + +/** + * struct ion_platform_heap - defines a heap in the given platform + * @type: type of the heap from ion_heap_type enum + * @id: unique identifier for heap. When allocating (lower numbers + * will be allocated from first) + * @name: used for debug purposes + * @base: base address of heap in physical memory if applicable + * @size: size of the heap in bytes if applicable + * @memory_type:Memory type used for the heap + * @has_outer_cache: set to 1 if outer cache is used, 0 otherwise. + * @extra_data: Extra data specific to each heap type + * @priv: heap private data + */ +struct ion_platform_heap { + enum ion_heap_type type; + unsigned int id; + const char *name; + ion_phys_addr_t base; + size_t size; + enum ion_memory_types memory_type; + unsigned int has_outer_cache; + void *extra_data; + void *priv; +}; + +/** + * struct ion_platform_data - array of platform heaps passed from board file + * @has_outer_cache: set to 1 if outer cache is used, 0 otherwise. + * @nr: number of structures in the array + * @request_region: function to be called when the number of allocations goes + * from 0 -> 1 + * @release_region: function to be called when the number of allocations goes + * from 1 -> 0 + * @setup_region: function to be called upon ion registration + * @heaps: array of platform_heap structions + * + * Provided by the board file in the form of platform data to a platform device. + */ +struct ion_platform_data { + unsigned int has_outer_cache; + int nr; + int (*request_region)(void *); + int (*release_region)(void *); + void *(*setup_region)(void); + struct ion_platform_heap *heaps; +}; + +#ifdef CONFIG_ION + +/** + * ion_reserve() - reserve memory for ion heaps if applicable + * @data: platform data specifying starting physical address and + * size + * + * Calls memblock reserve to set aside memory for heaps that are + * located at specific memory addresses or of specfic sizes not + * managed by the kernel + */ +void ion_reserve(struct ion_platform_data *data); + +/** + * ion_client_create() - allocate a client and returns it + * @dev: the global ion device + * @heap_mask: mask of heaps this client can allocate from + * @name: used for debugging + */ +struct ion_client *ion_client_create(struct ion_device *dev, + unsigned int heap_mask, const char *name); + +/** + * msm_ion_client_create - allocate a client using the ion_device specified in + * drivers/gpu/ion/msm/msm_ion.c + * + * heap_mask and name are the same as ion_client_create, return values + * are the same as ion_client_create. + */ + +struct ion_client *msm_ion_client_create(unsigned int heap_mask, + const char *name); + +/** + * ion_client_destroy() - free's a client and all it's handles + * @client: the client + * + * Free the provided client and all it's resources including + * any handles it is holding. + */ +void ion_client_destroy(struct ion_client *client); + +/** + * ion_alloc - allocate ion memory + * @client: the client + * @len: size of the allocation + * @align: requested allocation alignment, lots of hardware blocks have + * alignment requirements of some kind + * @heap_mask: mask of heaps to allocate from, if multiple bits are set + * heaps will be tried in order from lowest to highest order bit + * @flags: heap flags, the low 16 bits are consumed by ion, the high 16 + * bits are passed on to the respective heap and can be heap + * custom + * + * Allocate memory in one of the heaps provided in heap mask and return + * an opaque handle to it. + */ +struct ion_handle *ion_alloc(struct ion_client *client, size_t len, + size_t align, unsigned int heap_mask, + unsigned int flags); + +/** + * ion_free - free a handle + * @client: the client + * @handle: the handle to free + * + * Free the provided handle. + */ +void ion_free(struct ion_client *client, struct ion_handle *handle); + +/** + * ion_phys - returns the physical address and len of a handle + * @client: the client + * @handle: the handle + * @addr: a pointer to put the address in + * @len: a pointer to put the length in + * + * This function queries the heap for a particular handle to get the + * handle's physical address. It't output is only correct if + * a heap returns physically contiguous memory -- in other cases + * this api should not be implemented -- ion_sg_table should be used + * instead. Returns -EINVAL if the handle is invalid. This has + * no implications on the reference counting of the handle -- + * the returned value may not be valid if the caller is not + * holding a reference. + */ +int ion_phys(struct ion_client *client, struct ion_handle *handle, + ion_phys_addr_t *addr, size_t *len); + +/** + * ion_map_dma - return an sg_table describing a handle + * @client: the client + * @handle: the handle + * + * This function returns the sg_table describing + * a particular ion handle. + */ +struct sg_table *ion_sg_table(struct ion_client *client, + struct ion_handle *handle); + +/** + * ion_map_kernel - create mapping for the given handle + * @client: the client + * @handle: handle to map + * @flags: flags for this mapping + * + * Map the given handle into the kernel and return a kernel address that + * can be used to access this address. If no flags are specified, this + * will return a non-secure uncached mapping. + */ +void *ion_map_kernel(struct ion_client *client, struct ion_handle *handle); + +/** + * ion_unmap_kernel() - destroy a kernel mapping for a handle + * @client: the client + * @handle: handle to unmap + */ +void ion_unmap_kernel(struct ion_client *client, struct ion_handle *handle); + +/** + * ion_share_dma_buf() - given an ion client, create a dma-buf fd + * @client: the client + * @handle: the handle + */ +int ion_share_dma_buf(struct ion_client *client, struct ion_handle *handle); + +/** + * ion_import_dma_buf() - given an dma-buf fd from the ion exporter get handle + * @client: the client + * @fd: the dma-buf fd + * + * Given an dma-buf fd that was allocated through ion via ion_share_dma_buf, + * import that fd and return a handle representing it. If a dma-buf from + * another exporter is passed in this function will return ERR_PTR(-EINVAL) + */ +struct ion_handle *ion_import_dma_buf(struct ion_client *client, int fd); + +/** + * ion_handle_get_flags - get the flags for a given handle + * + * @client - client who allocated the handle + * @handle - handle to get the flags + * @flags - pointer to store the flags + * + * Gets the current flags for a handle. These flags indicate various options + * of the buffer (caching, security, etc.) + */ +int ion_handle_get_flags(struct ion_client *client, struct ion_handle *handle, + unsigned long *flags); + + +/** + * ion_map_iommu - map the given handle into an iommu + * + * @client - client who allocated the handle + * @handle - handle to map + * @domain_num - domain number to map to + * @partition_num - partition number to allocate iova from + * @align - alignment for the iova + * @iova_length - length of iova to map. If the iova length is + * greater than the handle length, the remaining + * address space will be mapped to a dummy buffer. + * @iova - pointer to store the iova address + * @buffer_size - pointer to store the size of the buffer + * @flags - flags for options to map + * @iommu_flags - flags specific to the iommu. + * + * Maps the handle into the iova space specified via domain number. Iova + * will be allocated from the partition specified via partition_num. + * Returns 0 on success, negative value on error. + */ +int ion_map_iommu(struct ion_client *client, struct ion_handle *handle, + int domain_num, int partition_num, unsigned long align, + unsigned long iova_length, unsigned long *iova, + unsigned long *buffer_size, + unsigned long flags, unsigned long iommu_flags); + + +/** + * ion_handle_get_size - get the allocated size of a given handle + * + * @client - client who allocated the handle + * @handle - handle to get the size + * @size - pointer to store the size + * + * gives the allocated size of a handle. returns 0 on success, negative + * value on error + * + * NOTE: This is intended to be used only to get a size to pass to map_iommu. + * You should *NOT* rely on this for any other usage. + */ + +int ion_handle_get_size(struct ion_client *client, struct ion_handle *handle, + unsigned long *size); + +/** + * ion_unmap_iommu - unmap the handle from an iommu + * + * @client - client who allocated the handle + * @handle - handle to unmap + * @domain_num - domain to unmap from + * @partition_num - partition to unmap from + * + * Decrement the reference count on the iommu mapping. If the count is + * 0, the mapping will be removed from the iommu. + */ +void ion_unmap_iommu(struct ion_client *client, struct ion_handle *handle, + int domain_num, int partition_num); + + +/** + * ion_secure_heap - secure a heap + * + * @client - a client that has allocated from the heap heap_id + * @heap_id - heap id to secure. + * @version - version of content protection + * @data - extra data needed for protection + * + * Secure a heap + * Returns 0 on success + */ +int ion_secure_heap(struct ion_device *dev, int heap_id, int version, + void *data); + +/** + * ion_unsecure_heap - un-secure a heap + * + * @client - a client that has allocated from the heap heap_id + * @heap_id - heap id to un-secure. + * @version - version of content protection + * @data - extra data needed for protection + * + * Un-secure a heap + * Returns 0 on success + */ +int ion_unsecure_heap(struct ion_device *dev, int heap_id, int version, + void *data); + +/** + * msm_ion_do_cache_op - do cache operations. + * + * @client - pointer to ION client. + * @handle - pointer to buffer handle. + * @vaddr - virtual address to operate on. + * @len - Length of data to do cache operation on. + * @cmd - Cache operation to perform: + * ION_IOC_CLEAN_CACHES + * ION_IOC_INV_CACHES + * ION_IOC_CLEAN_INV_CACHES + * + * Returns 0 on success + */ +int msm_ion_do_cache_op(struct ion_client *client, struct ion_handle *handle, + void *vaddr, unsigned long len, unsigned int cmd); + +#else +static inline void ion_reserve(struct ion_platform_data *data) +{ + +} + +static inline struct ion_client *ion_client_create(struct ion_device *dev, + unsigned int heap_mask, const char *name) +{ + return ERR_PTR(-ENODEV); +} + +static inline struct ion_client *msm_ion_client_create(unsigned int heap_mask, + const char *name) +{ + return ERR_PTR(-ENODEV); +} + +static inline void ion_client_destroy(struct ion_client *client) { } + +static inline struct ion_handle *ion_alloc(struct ion_client *client, + size_t len, size_t align, + unsigned int heap_mask, + unsigned int flags) +{ + return ERR_PTR(-ENODEV); +} + +static inline void ion_free(struct ion_client *client, + struct ion_handle *handle) { } + + +static inline int ion_phys(struct ion_client *client, + struct ion_handle *handle, ion_phys_addr_t *addr, size_t *len) +{ + return -ENODEV; +} + +static inline struct sg_table *ion_sg_table(struct ion_client *client, + struct ion_handle *handle) +{ + return ERR_PTR(-ENODEV); +} + +static inline void *ion_map_kernel(struct ion_client *client, + struct ion_handle *handle, unsigned long flags) +{ + return ERR_PTR(-ENODEV); +} + +static inline void ion_unmap_kernel(struct ion_client *client, + struct ion_handle *handle) { } + +static inline int ion_share_dma_buf(struct ion_client *client, struct ion_handle *handle) +{ + return -ENODEV; +} + +static inline struct ion_handle *ion_import_dma_buf(struct ion_client *client, int fd) +{ + return ERR_PTR(-ENODEV); +} + +static inline int ion_handle_get_flags(struct ion_client *client, + struct ion_handle *handle, unsigned long *flags) +{ + return -ENODEV; +} + +static inline int ion_map_iommu(struct ion_client *client, + struct ion_handle *handle, int domain_num, + int partition_num, unsigned long align, + unsigned long iova_length, unsigned long *iova, + unsigned long *buffer_size, + unsigned long flags, + unsigned long iommu_flags) +{ + return -ENODEV; +} + +static inline void ion_unmap_iommu(struct ion_client *client, + struct ion_handle *handle, int domain_num, + int partition_num) +{ + return; +} + +static inline int ion_secure_heap(struct ion_device *dev, int heap_id, + int version, void *data) +{ + return -ENODEV; + +} + +static inline int ion_unsecure_heap(struct ion_device *dev, int heap_id, + int version, void *data) +{ + return -ENODEV; +} + +static inline int msm_ion_do_cache_op(struct ion_client *client, + struct ion_handle *handle, void *vaddr, + unsigned long len, unsigned int cmd) +{ + return -ENODEV; +} + +#endif /* CONFIG_ION */ +#endif /* __KERNEL__ */ + +/** + * DOC: Ion Userspace API + * + * create a client by opening /dev/ion + * most operations handled via following ioctls + * + */ + +/** + * struct ion_allocation_data - metadata passed from userspace for allocations + * @len: size of the allocation + * @align: required alignment of the allocation + * @heap_mask: mask of heaps to allocate from + * @flags: flags passed to heap + * @handle: pointer that will be populated with a cookie to use to refer + * to this allocation + * + * Provided by userspace as an argument to the ioctl + */ +struct ion_allocation_data { + size_t len; + size_t align; + unsigned int heap_mask; + unsigned int flags; + struct ion_handle *handle; +}; + +/** + * struct ion_fd_data - metadata passed to/from userspace for a handle/fd pair + * @handle: a handle + * @fd: a file descriptor representing that handle + * + * For ION_IOC_SHARE or ION_IOC_MAP userspace populates the handle field with + * the handle returned from ion alloc, and the kernel returns the file + * descriptor to share or map in the fd field. For ION_IOC_IMPORT, userspace + * provides the file descriptor and the kernel returns the handle. + */ +struct ion_fd_data { + struct ion_handle *handle; + int fd; +}; + +/** + * struct ion_handle_data - a handle passed to/from the kernel + * @handle: a handle + */ +struct ion_handle_data { + struct ion_handle *handle; +}; + +/** + * struct ion_custom_data - metadata passed to/from userspace for a custom ioctl + * @cmd: the custom ioctl function to call + * @arg: additional data to pass to the custom ioctl, typically a user + * pointer to a predefined structure + * + * This works just like the regular cmd and arg fields of an ioctl. + */ +struct ion_custom_data { + unsigned int cmd; + unsigned long arg; +}; +#define ION_IOC_MAGIC 'I' + +/** + * DOC: ION_IOC_ALLOC - allocate memory + * + * Takes an ion_allocation_data struct and returns it with the handle field + * populated with the opaque handle for the allocation. + */ +#define ION_IOC_ALLOC _IOWR(ION_IOC_MAGIC, 0, \ + struct ion_allocation_data) + +/** + * DOC: ION_IOC_FREE - free memory + * + * Takes an ion_handle_data struct and frees the handle. + */ +#define ION_IOC_FREE _IOWR(ION_IOC_MAGIC, 1, struct ion_handle_data) + +/** + * DOC: ION_IOC_MAP - get a file descriptor to mmap + * + * Takes an ion_fd_data struct with the handle field populated with a valid + * opaque handle. Returns the struct with the fd field set to a file + * descriptor open in the current address space. This file descriptor + * can then be used as an argument to mmap. + */ +#define ION_IOC_MAP _IOWR(ION_IOC_MAGIC, 2, struct ion_fd_data) + +/** + * DOC: ION_IOC_SHARE - creates a file descriptor to use to share an allocation + * + * Takes an ion_fd_data struct with the handle field populated with a valid + * opaque handle. Returns the struct with the fd field set to a file + * descriptor open in the current address space. This file descriptor + * can then be passed to another process. The corresponding opaque handle can + * be retrieved via ION_IOC_IMPORT. + */ +#define ION_IOC_SHARE _IOWR(ION_IOC_MAGIC, 4, struct ion_fd_data) + +/** + * DOC: ION_IOC_IMPORT - imports a shared file descriptor + * + * Takes an ion_fd_data struct with the fd field populated with a valid file + * descriptor obtained from ION_IOC_SHARE and returns the struct with the handle + * filed set to the corresponding opaque handle. + */ +#define ION_IOC_IMPORT _IOWR(ION_IOC_MAGIC, 5, struct ion_fd_data) + +/** + * DOC: ION_IOC_CUSTOM - call architecture specific ion ioctl + * + * Takes the argument of the architecture specific ioctl to call and + * passes appropriate userdata for that ioctl + */ +#define ION_IOC_CUSTOM _IOWR(ION_IOC_MAGIC, 6, struct ion_custom_data) + + +#endif /* _LINUX_ION_H */ diff --git a/original-kernel-headers/linux/mfd/wcd9xxx/Kbuild b/original-kernel-headers/linux/mfd/wcd9xxx/Kbuild new file mode 100644 index 0000000..acfab6e --- /dev/null +++ b/original-kernel-headers/linux/mfd/wcd9xxx/Kbuild @@ -0,0 +1,2 @@ +header-y += wcd9xxx_registers.h +header-y += wcd9310_registers.h diff --git a/original-kernel-headers/linux/mfd/wcd9xxx/core.h b/original-kernel-headers/linux/mfd/wcd9xxx/core.h new file mode 100644 index 0000000..508bf3b --- /dev/null +++ b/original-kernel-headers/linux/mfd/wcd9xxx/core.h @@ -0,0 +1,220 @@ +/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MFD_TABLA_CORE_H__ +#define __MFD_TABLA_CORE_H__ + +#include <linux/interrupt.h> +#include <linux/pm_qos.h> + +#define WCD9XXX_NUM_IRQ_REGS 3 + +#define WCD9XXX_SLIM_NUM_PORT_REG 3 + +#define WCD9XXX_INTERFACE_TYPE_SLIMBUS 0x00 +#define WCD9XXX_INTERFACE_TYPE_I2C 0x01 + +#define TABLA_VERSION_1_0 0 +#define TABLA_VERSION_1_1 1 +#define TABLA_VERSION_2_0 2 +#define TABLA_IS_1_X(ver) \ + (((ver == TABLA_VERSION_1_0) || (ver == TABLA_VERSION_1_1)) ? 1 : 0) +#define TABLA_IS_2_0(ver) ((ver == TABLA_VERSION_2_0) ? 1 : 0) + +#define SITAR_VERSION_1P0 0 +#define SITAR_VERSION_1P1 1 +#define SITAR_IS_1P0(ver) \ + ((ver == SITAR_VERSION_1P0) ? 1 : 0) +#define SITAR_IS_1P1(ver) \ + ((ver == SITAR_VERSION_1P1) ? 1 : 0) + +enum { + TABLA_IRQ_SLIMBUS = 0, + TABLA_IRQ_MBHC_REMOVAL, + TABLA_IRQ_MBHC_SHORT_TERM, + TABLA_IRQ_MBHC_PRESS, + TABLA_IRQ_MBHC_RELEASE, + TABLA_IRQ_MBHC_POTENTIAL, + TABLA_IRQ_MBHC_INSERTION, + TABLA_IRQ_BG_PRECHARGE, + TABLA_IRQ_PA1_STARTUP, + TABLA_IRQ_PA2_STARTUP, + TABLA_IRQ_PA3_STARTUP, + TABLA_IRQ_PA4_STARTUP, + TABLA_IRQ_PA5_STARTUP, + TABLA_IRQ_MICBIAS1_PRECHARGE, + TABLA_IRQ_MICBIAS2_PRECHARGE, + TABLA_IRQ_MICBIAS3_PRECHARGE, + TABLA_IRQ_HPH_PA_OCPL_FAULT, + TABLA_IRQ_HPH_PA_OCPR_FAULT, + TABLA_IRQ_EAR_PA_OCPL_FAULT, + TABLA_IRQ_HPH_L_PA_STARTUP, + TABLA_IRQ_HPH_R_PA_STARTUP, + TABLA_IRQ_EAR_PA_STARTUP, + TABLA_NUM_IRQS, +}; + +enum { + SITAR_IRQ_SLIMBUS = 0, + SITAR_IRQ_MBHC_REMOVAL, + SITAR_IRQ_MBHC_SHORT_TERM, + SITAR_IRQ_MBHC_PRESS, + SITAR_IRQ_MBHC_RELEASE, + SITAR_IRQ_MBHC_POTENTIAL, + SITAR_IRQ_MBHC_INSERTION, + SITAR_IRQ_BG_PRECHARGE, + SITAR_IRQ_PA1_STARTUP, + SITAR_IRQ_PA2_STARTUP, + SITAR_IRQ_PA3_STARTUP, + SITAR_IRQ_PA4_STARTUP, + SITAR_IRQ_PA5_STARTUP, + SITAR_IRQ_MICBIAS1_PRECHARGE, + SITAR_IRQ_MICBIAS2_PRECHARGE, + SITAR_IRQ_MICBIAS3_PRECHARGE, + SITAR_IRQ_HPH_PA_OCPL_FAULT, + SITAR_IRQ_HPH_PA_OCPR_FAULT, + SITAR_IRQ_EAR_PA_OCPL_FAULT, + SITAR_IRQ_HPH_L_PA_STARTUP, + SITAR_IRQ_HPH_R_PA_STARTUP, + SITAR_IRQ_EAR_PA_STARTUP, + SITAR_NUM_IRQS, +}; + + +enum { + TAIKO_IRQ_SLIMBUS = 0, + TAIKO_IRQ_MBHC_REMOVAL, + TAIKO_IRQ_MBHC_SHORT_TERM, + TAIKO_IRQ_MBHC_PRESS, + TAIKO_IRQ_MBHC_RELEASE, + TAIKO_IRQ_MBHC_POTENTIAL, + TAIKO_IRQ_MBHC_INSERTION, + TAIKO_IRQ_BG_PRECHARGE, + TAIKO_IRQ_PA1_STARTUP, + TAIKO_IRQ_PA2_STARTUP, + TAIKO_IRQ_PA3_STARTUP, + TAIKO_IRQ_PA4_STARTUP, + TAIKO_IRQ_PA5_STARTUP, + TAIKO_IRQ_MICBIAS1_PRECHARGE, + TAIKO_IRQ_MICBIAS2_PRECHARGE, + TAIKO_IRQ_MICBIAS3_PRECHARGE, + TAIKO_IRQ_HPH_PA_OCPL_FAULT, + TAIKO_IRQ_HPH_PA_OCPR_FAULT, + TAIKO_IRQ_EAR_PA_OCPL_FAULT, + TAIKO_IRQ_HPH_L_PA_STARTUP, + TAIKO_IRQ_HPH_R_PA_STARTUP, + TAIKO_IRQ_EAR_PA_STARTUP, + TAIKO_NUM_IRQS, +}; + +enum wcd9xxx_pm_state { + WCD9XXX_PM_SLEEPABLE, + WCD9XXX_PM_AWAKE, + WCD9XXX_PM_ASLEEP, +}; + +struct wcd9xxx { + struct device *dev; + struct slim_device *slim; + struct slim_device *slim_slave; + struct mutex io_lock; + struct mutex xfer_lock; + struct mutex irq_lock; + u8 version; + + unsigned int irq_base; + unsigned int irq; + u8 irq_masks_cur[WCD9XXX_NUM_IRQ_REGS]; + u8 irq_masks_cache[WCD9XXX_NUM_IRQ_REGS]; + u8 irq_level[WCD9XXX_NUM_IRQ_REGS]; + + int reset_gpio; + + int (*read_dev)(struct wcd9xxx *wcd9xxx, unsigned short reg, + int bytes, void *dest, bool interface_reg); + int (*write_dev)(struct wcd9xxx *wcd9xxx, unsigned short reg, + int bytes, void *src, bool interface_reg); + + u32 num_of_supplies; + struct regulator_bulk_data *supplies; + + enum wcd9xxx_pm_state pm_state; + struct mutex pm_lock; + /* pm_wq notifies change of pm_state */ + wait_queue_head_t pm_wq; + struct pm_qos_request pm_qos_req; + int wlock_holders; + + int num_rx_port; + int num_tx_port; + + u8 idbyte[4]; +}; + +int wcd9xxx_reg_read(struct wcd9xxx *wcd9xxx, unsigned short reg); +int wcd9xxx_reg_write(struct wcd9xxx *wcd9xxx, unsigned short reg, + u8 val); +int wcd9xxx_interface_reg_read(struct wcd9xxx *wcd9xxx, unsigned short reg); +int wcd9xxx_interface_reg_write(struct wcd9xxx *wcd9xxx, unsigned short reg, + u8 val); +int wcd9xxx_bulk_read(struct wcd9xxx *wcd9xxx, unsigned short reg, + int count, u8 *buf); +int wcd9xxx_bulk_write(struct wcd9xxx *wcd9xxx, unsigned short reg, + int count, u8 *buf); +int wcd9xxx_irq_init(struct wcd9xxx *wcd9xxx); +void wcd9xxx_irq_exit(struct wcd9xxx *wcd9xxx); +int wcd9xxx_get_logical_addresses(u8 *pgd_la, u8 *inf_la); +int wcd9xxx_get_intf_type(void); + +bool wcd9xxx_lock_sleep(struct wcd9xxx *wcd9xxx); +void wcd9xxx_unlock_sleep(struct wcd9xxx *wcd9xxx); +enum wcd9xxx_pm_state wcd9xxx_pm_cmpxchg(struct wcd9xxx *wcd9xxx, + enum wcd9xxx_pm_state o, + enum wcd9xxx_pm_state n); + +static inline int wcd9xxx_request_irq(struct wcd9xxx *wcd9xxx, int irq, + irq_handler_t handler, const char *name, + void *data) +{ + if (!wcd9xxx->irq_base) + return -EINVAL; + return request_threaded_irq(wcd9xxx->irq_base + irq, NULL, handler, + IRQF_TRIGGER_RISING, name, + data); +} +static inline void wcd9xxx_free_irq(struct wcd9xxx *wcd9xxx, + int irq, void *data) +{ + if (!wcd9xxx->irq_base) + return; + free_irq(wcd9xxx->irq_base + irq, data); +} +static inline void wcd9xxx_enable_irq(struct wcd9xxx *wcd9xxx, int irq) +{ + if (!wcd9xxx->irq_base) + return; + enable_irq(wcd9xxx->irq_base + irq); +} +static inline void wcd9xxx_disable_irq(struct wcd9xxx *wcd9xxx, int irq) +{ + if (!wcd9xxx->irq_base) + return; + disable_irq_nosync(wcd9xxx->irq_base + irq); +} +static inline void wcd9xxx_disable_irq_sync(struct wcd9xxx *wcd9xxx, int irq) +{ + if (!wcd9xxx->irq_base) + return; + disable_irq(wcd9xxx->irq_base + irq); +} + +#endif diff --git a/original-kernel-headers/linux/mfd/wcd9xxx/pdata.h b/original-kernel-headers/linux/mfd/wcd9xxx/pdata.h new file mode 100644 index 0000000..5055a7f --- /dev/null +++ b/original-kernel-headers/linux/mfd/wcd9xxx/pdata.h @@ -0,0 +1,163 @@ +/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MFD_TABLA_PDATA_H__ + +#define __MFD_TABLA_PDATA_H__ + +#include <linux/slimbus/slimbus.h> + +#define MICBIAS_EXT_BYP_CAP 0x00 +#define MICBIAS_NO_EXT_BYP_CAP 0x01 + +#define SITAR_LDOH_1P95_V 0x0 +#define SITAR_LDOH_2P35_V 0x1 +#define SITAR_LDOH_2P75_V 0x2 +#define SITAR_LDOH_2P85_V 0x3 + +#define SITAR_CFILT1_SEL 0x0 +#define SITAR_CFILT2_SEL 0x1 +#define SITAR_CFILT3_SEL 0x2 + +#define TABLA_LDOH_1P95_V 0x0 +#define TABLA_LDOH_2P35_V 0x1 +#define TABLA_LDOH_2P75_V 0x2 +#define TABLA_LDOH_2P85_V 0x3 + +#define TABLA_CFILT1_SEL 0x0 +#define TABLA_CFILT2_SEL 0x1 +#define TABLA_CFILT3_SEL 0x2 + +#define TAIKO_CFILT1_SEL 0x0 +#define TAIKO_CFILT2_SEL 0x1 +#define TAIKO_CFILT3_SEL 0x2 + +#define TAIKO_LDOH_1P95_V 0x0 +#define TAIKO_LDOH_2P35_V 0x1 +#define TAIKO_LDOH_2P75_V 0x2 +#define TAIKO_LDOH_2P85_V 0x3 + + +#define MAX_AMIC_CHANNEL 7 + +#define TABLA_OCP_300_MA 0x0 +#define TABLA_OCP_350_MA 0x2 +#define TABLA_OCP_365_MA 0x3 +#define TABLA_OCP_150_MA 0x4 +#define TABLA_OCP_190_MA 0x6 +#define TABLA_OCP_220_MA 0x7 + +#define TABLA_DCYCLE_255 0x0 +#define TABLA_DCYCLE_511 0x1 +#define TABLA_DCYCLE_767 0x2 +#define TABLA_DCYCLE_1023 0x3 +#define TABLA_DCYCLE_1279 0x4 +#define TABLA_DCYCLE_1535 0x5 +#define TABLA_DCYCLE_1791 0x6 +#define TABLA_DCYCLE_2047 0x7 +#define TABLA_DCYCLE_2303 0x8 +#define TABLA_DCYCLE_2559 0x9 +#define TABLA_DCYCLE_2815 0xA +#define TABLA_DCYCLE_3071 0xB +#define TABLA_DCYCLE_3327 0xC +#define TABLA_DCYCLE_3583 0xD +#define TABLA_DCYCLE_3839 0xE +#define TABLA_DCYCLE_4095 0xF + +struct wcd9xxx_amic { + /*legacy mode, txfe_enable and txfe_buff take 7 input + * each bit represent the channel / TXFE number + * and numbered as below + * bit 0 = channel 1 / TXFE1_ENABLE / TXFE1_BUFF + * bit 1 = channel 2 / TXFE2_ENABLE / TXFE2_BUFF + * ... + * bit 7 = channel 7 / TXFE7_ENABLE / TXFE7_BUFF + */ + u8 legacy_mode:MAX_AMIC_CHANNEL; + u8 txfe_enable:MAX_AMIC_CHANNEL; + u8 txfe_buff:MAX_AMIC_CHANNEL; + u8 use_pdata:MAX_AMIC_CHANNEL; +}; + +/* Each micbias can be assigned to one of three cfilters + * Vbatt_min >= .15V + ldoh_v + * ldoh_v >= .15v + cfiltx_mv + * If ldoh_v = 1.95 160 mv < cfiltx_mv < 1800 mv + * If ldoh_v = 2.35 200 mv < cfiltx_mv < 2200 mv + * If ldoh_v = 2.75 240 mv < cfiltx_mv < 2600 mv + * If ldoh_v = 2.85 250 mv < cfiltx_mv < 2700 mv + */ + +struct wcd9xxx_micbias_setting { + u8 ldoh_v; + u32 cfilt1_mv; /* in mv */ + u32 cfilt2_mv; /* in mv */ + u32 cfilt3_mv; /* in mv */ + /* Different WCD9xxx series codecs may not + * have 4 mic biases. If a codec has fewer + * mic biases, some of these properties will + * not be used. + */ + u8 bias1_cfilt_sel; + u8 bias2_cfilt_sel; + u8 bias3_cfilt_sel; + u8 bias4_cfilt_sel; + u8 bias1_cap_mode; + u8 bias2_cap_mode; + u8 bias3_cap_mode; + u8 bias4_cap_mode; +}; + +struct wcd9xxx_ocp_setting { + unsigned int use_pdata:1; /* 0 - use sys default as recommended */ + unsigned int num_attempts:4; /* up to 15 attempts */ + unsigned int run_time:4; /* in duty cycle */ + unsigned int wait_time:4; /* in duty cycle */ + unsigned int hph_ocp_limit:3; /* Headphone OCP current limit */ +}; + +#define MAX_REGULATOR 7 +/* + * format : TABLA_<POWER_SUPPLY_PIN_NAME>_CUR_MAX + * + * <POWER_SUPPLY_PIN_NAME> from Tabla objective spec +*/ + +#define WCD9XXX_CDC_VDDA_CP_CUR_MAX 500000 +#define WCD9XXX_CDC_VDDA_RX_CUR_MAX 20000 +#define WCD9XXX_CDC_VDDA_TX_CUR_MAX 20000 +#define WCD9XXX_VDDIO_CDC_CUR_MAX 5000 + +#define WCD9XXX_VDDD_CDC_D_CUR_MAX 5000 +#define WCD9XXX_VDDD_CDC_A_CUR_MAX 5000 + +struct wcd9xxx_regulator { + const char *name; + int min_uV; + int max_uV; + int optimum_uA; + struct regulator *regulator; +}; + +struct wcd9xxx_pdata { + int irq; + int irq_base; + int num_irqs; + int reset_gpio; + struct wcd9xxx_amic amic_settings; + struct slim_device slimbus_slave_device; + struct wcd9xxx_micbias_setting micbias; + struct wcd9xxx_ocp_setting ocp; + struct wcd9xxx_regulator regulator[MAX_REGULATOR]; +}; + +#endif diff --git a/original-kernel-headers/linux/mfd/wcd9xxx/wcd9304_registers.h b/original-kernel-headers/linux/mfd/wcd9xxx/wcd9304_registers.h new file mode 100644 index 0000000..b8b42fa --- /dev/null +++ b/original-kernel-headers/linux/mfd/wcd9xxx/wcd9304_registers.h @@ -0,0 +1,807 @@ +/* Copyright (c) 2012, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SITAR_CODEC_DIGITAL_H +#define SITAR_CODEC_DIGITAL_H + +#define SITAR_A_PIN_CTL_OE0 (0x10) +#define SITAR_A_PIN_CTL_OE0__POR (0x00000000) +#define SITAR_A_PIN_CTL_OE1 (0x11) +#define SITAR_A_PIN_CTL_OE1__POR (0x00000000) +#define SITAR_A_PIN_CTL_DATA0 (0x12) +#define SITAR_A_PIN_CTL_DATA0__POR (0x00000000) +#define SITAR_A_PIN_CTL_DATA1 (0x13) +#define SITAR_A_PIN_CTL_DATA1__POR (0x00000000) +#define SITAR_A_HDRIVE_GENERIC (0x18) +#define SITAR_A_HDRIVE_GENERIC__POR (0x00000000) +#define SITAR_A_HDRIVE_OVERRIDE (0x19) +#define SITAR_A_HDRIVE_OVERRIDE__POR (0x00000008) +#define SITAR_A_ANA_CSR_WAIT_STATE (0x20) +#define SITAR_A_ANA_CSR_WAIT_STATE__POR (0x00000044) +#define SITAR_A_PROCESS_MONITOR_CTL0 (0x40) +#define SITAR_A_PROCESS_MONITOR_CTL0__POR (0x00000080) +#define SITAR_A_PROCESS_MONITOR_CTL1 (0x41) +#define SITAR_A_PROCESS_MONITOR_CTL1__POR (0x00000000) +#define SITAR_A_PROCESS_MONITOR_CTL2 (0x42) +#define SITAR_A_PROCESS_MONITOR_CTL2__POR (0x00000000) +#define SITAR_A_PROCESS_MONITOR_CTL3 (0x43) +#define SITAR_A_PROCESS_MONITOR_CTL3__POR (0x00000001) +#define SITAR_A_QFUSE_CTL (0x48) +#define SITAR_A_QFUSE_CTL__POR (0x00000000) +#define SITAR_A_QFUSE_STATUS (0x49) +#define SITAR_A_QFUSE_STATUS__POR (0x00000000) +#define SITAR_A_QFUSE_DATA_OUT0 (0x4A) +#define SITAR_A_QFUSE_DATA_OUT0__POR (0x00000000) +#define SITAR_A_QFUSE_DATA_OUT1 (0x4B) +#define SITAR_A_QFUSE_DATA_OUT1__POR (0x00000000) +#define SITAR_A_QFUSE_DATA_OUT2 (0x4C) +#define SITAR_A_QFUSE_DATA_OUT2__POR (0x00000000) +#define SITAR_A_QFUSE_DATA_OUT3 (0x4D) +#define SITAR_A_QFUSE_DATA_OUT3__POR (0x00000000) +#define SITAR_A_QFUSE_DATA_OUT4 (0x4E) +#define SITAR_A_QFUSE_DATA_OUT4__POR (0x00000000) +#define SITAR_A_QFUSE_DATA_OUT5 (0x4F) +#define SITAR_A_QFUSE_DATA_OUT5__POR (0x00000000) +#define SITAR_A_QFUSE_DATA_OUT6 (0x50) +#define SITAR_A_QFUSE_DATA_OUT6__POR (0x00000000) +#define SITAR_A_QFUSE_DATA_OUT7 (0x51) +#define SITAR_A_QFUSE_DATA_OUT7__POR (0x00000000) +#define SITAR_A_CDC_CTL (0x80) +#define SITAR_A_CDC_CTL__POR (0x00000000) +#define SITAR_A_LEAKAGE_CTL (0x88) +#define SITAR_A_LEAKAGE_CTL__POR (0x00000004) +#define SITAR_A_INTR_MODE (0x90) +#define SITAR_A_INTR_MODE__POR (0x00000000) +#define SITAR_A_INTR_MASK0 (0x94) +#define SITAR_A_INTR_MASK0__POR (0x000000ff) +#define SITAR_A_INTR_MASK1 (0x95) +#define SITAR_A_INTR_MASK1__POR (0x000000ff) +#define SITAR_A_INTR_MASK2 (0x96) +#define SITAR_A_INTR_MASK2__POR (0x000000ff) +#define SITAR_A_INTR_STATUS0 (0x98) +#define SITAR_A_INTR_STATUS0__POR (0x00000000) +#define SITAR_A_INTR_STATUS1 (0x99) +#define SITAR_A_INTR_STATUS1__POR (0x00000000) +#define SITAR_A_INTR_STATUS2 (0x9A) +#define SITAR_A_INTR_STATUS2__POR (0x00000000) +#define SITAR_A_INTR_CLEAR0 (0x9C) +#define SITAR_A_INTR_CLEAR0__POR (0x00000000) +#define SITAR_A_INTR_CLEAR1 (0x9D) +#define SITAR_A_INTR_CLEAR1__POR (0x00000000) +#define SITAR_A_INTR_CLEAR2 (0x9E) +#define SITAR_A_INTR_CLEAR2__POR (0x00000000) +#define SITAR_A_INTR_LEVEL0 (0xA0) +#define SITAR_A_INTR_LEVEL0__POR (0x00000001) +#define SITAR_A_INTR_LEVEL1 (0xA1) +#define SITAR_A_INTR_LEVEL1__POR (0x00000000) +#define SITAR_A_INTR_LEVEL2 (0xA2) +#define SITAR_A_INTR_LEVEL2__POR (0x00000000) +#define SITAR_A_INTR_TEST0 (0xA4) +#define SITAR_A_INTR_TEST0__POR (0x00000000) +#define SITAR_A_INTR_TEST1 (0xA5) +#define SITAR_A_INTR_TEST1__POR (0x00000000) +#define SITAR_A_INTR_TEST2 (0xA6) +#define SITAR_A_INTR_TEST2__POR (0x00000000) +#define SITAR_A_INTR_SET0 (0xA8) +#define SITAR_A_INTR_SET0__POR (0x00000000) +#define SITAR_A_INTR_SET1 (0xA9) +#define SITAR_A_INTR_SET1__POR (0x00000000) +#define SITAR_A_INTR_SET2 (0xAA) +#define SITAR_A_INTR_SET2__POR (0x00000000) +#define SITAR_A_CDC_TX_I2S_SCK_MODE (0xC0) +#define SITAR_A_CDC_TX_I2S_SCK_MODE__POR (0x00000000) +#define SITAR_A_CDC_TX_I2S_WS_MODE (0xC1) +#define SITAR_A_CDC_TX_I2S_WS_MODE__POR (0x00000000) +#define SITAR_A_CDC_DMIC_DATA0_MODE (0xC4) +#define SITAR_A_CDC_DMIC_DATA0_MODE__POR (0x00000000) +#define SITAR_A_CDC_DMIC_CLK0_MODE (0xC5) +#define SITAR_A_CDC_DMIC_CLK0_MODE__POR (0x00000000) +#define SITAR_A_CDC_DMIC_DATA1_MODE (0xC6) +#define SITAR_A_CDC_DMIC_DATA1_MODE__POR (0x00000000) +#define SITAR_A_CDC_DMIC_CLK1_MODE (0xC7) +#define SITAR_A_CDC_DMIC_CLK1_MODE__POR (0x00000000) +#define SITAR_A_CDC_TX_I2S_SD0_MODE (0xC8) +#define SITAR_A_CDC_TX_I2S_SD0_MODE__POR (0x00000000) +#define SITAR_A_CDC_INTR_MODE (0xC9) +#define SITAR_A_CDC_INTR_MODE__POR (0x00000000) +#define SITAR_A_CDC_RX_I2S_SD0_MODE (0xCA) +#define SITAR_A_CDC_RX_I2S_SD0_MODE__POR (0x00000000) +#define SITAR_A_CDC_RX_I2S_SD1_MODE (0xCB) +#define SITAR_A_CDC_RX_I2S_SD1_MODE__POR (0x00000000) +#define SITAR_A_BIAS_REF_CTL (0x100) +#define SITAR_A_BIAS_REF_CTL__POR (0x0000001c) +#define SITAR_A_BIAS_CENTRAL_BG_CTL (0x101) +#define SITAR_A_BIAS_CENTRAL_BG_CTL__POR (0x00000050) +#define SITAR_A_BIAS_PRECHRG_CTL (0x102) +#define SITAR_A_BIAS_PRECHRG_CTL__POR (0x00000007) +#define SITAR_A_BIAS_CURR_CTL_1 (0x103) +#define SITAR_A_BIAS_CURR_CTL_1__POR (0x00000052) +#define SITAR_A_BIAS_CURR_CTL_2 (0x104) +#define SITAR_A_BIAS_CURR_CTL_2__POR (0x00000000) +#define SITAR_A_BIAS_OSC_BG_CTL (0x105) +#define SITAR_A_BIAS_OSC_BG_CTL__POR (0x00000016) +#define SITAR_A_CLK_BUFF_EN1 (0x108) +#define SITAR_A_CLK_BUFF_EN1__POR (0x00000004) +#define SITAR_A_CLK_BUFF_EN2 (0x109) +#define SITAR_A_CLK_BUFF_EN2__POR (0x00000002) +#define SITAR_A_LDO_H_MODE_1 (0x110) +#define SITAR_A_LDO_H_MODE_1__POR (0x00000065) +#define SITAR_A_LDO_H_MODE_2 (0x111) +#define SITAR_A_LDO_H_MODE_2__POR (0x000000a8) +#define SITAR_A_LDO_H_LOOP_CTL (0x112) +#define SITAR_A_LDO_H_LOOP_CTL__POR (0x0000006b) +#define SITAR_A_LDO_H_COMP_1 (0x113) +#define SITAR_A_LDO_H_COMP_1__POR (0x00000084) +#define SITAR_A_LDO_H_COMP_2 (0x114) +#define SITAR_A_LDO_H_COMP_2__POR (0x000000e0) +#define SITAR_A_LDO_H_BIAS_1 (0x115) +#define SITAR_A_LDO_H_BIAS_1__POR (0x0000006d) +#define SITAR_A_LDO_H_BIAS_2 (0x116) +#define SITAR_A_LDO_H_BIAS_2__POR (0x000000a5) +#define SITAR_A_LDO_H_BIAS_3 (0x117) +#define SITAR_A_LDO_H_BIAS_3__POR (0x00000060) +#define SITAR_A_MICB_CFILT_1_CTL (0x128) +#define SITAR_A_MICB_CFILT_1_CTL__POR (0x00000040) +#define SITAR_A_MICB_CFILT_1_VAL (0x129) +#define SITAR_A_MICB_CFILT_1_VAL__POR (0x00000080) +#define SITAR_A_MICB_CFILT_1_PRECHRG (0x12A) +#define SITAR_A_MICB_CFILT_1_PRECHRG__POR (0x00000038) +#define SITAR_A_MICB_1_CTL (0x12B) +#define SITAR_A_MICB_1_CTL__POR (0x00000016) +#define SITAR_A_MICB_1_INT_RBIAS (0x12C) +#define SITAR_A_MICB_1_INT_RBIAS__POR (0x00000024) +#define SITAR_A_MICB_1_MBHC (0x12D) +#define SITAR_A_MICB_1_MBHC__POR (0x00000001) +#define SITAR_A_MICB_CFILT_2_CTL (0x12E) +#define SITAR_A_MICB_CFILT_2_CTL__POR (0x00000040) +#define SITAR_A_MICB_CFILT_2_VAL (0x12F) +#define SITAR_A_MICB_CFILT_2_VAL__POR (0x00000080) +#define SITAR_A_MICB_CFILT_2_PRECHRG (0x130) +#define SITAR_A_MICB_CFILT_2_PRECHRG__POR (0x00000038) +#define SITAR_A_MICB_2_CTL (0x131) +#define SITAR_A_MICB_2_CTL__POR (0x00000016) +#define SITAR_A_MICB_2_INT_RBIAS (0x132) +#define SITAR_A_MICB_2_INT_RBIAS__POR (0x00000024) +#define SITAR_A_MICB_2_MBHC (0x133) +#define SITAR_A_MICB_2_MBHC__POR (0x00000002) +#define SITAR_A_TX_COM_BIAS (0x14C) +#define SITAR_A_TX_COM_BIAS__POR (0x000000e0) +#define SITAR_A_MBHC_SCALING_MUX_1 (0x14E) +#define SITAR_A_MBHC_SCALING_MUX_1__POR (0x00000000) +#define SITAR_A_MBHC_SCALING_MUX_2 (0x14F) +#define SITAR_A_MBHC_SCALING_MUX_2__POR (0x00000080) +#define SITAR_A_TX_SUP_SWITCH_CTRL_1 (0x151) +#define SITAR_A_TX_SUP_SWITCH_CTRL_1__POR (0x00000000) +#define SITAR_A_TX_SUP_SWITCH_CTRL_2 (0x152) +#define SITAR_A_TX_SUP_SWITCH_CTRL_2__POR (0x00000080) +#define SITAR_A_TX_1_2_EN (0x153) +#define SITAR_A_TX_1_2_EN__POR (0x00000000) +#define SITAR_A_TX_1_2_TEST_EN (0x154) +#define SITAR_A_TX_1_2_TEST_EN__POR (0x000000cc) +#define SITAR_A_TX_1_2_ADC_CH1 (0x155) +#define SITAR_A_TX_1_2_ADC_CH1__POR (0x00000044) +#define SITAR_A_TX_1_2_ADC_CH2 (0x156) +#define SITAR_A_TX_1_2_ADC_CH2__POR (0x00000044) +#define SITAR_A_TX_1_2_ATEST_REFCTRL (0x157) +#define SITAR_A_TX_1_2_ATEST_REFCTRL__POR (0x00000000) +#define SITAR_A_TX_1_2_TEST_CTL (0x158) +#define SITAR_A_TX_1_2_TEST_CTL__POR (0x00000038) +#define SITAR_A_TX_1_2_TEST_BLOCK_EN (0x159) +#define SITAR_A_TX_1_2_TEST_BLOCK_EN__POR (0x000000fc) +#define SITAR_A_TX_1_2_TXFE_CLKDIV (0x15A) +#define SITAR_A_TX_1_2_TXFE_CLKDIV__POR (0x000000ee) +#define SITAR_A_TX_1_2_SAR_ERR_CH1 (0x15B) +#define SITAR_A_TX_1_2_SAR_ERR_CH1__POR (0x00000000) +#define SITAR_A_TX_1_2_SAR_ERR_CH2 (0x15C) +#define SITAR_A_TX_1_2_SAR_ERR_CH2__POR (0x00000000) +#define SITAR_A_TX_3_EN (0x15D) +#define SITAR_A_TX_3_EN__POR (0x00000000) +#define SITAR_A_TX_3_TEST_EN (0x15E) +#define SITAR_A_TX_3_TEST_EN__POR (0x000000cc) +#define SITAR_A_TX_3_ADC (0x15F) +#define SITAR_A_TX_3_ADC__POR (0x00000044) +#define SITAR_A_TX_3_MBHC_ATEST_REFCTRL (0x161) +#define SITAR_A_TX_3_MBHC_ATEST_REFCTRL__POR (0x00000000) +#define SITAR_A_TX_3_TEST_CTL (0x162) +#define SITAR_A_TX_3_TEST_CTL__POR (0x00000038) +#define SITAR_A_TX_3_TEST_BLOCK_EN (0x163) +#define SITAR_A_TX_3_TEST_BLOCK_EN__POR (0x000000fc) +#define SITAR_A_TX_3_TXFE_CKDIV (0x164) +#define SITAR_A_TX_3_TXFE_CKDIV__POR (0x000000ee) +#define SITAR_A_TX_3_SAR_ERR (0x165) +#define SITAR_A_TX_3_SAR_ERR__POR (0x00000000) +#define SITAR_A_TX_4_MBHC_EN (0x171) +#define SITAR_A_TX_4_MBHC_EN__POR (0x0000000c) +#define SITAR_A_TX_4_MBHC_ADC (0x173) +#define SITAR_A_TX_4_MBHC_ADC__POR (0x00000044) +#define SITAR_A_TX_4_MBHC_TEST_CTL (0x174) +#define SITAR_A_TX_4_MBHC_TEST_CTL__POR (0x00000038) +#define SITAR_A_TX_4_MBHC_SAR_ERR (0x175) +#define SITAR_A_TX_4_MBHC_SAR_ERR__POR (0x00000000) +#define SITAR_A_TX_4_TXFE_CLKDIV (0x176) +#define SITAR_A_TX_4_TXFE_CLKDIV__POR (0x0000001c) +#define SITAR_A_AUX_COM_CTL (0x180) +#define SITAR_A_AUX_COM_CTL__POR (0x00000034) +#define SITAR_A_AUX_COM_ATEST (0x181) +#define SITAR_A_AUX_COM_ATEST__POR (0x00000000) +#define SITAR_A_AUX_L_EN (0x182) +#define SITAR_A_AUX_L_EN__POR (0x00000000) +#define SITAR_A_AUX_L_GAIN (0x183) +#define SITAR_A_AUX_L_GAIN__POR (0x0000001f) +#define SITAR_A_AUX_L_PA_CONN (0x184) +#define SITAR_A_AUX_L_PA_CONN__POR (0x00000000) +#define SITAR_A_AUX_L_PA_CONN_INV (0x185) +#define SITAR_A_AUX_L_PA_CONN_INV__POR (0x00000000) +#define SITAR_A_AUX_R_EN (0x186) +#define SITAR_A_AUX_R_EN__POR (0x00000000) +#define SITAR_A_AUX_R_GAIN (0x187) +#define SITAR_A_AUX_R_GAIN__POR (0x0000001f) +#define SITAR_A_AUX_R_PA_CONN (0x188) +#define SITAR_A_AUX_R_PA_CONN__POR (0x00000000) +#define SITAR_A_AUX_R_PA_CONN_INV (0x189) +#define SITAR_A_AUX_R_PA_CONN_INV__POR (0x00000000) +#define SITAR_A_CP_EN (0x192) +#define SITAR_A_CP_EN__POR (0x000000e6) +#define SITAR_A_CP_CLK (0x193) +#define SITAR_A_CP_CLK__POR (0x00000029) +#define SITAR_A_CP_STATIC (0x194) +#define SITAR_A_CP_STATIC__POR (0x00000010) +#define SITAR_A_CP_DCC1 (0x195) +#define SITAR_A_CP_DCC1__POR (0x00000052) +#define SITAR_A_CP_DCC3 (0x196) +#define SITAR_A_CP_DCC3__POR (0x00000001) +#define SITAR_A_CP_ATEST (0x197) +#define SITAR_A_CP_ATEST__POR (0x00000000) +#define SITAR_A_CP_DTEST (0x198) +#define SITAR_A_CP_DTEST__POR (0x00000000) +#define SITAR_A_RX_COM_TIMER_DIV (0x19E) +#define SITAR_A_RX_COM_TIMER_DIV__POR (0x000000e8) +#define SITAR_A_RX_COM_OCP_CTL (0x19F) +#define SITAR_A_RX_COM_OCP_CTL__POR (0x0000001f) +#define SITAR_A_RX_COM_OCP_COUNT (0x1A0) +#define SITAR_A_RX_COM_OCP_COUNT__POR (0x00000077) +#define SITAR_A_RX_COM_DAC_CTL (0x1A1) +#define SITAR_A_RX_COM_DAC_CTL__POR (0x00000000) +#define SITAR_A_RX_COM_BIAS (0x1A2) +#define SITAR_A_RX_COM_BIAS__POR (0x00000000) +#define SITAR_A_RX_HPH_BIAS_PA (0x1A6) +#define SITAR_A_RX_HPH_BIAS_PA__POR (0x00000057) +#define SITAR_A_RX_HPH_BIAS_LDO (0x1A7) +#define SITAR_A_RX_HPH_BIAS_LDO__POR (0x00000056) +#define SITAR_A_RX_HPH_BIAS_CNP (0x1A8) +#define SITAR_A_RX_HPH_BIAS_CNP__POR (0x0000008a) +#define SITAR_A_RX_HPH_BIAS_WG (0x1A9) +#define SITAR_A_RX_HPH_BIAS_WG__POR (0x00000060) +#define SITAR_A_RX_HPH_OCP_CTL (0x1AA) +#define SITAR_A_RX_HPH_OCP_CTL__POR (0x000000e8) +#define SITAR_A_RX_HPH_CNP_EN (0x1AB) +#define SITAR_A_RX_HPH_CNP_EN__POR (0x00000080) +#define SITAR_A_RX_HPH_CNP_WG_CTL (0x1AC) +#define SITAR_A_RX_HPH_CNP_WG_CTL__POR (0x000000dc) +#define SITAR_A_RX_HPH_CNP_WG_TIME (0x1AD) +#define SITAR_A_RX_HPH_CNP_WG_TIME__POR (0x00000028) +#define SITAR_A_RX_HPH_L_GAIN (0x1AE) +#define SITAR_A_RX_HPH_L_GAIN__POR (0x00000000) +#define SITAR_A_RX_HPH_L_TEST (0x1AF) +#define SITAR_A_RX_HPH_L_TEST__POR (0x00000001) +#define SITAR_A_RX_HPH_L_PA_CTL (0x1B0) +#define SITAR_A_RX_HPH_L_PA_CTL__POR (0x00000040) +#define SITAR_A_RX_HPH_L_DAC_CTL (0x1B1) +#define SITAR_A_RX_HPH_L_DAC_CTL__POR (0x00000000) +#define SITAR_A_RX_HPH_L_ATEST (0x1B2) +#define SITAR_A_RX_HPH_L_ATEST__POR (0x00000000) +#define SITAR_A_RX_HPH_L_STATUS (0x1B3) +#define SITAR_A_RX_HPH_L_STATUS__POR (0x00000004) +#define SITAR_A_RX_HPH_R_GAIN (0x1B4) +#define SITAR_A_RX_HPH_R_GAIN__POR (0x00000000) +#define SITAR_A_RX_HPH_R_TEST (0x1B5) +#define SITAR_A_RX_HPH_R_TEST__POR (0x00000001) +#define SITAR_A_RX_HPH_R_PA_CTL (0x1B6) +#define SITAR_A_RX_HPH_R_PA_CTL__POR (0x00000040) +#define SITAR_A_RX_HPH_R_DAC_CTL (0x1B7) +#define SITAR_A_RX_HPH_R_DAC_CTL__POR (0x00000000) +#define SITAR_A_RX_HPH_R_ATEST (0x1B8) +#define SITAR_A_RX_HPH_R_ATEST__POR (0x00000000) +#define SITAR_A_RX_HPH_R_STATUS (0x1B9) +#define SITAR_A_RX_HPH_R_STATUS__POR (0x00000004) +#define SITAR_A_RX_EAR_BIAS_PA (0x1BA) +#define SITAR_A_RX_EAR_BIAS_PA__POR (0x000000a6) +#define SITAR_A_RX_EAR_BIAS_CMBUFF (0x1BB) +#define SITAR_A_RX_EAR_BIAS_CMBUFF__POR (0x000000a0) +#define SITAR_A_RX_EAR_EN (0x1BC) +#define SITAR_A_RX_EAR_EN__POR (0x00000000) +#define SITAR_A_RX_EAR_GAIN (0x1BD) +#define SITAR_A_RX_EAR_GAIN__POR (0x00000002) +#define SITAR_A_RX_EAR_CMBUFF (0x1BE) +#define SITAR_A_RX_EAR_CMBUFF__POR (0x00000004) +#define SITAR_A_RX_EAR_ICTL (0x1BF) +#define SITAR_A_RX_EAR_ICTL__POR (0x00000040) +#define SITAR_A_RX_EAR_CCOMP (0x1C0) +#define SITAR_A_RX_EAR_CCOMP__POR (0x00000008) +#define SITAR_A_RX_EAR_VCM (0x1C1) +#define SITAR_A_RX_EAR_VCM__POR (0x00000003) +#define SITAR_A_RX_EAR_CNP (0x1C2) +#define SITAR_A_RX_EAR_CNP__POR (0x000000f2) +#define SITAR_A_RX_EAR_ATEST (0x1C3) +#define SITAR_A_RX_EAR_ATEST__POR (0x00000000) +#define SITAR_A_RX_EAR_STATUS (0x1C5) +#define SITAR_A_RX_EAR_STATUS__POR (0x00000004) +#define SITAR_A_RX_LINE_BIAS_PA (0x1C6) +#define SITAR_A_RX_LINE_BIAS_PA__POR (0x000000aa) +#define SITAR_A_RX_LINE_BIAS_LDO (0x1C7) +#define SITAR_A_RX_LINE_BIAS_LDO__POR (0x00000086) +#define SITAR_A_RX_LINE_BIAS_CNP1 (0x1C8) +#define SITAR_A_RX_LINE_BIAS_CNP1__POR (0x00000060) +#define SITAR_A_RX_LINE_COM (0x1C9) +#define SITAR_A_RX_LINE_COM__POR (0x00000000) +#define SITAR_A_RX_LINE_CNP_EN (0x1CA) +#define SITAR_A_RX_LINE_CNP_EN__POR (0x00000080) +#define SITAR_A_RX_LINE_CNP_WG_CTL (0x1CB) +#define SITAR_A_RX_LINE_CNP_WG_CTL__POR (0x000000dc) +#define SITAR_A_RX_LINE_CNP_WG_TIME (0x1CC) +#define SITAR_A_RX_LINE_CNP_WG_TIME__POR (0x00000028) +#define SITAR_A_RX_LINE_1_GAIN (0x1CD) +#define SITAR_A_RX_LINE_1_GAIN__POR (0x00000000) +#define SITAR_A_RX_LINE_1_TEST (0x1CE) +#define SITAR_A_RX_LINE_1_TEST__POR (0x00000001) +#define SITAR_A_RX_LINE_1_DAC_CTL (0x1CF) +#define SITAR_A_RX_LINE_1_DAC_CTL__POR (0x00000000) +#define SITAR_A_RX_LINE_1_STATUS (0x1D0) +#define SITAR_A_RX_LINE_1_STATUS__POR (0x00000004) +#define SITAR_A_RX_LINE_2_GAIN (0x1D1) +#define SITAR_A_RX_LINE_2_GAIN__POR (0x00000000) +#define SITAR_A_RX_LINE_2_TEST (0x1D2) +#define SITAR_A_RX_LINE_2_TEST__POR (0x00000001) +#define SITAR_A_RX_LINE_2_DAC_CTL (0x1D3) +#define SITAR_A_RX_LINE_2_DAC_CTL__POR (0x00000000) +#define SITAR_A_RX_LINE_2_STATUS (0x1D4) +#define SITAR_A_RX_LINE_2_STATUS__POR (0x00000004) +#define SITAR_A_RX_LINE_BIAS_CNP2 (0x1E1) +#define SITAR_A_RX_LINE_BIAS_CNP2__POR (0x0000008a) +#define SITAR_A_RX_LINE_OCP_CTL (0x1E2) +#define SITAR_A_RX_LINE_OCP_CTL__POR (0x000000e8) +#define SITAR_A_RX_LINE_1_PA_CTL (0x1E3) +#define SITAR_A_RX_LINE_1_PA_CTL__POR (0x00000040) +#define SITAR_A_RX_LINE_2_PA_CTL (0x1E4) +#define SITAR_A_RX_LINE_2_PA_CTL__POR (0x00000040) +#define SITAR_A_RX_LINE_CNP_DBG (0x1EC) +#define SITAR_A_RX_LINE_CNP_DBG__POR (0x00000000) +#define SITAR_A_MBHC_HPH (0x1ED) +#define SITAR_A_MBHC_HPH__POR (0x00000048) +#define SITAR_A_RC_OSC_FREQ (0x1F7) +#define SITAR_A_RC_OSC_FREQ__POR (0x00000046) +#define SITAR_A_RC_OSC_TEST (0x1F8) +#define SITAR_A_RC_OSC_TEST__POR (0x0000000a) +#define SITAR_A_RC_OSC_STATUS (0x1F9) +#define SITAR_A_RC_OSC_STATUS__POR (0x0000001c) +#define SITAR_A_RC_OSC_TUNER (0x1FA) +#define SITAR_A_RC_OSC_TUNER__POR (0x00000000) +#define SITAR_A_CDC_ANC1_CTL (0x200) +#define SITAR_A_CDC_ANC1_CTL__POR (0x00000000) +#define SITAR_A_CDC_ANC1_SHIFT (0x201) +#define SITAR_A_CDC_ANC1_SHIFT__POR (0x00000000) +#define SITAR_A_CDC_ANC1_IIR_B1_CTL (0x202) +#define SITAR_A_CDC_ANC1_IIR_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_ANC1_IIR_B2_CTL (0x203) +#define SITAR_A_CDC_ANC1_IIR_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_ANC1_IIR_B3_CTL (0x204) +#define SITAR_A_CDC_ANC1_IIR_B3_CTL__POR (0x00000000) +#define SITAR_A_CDC_ANC1_IIR_B4_CTL (0x205) +#define SITAR_A_CDC_ANC1_IIR_B4_CTL__POR (0x00000000) +#define SITAR_A_CDC_ANC1_LPF_B1_CTL (0x206) +#define SITAR_A_CDC_ANC1_LPF_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_ANC1_LPF_B2_CTL (0x207) +#define SITAR_A_CDC_ANC1_LPF_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_ANC1_LPF_B3_CTL (0x208) +#define SITAR_A_CDC_ANC1_LPF_B3_CTL__POR (0x00000000) +#define SITAR_A_CDC_ANC1_SPARE (0x209) +#define SITAR_A_CDC_ANC1_SPARE__POR (0x00000000) +#define SITAR_A_CDC_ANC1_SMLPF_CTL (0x20A) +#define SITAR_A_CDC_ANC1_SMLPF_CTL__POR (0x00000000) +#define SITAR_A_CDC_ANC1_DCFLT_CTL (0x20B) +#define SITAR_A_CDC_ANC1_DCFLT_CTL__POR (0x00000000) +#define SITAR_A_CDC_TX1_VOL_CTL_TIMER (0x220) +#define SITAR_A_CDC_TX1_VOL_CTL_TIMER__POR (0x00000000) +#define SITAR_A_CDC_TX1_VOL_CTL_GAIN (0x221) +#define SITAR_A_CDC_TX1_VOL_CTL_GAIN__POR (0x00000000) +#define SITAR_A_CDC_TX2_VOL_CTL_GAIN (0x229) +#define SITAR_A_CDC_TX2_VOL_CTL_GAIN__POR (0x00000000) +#define SITAR_A_CDC_TX3_VOL_CTL_GAIN (0x231) +#define SITAR_A_CDC_TX3_VOL_CTL_GAIN__POR (0x00000000) +#define SITAR_A_CDC_TX4_VOL_CTL_GAIN (0x239) +#define SITAR_A_CDC_TX4_VOL_CTL_GAIN__POR (0x00000000) +#define SITAR_A_CDC_TX5_VOL_CTL_GAIN (0x241) +#define SITAR_A_CDC_TX5_VOL_CTL_GAIN__POR (0x00000000) +#define SITAR_A_CDC_TX1_VOL_CTL_CFG (0x222) +#define SITAR_A_CDC_TX1_VOL_CTL_CFG__POR (0x00000000) +#define SITAR_A_CDC_TX2_VOL_CTL_CFG (0x22A) +#define SITAR_A_CDC_TX2_VOL_CTL_CFG__POR (0x00000000) +#define SITAR_A_CDC_TX3_VOL_CTL_CFG (0x232) +#define SITAR_A_CDC_TX3_VOL_CTL_CFG__POR (0x00000000) +#define SITAR_A_CDC_TX4_VOL_CTL_CFG (0x23A) +#define SITAR_A_CDC_TX4_VOL_CTL_CFG__POR (0x00000000) + +#define SITAR_A_CDC_TX1_MUX_CTL (0x223) +#define SITAR_A_CDC_TX1_MUX_CTL__POR (0x00000008) +#define SITAR_A_CDC_TX1_CLK_FS_CTL (0x00000224) +#define SITAR_A_CDC_TX1_CLK_FS_CTL__POR (0x00000003) +#define SITAR_A_CDC_TX2_CLK_FS_CTL (0x0000022C) +#define SITAR_A_CDC_TX2_CLK_FS_CTL__POR (0x00000003) +#define SITAR_A_CDC_TX3_CLK_FS_CTL (0x00000234) +#define SITAR_A_CDC_TX3_CLK_FS_CTL__POR (0x00000003) +#define SITAR_A_CDC_TX4_CLK_FS_CTL (0x0000023C) +#define SITAR_A_CDC_TX4_CLK_FS_CTL__POR (0x00000003) +#define SITAR_A_CDC_TX1_DMIC_CTL (0x225) +#define SITAR_A_CDC_TX1_DMIC_CTL__POR (0x00000000) +#define SITAR_A_CDC_TX2_MUX_CTL (0x22B) +#define SITAR_A_CDC_TX2_MUX_CTL__POR (0x00000008) +#define SITAR_A_CDC_TX3_MUX_CTL (0x233) +#define SITAR_A_CDC_TX3_MUX_CTL__POR (0x00000008) +#define SITAR_A_CDC_TX4_MUX_CTL (0x23B) +#define SITAR_A_CDC_TX4_MUX_CTL__POR (0x00000008) +#define SITAR_A_CDC_TX5_MUX_CTL (0x243) +#define SITAR_A_CDC_TX5_MUX_CTL__POR (0x00000008) + +#define SITAR_A_CDC_SRC1_PDA_CFG (0x2A0) +#define SITAR_A_CDC_SRC1_PDA_CFG__POR (0x00000000) +#define SITAR_A_CDC_SRC1_FS_CTL (0x2A1) +#define SITAR_A_CDC_SRC1_FS_CTL__POR (0x0000001b) + +#define SITAR_A_CDC_RX1_B1_CTL (0x000002B0) +#define SITAR_A_CDC_RX1_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_RX2_B1_CTL (0x000002B8) +#define SITAR_A_CDC_RX2_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_RX3_B1_CTL (0x000002C0) +#define SITAR_A_CDC_RX3_B1_CTL__POR (0x00000000) + +#define SITAR_A_CDC_RX1_B2_CTL (0x000002B1) +#define SITAR_A_CDC_RX1_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_RX2_B2_CTL (0x000002B9) +#define SITAR_A_CDC_RX2_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_RX3_B2_CTL (0x000002C1) +#define SITAR_A_CDC_RX3_B2_CTL__POR (0x00000000) + +#define SITAR_A_CDC_RX1_B3_CTL (0x000002B2) +#define SITAR_A_CDC_RX1_B3_CTL__POR (0x00000000) +#define SITAR_A_CDC_RX2_B3_CTL (0x000002BA) +#define SITAR_A_CDC_RX2_B3_CTL__POR (0x00000000) +#define SITAR_A_CDC_RX3_B3_CTL (0x000002C2) +#define SITAR_A_CDC_RX3_B3_CTL__POR (0x00000000) + +#define SITAR_A_CDC_RX1_B4_CTL (0x000002B3) +#define SITAR_A_CDC_RX1_B4_CTL__POR (0x00000000) +#define SITAR_A_CDC_RX2_B4_CTL (0x000002BB) +#define SITAR_A_CDC_RX2_B4_CTL__POR (0x00000000) +#define SITAR_A_CDC_RX3_B4_CTL (0x000002C3) +#define SITAR_A_CDC_RX3_B4_CTL__POR (0x00000000) + +#define SITAR_A_CDC_RX1_B5_CTL (0x000002B4) +#define SITAR_A_CDC_RX1_B5_CTL__POR (0x00000078) +#define SITAR_A_CDC_RX2_B5_CTL (0x000002BC) +#define SITAR_A_CDC_RX2_B5_CTL__POR (0x00000078) +#define SITAR_A_CDC_RX3_B5_CTL (0x000002C4) +#define SITAR_A_CDC_RX3_B5_CTL__POR (0x00000078) + +#define SITAR_A_CDC_RX1_B6_CTL (0x000002B5) +#define SITAR_A_CDC_RX1_B6_CTL__POR (0x00000080) +#define SITAR_A_CDC_RX2_B6_CTL (0x000002BD) +#define SITAR_A_CDC_RX2_B6_CTL__POR (0x00000080) +#define SITAR_A_CDC_RX3_B6_CTL (0x000002C5) +#define SITAR_A_CDC_RX3_B6_CTL__POR (0x00000080) + + +#define SITAR_A_CDC_RX1_VOL_CTL_B1_CTL (0x2B6) +#define SITAR_A_CDC_RX1_VOL_CTL_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_RX1_VOL_CTL_B2_CTL (0x2B7) +#define SITAR_A_CDC_RX1_VOL_CTL_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_RX2_VOL_CTL_B2_CTL (0x2BF) +#define SITAR_A_CDC_RX2_VOL_CTL_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_RX3_VOL_CTL_B2_CTL (0x2C7) +#define SITAR_A_CDC_RX3_VOL_CTL_B2_CTL__POR (0x00000000) + +#define SITAR_A_CDC_CLK_ANC_RESET_CTL (0x300) +#define SITAR_A_CDC_CLK_ANC_RESET_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLK_RX_RESET_CTL (0x301) +#define SITAR_A_CDC_CLK_RX_RESET_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLK_TX_RESET_B1_CTL (0x302) +#define SITAR_A_CDC_CLK_TX_RESET_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLK_TX_RESET_B2_CTL (0x303) +#define SITAR_A_CDC_CLK_TX_RESET_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLK_DMIC_CTL (0x304) +#define SITAR_A_CDC_CLK_DMIC_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLK_RX_I2S_CTL (0x305) +#define SITAR_A_CDC_CLK_RX_I2S_CTL__POR (0x00000003) +#define SITAR_A_CDC_CLK_TX_I2S_CTL (0x306) +#define SITAR_A_CDC_CLK_TX_I2S_CTL__POR (0x00000003) +#define SITAR_A_CDC_CLK_OTHR_RESET_CTL (0x307) +#define SITAR_A_CDC_CLK_OTHR_RESET_CTL__POR (0x00000010) +#define SITAR_A_CDC_CLK_TX_CLK_EN_B1_CTL (0x308) +#define SITAR_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLK_OTHR_CTL (0x30A) +#define SITAR_A_CDC_CLK_OTHR_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLK_RDAC_CLK_EN_CTL (0x30B) +#define SITAR_A_CDC_CLK_RDAC_CLK_EN_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLK_ANC_CLK_EN_CTL (0x30C) +#define SITAR_A_CDC_CLK_ANC_CLK_EN_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLK_RX_B1_CTL (0x30D) +#define SITAR_A_CDC_CLK_RX_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLK_RX_B2_CTL (0x30E) +#define SITAR_A_CDC_CLK_RX_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLK_MCLK_CTL (0x30F) +#define SITAR_A_CDC_CLK_MCLK_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLK_PDM_CTL (0x310) +#define SITAR_A_CDC_CLK_PDM_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLK_SD_CTL (0x311) +#define SITAR_A_CDC_CLK_SD_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLK_LP_CTL (0x312) +#define SITAR_A_CDC_CLK_LP_CTL__POR (0x00000000) +#define SITAR_A_CDC_CLSG_FREQ_THRESH_B1_CTL (0x320) +#define SITAR_A_CDC_CLSG_FREQ_THRESH_B1_CTL__POR (0x00000007) +#define SITAR_A_CDC_CLSG_FREQ_THRESH_B2_CTL (0x321) +#define SITAR_A_CDC_CLSG_FREQ_THRESH_B2_CTL__POR (0x00000013) +#define SITAR_A_CDC_CLSG_FREQ_THRESH_B3_CTL (0x322) +#define SITAR_A_CDC_CLSG_FREQ_THRESH_B3_CTL__POR (0x0000001b) +#define SITAR_A_CDC_CLSG_FREQ_THRESH_B4_CTL (0x323) +#define SITAR_A_CDC_CLSG_FREQ_THRESH_B4_CTL__POR (0x0000007f) +#define SITAR_A_CDC_CLSG_GAIN_THRESH_CTL (0x324) +#define SITAR_A_CDC_CLSG_GAIN_THRESH_CTL__POR (0x00000026) +#define SITAR_A_CDC_CLSG_TIMER_B1_CFG (0x325) +#define SITAR_A_CDC_CLSG_TIMER_B1_CFG__POR (0x0000000a) +#define SITAR_A_CDC_CLSG_TIMER_B2_CFG (0x326) +#define SITAR_A_CDC_CLSG_TIMER_B2_CFG__POR (0x00000000) +#define SITAR_A_CDC_CLSG_CTL (0x327) +#define SITAR_A_CDC_CLSG_CTL__POR (0x00000013) +#define SITAR_A_CDC_IIR1_GAIN_B1_CTL (0x340) +#define SITAR_A_CDC_IIR1_GAIN_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR1_GAIN_B2_CTL (0x341) +#define SITAR_A_CDC_IIR1_GAIN_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR1_GAIN_B3_CTL (0x342) +#define SITAR_A_CDC_IIR1_GAIN_B3_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR1_GAIN_B4_CTL (0x343) +#define SITAR_A_CDC_IIR1_GAIN_B4_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR1_GAIN_B5_CTL (0x344) +#define SITAR_A_CDC_IIR1_GAIN_B5_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR1_GAIN_B6_CTL (0x345) +#define SITAR_A_CDC_IIR1_GAIN_B6_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR1_GAIN_B7_CTL (0x346) +#define SITAR_A_CDC_IIR1_GAIN_B7_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR1_GAIN_B8_CTL (0x347) +#define SITAR_A_CDC_IIR1_GAIN_B8_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR1_CTL (0x348) +#define SITAR_A_CDC_IIR1_CTL__POR (0x00000040) +#define SITAR_A_CDC_IIR1_GAIN_TIMER_CTL (0x349) +#define SITAR_A_CDC_IIR1_GAIN_TIMER_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR1_COEF_B1_CTL (0x34A) +#define SITAR_A_CDC_IIR1_COEF_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR1_COEF_B2_CTL (0x34B) +#define SITAR_A_CDC_IIR1_COEF_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR1_COEF_B3_CTL (0x34C) +#define SITAR_A_CDC_IIR1_COEF_B3_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR1_COEF_B4_CTL (0x34D) +#define SITAR_A_CDC_IIR1_COEF_B4_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR1_COEF_B5_CTL (0x34E) +#define SITAR_A_CDC_IIR1_COEF_B5_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR2_GAIN_B1_CTL (0x350) +#define SITAR_A_CDC_IIR2_GAIN_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR2_GAIN_B2_CTL (0x351) +#define SITAR_A_CDC_IIR2_GAIN_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR2_GAIN_B3_CTL (0x352) +#define SITAR_A_CDC_IIR2_GAIN_B3_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR2_GAIN_B4_CTL (0x353) +#define SITAR_A_CDC_IIR2_GAIN_B4_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR2_GAIN_B5_CTL (0x354) +#define SITAR_A_CDC_IIR2_GAIN_B5_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR2_GAIN_B6_CTL (0x355) +#define SITAR_A_CDC_IIR2_GAIN_B6_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR2_GAIN_B7_CTL (0x356) +#define SITAR_A_CDC_IIR2_GAIN_B7_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR2_GAIN_B8_CTL (0x357) +#define SITAR_A_CDC_IIR2_GAIN_B8_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR2_CTL (0x358) +#define SITAR_A_CDC_IIR2_CTL__POR (0x00000040) +#define SITAR_A_CDC_IIR2_GAIN_TIMER_CTL (0x359) +#define SITAR_A_CDC_IIR2_GAIN_TIMER_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR2_COEF_B1_CTL (0x35A) +#define SITAR_A_CDC_IIR2_COEF_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR2_COEF_B2_CTL (0x35B) +#define SITAR_A_CDC_IIR2_COEF_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR2_COEF_B3_CTL (0x35C) +#define SITAR_A_CDC_IIR2_COEF_B3_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR2_COEF_B4_CTL (0x35D) +#define SITAR_A_CDC_IIR2_COEF_B4_CTL__POR (0x00000000) +#define SITAR_A_CDC_IIR2_COEF_B5_CTL (0x35E) +#define SITAR_A_CDC_IIR2_COEF_B5_CTL__POR (0x00000000) +#define SITAR_A_CDC_TOP_GAIN_UPDATE (0x360) +#define SITAR_A_CDC_TOP_GAIN_UPDATE__POR (0x00000000) +#define SITAR_A_CDC_TOP_RDAC_DOUT_CTL (0x361) +#define SITAR_A_CDC_TOP_RDAC_DOUT_CTL__POR (0x00000000) +#define SITAR_A_CDC_DEBUG_B1_CTL (0x368) +#define SITAR_A_CDC_DEBUG_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_DEBUG_B2_CTL (0x369) +#define SITAR_A_CDC_DEBUG_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_DEBUG_B3_CTL (0x36A) +#define SITAR_A_CDC_DEBUG_B3_CTL__POR (0x00000000) +#define SITAR_A_CDC_DEBUG_B4_CTL (0x36B) +#define SITAR_A_CDC_DEBUG_B4_CTL__POR (0x00000000) +#define SITAR_A_CDC_DEBUG_B5_CTL (0x36C) +#define SITAR_A_CDC_DEBUG_B5_CTL__POR (0x00000000) +#define SITAR_A_CDC_DEBUG_B6_CTL (0x36D) +#define SITAR_A_CDC_DEBUG_B6_CTL__POR (0x00000000) +#define SITAR_A_CDC_DEBUG_B7_CTL (0x36E) +#define SITAR_A_CDC_DEBUG_B7_CTL__POR (0x00000000) +#define SITAR_A_CDC_COMP1_B1_CTL (0x370) +#define SITAR_A_CDC_COMP1_B1_CTL__POR (0x00000030) +#define SITAR_A_CDC_COMP1_B2_CTL (0x371) +#define SITAR_A_CDC_COMP1_B2_CTL__POR (0x000000b5) +#define SITAR_A_CDC_COMP1_B3_CTL (0x372) +#define SITAR_A_CDC_COMP1_B3_CTL__POR (0x00000028) +#define SITAR_A_CDC_COMP1_B4_CTL (0x373) +#define SITAR_A_CDC_COMP1_B4_CTL__POR (0x0000003c) +#define SITAR_A_CDC_COMP1_B5_CTL (0x374) +#define SITAR_A_CDC_COMP1_B5_CTL__POR (0x0000001f) +#define SITAR_A_CDC_COMP1_B6_CTL (0x375) +#define SITAR_A_CDC_COMP1_B6_CTL__POR (0x00000000) +#define SITAR_A_CDC_COMP1_SHUT_DOWN_STATUS (0x376) +#define SITAR_A_CDC_COMP1_SHUT_DOWN_STATUS__POR (0x00000003) +#define SITAR_A_CDC_COMP1_FS_CFG (0x377) +#define SITAR_A_CDC_COMP1_FS_CFG__POR (0x0000001b) +#define SITAR_A_CDC_CONN_RX1_B1_CTL (0x380) +#define SITAR_A_CDC_CONN_RX1_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_RX1_B2_CTL (0x381) +#define SITAR_A_CDC_CONN_RX1_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_RX1_B3_CTL (0x382) +#define SITAR_A_CDC_CONN_RX1_B3_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_RX2_B1_CTL (0x383) +#define SITAR_A_CDC_CONN_RX2_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_RX2_B2_CTL (0x384) +#define SITAR_A_CDC_CONN_RX2_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_RX2_B3_CTL (0x385) +#define SITAR_A_CDC_CONN_RX2_B3_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_RX3_B1_CTL (0x386) +#define SITAR_A_CDC_CONN_RX3_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_RX3_B2_CTL (0x387) +#define SITAR_A_CDC_CONN_RX3_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_RX3_B3_CTL (0x388) +#define SITAR_A_CDC_CONN_RX3_B3_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_ANC_B1_CTL (0x391) +#define SITAR_A_CDC_CONN_ANC_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_ANC_B2_CTL (0x392) +#define SITAR_A_CDC_CONN_ANC_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_TX_B1_CTL (0x393) +#define SITAR_A_CDC_CONN_TX_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_TX_B2_CTL (0x394) +#define SITAR_A_CDC_CONN_TX_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_EQ1_B1_CTL (0x397) +#define SITAR_A_CDC_CONN_EQ1_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_EQ1_B2_CTL (0x398) +#define SITAR_A_CDC_CONN_EQ1_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_EQ1_B3_CTL (0x399) +#define SITAR_A_CDC_CONN_EQ1_B3_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_EQ1_B4_CTL (0x39A) +#define SITAR_A_CDC_CONN_EQ1_B4_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_EQ2_B1_CTL (0x39B) +#define SITAR_A_CDC_CONN_EQ2_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_EQ2_B2_CTL (0x39C) +#define SITAR_A_CDC_CONN_EQ2_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_EQ2_B3_CTL (0x39D) +#define SITAR_A_CDC_CONN_EQ2_B3_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_EQ2_B4_CTL (0x39E) +#define SITAR_A_CDC_CONN_EQ2_B4_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_SRC1_B1_CTL (0x39F) +#define SITAR_A_CDC_CONN_SRC1_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_SRC1_B2_CTL (0x3A0) +#define SITAR_A_CDC_CONN_SRC1_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_SRC2_B1_CTL (0x3A1) +#define SITAR_A_CDC_CONN_SRC2_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_SRC2_B2_CTL (0x3A2) +#define SITAR_A_CDC_CONN_SRC2_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_TX_SB_B1_CTL (0x3A3) +#define SITAR_A_CDC_CONN_TX_SB_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_TX_SB_B2_CTL (0x3A4) +#define SITAR_A_CDC_CONN_TX_SB_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_TX_SB_B3_CTL (0x3A5) +#define SITAR_A_CDC_CONN_TX_SB_B3_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_TX_SB_B4_CTL (0x3A6) +#define SITAR_A_CDC_CONN_TX_SB_B4_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_TX_SB_B5_CTL (0x3A7) +#define SITAR_A_CDC_CONN_TX_SB_B5_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_RX_SB_B1_CTL (0x3AE) +#define SITAR_A_CDC_CONN_RX_SB_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_RX_SB_B2_CTL (0x3AF) +#define SITAR_A_CDC_CONN_RX_SB_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_CLSG_CTL (0x3B0) +#define SITAR_A_CDC_CONN_CLSG_CTL__POR (0x00000000) +#define SITAR_A_CDC_CONN_SPARE (0x3B1) +#define SITAR_A_CDC_CONN_SPARE__POR (0x00000000) +#define SITAR_A_CDC_MBHC_EN_CTL (0x3C0) +#define SITAR_A_CDC_MBHC_EN_CTL__POR (0x00000000) +#define SITAR_A_CDC_MBHC_FIR_B1_CFG (0x3C1) +#define SITAR_A_CDC_MBHC_FIR_B1_CFG__POR (0x00000000) +#define SITAR_A_CDC_MBHC_FIR_B2_CFG (0x3C2) +#define SITAR_A_CDC_MBHC_FIR_B2_CFG__POR (0x00000006) +#define SITAR_A_CDC_MBHC_TIMER_B1_CTL (0x3C3) +#define SITAR_A_CDC_MBHC_TIMER_B1_CTL__POR (0x00000003) +#define SITAR_A_CDC_MBHC_TIMER_B2_CTL (0x3C4) +#define SITAR_A_CDC_MBHC_TIMER_B2_CTL__POR (0x00000009) +#define SITAR_A_CDC_MBHC_TIMER_B3_CTL (0x3C5) +#define SITAR_A_CDC_MBHC_TIMER_B3_CTL__POR (0x0000001e) +#define SITAR_A_CDC_MBHC_TIMER_B4_CTL (0x3C6) +#define SITAR_A_CDC_MBHC_TIMER_B4_CTL__POR (0x00000045) +#define SITAR_A_CDC_MBHC_TIMER_B5_CTL (0x3C7) +#define SITAR_A_CDC_MBHC_TIMER_B5_CTL__POR (0x00000004) +#define SITAR_A_CDC_MBHC_TIMER_B6_CTL (0x3C8) +#define SITAR_A_CDC_MBHC_TIMER_B6_CTL__POR (0x00000078) +#define SITAR_A_CDC_MBHC_B1_STATUS (0x3C9) +#define SITAR_A_CDC_MBHC_B1_STATUS__POR (0x00000000) +#define SITAR_A_CDC_MBHC_B2_STATUS (0x3CA) +#define SITAR_A_CDC_MBHC_B2_STATUS__POR (0x00000000) +#define SITAR_A_CDC_MBHC_B3_STATUS (0x3CB) +#define SITAR_A_CDC_MBHC_B3_STATUS__POR (0x00000000) +#define SITAR_A_CDC_MBHC_B4_STATUS (0x3CC) +#define SITAR_A_CDC_MBHC_B4_STATUS__POR (0x00000000) +#define SITAR_A_CDC_MBHC_B5_STATUS (0x3CD) +#define SITAR_A_CDC_MBHC_B5_STATUS__POR (0x00000000) +#define SITAR_A_CDC_MBHC_B1_CTL (0x3CE) +#define SITAR_A_CDC_MBHC_B1_CTL__POR (0x000000c0) +#define SITAR_A_CDC_MBHC_B2_CTL (0x3CF) +#define SITAR_A_CDC_MBHC_B2_CTL__POR (0x0000005d) +#define SITAR_A_CDC_MBHC_VOLT_B1_CTL (0x3D0) +#define SITAR_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00000000) +#define SITAR_A_CDC_MBHC_VOLT_B2_CTL (0x3D1) +#define SITAR_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00000000) +#define SITAR_A_CDC_MBHC_VOLT_B3_CTL (0x3D2) +#define SITAR_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00000000) +#define SITAR_A_CDC_MBHC_VOLT_B4_CTL (0x3D3) +#define SITAR_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00000000) +#define SITAR_A_CDC_MBHC_VOLT_B5_CTL (0x3D4) +#define SITAR_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00000000) +#define SITAR_A_CDC_MBHC_VOLT_B6_CTL (0x3D5) +#define SITAR_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00000000) +#define SITAR_A_CDC_MBHC_VOLT_B7_CTL (0x3D6) +#define SITAR_A_CDC_MBHC_VOLT_B7_CTL__POR (0x000000ff) +#define SITAR_A_CDC_MBHC_VOLT_B8_CTL (0x3D7) +#define SITAR_A_CDC_MBHC_VOLT_B8_CTL__POR (0x00000007) +#define SITAR_A_CDC_MBHC_VOLT_B9_CTL (0x3D8) +#define SITAR_A_CDC_MBHC_VOLT_B9_CTL__POR (0x000000ff) +#define SITAR_A_CDC_MBHC_VOLT_B10_CTL (0x3D9) +#define SITAR_A_CDC_MBHC_VOLT_B10_CTL__POR (0x0000007f) +#define SITAR_A_CDC_MBHC_VOLT_B11_CTL (0x3DA) +#define SITAR_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00000000) +#define SITAR_A_CDC_MBHC_VOLT_B12_CTL (0x3DB) +#define SITAR_A_CDC_MBHC_VOLT_B12_CTL__POR (0x00000080) +#define SITAR_A_CDC_MBHC_CLK_CTL (0x3DC) +#define SITAR_A_CDC_MBHC_CLK_CTL__POR (0x00000000) +#define SITAR_A_CDC_MBHC_INT_CTL (0x3DD) +#define SITAR_A_CDC_MBHC_INT_CTL__POR (0x00000000) +#define SITAR_A_CDC_MBHC_DEBUG_CTL (0x3DE) +#define SITAR_A_CDC_MBHC_DEBUG_CTL__POR (0x00000000) +#define SITAR_A_CDC_MBHC_SPARE (0x3DF) +#define SITAR_A_CDC_MBHC_SPARE__POR (0x00000000) +/* SLIMBUS Slave Registers */ +#define SITAR_SLIM_PGD_PORT_INT_EN0 (0x30) +#define SITAR_SLIM_PGD_PORT_INT_STATUS0 (0x34) +#define SITAR_SLIM_PGD_PORT_INT_CLR0 (0x38) +#define SITAR_SLIM_PGD_PORT_INT_SOURCE0 (0x60) + +/* Macros for Packing Register Writes into a U32 */ +#define SITAR_PACKED_REG_SIZE sizeof(u32) + +#define SITAR_CODEC_PACK_ENTRY(reg, mask, val) ((val & 0xff)|\ + ((mask & 0xff) << 8)|((reg & 0xffff) << 16)) + +#define SITAR_CODEC_UNPACK_ENTRY(packed, reg, mask, val) \ + do { \ + ((reg) = ((packed >> 16) & (0xffff))); \ + ((mask) = ((packed >> 8) & (0xff))); \ + ((val) = ((packed) & (0xff))); \ + } while (0); +#endif diff --git a/original-kernel-headers/linux/mfd/wcd9xxx/wcd9310_registers.h b/original-kernel-headers/linux/mfd/wcd9xxx/wcd9310_registers.h new file mode 100644 index 0000000..46336e2 --- /dev/null +++ b/original-kernel-headers/linux/mfd/wcd9xxx/wcd9310_registers.h @@ -0,0 +1,1117 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef TABLA_CODEC_DIGITAL_H + +#define TABLA_CODEC_DIGITAL_H +#include <linux/mfd/wcd9xxx/wcd9xxx_registers.h> + +#define TABLA_A_CHIP_CTL WCD9XXX_A_CHIP_CTL +#define TABLA_A_CHIP_CTL__POR WCD9XXX_A_CHIP_CTL__POR +#define TABLA_A_CHIP_STATUS WCD9XXX_A_CHIP_STATUS +#define TABLA_A_CHIP_STATUS__POR WCD9XXX_A_CHIP_STATUS__POR +#define TABLA_A_CHIP_ID_BYTE_0 WCD9XXX_A_CHIP_ID_BYTE_0 +#define TABLA_A_CHIP_ID_BYTE_0__POR WCD9XXX_A_CHIP_ID_BYTE_0__POR +#define TABLA_A_CHIP_ID_BYTE_1 WCD9XXX_A_CHIP_ID_BYTE_1 +#define TABLA_A_CHIP_ID_BYTE_1__POR WCD9XXX_A_CHIP_ID_BYTE_1__POR +#define TABLA_A_CHIP_ID_BYTE_2 WCD9XXX_A_CHIP_ID_BYTE_2 +#define TABLA_A_CHIP_ID_BYTE_2__POR WCD9XXX_A_CHIP_ID_BYTE_2__POR +#define TABLA_A_CHIP_ID_BYTE_3 WCD9XXX_A_CHIP_ID_BYTE_3 +#define TABLA_A_CHIP_ID_BYTE_3__POR WCD9XXX_A_CHIP_ID_BYTE_3__POR +#define TABLA_A_CHIP_VERSION WCD9XXX_A_CHIP_VERSION +#define TABLA_A_CHIP_VERSION__POR WCD9XXX_A_CHIP_VERSION__POR +#define TABLA_A_SB_VERSION WCD9XXX_A_SB_VERSION +#define TABLA_A_SB_VERSION__POR WCD9XXX_A_SB_VERSION__POR +#define TABLA_A_SLAVE_ID_1 WCD9XXX_A_SLAVE_ID_1 +#define TABLA_A_SLAVE_ID_1__POR WCD9XXX_A_SLAVE_ID_1__POR +#define TABLA_A_SLAVE_ID_2 WCD9XXX_A_SLAVE_ID_2 +#define TABLA_A_SLAVE_ID_2__POR WCD9XXX_A_SLAVE_ID_2__POR +#define TABLA_A_SLAVE_ID_3 WCD9XXX_A_SLAVE_ID_3 +#define TABLA_A_SLAVE_ID_3__POR WCD9XXX_A_SLAVE_ID_3__POR +#define TABLA_A_PIN_CTL_OE0 (0x10) +#define TABLA_A_PIN_CTL_OE0__POR (0x00000000) +#define TABLA_A_PIN_CTL_OE1 (0x11) +#define TABLA_A_PIN_CTL_OE1__POR (0x00000000) +#define TABLA_A_PIN_CTL_DATA0 (0x12) +#define TABLA_A_PIN_CTL_DATA0__POR (0x00000000) +#define TABLA_A_PIN_CTL_DATA1 (0x13) +#define TABLA_A_PIN_CTL_DATA1__POR (0x00000000) +#define TABLA_A_HDRIVE_GENERIC (0x18) +#define TABLA_A_HDRIVE_GENERIC__POR (0x00000000) +#define TABLA_A_HDRIVE_OVERRIDE (0x19) +#define TABLA_A_HDRIVE_OVERRIDE__POR (0x00000008) +#define TABLA_A_ANA_CSR_WAIT_STATE (0x20) +#define TABLA_A_ANA_CSR_WAIT_STATE__POR (0x00000044) +#define TABLA_A_PROCESS_MONITOR_CTL0 (0x40) +#define TABLA_A_PROCESS_MONITOR_CTL0__POR (0x00000080) +#define TABLA_A_PROCESS_MONITOR_CTL1 (0x41) +#define TABLA_A_PROCESS_MONITOR_CTL1__POR (0x00000000) +#define TABLA_A_PROCESS_MONITOR_CTL2 (0x42) +#define TABLA_A_PROCESS_MONITOR_CTL2__POR (0x00000000) +#define TABLA_A_PROCESS_MONITOR_CTL3 (0x43) +#define TABLA_A_PROCESS_MONITOR_CTL3__POR (0x00000001) +#define TABLA_A_QFUSE_CTL (0x48) +#define TABLA_A_QFUSE_CTL__POR (0x00000000) +#define TABLA_A_QFUSE_STATUS (0x49) +#define TABLA_A_QFUSE_STATUS__POR (0x00000000) +#define TABLA_A_QFUSE_DATA_OUT0 (0x4A) +#define TABLA_A_QFUSE_DATA_OUT0__POR (0x00000000) +#define TABLA_A_QFUSE_DATA_OUT1 (0x4B) +#define TABLA_A_QFUSE_DATA_OUT1__POR (0x00000000) +#define TABLA_A_QFUSE_DATA_OUT2 (0x4C) +#define TABLA_A_QFUSE_DATA_OUT2__POR (0x00000000) +#define TABLA_A_QFUSE_DATA_OUT3 (0x4D) +#define TABLA_A_QFUSE_DATA_OUT3__POR (0x00000000) +#define TABLA_A_CDC_CTL WCD9XXX_A_CDC_CTL +#define TABLA_A_CDC_CTL__POR WCD9XXX_A_CDC_CTL__POR +#define TABLA_A_LEAKAGE_CTL WCD9XXX_A_LEAKAGE_CTL +#define TABLA_A_LEAKAGE_CTL__POR WCD9XXX_A_LEAKAGE_CTL__POR +#define TABLA_A_INTR_MODE (0x90) +#define TABLA_A_INTR_MODE__POR (0x00000000) +#define TABLA_A_INTR_MASK0 (0x94) +#define TABLA_A_INTR_MASK0__POR (0x000000ff) +#define TABLA_A_INTR_MASK1 (0x95) +#define TABLA_A_INTR_MASK1__POR (0x000000ff) +#define TABLA_A_INTR_MASK2 (0x96) +#define TABLA_A_INTR_MASK2__POR (0x000000ff) +#define TABLA_A_INTR_STATUS0 (0x98) +#define TABLA_A_INTR_STATUS0__POR (0x00000000) +#define TABLA_A_INTR_STATUS1 (0x99) +#define TABLA_A_INTR_STATUS1__POR (0x00000000) +#define TABLA_A_INTR_STATUS2 (0x9A) +#define TABLA_A_INTR_STATUS2__POR (0x00000000) +#define TABLA_A_INTR_CLEAR0 (0x9C) +#define TABLA_A_INTR_CLEAR0__POR (0x00000000) +#define TABLA_A_INTR_CLEAR1 (0x9D) +#define TABLA_A_INTR_CLEAR1__POR (0x00000000) +#define TABLA_A_INTR_CLEAR2 (0x9E) +#define TABLA_A_INTR_CLEAR2__POR (0x00000000) +#define TABLA_A_INTR_LEVEL0 (0xA0) +#define TABLA_A_INTR_LEVEL0__POR (0x00000001) +#define TABLA_A_INTR_LEVEL1 (0xA1) +#define TABLA_A_INTR_LEVEL1__POR (0x00000000) +#define TABLA_A_INTR_LEVEL2 (0xA2) +#define TABLA_A_INTR_LEVEL2__POR (0x00000000) +#define TABLA_A_INTR_TEST0 (0xA4) +#define TABLA_A_INTR_TEST0__POR (0x00000000) +#define TABLA_A_INTR_TEST1 (0xA5) +#define TABLA_A_INTR_TEST1__POR (0x00000000) +#define TABLA_A_INTR_TEST2 (0xA6) +#define TABLA_A_INTR_TEST2__POR (0x00000000) +#define TABLA_A_INTR_SET0 (0xA8) +#define TABLA_A_INTR_SET0__POR (0x00000000) +#define TABLA_A_INTR_SET1 (0xA9) +#define TABLA_A_INTR_SET1__POR (0x00000000) +#define TABLA_A_INTR_SET2 (0xAA) +#define TABLA_A_INTR_SET2__POR (0x00000000) +#define TABLA_A_CDC_TX_I2S_SCK_MODE (0xC0) +#define TABLA_A_CDC_TX_I2S_SCK_MODE__POR (0x00000000) +#define TABLA_A_CDC_TX_I2S_WS_MODE (0xC1) +#define TABLA_A_CDC_TX_I2S_WS_MODE__POR (0x00000000) +#define TABLA_A_CDC_DMIC_DATA0_MODE (0xC4) +#define TABLA_A_CDC_DMIC_DATA0_MODE__POR (0x00000000) +#define TABLA_A_CDC_DMIC_CLK0_MODE (0xC5) +#define TABLA_A_CDC_DMIC_CLK0_MODE__POR (0x00000000) +#define TABLA_A_CDC_DMIC_DATA1_MODE (0xC6) +#define TABLA_A_CDC_DMIC_DATA1_MODE__POR (0x00000000) +#define TABLA_A_CDC_DMIC_CLK1_MODE (0xC7) +#define TABLA_A_CDC_DMIC_CLK1_MODE__POR (0x00000000) +#define TABLA_A_CDC_RX_I2S_SCK_MODE (0xC8) +#define TABLA_A_CDC_RX_I2S_SCK_MODE__POR (0x00000000) +#define TABLA_A_CDC_RX_I2S_WS_MODE (0xC9) +#define TABLA_A_CDC_RX_I2S_WS_MODE__POR (0x00000000) +#define TABLA_A_CDC_DMIC_DATA2_MODE (0xCA) +#define TABLA_A_CDC_DMIC_DATA2_MODE__POR (0x00000000) +#define TABLA_A_CDC_DMIC_CLK2_MODE (0xCB) +#define TABLA_A_CDC_DMIC_CLK2_MODE__POR (0x00000000) +#define TABLA_A_CDC_INTR_MODE (0xCC) +#define TABLA_A_CDC_INTR_MODE__POR (0x00000000) +#define TABLA_A_BIAS_REF_CTL (0x0100) +#define TABLA_A_BIAS_REF_CTL__POR (0x0000001C) +#define TABLA_A_BIAS_CENTRAL_BG_CTL (0x0101) +#define TABLA_A_BIAS_CENTRAL_BG_CTL__POR (0x00000050) +#define TABLA_A_BIAS_PRECHRG_CTL (0x0102) +#define TABLA_A_BIAS_PRECHRG_CTL__POR (0x00000007) +#define TABLA_A_BIAS_CURR_CTL_1 (0x0103) +#define TABLA_A_BIAS_CURR_CTL_1__POR (0x00000052) +#define TABLA_A_BIAS_CURR_CTL_2 (0x0104) +#define TABLA_A_BIAS_CURR_CTL_2__POR (0x00000000) +#define TABLA_A_BIAS_CONFIG_MODE_BG_CTL (0x0105) +#define TABLA_A_BIAS_CONFIG_MODE_BG_CTL__POR (0x00000016) +#define TABLA_A_BIAS_BG_STATUS (0x0106) +#define TABLA_A_BIAS_BG_STATUS__POR (0x00000000) +#define TABLA_A_CLK_BUFF_EN1 (0x0108) +#define TABLA_A_CLK_BUFF_EN1__POR (0x00000004) +#define TABLA_A_CLK_BUFF_EN2 (0x0109) +#define TABLA_A_CLK_BUFF_EN2__POR (0x00000002) +#define TABLA_A_LDO_H_MODE_1 (0x0110) +#define TABLA_A_LDO_H_MODE_1__POR (0x00000065) +#define TABLA_A_LDO_H_MODE_2 (0x0111) +#define TABLA_A_LDO_H_MODE_2__POR (0x000000A8) +#define TABLA_A_LDO_H_LOOP_CTL (0x0112) +#define TABLA_A_LDO_H_LOOP_CTL__POR (0x0000006B) +#define TABLA_A_LDO_H_COMP_1 (0x0113) +#define TABLA_A_LDO_H_COMP_1__POR (0x00000084) +#define TABLA_A_LDO_H_COMP_2 (0x0114) +#define TABLA_A_LDO_H_COMP_2__POR (0x000000E0) +#define TABLA_A_LDO_H_BIAS_1 (0x0115) +#define TABLA_A_LDO_H_BIAS_1__POR (0x0000006D) +#define TABLA_A_LDO_H_BIAS_2 (0x0116) +#define TABLA_A_LDO_H_BIAS_2__POR (0x000000A5) +#define TABLA_A_LDO_H_BIAS_3 (0x0117) +#define TABLA_A_LDO_H_BIAS_3__POR (0x00000060) +#define TABLA_A_LDO_L_MODE_1 (0x0118) +#define TABLA_A_LDO_L_MODE_1__POR (0x00000028) +#define TABLA_A_LDO_L_MODE_2 (0x0119) +#define TABLA_A_LDO_L_MODE_2__POR (0x000000A8) +#define TABLA_A_LDO_L_LOOP_CTL (0x011A) +#define TABLA_A_LDO_L_LOOP_CTL__POR (0x0000006D) +#define TABLA_A_LDO_L_COMP_1 (0x011B) +#define TABLA_A_LDO_L_COMP_1__POR (0x00000031) +#define TABLA_A_LDO_L_COMP_2 (0x011C) +#define TABLA_A_LDO_L_COMP_2__POR (0x000000A0) +#define TABLA_A_LDO_L_BIAS_1 (0x011D) +#define TABLA_A_LDO_L_BIAS_1__POR (0x0000006D) +#define TABLA_A_LDO_L_BIAS_2 (0x011E) +#define TABLA_A_LDO_L_BIAS_2__POR (0x00000065) +#define TABLA_A_LDO_L_BIAS_3 (0x011F) +#define TABLA_A_LDO_L_BIAS_3__POR (0x00000050) +#define TABLA_A_MICB_CFILT_1_CTL (0x0128) +#define TABLA_A_MICB_CFILT_1_CTL__POR (0x00000040) +#define TABLA_A_MICB_CFILT_1_VAL (0x0129) +#define TABLA_A_MICB_CFILT_1_VAL__POR (0x00000080) +#define TABLA_A_MICB_CFILT_1_PRECHRG (0x012A) +#define TABLA_A_MICB_CFILT_1_PRECHRG__POR (0x00000038) +#define TABLA_A_MICB_1_CTL (0x012B) +#define TABLA_A_MICB_1_CTL__POR (0x00000016) +#define TABLA_A_MICB_1_INT_RBIAS (0x012C) +#define TABLA_A_MICB_1_INT_RBIAS__POR (0x00000000) +#define TABLA_A_MICB_1_MBHC (0x012D) +#define TABLA_A_MICB_1_MBHC__POR (0x00000001) +#define TABLA_A_MICB_CFILT_2_CTL (0x012E) +#define TABLA_A_MICB_CFILT_2_CTL__POR (0x00000040) +#define TABLA_A_MICB_CFILT_2_VAL (0x012F) +#define TABLA_A_MICB_CFILT_2_VAL__POR (0x00000080) +#define TABLA_A_MICB_CFILT_2_PRECHRG (0x0130) +#define TABLA_A_MICB_CFILT_2_PRECHRG__POR (0x00000038) +#define TABLA_A_MICB_2_CTL (0x0131) +#define TABLA_A_MICB_2_CTL__POR (0x00000016) +#define TABLA_A_MICB_2_INT_RBIAS (0x0132) +#define TABLA_A_MICB_2_INT_RBIAS__POR (0x00000000) +#define TABLA_A_MICB_2_MBHC (0x0133) +#define TABLA_A_MICB_2_MBHC__POR (0x00000000) +#define TABLA_A_MICB_CFILT_3_CTL (0x0134) +#define TABLA_A_MICB_CFILT_3_CTL__POR (0x00000040) +#define TABLA_A_MICB_CFILT_3_VAL (0x0135) +#define TABLA_A_MICB_CFILT_3_VAL__POR (0x00000080) +#define TABLA_A_MICB_CFILT_3_PRECHRG (0x0136) +#define TABLA_A_MICB_CFILT_3_PRECHRG__POR (0x00000038) +#define TABLA_A_MICB_3_CTL (0x0137) +#define TABLA_A_MICB_3_CTL__POR (0x00000016) +#define TABLA_A_MICB_3_INT_RBIAS (0x0138) +#define TABLA_A_MICB_3_INT_RBIAS__POR (0x00000000) +#define TABLA_A_MICB_3_MBHC (0x0139) +#define TABLA_A_MICB_3_MBHC__POR (0x00000000) +#define TABLA_1_A_MICB_4_CTL (0x013A) +#define TABLA_2_A_MICB_4_CTL (0x013D) +#define TABLA_A_MICB_4_CTL__POR (0x00000016) +#define TABLA_1_A_MICB_4_INT_RBIAS (0x013B) +#define TABLA_2_A_MICB_4_INT_RBIAS (0x013E) +#define TABLA_A_MICB_4_INT_RBIAS__POR (0x00000000) +#define TABLA_1_A_MICB_4_MBHC (0x013C) +#define TABLA_2_A_MICB_4_MBHC (0x013F) +#define TABLA_A_MICB_4_MBHC__POR (0x00000001) +#define TABLA_A_TX_COM_BIAS (0x014C) +#define TABLA_A_TX_COM_BIAS__POR (0x000000E0) +#define TABLA_A_MBHC_SCALING_MUX_1 (0x014E) +#define TABLA_A_MBHC_SCALING_MUX_1__POR (0x00000000) +#define TABLA_A_MBHC_SCALING_MUX_2 (0x014F) +#define TABLA_A_MBHC_SCALING_MUX_2__POR (0x00000080) +#define TABLA_A_TX_SUP_SWITCH_CTRL_1 (0x0151) +#define TABLA_A_TX_SUP_SWITCH_CTRL_1__POR (0x00000000) +#define TABLA_A_TX_SUP_SWITCH_CTRL_2 (0x0152) +#define TABLA_A_TX_SUP_SWITCH_CTRL_2__POR (0x00000080) +#define TABLA_A_TX_1_2_EN (0x0153) +#define TABLA_A_TX_1_2_EN__POR (0x00000000) +#define TABLA_A_TX_1_2_TEST_EN (0x0154) +#define TABLA_A_TX_1_2_TEST_EN__POR (0x000000CC) +#define TABLA_A_TX_1_2_ADC_CH1 (0x0155) +#define TABLA_A_TX_1_2_ADC_CH1__POR (0x00000044) +#define TABLA_A_TX_1_2_ADC_CH2 (0x0156) +#define TABLA_A_TX_1_2_ADC_CH2__POR (0x00000044) +#define TABLA_A_TX_1_2_ATEST_REFCTRL (0x0157) +#define TABLA_A_TX_1_2_ATEST_REFCTRL__POR (0x00000000) +#define TABLA_A_TX_1_2_TEST_CTL (0x0158) +#define TABLA_A_TX_1_2_TEST_CTL__POR (0x00000038) +#define TABLA_A_TX_1_2_TEST_BLOCK_EN (0x0159) +#define TABLA_A_TX_1_2_TEST_BLOCK_EN__POR (0x000000FF) +#define TABLA_A_TX_1_2_TXFE_CLKDIV (0x015A) +#define TABLA_A_TX_1_2_TXFE_CLKDIV__POR (0x000000EE) +#define TABLA_A_TX_1_2_SAR_ERR_CH1 (0x015B) +#define TABLA_A_TX_1_2_SAR_ERR_CH1__POR (0x00000000) +#define TABLA_A_TX_1_2_SAR_ERR_CH2 (0x015C) +#define TABLA_A_TX_1_2_SAR_ERR_CH2__POR (0x00000000) +#define TABLA_A_TX_3_4_EN (0x015D) +#define TABLA_A_TX_3_4_EN__POR (0x00000000) +#define TABLA_A_TX_3_4_TEST_EN (0x015E) +#define TABLA_A_TX_3_4_TEST_EN__POR (0x000000CC) +#define TABLA_A_TX_3_4_ADC_CH3 (0x015F) +#define TABLA_A_TX_3_4_ADC_CH3__POR (0x00000044) +#define TABLA_A_TX_3_4_ADC_CH4 (0x0160) +#define TABLA_A_TX_3_4_ADC_CH4__POR (0x00000044) +#define TABLA_A_TX_3_4_ATEST_REFCTRL (0x0161) +#define TABLA_A_TX_3_4_ATEST_REFCTRL__POR (0x00000000) +#define TABLA_A_TX_3_4_TEST_CTL (0x0162) +#define TABLA_A_TX_3_4_TEST_CTL__POR (0x00000038) +#define TABLA_A_TX_3_4_TEST_BLOCK_EN (0x0163) +#define TABLA_A_TX_3_4_TEST_BLOCK_EN__POR (0x000000FF) +#define TABLA_A_TX_3_4_TXFE_CKDIV (0x0164) +#define TABLA_A_TX_3_4_TXFE_CKDIV__POR (0x000000EE) +#define TABLA_A_TX_3_4_SAR_ERR_CH3 (0x0165) +#define TABLA_A_TX_3_4_SAR_ERR_CH3__POR (0x00000000) +#define TABLA_A_TX_3_4_SAR_ERR_CH4 (0x0166) +#define TABLA_A_TX_3_4_SAR_ERR_CH4__POR (0x00000000) +#define TABLA_A_TX_5_6_EN (0x0167) +#define TABLA_A_TX_5_6_EN__POR (0x00000011) +#define TABLA_A_TX_5_6_TEST_EN (0x0168) +#define TABLA_A_TX_5_6_TEST_EN__POR (0x000000CC) +#define TABLA_A_TX_5_6_ADC_CH5 (0x0169) +#define TABLA_A_TX_5_6_ADC_CH5__POR (0x00000044) +#define TABLA_A_TX_5_6_ADC_CH6 (0x016A) +#define TABLA_A_TX_5_6_ADC_CH6__POR (0x00000044) +#define TABLA_A_TX_5_6_ATEST_REFCTRL (0x016B) +#define TABLA_A_TX_5_6_ATEST_REFCTRL__POR (0x00000000) +#define TABLA_A_TX_5_6_TEST_CTL (0x016C) +#define TABLA_A_TX_5_6_TEST_CTL__POR (0x00000038) +#define TABLA_A_TX_5_6_TEST_BLOCK_EN (0x016D) +#define TABLA_A_TX_5_6_TEST_BLOCK_EN__POR (0x000000FF) +#define TABLA_A_TX_5_6_TXFE_CKDIV (0x016E) +#define TABLA_A_TX_5_6_TXFE_CKDIV__POR (0x000000EE) +#define TABLA_A_TX_5_6_SAR_ERR_CH5 (0x016F) +#define TABLA_A_TX_5_6_SAR_ERR_CH5__POR (0x00000000) +#define TABLA_A_TX_5_6_SAR_ERR_CH6 (0x0170) +#define TABLA_A_TX_5_6_SAR_ERR_CH6__POR (0x00000000) +#define TABLA_A_TX_7_MBHC_EN (0x0171) +#define TABLA_A_TX_7_MBHC_EN__POR (0x0000000C) +#define TABLA_A_TX_7_MBHC_ATEST_REFCTRL (0x0172) +#define TABLA_A_TX_7_MBHC_ATEST_REFCTRL__POR (0x00000000) +#define TABLA_A_TX_7_MBHC_ADC (0x0173) +#define TABLA_A_TX_7_MBHC_ADC__POR (0x00000044) +#define TABLA_A_TX_7_MBHC_TEST_CTL (0x0174) +#define TABLA_A_TX_7_MBHC_TEST_CTL__POR (0x00000038) +#define TABLA_A_TX_7_MBHC_SAR_ERR (0x0175) +#define TABLA_A_TX_7_MBHC_SAR_ERR__POR (0x00000000) +#define TABLA_A_TX_7_TXFE_CLKDIV (0x0176) +#define TABLA_A_TX_7_TXFE_CLKDIV__POR (0x0000001C) +#define TABLA_A_AUX_COM_CTL (0x0180) +#define TABLA_A_AUX_COM_CTL__POR (0x00000034) +#define TABLA_A_AUX_COM_ATEST (0x0181) +#define TABLA_A_AUX_COM_ATEST__POR (0x00000000) +#define TABLA_A_AUX_L_EN (0x0182) +#define TABLA_A_AUX_L_EN__POR (0x00000000) +#define TABLA_A_AUX_L_GAIN (0x0183) +#define TABLA_A_AUX_L_GAIN__POR (0x0000001F) +#define TABLA_A_AUX_L_PA_CONN (0x0184) +#define TABLA_A_AUX_L_PA_CONN__POR (0x00000000) +#define TABLA_A_AUX_L_PA_CONN_INV (0x0185) +#define TABLA_A_AUX_L_PA_CONN_INV__POR (0x00000000) +#define TABLA_A_AUX_R_EN (0x0186) +#define TABLA_A_AUX_R_EN__POR (0x00000000) +#define TABLA_A_AUX_R_GAIN (0x0187) +#define TABLA_A_AUX_R_GAIN__POR (0x0000001F) +#define TABLA_A_AUX_R_PA_CONN (0x0188) +#define TABLA_A_AUX_R_PA_CONN__POR (0x00000000) +#define TABLA_A_AUX_R_PA_CONN_INV (0x0189) +#define TABLA_A_AUX_R_PA_CONN_INV__POR (0x00000000) +#define TABLA_A_CP_EN (0x0192) +#define TABLA_A_CP_EN__POR (0x000000E6) +#define TABLA_A_CP_CLK (0x0193) +#define TABLA_A_CP_CLK__POR (0x00000029) +#define TABLA_A_CP_STATIC (0x0194) +#define TABLA_A_CP_STATIC__POR (0x00000010) +#define TABLA_A_CP_DCC1 (0x0195) +#define TABLA_A_CP_DCC1__POR (0x00000052) +#define TABLA_A_CP_DCC3 (0x0196) +#define TABLA_A_CP_DCC3__POR (0x00000001) +#define TABLA_A_CP_ATEST (0x0197) +#define TABLA_A_CP_ATEST__POR (0x00000000) +#define TABLA_A_CP_DTEST (0x0198) +#define TABLA_A_CP_DTEST__POR (0x00000000) +#define TABLA_A_RX_COM_TIMER_DIV (0x019E) +#define TABLA_A_RX_COM_TIMER_DIV__POR (0x000000E8) +#define TABLA_A_RX_COM_OCP_CTL (0x019F) +#define TABLA_A_RX_COM_OCP_CTL__POR (0x0000001F) +#define TABLA_A_RX_COM_OCP_COUNT (0x01A0) +#define TABLA_A_RX_COM_OCP_COUNT__POR (0x00000077) +#define TABLA_A_RX_COM_DAC_CTL (0x01A1) +#define TABLA_A_RX_COM_DAC_CTL__POR (0x00000000) +#define TABLA_A_RX_COM_BIAS (0x01A2) +#define TABLA_A_RX_COM_BIAS__POR (0x00000000) +#define TABLA_A_RX_HPH_BIAS_PA (0x01A6) +#define TABLA_A_RX_HPH_BIAS_PA__POR (0x000000AA) +#define TABLA_A_RX_HPH_BIAS_LDO (0x01A7) +#define TABLA_A_RX_HPH_BIAS_LDO__POR (0x00000086) +#define TABLA_A_RX_HPH_BIAS_CNP (0x01A8) +#define TABLA_A_RX_HPH_BIAS_CNP__POR (0x0000008A) +#define TABLA_A_RX_HPH_BIAS_WG (0x01A9) +#define TABLA_A_RX_HPH_BIAS_WG__POR (0x00000060) +#define TABLA_A_RX_HPH_OCP_CTL (0x01AA) +#define TABLA_A_RX_HPH_OCP_CTL__POR (0x000000E8) +#define TABLA_A_RX_HPH_CNP_EN (0x01AB) +#define TABLA_A_RX_HPH_CNP_EN__POR (0x00000080) +#define TABLA_A_RX_HPH_CNP_WG_CTL (0x01AC) +#define TABLA_A_RX_HPH_CNP_WG_CTL__POR (0x000000DC) +#define TABLA_A_RX_HPH_CNP_WG_TIME (0x01AD) +#define TABLA_A_RX_HPH_CNP_WG_TIME__POR (0x00000028) +#define TABLA_A_RX_HPH_L_GAIN (0x01AE) +#define TABLA_A_RX_HPH_L_GAIN__POR (0x00000000) +#define TABLA_A_RX_HPH_L_TEST (0x01AF) +#define TABLA_A_RX_HPH_L_TEST__POR (0x00000001) +#define TABLA_A_RX_HPH_L_PA_CTL (0x01B0) +#define TABLA_A_RX_HPH_L_PA_CTL__POR (0x00000040) +#define TABLA_A_RX_HPH_L_DAC_CTL (0x01B1) +#define TABLA_A_RX_HPH_L_DAC_CTL__POR (0x00000000) +#define TABLA_A_RX_HPH_L_ATEST (0x01B2) +#define TABLA_A_RX_HPH_L_ATEST__POR (0x00000000) +#define TABLA_A_RX_HPH_L_STATUS (0x01B3) +#define TABLA_A_RX_HPH_L_STATUS__POR (0x00000004) +#define TABLA_A_RX_HPH_R_GAIN (0x01B4) +#define TABLA_A_RX_HPH_R_GAIN__POR (0x00000000) +#define TABLA_A_RX_HPH_R_TEST (0x01B5) +#define TABLA_A_RX_HPH_R_TEST__POR (0x00000001) +#define TABLA_A_RX_HPH_R_PA_CTL (0x01B6) +#define TABLA_A_RX_HPH_R_PA_CTL__POR (0x00000040) +#define TABLA_A_RX_HPH_R_DAC_CTL (0x01B7) +#define TABLA_A_RX_HPH_R_DAC_CTL__POR (0x00000000) +#define TABLA_A_RX_HPH_R_ATEST (0x01B8) +#define TABLA_A_RX_HPH_R_ATEST__POR (0x00000000) +#define TABLA_A_RX_HPH_R_STATUS (0x01B9) +#define TABLA_A_RX_HPH_R_STATUS__POR (0x00000004) +#define TABLA_A_RX_EAR_BIAS_PA (0x01BA) +#define TABLA_A_RX_EAR_BIAS_PA__POR (0x000000AA) +#define TABLA_A_RX_EAR_BIAS_CMBUFF (0x01BB) +#define TABLA_A_RX_EAR_BIAS_CMBUFF__POR (0x000000A0) +#define TABLA_A_RX_EAR_EN (0x01BC) +#define TABLA_A_RX_EAR_EN__POR (0x00000000) +#define TABLA_A_RX_EAR_GAIN (0x01BD) +#define TABLA_A_RX_EAR_GAIN__POR (0x00000008) +#define TABLA_A_RX_EAR_CMBUFF (0x01BE) +#define TABLA_A_RX_EAR_CMBUFF__POR (0x00000000) +#define TABLA_A_RX_EAR_ICTL (0x01BF) +#define TABLA_A_RX_EAR_ICTL__POR (0x00000040) +#define TABLA_A_RX_EAR_CCOMP (0x01C0) +#define TABLA_A_RX_EAR_CCOMP__POR (0x00000008) +#define TABLA_A_RX_EAR_VCM (0x01C1) +#define TABLA_A_RX_EAR_VCM__POR (0x00000000) +#define TABLA_A_RX_EAR_CNP (0x01C2) +#define TABLA_A_RX_EAR_CNP__POR (0x00000080) +#define TABLA_A_RX_EAR_ATEST (0x01C3) +#define TABLA_A_RX_EAR_ATEST__POR (0x00000000) +#define TABLA_A_RX_EAR_STATUS (0x01C5) +#define TABLA_A_RX_EAR_STATUS__POR (0x00000004) +#define TABLA_A_RX_LINE_BIAS_PA (0x01C6) +#define TABLA_A_RX_LINE_BIAS_PA__POR (0x000000AA) +#define TABLA_A_RX_LINE_BIAS_DAC (0x01C7) +#define TABLA_A_RX_LINE_BIAS_DAC__POR (0x000000A0) +#define TABLA_A_RX_LINE_BIAS_CNP (0x01C8) +#define TABLA_A_RX_LINE_BIAS_CNP__POR (0x0000003A) +#define TABLA_A_RX_LINE_COM (0x01C9) +#define TABLA_A_RX_LINE_COM__POR (0x00000000) +#define TABLA_A_RX_LINE_CNP_EN (0x01CA) +#define TABLA_A_RX_LINE_CNP_EN__POR (0x00000080) +#define TABLA_A_RX_LINE_CNP_WG_CTL (0x01CB) +#define TABLA_A_RX_LINE_CNP_WG_CTL__POR (0x0000001C) +#define TABLA_A_RX_LINE_CNP_WG_TIME (0x01CC) +#define TABLA_A_RX_LINE_CNP_WG_TIME__POR (0x00000064) +#define TABLA_A_RX_LINE_1_GAIN (0x01CD) +#define TABLA_A_RX_LINE_1_GAIN__POR (0x00000000) +#define TABLA_A_RX_LINE_1_TEST (0x01CE) +#define TABLA_A_RX_LINE_1_TEST__POR (0x00000000) +#define TABLA_A_RX_LINE_1_DAC_CTL (0x01CF) +#define TABLA_A_RX_LINE_1_DAC_CTL__POR (0x0000000C) +#define TABLA_A_RX_LINE_1_STATUS (0x01D0) +#define TABLA_A_RX_LINE_1_STATUS__POR (0x00000000) +#define TABLA_A_RX_LINE_2_GAIN (0x01D1) +#define TABLA_A_RX_LINE_2_GAIN__POR (0x00000000) +#define TABLA_A_RX_LINE_2_TEST (0x01D2) +#define TABLA_A_RX_LINE_2_TEST__POR (0x00000000) +#define TABLA_A_RX_LINE_2_DAC_CTL (0x01D3) +#define TABLA_A_RX_LINE_2_DAC_CTL__POR (0x0000000C) +#define TABLA_A_RX_LINE_2_STATUS (0x01D4) +#define TABLA_A_RX_LINE_2_STATUS__POR (0x00000000) +#define TABLA_A_RX_LINE_3_GAIN (0x01D5) +#define TABLA_A_RX_LINE_3_GAIN__POR (0x00000000) +#define TABLA_A_RX_LINE_3_TEST (0x01D6) +#define TABLA_A_RX_LINE_3_TEST__POR (0x00000000) +#define TABLA_A_RX_LINE_3_DAC_CTL (0x01D7) +#define TABLA_A_RX_LINE_3_DAC_CTL__POR (0x0000000C) +#define TABLA_A_RX_LINE_3_STATUS (0x01D8) +#define TABLA_A_RX_LINE_3_STATUS__POR (0x00000000) +#define TABLA_A_RX_LINE_4_GAIN (0x01D9) +#define TABLA_A_RX_LINE_4_GAIN__POR (0x00000000) +#define TABLA_A_RX_LINE_4_TEST (0x01DA) +#define TABLA_A_RX_LINE_4_TEST__POR (0x00000000) +#define TABLA_A_RX_LINE_4_DAC_CTL (0x01DB) +#define TABLA_A_RX_LINE_4_DAC_CTL__POR (0x0000000C) +#define TABLA_A_RX_LINE_4_STATUS (0x01DC) +#define TABLA_A_RX_LINE_4_STATUS__POR (0x00000000) +#define TABLA_A_RX_LINE_5_GAIN (0x01DD) +#define TABLA_A_RX_LINE_5_GAIN__POR (0x00000000) +#define TABLA_A_RX_LINE_5_TEST (0x01DE) +#define TABLA_A_RX_LINE_5_TEST__POR (0x00000000) +#define TABLA_A_RX_LINE_5_DAC_CTL (0x01DF) +#define TABLA_A_RX_LINE_5_DAC_CTL__POR (0x0000000C) +#define TABLA_A_RX_LINE_5_STATUS (0x01E0) +#define TABLA_A_RX_LINE_5_STATUS__POR (0x00000000) +#define TABLA_A_RX_LINE_CNP_DBG (0x01EC) +#define TABLA_A_RX_LINE_CNP_DBG__POR (0x00000000) +#define TABLA_A_MBHC_HPH (0x01ED) +#define TABLA_A_MBHC_HPH__POR (0x00000048) +#define TABLA_A_CONFIG_MODE_FREQ (0x01F7) +#define TABLA_A_CONFIG_MODE_FREQ__POR (0x00000047) +#define TABLA_A_CONFIG_MODE_TEST (0x01F8) +#define TABLA_A_CONFIG_MODE_TEST__POR (0x0000000A) +#define TABLA_A_CONFIG_MODE_STATUS (0x01F9) +#define TABLA_A_CONFIG_MODE_STATUS__POR (0x0000001C) +#define TABLA_A_CONFIG_MODE_TUNER (0x01FA) +#define TABLA_A_CONFIG_MODE_TUNER__POR (0x00000000) +#define TABLA_A_CDC_ANC1_CTL (0x00000200) +#define TABLA_A_CDC_ANC1_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_CTL (0x00000280) +#define TABLA_A_CDC_ANC2_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC1_SHIFT (0x00000201) +#define TABLA_A_CDC_ANC1_SHIFT__POR (0x00000000) +#define TABLA_A_CDC_ANC2_SHIFT (0x00000281) +#define TABLA_A_CDC_ANC2_SHIFT__POR (0x00000000) +#define TABLA_A_CDC_ANC1_FILT1_B1_CTL (0x00000202) +#define TABLA_A_CDC_ANC1_FILT1_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT1_B1_CTL (0x00000282) +#define TABLA_A_CDC_ANC2_FILT1_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC1_FILT1_B2_CTL (0x00000203) +#define TABLA_A_CDC_ANC1_FILT1_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT1_B2_CTL (0x00000283) +#define TABLA_A_CDC_ANC2_FILT1_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC1_FILT1_B3_CTL (0x00000204) +#define TABLA_A_CDC_ANC1_FILT1_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT1_B3_CTL (0x00000284) +#define TABLA_A_CDC_ANC2_FILT1_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC1_FILT1_B4_CTL (0x00000205) +#define TABLA_A_CDC_ANC1_FILT1_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT1_B4_CTL (0x00000285) +#define TABLA_A_CDC_ANC2_FILT1_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC1_FILT2_B1_CTL (0x00000206) +#define TABLA_A_CDC_ANC1_FILT2_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT2_B1_CTL (0x00000286) +#define TABLA_A_CDC_ANC2_FILT2_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC1_FILT2_B2_CTL (0x00000207) +#define TABLA_A_CDC_ANC1_FILT2_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT2_B2_CTL (0x00000287) +#define TABLA_A_CDC_ANC2_FILT2_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC1_FILT2_B3_CTL (0x00000208) +#define TABLA_A_CDC_ANC1_FILT2_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT2_B3_CTL (0x00000288) +#define TABLA_A_CDC_ANC2_FILT2_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC1_SPARE (0x00000209) +#define TABLA_A_CDC_ANC1_SPARE__POR (0x00000000) +#define TABLA_A_CDC_ANC2_SPARE (0x00000289) +#define TABLA_A_CDC_ANC2_SPARE__POR (0x00000000) +#define TABLA_A_CDC_ANC1_FILT3_CTL (0x0000020A) +#define TABLA_A_CDC_ANC1_FILT3_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT3_CTL (0x0000028A) +#define TABLA_A_CDC_ANC2_FILT3_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC1_FILT4_CTL (0x0000020B) +#define TABLA_A_CDC_ANC1_FILT4_CTL__POR (0x00000000) +#define TABLA_A_CDC_ANC2_FILT4_CTL (0x0000028B) +#define TABLA_A_CDC_ANC2_FILT4_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX1_VOL_CTL_TIMER (0x00000220) +#define TABLA_A_CDC_TX1_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX2_VOL_CTL_TIMER (0x00000228) +#define TABLA_A_CDC_TX2_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX3_VOL_CTL_TIMER (0x00000230) +#define TABLA_A_CDC_TX3_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX4_VOL_CTL_TIMER (0x00000238) +#define TABLA_A_CDC_TX4_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX5_VOL_CTL_TIMER (0x00000240) +#define TABLA_A_CDC_TX5_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX6_VOL_CTL_TIMER (0x00000248) +#define TABLA_A_CDC_TX6_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX7_VOL_CTL_TIMER (0x00000250) +#define TABLA_A_CDC_TX7_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX8_VOL_CTL_TIMER (0x00000258) +#define TABLA_A_CDC_TX8_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX9_VOL_CTL_TIMER (0x00000260) +#define TABLA_A_CDC_TX9_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX10_VOL_CTL_TIMER (0x00000268) +#define TABLA_A_CDC_TX10_VOL_CTL_TIMER__POR (0x00000000) +#define TABLA_A_CDC_TX1_VOL_CTL_GAIN (0x00000221) +#define TABLA_A_CDC_TX1_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX2_VOL_CTL_GAIN (0x00000229) +#define TABLA_A_CDC_TX2_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX3_VOL_CTL_GAIN (0x00000231) +#define TABLA_A_CDC_TX3_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX4_VOL_CTL_GAIN (0x00000239) +#define TABLA_A_CDC_TX4_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX5_VOL_CTL_GAIN (0x00000241) +#define TABLA_A_CDC_TX5_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX6_VOL_CTL_GAIN (0x00000249) +#define TABLA_A_CDC_TX6_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX7_VOL_CTL_GAIN (0x00000251) +#define TABLA_A_CDC_TX7_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX8_VOL_CTL_GAIN (0x00000259) +#define TABLA_A_CDC_TX8_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX9_VOL_CTL_GAIN (0x00000261) +#define TABLA_A_CDC_TX9_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX10_VOL_CTL_GAIN (0x00000269) +#define TABLA_A_CDC_TX10_VOL_CTL_GAIN__POR (0x00000000) +#define TABLA_A_CDC_TX1_VOL_CTL_CFG (0x00000222) +#define TABLA_A_CDC_TX1_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX2_VOL_CTL_CFG (0x0000022A) +#define TABLA_A_CDC_TX2_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX3_VOL_CTL_CFG (0x00000232) +#define TABLA_A_CDC_TX3_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX4_VOL_CTL_CFG (0x0000023A) +#define TABLA_A_CDC_TX4_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX5_VOL_CTL_CFG (0x00000242) +#define TABLA_A_CDC_TX5_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX6_VOL_CTL_CFG (0x0000024A) +#define TABLA_A_CDC_TX6_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX7_VOL_CTL_CFG (0x00000252) +#define TABLA_A_CDC_TX7_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX8_VOL_CTL_CFG (0x0000025A) +#define TABLA_A_CDC_TX8_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX9_VOL_CTL_CFG (0x00000262) +#define TABLA_A_CDC_TX9_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX10_VOL_CTL_CFG (0x0000026A) +#define TABLA_A_CDC_TX10_VOL_CTL_CFG__POR (0x00000000) +#define TABLA_A_CDC_TX1_MUX_CTL (0x00000223) +#define TABLA_A_CDC_TX1_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX2_MUX_CTL (0x0000022B) +#define TABLA_A_CDC_TX2_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX3_MUX_CTL (0x00000233) +#define TABLA_A_CDC_TX3_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX4_MUX_CTL (0x0000023B) +#define TABLA_A_CDC_TX4_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX5_MUX_CTL (0x00000243) +#define TABLA_A_CDC_TX5_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX6_MUX_CTL (0x0000024B) +#define TABLA_A_CDC_TX6_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX7_MUX_CTL (0x00000253) +#define TABLA_A_CDC_TX7_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX8_MUX_CTL (0x0000025B) +#define TABLA_A_CDC_TX8_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX9_MUX_CTL (0x00000263) +#define TABLA_A_CDC_TX9_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX10_MUX_CTL (0x0000026B) +#define TABLA_A_CDC_TX10_MUX_CTL__POR (0x00000008) +#define TABLA_A_CDC_TX1_CLK_FS_CTL (0x00000224) +#define TABLA_A_CDC_TX1_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX2_CLK_FS_CTL (0x0000022C) +#define TABLA_A_CDC_TX2_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX3_CLK_FS_CTL (0x00000234) +#define TABLA_A_CDC_TX3_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX4_CLK_FS_CTL (0x0000023C) +#define TABLA_A_CDC_TX4_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX5_CLK_FS_CTL (0x00000244) +#define TABLA_A_CDC_TX5_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX6_CLK_FS_CTL (0x0000024C) +#define TABLA_A_CDC_TX6_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX7_CLK_FS_CTL (0x00000254) +#define TABLA_A_CDC_TX7_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX8_CLK_FS_CTL (0x0000025C) +#define TABLA_A_CDC_TX8_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX9_CLK_FS_CTL (0x00000264) +#define TABLA_A_CDC_TX9_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX10_CLK_FS_CTL (0x0000026C) +#define TABLA_A_CDC_TX10_CLK_FS_CTL__POR (0x00000003) +#define TABLA_A_CDC_TX1_DMIC_CTL (0x00000225) +#define TABLA_A_CDC_TX1_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX2_DMIC_CTL (0x0000022D) +#define TABLA_A_CDC_TX2_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX3_DMIC_CTL (0x00000235) +#define TABLA_A_CDC_TX3_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX4_DMIC_CTL (0x0000023D) +#define TABLA_A_CDC_TX4_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX5_DMIC_CTL (0x00000245) +#define TABLA_A_CDC_TX5_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX6_DMIC_CTL (0x0000024D) +#define TABLA_A_CDC_TX6_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX7_DMIC_CTL (0x00000255) +#define TABLA_A_CDC_TX7_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX8_DMIC_CTL (0x0000025D) +#define TABLA_A_CDC_TX8_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX9_DMIC_CTL (0x00000265) +#define TABLA_A_CDC_TX9_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_TX10_DMIC_CTL (0x0000026D) +#define TABLA_A_CDC_TX10_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_SRC1_PDA_CFG (0x000002A0) +#define TABLA_A_CDC_SRC1_PDA_CFG__POR (0x00000000) +#define TABLA_A_CDC_SRC2_PDA_CFG (0x000002A8) +#define TABLA_A_CDC_SRC2_PDA_CFG__POR (0x00000000) +#define TABLA_A_CDC_SRC1_FS_CTL (0x000002A1) +#define TABLA_A_CDC_SRC1_FS_CTL__POR (0x0000001b) +#define TABLA_A_CDC_SRC2_FS_CTL (0x000002A9) +#define TABLA_A_CDC_SRC2_FS_CTL__POR (0x0000001b) +#define TABLA_A_CDC_RX1_B1_CTL (0x000002B0) +#define TABLA_A_CDC_RX1_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX2_B1_CTL (0x000002B8) +#define TABLA_A_CDC_RX2_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX3_B1_CTL (0x000002C0) +#define TABLA_A_CDC_RX3_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX4_B1_CTL (0x000002C8) +#define TABLA_A_CDC_RX4_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX5_B1_CTL (0x000002D0) +#define TABLA_A_CDC_RX5_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX6_B1_CTL (0x000002D8) +#define TABLA_A_CDC_RX6_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX7_B1_CTL (0x000002E0) +#define TABLA_A_CDC_RX7_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX1_B2_CTL (0x000002B1) +#define TABLA_A_CDC_RX1_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX2_B2_CTL (0x000002B9) +#define TABLA_A_CDC_RX2_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX3_B2_CTL (0x000002C1) +#define TABLA_A_CDC_RX3_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX4_B2_CTL (0x000002C9) +#define TABLA_A_CDC_RX4_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX5_B2_CTL (0x000002D1) +#define TABLA_A_CDC_RX5_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX6_B2_CTL (0x000002D9) +#define TABLA_A_CDC_RX6_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX7_B2_CTL (0x000002E1) +#define TABLA_A_CDC_RX7_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX1_B3_CTL (0x000002B2) +#define TABLA_A_CDC_RX1_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX2_B3_CTL (0x000002BA) +#define TABLA_A_CDC_RX2_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX3_B3_CTL (0x000002C2) +#define TABLA_A_CDC_RX3_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX4_B3_CTL (0x000002CA) +#define TABLA_A_CDC_RX4_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX5_B3_CTL (0x000002D2) +#define TABLA_A_CDC_RX5_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX6_B3_CTL (0x000002DA) +#define TABLA_A_CDC_RX6_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX7_B3_CTL (0x000002E2) +#define TABLA_A_CDC_RX7_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX1_B4_CTL (0x000002B3) +#define TABLA_A_CDC_RX1_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX2_B4_CTL (0x000002BB) +#define TABLA_A_CDC_RX2_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX3_B4_CTL (0x000002C3) +#define TABLA_A_CDC_RX3_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX4_B4_CTL (0x000002CB) +#define TABLA_A_CDC_RX4_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX5_B4_CTL (0x000002D3) +#define TABLA_A_CDC_RX5_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX6_B4_CTL (0x000002DB) +#define TABLA_A_CDC_RX6_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX7_B4_CTL (0x000002E3) +#define TABLA_A_CDC_RX7_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX1_B5_CTL (0x000002B4) +#define TABLA_A_CDC_RX1_B5_CTL__POR (0x00000060) +#define TABLA_A_CDC_RX2_B5_CTL (0x000002BC) +#define TABLA_A_CDC_RX2_B5_CTL__POR (0x00000060) +#define TABLA_A_CDC_RX3_B5_CTL (0x000002C4) +#define TABLA_A_CDC_RX3_B5_CTL__POR (0x00000060) +#define TABLA_A_CDC_RX4_B5_CTL (0x000002CC) +#define TABLA_A_CDC_RX4_B5_CTL__POR (0x00000060) +#define TABLA_A_CDC_RX5_B5_CTL (0x000002D4) +#define TABLA_A_CDC_RX5_B5_CTL__POR (0x00000060) +#define TABLA_A_CDC_RX6_B5_CTL (0x000002DC) +#define TABLA_A_CDC_RX6_B5_CTL__POR (0x00000060) +#define TABLA_A_CDC_RX7_B5_CTL (0x000002E4) +#define TABLA_A_CDC_RX7_B5_CTL__POR (0x00000060) +#define TABLA_A_CDC_RX1_B6_CTL (0x000002B5) +#define TABLA_A_CDC_RX1_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX2_B6_CTL (0x000002BD) +#define TABLA_A_CDC_RX2_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX3_B6_CTL (0x000002C5) +#define TABLA_A_CDC_RX3_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX4_B6_CTL (0x000002CD) +#define TABLA_A_CDC_RX4_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX5_B6_CTL (0x000002D5) +#define TABLA_A_CDC_RX5_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX6_B6_CTL (0x000002DD) +#define TABLA_A_CDC_RX6_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX7_B6_CTL (0x000002E5) +#define TABLA_A_CDC_RX7_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX1_VOL_CTL_B1_CTL (0x000002B6) +#define TABLA_A_CDC_RX1_VOL_CTL_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX2_VOL_CTL_B1_CTL (0x000002BE) +#define TABLA_A_CDC_RX2_VOL_CTL_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX3_VOL_CTL_B1_CTL (0x000002C6) +#define TABLA_A_CDC_RX3_VOL_CTL_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX4_VOL_CTL_B1_CTL (0x000002CE) +#define TABLA_A_CDC_RX4_VOL_CTL_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX5_VOL_CTL_B1_CTL (0x000002D6) +#define TABLA_A_CDC_RX5_VOL_CTL_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX6_VOL_CTL_B1_CTL (0x000002DE) +#define TABLA_A_CDC_RX6_VOL_CTL_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX7_VOL_CTL_B1_CTL (0x000002E6) +#define TABLA_A_CDC_RX7_VOL_CTL_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX1_VOL_CTL_B2_CTL (0x000002B7) +#define TABLA_A_CDC_RX1_VOL_CTL_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX2_VOL_CTL_B2_CTL (0x000002BF) +#define TABLA_A_CDC_RX2_VOL_CTL_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX3_VOL_CTL_B2_CTL (0x000002C7) +#define TABLA_A_CDC_RX3_VOL_CTL_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX4_VOL_CTL_B2_CTL (0x000002CF) +#define TABLA_A_CDC_RX4_VOL_CTL_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX5_VOL_CTL_B2_CTL (0x000002D7) +#define TABLA_A_CDC_RX5_VOL_CTL_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX6_VOL_CTL_B2_CTL (0x000002DF) +#define TABLA_A_CDC_RX6_VOL_CTL_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_RX7_VOL_CTL_B2_CTL (0x000002E7) +#define TABLA_A_CDC_RX7_VOL_CTL_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_ANC_RESET_CTL (0x00000300) +#define TABLA_A_CDC_CLK_ANC_RESET_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_RX_RESET_CTL (0x00000301) +#define TABLA_A_CDC_CLK_RX_RESET_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_TX_RESET_B1_CTL (0x00000302) +#define TABLA_A_CDC_CLK_TX_RESET_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_TX_RESET_B2_CTL (0x00000303) +#define TABLA_A_CDC_CLK_TX_RESET_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_DMIC_CTL (0x00000304) +#define TABLA_A_CDC_CLK_DMIC_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_RX_I2S_CTL (0x00000305) +#define TABLA_A_CDC_CLK_RX_I2S_CTL__POR (0x00000003) +#define TABLA_A_CDC_CLK_TX_I2S_CTL (0x00000306) +#define TABLA_A_CDC_CLK_TX_I2S_CTL__POR (0x00000003) +#define TABLA_A_CDC_CLK_OTHR_RESET_CTL (0x00000307) +#define TABLA_A_CDC_CLK_OTHR_RESET_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL (0x00000308) +#define TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_TX_CLK_EN_B2_CTL (0x00000309) +#define TABLA_A_CDC_CLK_TX_CLK_EN_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_OTHR_CTL (0x0000030A) +#define TABLA_A_CDC_CLK_OTHR_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_RDAC_CLK_EN_CTL (0x0000030B) +#define TABLA_A_CDC_CLK_RDAC_CLK_EN_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_ANC_CLK_EN_CTL (0x0000030C) +#define TABLA_A_CDC_CLK_ANC_CLK_EN_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_RX_B1_CTL (0x0000030D) +#define TABLA_A_CDC_CLK_RX_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_RX_B2_CTL (0x0000030E) +#define TABLA_A_CDC_CLK_RX_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_MCLK_CTL (0x0000030F) +#define TABLA_A_CDC_CLK_MCLK_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_PDM_CTL (0x00000310) +#define TABLA_A_CDC_CLK_PDM_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLK_SD_CTL (0x00000311) +#define TABLA_A_CDC_CLK_SD_CTL__POR (0x00000000) +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B1_CTL (0x00000320) +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B1_CTL__POR (0x00000007) +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B2_CTL (0x00000321) +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B2_CTL__POR (0x00000013) +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B3_CTL (0x00000322) +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B3_CTL__POR (0x00000053) +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B4_CTL (0x00000323) +#define TABLA_A_CDC_CLSG_FREQ_THRESH_B4_CTL__POR (0x0000007f) +#define TABLA_A_CDC_CLSG_GAIN_THRESH_CTL (0x00000324) +#define TABLA_A_CDC_CLSG_GAIN_THRESH_CTL__POR (0x00000026) +#define TABLA_A_CDC_CLSG_TIMER_B1_CFG (0x00000325) +#define TABLA_A_CDC_CLSG_TIMER_B1_CFG__POR (0x0000000a) +#define TABLA_A_CDC_CLSG_TIMER_B2_CFG (0x00000326) +#define TABLA_A_CDC_CLSG_TIMER_B2_CFG__POR (0x00000000) +#define TABLA_A_CDC_CLSG_CTL (0x00000327) +#define TABLA_A_CDC_CLSG_CTL__POR (0x00000013) +#define TABLA_A_CDC_IIR1_GAIN_B1_CTL (0x00000340) +#define TABLA_A_CDC_IIR1_GAIN_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B1_CTL (0x00000350) +#define TABLA_A_CDC_IIR2_GAIN_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_GAIN_B2_CTL (0x00000341) +#define TABLA_A_CDC_IIR1_GAIN_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B2_CTL (0x00000351) +#define TABLA_A_CDC_IIR2_GAIN_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_GAIN_B3_CTL (0x00000342) +#define TABLA_A_CDC_IIR1_GAIN_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B3_CTL (0x00000352) +#define TABLA_A_CDC_IIR2_GAIN_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_GAIN_B4_CTL (0x00000343) +#define TABLA_A_CDC_IIR1_GAIN_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B4_CTL (0x00000353) +#define TABLA_A_CDC_IIR2_GAIN_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_GAIN_B5_CTL (0x00000344) +#define TABLA_A_CDC_IIR1_GAIN_B5_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B5_CTL (0x00000354) +#define TABLA_A_CDC_IIR2_GAIN_B5_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_GAIN_B6_CTL (0x00000345) +#define TABLA_A_CDC_IIR1_GAIN_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B6_CTL (0x00000355) +#define TABLA_A_CDC_IIR2_GAIN_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_GAIN_B7_CTL (0x00000346) +#define TABLA_A_CDC_IIR1_GAIN_B7_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B7_CTL (0x00000356) +#define TABLA_A_CDC_IIR2_GAIN_B7_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_GAIN_B8_CTL (0x00000347) +#define TABLA_A_CDC_IIR1_GAIN_B8_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_B8_CTL (0x00000357) +#define TABLA_A_CDC_IIR2_GAIN_B8_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_CTL (0x00000348) +#define TABLA_A_CDC_IIR1_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_CTL (0x00000358) +#define TABLA_A_CDC_IIR2_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_GAIN_TIMER_CTL (0x00000349) +#define TABLA_A_CDC_IIR1_GAIN_TIMER_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_GAIN_TIMER_CTL (0x00000359) +#define TABLA_A_CDC_IIR2_GAIN_TIMER_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_COEF_B1_CTL (0x0000034A) +#define TABLA_A_CDC_IIR1_COEF_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_COEF_B1_CTL (0x0000035A) +#define TABLA_A_CDC_IIR2_COEF_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_COEF_B2_CTL (0x0000034B) +#define TABLA_A_CDC_IIR1_COEF_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_COEF_B2_CTL (0x0000035B) +#define TABLA_A_CDC_IIR2_COEF_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_COEF_B3_CTL (0x0000034C) +#define TABLA_A_CDC_IIR1_COEF_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_COEF_B3_CTL (0x0000035C) +#define TABLA_A_CDC_IIR2_COEF_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_COEF_B4_CTL (0x0000034D) +#define TABLA_A_CDC_IIR1_COEF_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_COEF_B4_CTL (0x0000035D) +#define TABLA_A_CDC_IIR2_COEF_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR1_COEF_B5_CTL (0x0000034E) +#define TABLA_A_CDC_IIR1_COEF_B5_CTL__POR (0x00000000) +#define TABLA_A_CDC_IIR2_COEF_B5_CTL (0x0000035E) +#define TABLA_A_CDC_IIR2_COEF_B5_CTL__POR (0x00000000) +#define TABLA_A_CDC_TOP_GAIN_UPDATE (0x00000360) +#define TABLA_A_CDC_TOP_GAIN_UPDATE__POR (0x00000000) +#define TABLA_A_CDC_DEBUG_B1_CTL (0x00000368) +#define TABLA_A_CDC_DEBUG_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_DEBUG_B2_CTL (0x00000369) +#define TABLA_A_CDC_DEBUG_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_DEBUG_B3_CTL (0x0000036A) +#define TABLA_A_CDC_DEBUG_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_DEBUG_B4_CTL (0x0000036B) +#define TABLA_A_CDC_DEBUG_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_DEBUG_B5_CTL (0x0000036C) +#define TABLA_A_CDC_DEBUG_B5_CTL__POR (0x00000000) +#define TABLA_A_CDC_DEBUG_B6_CTL (0x0000036D) +#define TABLA_A_CDC_DEBUG_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_COMP1_B1_CTL (0x00000370) +#define TABLA_A_CDC_COMP1_B1_CTL__POR (0x00000030) +#define TABLA_A_CDC_COMP1_B2_CTL (0x00000371) +#define TABLA_A_CDC_COMP1_B2_CTL__POR (0x000000B5) +#define TABLA_A_CDC_COMP1_B3_CTL (0x00000372) +#define TABLA_A_CDC_COMP1_B3_CTL__POR (0x00000028) +#define TABLA_A_CDC_COMP1_B4_CTL (0x00000373) +#define TABLA_A_CDC_COMP1_B4_CTL__POR (0x0000003C) +#define TABLA_A_CDC_COMP1_B5_CTL (0x00000374) +#define TABLA_A_CDC_COMP1_B5_CTL__POR (0x0000001F) +#define TABLA_A_CDC_COMP1_B6_CTL (0x00000375) +#define TABLA_A_CDC_COMP1_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_COMP1_SHUT_DOWN_STATUS (0x00000376) +#define TABLA_A_CDC_COMP1_SHUT_DOWN_STATUS__POR (0x00000000) +#define TABLA_A_CDC_COMP1_FS_CFG (0x00000377) +#define TABLA_A_CDC_COMP1_FS_CFG__POR (0x0000001B) +#define TABLA_A_CDC_COMP2_B1_CTL (0x00000378) +#define TABLA_A_CDC_COMP2_B1_CTL__POR (0x00000030) +#define TABLA_A_CDC_COMP2_B2_CTL (0x00000379) +#define TABLA_A_CDC_COMP2_B2_CTL__POR (0x000000B5) +#define TABLA_A_CDC_COMP2_B3_CTL (0x0000037A) +#define TABLA_A_CDC_COMP2_B3_CTL__POR (0x00000028) +#define TABLA_A_CDC_COMP2_B4_CTL (0x0000037B) +#define TABLA_A_CDC_COMP2_B4_CTL__POR (0x0000003C) +#define TABLA_A_CDC_COMP2_B5_CTL (0x0000037C) +#define TABLA_A_CDC_COMP2_B5_CTL__POR (0x0000001F) +#define TABLA_A_CDC_COMP2_B6_CTL (0x0000037D) +#define TABLA_A_CDC_COMP2_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_COMP2_SHUT_DOWN_STATUS (0x0000037E) +#define TABLA_A_CDC_COMP2_SHUT_DOWN_STATUS__POR (0x00000000) +#define TABLA_A_CDC_COMP2_FS_CFG (0x0000037F) +#define TABLA_A_CDC_COMP2_FS_CFG__POR (0x0000001B) +#define TABLA_A_CDC_CONN_RX1_B1_CTL (0x00000380) +#define TABLA_A_CDC_CONN_RX1_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX1_B2_CTL (0x00000381) +#define TABLA_A_CDC_CONN_RX1_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX1_B3_CTL (0x00000382) +#define TABLA_A_CDC_CONN_RX1_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX2_B1_CTL (0x00000383) +#define TABLA_A_CDC_CONN_RX2_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX2_B2_CTL (0x00000384) +#define TABLA_A_CDC_CONN_RX2_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX2_B3_CTL (0x00000385) +#define TABLA_A_CDC_CONN_RX2_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX3_B1_CTL (0x00000386) +#define TABLA_A_CDC_CONN_RX3_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX3_B2_CTL (0x00000387) +#define TABLA_A_CDC_CONN_RX3_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX3_B3_CTL (0x00000388) +#define TABLA_A_CDC_CONN_RX3_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX4_B1_CTL (0x00000389) +#define TABLA_A_CDC_CONN_RX4_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX4_B2_CTL (0x0000038A) +#define TABLA_A_CDC_CONN_RX4_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX5_B1_CTL (0x0000038B) +#define TABLA_A_CDC_CONN_RX5_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX5_B2_CTL (0x0000038C) +#define TABLA_A_CDC_CONN_RX5_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX6_B1_CTL (0x0000038D) +#define TABLA_A_CDC_CONN_RX6_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX6_B2_CTL (0x0000038E) +#define TABLA_A_CDC_CONN_RX6_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX7_B1_CTL (0x0000038F) +#define TABLA_A_CDC_CONN_RX7_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX7_B2_CTL (0x00000390) +#define TABLA_A_CDC_CONN_RX7_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_ANC_B1_CTL (0x00000391) +#define TABLA_A_CDC_CONN_ANC_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_ANC_B2_CTL (0x00000392) +#define TABLA_A_CDC_CONN_ANC_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_B1_CTL (0x00000393) +#define TABLA_A_CDC_CONN_TX_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_B2_CTL (0x00000394) +#define TABLA_A_CDC_CONN_TX_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_B3_CTL (0x00000395) +#define TABLA_A_CDC_CONN_TX_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_B4_CTL (0x00000396) +#define TABLA_A_CDC_CONN_TX_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_EQ1_B1_CTL (0x00000397) +#define TABLA_A_CDC_CONN_EQ1_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_EQ1_B2_CTL (0x00000398) +#define TABLA_A_CDC_CONN_EQ1_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_EQ1_B3_CTL (0x00000399) +#define TABLA_A_CDC_CONN_EQ1_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_EQ1_B4_CTL (0x0000039A) +#define TABLA_A_CDC_CONN_EQ1_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_EQ2_B1_CTL (0x0000039B) +#define TABLA_A_CDC_CONN_EQ2_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_EQ2_B2_CTL (0x0000039C) +#define TABLA_A_CDC_CONN_EQ2_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_EQ2_B3_CTL (0x0000039D) +#define TABLA_A_CDC_CONN_EQ2_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_EQ2_B4_CTL (0x0000039E) +#define TABLA_A_CDC_CONN_EQ2_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_SRC1_B1_CTL (0x0000039F) +#define TABLA_A_CDC_CONN_SRC1_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_SRC1_B2_CTL (0x000003A0) +#define TABLA_A_CDC_CONN_SRC1_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_SRC2_B1_CTL (0x000003A1) +#define TABLA_A_CDC_CONN_SRC2_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_SRC2_B2_CTL (0x000003A2) +#define TABLA_A_CDC_CONN_SRC2_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B1_CTL (0x000003A3) +#define TABLA_A_CDC_CONN_TX_SB_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B2_CTL (0x000003A4) +#define TABLA_A_CDC_CONN_TX_SB_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B3_CTL (0x000003A5) +#define TABLA_A_CDC_CONN_TX_SB_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B4_CTL (0x000003A6) +#define TABLA_A_CDC_CONN_TX_SB_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B5_CTL (0x000003A7) +#define TABLA_A_CDC_CONN_TX_SB_B5_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B6_CTL (0x000003A8) +#define TABLA_A_CDC_CONN_TX_SB_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B7_CTL (0x000003A9) +#define TABLA_A_CDC_CONN_TX_SB_B7_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B8_CTL (0x000003AA) +#define TABLA_A_CDC_CONN_TX_SB_B8_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B9_CTL (0x000003AB) +#define TABLA_A_CDC_CONN_TX_SB_B9_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B10_CTL (0x000003AC) +#define TABLA_A_CDC_CONN_TX_SB_B10_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_TX_SB_B11_CTL (0x000003AD) +#define TABLA_A_CDC_CONN_TX_SB_B11_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX_SB_B1_CTL (0x000003AE) +#define TABLA_A_CDC_CONN_RX_SB_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_RX_SB_B2_CTL (0x000003AF) +#define TABLA_A_CDC_CONN_RX_SB_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_CLSG_CTL (0x000003B0) +#define TABLA_A_CDC_CONN_CLSG_CTL__POR (0x00000000) +#define TABLA_A_CDC_CONN_SPARE (0x000003B1) +#define TABLA_A_CDC_CONN_SPARE__POR (0x00000000) +#define TABLA_A_CDC_MBHC_EN_CTL (0x000003C0) +#define TABLA_A_CDC_MBHC_EN_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_FEATURE_B1_CFG (0x000003C1) +#define TABLA_A_CDC_MBHC_FEATURE_B1_CFG__POR (0x00000000) +#define TABLA_A_CDC_MBHC_FEATURE_B2_CFG (0x000003C2) +#define TABLA_A_CDC_MBHC_FEATURE_B2_CFG__POR (0x00000006) +#define TABLA_A_CDC_MBHC_TIMER_B1_CTL (0x000003C3) +#define TABLA_A_CDC_MBHC_TIMER_B1_CTL__POR (0x00000003) +#define TABLA_A_CDC_MBHC_TIMER_B2_CTL (0x000003C4) +#define TABLA_A_CDC_MBHC_TIMER_B2_CTL__POR (0x00000009) +#define TABLA_A_CDC_MBHC_TIMER_B3_CTL (0x000003C5) +#define TABLA_A_CDC_MBHC_TIMER_B3_CTL__POR (0x0000001e) +#define TABLA_A_CDC_MBHC_TIMER_B4_CTL (0x000003C6) +#define TABLA_A_CDC_MBHC_TIMER_B4_CTL__POR (0x00000045) +#define TABLA_A_CDC_MBHC_TIMER_B5_CTL (0x000003C7) +#define TABLA_A_CDC_MBHC_TIMER_B5_CTL__POR (0x00000004) +#define TABLA_A_CDC_MBHC_TIMER_B6_CTL (0x000003C8) +#define TABLA_A_CDC_MBHC_TIMER_B6_CTL__POR (0x00000078) +#define TABLA_A_CDC_MBHC_B1_STATUS (0x000003C9) +#define TABLA_A_CDC_MBHC_B1_STATUS__POR (0x00000000) +#define TABLA_A_CDC_MBHC_B2_STATUS (0x000003CA) +#define TABLA_A_CDC_MBHC_B2_STATUS__POR (0x00000000) +#define TABLA_A_CDC_MBHC_B3_STATUS (0x000003CB) +#define TABLA_A_CDC_MBHC_B3_STATUS__POR (0x00000000) +#define TABLA_A_CDC_MBHC_B4_STATUS (0x000003CC) +#define TABLA_A_CDC_MBHC_B4_STATUS__POR (0x00000000) +#define TABLA_A_CDC_MBHC_B5_STATUS (0x000003CD) +#define TABLA_A_CDC_MBHC_B5_STATUS__POR (0x00000000) +#define TABLA_A_CDC_MBHC_B1_CTL (0x000003CE) +#define TABLA_A_CDC_MBHC_B1_CTL__POR (0x000000c0) +#define TABLA_A_CDC_MBHC_B2_CTL (0x000003CF) +#define TABLA_A_CDC_MBHC_B2_CTL__POR (0x0000005d) +#define TABLA_A_CDC_MBHC_VOLT_B1_CTL (0x000003D0) +#define TABLA_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_VOLT_B2_CTL (0x000003D1) +#define TABLA_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_VOLT_B3_CTL (0x000003D2) +#define TABLA_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_VOLT_B4_CTL (0x000003D3) +#define TABLA_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_VOLT_B5_CTL (0x000003D4) +#define TABLA_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_VOLT_B6_CTL (0x000003D5) +#define TABLA_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_VOLT_B7_CTL (0x000003D6) +#define TABLA_A_CDC_MBHC_VOLT_B7_CTL__POR (0x000000ff) +#define TABLA_A_CDC_MBHC_VOLT_B8_CTL (0x000003D7) +#define TABLA_A_CDC_MBHC_VOLT_B8_CTL__POR (0x00000007) +#define TABLA_A_CDC_MBHC_VOLT_B9_CTL (0x000003D8) +#define TABLA_A_CDC_MBHC_VOLT_B9_CTL__POR (0x000000ff) +#define TABLA_A_CDC_MBHC_VOLT_B10_CTL (0x000003D9) +#define TABLA_A_CDC_MBHC_VOLT_B10_CTL__POR (0x0000007f) +#define TABLA_A_CDC_MBHC_VOLT_B11_CTL (0x000003DA) +#define TABLA_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_VOLT_B12_CTL (0x000003DB) +#define TABLA_A_CDC_MBHC_VOLT_B12_CTL__POR (0x00000080) +#define TABLA_A_CDC_MBHC_CLK_CTL (0x000003DC) +#define TABLA_A_CDC_MBHC_CLK_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_INT_CTL (0x000003DD) +#define TABLA_A_CDC_MBHC_INT_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_DEBUG_CTL (0x000003DE) +#define TABLA_A_CDC_MBHC_DEBUG_CTL__POR (0x00000000) +#define TABLA_A_CDC_MBHC_SPARE (0x000003DF) +#define TABLA_A_CDC_MBHC_SPARE__POR (0x00000000) + + +/* SLIMBUS Slave Registers */ +#define TABLA_SLIM_PGD_PORT_INT_EN0 (0x30) +#define TABLA_SLIM_PGD_PORT_INT_STATUS0 (0x34) +#define TABLA_SLIM_PGD_PORT_INT_CLR0 (0x38) +#define TABLA_SLIM_PGD_PORT_INT_SOURCE0 (0x60) + +/* Macros for Packing Register Writes into a U32 */ +#define TABLA_PACKED_REG_SIZE sizeof(u32) + +#define TABLA_CODEC_PACK_ENTRY(reg, mask, val) ((val & 0xff)|\ + ((mask & 0xff) << 8)|((reg & 0xffff) << 16)) + +#define TABLA_CODEC_UNPACK_ENTRY(packed, reg, mask, val) \ + do { \ + ((reg) = ((packed >> 16) & (0xffff))); \ + ((mask) = ((packed >> 8) & (0xff))); \ + ((val) = ((packed) & (0xff))); \ + } while (0); + +#endif diff --git a/original-kernel-headers/linux/mfd/wcd9xxx/wcd9320_registers.h b/original-kernel-headers/linux/mfd/wcd9xxx/wcd9320_registers.h new file mode 100644 index 0000000..9a20397 --- /dev/null +++ b/original-kernel-headers/linux/mfd/wcd9xxx/wcd9320_registers.h @@ -0,0 +1,1354 @@ +/* Copyright (c) 2012, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef WCD9320_REGISTERS_H +#define WCD9320_REGISTERS_H + +#include <linux/mfd/wcd9xxx/wcd9xxx_registers.h> + +#define TAIKO_A_CHIP_CTL WCD9XXX_A_CHIP_CTL +#define TAIKO_A_CHIP_CTL__POR WCD9XXX_A_CHIP_CTL__POR +#define TAIKO_A_CHIP_STATUS WCD9XXX_A_CHIP_STATUS +#define TAIKO_A_CHIP_STATUS__POR WCD9XXX_A_CHIP_STATUS__POR +#define TAIKO_A_CHIP_ID_BYTE_0 WCD9XXX_A_CHIP_ID_BYTE_0 +#define TAIKO_A_CHIP_ID_BYTE_0__POR WCD9XXX_A_CHIP_ID_BYTE_0__POR +#define TAIKO_A_CHIP_ID_BYTE_1 WCD9XXX_A_CHIP_ID_BYTE_1 +#define TAIKO_A_CHIP_ID_BYTE_1__POR WCD9XXX_A_CHIP_ID_BYTE_1__POR +#define TAIKO_A_CHIP_ID_BYTE_2 WCD9XXX_A_CHIP_ID_BYTE_2 +#define TAIKO_A_CHIP_ID_BYTE_2__POR WCD9XXX_A_CHIP_ID_BYTE_2__POR +#define TAIKO_A_CHIP_ID_BYTE_3 WCD9XXX_A_CHIP_ID_BYTE_3 +#define TAIKO_A_CHIP_ID_BYTE_3__POR WCD9XXX_A_CHIP_ID_BYTE_3__POR +#define TAIKO_A_CHIP_VERSION WCD9XXX_A_CHIP_VERSION +#define TAIKO_A_CHIP_VERSION__POR WCD9XXX_A_CHIP_VERSION__POR +#define TAIKO_A_SB_VERSION WCD9XXX_A_SB_VERSION +#define TAIKO_A_SB_VERSION__POR WCD9XXX_A_SB_VERSION__POR +#define TAIKO_A_SLAVE_ID_1 WCD9XXX_A_SLAVE_ID_1 +#define TAIKO_A_SLAVE_ID_1__POR WCD9XXX_A_SLAVE_ID_1__POR +#define TAIKO_A_SLAVE_ID_2 WCD9XXX_A_SLAVE_ID_2 +#define TAIKO_A_SLAVE_ID_2__POR WCD9XXX_A_SLAVE_ID_2__POR +#define TAIKO_A_SLAVE_ID_3 WCD9XXX_A_SLAVE_ID_3 +#define TAIKO_A_SLAVE_ID_3__POR WCD9XXX_A_SLAVE_ID_3__POR +#define TAIKO_A_PIN_CTL_OE0 (0x010) +#define TAIKO_A_PIN_CTL_OE0__POR (0x00) +#define TAIKO_A_PIN_CTL_OE1 (0x011) +#define TAIKO_A_PIN_CTL_OE1__POR (0x00) +#define TAIKO_A_PIN_CTL_DATA0 (0x012) +#define TAIKO_A_PIN_CTL_DATA0__POR (0x00) +#define TAIKO_A_PIN_CTL_DATA1 (0x013) +#define TAIKO_A_PIN_CTL_DATA1__POR (0x00) +#define TAIKO_A_HDRIVE_GENERIC (0x018) +#define TAIKO_A_HDRIVE_GENERIC__POR (0x00) +#define TAIKO_A_HDRIVE_OVERRIDE (0x019) +#define TAIKO_A_HDRIVE_OVERRIDE__POR (0x08) +#define TAIKO_A_ANA_CSR_WAIT_STATE (0x020) +#define TAIKO_A_ANA_CSR_WAIT_STATE__POR (0x44) +#define TAIKO_A_PROCESS_MONITOR_CTL0 (0x040) +#define TAIKO_A_PROCESS_MONITOR_CTL0__POR (0x80) +#define TAIKO_A_PROCESS_MONITOR_CTL1 (0x041) +#define TAIKO_A_PROCESS_MONITOR_CTL1__POR (0x00) +#define TAIKO_A_PROCESS_MONITOR_CTL2 (0x042) +#define TAIKO_A_PROCESS_MONITOR_CTL2__POR (0x00) +#define TAIKO_A_PROCESS_MONITOR_CTL3 (0x043) +#define TAIKO_A_PROCESS_MONITOR_CTL3__POR (0x01) +#define TAIKO_A_QFUSE_CTL (0x048) +#define TAIKO_A_QFUSE_CTL__POR (0x00) +#define TAIKO_A_QFUSE_STATUS (0x049) +#define TAIKO_A_QFUSE_STATUS__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT0 (0x04A) +#define TAIKO_A_QFUSE_DATA_OUT0__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT1 (0x04B) +#define TAIKO_A_QFUSE_DATA_OUT1__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT2 (0x04C) +#define TAIKO_A_QFUSE_DATA_OUT2__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT3 (0x04D) +#define TAIKO_A_QFUSE_DATA_OUT3__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT4 (0x04E) +#define TAIKO_A_QFUSE_DATA_OUT4__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT5 (0x04F) +#define TAIKO_A_QFUSE_DATA_OUT5__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT6 (0x050) +#define TAIKO_A_QFUSE_DATA_OUT6__POR (0x00) +#define TAIKO_A_QFUSE_DATA_OUT7 (0x051) +#define TAIKO_A_QFUSE_DATA_OUT7__POR (0x00) +#define TAIKO_A_CDC_CTL WCD9XXX_A_CDC_CTL +#define TAIKO_A_CDC_CTL__POR WCD9XXX_A_CDC_CTL__POR +#define TAIKO_A_LEAKAGE_CTL WCD9XXX_A_LEAKAGE_CTL +#define TAIKO_A_LEAKAGE_CTL__POR WCD9XXX_A_LEAKAGE_CTL__POR +#define TAIKO_A_INTR_MODE (0x090) +#define TAIKO_A_INTR_MODE__POR (0x00) +#define TAIKO_A_INTR_MASK0 (0x094) +#define TAIKO_A_INTR_MASK0__POR (0xFF) +#define TAIKO_A_INTR_MASK1 (0x095) +#define TAIKO_A_INTR_MASK1__POR (0xFF) +#define TAIKO_A_INTR_MASK2 (0x096) +#define TAIKO_A_INTR_MASK2__POR (0x3F) +#define TAIKO_A_INTR_MASK3 (0x097) +#define TAIKO_A_INTR_MASK3__POR (0x3F) +#define TAIKO_A_INTR_STATUS0 (0x098) +#define TAIKO_A_INTR_STATUS0__POR (0x00) +#define TAIKO_A_INTR_STATUS1 (0x099) +#define TAIKO_A_INTR_STATUS1__POR (0x00) +#define TAIKO_A_INTR_STATUS2 (0x09A) +#define TAIKO_A_INTR_STATUS2__POR (0x00) +#define TAIKO_A_INTR_STATUS3 (0x09B) +#define TAIKO_A_INTR_STATUS3__POR (0x00) +#define TAIKO_A_INTR_CLEAR0 (0x09C) +#define TAIKO_A_INTR_CLEAR0__POR (0x00) +#define TAIKO_A_INTR_CLEAR1 (0x09D) +#define TAIKO_A_INTR_CLEAR1__POR (0x00) +#define TAIKO_A_INTR_CLEAR2 (0x09E) +#define TAIKO_A_INTR_CLEAR2__POR (0x00) +#define TAIKO_A_INTR_CLEAR3 (0x09F) +#define TAIKO_A_INTR_CLEAR3__POR (0x00) +#define TAIKO_A_INTR_LEVEL0 (0x0A0) +#define TAIKO_A_INTR_LEVEL0__POR (0x01) +#define TAIKO_A_INTR_LEVEL1 (0x0A1) +#define TAIKO_A_INTR_LEVEL1__POR (0x00) +#define TAIKO_A_INTR_LEVEL2 (0x0A2) +#define TAIKO_A_INTR_LEVEL2__POR (0x00) +#define TAIKO_A_INTR_LEVEL3 (0x0A3) +#define TAIKO_A_INTR_LEVEL3__POR (0x00) +#define TAIKO_A_INTR_TEST0 (0x0A4) +#define TAIKO_A_INTR_TEST0__POR (0x00) +#define TAIKO_A_INTR_TEST1 (0x0A5) +#define TAIKO_A_INTR_TEST1__POR (0x00) +#define TAIKO_A_INTR_TEST2 (0x0A6) +#define TAIKO_A_INTR_TEST2__POR (0x00) +#define TAIKO_A_INTR_TEST3 (0x0A7) +#define TAIKO_A_INTR_TEST3__POR (0x00) +#define TAIKO_A_INTR_SET0 (0x0A8) +#define TAIKO_A_INTR_SET0__POR (0x00) +#define TAIKO_A_INTR_SET1 (0x0A9) +#define TAIKO_A_INTR_SET1__POR (0x00) +#define TAIKO_A_INTR_SET2 (0x0AA) +#define TAIKO_A_INTR_SET2__POR (0x00) +#define TAIKO_A_INTR_SET3 (0x0AB) +#define TAIKO_A_INTR_SET3__POR (0x00) +#define TAIKO_A_INTR_DESTN0 (0x0AC) +#define TAIKO_A_INTR_DESTN0__POR (0x00) +#define TAIKO_A_INTR_DESTN1 (0x0AD) +#define TAIKO_A_INTR_DESTN1__POR (0x00) +#define TAIKO_A_INTR_DESTN2 (0x0AE) +#define TAIKO_A_INTR_DESTN2__POR (0x00) +#define TAIKO_A_INTR_DESTN3 (0x0AF) +#define TAIKO_A_INTR_DESTN3__POR (0x00) +#define TAIKO_A_CDC_TX_I2S_SCK_MODE (0x0C0) +#define TAIKO_A_CDC_TX_I2S_SCK_MODE__POR (0x00) +#define TAIKO_A_CDC_TX_I2S_WS_MODE (0x0C1) +#define TAIKO_A_CDC_TX_I2S_WS_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_DATA0_MODE (0x0C4) +#define TAIKO_A_CDC_DMIC_DATA0_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_CLK0_MODE (0x0C5) +#define TAIKO_A_CDC_DMIC_CLK0_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_DATA1_MODE (0x0C6) +#define TAIKO_A_CDC_DMIC_DATA1_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_CLK1_MODE (0x0C7) +#define TAIKO_A_CDC_DMIC_CLK1_MODE__POR (0x00) +#define TAIKO_A_CDC_RX_I2S_SCK_MODE (0x0C8) +#define TAIKO_A_CDC_RX_I2S_SCK_MODE__POR (0x00) +#define TAIKO_A_CDC_RX_I2S_WS_MODE (0x0C9) +#define TAIKO_A_CDC_RX_I2S_WS_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_DATA2_MODE (0x0CA) +#define TAIKO_A_CDC_DMIC_DATA2_MODE__POR (0x00) +#define TAIKO_A_CDC_DMIC_CLK2_MODE (0x0CB) +#define TAIKO_A_CDC_DMIC_CLK2_MODE__POR (0x00) +#define TAIKO_A_CDC_INTR1_MODE (0x0CC) +#define TAIKO_A_CDC_INTR1_MODE__POR (0x00) +#define TAIKO_A_CDC_SB_NRZ_SEL_MODE (0x0CD) +#define TAIKO_A_CDC_SB_NRZ_SEL_MODE__POR (0x00) +#define TAIKO_A_CDC_INTR2_MODE (0x0CE) +#define TAIKO_A_CDC_INTR2_MODE__POR (0x00) +#define TAIKO_A_CDC_RF_PA_ON_MODE (0x0CF) +#define TAIKO_A_CDC_RF_PA_ON_MODE__POR (0x00) +#define TAIKO_A_BIAS_REF_CTL (0x100) +#define TAIKO_A_BIAS_REF_CTL__POR (0x1C) +#define TAIKO_A_BIAS_CENTRAL_BG_CTL (0x101) +#define TAIKO_A_BIAS_CENTRAL_BG_CTL__POR (0x50) +#define TAIKO_A_BIAS_PRECHRG_CTL (0x102) +#define TAIKO_A_BIAS_PRECHRG_CTL__POR (0x07) +#define TAIKO_A_BIAS_CURR_CTL_1 (0x103) +#define TAIKO_A_BIAS_CURR_CTL_1__POR (0x52) +#define TAIKO_A_BIAS_CURR_CTL_2 (0x104) +#define TAIKO_A_BIAS_CURR_CTL_2__POR (0x00) +#define TAIKO_A_BIAS_OSC_BG_CTL (0x105) +#define TAIKO_A_BIAS_OSC_BG_CTL__POR (0x16) +#define TAIKO_A_CLK_BUFF_EN1 (0x108) +#define TAIKO_A_CLK_BUFF_EN1__POR (0x04) +#define TAIKO_A_CLK_BUFF_EN2 (0x109) +#define TAIKO_A_CLK_BUFF_EN2__POR (0x02) +#define TAIKO_A_LDO_H_MODE_1 (0x110) +#define TAIKO_A_LDO_H_MODE_1__POR (0x65) +#define TAIKO_A_LDO_H_MODE_2 (0x111) +#define TAIKO_A_LDO_H_MODE_2__POR (0xA8) +#define TAIKO_A_LDO_H_LOOP_CTL (0x112) +#define TAIKO_A_LDO_H_LOOP_CTL__POR (0x6B) +#define TAIKO_A_LDO_H_COMP_1 (0x113) +#define TAIKO_A_LDO_H_COMP_1__POR (0x84) +#define TAIKO_A_LDO_H_COMP_2 (0x114) +#define TAIKO_A_LDO_H_COMP_2__POR (0xE0) +#define TAIKO_A_LDO_H_BIAS_1 (0x115) +#define TAIKO_A_LDO_H_BIAS_1__POR (0x6D) +#define TAIKO_A_LDO_H_BIAS_2 (0x116) +#define TAIKO_A_LDO_H_BIAS_2__POR (0xA5) +#define TAIKO_A_LDO_H_BIAS_3 (0x117) +#define TAIKO_A_LDO_H_BIAS_3__POR (0x60) +#define TAIKO_A_VBAT_CLK (0x118) +#define TAIKO_A_VBAT_CLK__POR (0x03) +#define TAIKO_A_VBAT_LOOP (0x119) +#define TAIKO_A_VBAT_LOOP__POR (0x02) +#define TAIKO_A_VBAT_REF (0x11A) +#define TAIKO_A_VBAT_REF__POR (0x20) +#define TAIKO_A_VBAT_ADC_TEST (0x11B) +#define TAIKO_A_VBAT_ADC_TEST__POR (0x00) +#define TAIKO_A_VBAT_FE (0x11C) +#define TAIKO_A_VBAT_FE__POR (0x48) +#define TAIKO_A_VBAT_BIAS_1 (0x11D) +#define TAIKO_A_VBAT_BIAS_1__POR (0x03) +#define TAIKO_A_VBAT_BIAS_2 (0x11E) +#define TAIKO_A_VBAT_BIAS_2__POR (0x00) +#define TAIKO_A_VBAT_ADC_DATA_MSB (0x11F) +#define TAIKO_A_VBAT_ADC_DATA_MSB__POR (0x00) +#define TAIKO_A_VBAT_ADC_DATA_LSB (0x120) +#define TAIKO_A_VBAT_ADC_DATA_LSB__POR (0x00) +#define TAIKO_A_MICB_CFILT_1_CTL (0x128) +#define TAIKO_A_MICB_CFILT_1_CTL__POR (0x40) +#define TAIKO_A_MICB_CFILT_1_VAL (0x129) +#define TAIKO_A_MICB_CFILT_1_VAL__POR (0x80) +#define TAIKO_A_MICB_CFILT_1_PRECHRG (0x12A) +#define TAIKO_A_MICB_CFILT_1_PRECHRG__POR (0x38) +#define TAIKO_A_MICB_1_CTL (0x12B) +#define TAIKO_A_MICB_1_CTL__POR (0x16) +#define TAIKO_A_MICB_1_INT_RBIAS (0x12C) +#define TAIKO_A_MICB_1_INT_RBIAS__POR (0x24) +#define TAIKO_A_MICB_1_MBHC (0x12D) +#define TAIKO_A_MICB_1_MBHC__POR (0x01) +#define TAIKO_A_MICB_CFILT_2_CTL (0x12E) +#define TAIKO_A_MICB_CFILT_2_CTL__POR (0x40) +#define TAIKO_A_MICB_CFILT_2_VAL (0x12F) +#define TAIKO_A_MICB_CFILT_2_VAL__POR (0x80) +#define TAIKO_A_MICB_CFILT_2_PRECHRG (0x130) +#define TAIKO_A_MICB_CFILT_2_PRECHRG__POR (0x38) +#define TAIKO_A_MICB_2_CTL (0x131) +#define TAIKO_A_MICB_2_CTL__POR (0x16) +#define TAIKO_A_MICB_2_INT_RBIAS (0x132) +#define TAIKO_A_MICB_2_INT_RBIAS__POR (0x24) +#define TAIKO_A_MICB_2_MBHC (0x133) +#define TAIKO_A_MICB_2_MBHC__POR (0x02) +#define TAIKO_A_MICB_CFILT_3_CTL (0x134) +#define TAIKO_A_MICB_CFILT_3_CTL__POR (0x40) +#define TAIKO_A_MICB_CFILT_3_VAL (0x135) +#define TAIKO_A_MICB_CFILT_3_VAL__POR (0x80) +#define TAIKO_A_MICB_CFILT_3_PRECHRG (0x136) +#define TAIKO_A_MICB_CFILT_3_PRECHRG__POR (0x38) +#define TAIKO_A_MICB_3_CTL (0x137) +#define TAIKO_A_MICB_3_CTL__POR (0x16) +#define TAIKO_A_MICB_3_INT_RBIAS (0x138) +#define TAIKO_A_MICB_3_INT_RBIAS__POR (0x24) +#define TAIKO_A_MICB_3_MBHC (0x139) +#define TAIKO_A_MICB_3_MBHC__POR (0x00) +#define TAIKO_A_MICB_4_CTL (0x13D) +#define TAIKO_A_MICB_4_CTL__POR (0x16) +#define TAIKO_A_MICB_4_INT_RBIAS (0x13E) +#define TAIKO_A_MICB_4_INT_RBIAS__POR (0x24) +#define TAIKO_A_MICB_4_MBHC (0x13F) +#define TAIKO_A_MICB_4_MBHC__POR (0x01) +#define TAIKO_A_MBHC_INSERT_DETECT (0x14A) +#define TAIKO_A_MBHC_INSERT_DETECT__POR (0x00) +#define TAIKO_A_MBHC_INSERT_DET_STATUS (0x14B) +#define TAIKO_A_MBHC_INSERT_DET_STATUS__POR (0x00) +#define TAIKO_A_TX_COM_BIAS (0x14C) +#define TAIKO_A_TX_COM_BIAS__POR (0xF0) +#define TAIKO_A_MBHC_SCALING_MUX_1 (0x14E) +#define TAIKO_A_MBHC_SCALING_MUX_1__POR (0x00) +#define TAIKO_A_MBHC_SCALING_MUX_2 (0x14F) +#define TAIKO_A_MBHC_SCALING_MUX_2__POR (0x80) +#define TAIKO_A_MAD_ANA_CTRL (0x150) +#define TAIKO_A_MAD_ANA_CTRL__POR (0xF1) +#define TAIKO_A_TX_SUP_SWITCH_CTRL_1 (0x151) +#define TAIKO_A_TX_SUP_SWITCH_CTRL_1__POR (0x00) +#define TAIKO_A_TX_SUP_SWITCH_CTRL_2 (0x152) +#define TAIKO_A_TX_SUP_SWITCH_CTRL_2__POR (0x80) +#define TAIKO_A_TX_1_2_EN (0x153) +#define TAIKO_A_TX_1_2_EN__POR (0x00) +#define TAIKO_A_TX_1_2_TEST_EN (0x154) +#define TAIKO_A_TX_1_2_TEST_EN__POR (0xCC) +#define TAIKO_A_TX_1_2_ADC_CH1 (0x155) +#define TAIKO_A_TX_1_2_ADC_CH1__POR (0x44) +#define TAIKO_A_TX_1_2_ADC_CH2 (0x156) +#define TAIKO_A_TX_1_2_ADC_CH2__POR (0x44) +#define TAIKO_A_TX_1_2_ATEST_REFCTRL (0x157) +#define TAIKO_A_TX_1_2_ATEST_REFCTRL__POR (0x00) +#define TAIKO_A_TX_1_2_TEST_CTL (0x158) +#define TAIKO_A_TX_1_2_TEST_CTL__POR (0x38) +#define TAIKO_A_TX_1_2_TEST_BLOCK_EN (0x159) +#define TAIKO_A_TX_1_2_TEST_BLOCK_EN__POR (0xFC) +#define TAIKO_A_TX_1_2_TXFE_CLKDIV (0x15A) +#define TAIKO_A_TX_1_2_TXFE_CLKDIV__POR (0x55) +#define TAIKO_A_TX_1_2_SAR_ERR_CH1 (0x15B) +#define TAIKO_A_TX_1_2_SAR_ERR_CH1__POR (0x00) +#define TAIKO_A_TX_1_2_SAR_ERR_CH2 (0x15C) +#define TAIKO_A_TX_1_2_SAR_ERR_CH2__POR (0x00) +#define TAIKO_A_TX_3_4_EN (0x15D) +#define TAIKO_A_TX_3_4_EN__POR (0x00) +#define TAIKO_A_TX_3_4_TEST_EN (0x15E) +#define TAIKO_A_TX_3_4_TEST_EN__POR (0xCC) +#define TAIKO_A_TX_3_4_ADC_CH3 (0x15F) +#define TAIKO_A_TX_3_4_ADC_CH3__POR (0x44) +#define TAIKO_A_TX_3_4_ADC_CH4 (0x160) +#define TAIKO_A_TX_3_4_ADC_CH4__POR (0x44) +#define TAIKO_A_TX_3_4_ATEST_REFCTRL (0x161) +#define TAIKO_A_TX_3_4_ATEST_REFCTRL__POR (0x00) +#define TAIKO_A_TX_3_4_TEST_CTL (0x162) +#define TAIKO_A_TX_3_4_TEST_CTL__POR (0x38) +#define TAIKO_A_TX_3_4_TEST_BLOCK_EN (0x163) +#define TAIKO_A_TX_3_4_TEST_BLOCK_EN__POR (0xFC) +#define TAIKO_A_TX_3_4_TXFE_CKDIV (0x164) +#define TAIKO_A_TX_3_4_TXFE_CKDIV__POR (0x55) +#define TAIKO_A_TX_3_4_SAR_ERR_CH3 (0x165) +#define TAIKO_A_TX_3_4_SAR_ERR_CH3__POR (0x00) +#define TAIKO_A_TX_3_4_SAR_ERR_CH4 (0x166) +#define TAIKO_A_TX_3_4_SAR_ERR_CH4__POR (0x00) +#define TAIKO_A_TX_5_6_EN (0x167) +#define TAIKO_A_TX_5_6_EN__POR (0x11) +#define TAIKO_A_TX_5_6_TEST_EN (0x168) +#define TAIKO_A_TX_5_6_TEST_EN__POR (0xCC) +#define TAIKO_A_TX_5_6_ADC_CH5 (0x169) +#define TAIKO_A_TX_5_6_ADC_CH5__POR (0x44) +#define TAIKO_A_TX_5_6_ADC_CH6 (0x16A) +#define TAIKO_A_TX_5_6_ADC_CH6__POR (0x44) +#define TAIKO_A_TX_5_6_ATEST_REFCTRL (0x16B) +#define TAIKO_A_TX_5_6_ATEST_REFCTRL__POR (0x00) +#define TAIKO_A_TX_5_6_TEST_CTL (0x16C) +#define TAIKO_A_TX_5_6_TEST_CTL__POR (0x38) +#define TAIKO_A_TX_5_6_TEST_BLOCK_EN (0x16D) +#define TAIKO_A_TX_5_6_TEST_BLOCK_EN__POR (0xFC) +#define TAIKO_A_TX_5_6_TXFE_CKDIV (0x16E) +#define TAIKO_A_TX_5_6_TXFE_CKDIV__POR (0x55) +#define TAIKO_A_TX_5_6_SAR_ERR_CH5 (0x16F) +#define TAIKO_A_TX_5_6_SAR_ERR_CH5__POR (0x00) +#define TAIKO_A_TX_5_6_SAR_ERR_CH6 (0x170) +#define TAIKO_A_TX_5_6_SAR_ERR_CH6__POR (0x00) +#define TAIKO_A_TX_7_MBHC_EN (0x171) +#define TAIKO_A_TX_7_MBHC_EN__POR (0x0C) +#define TAIKO_A_TX_7_MBHC_ATEST_REFCTRL (0x172) +#define TAIKO_A_TX_7_MBHC_ATEST_REFCTRL__POR (0x00) +#define TAIKO_A_TX_7_MBHC_ADC (0x173) +#define TAIKO_A_TX_7_MBHC_ADC__POR (0x44) +#define TAIKO_A_TX_7_MBHC_TEST_CTL (0x174) +#define TAIKO_A_TX_7_MBHC_TEST_CTL__POR (0x38) +#define TAIKO_A_TX_7_MBHC_SAR_ERR (0x175) +#define TAIKO_A_TX_7_MBHC_SAR_ERR__POR (0x00) +#define TAIKO_A_TX_7_TXFE_CLKDIV (0x176) +#define TAIKO_A_TX_7_TXFE_CLKDIV__POR (0x0B) +#define TAIKO_A_BUCK_MODE_1 (0x181) +#define TAIKO_A_BUCK_MODE_1__POR (0x21) +#define TAIKO_A_BUCK_MODE_2 (0x182) +#define TAIKO_A_BUCK_MODE_2__POR (0xFF) +#define TAIKO_A_BUCK_MODE_3 (0x183) +#define TAIKO_A_BUCK_MODE_3__POR (0xCC) +#define TAIKO_A_BUCK_MODE_4 (0x184) +#define TAIKO_A_BUCK_MODE_4__POR (0x3A) +#define TAIKO_A_BUCK_MODE_5 (0x185) +#define TAIKO_A_BUCK_MODE_5__POR (0x00) +#define TAIKO_A_BUCK_CTRL_VCL_1 (0x186) +#define TAIKO_A_BUCK_CTRL_VCL_1__POR (0x48) +#define TAIKO_A_BUCK_CTRL_VCL_2 (0x187) +#define TAIKO_A_BUCK_CTRL_VCL_2__POR (0xA3) +#define TAIKO_A_BUCK_CTRL_VCL_3 (0x188) +#define TAIKO_A_BUCK_CTRL_VCL_3__POR (0x82) +#define TAIKO_A_BUCK_CTRL_CCL_1 (0x189) +#define TAIKO_A_BUCK_CTRL_CCL_1__POR (0xAB) +#define TAIKO_A_BUCK_CTRL_CCL_2 (0x18A) +#define TAIKO_A_BUCK_CTRL_CCL_2__POR (0xDC) +#define TAIKO_A_BUCK_CTRL_CCL_3 (0x18B) +#define TAIKO_A_BUCK_CTRL_CCL_3__POR (0x6A) +#define TAIKO_A_BUCK_CTRL_CCL_4 (0x18C) +#define TAIKO_A_BUCK_CTRL_CCL_4__POR (0x58) +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_1 (0x18D) +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_1__POR (0x50) +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_2 (0x18E) +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_2__POR (0x64) +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_3 (0x18F) +#define TAIKO_A_BUCK_CTRL_PWM_DRVR_3__POR (0x77) +#define TAIKO_A_BUCK_TMUX_A_D (0x190) +#define TAIKO_A_BUCK_TMUX_A_D__POR (0x00) +#define TAIKO_A_NCP_BUCKREF (0x191) +#define TAIKO_A_NCP_BUCKREF__POR (0x00) +#define TAIKO_A_NCP_EN (0x192) +#define TAIKO_A_NCP_EN__POR (0xFE) +#define TAIKO_A_NCP_CLK (0x193) +#define TAIKO_A_NCP_CLK__POR (0x94) +#define TAIKO_A_NCP_STATIC (0x194) +#define TAIKO_A_NCP_STATIC__POR (0x28) +#define TAIKO_A_NCP_VTH_LOW (0x195) +#define TAIKO_A_NCP_VTH_LOW__POR (0x88) +#define TAIKO_A_NCP_VTH_HIGH (0x196) +#define TAIKO_A_NCP_VTH_HIGH__POR (0xA0) +#define TAIKO_A_NCP_ATEST (0x197) +#define TAIKO_A_NCP_ATEST__POR (0x00) +#define TAIKO_A_NCP_DTEST (0x198) +#define TAIKO_A_NCP_DTEST__POR (0x00) +#define TAIKO_A_NCP_DLY1 (0x199) +#define TAIKO_A_NCP_DLY1__POR (0x06) +#define TAIKO_A_NCP_DLY2 (0x19A) +#define TAIKO_A_NCP_DLY2__POR (0x06) +#define TAIKO_A_RX_AUX_SW_CTL (0x19B) +#define TAIKO_A_RX_AUX_SW_CTL__POR (0x00) +#define TAIKO_A_RX_PA_AUX_IN_CONN (0x19C) +#define TAIKO_A_RX_PA_AUX_IN_CONN__POR (0x00) +#define TAIKO_A_RX_COM_TIMER_DIV (0x19E) +#define TAIKO_A_RX_COM_TIMER_DIV__POR (0xE8) +#define TAIKO_A_RX_COM_OCP_CTL (0x19F) +#define TAIKO_A_RX_COM_OCP_CTL__POR (0x1F) +#define TAIKO_A_RX_COM_OCP_COUNT (0x1A0) +#define TAIKO_A_RX_COM_OCP_COUNT__POR (0x77) +#define TAIKO_A_RX_COM_DAC_CTL (0x1A1) +#define TAIKO_A_RX_COM_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_COM_BIAS (0x1A2) +#define TAIKO_A_RX_COM_BIAS__POR (0x00) +#define TAIKO_A_RX_HPH_AUTO_CHOP (0x1A4) +#define TAIKO_A_RX_HPH_AUTO_CHOP__POR (0x38) +#define TAIKO_A_RX_HPH_CHOP_CTL (0x1A5) +#define TAIKO_A_RX_HPH_CHOP_CTL__POR (0xB4) +#define TAIKO_A_RX_HPH_BIAS_PA (0x1A6) +#define TAIKO_A_RX_HPH_BIAS_PA__POR (0xAA) +#define TAIKO_A_RX_HPH_BIAS_LDO (0x1A7) +#define TAIKO_A_RX_HPH_BIAS_LDO__POR (0x87) +#define TAIKO_A_RX_HPH_BIAS_CNP (0x1A8) +#define TAIKO_A_RX_HPH_BIAS_CNP__POR (0x8A) +#define TAIKO_A_RX_HPH_BIAS_WG_OCP (0x1A9) +#define TAIKO_A_RX_HPH_BIAS_WG_OCP__POR (0x2A) +#define TAIKO_A_RX_HPH_OCP_CTL (0x1AA) +#define TAIKO_A_RX_HPH_OCP_CTL__POR (0x68) +#define TAIKO_A_RX_HPH_CNP_EN (0x1AB) +#define TAIKO_A_RX_HPH_CNP_EN__POR (0x80) +#define TAIKO_A_RX_HPH_CNP_WG_CTL (0x1AC) +#define TAIKO_A_RX_HPH_CNP_WG_CTL__POR (0xDE) +#define TAIKO_A_RX_HPH_CNP_WG_TIME (0x1AD) +#define TAIKO_A_RX_HPH_CNP_WG_TIME__POR (0x2A) +#define TAIKO_A_RX_HPH_L_GAIN (0x1AE) +#define TAIKO_A_RX_HPH_L_GAIN__POR (0x00) +#define TAIKO_A_RX_HPH_L_TEST (0x1AF) +#define TAIKO_A_RX_HPH_L_TEST__POR (0x00) +#define TAIKO_A_RX_HPH_L_PA_CTL (0x1B0) +#define TAIKO_A_RX_HPH_L_PA_CTL__POR (0x40) +#define TAIKO_A_RX_HPH_L_DAC_CTL (0x1B1) +#define TAIKO_A_RX_HPH_L_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_HPH_L_ATEST (0x1B2) +#define TAIKO_A_RX_HPH_L_ATEST__POR (0x00) +#define TAIKO_A_RX_HPH_L_STATUS (0x1B3) +#define TAIKO_A_RX_HPH_L_STATUS__POR (0x00) +#define TAIKO_A_RX_HPH_R_GAIN (0x1B4) +#define TAIKO_A_RX_HPH_R_GAIN__POR (0x00) +#define TAIKO_A_RX_HPH_R_TEST (0x1B5) +#define TAIKO_A_RX_HPH_R_TEST__POR (0x00) +#define TAIKO_A_RX_HPH_R_PA_CTL (0x1B6) +#define TAIKO_A_RX_HPH_R_PA_CTL__POR (0x40) +#define TAIKO_A_RX_HPH_R_DAC_CTL (0x1B7) +#define TAIKO_A_RX_HPH_R_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_HPH_R_ATEST (0x1B8) +#define TAIKO_A_RX_HPH_R_ATEST__POR (0x00) +#define TAIKO_A_RX_HPH_R_STATUS (0x1B9) +#define TAIKO_A_RX_HPH_R_STATUS__POR (0x00) +#define TAIKO_A_RX_EAR_BIAS_PA (0x1BA) +#define TAIKO_A_RX_EAR_BIAS_PA__POR (0xA6) +#define TAIKO_A_RX_EAR_BIAS_CMBUFF (0x1BB) +#define TAIKO_A_RX_EAR_BIAS_CMBUFF__POR (0xA0) +#define TAIKO_A_RX_EAR_EN (0x1BC) +#define TAIKO_A_RX_EAR_EN__POR (0x00) +#define TAIKO_A_RX_EAR_GAIN (0x1BD) +#define TAIKO_A_RX_EAR_GAIN__POR (0x02) +#define TAIKO_A_RX_EAR_CMBUFF (0x1BE) +#define TAIKO_A_RX_EAR_CMBUFF__POR (0x04) +#define TAIKO_A_RX_EAR_ICTL (0x1BF) +#define TAIKO_A_RX_EAR_ICTL__POR (0x40) +#define TAIKO_A_RX_EAR_CCOMP (0x1C0) +#define TAIKO_A_RX_EAR_CCOMP__POR (0x08) +#define TAIKO_A_RX_EAR_VCM (0x1C1) +#define TAIKO_A_RX_EAR_VCM__POR (0x03) +#define TAIKO_A_RX_EAR_CNP (0x1C2) +#define TAIKO_A_RX_EAR_CNP__POR (0xF2) +#define TAIKO_A_RX_EAR_DAC_CTL_ATEST (0x1C3) +#define TAIKO_A_RX_EAR_DAC_CTL_ATEST__POR (0x00) +#define TAIKO_A_RX_EAR_STATUS (0x1C5) +#define TAIKO_A_RX_EAR_STATUS__POR (0x04) +#define TAIKO_A_RX_LINE_BIAS_PA (0x1C6) +#define TAIKO_A_RX_LINE_BIAS_PA__POR (0xA8) +#define TAIKO_A_RX_BUCK_BIAS1 (0x1C7) +#define TAIKO_A_RX_BUCK_BIAS1__POR (0x42) +#define TAIKO_A_RX_BUCK_BIAS2 (0x1C8) +#define TAIKO_A_RX_BUCK_BIAS2__POR (0x84) +#define TAIKO_A_RX_LINE_COM (0x1C9) +#define TAIKO_A_RX_LINE_COM__POR (0x80) +#define TAIKO_A_RX_LINE_CNP_EN (0x1CA) +#define TAIKO_A_RX_LINE_CNP_EN__POR (0x00) +#define TAIKO_A_RX_LINE_CNP_WG_CTL (0x1CB) +#define TAIKO_A_RX_LINE_CNP_WG_CTL__POR (0x00) +#define TAIKO_A_RX_LINE_CNP_WG_TIME (0x1CC) +#define TAIKO_A_RX_LINE_CNP_WG_TIME__POR (0x04) +#define TAIKO_A_RX_LINE_1_GAIN (0x1CD) +#define TAIKO_A_RX_LINE_1_GAIN__POR (0x00) +#define TAIKO_A_RX_LINE_1_TEST (0x1CE) +#define TAIKO_A_RX_LINE_1_TEST__POR (0x00) +#define TAIKO_A_RX_LINE_1_DAC_CTL (0x1CF) +#define TAIKO_A_RX_LINE_1_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_LINE_1_STATUS (0x1D0) +#define TAIKO_A_RX_LINE_1_STATUS__POR (0x00) +#define TAIKO_A_RX_LINE_2_GAIN (0x1D1) +#define TAIKO_A_RX_LINE_2_GAIN__POR (0x00) +#define TAIKO_A_RX_LINE_2_TEST (0x1D2) +#define TAIKO_A_RX_LINE_2_TEST__POR (0x00) +#define TAIKO_A_RX_LINE_2_DAC_CTL (0x1D3) +#define TAIKO_A_RX_LINE_2_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_LINE_2_STATUS (0x1D4) +#define TAIKO_A_RX_LINE_2_STATUS__POR (0x00) +#define TAIKO_A_RX_LINE_3_GAIN (0x1D5) +#define TAIKO_A_RX_LINE_3_GAIN__POR (0x00) +#define TAIKO_A_RX_LINE_3_TEST (0x1D6) +#define TAIKO_A_RX_LINE_3_TEST__POR (0x00) +#define TAIKO_A_RX_LINE_3_DAC_CTL (0x1D7) +#define TAIKO_A_RX_LINE_3_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_LINE_3_STATUS (0x1D8) +#define TAIKO_A_RX_LINE_3_STATUS__POR (0x00) +#define TAIKO_A_RX_LINE_4_GAIN (0x1D9) +#define TAIKO_A_RX_LINE_4_GAIN__POR (0x00) +#define TAIKO_A_RX_LINE_4_TEST (0x1DA) +#define TAIKO_A_RX_LINE_4_TEST__POR (0x00) +#define TAIKO_A_RX_LINE_4_DAC_CTL (0x1DB) +#define TAIKO_A_RX_LINE_4_DAC_CTL__POR (0x00) +#define TAIKO_A_RX_LINE_4_STATUS (0x1DC) +#define TAIKO_A_RX_LINE_4_STATUS__POR (0x00) +#define TAIKO_A_RX_LINE_CNP_DBG (0x1DD) +#define TAIKO_A_RX_LINE_CNP_DBG__POR (0x00) +#define TAIKO_A_SPKR_DRV_EN (0x1DF) +#define TAIKO_A_SPKR_DRV_EN__POR (0x6F) +#define TAIKO_A_SPKR_DRV_GAIN (0x1E0) +#define TAIKO_A_SPKR_DRV_GAIN__POR (0x00) +#define TAIKO_A_SPKR_DRV_DAC_CTL (0x1E1) +#define TAIKO_A_SPKR_DRV_DAC_CTL__POR (0x04) +#define TAIKO_A_SPKR_DRV_OCP_CTL (0x1E2) +#define TAIKO_A_SPKR_DRV_OCP_CTL__POR (0x98) +#define TAIKO_A_SPKR_DRV_CLIP_DET (0x1E3) +#define TAIKO_A_SPKR_DRV_CLIP_DET__POR (0x48) +#define TAIKO_A_SPKR_DRV_IEC (0x1E4) +#define TAIKO_A_SPKR_DRV_IEC__POR (0x20) +#define TAIKO_A_SPKR_DRV_DBG_DAC (0x1E5) +#define TAIKO_A_SPKR_DRV_DBG_DAC__POR (0x05) +#define TAIKO_A_SPKR_DRV_DBG_PA (0x1E6) +#define TAIKO_A_SPKR_DRV_DBG_PA__POR (0x18) +#define TAIKO_A_SPKR_DRV_DBG_PWRSTG (0x1E7) +#define TAIKO_A_SPKR_DRV_DBG_PWRSTG__POR (0x00) +#define TAIKO_A_SPKR_DRV_BIAS_LDO (0x1E8) +#define TAIKO_A_SPKR_DRV_BIAS_LDO__POR (0x45) +#define TAIKO_A_SPKR_DRV_BIAS_INT (0x1E9) +#define TAIKO_A_SPKR_DRV_BIAS_INT__POR (0xA5) +#define TAIKO_A_SPKR_DRV_BIAS_PA (0x1EA) +#define TAIKO_A_SPKR_DRV_BIAS_PA__POR (0x55) +#define TAIKO_A_SPKR_DRV_STATUS_OCP (0x1EB) +#define TAIKO_A_SPKR_DRV_STATUS_OCP__POR (0x00) +#define TAIKO_A_SPKR_DRV_STATUS_PA (0x1EC) +#define TAIKO_A_SPKR_DRV_STATUS_PA__POR (0x00) +#define TAIKO_A_SPKR_PROT_EN (0x1ED) +#define TAIKO_A_SPKR_PROT_EN__POR (0x00) +#define TAIKO_A_SPKR_PROT_ADC_EN (0x1EE) +#define TAIKO_A_SPKR_PROT_ADC_EN__POR (0x44) +#define TAIKO_A_SPKR_PROT_ISENSE_BIAS (0x1EF) +#define TAIKO_A_SPKR_PROT_ISENSE_BIAS__POR (0x44) +#define TAIKO_A_SPKR_PROT_VSENSE_BIAS (0x1F0) +#define TAIKO_A_SPKR_PROT_VSENSE_BIAS__POR (0x44) +#define TAIKO_A_SPKR_PROT_ADC_ATEST_REFCTRL (0x1F1) +#define TAIKO_A_SPKR_PROT_ADC_ATEST_REFCTRL__POR (0x00) +#define TAIKO_A_SPKR_PROT_ADC_TEST_CTL (0x1F2) +#define TAIKO_A_SPKR_PROT_ADC_TEST_CTL__POR (0x38) +#define TAIKO_A_SPKR_PROT_TEST_BLOCK_EN (0x1F3) +#define TAIKO_A_SPKR_PROT_TEST_BLOCK_EN__POR (0xFC) +#define TAIKO_A_SPKR_PROT_ATEST (0x1F4) +#define TAIKO_A_SPKR_PROT_ATEST__POR (0x00) +#define TAIKO_A_SPKR_PROT_V_SAR_ERR (0x1F5) +#define TAIKO_A_SPKR_PROT_V_SAR_ERR__POR (0x00) +#define TAIKO_A_SPKR_PROT_I_SAR_ERR (0x1F6) +#define TAIKO_A_SPKR_PROT_I_SAR_ERR__POR (0x00) +#define TAIKO_A_SPKR_PROT_LDO_CTRL (0x1F7) +#define TAIKO_A_SPKR_PROT_LDO_CTRL__POR (0x00) +#define TAIKO_A_SPKR_PROT_ISENSE_CTRL (0x1F8) +#define TAIKO_A_SPKR_PROT_ISENSE_CTRL__POR (0x00) +#define TAIKO_A_SPKR_PROT_VSENSE_CTRL (0x1F9) +#define TAIKO_A_SPKR_PROT_VSENSE_CTRL__POR (0x00) +#define TAIKO_A_RC_OSC_FREQ (0x1FA) +#define TAIKO_A_RC_OSC_FREQ__POR (0x46) +#define TAIKO_A_RC_OSC_TEST (0x1FB) +#define TAIKO_A_RC_OSC_TEST__POR (0x0A) +#define TAIKO_A_RC_OSC_STATUS (0x1FC) +#define TAIKO_A_RC_OSC_STATUS__POR (0x18) +#define TAIKO_A_RC_OSC_TUNER (0x1FD) +#define TAIKO_A_RC_OSC_TUNER__POR (0x00) +#define TAIKO_A_MBHC_HPH (0x1FE) +#define TAIKO_A_MBHC_HPH__POR (0x44) +#define TAIKO_A_CDC_ANC1_B1_CTL (0x200) +#define TAIKO_A_CDC_ANC1_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_B1_CTL (0x280) +#define TAIKO_A_CDC_ANC2_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_SHIFT (0x201) +#define TAIKO_A_CDC_ANC1_SHIFT__POR (0x00) +#define TAIKO_A_CDC_ANC2_SHIFT (0x281) +#define TAIKO_A_CDC_ANC2_SHIFT__POR (0x00) +#define TAIKO_A_CDC_ANC1_IIR_B1_CTL (0x202) +#define TAIKO_A_CDC_ANC1_IIR_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_IIR_B1_CTL (0x282) +#define TAIKO_A_CDC_ANC2_IIR_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_IIR_B2_CTL (0x203) +#define TAIKO_A_CDC_ANC1_IIR_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_IIR_B2_CTL (0x283) +#define TAIKO_A_CDC_ANC2_IIR_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_IIR_B3_CTL (0x204) +#define TAIKO_A_CDC_ANC1_IIR_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_IIR_B3_CTL (0x284) +#define TAIKO_A_CDC_ANC2_IIR_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_LPF_B1_CTL (0x206) +#define TAIKO_A_CDC_ANC1_LPF_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_LPF_B1_CTL (0x286) +#define TAIKO_A_CDC_ANC2_LPF_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_LPF_B2_CTL (0x207) +#define TAIKO_A_CDC_ANC1_LPF_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_LPF_B2_CTL (0x287) +#define TAIKO_A_CDC_ANC2_LPF_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_SPARE (0x209) +#define TAIKO_A_CDC_ANC1_SPARE__POR (0x00) +#define TAIKO_A_CDC_ANC2_SPARE (0x289) +#define TAIKO_A_CDC_ANC2_SPARE__POR (0x00) +#define TAIKO_A_CDC_ANC1_SMLPF_CTL (0x20A) +#define TAIKO_A_CDC_ANC1_SMLPF_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_SMLPF_CTL (0x28A) +#define TAIKO_A_CDC_ANC2_SMLPF_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_DCFLT_CTL (0x20B) +#define TAIKO_A_CDC_ANC1_DCFLT_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_DCFLT_CTL (0x28B) +#define TAIKO_A_CDC_ANC2_DCFLT_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_GAIN_CTL (0x20C) +#define TAIKO_A_CDC_ANC1_GAIN_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_GAIN_CTL (0x28C) +#define TAIKO_A_CDC_ANC2_GAIN_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC1_B2_CTL (0x20D) +#define TAIKO_A_CDC_ANC1_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_ANC2_B2_CTL (0x28D) +#define TAIKO_A_CDC_ANC2_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_TX1_VOL_CTL_TIMER (0x220) +#define TAIKO_A_CDC_TX1_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX2_VOL_CTL_TIMER (0x228) +#define TAIKO_A_CDC_TX2_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX3_VOL_CTL_TIMER (0x230) +#define TAIKO_A_CDC_TX3_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX4_VOL_CTL_TIMER (0x238) +#define TAIKO_A_CDC_TX4_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX5_VOL_CTL_TIMER (0x240) +#define TAIKO_A_CDC_TX5_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX6_VOL_CTL_TIMER (0x248) +#define TAIKO_A_CDC_TX6_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX7_VOL_CTL_TIMER (0x250) +#define TAIKO_A_CDC_TX7_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX8_VOL_CTL_TIMER (0x258) +#define TAIKO_A_CDC_TX8_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX9_VOL_CTL_TIMER (0x260) +#define TAIKO_A_CDC_TX9_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX10_VOL_CTL_TIMER (0x268) +#define TAIKO_A_CDC_TX10_VOL_CTL_TIMER__POR (0x00) +#define TAIKO_A_CDC_TX1_VOL_CTL_GAIN (0x221) +#define TAIKO_A_CDC_TX1_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX2_VOL_CTL_GAIN (0x229) +#define TAIKO_A_CDC_TX2_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX3_VOL_CTL_GAIN (0x231) +#define TAIKO_A_CDC_TX3_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX4_VOL_CTL_GAIN (0x239) +#define TAIKO_A_CDC_TX4_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX5_VOL_CTL_GAIN (0x241) +#define TAIKO_A_CDC_TX5_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX6_VOL_CTL_GAIN (0x249) +#define TAIKO_A_CDC_TX6_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX7_VOL_CTL_GAIN (0x251) +#define TAIKO_A_CDC_TX7_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX8_VOL_CTL_GAIN (0x259) +#define TAIKO_A_CDC_TX8_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX9_VOL_CTL_GAIN (0x261) +#define TAIKO_A_CDC_TX9_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX10_VOL_CTL_GAIN (0x269) +#define TAIKO_A_CDC_TX10_VOL_CTL_GAIN__POR (0x00) +#define TAIKO_A_CDC_TX1_VOL_CTL_CFG (0x222) +#define TAIKO_A_CDC_TX1_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX2_VOL_CTL_CFG (0x22A) +#define TAIKO_A_CDC_TX2_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX3_VOL_CTL_CFG (0x232) +#define TAIKO_A_CDC_TX3_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX4_VOL_CTL_CFG (0x23A) +#define TAIKO_A_CDC_TX4_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX5_VOL_CTL_CFG (0x242) +#define TAIKO_A_CDC_TX5_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX6_VOL_CTL_CFG (0x24A) +#define TAIKO_A_CDC_TX6_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX7_VOL_CTL_CFG (0x252) +#define TAIKO_A_CDC_TX7_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX8_VOL_CTL_CFG (0x25A) +#define TAIKO_A_CDC_TX8_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX9_VOL_CTL_CFG (0x262) +#define TAIKO_A_CDC_TX9_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX10_VOL_CTL_CFG (0x26A) +#define TAIKO_A_CDC_TX10_VOL_CTL_CFG__POR (0x00) +#define TAIKO_A_CDC_TX1_MUX_CTL (0x223) +#define TAIKO_A_CDC_TX1_MUX_CTL__POR (0x00) +#define TAIKO_A_CDC_TX2_MUX_CTL (0x22B) +#define TAIKO_A_CDC_TX2_MUX_CTL__POR (0x00) +#define TAIKO_A_CDC_TX3_MUX_CTL (0x233) +#define TAIKO_A_CDC_TX3_MUX_CTL__POR (0x00) +#define TAIKO_A_CDC_TX4_MUX_CTL (0x23B) +#define TAIKO_A_CDC_TX4_MUX_CTL__POR (0x00) +#define TAIKO_A_CDC_TX5_MUX_CTL (0x243) +#define TAIKO_A_CDC_TX5_MUX_CTL__POR (0x00) +#define TAIKO_A_CDC_TX6_MUX_CTL (0x24B) +#define TAIKO_A_CDC_TX6_MUX_CTL__POR (0x00) +#define TAIKO_A_CDC_TX7_MUX_CTL (0x253) +#define TAIKO_A_CDC_TX7_MUX_CTL__POR (0x00) +#define TAIKO_A_CDC_TX8_MUX_CTL (0x25B) +#define TAIKO_A_CDC_TX8_MUX_CTL__POR (0x00) +#define TAIKO_A_CDC_TX9_MUX_CTL (0x263) +#define TAIKO_A_CDC_TX9_MUX_CTL__POR (0x00) +#define TAIKO_A_CDC_TX10_MUX_CTL (0x26B) +#define TAIKO_A_CDC_TX10_MUX_CTL__POR (0x00) +#define TAIKO_A_CDC_TX1_CLK_FS_CTL (0x224) +#define TAIKO_A_CDC_TX1_CLK_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_TX2_CLK_FS_CTL (0x22C) +#define TAIKO_A_CDC_TX2_CLK_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_TX3_CLK_FS_CTL (0x234) +#define TAIKO_A_CDC_TX3_CLK_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_TX4_CLK_FS_CTL (0x23C) +#define TAIKO_A_CDC_TX4_CLK_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_TX5_CLK_FS_CTL (0x244) +#define TAIKO_A_CDC_TX5_CLK_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_TX6_CLK_FS_CTL (0x24C) +#define TAIKO_A_CDC_TX6_CLK_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_TX7_CLK_FS_CTL (0x254) +#define TAIKO_A_CDC_TX7_CLK_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_TX8_CLK_FS_CTL (0x25C) +#define TAIKO_A_CDC_TX8_CLK_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_TX9_CLK_FS_CTL (0x264) +#define TAIKO_A_CDC_TX9_CLK_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_TX10_CLK_FS_CTL (0x26C) +#define TAIKO_A_CDC_TX10_CLK_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_TX1_DMIC_CTL (0x225) +#define TAIKO_A_CDC_TX1_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX2_DMIC_CTL (0x22D) +#define TAIKO_A_CDC_TX2_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX3_DMIC_CTL (0x235) +#define TAIKO_A_CDC_TX3_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX4_DMIC_CTL (0x23D) +#define TAIKO_A_CDC_TX4_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX5_DMIC_CTL (0x245) +#define TAIKO_A_CDC_TX5_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX6_DMIC_CTL (0x24D) +#define TAIKO_A_CDC_TX6_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX7_DMIC_CTL (0x255) +#define TAIKO_A_CDC_TX7_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX8_DMIC_CTL (0x25D) +#define TAIKO_A_CDC_TX8_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX9_DMIC_CTL (0x265) +#define TAIKO_A_CDC_TX9_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_TX10_DMIC_CTL (0x26D) +#define TAIKO_A_CDC_TX10_DMIC_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B1_CTL (0x278) +#define TAIKO_A_CDC_DEBUG_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B2_CTL (0x279) +#define TAIKO_A_CDC_DEBUG_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B3_CTL (0x27A) +#define TAIKO_A_CDC_DEBUG_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B4_CTL (0x27B) +#define TAIKO_A_CDC_DEBUG_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B5_CTL (0x27C) +#define TAIKO_A_CDC_DEBUG_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B6_CTL (0x27D) +#define TAIKO_A_CDC_DEBUG_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_DEBUG_B7_CTL (0x27E) +#define TAIKO_A_CDC_DEBUG_B7_CTL__POR (0x00) +#define TAIKO_A_CDC_SRC1_PDA_CFG (0x2A0) +#define TAIKO_A_CDC_SRC1_PDA_CFG__POR (0x00) +#define TAIKO_A_CDC_SRC2_PDA_CFG (0x2A8) +#define TAIKO_A_CDC_SRC2_PDA_CFG__POR (0x00) +#define TAIKO_A_CDC_SRC1_FS_CTL (0x2A1) +#define TAIKO_A_CDC_SRC1_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_SRC2_FS_CTL (0x2A9) +#define TAIKO_A_CDC_SRC2_FS_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_B1_CTL (0x2B0) +#define TAIKO_A_CDC_RX1_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_B1_CTL (0x2B8) +#define TAIKO_A_CDC_RX2_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_B1_CTL (0x2C0) +#define TAIKO_A_CDC_RX3_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_B1_CTL (0x2C8) +#define TAIKO_A_CDC_RX4_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_B1_CTL (0x2D0) +#define TAIKO_A_CDC_RX5_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_B1_CTL (0x2D8) +#define TAIKO_A_CDC_RX6_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_B1_CTL (0x2E0) +#define TAIKO_A_CDC_RX7_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_B2_CTL (0x2B1) +#define TAIKO_A_CDC_RX1_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_B2_CTL (0x2B9) +#define TAIKO_A_CDC_RX2_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_B2_CTL (0x2C1) +#define TAIKO_A_CDC_RX3_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_B2_CTL (0x2C9) +#define TAIKO_A_CDC_RX4_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_B2_CTL (0x2D1) +#define TAIKO_A_CDC_RX5_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_B2_CTL (0x2D9) +#define TAIKO_A_CDC_RX6_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_B2_CTL (0x2E1) +#define TAIKO_A_CDC_RX7_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_B3_CTL (0x2B2) +#define TAIKO_A_CDC_RX1_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_B3_CTL (0x2BA) +#define TAIKO_A_CDC_RX2_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_B3_CTL (0x2C2) +#define TAIKO_A_CDC_RX3_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_B3_CTL (0x2CA) +#define TAIKO_A_CDC_RX4_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_B3_CTL (0x2D2) +#define TAIKO_A_CDC_RX5_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_B3_CTL (0x2DA) +#define TAIKO_A_CDC_RX6_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_B3_CTL (0x2E2) +#define TAIKO_A_CDC_RX7_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_B4_CTL (0x2B3) +#define TAIKO_A_CDC_RX1_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_B4_CTL (0x2BB) +#define TAIKO_A_CDC_RX2_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_B4_CTL (0x2C3) +#define TAIKO_A_CDC_RX3_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_B4_CTL (0x2CB) +#define TAIKO_A_CDC_RX4_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_B4_CTL (0x2D3) +#define TAIKO_A_CDC_RX5_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_B4_CTL (0x2DB) +#define TAIKO_A_CDC_RX6_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_B4_CTL (0x2E3) +#define TAIKO_A_CDC_RX7_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_B5_CTL (0x2B4) +#define TAIKO_A_CDC_RX1_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_B5_CTL (0x2BC) +#define TAIKO_A_CDC_RX2_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_B5_CTL (0x2C4) +#define TAIKO_A_CDC_RX3_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_B5_CTL (0x2CC) +#define TAIKO_A_CDC_RX4_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_B5_CTL (0x2D4) +#define TAIKO_A_CDC_RX5_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_B5_CTL (0x2DC) +#define TAIKO_A_CDC_RX6_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_B5_CTL (0x2E4) +#define TAIKO_A_CDC_RX7_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_B6_CTL (0x2B5) +#define TAIKO_A_CDC_RX1_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_B6_CTL (0x2BD) +#define TAIKO_A_CDC_RX2_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_B6_CTL (0x2C5) +#define TAIKO_A_CDC_RX3_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_B6_CTL (0x2CD) +#define TAIKO_A_CDC_RX4_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_B6_CTL (0x2D5) +#define TAIKO_A_CDC_RX5_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_B6_CTL (0x2DD) +#define TAIKO_A_CDC_RX6_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_B6_CTL (0x2E5) +#define TAIKO_A_CDC_RX7_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_VOL_CTL_B1_CTL (0x2B6) +#define TAIKO_A_CDC_RX1_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_VOL_CTL_B1_CTL (0x2BE) +#define TAIKO_A_CDC_RX2_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_VOL_CTL_B1_CTL (0x2C6) +#define TAIKO_A_CDC_RX3_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_VOL_CTL_B1_CTL (0x2CE) +#define TAIKO_A_CDC_RX4_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_VOL_CTL_B1_CTL (0x2D6) +#define TAIKO_A_CDC_RX5_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_VOL_CTL_B1_CTL (0x2DE) +#define TAIKO_A_CDC_RX6_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_VOL_CTL_B1_CTL (0x2E6) +#define TAIKO_A_CDC_RX7_VOL_CTL_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_RX1_VOL_CTL_B2_CTL (0x2B7) +#define TAIKO_A_CDC_RX1_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX2_VOL_CTL_B2_CTL (0x2BF) +#define TAIKO_A_CDC_RX2_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX3_VOL_CTL_B2_CTL (0x2C7) +#define TAIKO_A_CDC_RX3_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX4_VOL_CTL_B2_CTL (0x2CF) +#define TAIKO_A_CDC_RX4_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX5_VOL_CTL_B2_CTL (0x2D7) +#define TAIKO_A_CDC_RX5_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX6_VOL_CTL_B2_CTL (0x2DF) +#define TAIKO_A_CDC_RX6_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_RX7_VOL_CTL_B2_CTL (0x2E7) +#define TAIKO_A_CDC_RX7_VOL_CTL_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_VBAT_CFG (0x2E8) +#define TAIKO_A_CDC_VBAT_CFG__POR (0x1A) +#define TAIKO_A_CDC_VBAT_ADC_CAL1 (0x2E9) +#define TAIKO_A_CDC_VBAT_ADC_CAL1__POR (0x00) +#define TAIKO_A_CDC_VBAT_ADC_CAL2 (0x2EA) +#define TAIKO_A_CDC_VBAT_ADC_CAL2__POR (0x00) +#define TAIKO_A_CDC_VBAT_ADC_CAL3 (0x2EB) +#define TAIKO_A_CDC_VBAT_ADC_CAL3__POR (0x04) +#define TAIKO_A_CDC_VBAT_PK_EST1 (0x2EC) +#define TAIKO_A_CDC_VBAT_PK_EST1__POR (0xE0) +#define TAIKO_A_CDC_VBAT_PK_EST2 (0x2ED) +#define TAIKO_A_CDC_VBAT_PK_EST2__POR (0x01) +#define TAIKO_A_CDC_VBAT_PK_EST3 (0x2EE) +#define TAIKO_A_CDC_VBAT_PK_EST3__POR (0x40) +#define TAIKO_A_CDC_VBAT_RF_PROC1 (0x2EF) +#define TAIKO_A_CDC_VBAT_RF_PROC1__POR (0x2A) +#define TAIKO_A_CDC_VBAT_RF_PROC2 (0x2F0) +#define TAIKO_A_CDC_VBAT_RF_PROC2__POR (0x86) +#define TAIKO_A_CDC_VBAT_TAC1 (0x2F1) +#define TAIKO_A_CDC_VBAT_TAC1__POR (0x70) +#define TAIKO_A_CDC_VBAT_TAC2 (0x2F2) +#define TAIKO_A_CDC_VBAT_TAC2__POR (0x18) +#define TAIKO_A_CDC_VBAT_TAC3 (0x2F3) +#define TAIKO_A_CDC_VBAT_TAC3__POR (0x18) +#define TAIKO_A_CDC_VBAT_TAC4 (0x2F4) +#define TAIKO_A_CDC_VBAT_TAC4__POR (0x03) +#define TAIKO_A_CDC_VBAT_GAIN_UPD1 (0x2F5) +#define TAIKO_A_CDC_VBAT_GAIN_UPD1__POR (0x01) +#define TAIKO_A_CDC_VBAT_GAIN_UPD2 (0x2F6) +#define TAIKO_A_CDC_VBAT_GAIN_UPD2__POR (0x00) +#define TAIKO_A_CDC_VBAT_GAIN_UPD3 (0x2F7) +#define TAIKO_A_CDC_VBAT_GAIN_UPD3__POR (0x64) +#define TAIKO_A_CDC_VBAT_GAIN_UPD4 (0x2F8) +#define TAIKO_A_CDC_VBAT_GAIN_UPD4__POR (0x01) +#define TAIKO_A_CDC_VBAT_DEBUG1 (0x2F9) +#define TAIKO_A_CDC_VBAT_DEBUG1__POR (0x00) +#define TAIKO_A_CDC_CLK_ANC_RESET_CTL (0x300) +#define TAIKO_A_CDC_CLK_ANC_RESET_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_RX_RESET_CTL (0x301) +#define TAIKO_A_CDC_CLK_RX_RESET_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_TX_RESET_B1_CTL (0x302) +#define TAIKO_A_CDC_CLK_TX_RESET_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_TX_RESET_B2_CTL (0x303) +#define TAIKO_A_CDC_CLK_TX_RESET_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_DMIC_B1_CTL (0x304) +#define TAIKO_A_CDC_CLK_DMIC_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_DMIC_B2_CTL (0x305) +#define TAIKO_A_CDC_CLK_DMIC_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_RX_I2S_CTL (0x306) +#define TAIKO_A_CDC_CLK_RX_I2S_CTL__POR (0x03) +#define TAIKO_A_CDC_CLK_TX_I2S_CTL (0x307) +#define TAIKO_A_CDC_CLK_TX_I2S_CTL__POR (0x03) +#define TAIKO_A_CDC_CLK_OTHR_RESET_B1_CTL (0x308) +#define TAIKO_A_CDC_CLK_OTHR_RESET_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_OTHR_RESET_B2_CTL (0x309) +#define TAIKO_A_CDC_CLK_OTHR_RESET_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_TX_CLK_EN_B1_CTL (0x30A) +#define TAIKO_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_TX_CLK_EN_B2_CTL (0x30B) +#define TAIKO_A_CDC_CLK_TX_CLK_EN_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_OTHR_CTL (0x30C) +#define TAIKO_A_CDC_CLK_OTHR_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_RDAC_CLK_EN_CTL (0x30D) +#define TAIKO_A_CDC_CLK_RDAC_CLK_EN_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_ANC_CLK_EN_CTL (0x30E) +#define TAIKO_A_CDC_CLK_ANC_CLK_EN_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_RX_B1_CTL (0x30F) +#define TAIKO_A_CDC_CLK_RX_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_RX_B2_CTL (0x310) +#define TAIKO_A_CDC_CLK_RX_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_MCLK_CTL (0x311) +#define TAIKO_A_CDC_CLK_MCLK_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_PDM_CTL (0x312) +#define TAIKO_A_CDC_CLK_PDM_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_SD_CTL (0x313) +#define TAIKO_A_CDC_CLK_SD_CTL__POR (0x00) +#define TAIKO_A_CDC_CLK_POWER_CTL (0x314) +#define TAIKO_A_CDC_CLK_POWER_CTL__POR (0x00) +#define TAIKO_A_CDC_CLSH_B1_CTL (0x320) +#define TAIKO_A_CDC_CLSH_B1_CTL__POR (0xE4) +#define TAIKO_A_CDC_CLSH_B2_CTL (0x321) +#define TAIKO_A_CDC_CLSH_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CLSH_B3_CTL (0x322) +#define TAIKO_A_CDC_CLSH_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CLSH_BUCK_NCP_VARS (0x323) +#define TAIKO_A_CDC_CLSH_BUCK_NCP_VARS__POR (0x00) +#define TAIKO_A_CDC_CLSH_IDLE_HPH_THSD (0x324) +#define TAIKO_A_CDC_CLSH_IDLE_HPH_THSD__POR (0x12) +#define TAIKO_A_CDC_CLSH_IDLE_EAR_THSD (0x325) +#define TAIKO_A_CDC_CLSH_IDLE_EAR_THSD__POR (0x0C) +#define TAIKO_A_CDC_CLSH_FCLKONLY_HPH_THSD (0x326) +#define TAIKO_A_CDC_CLSH_FCLKONLY_HPH_THSD__POR (0x18) +#define TAIKO_A_CDC_CLSH_FCLKONLY_EAR_THSD (0x327) +#define TAIKO_A_CDC_CLSH_FCLKONLY_EAR_THSD__POR (0x23) +#define TAIKO_A_CDC_CLSH_K_ADDR (0x328) +#define TAIKO_A_CDC_CLSH_K_ADDR__POR (0x00) +#define TAIKO_A_CDC_CLSH_K_DATA (0x329) +#define TAIKO_A_CDC_CLSH_K_DATA__POR (0xA4) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_L (0x32A) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_L__POR (0xD7) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_U (0x32B) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_HPH_U__POR (0x05) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_L (0x32C) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_L__POR (0x60) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_U (0x32D) +#define TAIKO_A_CDC_CLSH_I_PA_FACT_EAR_U__POR (0x09) +#define TAIKO_A_CDC_CLSH_V_PA_HD_EAR (0x32E) +#define TAIKO_A_CDC_CLSH_V_PA_HD_EAR__POR (0x00) +#define TAIKO_A_CDC_CLSH_V_PA_HD_HPH (0x32F) +#define TAIKO_A_CDC_CLSH_V_PA_HD_HPH__POR (0x00) +#define TAIKO_A_CDC_CLSH_V_PA_MIN_EAR (0x330) +#define TAIKO_A_CDC_CLSH_V_PA_MIN_EAR__POR (0x00) +#define TAIKO_A_CDC_CLSH_V_PA_MIN_HPH (0x331) +#define TAIKO_A_CDC_CLSH_V_PA_MIN_HPH__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B1_CTL (0x340) +#define TAIKO_A_CDC_IIR1_GAIN_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B1_CTL (0x350) +#define TAIKO_A_CDC_IIR2_GAIN_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B2_CTL (0x341) +#define TAIKO_A_CDC_IIR1_GAIN_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B2_CTL (0x351) +#define TAIKO_A_CDC_IIR2_GAIN_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B3_CTL (0x342) +#define TAIKO_A_CDC_IIR1_GAIN_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B3_CTL (0x352) +#define TAIKO_A_CDC_IIR2_GAIN_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B4_CTL (0x343) +#define TAIKO_A_CDC_IIR1_GAIN_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B4_CTL (0x353) +#define TAIKO_A_CDC_IIR2_GAIN_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B5_CTL (0x344) +#define TAIKO_A_CDC_IIR1_GAIN_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B5_CTL (0x354) +#define TAIKO_A_CDC_IIR2_GAIN_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B6_CTL (0x345) +#define TAIKO_A_CDC_IIR1_GAIN_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B6_CTL (0x355) +#define TAIKO_A_CDC_IIR2_GAIN_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B7_CTL (0x346) +#define TAIKO_A_CDC_IIR1_GAIN_B7_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B7_CTL (0x356) +#define TAIKO_A_CDC_IIR2_GAIN_B7_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_B8_CTL (0x347) +#define TAIKO_A_CDC_IIR1_GAIN_B8_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_B8_CTL (0x357) +#define TAIKO_A_CDC_IIR2_GAIN_B8_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_CTL (0x348) +#define TAIKO_A_CDC_IIR1_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_CTL (0x358) +#define TAIKO_A_CDC_IIR2_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_GAIN_TIMER_CTL (0x349) +#define TAIKO_A_CDC_IIR1_GAIN_TIMER_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_GAIN_TIMER_CTL (0x359) +#define TAIKO_A_CDC_IIR2_GAIN_TIMER_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_COEF_B1_CTL (0x34A) +#define TAIKO_A_CDC_IIR1_COEF_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_COEF_B1_CTL (0x35A) +#define TAIKO_A_CDC_IIR2_COEF_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR1_COEF_B2_CTL (0x34B) +#define TAIKO_A_CDC_IIR1_COEF_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_IIR2_COEF_B2_CTL (0x35B) +#define TAIKO_A_CDC_IIR2_COEF_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_TOP_GAIN_UPDATE (0x360) +#define TAIKO_A_CDC_TOP_GAIN_UPDATE__POR (0x00) +#define TAIKO_A_CDC_COMP0_B1_CTL (0x368) +#define TAIKO_A_CDC_COMP0_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP1_B1_CTL (0x370) +#define TAIKO_A_CDC_COMP1_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP2_B1_CTL (0x378) +#define TAIKO_A_CDC_COMP2_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP0_B2_CTL (0x369) +#define TAIKO_A_CDC_COMP0_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP1_B2_CTL (0x371) +#define TAIKO_A_CDC_COMP1_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP2_B2_CTL (0x379) +#define TAIKO_A_CDC_COMP2_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP0_B3_CTL (0x36A) +#define TAIKO_A_CDC_COMP0_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP1_B3_CTL (0x372) +#define TAIKO_A_CDC_COMP1_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP2_B3_CTL (0x37A) +#define TAIKO_A_CDC_COMP2_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP0_B4_CTL (0x36B) +#define TAIKO_A_CDC_COMP0_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP1_B4_CTL (0x373) +#define TAIKO_A_CDC_COMP1_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP2_B4_CTL (0x37B) +#define TAIKO_A_CDC_COMP2_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP0_B5_CTL (0x36C) +#define TAIKO_A_CDC_COMP0_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP1_B5_CTL (0x374) +#define TAIKO_A_CDC_COMP1_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP2_B5_CTL (0x37C) +#define TAIKO_A_CDC_COMP2_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP0_B6_CTL (0x36D) +#define TAIKO_A_CDC_COMP0_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP1_B6_CTL (0x375) +#define TAIKO_A_CDC_COMP1_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP2_B6_CTL (0x37D) +#define TAIKO_A_CDC_COMP2_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_COMP0_SHUT_DOWN_STATUS (0x36E) +#define TAIKO_A_CDC_COMP0_SHUT_DOWN_STATUS__POR (0x00) +#define TAIKO_A_CDC_COMP1_SHUT_DOWN_STATUS (0x376) +#define TAIKO_A_CDC_COMP1_SHUT_DOWN_STATUS__POR (0x00) +#define TAIKO_A_CDC_COMP2_SHUT_DOWN_STATUS (0x37E) +#define TAIKO_A_CDC_COMP2_SHUT_DOWN_STATUS__POR (0x00) +#define TAIKO_A_CDC_COMP0_FS_CFG (0x36F) +#define TAIKO_A_CDC_COMP0_FS_CFG__POR (0x00) +#define TAIKO_A_CDC_COMP1_FS_CFG (0x377) +#define TAIKO_A_CDC_COMP1_FS_CFG__POR (0x00) +#define TAIKO_A_CDC_COMP2_FS_CFG (0x37F) +#define TAIKO_A_CDC_COMP2_FS_CFG__POR (0x00) +#define TAIKO_A_CDC_CONN_RX1_B1_CTL (0x380) +#define TAIKO_A_CDC_CONN_RX1_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX1_B2_CTL (0x381) +#define TAIKO_A_CDC_CONN_RX1_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX1_B3_CTL (0x382) +#define TAIKO_A_CDC_CONN_RX1_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX2_B1_CTL (0x383) +#define TAIKO_A_CDC_CONN_RX2_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX2_B2_CTL (0x384) +#define TAIKO_A_CDC_CONN_RX2_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX2_B3_CTL (0x385) +#define TAIKO_A_CDC_CONN_RX2_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX3_B1_CTL (0x386) +#define TAIKO_A_CDC_CONN_RX3_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX3_B2_CTL (0x387) +#define TAIKO_A_CDC_CONN_RX3_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX4_B1_CTL (0x388) +#define TAIKO_A_CDC_CONN_RX4_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX4_B2_CTL (0x389) +#define TAIKO_A_CDC_CONN_RX4_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX5_B1_CTL (0x38A) +#define TAIKO_A_CDC_CONN_RX5_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX5_B2_CTL (0x38B) +#define TAIKO_A_CDC_CONN_RX5_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX6_B1_CTL (0x38C) +#define TAIKO_A_CDC_CONN_RX6_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX6_B2_CTL (0x38D) +#define TAIKO_A_CDC_CONN_RX6_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX7_B1_CTL (0x38E) +#define TAIKO_A_CDC_CONN_RX7_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX7_B2_CTL (0x38F) +#define TAIKO_A_CDC_CONN_RX7_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX7_B3_CTL (0x390) +#define TAIKO_A_CDC_CONN_RX7_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_ANC_B1_CTL (0x391) +#define TAIKO_A_CDC_CONN_ANC_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_ANC_B2_CTL (0x392) +#define TAIKO_A_CDC_CONN_ANC_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_B1_CTL (0x393) +#define TAIKO_A_CDC_CONN_TX_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_B2_CTL (0x394) +#define TAIKO_A_CDC_CONN_TX_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_B3_CTL (0x395) +#define TAIKO_A_CDC_CONN_TX_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_B4_CTL (0x396) +#define TAIKO_A_CDC_CONN_TX_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ1_B1_CTL (0x397) +#define TAIKO_A_CDC_CONN_EQ1_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ1_B2_CTL (0x398) +#define TAIKO_A_CDC_CONN_EQ1_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ1_B3_CTL (0x399) +#define TAIKO_A_CDC_CONN_EQ1_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ1_B4_CTL (0x39A) +#define TAIKO_A_CDC_CONN_EQ1_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ2_B1_CTL (0x39B) +#define TAIKO_A_CDC_CONN_EQ2_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ2_B2_CTL (0x39C) +#define TAIKO_A_CDC_CONN_EQ2_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ2_B3_CTL (0x39D) +#define TAIKO_A_CDC_CONN_EQ2_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_EQ2_B4_CTL (0x39E) +#define TAIKO_A_CDC_CONN_EQ2_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_SRC1_B1_CTL (0x39F) +#define TAIKO_A_CDC_CONN_SRC1_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_SRC1_B2_CTL (0x3A0) +#define TAIKO_A_CDC_CONN_SRC1_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_SRC2_B1_CTL (0x3A1) +#define TAIKO_A_CDC_CONN_SRC2_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_SRC2_B2_CTL (0x3A2) +#define TAIKO_A_CDC_CONN_SRC2_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B1_CTL (0x3A3) +#define TAIKO_A_CDC_CONN_TX_SB_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B2_CTL (0x3A4) +#define TAIKO_A_CDC_CONN_TX_SB_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B3_CTL (0x3A5) +#define TAIKO_A_CDC_CONN_TX_SB_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B4_CTL (0x3A6) +#define TAIKO_A_CDC_CONN_TX_SB_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B5_CTL (0x3A7) +#define TAIKO_A_CDC_CONN_TX_SB_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B6_CTL (0x3A8) +#define TAIKO_A_CDC_CONN_TX_SB_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B7_CTL (0x3A9) +#define TAIKO_A_CDC_CONN_TX_SB_B7_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B8_CTL (0x3AA) +#define TAIKO_A_CDC_CONN_TX_SB_B8_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B9_CTL (0x3AB) +#define TAIKO_A_CDC_CONN_TX_SB_B9_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B10_CTL (0x3AC) +#define TAIKO_A_CDC_CONN_TX_SB_B10_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_TX_SB_B11_CTL (0x3AD) +#define TAIKO_A_CDC_CONN_TX_SB_B11_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX_SB_B1_CTL (0x3AE) +#define TAIKO_A_CDC_CONN_RX_SB_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_RX_SB_B2_CTL (0x3AF) +#define TAIKO_A_CDC_CONN_RX_SB_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_CLSH_CTL (0x3B0) +#define TAIKO_A_CDC_CONN_CLSH_CTL__POR (0x00) +#define TAIKO_A_CDC_CONN_MISC (0x3B1) +#define TAIKO_A_CDC_CONN_MISC__POR (0x01) +#define TAIKO_A_CDC_CONN_MAD (0x3B2) +#define TAIKO_A_CDC_CONN_MAD__POR (0x01) +#define TAIKO_A_CDC_MBHC_EN_CTL (0x3C0) +#define TAIKO_A_CDC_MBHC_EN_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_FIR_B1_CFG (0x3C1) +#define TAIKO_A_CDC_MBHC_FIR_B1_CFG__POR (0x00) +#define TAIKO_A_CDC_MBHC_FIR_B2_CFG (0x3C2) +#define TAIKO_A_CDC_MBHC_FIR_B2_CFG__POR (0x06) +#define TAIKO_A_CDC_MBHC_TIMER_B1_CTL (0x3C3) +#define TAIKO_A_CDC_MBHC_TIMER_B1_CTL__POR (0x03) +#define TAIKO_A_CDC_MBHC_TIMER_B2_CTL (0x3C4) +#define TAIKO_A_CDC_MBHC_TIMER_B2_CTL__POR (0x09) +#define TAIKO_A_CDC_MBHC_TIMER_B3_CTL (0x3C5) +#define TAIKO_A_CDC_MBHC_TIMER_B3_CTL__POR (0x1E) +#define TAIKO_A_CDC_MBHC_TIMER_B4_CTL (0x3C6) +#define TAIKO_A_CDC_MBHC_TIMER_B4_CTL__POR (0x45) +#define TAIKO_A_CDC_MBHC_TIMER_B5_CTL (0x3C7) +#define TAIKO_A_CDC_MBHC_TIMER_B5_CTL__POR (0x04) +#define TAIKO_A_CDC_MBHC_TIMER_B6_CTL (0x3C8) +#define TAIKO_A_CDC_MBHC_TIMER_B6_CTL__POR (0x78) +#define TAIKO_A_CDC_MBHC_B1_STATUS (0x3C9) +#define TAIKO_A_CDC_MBHC_B1_STATUS__POR (0x00) +#define TAIKO_A_CDC_MBHC_B2_STATUS (0x3CA) +#define TAIKO_A_CDC_MBHC_B2_STATUS__POR (0x00) +#define TAIKO_A_CDC_MBHC_B3_STATUS (0x3CB) +#define TAIKO_A_CDC_MBHC_B3_STATUS__POR (0x00) +#define TAIKO_A_CDC_MBHC_B4_STATUS (0x3CC) +#define TAIKO_A_CDC_MBHC_B4_STATUS__POR (0x00) +#define TAIKO_A_CDC_MBHC_B5_STATUS (0x3CD) +#define TAIKO_A_CDC_MBHC_B5_STATUS__POR (0x00) +#define TAIKO_A_CDC_MBHC_B1_CTL (0x3CE) +#define TAIKO_A_CDC_MBHC_B1_CTL__POR (0xC0) +#define TAIKO_A_CDC_MBHC_B2_CTL (0x3CF) +#define TAIKO_A_CDC_MBHC_B2_CTL__POR (0x5D) +#define TAIKO_A_CDC_MBHC_VOLT_B1_CTL (0x3D0) +#define TAIKO_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B2_CTL (0x3D1) +#define TAIKO_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B3_CTL (0x3D2) +#define TAIKO_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B4_CTL (0x3D3) +#define TAIKO_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B5_CTL (0x3D4) +#define TAIKO_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B6_CTL (0x3D5) +#define TAIKO_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B7_CTL (0x3D6) +#define TAIKO_A_CDC_MBHC_VOLT_B7_CTL__POR (0xFF) +#define TAIKO_A_CDC_MBHC_VOLT_B8_CTL (0x3D7) +#define TAIKO_A_CDC_MBHC_VOLT_B8_CTL__POR (0x07) +#define TAIKO_A_CDC_MBHC_VOLT_B9_CTL (0x3D8) +#define TAIKO_A_CDC_MBHC_VOLT_B9_CTL__POR (0xFF) +#define TAIKO_A_CDC_MBHC_VOLT_B10_CTL (0x3D9) +#define TAIKO_A_CDC_MBHC_VOLT_B10_CTL__POR (0x7F) +#define TAIKO_A_CDC_MBHC_VOLT_B11_CTL (0x3DA) +#define TAIKO_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_VOLT_B12_CTL (0x3DB) +#define TAIKO_A_CDC_MBHC_VOLT_B12_CTL__POR (0x80) +#define TAIKO_A_CDC_MBHC_CLK_CTL (0x3DC) +#define TAIKO_A_CDC_MBHC_CLK_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_INT_CTL (0x3DD) +#define TAIKO_A_CDC_MBHC_INT_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_DEBUG_CTL (0x3DE) +#define TAIKO_A_CDC_MBHC_DEBUG_CTL__POR (0x00) +#define TAIKO_A_CDC_MBHC_SPARE (0x3DF) +#define TAIKO_A_CDC_MBHC_SPARE__POR (0x00) +#define TAIKO_A_CDC_MAD_MAIN_CTL_1 (0x3E0) +#define TAIKO_A_CDC_MAD_MAIN_CTL_1__POR (0x00) +#define TAIKO_A_CDC_MAD_MAIN_CTL_2 (0x3E1) +#define TAIKO_A_CDC_MAD_MAIN_CTL_2__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_1 (0x3E2) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_1__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_2 (0x3E3) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_2__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_3 (0x3E4) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_3__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_4 (0x3E5) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_4__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_5 (0x3E6) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_5__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_6 (0x3E7) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_6__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_7 (0x3E8) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_7__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_8 (0x3E9) +#define TAIKO_A_CDC_MAD_AUDIO_CTL_8__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_PTR (0x3EA) +#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_PTR__POR (0x00) +#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_VAL (0x3EB) +#define TAIKO_A_CDC_MAD_AUDIO_IIR_CTL_VAL__POR (0x40) +#define TAIKO_A_CDC_MAD_ULTR_CTL_1 (0x3EC) +#define TAIKO_A_CDC_MAD_ULTR_CTL_1__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_2 (0x3ED) +#define TAIKO_A_CDC_MAD_ULTR_CTL_2__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_3 (0x3EE) +#define TAIKO_A_CDC_MAD_ULTR_CTL_3__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_4 (0x3EF) +#define TAIKO_A_CDC_MAD_ULTR_CTL_4__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_5 (0x3F0) +#define TAIKO_A_CDC_MAD_ULTR_CTL_5__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_6 (0x3F1) +#define TAIKO_A_CDC_MAD_ULTR_CTL_6__POR (0x00) +#define TAIKO_A_CDC_MAD_ULTR_CTL_7 (0x3F2) +#define TAIKO_A_CDC_MAD_ULTR_CTL_7__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_1 (0x3F3) +#define TAIKO_A_CDC_MAD_BEACON_CTL_1__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_2 (0x3F4) +#define TAIKO_A_CDC_MAD_BEACON_CTL_2__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_3 (0x3F5) +#define TAIKO_A_CDC_MAD_BEACON_CTL_3__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_4 (0x3F6) +#define TAIKO_A_CDC_MAD_BEACON_CTL_4__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_5 (0x3F7) +#define TAIKO_A_CDC_MAD_BEACON_CTL_5__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_6 (0x3F8) +#define TAIKO_A_CDC_MAD_BEACON_CTL_6__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_7 (0x3F9) +#define TAIKO_A_CDC_MAD_BEACON_CTL_7__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_CTL_8 (0x3FA) +#define TAIKO_A_CDC_MAD_BEACON_CTL_8__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_PTR (0x3FB) +#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_PTR__POR (0x00) +#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_VAL (0x3FC) +#define TAIKO_A_CDC_MAD_BEACON_IIR_CTL_VAL__POR (0x00) + + +/* SLIMBUS Slave Registers */ +#define TAIKO_SLIM_PGD_PORT_INT_EN0 (0x30) +#define TAIKO_SLIM_PGD_PORT_INT_STATUS0 (0x34) +#define TAIKO_SLIM_PGD_PORT_INT_CLR0 (0x38) +#define TAIKO_SLIM_PGD_PORT_INT_SOURCE0 (0x60) + +/* Macros for Packing Register Writes into a U32 */ +#define TAIKO_PACKED_REG_SIZE sizeof(u32) + +#define TAIKO_CODEC_PACK_ENTRY(reg, mask, val) ((val & 0xff)|\ + ((mask & 0xff) << 8)|((reg & 0xffff) << 16)) + +#define TAIKO_CODEC_UNPACK_ENTRY(packed, reg, mask, val) \ + do { \ + ((reg) = ((packed >> 16) & (0xffff))); \ + ((mask) = ((packed >> 8) & (0xff))); \ + ((val) = ((packed) & (0xff))); \ + } while (0); + +#endif diff --git a/original-kernel-headers/linux/mfd/wcd9xxx/wcd9xxx-slimslave.h b/original-kernel-headers/linux/mfd/wcd9xxx/wcd9xxx-slimslave.h new file mode 100644 index 0000000..2b033d0 --- /dev/null +++ b/original-kernel-headers/linux/mfd/wcd9xxx/wcd9xxx-slimslave.h @@ -0,0 +1,121 @@ +/* Copyright (c) 2012, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __WCD9310_SLIMSLAVE_H_ +#define __WCD9310_SLIMSLAVE_H_ + +#include <linux/slimbus/slimbus.h> +#include <linux/mfd/wcd9xxx/core.h> + +/* Channel numbers to be used for each port */ +enum { + SLIM_TX_1 = 128, + SLIM_TX_2 = 129, + SLIM_TX_3 = 130, + SLIM_TX_4 = 131, + SLIM_TX_5 = 132, + SLIM_TX_6 = 133, + SLIM_TX_7 = 134, + SLIM_TX_8 = 135, + SLIM_TX_9 = 136, + SLIM_TX_10 = 137, + SLIM_RX_1 = 138, + SLIM_RX_2 = 139, + SLIM_RX_3 = 140, + SLIM_RX_4 = 141, + SLIM_RX_5 = 142, + SLIM_RX_6 = 143, + SLIM_RX_7 = 144, + SLIM_MAX = 145 +}; + +/* + * client is expected to give port ids in the range of + * 1-10 for pre Taiko Tx ports and 1-16 for Taiko + * 1-7 for pre Taiko Rx ports and 1-16 for Tako, + * we need to add offset for getting the absolute slave + * port id before configuring the HW + */ +#define TABLA_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS 10 +#define TAIKO_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS 16 + +#define SLIM_MAX_TX_PORTS TAIKO_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS + +#define TABLA_SB_PGD_OFFSET_OF_RX_SLAVE_DEV_PORTS \ + TABLA_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS +#define TAIKO_SB_PGD_OFFSET_OF_RX_SLAVE_DEV_PORTS \ + TAIKO_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS + +#define TABLA_SB_PGD_MAX_NUMBER_OF_RX_SLAVE_DEV_PORTS 7 +#define TAIKO_SB_PGD_MAX_NUMBER_OF_RX_SLAVE_DEV_PORTS 13 + +#define SLIM_MAX_RX_PORTS TAIKO_SB_PGD_MAX_NUMBER_OF_RX_SLAVE_DEV_PORTS + +#define TABLA_SB_PGD_RX_PORT_MULTI_CHANNEL_0_START_PORT_ID \ + TABLA_SB_PGD_OFFSET_OF_RX_SLAVE_DEV_PORTS +#define TAIKO_SB_PGD_RX_PORT_MULTI_CHANNEL_0_START_PORT_ID \ + TAIKO_SB_PGD_OFFSET_OF_RX_SLAVE_DEV_PORTS + +#define TABLA_SB_PGD_RX_PORT_MULTI_CHANNEL_0_END_PORT_ID 16 +#define TAIKO_SB_PGD_RX_PORT_MULTI_CHANNEL_0_END_PORT_ID 31 + +#define TABLA_SB_PGD_TX_PORT_MULTI_CHANNEL_1_END_PORT_ID 9 +#define TAIKO_SB_PGD_TX_PORT_MULTI_CHANNEL_1_END_PORT_ID 15 + +/* below details are taken from SLIMBUS slave SWI */ +#define SB_PGD_PORT_BASE 0x000 + +#define SB_PGD_PORT_CFG_BYTE_ADDR(offset, port_num) \ + (SB_PGD_PORT_BASE + offset + (1 * port_num)) + +#define SB_PGD_TX_PORT_MULTI_CHANNEL_0(port_num) \ + (SB_PGD_PORT_BASE + 0x100 + 4*port_num) +#define SB_PGD_TX_PORT_MULTI_CHANNEL_0_START_PORT_ID 0 +#define SB_PGD_TX_PORT_MULTI_CHANNEL_0_END_PORT_ID 7 + +#define SB_PGD_TX_PORT_MULTI_CHANNEL_1(port_num) \ + (SB_PGD_PORT_BASE + 0x101 + 4*port_num) +#define SB_PGD_TX_PORT_MULTI_CHANNEL_1_START_PORT_ID 8 + +#define SB_PGD_RX_PORT_MULTI_CHANNEL_0(offset, port_num) \ + (SB_PGD_PORT_BASE + offset + (4 * port_num)) + +/* slave port water mark level + * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes) + */ +#define SLAVE_PORT_WATER_MARK_VALUE 2 +#define SLAVE_PORT_WATER_MARK_SHIFT 1 +#define SLAVE_PORT_ENABLE 1 +#define SLAVE_PORT_DISABLE 0 + +#define BASE_CH_NUM 128 + + +int wcd9xxx_init_slimslave(struct wcd9xxx *wcd9xxx, u8 wcd9xxx_pgd_la); + +int wcd9xxx_deinit_slimslave(struct wcd9xxx *wcd9xxx); + +int wcd9xxx_cfg_slim_sch_rx(struct wcd9xxx *wcd9xxx, unsigned int *ch_num, + unsigned int tot_ch, unsigned int rate); +int wcd9xxx_cfg_slim_sch_tx(struct wcd9xxx *wcd9xxx, unsigned int *ch_num, + unsigned int tot_ch, unsigned int rate); +int wcd9xxx_close_slim_sch_rx(struct wcd9xxx *wcd9xxx, unsigned int *ch_num, + unsigned int tot_ch); +int wcd9xxx_close_slim_sch_tx(struct wcd9xxx *wcd9xxx, unsigned int *ch_num, + unsigned int tot_ch); +int wcd9xxx_get_channel(struct wcd9xxx *wcd9xxx, + unsigned int *rx_ch, + unsigned int *tx_ch); +int wcd9xxx_get_slave_port(unsigned int ch_num); +int wcd9xxx_disconnect_port(struct wcd9xxx *wcd9xxx, unsigned int *ch_num, + unsigned int tot_ch, unsigned int rx_tx); +#endif /* __WCD9310_SLIMSLAVE_H_ */ diff --git a/original-kernel-headers/linux/mfd/wcd9xxx/wcd9xxx_registers.h b/original-kernel-headers/linux/mfd/wcd9xxx/wcd9xxx_registers.h new file mode 100644 index 0000000..73dda8f --- /dev/null +++ b/original-kernel-headers/linux/mfd/wcd9xxx/wcd9xxx_registers.h @@ -0,0 +1,42 @@ +/* Copyright (c) 2012, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef WCD9XXX_CODEC_DIGITAL_H + +#define WCD9XXX_CODEC_DIGITAL_H + +#define WCD9XXX_A_CHIP_CTL (0x00) +#define WCD9XXX_A_CHIP_CTL__POR (0x00000000) +#define WCD9XXX_A_CHIP_STATUS (0x01) +#define WCD9XXX_A_CHIP_STATUS__POR (0x00000000) +#define WCD9XXX_A_CHIP_ID_BYTE_0 (0x04) +#define WCD9XXX_A_CHIP_ID_BYTE_0__POR (0x00000000) +#define WCD9XXX_A_CHIP_ID_BYTE_1 (0x05) +#define WCD9XXX_A_CHIP_ID_BYTE_1__POR (0x00000000) +#define WCD9XXX_A_CHIP_ID_BYTE_2 (0x06) +#define WCD9XXX_A_CHIP_ID_BYTE_2__POR (0x00000000) +#define WCD9XXX_A_CHIP_ID_BYTE_3 (0x07) +#define WCD9XXX_A_CHIP_ID_BYTE_3__POR (0x00000001) +#define WCD9XXX_A_CHIP_VERSION (0x08) +#define WCD9XXX_A_CHIP_VERSION__POR (0x00000020) +#define WCD9XXX_A_SB_VERSION (0x09) +#define WCD9XXX_A_SB_VERSION__POR (0x00000010) +#define WCD9XXX_A_SLAVE_ID_1 (0x0C) +#define WCD9XXX_A_SLAVE_ID_1__POR (0x00000077) +#define WCD9XXX_A_SLAVE_ID_2 (0x0D) +#define WCD9XXX_A_SLAVE_ID_2__POR (0x00000066) +#define WCD9XXX_A_SLAVE_ID_3 (0x0E) +#define WCD9XXX_A_SLAVE_ID_3__POR (0x00000055) +#define WCD9XXX_A_CDC_CTL (0x80) +#define WCD9XXX_A_CDC_CTL__POR (0x00000000) +#define WCD9XXX_A_LEAKAGE_CTL (0x88) +#define WCD9XXX_A_LEAKAGE_CTL__POR (0x00000004) +#endif diff --git a/original-kernel-headers/linux/msm_adsp.h b/original-kernel-headers/linux/msm_adsp.h index f6ab29d..ca23ad8 100644 --- a/original-kernel-headers/linux/msm_adsp.h +++ b/original-kernel-headers/linux/msm_adsp.h @@ -1,14 +1,18 @@ -/**************************************************************************** - **************************************************************************** - *** - *** This header was automatically generated from a Linux kernel header - *** of the same name, to make information necessary for userspace to - *** call into the kernel available to libc. It contains only constants, - *** structures, and macros generated from the original header, and thus, - *** contains no copyrightable information. - *** - **************************************************************************** - ****************************************************************************/ +/* include/linux/msm_adsp.h + * + * Copyright (C) 2007 Google, Inc. + * Author: Iliyan Malchev <ibm@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ #ifndef __LINUX_MSM_ADSP_H #define __LINUX_MSM_ADSP_H @@ -17,47 +21,58 @@ #define ADSP_IOCTL_MAGIC 'q' +/* ADSP_IOCTL_WRITE_COMMAND */ struct adsp_command_t { - uint16_t queue; - uint32_t len; - uint8_t *data; + uint16_t queue; + uint32_t len; /* bytes */ + uint8_t *data; }; +/* ADSP_IOCTL_GET_EVENT */ struct adsp_event_t { - uint16_t type; - uint32_t timeout_ms; - uint16_t msg_id; - uint16_t flags; - uint32_t len; - uint8_t *data; + uint16_t type; /* 1 == event (RPC), 0 == message (adsp) */ + uint32_t timeout_ms; /* -1 for infinite, 0 for immediate return */ + uint16_t msg_id; + uint16_t flags; /* 1 == 16--bit event, 0 == 32-bit event */ + uint32_t len; /* size in, number of bytes out */ + uint8_t *data; }; -#define ADSP_IOCTL_ENABLE _IOR(ADSP_IOCTL_MAGIC, 1, unsigned) +#define ADSP_IOCTL_ENABLE \ + _IOR(ADSP_IOCTL_MAGIC, 1, unsigned) -#define ADSP_IOCTL_DISABLE _IOR(ADSP_IOCTL_MAGIC, 2, unsigned) +#define ADSP_IOCTL_DISABLE \ + _IOR(ADSP_IOCTL_MAGIC, 2, unsigned) -#define ADSP_IOCTL_DISABLE_ACK _IOR(ADSP_IOCTL_MAGIC, 3, unsigned) +#define ADSP_IOCTL_DISABLE_ACK \ + _IOR(ADSP_IOCTL_MAGIC, 3, unsigned) -#define ADSP_IOCTL_WRITE_COMMAND _IOR(ADSP_IOCTL_MAGIC, 4, struct adsp_command_t *) +#define ADSP_IOCTL_WRITE_COMMAND \ + _IOR(ADSP_IOCTL_MAGIC, 4, struct adsp_command_t *) -#define ADSP_IOCTL_GET_EVENT _IOWR(ADSP_IOCTL_MAGIC, 5, struct adsp_event_data_t *) +#define ADSP_IOCTL_GET_EVENT \ + _IOWR(ADSP_IOCTL_MAGIC, 5, struct adsp_event_data_t *) -#define ADSP_IOCTL_SET_CLKRATE _IOR(ADSP_IOCTL_MAGIC, 6, unsigned) +#define ADSP_IOCTL_SET_CLKRATE \ + _IOR(ADSP_IOCTL_MAGIC, 6, unsigned) -#define ADSP_IOCTL_DISABLE_EVENT_RSP _IOR(ADSP_IOCTL_MAGIC, 10, unsigned) +#define ADSP_IOCTL_DISABLE_EVENT_RSP \ + _IOR(ADSP_IOCTL_MAGIC, 10, unsigned) -struct adsp_pmem_info { - int fd; - void *vaddr; -}; - -#define ADSP_IOCTL_REGISTER_PMEM _IOW(ADSP_IOCTL_MAGIC, 13, unsigned) +#define ADSP_IOCTL_REGISTER_PMEM \ + _IOW(ADSP_IOCTL_MAGIC, 13, unsigned) -#define ADSP_IOCTL_UNREGISTER_PMEM _IOW(ADSP_IOCTL_MAGIC, 14, unsigned) +#define ADSP_IOCTL_UNREGISTER_PMEM \ + _IOW(ADSP_IOCTL_MAGIC, 14, unsigned) -#define ADSP_IOCTL_ABORT_EVENT_READ _IOW(ADSP_IOCTL_MAGIC, 15, unsigned) +/* Cause any further GET_EVENT ioctls to fail (-ENODEV) + * until the device is closed and reopened. Useful for + * terminating event dispatch threads + */ +#define ADSP_IOCTL_ABORT_EVENT_READ \ + _IOW(ADSP_IOCTL_MAGIC, 15, unsigned) -#define ADSP_IOCTL_LINK_TASK _IOW(ADSP_IOCTL_MAGIC, 16, unsigned) +#define ADSP_IOCTL_LINK_TASK \ + _IOW(ADSP_IOCTL_MAGIC, 16, unsigned) #endif - diff --git a/original-kernel-headers/linux/msm_audio.h b/original-kernel-headers/linux/msm_audio.h index f2a39e4..04d4e5b 100644 --- a/original-kernel-headers/linux/msm_audio.h +++ b/original-kernel-headers/linux/msm_audio.h @@ -1,7 +1,7 @@ /* include/linux/msm_audio.h * * Copyright (C) 2008 Google, Inc. - * Copyright (c) 2012 Code Aurora Forum. All rights reserved. + * Copyright (c) 2012 The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/original-kernel-headers/linux/msm_audio_aac.h b/original-kernel-headers/linux/msm_audio_aac.h index 620e5ab..e03c4f8 100644 --- a/original-kernel-headers/linux/msm_audio_aac.h +++ b/original-kernel-headers/linux/msm_audio_aac.h @@ -14,6 +14,9 @@ #define AUDIO_GET_AAC_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ (AUDIO_MAX_COMMON_IOCTL_NUM+4), struct msm_audio_aac_enc_config) +#define AUDIO_SET_AAC_MIX_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \ + (AUDIO_MAX_COMMON_IOCTL_NUM+5), unsigned) + #define AUDIO_AAC_FORMAT_ADTS -1 #define AUDIO_AAC_FORMAT_RAW 0x0000 #define AUDIO_AAC_FORMAT_PSUEDO_RAW 0x0001 diff --git a/original-kernel-headers/linux/msm_charm.h b/original-kernel-headers/linux/msm_charm.h index c31e493..1d1f3bb 100644 --- a/original-kernel-headers/linux/msm_charm.h +++ b/original-kernel-headers/linux/msm_charm.h @@ -11,10 +11,16 @@ #define RAM_DUMP_DONE _IOW(CHARM_CODE, 6, int) #define WAIT_FOR_RESTART _IOR(CHARM_CODE, 7, int) #define GET_DLOAD_STATUS _IOR(CHARM_CODE, 8, int) +#define IMAGE_UPGRADE _IOW(CHARM_CODE, 9, int) +#define SHUTDOWN_CHARM _IOW(CHARM_CODE, 10, int) enum charm_boot_type { CHARM_NORMAL_BOOT = 0, CHARM_RAM_DUMPS, }; +enum image_upgrade_type { + APQ_CONTROLLED_UPGRADE = 0, + MDM_CONTROLLED_UPGRADE, +}; #endif diff --git a/original-kernel-headers/linux/msm_dsps.h b/original-kernel-headers/linux/msm_dsps.h index a5ac256..1f997ba 100644 --- a/original-kernel-headers/linux/msm_dsps.h +++ b/original-kernel-headers/linux/msm_dsps.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011, Code Aurora Forum. All rights reserved. + * Copyright (c) 2011, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/original-kernel-headers/linux/msm_hw3d.h b/original-kernel-headers/linux/msm_hw3d.h deleted file mode 100644 index a4afd87..0000000 --- a/original-kernel-headers/linux/msm_hw3d.h +++ /dev/null @@ -1,54 +0,0 @@ -/* include/linux/msm_hw3d.h - * - * Copyright (C) 2007 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - - -#ifndef _MSM_HW3D_H_ -#define _MSM_HW3D_H_ - -#include <linux/fs.h> -#include <linux/ioctl.h> - -struct hw3d_region; - -#define HW3D_IOCTL_MAGIC 'h' -#define HW3D_WAIT_FOR_REVOKE _IO(HW3D_IOCTL_MAGIC, 0x80) -#define HW3D_WAIT_FOR_INTERRUPT _IO(HW3D_IOCTL_MAGIC, 0x81) -#define HW3D_GET_REGIONS \ - _IOR(HW3D_IOCTL_MAGIC, 0x82, struct hw3d_region *) - -#define HW3D_REGION_OFFSET(id) ((((uint32_t)(id)) & 0xf) << 28) -#define HW3D_REGION_ID(addr) (((uint32_t)(addr) >> 28) & 0xf) -#define HW3D_OFFSET_IN_REGION(addr) ((uint32_t)(addr) & ~(0xfUL << 28)) - -enum { - HW3D_EBI = 0, - HW3D_SMI = 1, - HW3D_REGS = 2, - - HW3D_NUM_REGIONS = HW3D_REGS + 1, -}; - -struct hw3d_region { - unsigned long phys; - unsigned long map_offset; - unsigned long len; -}; - -int get_msm_hw3d_file(int fd, uint32_t *offs, unsigned long *pbase, - unsigned long *len, struct file **filp); -void put_msm_hw3d_file(struct file *file); -bool is_msm_hw3d_file(struct file *file); - -#endif /* _MSM_HW3D_H_ */ diff --git a/original-kernel-headers/linux/msm_ion.h b/original-kernel-headers/linux/msm_ion.h new file mode 100644 index 0000000..7585861 --- /dev/null +++ b/original-kernel-headers/linux/msm_ion.h @@ -0,0 +1,321 @@ +/* + * + * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _LINUX_MSM_ION_H +#define _LINUX_MSM_ION_H + +#include <linux/ion.h> + +#define ION_HEAP_TYPE_MSM_START (ION_HEAP_TYPE_CUSTOM + 1) +#define ION_HEAP_TYPE_IOMMU (ION_HEAP_TYPE_MSM_START) +#define ION_HEAP_TYPE_CP (ION_HEAP_TYPE_IOMMU + 1) + +/** + * These are the only ids that should be used for Ion heap ids. + * The ids listed are the order in which allocation will be attempted + * if specified. Don't swap the order of heap ids unless you know what + * you are doing! + * Id's are spaced by purpose to allow new Id's to be inserted in-between (for + * possible fallbacks) + */ + +enum ion_heap_ids { + INVALID_HEAP_ID = -1, + ION_CP_MM_HEAP_ID = 8, + ION_CP_MFC_HEAP_ID = 12, + ION_CP_WB_HEAP_ID = 16, /* 8660 only */ + ION_CAMERA_HEAP_ID = 20, /* 8660 only */ + ION_ADSP_HEAP_ID = 22, + ION_SF_HEAP_ID = 24, + ION_IOMMU_HEAP_ID = 25, + ION_QSECOM_HEAP_ID = 27, + ION_AUDIO_HEAP_ID = 28, + + ION_MM_FIRMWARE_HEAP_ID = 29, + ION_SYSTEM_HEAP_ID = 30, + + ION_HEAP_ID_RESERVED = 31 /** Bit reserved for ION_SECURE flag */ +}; + +enum ion_fixed_position { + NOT_FIXED, + FIXED_LOW, + FIXED_MIDDLE, + FIXED_HIGH, +}; + +enum cp_mem_usage { + VIDEO_BITSTREAM = 0x1, + VIDEO_PIXEL = 0x2, + VIDEO_NONPIXEL = 0x3, + MAX_USAGE = 0x4, + UNKNOWN = 0x7FFFFFFF, +}; + +#define ION_HEAP_CP_MASK (1 << ION_HEAP_TYPE_CP) + +/** + * Flag to use when allocating to indicate that a heap is secure. + */ +#define ION_SECURE (1 << ION_HEAP_ID_RESERVED) + +/** + * Flag for clients to force contiguous memort allocation + * + * Use of this flag is carefully monitored! + */ +#define ION_FORCE_CONTIGUOUS (1 << 30) + +/** + * Macro should be used with ion_heap_ids defined above. + */ +#define ION_HEAP(bit) (1 << (bit)) + +#define ION_ADSP_HEAP_NAME "adsp" +#define ION_VMALLOC_HEAP_NAME "vmalloc" +#define ION_AUDIO_HEAP_NAME "audio" +#define ION_SF_HEAP_NAME "sf" +#define ION_MM_HEAP_NAME "mm" +#define ION_CAMERA_HEAP_NAME "camera_preview" +#define ION_IOMMU_HEAP_NAME "iommu" +#define ION_MFC_HEAP_NAME "mfc" +#define ION_WB_HEAP_NAME "wb" +#define ION_MM_FIRMWARE_HEAP_NAME "mm_fw" +#define ION_QSECOM_HEAP_NAME "qsecom" +#define ION_FMEM_HEAP_NAME "fmem" + +#define ION_SET_CACHED(__cache) (__cache | ION_FLAG_CACHED) +#define ION_SET_UNCACHED(__cache) (__cache & ~ION_FLAG_CACHED) + +#define ION_IS_CACHED(__flags) ((__flags) & ION_FLAG_CACHED) + +#ifdef __KERNEL__ + +/* + * This flag allows clients when mapping into the IOMMU to specify to + * defer un-mapping from the IOMMU until the buffer memory is freed. + */ +#define ION_IOMMU_UNMAP_DELAYED 1 + +/** + * struct ion_cp_heap_pdata - defines a content protection heap in the given + * platform + * @permission_type: Memory ID used to identify the memory to TZ + * @align: Alignment requirement for the memory + * @secure_base: Base address for securing the heap. + * Note: This might be different from actual base address + * of this heap in the case of a shared heap. + * @secure_size: Memory size for securing the heap. + * Note: This might be different from actual size + * of this heap in the case of a shared heap. + * @reusable Flag indicating whether this heap is reusable of not. + * (see FMEM) + * @mem_is_fmem Flag indicating whether this memory is coming from fmem + * or not. + * @fixed_position If nonzero, position in the fixed area. + * @virt_addr: Virtual address used when using fmem. + * @iommu_map_all: Indicates whether we should map whole heap into IOMMU. + * @iommu_2x_map_domain: Indicates the domain to use for overmapping. + * @request_region: function to be called when the number of allocations + * goes from 0 -> 1 + * @release_region: function to be called when the number of allocations + * goes from 1 -> 0 + * @setup_region: function to be called upon ion registration + * @memory_type:Memory type used for the heap + * @no_nonsecure_alloc: don't allow non-secure allocations from this heap + * + */ +struct ion_cp_heap_pdata { + enum ion_permission_type permission_type; + unsigned int align; + ion_phys_addr_t secure_base; /* Base addr used when heap is shared */ + size_t secure_size; /* Size used for securing heap when heap is shared*/ + int reusable; + int mem_is_fmem; + int is_cma; + enum ion_fixed_position fixed_position; + int iommu_map_all; + int iommu_2x_map_domain; + ion_virt_addr_t *virt_addr; + int (*request_region)(void *); + int (*release_region)(void *); + void *(*setup_region)(void); + enum ion_memory_types memory_type; + int no_nonsecure_alloc; +}; + +/** + * struct ion_co_heap_pdata - defines a carveout heap in the given platform + * @adjacent_mem_id: Id of heap that this heap must be adjacent to. + * @align: Alignment requirement for the memory + * @mem_is_fmem Flag indicating whether this memory is coming from fmem + * or not. + * @fixed_position If nonzero, position in the fixed area. + * @request_region: function to be called when the number of allocations + * goes from 0 -> 1 + * @release_region: function to be called when the number of allocations + * goes from 1 -> 0 + * @setup_region: function to be called upon ion registration + * @memory_type:Memory type used for the heap + * + */ +struct ion_co_heap_pdata { + int adjacent_mem_id; + unsigned int align; + int mem_is_fmem; + enum ion_fixed_position fixed_position; + int (*request_region)(void *); + int (*release_region)(void *); + void *(*setup_region)(void); + enum ion_memory_types memory_type; +}; + +#ifdef CONFIG_ION +/** + * msm_ion_secure_heap - secure a heap. Wrapper around ion_secure_heap. + * + * @heap_id - heap id to secure. + * + * Secure a heap + * Returns 0 on success + */ +int msm_ion_secure_heap(int heap_id); + +/** + * msm_ion_unsecure_heap - unsecure a heap. Wrapper around ion_unsecure_heap. + * + * @heap_id - heap id to secure. + * + * Un-secure a heap + * Returns 0 on success + */ +int msm_ion_unsecure_heap(int heap_id); + +/** + * msm_ion_secure_heap_2_0 - secure a heap using 2.0 APIs + * Wrapper around ion_secure_heap. + * + * @heap_id - heap id to secure. + * @usage - usage hint to TZ + * + * Secure a heap + * Returns 0 on success + */ +int msm_ion_secure_heap_2_0(int heap_id, enum cp_mem_usage usage); + +/** + * msm_ion_unsecure_heap - unsecure a heap secured with 3.0 APIs. + * Wrapper around ion_unsecure_heap. + * + * @heap_id - heap id to secure. + * @usage - usage hint to TZ + * + * Un-secure a heap + * Returns 0 on success + */ +int msm_ion_unsecure_heap_2_0(int heap_id, enum cp_mem_usage usage); +#else +static inline int msm_ion_secure_heap(int heap_id) +{ + return -ENODEV; + +} + +static inline int msm_ion_unsecure_heap(int heap_id) +{ + return -ENODEV; +} + +static inline int msm_ion_secure_heap_2_0(int heap_id, enum cp_mem_usage usage) +{ + return -ENODEV; +} + +static inline int msm_ion_unsecure_heap_2_0(int heap_id, + enum cp_mem_usage usage) +{ + return -ENODEV; +} +#endif /* CONFIG_ION */ + +#endif /* __KERNEL */ + +/* struct ion_flush_data - data passed to ion for flushing caches + * + * @handle: handle with data to flush + * @fd: fd to flush + * @vaddr: userspace virtual address mapped with mmap + * @offset: offset into the handle to flush + * @length: length of handle to flush + * + * Performs cache operations on the handle. If p is the start address + * of the handle, p + offset through p + offset + length will have + * the cache operations performed + */ +struct ion_flush_data { + struct ion_handle *handle; + int fd; + void *vaddr; + unsigned int offset; + unsigned int length; +}; + +/* struct ion_flag_data - information about flags for this buffer + * + * @handle: handle to get flags from + * @flags: flags of this handle + * + * Takes handle as an input and outputs the flags from the handle + * in the flag field. + */ +struct ion_flag_data { + struct ion_handle *handle; + unsigned long flags; +}; + +#define ION_IOC_MSM_MAGIC 'M' + +/** + * DOC: ION_IOC_CLEAN_CACHES - clean the caches + * + * Clean the caches of the handle specified. + */ +#define ION_IOC_CLEAN_CACHES _IOWR(ION_IOC_MSM_MAGIC, 0, \ + struct ion_flush_data) +/** + * DOC: ION_IOC_INV_CACHES - invalidate the caches + * + * Invalidate the caches of the handle specified. + */ +#define ION_IOC_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 1, \ + struct ion_flush_data) +/** + * DOC: ION_IOC_CLEAN_INV_CACHES - clean and invalidate the caches + * + * Clean and invalidate the caches of the handle specified. + */ +#define ION_IOC_CLEAN_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 2, \ + struct ion_flush_data) + +/** + * DOC: ION_IOC_GET_FLAGS - get the flags of the handle + * + * Gets the flags of the current handle which indicate cachability, + * secure state etc. + */ +#define ION_IOC_GET_FLAGS _IOWR(ION_IOC_MSM_MAGIC, 3, \ + struct ion_flag_data) + +#endif diff --git a/original-kernel-headers/linux/msm_kgsl.h b/original-kernel-headers/linux/msm_kgsl.h index 6912087..78c0ef4 100644 --- a/original-kernel-headers/linux/msm_kgsl.h +++ b/original-kernel-headers/linux/msm_kgsl.h @@ -13,6 +13,8 @@ #define KGSL_CONTEXT_TRASH_STATE 0x00000020 #define KGSL_CONTEXT_PER_CONTEXT_TS 0x00000040 #define KGSL_CONTEXT_USER_GENERATED_TS 0x00000080 +#define KGSL_CONTEXT_NO_FAULT_TOLERANCE 0x00000200 + #define KGSL_CONTEXT_INVALID 0xffffffff @@ -163,6 +165,31 @@ enum kgsl_property_type { KGSL_PROP_VERSION = 0x00000008, KGSL_PROP_GPU_RESET_STAT = 0x00000009, KGSL_PROP_PWRCTRL = 0x0000000E, + KGSL_PROP_FAULT_TOLERANCE = 0x00000011, +}; + +/* Fault Tolerance policy flags */ +#define KGSL_FT_DISABLE 0x00000001 +#define KGSL_FT_REPLAY 0x00000002 +#define KGSL_FT_SKIPIB 0x00000004 +#define KGSL_FT_SKIPFRAME 0x00000008 +#define KGSL_FT_DEFAULT_POLICY (KGSL_FT_REPLAY + KGSL_FT_SKIPIB) + +/* Pagefault policy flags */ +#define KGSL_FT_PAGEFAULT_INT_ENABLE 0x00000001 +#define KGSL_FT_PAGEFAULT_GPUHALT_ENABLE 0x00000002 +#define KGSL_FT_PAGEFAULT_LOG_ONE_PER_PAGE 0x00000004 +#define KGSL_FT_PAGEFAULT_LOG_ONE_PER_INT 0x00000008 +#define KGSL_FT_PAGEFAULT_DEFAULT_POLICY (KGSL_FT_PAGEFAULT_INT_ENABLE + \ + KGSL_FT_PAGEFAULT_LOG_ONE_PER_PAGE) + +/* Fault tolerance config */ +struct kgsl_ft_config { + unsigned int ft_policy; /* Fault Tolerance policy flags */ + unsigned int ft_pf_policy; /* Pagefault policy flags */ + unsigned int ft_pm_dump; /* KGSL enable postmortem dump */ + unsigned int ft_detect_ms; + unsigned int ft_dos_timeout_ms; }; struct kgsl_shadowprop { diff --git a/original-kernel-headers/linux/msm_mdp.h b/original-kernel-headers/linux/msm_mdp.h index 5fdc390..d3bfdc2 100755 --- a/original-kernel-headers/linux/msm_mdp.h +++ b/original-kernel-headers/linux/msm_mdp.h @@ -1,7 +1,7 @@ /* include/linux/msm_mdp.h * * Copyright (C) 2007 Google Incorporated - * Copyright (c) 2012 Code Aurora Forum. All rights reserved. + * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -71,9 +71,11 @@ #define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) #define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) #define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) - #define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \ struct mdp_display_commit) +#define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 165, \ + unsigned int) +#define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) #define FB_TYPE_3D_PANEL 0x10101010 #define MDP_IMGTYPE2_START 0x10000 @@ -274,8 +276,10 @@ struct msmfb_writeback_data { struct msmfb_img img; }; +#define MDP_PP_OPS_ENABLE 0x1 #define MDP_PP_OPS_READ 0x2 #define MDP_PP_OPS_WRITE 0x4 +#define MDP_PP_OPS_DISABLE 0x8 struct mdp_qseed_cfg { uint32_t table_num; @@ -289,8 +293,19 @@ struct mdp_qseed_cfg_data { struct mdp_qseed_cfg qseed_data; }; +struct mdp_sharp_cfg { + uint32_t flags; + uint32_t strength; + uint32_t edge_thr; + uint32_t smooth_thr; + uint32_t noise_thr; +}; + #define MDP_OVERLAY_PP_CSC_CFG 0x1 #define MDP_OVERLAY_PP_QSEED_CFG 0x2 +#define MDP_OVERLAY_PP_PA_CFG 0x4 +#define MDP_OVERLAY_PP_IGC_CFG 0x8 +#define MDP_OVERLAY_PP_SHARP_CFG 0x10 #define MDP_CSC_FLAG_ENABLE 0x1 #define MDP_CSC_FLAG_YUV_IN 0x2 @@ -311,10 +326,28 @@ struct mdp_csc_cfg_data { struct mdp_csc_cfg csc_data; }; +struct mdp_pa_cfg { + uint32_t flags; + uint32_t hue_adj; + uint32_t sat_adj; + uint32_t val_adj; + uint32_t cont_adj; +}; + +struct mdp_igc_lut_data { + uint32_t block; + uint32_t len, ops; + uint32_t *c0_c1_data; + uint32_t *c2_data; +}; + struct mdp_overlay_pp_params { uint32_t config_ops; struct mdp_csc_cfg csc_cfg; struct mdp_qseed_cfg qseed_cfg[2]; + struct mdp_pa_cfg pa_cfg; + struct mdp_igc_lut_data igc_cfg; + struct mdp_sharp_cfg sharp_cfg; }; struct mdp_overlay { @@ -357,12 +390,15 @@ struct mdp_histogram { /* - mdp_block_type defines the identifiers for each of pipes in MDP 4.3 + mdp_block_type defines the identifiers for pipes in MDP 4.3 and up MDP_BLOCK_RESERVED is provided for backward compatibility and is deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used instead. + MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses, + same for others. + */ enum { @@ -377,6 +413,9 @@ enum { MDP_BLOCK_DMA_S, MDP_BLOCK_DMA_E, MDP_BLOCK_OVERLAY_2, + MDP_LOGICAL_BLOCK_DISP_0 = 0x1000, + MDP_LOGICAL_BLOCK_DISP_1, + MDP_LOGICAL_BLOCK_DISP_2, MDP_BLOCK_MAX, }; @@ -423,13 +462,6 @@ enum { mdp_lut_max, }; -struct mdp_igc_lut_data { - uint32_t block; - uint32_t len, ops; - uint32_t *c0_c1_data; - uint32_t *c2_data; -}; - struct mdp_ar_gc_lut_data { uint32_t x_start; uint32_t slope; @@ -469,12 +501,25 @@ struct mdp_bl_scale_data { uint32_t scale; }; +struct mdp_calib_config_data { + uint32_t ops; + uint32_t addr; + uint32_t data; +}; + +struct mdp_pa_cfg_data { + uint32_t block; + struct mdp_pa_cfg pa_data; +}; + enum { mdp_op_pcc_cfg, mdp_op_csc_cfg, mdp_op_lut_cfg, mdp_op_qseed_cfg, mdp_bl_scale_cfg, + mdp_op_calib_cfg, + mdp_op_pa_cfg, mdp_op_max, }; @@ -486,6 +531,28 @@ struct msmfb_mdp_pp { struct mdp_lut_cfg_data lut_cfg_data; struct mdp_qseed_cfg_data qseed_cfg_data; struct mdp_bl_scale_data bl_scale_data; + struct mdp_calib_config_data calib_cfg; + struct mdp_pa_cfg_data pa_cfg_data; + } data; +}; + +enum { + metadata_op_none, + metadata_op_base_blend, + metadata_op_frame_rate, + metadata_op_max +}; + +struct mdp_blend_cfg { + uint32_t is_premultiplied; +}; + +struct msmfb_metadata { + uint32_t op; + uint32_t flags; + union { + struct mdp_blend_cfg blend_cfg; + uint32_t panel_frame_rate; } data; }; @@ -512,7 +579,6 @@ struct mdp_display_commit { uint32_t flags; uint32_t wait_for_finish; struct fb_var_screeninfo var; - struct mdp_buf_fence buf_fence; }; struct mdp_page_protection { @@ -541,6 +607,13 @@ enum { ROTATOR_SUBSYSTEM_ID, }; +enum { + MDP_WRITEBACK_MIRROR_OFF, + MDP_WRITEBACK_MIRROR_ON, + MDP_WRITEBACK_MIRROR_PAUSE, + MDP_WRITEBACK_MIRROR_RESUME, +}; + #ifdef __KERNEL__ /* get the framebuffer physical address information */ diff --git a/original-kernel-headers/linux/msm_q6vdec.h b/original-kernel-headers/linux/msm_q6vdec.h index 1dca803..47b8163 100644 --- a/original-kernel-headers/linux/msm_q6vdec.h +++ b/original-kernel-headers/linux/msm_q6vdec.h @@ -1,31 +1,3 @@ -/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Code Aurora nor - * the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - #ifndef _MSM_VDEC_H_ #define _MSM_VDEC_H_ @@ -45,6 +17,13 @@ #define VDEC_IOCTL_FREEBUFFERS _IOW(VDEC_IOCTL_MAGIC, 9, struct vdec_buf_info) #define VDEC_IOCTL_GETDECATTRIBUTES _IOR(VDEC_IOCTL_MAGIC, 10, \ struct vdec_dec_attributes) +#define VDEC_IOCTL_GETVERSION _IOR(VDEC_IOCTL_MAGIC, 11, struct vdec_version) +#define VDEC_IOCTL_SETPROPERTY _IOW \ + (VDEC_IOCTL_MAGIC, 12, struct vdec_property_info) +#define VDEC_IOCTL_GETPROPERTY _IOR \ + (VDEC_IOCTL_MAGIC, 13, struct vdec_property_info) +#define VDEC_IOCTL_PERFORMANCE_CHANGE_REQ _IOW(VDEC_IOCTL_MAGIC, 14, \ + unsigned int) enum { VDEC_FRAME_DECODE_OK, @@ -77,6 +56,32 @@ enum { VDEC_QUEUE_BADSTATE, }; +enum { + VDEC_COLOR_FORMAT_NV21 = 0x01, + VDEC_COLOR_FORMAT_NV21_YAMOTO = 0x02 + }; + +enum vdec_property_id { + VDEC_FOURCC, + VDEC_PROFILE, + VDEC_LEVEL, + VDEC_DIMENSIONS, + VDEC_CWIN, + VDEC_INPUT_BUF_REQ, + VDEC_OUTPUT_BUF_REQ, + VDEC_LUMA_CHROMA_STRIDE, + VDEC_NUM_DAL_PORTS, + VDEC_PRIORITY, + VDEC_FRAME_ALIGNMENT +}; + +enum { + PERF_REQUEST_SET_MIN = 0, + PERF_REQUEST_LOWER, + PERF_REQUEST_RAISE, + PERF_REQUEST_SET_MAX +}; + struct vdec_input_buf_info { u32 offset; u32 data; @@ -118,7 +123,7 @@ struct vdec_config { u32 h264_nal_len_size; u32 postproc_flag; u32 fruc_enable; - u32 reserved; + u32 color_format; /* used to set YUV color format */ }; struct vdec_vc1_panscan_regions { @@ -161,7 +166,7 @@ struct vdec_frame_info { u32 concealed_macblk_num; /* number of concealed macro blk */ u32 flags; /* input flags */ u32 performance_stats; /* performance statistics returned by decoder */ - u32 data3; /* user data field 3 */ + u32 data3; /* user data field 3 */ }; struct vdec_buf_info { @@ -227,4 +232,46 @@ struct vdec_dec_attributes { struct vdec_buf_desc dec_req2; }; +struct vdec_version { + u32 major; + u32 minor; +}; + +struct dal_vdec_rectangle { + u32 width; + u32 height; +}; + +struct stride_type { + u32 luma; + u32 chroma; +}; + +struct frame_alignment_type { + u32 luma_width; + u32 luma_height; + u32 chroma_width; + u32 chroma_height; + u32 chroma_offset; +}; + +union vdec_property { + u32 fourcc; + u32 profile; + u32 level; + struct dal_vdec_rectangle dim; + struct vdec_cropping_window cw; + struct vdec_buf_desc input_req; + struct vdec_buf_desc output_req; + struct stride_type stride; + u32 num_dal_ports; + u32 priority; + struct frame_alignment_type frame_alignment; + u32 def_type; +}; + +struct vdec_property_info { + enum vdec_property_id id; + union vdec_property property; +}; #endif /* _MSM_VDEC_H_ */ diff --git a/original-kernel-headers/linux/msm_q6venc.h b/original-kernel-headers/linux/msm_q6venc.h index db31332..c6bf20c 100755 --- a/original-kernel-headers/linux/msm_q6venc.h +++ b/original-kernel-headers/linux/msm_q6venc.h @@ -1,31 +1,3 @@ -/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Code Aurora nor - * the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - #ifndef _MSM_VENC_H_ #define _MSM_VENC_H_ @@ -116,52 +88,52 @@ enum venc_mem_region_enum { }; struct venc_buf_type { - unsigned int region; - unsigned int phys; - unsigned int size; + u32 region; + u32 phys; + u32 size; int offset; }; struct venc_qp_range { - unsigned int min_qp; - unsigned int max_qp; + u32 min_qp; + u32 max_qp; }; struct venc_frame_rate { - unsigned int frame_rate_num; - unsigned int frame_rate_den; + u32 frame_rate_num; + u32 frame_rate_den; }; struct venc_slice_info { - unsigned int slice_mode; - unsigned int units_per_slice; + u32 slice_mode; + u32 units_per_slice; }; struct venc_extra_data { - unsigned int slice_extra_data_flag; - unsigned int slice_client_data1; - unsigned int slice_client_data2; - unsigned int slice_client_data3; - unsigned int none_extra_data_flag; - unsigned int none_client_data1; - unsigned int none_client_data2; - unsigned int none_client_data3; + u32 slice_extra_data_flag; + u32 slice_client_data1; + u32 slice_client_data2; + u32 slice_client_data3; + u32 none_extra_data_flag; + u32 none_client_data1; + u32 none_client_data2; + u32 none_client_data3; }; struct venc_common_config { - unsigned int standard; - unsigned int input_frame_height; - unsigned int input_frame_width; - unsigned int output_frame_height; - unsigned int output_frame_width; - unsigned int rotation_angle; - unsigned int intra_period; - unsigned int rate_control; + u32 standard; + u32 input_frame_height; + u32 input_frame_width; + u32 output_frame_height; + u32 output_frame_width; + u32 rotation_angle; + u32 intra_period; + u32 rate_control; struct venc_frame_rate frame_rate; - unsigned int bitrate; + u32 bitrate; struct venc_qp_range qp_range; - unsigned int iframe_qp; - unsigned int pframe_qp; + u32 iframe_qp; + u32 pframe_qp; struct venc_slice_info slice_config; struct venc_extra_data extra_data; }; @@ -175,45 +147,46 @@ struct venc_nonio_buf_config { }; struct venc_mpeg4_config { - unsigned int profile; - unsigned int level; - unsigned int time_resolution; - unsigned int ac_prediction; - unsigned int hec_interval; - unsigned int data_partition; - unsigned int short_header; - unsigned int rvlc_enable; + u32 profile; + u32 level; + u32 time_resolution; + u32 ac_prediction; + u32 hec_interval; + u32 data_partition; + u32 short_header; + u32 rvlc_enable; }; struct venc_h263_config { - unsigned int profile; - unsigned int level; + u32 profile; + u32 level; }; struct venc_h264_config { - unsigned int profile; - unsigned int level; - unsigned int max_nal; - unsigned int idr_period; + u32 profile; + u32 level; + u32 max_nal; + u32 idr_period; }; struct venc_pmem { int src; int fd; - unsigned int offset; + u32 offset; void *virt; void *phys; - unsigned int size; + u32 size; }; struct venc_buffer { unsigned char *ptr_buffer; - unsigned int size; - unsigned int len; - unsigned int offset; + u32 size; + u32 len; + u32 offset; long long time_stamp; - unsigned int flags; - unsigned int client_data; + u32 flags; + u32 client_data; + }; struct venc_buffers { @@ -224,19 +197,20 @@ struct venc_buffers { }; struct venc_buffer_flush { - unsigned int flush_mode; + u32 flush_mode; }; union venc_msg_data { struct venc_buffer buf; struct venc_buffer_flush flush_ret; + }; struct venc_msg { - unsigned int status_code; - unsigned int msg_code; + u32 status_code; + u32 msg_code; + u32 msg_data_size; union venc_msg_data msg_data; - unsigned int msg_data_size; }; union venc_codec_config { @@ -268,6 +242,11 @@ struct venc_seq_config { struct venc_q6_config q6_config; }; +struct venc_version { + u32 major; + u32 minor; +}; + #define VENC_IOCTL_MAGIC 'V' #define VENC_IOCTL_CMD_READ_NEXT_MSG \ @@ -318,4 +297,7 @@ struct venc_seq_config { #define VENC_IOCTL_SET_QP_RANGE \ _IOW(VENC_IOCTL_MAGIC, 18, struct venc_qp_range) +#define VENC_IOCTL_GET_VERSION \ + _IOR(VENC_IOCTL_MAGIC, 19, struct venc_version) + #endif diff --git a/original-kernel-headers/linux/msm_rmnet.h b/original-kernel-headers/linux/msm_rmnet.h index 9f52464..01d52b6 100644 --- a/original-kernel-headers/linux/msm_rmnet.h +++ b/original-kernel-headers/linux/msm_rmnet.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. +/* Copyright (c) 2010, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -40,6 +40,8 @@ enum rmnet_ioctl_cmds_e { RMNET_IOCTL_GET_OPMODE = 0x000089F7, /* Get operation mode */ RMNET_IOCTL_OPEN = 0x000089F8, /* Open transport port */ RMNET_IOCTL_CLOSE = 0x000089F9, /* Close transport port */ + RMNET_IOCTL_FLOW_ENABLE = 0x000089FA, /* Flow enable */ + RMNET_IOCTL_FLOW_DISABLE = 0x000089FB, /* Flow disable */ RMNET_IOCTL_MAX }; diff --git a/original-kernel-headers/linux/msm_vidc_dec.h b/original-kernel-headers/linux/msm_vidc_dec.h index 0c03e13..cd363c5 100644 --- a/original-kernel-headers/linux/msm_vidc_dec.h +++ b/original-kernel-headers/linux/msm_vidc_dec.h @@ -76,6 +76,10 @@ #define VDEC_EXTRADATA_VUI 0x020 #define VDEC_EXTRADATA_VC1 0x040 +#define VDEC_EXTRADATA_EXT_DATA 0x0800 +#define VDEC_EXTRADATA_USER_DATA 0x1000 +#define VDEC_EXTRADATA_EXT_BUFFER 0x2000 + #define VDEC_CMDBASE 0x800 #define VDEC_CMD_SET_INTF_VERSION (VDEC_CMDBASE) @@ -207,6 +211,18 @@ struct vdec_ioctl_msg { #define VDEC_IOCTL_GET_DISABLE_DMX_SUPPORT \ _IOR(VDEC_IOCTL_MAGIC, 37, struct vdec_ioctl_msg) +#define VDEC_IOCTL_SET_PERF_CLK \ + _IOR(VDEC_IOCTL_MAGIC, 38, struct vdec_ioctl_msg) + +#define VDEC_IOCTL_SET_META_BUFFERS \ + _IOW(VDEC_IOCTL_MAGIC, 39, struct vdec_ioctl_msg) + +#define VDEC_IOCTL_FREE_META_BUFFERS \ + _IO(VDEC_IOCTL_MAGIC, 40) + +#define VDEC_IOCTL_GET_ENABLE_SEC_METADATA \ + _IOR(VDEC_IOCTL_MAGIC, 41, struct vdec_ioctl_msg) + enum vdec_picture { PICTURE_TYPE_I, PICTURE_TYPE_P, @@ -230,6 +246,7 @@ struct vdec_allocatorproperty { size_t buffer_size; uint32_t alignment; uint32_t buf_poolid; + size_t meta_buffer_size; }; struct vdec_bufferpayload { @@ -520,6 +537,11 @@ struct vdec_aspectratioinfo { uint32_t par_height; }; +struct vdec_sep_metadatainfo { + void __user *metabufaddr; + uint32_t size; +}; + struct vdec_output_frameinfo { void __user *bufferaddr; size_t offset; @@ -532,6 +554,7 @@ struct vdec_output_frameinfo { struct vdec_framesize framesize; enum vdec_interlaced_format interlaced_format; struct vdec_aspectratioinfo aspect_ratio_info; + struct vdec_sep_metadatainfo metadata_info; }; union vdec_msgdata { @@ -565,4 +588,12 @@ struct vdec_mv_buff_size{ int alignment; }; +struct vdec_meta_buffers { + size_t size; + int count; + int pmem_fd; + int pmem_fd_iommu; + int offset; +}; + #endif /* end of macro _VDECDECODER_H_ */ diff --git a/original-kernel-headers/linux/msm_vidc_enc.h b/original-kernel-headers/linux/msm_vidc_enc.h index 0a163ce..de78873 100644 --- a/original-kernel-headers/linux/msm_vidc_enc.h +++ b/original-kernel-headers/linux/msm_vidc_enc.h @@ -144,6 +144,8 @@ #define VEN_INPUTFMT_NV12 1/* NV12 Linear */ #define VEN_INPUTFMT_NV21 2/* NV21 Linear */ #define VEN_INPUTFMT_NV12_16M2KA 3/* NV12 Linear */ +#define VEN_INPUTFMT_NV21_16M2KA 4 + /*Different allowed rotation modes.*/ #define VEN_ROTATION_0 1/* 0 degrees */ diff --git a/original-kernel-headers/media/msm_camera.h b/original-kernel-headers/media/msm_camera.h index d1d4eaa..e2828b6 100644 --- a/original-kernel-headers/media/msm_camera.h +++ b/original-kernel-headers/media/msm_camera.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved. +/* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -27,7 +27,7 @@ #include <linux/time.h> #endif -#include <linux/ion.h> +#include <linux/msm_ion.h> #define BIT(nr) (1UL << (nr)) @@ -216,20 +216,19 @@ #define MSM_CAM_IOCTL_STATS_UNREG_BUF \ _IOR(MSM_CAM_IOCTL_MAGIC, 61, struct msm_stats_flush_bufq *) - struct msm_stats_reqbuf { int num_buf; /* how many buffers requested */ - int stats_type; /* stats type */ + int stats_type; /* stats type */ }; struct msm_stats_flush_bufq { - int stats_type; /* enum msm_stats_enum_type */ + int stats_type; /* enum msm_stats_enum_type */ }; struct msm_mctl_pp_cmd { - int32_t id; + int32_t id; uint16_t length; - void *value; + void *value; }; struct msm_mctl_post_proc_cmd { @@ -258,7 +257,6 @@ struct msm_mctl_post_proc_cmd { #define MAX_ACTUATOR_TYPE_SIZE 32 #define MAX_ACTUATOR_REG_TBL_SIZE 8 - #define MSM_MAX_CAMERA_CONFIGS 2 #define PP_SNAP 0x01 @@ -291,12 +289,12 @@ struct msm_ctrl_cmd { void *value; uint16_t status; uint32_t timeout_ms; - int resp_fd; /* FIXME: to be used by the kernel, pass-through for now */ - int vnode_id; /* video dev id. Can we overload resp_fd? */ + int resp_fd; /* FIXME: to be used by the kernel, pass-through for now */ + int vnode_id; /* video dev id. Can we overload resp_fd? */ int queue_idx; uint32_t evt_id; - uint32_t stream_type; /* used to pass value to qcamera server */ - int config_ident; /*used as identifier for config node*/ + uint32_t stream_type; /* used to pass value to qcamera server */ + int config_ident; /*used as identifier for config node */ }; struct msm_cam_evt_msg { @@ -310,37 +308,37 @@ struct msm_cam_evt_msg { struct msm_pp_frame_sp { /* phy addr of the buffer */ - unsigned long phy_addr; - uint32_t y_off; - uint32_t cbcr_off; + unsigned long phy_addr; + uint32_t y_off; + uint32_t cbcr_off; /* buffer length */ - uint32_t length; - int32_t fd; - uint32_t addr_offset; + uint32_t length; + int32_t fd; + uint32_t addr_offset; /* mapped addr */ - unsigned long vaddr; + unsigned long vaddr; }; struct msm_pp_frame_mp { /* phy addr of the plane */ - unsigned long phy_addr; + unsigned long phy_addr; /* offset of plane data */ - uint32_t data_offset; + uint32_t data_offset; /* plane length */ - uint32_t length; - int32_t fd; - uint32_t addr_offset; + uint32_t length; + int32_t fd; + uint32_t addr_offset; /* mapped addr */ - unsigned long vaddr; + unsigned long vaddr; }; struct msm_pp_frame { - uint32_t handle; /* stores vb cookie */ - uint32_t frame_id; + uint32_t handle; /* stores vb cookie */ + uint32_t frame_id; unsigned short buf_idx; - int path; + int path; unsigned short image_type; - unsigned short num_planes; /* 1 for sp */ + unsigned short num_planes; /* 1 for sp */ struct timeval timestamp; union { struct msm_pp_frame_sp sp; @@ -356,17 +354,17 @@ struct msm_cam_evt_divert_frame { unsigned short inst_idx; unsigned short node_idx; struct msm_pp_frame frame; - int do_pp; + int do_pp; }; struct msm_mctl_pp_cmd_ack_event { - uint32_t cmd; /* VPE_CMD_ZOOM? */ - int status; /* 0 done, < 0 err */ - uint32_t cookie; /* daemon's cookie */ + uint32_t cmd; /* VPE_CMD_ZOOM? */ + int status; /* 0 done, < 0 err */ + uint32_t cookie; /* daemon's cookie */ }; struct msm_mctl_pp_event_info { - int32_t event; + int32_t event; union { struct msm_mctl_pp_cmd_ack_event ack; }; @@ -500,7 +498,6 @@ struct msm_camera_cfg_cmd { #define CMD_AXI_STOP 0xE2 #define CMD_AXI_RESET 0xE3 - #define AXI_CMD_PREVIEW BIT(0) #define AXI_CMD_CAPTURE BIT(1) #define AXI_CMD_RECORD BIT(2) @@ -572,22 +569,22 @@ struct camera_enable_cmd { #define FRAME_MAX 5 enum msm_stats_enum_type { - MSM_STATS_TYPE_AEC, /* legacy based AEC */ - MSM_STATS_TYPE_AF, /* legacy based AF */ - MSM_STATS_TYPE_AWB, /* legacy based AWB */ - MSM_STATS_TYPE_RS, /* legacy based RS */ - MSM_STATS_TYPE_CS, /* legacy based CS */ - MSM_STATS_TYPE_IHIST, /* legacy based HIST */ - MSM_STATS_TYPE_SKIN, /* legacy based SKIN */ - MSM_STATS_TYPE_BG, /* Bayer Grids */ - MSM_STATS_TYPE_BF, /* Bayer Focus */ - MSM_STATS_TYPE_BHIST, /* Bayer Hist */ - MSM_STATS_TYPE_AE_AW, /* legacy stats for vfe 2.x*/ - MSM_STATS_TYPE_MAX /* MAX */ + MSM_STATS_TYPE_AEC, /* legacy based AEC */ + MSM_STATS_TYPE_AF, /* legacy based AF */ + MSM_STATS_TYPE_AWB, /* legacy based AWB */ + MSM_STATS_TYPE_RS, /* legacy based RS */ + MSM_STATS_TYPE_CS, /* legacy based CS */ + MSM_STATS_TYPE_IHIST, /* legacy based HIST */ + MSM_STATS_TYPE_SKIN, /* legacy based SKIN */ + MSM_STATS_TYPE_BG, /* Bayer Grids */ + MSM_STATS_TYPE_BF, /* Bayer Focus */ + MSM_STATS_TYPE_BHIST, /* Bayer Hist */ + MSM_STATS_TYPE_AE_AW, /* legacy stats for vfe 2.x */ + MSM_STATS_TYPE_MAX /* MAX */ }; struct msm_stats_buf_info { - int type; /* msm_stats_enum_type */ + int type; /* msm_stats_enum_type */ int fd; void *vaddr; uint32_t offset; @@ -628,8 +625,8 @@ struct outputCfg { #define OUTPUT_1 0 #define OUTPUT_2 1 -#define OUTPUT_1_AND_2 2 /* snapshot only */ -#define OUTPUT_1_AND_3 3 /* video */ +#define OUTPUT_1_AND_2 2 /* snapshot only */ +#define OUTPUT_1_AND_3 3 /* video */ #define CAMIF_TO_AXI_VIA_OUTPUT_2 4 #define OUTPUT_1_AND_CAMIF_TO_AXI_VIA_OUTPUT_2 5 #define OUTPUT_2_AND_CAMIF_TO_AXI_VIA_OUTPUT_1 6 @@ -646,8 +643,6 @@ struct outputCfg { #define OUTPUT_TERT1 BIT(12) #define OUTPUT_TERT2 BIT(13) - - #define MSM_FRAME_PREV_1 0 #define MSM_FRAME_PREV_2 1 #define MSM_FRAME_ENC 2 @@ -663,8 +658,6 @@ struct outputCfg { #define OUTPUT_TYPE_R BIT(8) #define OUTPUT_TYPE_R1 BIT(9) - - struct fd_roi_info { void *info; int info_len; @@ -836,7 +829,6 @@ struct msm_stats_buf { /* camera operation mode for jpeg snapshot - one frame output queue */ #define MSM_V4L2_CAM_OP_JPEG_CAPTURE (MSM_V4L2_CAM_OP_DEFAULT+6) - #define MSM_V4L2_VID_CAP_TYPE 0 #define MSM_V4L2_STREAM_ON 1 #define MSM_V4L2_STREAM_OFF 2 @@ -920,7 +912,6 @@ struct msm_snapshot_pp_status { #define CFG_GET_CSI_PARAMS 46 #define CFG_MAX 47 - #define MOVE_NEAR 0 #define MOVE_FAR 1 @@ -983,7 +974,6 @@ struct msm_snapshot_pp_status { #define CAMERA_BRIGHTNESS_LV7 7 #define CAMERA_BRIGHTNESS_LV8 8 - #define CAMERA_SATURATION_LV0 0 #define CAMERA_SATURATION_LV1 1 #define CAMERA_SATURATION_LV2 2 @@ -1009,7 +999,7 @@ struct msm_snapshot_pp_status { #define CAMERA_SETAE_AVERAGE 0 #define CAMERA_SETAE_CENWEIGHT 1 -#define CAMERA_WB_AUTO 1 /* This list must match aeecamera.h */ +#define CAMERA_WB_AUTO 1 /* This list must match aeecamera.h */ #define CAMERA_WB_CUSTOM 2 #define CAMERA_WB_INCANDESCENT 3 #define CAMERA_WB_FLUORESCENT 4 @@ -1052,7 +1042,6 @@ enum msm_v4l2_contrast_level { MSM_V4L2_CONTRAST_L10, }; - enum msm_v4l2_exposure_level { MSM_V4L2_EXPOSURE_N2, MSM_V4L2_EXPOSURE_N1, @@ -1089,7 +1078,7 @@ enum msm_v4l2_iso_mode { enum msm_v4l2_wb_mode { MSM_V4L2_WB_OFF, - MSM_V4L2_WB_AUTO , + MSM_V4L2_WB_AUTO, MSM_V4L2_WB_CUSTOM, MSM_V4L2_WB_INCANDESCENT, MSM_V4L2_WB_FLUORESCENT, @@ -1162,7 +1151,7 @@ struct sensor_3d_exp_cfg { uint16_t gb_gain; uint16_t gain_adjust; }; -struct sensor_3d_cali_data_t{ +struct sensor_3d_cali_data_t { unsigned char left_p_matrix[3][4][8]; unsigned char right_p_matrix[3][4][8]; unsigned char square_len[8]; @@ -1193,14 +1182,13 @@ struct sensor_init_cfg { }; #define ROLLOFF_CALDATA_SIZE (17 * 13) -typedef struct -{ - unsigned short mesh_rolloff_table_size; // TableSize - uint8_t r_gain[ROLLOFF_CALDATA_SIZE]; // RGain - uint8_t gr_gain[ROLLOFF_CALDATA_SIZE]; // GRGain - uint8_t gb_gain[ROLLOFF_CALDATA_SIZE]; // GBGain - uint8_t b_gain[ROLLOFF_CALDATA_SIZE]; // BGain - uint8_t red_ref[17]; +typedef struct { + unsigned short mesh_rolloff_table_size; // TableSize + uint8_t r_gain[ROLLOFF_CALDATA_SIZE]; // RGain + uint8_t gr_gain[ROLLOFF_CALDATA_SIZE]; // GRGain + uint8_t gb_gain[ROLLOFF_CALDATA_SIZE]; // GBGain + uint8_t b_gain[ROLLOFF_CALDATA_SIZE]; // BGain + uint8_t red_ref[17]; } rolloff_caldata_array_type; struct sensor_calib_data { @@ -1661,8 +1649,8 @@ struct msm_camsensor_info { uint8_t support_3d; enum flash_type flashtype; enum sensor_type_t sensor_type; - uint32_t pxlcode; /* enum v4l2_mbus_pixelcode */ - uint32_t camera_type; /* msm_camera_type */ + uint32_t pxlcode; /* enum v4l2_mbus_pixelcode */ + uint32_t camera_type; /* msm_camera_type */ int mount_angle; uint32_t max_width; uint32_t max_height; @@ -1684,7 +1672,7 @@ struct img_plane_info { uint32_t width; uint32_t height; uint32_t pixelformat; - uint8_t buffer_type; /*Single/Multi planar*/ + uint8_t buffer_type; /*Single/Multi planar */ uint8_t output_port; uint32_t ext_mode; uint8_t num_planes; @@ -1847,8 +1835,8 @@ struct msm_camera_irq_cfg { * 0 - MSM_CAM_HW_MICRO */ uint32_t cam_hw_mask; - uint8_t irq_idx; - uint8_t num_hwcore; + uint8_t irq_idx; + uint8_t num_hwcore; }; #define MSM_IRQROUTER_CFG_COMPIRQ \ @@ -1878,7 +1866,7 @@ struct msm_cpp_frame_strip_info { * rotation expects all the blocks in the stripe to be the same size * Padding is done such that all the extra padded pixels * are on the right and bottom - */ + */ int pad_bottom; int pad_top; int pad_right; diff --git a/original-kernel-headers/media/msm_gestures.h b/original-kernel-headers/media/msm_gestures.h index c9af034..a6efd4f 100644 --- a/original-kernel-headers/media/msm_gestures.h +++ b/original-kernel-headers/media/msm_gestures.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2012, Code Aurora Forum. All rights reserved. +/* Copyright (c) 2012, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/original-kernel-headers/media/msm_isp.h b/original-kernel-headers/media/msm_isp.h index 9fa5932..a0aede0 100644 --- a/original-kernel-headers/media/msm_isp.h +++ b/original-kernel-headers/media/msm_isp.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. +/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -235,9 +235,9 @@ #define VFE_CMD_TEST_GEN_CFG 162 struct msm_isp_cmd { - int32_t id; + int32_t id; uint16_t length; - void *value; + void *value; }; #define VPE_CMD_DUMMY_0 0 @@ -255,14 +255,14 @@ struct msm_isp_cmd { #define VPE_CMD_ZOOM 13 #define VPE_CMD_MAX 14 -#define MSM_PP_CMD_TYPE_NOT_USED 0 /* not used */ -#define MSM_PP_CMD_TYPE_VPE 1 /* VPE cmd */ -#define MSM_PP_CMD_TYPE_MCTL 2 /* MCTL cmd */ +#define MSM_PP_CMD_TYPE_NOT_USED 0 /* not used */ +#define MSM_PP_CMD_TYPE_VPE 1 /* VPE cmd */ +#define MSM_PP_CMD_TYPE_MCTL 2 /* MCTL cmd */ -#define MCTL_CMD_DUMMY_0 0 /* not used */ -#define MCTL_CMD_GET_FRAME_BUFFER 1 /* reserve a free frame buffer */ -#define MCTL_CMD_PUT_FRAME_BUFFER 2 /* return the free frame buffer */ -#define MCTL_CMD_DIVERT_FRAME_PP_PATH 3 /* divert frame for pp */ +#define MCTL_CMD_DUMMY_0 0 /* not used */ +#define MCTL_CMD_GET_FRAME_BUFFER 1 /* reserve a free frame buffer */ +#define MCTL_CMD_PUT_FRAME_BUFFER 2 /* return the free frame buffer */ +#define MCTL_CMD_DIVERT_FRAME_PP_PATH 3 /* divert frame for pp */ /* event typese sending to MCTL PP module */ #define MCTL_PP_EVENT_NOTUSED 0 @@ -275,7 +275,6 @@ struct msm_isp_cmd { #define VPE_SCALER_CONFIG_LEN 260 #define VPE_DIS_OFFSET_CFG_LEN 12 - #define CAPTURE_WIDTH 1280 #define IMEM_Y_SIZE (CAPTURE_WIDTH*16) #define IMEM_CBCR_SIZE (CAPTURE_WIDTH*8) @@ -286,7 +285,6 @@ struct msm_isp_cmd { #define IMEM_Y_PONG_OFFSET (IMEM_CBCR_PING_OFFSET + IMEM_CBCR_SIZE) #define IMEM_CBCR_PONG_OFFSET (IMEM_Y_PONG_OFFSET + IMEM_Y_SIZE) - struct msm_vpe_op_mode_cfg { uint8_t op_mode_cfg[VPE_OPERATION_MODE_CFG_LEN]; }; @@ -325,14 +323,14 @@ struct msm_vpe_clock_rate { uint32_t rate; }; struct msm_pp_crop { - uint32_t src_x; - uint32_t src_y; - uint32_t src_w; - uint32_t src_h; - uint32_t dst_x; - uint32_t dst_y; - uint32_t dst_w; - uint32_t dst_h; + uint32_t src_x; + uint32_t src_y; + uint32_t src_w; + uint32_t src_h; + uint32_t dst_x; + uint32_t dst_y; + uint32_t dst_w; + uint32_t dst_h; uint8_t update_flag; }; #define MSM_MCTL_PP_VPE_FRAME_ACK (1<<0) @@ -340,7 +338,7 @@ struct msm_pp_crop { struct msm_mctl_pp_frame_cmd { uint32_t cookie; - uint8_t vpe_output_action; + uint8_t vpe_output_action; uint32_t src_buf_handle; uint32_t dest_buf_handle; struct msm_pp_crop crop; @@ -368,4 +366,3 @@ struct msm_frame_info { }; #endif /*__MSM_ISP_H__*/ - |