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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _SDE_DRM_H_
#define _SDE_DRM_H_
#define SDE_MAX_PLANES 4
#define SDE_MAX_DE_CURVES 3
#define FILTER_EDGE_DIRECTED_2D 0x0
#define FILTER_CIRCULAR_2D 0x1
#define FILTER_SEPARABLE_1D 0x2
#define FILTER_BILINEAR 0x3
#define FILTER_ALPHA_DROP_REPEAT 0x0
#define FILTER_ALPHA_BILINEAR 0x1
#define FILTER_ALPHA_2D 0x3
#define FILTER_BLEND_CIRCULAR_2D 0x0
#define FILTER_BLEND_SEPARABLE_1D 0x1
#define SCALER_LUT_SWAP 0x1
#define SCALER_LUT_DIR_WR 0x2
#define SCALER_LUT_Y_CIR_WR 0x4
#define SCALER_LUT_UV_CIR_WR 0x8
#define SCALER_LUT_Y_SEP_WR 0x10
#define SCALER_LUT_UV_SEP_WR 0x20
#define SDE_DRM_BLEND_OP_NOT_DEFINED 0
#define SDE_DRM_BLEND_OP_OPAQUE 1
#define SDE_DRM_BLEND_OP_PREMULTIPLIED 2
#define SDE_DRM_BLEND_OP_COVERAGE 3
#define SDE_DRM_BLEND_OP_MAX 4
#define SDE_DRM_DEINTERLACE 0
#define SDE_DRM_BITMASK_COUNT 64
struct sde_drm_pix_ext_v1 {
int32_t num_ext_pxls_lr[SDE_MAX_PLANES];
int32_t num_ext_pxls_tb[SDE_MAX_PLANES];
int32_t left_ftch[SDE_MAX_PLANES];
int32_t right_ftch[SDE_MAX_PLANES];
int32_t top_ftch[SDE_MAX_PLANES];
int32_t btm_ftch[SDE_MAX_PLANES];
int32_t left_rpt[SDE_MAX_PLANES];
int32_t right_rpt[SDE_MAX_PLANES];
int32_t top_rpt[SDE_MAX_PLANES];
int32_t btm_rpt[SDE_MAX_PLANES];
};
#define SDE_DRM_SCALER_PIX_EXT 0x1
#define SDE_DRM_SCALER_SCALER_2 0x2
#define SDE_DRM_SCALER_SCALER_3 0x4
#define SDE_DRM_SCALER_DECIMATE 0x8
struct sde_drm_scaler_v1 {
uint32_t enable;
struct sde_drm_pix_ext_v1 pe;
uint32_t horz_decimate;
uint32_t vert_decimate;
int32_t init_phase_x[SDE_MAX_PLANES];
int32_t phase_step_x[SDE_MAX_PLANES];
int32_t init_phase_y[SDE_MAX_PLANES];
int32_t phase_step_y[SDE_MAX_PLANES];
uint32_t horz_filter[SDE_MAX_PLANES];
uint32_t vert_filter[SDE_MAX_PLANES];
};
struct sde_drm_de_v1 {
uint32_t enable;
int16_t sharpen_level1;
int16_t sharpen_level2;
uint16_t clip;
uint16_t limit;
uint16_t thr_quiet;
uint16_t thr_dieout;
uint16_t thr_low;
uint16_t thr_high;
uint16_t prec_shift;
int16_t adjust_a[SDE_MAX_DE_CURVES];
int16_t adjust_b[SDE_MAX_DE_CURVES];
int16_t adjust_c[SDE_MAX_DE_CURVES];
};
struct sde_drm_scaler_v2 {
uint32_t enable;
uint32_t dir_en;
struct sde_drm_pix_ext_v1 pe;
uint32_t horz_decimate;
uint32_t vert_decimate;
int32_t init_phase_x[SDE_MAX_PLANES];
int32_t phase_step_x[SDE_MAX_PLANES];
int32_t init_phase_y[SDE_MAX_PLANES];
int32_t phase_step_y[SDE_MAX_PLANES];
uint32_t preload_x[SDE_MAX_PLANES];
uint32_t preload_y[SDE_MAX_PLANES];
uint32_t src_width[SDE_MAX_PLANES];
uint32_t src_height[SDE_MAX_PLANES];
uint32_t dst_width;
uint32_t dst_height;
uint32_t y_rgb_filter_cfg;
uint32_t uv_filter_cfg;
uint32_t alpha_filter_cfg;
uint32_t blend_cfg;
uint32_t lut_flag;
uint32_t dir_lut_idx;
uint32_t y_rgb_cir_lut_idx;
uint32_t uv_cir_lut_idx;
uint32_t y_rgb_sep_lut_idx;
uint32_t uv_sep_lut_idx;
struct sde_drm_de_v1 de;
};
#define SDE_DRM_SCALER_V1 0x1
#define SDE_DRM_SCALER_VERSION SDE_DRM_SCALER_V1
struct sde_drm_scaler {
uint64_t version;
union {
struct sde_drm_scaler_v1 v1;
};
};
#define SDE_CSC_MATRIX_COEFF_SIZE 9
#define SDE_CSC_CLAMP_SIZE 6
#define SDE_CSC_BIAS_SIZE 3
#define SDE_DRM_CSC_V1 0x1
#define SDE_DRM_CSC_VERSION SDE_DRM_CSC_V1
struct sde_drm_csc_v1 {
int64_t ctm_coeff[SDE_CSC_MATRIX_COEFF_SIZE];
uint32_t pre_bias[SDE_CSC_BIAS_SIZE];
uint32_t post_bias[SDE_CSC_BIAS_SIZE];
uint32_t pre_clamp[SDE_CSC_CLAMP_SIZE];
uint32_t post_clamp[SDE_CSC_CLAMP_SIZE];
};
struct sde_drm_csc {
uint64_t version;
union {
struct sde_drm_csc_v1 v1;
};
};
#define SDE_DRM_WB_CFG 0x1
#define SDE_DRM_WB_CFG_FLAGS_CONNECTED (1 << 0)
struct sde_drm_wb_cfg {
uint32_t flags;
uint32_t connector_id;
uint32_t count_modes;
uint64_t modes;
};
#endif
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