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| author | Gustavo Diaz Prado <a0273371@ti.com> | 2012-08-31 15:11:37 -0500 |
|---|---|---|
| committer | Jason Simmons <jsimmons@google.com> | 2012-10-22 16:01:39 -0700 |
| commit | 8594f3edb1632ad900d7a5f06e2819e65114924b (patch) | |
| tree | f6b73bc6b16bae9c91038440f5e14a1f1e9d5ea4 | |
| parent | b05c5715bd7f2321c9783a2943a8b98c719944c8 (diff) | |
| download | omap4-aah-8594f3edb1632ad900d7a5f06e2819e65114924b.tar.gz | |
hwc: Fix incorrect tiler memory available check
When the buffers composed with DSS pipes use exactly the tiler1d
memory available (like 4 fullscreen layers on Tablet 2), the
prepare operation fails to assign a DSS pipe to the last buffer
(even if it was possible) making it to be rendered by the GPU
but without a pipe to show it. This patch fixes the incorrect
memory check that caused this problem.
Change-Id: Ibb147a468aa2e1622600a56f581013dc1e517777
Signed-off-by: Gustavo Diaz Prado <a0273371@ti.com>
Signed-off-by: Jonas Larsson <jonas.larsson@ti.com>
(cherry picked from commit a9606e762f54eb433880561548d0cb4498a3951e)
| -rw-r--r-- | hwc/hwc.c | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -1724,7 +1724,7 @@ static int omap4_hwc_prepare(struct hwc_composer_device_1 *dev, size_t numDispla is_protected(layer) || is_upscaled_NV12(hwc_dev, layer) || (hwc_dev->ext.current.docking && hwc_dev->ext.current.enabled && dockable(layer))) && - mem_used + mem1d(handle) < limits.tiler1d_slot_size && + mem_used + mem1d(handle) <= limits.tiler1d_slot_size && /* can't have a transparent overlay in the middle of the framebuffer stack */ !(is_BLENDED(layer) && fb_z >= 0) && /* current hardware is unable to keep up with more than 1 'large' RGB32 layer */ |