diff options
Diffstat (limited to 'share/man')
29 files changed, 51285 insertions, 0 deletions
diff --git a/share/man/man1/arm-eabi-addr2line.1 b/share/man/man1/arm-eabi-addr2line.1 new file mode 100644 index 0000000..c25f729 --- /dev/null +++ b/share/man/man1/arm-eabi-addr2line.1 @@ -0,0 +1,287 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "ADDR2LINE 1" +.TH ADDR2LINE 1 " " "binutils-2.21" "GNU Development Tools" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +addr2line \- convert addresses into file names and line numbers. +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +addr2line [\fB\-a\fR|\fB\-\-addresses\fR] + [\fB\-b\fR \fIbfdname\fR|\fB\-\-target=\fR\fIbfdname\fR] + [\fB\-C\fR|\fB\-\-demangle\fR[=\fIstyle\fR]] + [\fB\-e\fR \fIfilename\fR|\fB\-\-exe=\fR\fIfilename\fR] + [\fB\-f\fR|\fB\-\-functions\fR] [\fB\-s\fR|\fB\-\-basename\fR] + [\fB\-i\fR|\fB\-\-inlines\fR] + [\fB\-p\fR|\fB\-\-pretty\-print\fR] + [\fB\-j\fR|\fB\-\-section=\fR\fIname\fR] + [\fB\-H\fR|\fB\-\-help\fR] [\fB\-V\fR|\fB\-\-version\fR] + [addr addr ...] +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +\&\fBaddr2line\fR translates addresses into file names and line numbers. +Given an address in an executable or an offset in a section of a relocatable +object, it uses the debugging information to figure out which file name and +line number are associated with it. +.PP +The executable or relocatable object to use is specified with the \fB\-e\fR +option. The default is the file \fIa.out\fR. The section in the relocatable +object to use is specified with the \fB\-j\fR option. +.PP +\&\fBaddr2line\fR has two modes of operation. +.PP +In the first, hexadecimal addresses are specified on the command line, +and \fBaddr2line\fR displays the file name and line number for each +address. +.PP +In the second, \fBaddr2line\fR reads hexadecimal addresses from +standard input, and prints the file name and line number for each +address on standard output. In this mode, \fBaddr2line\fR may be used +in a pipe to convert dynamically chosen addresses. +.PP +The format of the output is \fB\s-1FILENAME:LINENO\s0\fR. The file name and +line number for each address is printed on a separate line. If the +\&\fB\-f\fR option is used, then each \fB\s-1FILENAME:LINENO\s0\fR line is +preceded by a \fB\s-1FUNCTIONNAME\s0\fR line which is the name of the function +containing the address. If the \fB\-a\fR option is used, then the +address read is first printed. +.PP +If the file name or function name can not be determined, +\&\fBaddr2line\fR will print two question marks in their place. If the +line number can not be determined, \fBaddr2line\fR will print 0. +.SH "OPTIONS" +.IX Header "OPTIONS" +The long and short forms of options, shown here as alternatives, are +equivalent. +.IP "\fB\-a\fR" 4 +.IX Item "-a" +.PD 0 +.IP "\fB\-\-addresses\fR" 4 +.IX Item "--addresses" +.PD +Display address before function names or file and line number +information. The address is printed with a \fB0x\fR prefix to easily +identify it. +.IP "\fB\-b\fR \fIbfdname\fR" 4 +.IX Item "-b bfdname" +.PD 0 +.IP "\fB\-\-target=\fR\fIbfdname\fR" 4 +.IX Item "--target=bfdname" +.PD +Specify that the object-code format for the object files is +\&\fIbfdname\fR. +.IP "\fB\-C\fR" 4 +.IX Item "-C" +.PD 0 +.IP "\fB\-\-demangle[=\fR\fIstyle\fR\fB]\fR" 4 +.IX Item "--demangle[=style]" +.PD +Decode (\fIdemangle\fR) low-level symbol names into user-level names. +Besides removing any initial underscore prepended by the system, this +makes \*(C+ function names readable. Different compilers have different +mangling styles. The optional demangling style argument can be used to +choose an appropriate demangling style for your compiler. +.IP "\fB\-e\fR \fIfilename\fR" 4 +.IX Item "-e filename" +.PD 0 +.IP "\fB\-\-exe=\fR\fIfilename\fR" 4 +.IX Item "--exe=filename" +.PD +Specify the name of the executable for which addresses should be +translated. The default file is \fIa.out\fR. +.IP "\fB\-f\fR" 4 +.IX Item "-f" +.PD 0 +.IP "\fB\-\-functions\fR" 4 +.IX Item "--functions" +.PD +Display function names as well as file and line number information. +.IP "\fB\-s\fR" 4 +.IX Item "-s" +.PD 0 +.IP "\fB\-\-basenames\fR" 4 +.IX Item "--basenames" +.PD +Display only the base of each file name. +.IP "\fB\-i\fR" 4 +.IX Item "-i" +.PD 0 +.IP "\fB\-\-inlines\fR" 4 +.IX Item "--inlines" +.PD +If the address belongs to a function that was inlined, the source +information for all enclosing scopes back to the first non-inlined +function will also be printed. For example, if \f(CW\*(C`main\*(C'\fR inlines +\&\f(CW\*(C`callee1\*(C'\fR which inlines \f(CW\*(C`callee2\*(C'\fR, and address is from +\&\f(CW\*(C`callee2\*(C'\fR, the source information for \f(CW\*(C`callee1\*(C'\fR and \f(CW\*(C`main\*(C'\fR +will also be printed. +.IP "\fB\-j\fR" 4 +.IX Item "-j" +.PD 0 +.IP "\fB\-\-section\fR" 4 +.IX Item "--section" +.PD +Read offsets relative to the specified section instead of absolute addresses. +.IP "\fB\-p\fR" 4 +.IX Item "-p" +.PD 0 +.IP "\fB\-\-pretty\-print\fR" 4 +.IX Item "--pretty-print" +.PD +Make the output more human friendly: each location are printed on one line. +If option \fB\-i\fR is specified, lines for all enclosing scopes are +prefixed with \fB(inlined by)\fR. +.IP "\fB@\fR\fIfile\fR" 4 +.IX Item "@file" +Read command-line options from \fIfile\fR. The options read are +inserted in place of the original @\fIfile\fR option. If \fIfile\fR +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +.Sp +Options in \fIfile\fR are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The \fIfile\fR may itself contain additional +@\fIfile\fR options; any such options will be processed recursively. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +Info entries for \fIbinutils\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 +or any later version published by the Free Software Foundation; +with no Invariant Sections, with no Front-Cover Texts, and with no +Back-Cover Texts. A copy of the license is included in the +section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". diff --git a/share/man/man1/arm-eabi-ar.1 b/share/man/man1/arm-eabi-ar.1 new file mode 100644 index 0000000..f93bb5c --- /dev/null +++ b/share/man/man1/arm-eabi-ar.1 @@ -0,0 +1,428 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "AR 1" +.TH AR 1 " " "binutils-2.21" "GNU Development Tools" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +ar \- create, modify, and extract from archives +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +ar [\fB\-\-plugin\fR \fIname\fR] [\fB\-X32_64\fR] [\fB\-\fR]\fIp\fR[\fImod\fR [\fIrelpos\fR] [\fIcount\fR]] \fIarchive\fR [\fImember\fR...] +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +The \s-1GNU\s0 \fBar\fR program creates, modifies, and extracts from +archives. An \fIarchive\fR is a single file holding a collection of +other files in a structure that makes it possible to retrieve +the original individual files (called \fImembers\fR of the archive). +.PP +The original files' contents, mode (permissions), timestamp, owner, and +group are preserved in the archive, and can be restored on +extraction. +.PP +\&\s-1GNU\s0 \fBar\fR can maintain archives whose members have names of any +length; however, depending on how \fBar\fR is configured on your +system, a limit on member-name length may be imposed for compatibility +with archive formats maintained with other tools. If it exists, the +limit is often 15 characters (typical of formats related to a.out) or 16 +characters (typical of formats related to coff). +.PP +\&\fBar\fR is considered a binary utility because archives of this sort +are most often used as \fIlibraries\fR holding commonly needed +subroutines. +.PP +\&\fBar\fR creates an index to the symbols defined in relocatable +object modules in the archive when you specify the modifier \fBs\fR. +Once created, this index is updated in the archive whenever \fBar\fR +makes a change to its contents (save for the \fBq\fR update operation). +An archive with such an index speeds up linking to the library, and +allows routines in the library to call each other without regard to +their placement in the archive. +.PP +You may use \fBnm \-s\fR or \fBnm \-\-print\-armap\fR to list this index +table. If an archive lacks the table, another form of \fBar\fR called +\&\fBranlib\fR can be used to add just the table. +.PP +\&\s-1GNU\s0 \fBar\fR can optionally create a \fIthin\fR archive, +which contains a symbol index and references to the original copies +of the member files of the archives. Such an archive is useful +for building libraries for use within a local build, where the +relocatable objects are expected to remain available, and copying the +contents of each object would only waste time and space. Thin archives +are also \fIflattened\fR, so that adding one or more archives to a +thin archive will add the elements of the nested archive individually. +The paths to the elements of the archive are stored relative to the +archive itself. +.PP +\&\s-1GNU\s0 \fBar\fR is designed to be compatible with two different +facilities. You can control its activity using command-line options, +like the different varieties of \fBar\fR on Unix systems; or, if you +specify the single command-line option \fB\-M\fR, you can control it +with a script supplied via standard input, like the \s-1MRI\s0 \*(L"librarian\*(R" +program. +.SH "OPTIONS" +.IX Header "OPTIONS" +\&\s-1GNU\s0 \fBar\fR allows you to mix the operation code \fIp\fR and modifier +flags \fImod\fR in any order, within the first command-line argument. +.PP +If you wish, you may begin the first command-line argument with a +dash. +.PP +The \fIp\fR keyletter specifies what operation to execute; it may be +any of the following, but you must specify only one of them: +.IP "\fBd\fR" 4 +.IX Item "d" +\&\fIDelete\fR modules from the archive. Specify the names of modules to +be deleted as \fImember\fR...; the archive is untouched if you +specify no files to delete. +.Sp +If you specify the \fBv\fR modifier, \fBar\fR lists each module +as it is deleted. +.IP "\fBm\fR" 4 +.IX Item "m" +Use this operation to \fImove\fR members in an archive. +.Sp +The ordering of members in an archive can make a difference in how +programs are linked using the library, if a symbol is defined in more +than one member. +.Sp +If no modifiers are used with \f(CW\*(C`m\*(C'\fR, any members you name in the +\&\fImember\fR arguments are moved to the \fIend\fR of the archive; +you can use the \fBa\fR, \fBb\fR, or \fBi\fR modifiers to move them to a +specified place instead. +.IP "\fBp\fR" 4 +.IX Item "p" +\&\fIPrint\fR the specified members of the archive, to the standard +output file. If the \fBv\fR modifier is specified, show the member +name before copying its contents to standard output. +.Sp +If you specify no \fImember\fR arguments, all the files in the archive are +printed. +.IP "\fBq\fR" 4 +.IX Item "q" +\&\fIQuick append\fR; Historically, add the files \fImember\fR... to the end of +\&\fIarchive\fR, without checking for replacement. +.Sp +The modifiers \fBa\fR, \fBb\fR, and \fBi\fR do \fInot\fR affect this +operation; new members are always placed at the end of the archive. +.Sp +The modifier \fBv\fR makes \fBar\fR list each file as it is appended. +.Sp +Since the point of this operation is speed, the archive's symbol table +index is not updated, even if it already existed; you can use \fBar s\fR or +\&\fBranlib\fR explicitly to update the symbol table index. +.Sp +However, too many different systems assume quick append rebuilds the +index, so \s-1GNU\s0 \fBar\fR implements \fBq\fR as a synonym for \fBr\fR. +.IP "\fBr\fR" 4 +.IX Item "r" +Insert the files \fImember\fR... into \fIarchive\fR (with +\&\fIreplacement\fR). This operation differs from \fBq\fR in that any +previously existing members are deleted if their names match those being +added. +.Sp +If one of the files named in \fImember\fR... does not exist, \fBar\fR +displays an error message, and leaves undisturbed any existing members +of the archive matching that name. +.Sp +By default, new members are added at the end of the file; but you may +use one of the modifiers \fBa\fR, \fBb\fR, or \fBi\fR to request +placement relative to some existing member. +.Sp +The modifier \fBv\fR used with this operation elicits a line of +output for each file inserted, along with one of the letters \fBa\fR or +\&\fBr\fR to indicate whether the file was appended (no old member +deleted) or replaced. +.IP "\fBs\fR" 4 +.IX Item "s" +Add an index to the archive, or update it if it already exists. Note +this command is an exception to the rule that there can only be one +command letter, as it is possible to use it as either a command or a +modifier. In either case it does the same thing. +.IP "\fBt\fR" 4 +.IX Item "t" +Display a \fItable\fR listing the contents of \fIarchive\fR, or those +of the files listed in \fImember\fR... that are present in the +archive. Normally only the member name is shown; if you also want to +see the modes (permissions), timestamp, owner, group, and size, you can +request that by also specifying the \fBv\fR modifier. +.Sp +If you do not specify a \fImember\fR, all files in the archive +are listed. +.Sp +If there is more than one file with the same name (say, \fBfie\fR) in +an archive (say \fBb.a\fR), \fBar t b.a fie\fR lists only the +first instance; to see them all, you must ask for a complete +listing\-\-\-in our example, \fBar t b.a\fR. +.IP "\fBx\fR" 4 +.IX Item "x" +\&\fIExtract\fR members (named \fImember\fR) from the archive. You can +use the \fBv\fR modifier with this operation, to request that +\&\fBar\fR list each name as it extracts it. +.Sp +If you do not specify a \fImember\fR, all files in the archive +are extracted. +.Sp +Files cannot be extracted from a thin archive. +.PP +A number of modifiers (\fImod\fR) may immediately follow the \fIp\fR +keyletter, to specify variations on an operation's behavior: +.IP "\fBa\fR" 4 +.IX Item "a" +Add new files \fIafter\fR an existing member of the +archive. If you use the modifier \fBa\fR, the name of an existing archive +member must be present as the \fIrelpos\fR argument, before the +\&\fIarchive\fR specification. +.IP "\fBb\fR" 4 +.IX Item "b" +Add new files \fIbefore\fR an existing member of the +archive. If you use the modifier \fBb\fR, the name of an existing archive +member must be present as the \fIrelpos\fR argument, before the +\&\fIarchive\fR specification. (same as \fBi\fR). +.IP "\fBc\fR" 4 +.IX Item "c" +\&\fICreate\fR the archive. The specified \fIarchive\fR is always +created if it did not exist, when you request an update. But a warning is +issued unless you specify in advance that you expect to create it, by +using this modifier. +.IP "\fBD\fR" 4 +.IX Item "D" +Operate in \fIdeterministic\fR mode. When adding files and the archive +index use zero for UIDs, GIDs, timestamps, and use consistent file modes +for all files. When this option is used, if \fBar\fR is used with +identical options and identical input files, multiple runs will create +identical output files regardless of the input files' owners, groups, +file modes, or modification times. +.IP "\fBf\fR" 4 +.IX Item "f" +Truncate names in the archive. \s-1GNU\s0 \fBar\fR will normally permit file +names of any length. This will cause it to create archives which are +not compatible with the native \fBar\fR program on some systems. If +this is a concern, the \fBf\fR modifier may be used to truncate file +names when putting them in the archive. +.IP "\fBi\fR" 4 +.IX Item "i" +Insert new files \fIbefore\fR an existing member of the +archive. If you use the modifier \fBi\fR, the name of an existing archive +member must be present as the \fIrelpos\fR argument, before the +\&\fIarchive\fR specification. (same as \fBb\fR). +.IP "\fBl\fR" 4 +.IX Item "l" +This modifier is accepted but not used. +.IP "\fBN\fR" 4 +.IX Item "N" +Uses the \fIcount\fR parameter. This is used if there are multiple +entries in the archive with the same name. Extract or delete instance +\&\fIcount\fR of the given name from the archive. +.IP "\fBo\fR" 4 +.IX Item "o" +Preserve the \fIoriginal\fR dates of members when extracting them. If +you do not specify this modifier, files extracted from the archive +are stamped with the time of extraction. +.IP "\fBP\fR" 4 +.IX Item "P" +Use the full path name when matching names in the archive. \s-1GNU\s0 +\&\fBar\fR can not create an archive with a full path name (such archives +are not \s-1POSIX\s0 complaint), but other archive creators can. This option +will cause \s-1GNU\s0 \fBar\fR to match file names using a complete path +name, which can be convenient when extracting a single file from an +archive created by another tool. +.IP "\fBs\fR" 4 +.IX Item "s" +Write an object-file index into the archive, or update an existing one, +even if no other change is made to the archive. You may use this modifier +flag either with any operation, or alone. Running \fBar s\fR on an +archive is equivalent to running \fBranlib\fR on it. +.IP "\fBS\fR" 4 +.IX Item "S" +Do not generate an archive symbol table. This can speed up building a +large library in several steps. The resulting archive can not be used +with the linker. In order to build a symbol table, you must omit the +\&\fBS\fR modifier on the last execution of \fBar\fR, or you must run +\&\fBranlib\fR on the archive. +.IP "\fBT\fR" 4 +.IX Item "T" +Make the specified \fIarchive\fR a \fIthin\fR archive. If it already +exists and is a regular archive, the existing members must be present +in the same directory as \fIarchive\fR. +.IP "\fBu\fR" 4 +.IX Item "u" +Normally, \fBar r\fR... inserts all files +listed into the archive. If you would like to insert \fIonly\fR those +of the files you list that are newer than existing members of the same +names, use this modifier. The \fBu\fR modifier is allowed only for the +operation \fBr\fR (replace). In particular, the combination \fBqu\fR is +not allowed, since checking the timestamps would lose any speed +advantage from the operation \fBq\fR. +.IP "\fBv\fR" 4 +.IX Item "v" +This modifier requests the \fIverbose\fR version of an operation. Many +operations display additional information, such as filenames processed, +when the modifier \fBv\fR is appended. +.IP "\fBV\fR" 4 +.IX Item "V" +This modifier shows the version number of \fBar\fR. +.PP +\&\fBar\fR ignores an initial option spelt \fB\-X32_64\fR, for +compatibility with \s-1AIX\s0. The behaviour produced by this option is the +default for \s-1GNU\s0 \fBar\fR. \fBar\fR does not support any of the other +\&\fB\-X\fR options; in particular, it does not support \fB\-X32\fR +which is the default for \s-1AIX\s0 \fBar\fR. +.PP +The optional command line switch \fB\-\-plugin\fR \fIname\fR causes +\&\fBar\fR to load the plugin called \fIname\fR which adds support +for more file formats. This option is only available if the toolchain +has been built with plugin support enabled. +.IP "\fB@\fR\fIfile\fR" 4 +.IX Item "@file" +Read command-line options from \fIfile\fR. The options read are +inserted in place of the original @\fIfile\fR option. If \fIfile\fR +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +.Sp +Options in \fIfile\fR are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The \fIfile\fR may itself contain additional +@\fIfile\fR options; any such options will be processed recursively. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fInm\fR\|(1), \fIranlib\fR\|(1), and the Info entries for \fIbinutils\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 +or any later version published by the Free Software Foundation; +with no Invariant Sections, with no Front-Cover Texts, and with no +Back-Cover Texts. A copy of the license is included in the +section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". diff --git a/share/man/man1/arm-eabi-as.1 b/share/man/man1/arm-eabi-as.1 new file mode 100644 index 0000000..3223590 --- /dev/null +++ b/share/man/man1/arm-eabi-as.1 @@ -0,0 +1,1321 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "AS 1" +.TH AS 1 " " "binutils-2.21" "GNU Development Tools" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +AS \- the portable GNU assembler. +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-\-alternate\fR] [\fB\-D\fR] + [\fB\-\-compress\-debug\-sections\fR] [\fB\-\-nocompress\-debug\-sections\fR] + [\fB\-\-debug\-prefix\-map\fR \fIold\fR=\fInew\fR] + [\fB\-\-defsym\fR \fIsym\fR=\fIval\fR] [\fB\-f\fR] [\fB\-g\fR] [\fB\-\-gstabs\fR] + [\fB\-\-gstabs+\fR] [\fB\-\-gdwarf\-2\fR] [\fB\-\-help\fR] [\fB\-I\fR \fIdir\fR] [\fB\-J\fR] + [\fB\-K\fR] [\fB\-L\fR] [\fB\-\-listing\-lhs\-width\fR=\fI\s-1NUM\s0\fR] + [\fB\-\-listing\-lhs\-width2\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-rhs\-width\fR=\fI\s-1NUM\s0\fR] + [\fB\-\-listing\-cont\-lines\fR=\fI\s-1NUM\s0\fR] [\fB\-\-keep\-locals\fR] [\fB\-o\fR + \fIobjfile\fR] [\fB\-R\fR] [\fB\-\-reduce\-memory\-overheads\fR] [\fB\-\-statistics\fR] + [\fB\-v\fR] [\fB\-version\fR] [\fB\-\-version\fR] [\fB\-W\fR] [\fB\-\-warn\fR] + [\fB\-\-fatal\-warnings\fR] [\fB\-w\fR] [\fB\-x\fR] [\fB\-Z\fR] [\fB@\fR\fI\s-1FILE\s0\fR] + [\fB\-\-target\-help\fR] [\fItarget-options\fR] + [\fB\-\-\fR|\fIfiles\fR ...] +.PP +\&\fITarget Alpha options:\fR + [\fB\-m\fR\fIcpu\fR] + [\fB\-mdebug\fR | \fB\-no\-mdebug\fR] + [\fB\-replace\fR | \fB\-noreplace\fR] + [\fB\-relax\fR] [\fB\-g\fR] [\fB\-G\fR\fIsize\fR] + [\fB\-F\fR] [\fB\-32addr\fR] +.PP +\&\fITarget \s-1ARC\s0 options:\fR + [\fB\-marc[5|6|7|8]\fR] + [\fB\-EB\fR|\fB\-EL\fR] +.PP +\&\fITarget \s-1ARM\s0 options:\fR + [\fB\-mcpu\fR=\fIprocessor\fR[+\fIextension\fR...]] + [\fB\-march\fR=\fIarchitecture\fR[+\fIextension\fR...]] + [\fB\-mfpu\fR=\fIfloating-point-format\fR] + [\fB\-mfloat\-abi\fR=\fIabi\fR] + [\fB\-meabi\fR=\fIver\fR] + [\fB\-mthumb\fR] + [\fB\-EB\fR|\fB\-EL\fR] + [\fB\-mapcs\-32\fR|\fB\-mapcs\-26\fR|\fB\-mapcs\-float\fR| + \fB\-mapcs\-reentrant\fR] + [\fB\-mthumb\-interwork\fR] [\fB\-k\fR] +.PP +\&\fITarget Blackfin options:\fR + [\fB\-mcpu\fR=\fIprocessor\fR[\-\fIsirevision\fR]] + [\fB\-mfdpic\fR] + [\fB\-mno\-fdpic\fR] + [\fB\-mnopic\fR] +.PP +\&\fITarget \s-1CRIS\s0 options:\fR + [\fB\-\-underscore\fR | \fB\-\-no\-underscore\fR] + [\fB\-\-pic\fR] [\fB\-N\fR] + [\fB\-\-emulation=criself\fR | \fB\-\-emulation=crisaout\fR] + [\fB\-\-march=v0_v10\fR | \fB\-\-march=v10\fR | \fB\-\-march=v32\fR | \fB\-\-march=common_v10_v32\fR] +.PP +\&\fITarget D10V options:\fR + [\fB\-O\fR] +.PP +\&\fITarget D30V options:\fR + [\fB\-O\fR|\fB\-n\fR|\fB\-N\fR] +.PP +\&\fITarget H8/300 options:\fR + [\-h\-tick\-hex] +.PP +\&\fITarget i386 options:\fR + [\fB\-\-32\fR|\fB\-\-64\fR] [\fB\-n\fR] + [\fB\-march\fR=\fI\s-1CPU\s0\fR[+\fI\s-1EXTENSION\s0\fR...]] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR] +.PP +\&\fITarget i960 options:\fR + [\fB\-ACA\fR|\fB\-ACA_A\fR|\fB\-ACB\fR|\fB\-ACC\fR|\fB\-AKA\fR|\fB\-AKB\fR| + \fB\-AKC\fR|\fB\-AMC\fR] + [\fB\-b\fR] [\fB\-no\-relax\fR] +.PP +\&\fITarget \s-1IA\-64\s0 options:\fR + [\fB\-mconstant\-gp\fR|\fB\-mauto\-pic\fR] + [\fB\-milp32\fR|\fB\-milp64\fR|\fB\-mlp64\fR|\fB\-mp64\fR] + [\fB\-mle\fR|\fBmbe\fR] + [\fB\-mtune=itanium1\fR|\fB\-mtune=itanium2\fR] + [\fB\-munwind\-check=warning\fR|\fB\-munwind\-check=error\fR] + [\fB\-mhint.b=ok\fR|\fB\-mhint.b=warning\fR|\fB\-mhint.b=error\fR] + [\fB\-x\fR|\fB\-xexplicit\fR] [\fB\-xauto\fR] [\fB\-xdebug\fR] +.PP +\&\fITarget \s-1IP2K\s0 options:\fR + [\fB\-mip2022\fR|\fB\-mip2022ext\fR] +.PP +\&\fITarget M32C options:\fR + [\fB\-m32c\fR|\fB\-m16c\fR] [\-relax] [\-h\-tick\-hex] +.PP +\&\fITarget M32R options:\fR + [\fB\-\-m32rx\fR|\fB\-\-[no\-]warn\-explicit\-parallel\-conflicts\fR| + \fB\-\-W[n]p\fR] +.PP +\&\fITarget M680X0 options:\fR + [\fB\-l\fR] [\fB\-m68000\fR|\fB\-m68010\fR|\fB\-m68020\fR|...] +.PP +\&\fITarget M68HC11 options:\fR + [\fB\-m68hc11\fR|\fB\-m68hc12\fR|\fB\-m68hcs12\fR] + [\fB\-mshort\fR|\fB\-mlong\fR] + [\fB\-mshort\-double\fR|\fB\-mlong\-double\fR] + [\fB\-\-force\-long\-branches\fR] [\fB\-\-short\-branches\fR] + [\fB\-\-strict\-direct\-mode\fR] [\fB\-\-print\-insn\-syntax\fR] + [\fB\-\-print\-opcodes\fR] [\fB\-\-generate\-example\fR] +.PP +\&\fITarget \s-1MCORE\s0 options:\fR + [\fB\-jsri2bsr\fR] [\fB\-sifilter\fR] [\fB\-relax\fR] + [\fB\-mcpu=[210|340]\fR] +\&\fITarget \s-1MICROBLAZE\s0 options:\fR +.PP +\&\fITarget \s-1MIPS\s0 options:\fR + [\fB\-nocpp\fR] [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-O\fR[\fIoptimization level\fR]] + [\fB\-g\fR[\fIdebug level\fR]] [\fB\-G\fR \fInum\fR] [\fB\-KPIC\fR] [\fB\-call_shared\fR] + [\fB\-non_shared\fR] [\fB\-xgot\fR [\fB\-mvxworks\-pic\fR] + [\fB\-mabi\fR=\fI\s-1ABI\s0\fR] [\fB\-32\fR] [\fB\-n32\fR] [\fB\-64\fR] [\fB\-mfp32\fR] [\fB\-mgp32\fR] + [\fB\-march\fR=\fI\s-1CPU\s0\fR] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR] [\fB\-mips1\fR] [\fB\-mips2\fR] + [\fB\-mips3\fR] [\fB\-mips4\fR] [\fB\-mips5\fR] [\fB\-mips32\fR] [\fB\-mips32r2\fR] + [\fB\-mips64\fR] [\fB\-mips64r2\fR] + [\fB\-construct\-floats\fR] [\fB\-no\-construct\-floats\fR] + [\fB\-trap\fR] [\fB\-no\-break\fR] [\fB\-break\fR] [\fB\-no\-trap\fR] + [\fB\-mips16\fR] [\fB\-no\-mips16\fR] + [\fB\-msmartmips\fR] [\fB\-mno\-smartmips\fR] + [\fB\-mips3d\fR] [\fB\-no\-mips3d\fR] + [\fB\-mdmx\fR] [\fB\-no\-mdmx\fR] + [\fB\-mdsp\fR] [\fB\-mno\-dsp\fR] + [\fB\-mdspr2\fR] [\fB\-mno\-dspr2\fR] + [\fB\-mmt\fR] [\fB\-mno\-mt\fR] + [\fB\-mfix7000\fR] [\fB\-mno\-fix7000\fR] + [\fB\-mfix\-vr4120\fR] [\fB\-mno\-fix\-vr4120\fR] + [\fB\-mfix\-vr4130\fR] [\fB\-mno\-fix\-vr4130\fR] + [\fB\-mdebug\fR] [\fB\-no\-mdebug\fR] + [\fB\-mpdr\fR] [\fB\-mno\-pdr\fR] +.PP +\&\fITarget \s-1MMIX\s0 options:\fR + [\fB\-\-fixed\-special\-register\-names\fR] [\fB\-\-globalize\-symbols\fR] + [\fB\-\-gnu\-syntax\fR] [\fB\-\-relax\fR] [\fB\-\-no\-predefined\-symbols\fR] + [\fB\-\-no\-expand\fR] [\fB\-\-no\-merge\-gregs\fR] [\fB\-x\fR] + [\fB\-\-linker\-allocated\-gregs\fR] +.PP +\&\fITarget \s-1PDP11\s0 options:\fR + [\fB\-mpic\fR|\fB\-mno\-pic\fR] [\fB\-mall\fR] [\fB\-mno\-extensions\fR] + [\fB\-m\fR\fIextension\fR|\fB\-mno\-\fR\fIextension\fR] + [\fB\-m\fR\fIcpu\fR] [\fB\-m\fR\fImachine\fR] +.PP +\&\fITarget picoJava options:\fR + [\fB\-mb\fR|\fB\-me\fR] +.PP +\&\fITarget PowerPC options:\fR + [\fB\-mpwrx\fR|\fB\-mpwr2\fR|\fB\-mpwr\fR|\fB\-m601\fR|\fB\-mppc\fR|\fB\-mppc32\fR|\fB\-m603\fR|\fB\-m604\fR| + \fB\-m403\fR|\fB\-m405\fR|\fB\-mppc64\fR|\fB\-m620\fR|\fB\-mppc64bridge\fR|\fB\-mbooke\fR] + [\fB\-mcom\fR|\fB\-many\fR|\fB\-maltivec\fR|\fB\-mvsx\fR] [\fB\-memb\fR] + [\fB\-mregnames\fR|\fB\-mno\-regnames\fR] + [\fB\-mrelocatable\fR|\fB\-mrelocatable\-lib\fR] + [\fB\-mlittle\fR|\fB\-mlittle\-endian\fR|\fB\-mbig\fR|\fB\-mbig\-endian\fR] + [\fB\-msolaris\fR|\fB\-mno\-solaris\fR] +.PP +\&\fITarget \s-1RX\s0 options:\fR + [\fB\-mlittle\-endian\fR|\fB\-mbig\-endian\fR] + [\fB\-m32bit\-ints\fR|\fB\-m16bit\-ints\fR] + [\fB\-m32bit\-doubles\fR|\fB\-m64bit\-doubles\fR] +.PP +\&\fITarget s390 options:\fR + [\fB\-m31\fR|\fB\-m64\fR] [\fB\-mesa\fR|\fB\-mzarch\fR] [\fB\-march\fR=\fI\s-1CPU\s0\fR] + [\fB\-mregnames\fR|\fB\-mno\-regnames\fR] + [\fB\-mwarn\-areg\-zero\fR] +.PP +\&\fITarget \s-1SCORE\s0 options:\fR + [\fB\-EB\fR][\fB\-EL\fR][\fB\-FIXDD\fR][\fB\-NWARN\fR] + [\fB\-SCORE5\fR][\fB\-SCORE5U\fR][\fB\-SCORE7\fR][\fB\-SCORE3\fR] + [\fB\-march=score7\fR][\fB\-march=score3\fR] + [\fB\-USE_R1\fR][\fB\-KPIC\fR][\fB\-O0\fR][\fB\-G\fR \fInum\fR][\fB\-V\fR] +.PP +\&\fITarget \s-1SPARC\s0 options:\fR + [\fB\-Av6\fR|\fB\-Av7\fR|\fB\-Av8\fR|\fB\-Asparclet\fR|\fB\-Asparclite\fR + \fB\-Av8plus\fR|\fB\-Av8plusa\fR|\fB\-Av9\fR|\fB\-Av9a\fR] + [\fB\-xarch=v8plus\fR|\fB\-xarch=v8plusa\fR] [\fB\-bump\fR] + [\fB\-32\fR|\fB\-64\fR] +.PP +\&\fITarget \s-1TIC54X\s0 options:\fR + [\fB\-mcpu=54[123589]\fR|\fB\-mcpu=54[56]lp\fR] [\fB\-mfar\-mode\fR|\fB\-mf\fR] + [\fB\-merrors\-to\-file\fR \fI<filename>\fR|\fB\-me\fR \fI<filename>\fR] +.PP +\&\fITarget \s-1TIC6X\s0 options:\fR + [\fB\-march=\fR\fIarch\fR] [\fB\-matomic\fR|\fB\-mno\-atomic\fR] + [\fB\-mbig\-endian\fR|\fB\-mlittle\-endian\fR] [\fB\-mdsbt\fR|\fB\-mno\-dsbt\fR] + [\fB\-mpid=no\fR|\fB\-mpid=near\fR|\fB\-mpid=far\fR] [\fB\-mpic\fR|\fB\-mno\-pic\fR] +.PP +\&\fITarget Z80 options:\fR + [\fB\-z80\fR] [\fB\-r800\fR] + [ \fB\-ignore\-undocumented\-instructions\fR] [\fB\-Wnud\fR] + [ \fB\-ignore\-unportable\-instructions\fR] [\fB\-Wnup\fR] + [ \fB\-warn\-undocumented\-instructions\fR] [\fB\-Wud\fR] + [ \fB\-warn\-unportable\-instructions\fR] [\fB\-Wup\fR] + [ \fB\-forbid\-undocumented\-instructions\fR] [\fB\-Fud\fR] + [ \fB\-forbid\-unportable\-instructions\fR] [\fB\-Fup\fR] +.PP +\&\fITarget Xtensa options:\fR + [\fB\-\-[no\-]text\-section\-literals\fR] [\fB\-\-[no\-]absolute\-literals\fR] + [\fB\-\-[no\-]target\-align\fR] [\fB\-\-[no\-]longcalls\fR] + [\fB\-\-[no\-]transform\fR] + [\fB\-\-rename\-section\fR \fIoldname\fR=\fInewname\fR] +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +\&\s-1GNU\s0 \fBas\fR is really a family of assemblers. +If you use (or have used) the \s-1GNU\s0 assembler on one architecture, you +should find a fairly similar environment when you use it on another +architecture. Each version has much in common with the others, +including object file formats, most assembler directives (often called +\&\fIpseudo-ops\fR) and assembler syntax. +.PP +\&\fBas\fR is primarily intended to assemble the output of the +\&\s-1GNU\s0 C compiler \f(CW\*(C`gcc\*(C'\fR for use by the linker +\&\f(CW\*(C`ld\*(C'\fR. Nevertheless, we've tried to make \fBas\fR +assemble correctly everything that other assemblers for the same +machine would assemble. +Any exceptions are documented explicitly. +This doesn't mean \fBas\fR always uses the same syntax as another +assembler for the same architecture; for example, we know of several +incompatible versions of 680x0 assembly language syntax. +.PP +Each time you run \fBas\fR it assembles exactly one source +program. The source program is made up of one or more files. +(The standard input is also a file.) +.PP +You give \fBas\fR a command line that has zero or more input file +names. The input files are read (from left file name to right). A +command line argument (in any position) that has no special meaning +is taken to be an input file name. +.PP +If you give \fBas\fR no file names it attempts to read one input file +from the \fBas\fR standard input, which is normally your terminal. You +may have to type \fBctl-D\fR to tell \fBas\fR there is no more program +to assemble. +.PP +Use \fB\-\-\fR if you need to explicitly name the standard input file +in your command line. +.PP +If the source is empty, \fBas\fR produces a small, empty object +file. +.PP +\&\fBas\fR may write warnings and error messages to the standard error +file (usually your terminal). This should not happen when a compiler +runs \fBas\fR automatically. Warnings report an assumption made so +that \fBas\fR could keep assembling a flawed program; errors report a +grave problem that stops the assembly. +.PP +If you are invoking \fBas\fR via the \s-1GNU\s0 C compiler, +you can use the \fB\-Wa\fR option to pass arguments through to the assembler. +The assembler arguments must be separated from each other (and the \fB\-Wa\fR) +by commas. For example: +.PP +.Vb 1 +\& gcc \-c \-g \-O \-Wa,\-alh,\-L file.c +.Ve +.PP +This passes two options to the assembler: \fB\-alh\fR (emit a listing to +standard output with high-level and assembly source) and \fB\-L\fR (retain +local symbols in the symbol table). +.PP +Usually you do not need to use this \fB\-Wa\fR mechanism, since many compiler +command-line options are automatically passed to the assembler by the compiler. +(You can call the \s-1GNU\s0 compiler driver with the \fB\-v\fR option to see +precisely what options it passes to each compilation pass, including the +assembler.) +.SH "OPTIONS" +.IX Header "OPTIONS" +.IP "\fB@\fR\fIfile\fR" 4 +.IX Item "@file" +Read command-line options from \fIfile\fR. The options read are +inserted in place of the original @\fIfile\fR option. If \fIfile\fR +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +.Sp +Options in \fIfile\fR are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The \fIfile\fR may itself contain additional +@\fIfile\fR options; any such options will be processed recursively. +.IP "\fB\-a[cdghlmns]\fR" 4 +.IX Item "-a[cdghlmns]" +Turn on listings, in any of a variety of ways: +.RS 4 +.IP "\fB\-ac\fR" 4 +.IX Item "-ac" +omit false conditionals +.IP "\fB\-ad\fR" 4 +.IX Item "-ad" +omit debugging directives +.IP "\fB\-ag\fR" 4 +.IX Item "-ag" +include general information, like as version and options passed +.IP "\fB\-ah\fR" 4 +.IX Item "-ah" +include high-level source +.IP "\fB\-al\fR" 4 +.IX Item "-al" +include assembly +.IP "\fB\-am\fR" 4 +.IX Item "-am" +include macro expansions +.IP "\fB\-an\fR" 4 +.IX Item "-an" +omit forms processing +.IP "\fB\-as\fR" 4 +.IX Item "-as" +include symbols +.IP "\fB=file\fR" 4 +.IX Item "=file" +set the name of the listing file +.RE +.RS 4 +.Sp +You may combine these options; for example, use \fB\-aln\fR for assembly +listing without forms processing. The \fB=file\fR option, if used, must be +the last one. By itself, \fB\-a\fR defaults to \fB\-ahls\fR. +.RE +.IP "\fB\-\-alternate\fR" 4 +.IX Item "--alternate" +Begin in alternate macro mode. +.IP "\fB\-\-compress\-debug\-sections\fR" 4 +.IX Item "--compress-debug-sections" +Compress \s-1DWARF\s0 debug sections using zlib. The debug sections are renamed +to begin with \fB.zdebug\fR, and the resulting object file may not be +compatible with older linkers and object file utilities. +.IP "\fB\-\-nocompress\-debug\-sections\fR" 4 +.IX Item "--nocompress-debug-sections" +Do not compress \s-1DWARF\s0 debug sections. This is the default. +.IP "\fB\-D\fR" 4 +.IX Item "-D" +Ignored. This option is accepted for script compatibility with calls to +other assemblers. +.IP "\fB\-\-debug\-prefix\-map\fR \fIold\fR\fB=\fR\fInew\fR" 4 +.IX Item "--debug-prefix-map old=new" +When assembling files in directory \fI\fIold\fI\fR, record debugging +information describing them as in \fI\fInew\fI\fR instead. +.IP "\fB\-\-defsym\fR \fIsym\fR\fB=\fR\fIvalue\fR" 4 +.IX Item "--defsym sym=value" +Define the symbol \fIsym\fR to be \fIvalue\fR before assembling the input file. +\&\fIvalue\fR must be an integer constant. As in C, a leading \fB0x\fR +indicates a hexadecimal value, and a leading \fB0\fR indicates an octal +value. The value of the symbol can be overridden inside a source file via the +use of a \f(CW\*(C`.set\*(C'\fR pseudo-op. +.IP "\fB\-f\fR" 4 +.IX Item "-f" +\&\*(L"fast\*(R"\-\-\-skip whitespace and comment preprocessing (assume source is +compiler output). +.IP "\fB\-g\fR" 4 +.IX Item "-g" +.PD 0 +.IP "\fB\-\-gen\-debug\fR" 4 +.IX Item "--gen-debug" +.PD +Generate debugging information for each assembler source line using whichever +debug format is preferred by the target. This currently means either \s-1STABS\s0, +\&\s-1ECOFF\s0 or \s-1DWARF2\s0. +.IP "\fB\-\-gstabs\fR" 4 +.IX Item "--gstabs" +Generate stabs debugging information for each assembler line. This +may help debugging assembler code, if the debugger can handle it. +.IP "\fB\-\-gstabs+\fR" 4 +.IX Item "--gstabs+" +Generate stabs debugging information for each assembler line, with \s-1GNU\s0 +extensions that probably only gdb can handle, and that could make other +debuggers crash or refuse to read your program. This +may help debugging assembler code. Currently the only \s-1GNU\s0 extension is +the location of the current working directory at assembling time. +.IP "\fB\-\-gdwarf\-2\fR" 4 +.IX Item "--gdwarf-2" +Generate \s-1DWARF2\s0 debugging information for each assembler line. This +may help debugging assembler code, if the debugger can handle it. Note\-\-\-this +option is only supported by some targets, not all of them. +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +Print a summary of the command line options and exit. +.IP "\fB\-\-target\-help\fR" 4 +.IX Item "--target-help" +Print a summary of all target specific options and exit. +.IP "\fB\-I\fR \fIdir\fR" 4 +.IX Item "-I dir" +Add directory \fIdir\fR to the search list for \f(CW\*(C`.include\*(C'\fR directives. +.IP "\fB\-J\fR" 4 +.IX Item "-J" +Don't warn about signed overflow. +.IP "\fB\-K\fR" 4 +.IX Item "-K" +Issue warnings when difference tables altered for long displacements. +.IP "\fB\-L\fR" 4 +.IX Item "-L" +.PD 0 +.IP "\fB\-\-keep\-locals\fR" 4 +.IX Item "--keep-locals" +.PD +Keep (in the symbol table) local symbols. These symbols start with +system-specific local label prefixes, typically \fB.L\fR for \s-1ELF\s0 systems +or \fBL\fR for traditional a.out systems. +.IP "\fB\-\-listing\-lhs\-width=\fR\fInumber\fR" 4 +.IX Item "--listing-lhs-width=number" +Set the maximum width, in words, of the output data column for an assembler +listing to \fInumber\fR. +.IP "\fB\-\-listing\-lhs\-width2=\fR\fInumber\fR" 4 +.IX Item "--listing-lhs-width2=number" +Set the maximum width, in words, of the output data column for continuation +lines in an assembler listing to \fInumber\fR. +.IP "\fB\-\-listing\-rhs\-width=\fR\fInumber\fR" 4 +.IX Item "--listing-rhs-width=number" +Set the maximum width of an input source line, as displayed in a listing, to +\&\fInumber\fR bytes. +.IP "\fB\-\-listing\-cont\-lines=\fR\fInumber\fR" 4 +.IX Item "--listing-cont-lines=number" +Set the maximum number of lines printed in a listing for a single line of input +to \fInumber\fR + 1. +.IP "\fB\-o\fR \fIobjfile\fR" 4 +.IX Item "-o objfile" +Name the object-file output from \fBas\fR \fIobjfile\fR. +.IP "\fB\-R\fR" 4 +.IX Item "-R" +Fold the data section into the text section. +.Sp +Set the default size of \s-1GAS\s0's hash tables to a prime number close to +\&\fInumber\fR. Increasing this value can reduce the length of time it takes the +assembler to perform its tasks, at the expense of increasing the assembler's +memory requirements. Similarly reducing this value can reduce the memory +requirements at the expense of speed. +.IP "\fB\-\-reduce\-memory\-overheads\fR" 4 +.IX Item "--reduce-memory-overheads" +This option reduces \s-1GAS\s0's memory requirements, at the expense of making the +assembly processes slower. Currently this switch is a synonym for +\&\fB\-\-hash\-size=4051\fR, but in the future it may have other effects as well. +.IP "\fB\-\-statistics\fR" 4 +.IX Item "--statistics" +Print the maximum space (in bytes) and total time (in seconds) used by +assembly. +.IP "\fB\-\-strip\-local\-absolute\fR" 4 +.IX Item "--strip-local-absolute" +Remove local absolute symbols from the outgoing symbol table. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +.PD 0 +.IP "\fB\-version\fR" 4 +.IX Item "-version" +.PD +Print the \fBas\fR version. +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +Print the \fBas\fR version and exit. +.IP "\fB\-W\fR" 4 +.IX Item "-W" +.PD 0 +.IP "\fB\-\-no\-warn\fR" 4 +.IX Item "--no-warn" +.PD +Suppress warning messages. +.IP "\fB\-\-fatal\-warnings\fR" 4 +.IX Item "--fatal-warnings" +Treat warnings as errors. +.IP "\fB\-\-warn\fR" 4 +.IX Item "--warn" +Don't suppress warning messages or treat them as errors. +.IP "\fB\-w\fR" 4 +.IX Item "-w" +Ignored. +.IP "\fB\-x\fR" 4 +.IX Item "-x" +Ignored. +.IP "\fB\-Z\fR" 4 +.IX Item "-Z" +Generate an object file even after errors. +.IP "\fB\-\- |\fR \fIfiles\fR \fB...\fR" 4 +.IX Item "-- | files ..." +Standard input, or source files to assemble. +.PP +The following options are available when as is configured for +an \s-1ARC\s0 processor. +.IP "\fB\-marc[5|6|7|8]\fR" 4 +.IX Item "-marc[5|6|7|8]" +This option selects the core processor variant. +.IP "\fB\-EB | \-EL\fR" 4 +.IX Item "-EB | -EL" +Select either big-endian (\-EB) or little-endian (\-EL) output. +.PP +The following options are available when as is configured for the \s-1ARM\s0 +processor family. +.IP "\fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4 +.IX Item "-mcpu=processor[+extension...]" +Specify which \s-1ARM\s0 processor variant is the target. +.IP "\fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4 +.IX Item "-march=architecture[+extension...]" +Specify which \s-1ARM\s0 architecture variant is used by the target. +.IP "\fB\-mfpu=\fR\fIfloating-point-format\fR" 4 +.IX Item "-mfpu=floating-point-format" +Select which Floating Point architecture is the target. +.IP "\fB\-mfloat\-abi=\fR\fIabi\fR" 4 +.IX Item "-mfloat-abi=abi" +Select which floating point \s-1ABI\s0 is in use. +.IP "\fB\-mthumb\fR" 4 +.IX Item "-mthumb" +Enable Thumb only instruction decoding. +.IP "\fB\-mapcs\-32 | \-mapcs\-26 | \-mapcs\-float | \-mapcs\-reentrant\fR" 4 +.IX Item "-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant" +Select which procedure calling convention is in use. +.IP "\fB\-EB | \-EL\fR" 4 +.IX Item "-EB | -EL" +Select either big-endian (\-EB) or little-endian (\-EL) output. +.IP "\fB\-mthumb\-interwork\fR" 4 +.IX Item "-mthumb-interwork" +Specify that the code has been generated with interworking between Thumb and +\&\s-1ARM\s0 code in mind. +.IP "\fB\-k\fR" 4 +.IX Item "-k" +Specify that \s-1PIC\s0 code has been generated. +.PP +The following options are available when as is configured for +the Blackfin processor family. +.IP "\fB\-mcpu=\fR\fIprocessor\fR[\fB\-\fR\fIsirevision\fR]" 4 +.IX Item "-mcpu=processor[-sirevision]" +This option specifies the target processor. The optional \fIsirevision\fR +is not used in assembler. +.IP "\fB\-mfdpic\fR" 4 +.IX Item "-mfdpic" +Assemble for the \s-1FDPIC\s0 \s-1ABI\s0. +.IP "\fB\-mno\-fdpic\fR" 4 +.IX Item "-mno-fdpic" +.PD 0 +.IP "\fB\-mnopic\fR" 4 +.IX Item "-mnopic" +.PD +Disable \-mfdpic. +.PP +See the info pages for documentation of the CRIS-specific options. +.PP +The following options are available when as is configured for +a D10V processor. +.IP "\fB\-O\fR" 4 +.IX Item "-O" +Optimize output by parallelizing instructions. +.PP +The following options are available when as is configured for a D30V +processor. +.IP "\fB\-O\fR" 4 +.IX Item "-O" +Optimize output by parallelizing instructions. +.IP "\fB\-n\fR" 4 +.IX Item "-n" +Warn when nops are generated. +.IP "\fB\-N\fR" 4 +.IX Item "-N" +Warn when a nop after a 32\-bit multiply instruction is generated. +.PP +The following options are available when as is configured for the +Intel 80960 processor. +.IP "\fB\-ACA | \-ACA_A | \-ACB | \-ACC | \-AKA | \-AKB | \-AKC | \-AMC\fR" 4 +.IX Item "-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC" +Specify which variant of the 960 architecture is the target. +.IP "\fB\-b\fR" 4 +.IX Item "-b" +Add code to collect statistics about branches taken. +.IP "\fB\-no\-relax\fR" 4 +.IX Item "-no-relax" +Do not alter compare-and-branch instructions for long displacements; +error if necessary. +.PP +The following options are available when as is configured for the +Ubicom \s-1IP2K\s0 series. +.IP "\fB\-mip2022ext\fR" 4 +.IX Item "-mip2022ext" +Specifies that the extended \s-1IP2022\s0 instructions are allowed. +.IP "\fB\-mip2022\fR" 4 +.IX Item "-mip2022" +Restores the default behaviour, which restricts the permitted instructions to +just the basic \s-1IP2022\s0 ones. +.PP +The following options are available when as is configured for the +Renesas M32C and M16C processors. +.IP "\fB\-m32c\fR" 4 +.IX Item "-m32c" +Assemble M32C instructions. +.IP "\fB\-m16c\fR" 4 +.IX Item "-m16c" +Assemble M16C instructions (the default). +.IP "\fB\-relax\fR" 4 +.IX Item "-relax" +Enable support for link-time relaxations. +.IP "\fB\-h\-tick\-hex\fR" 4 +.IX Item "-h-tick-hex" +Support H'00 style hex constants in addition to 0x00 style. +.PP +The following options are available when as is configured for the +Renesas M32R (formerly Mitsubishi M32R) series. +.IP "\fB\-\-m32rx\fR" 4 +.IX Item "--m32rx" +Specify which processor in the M32R family is the target. The default +is normally the M32R, but this option changes it to the M32RX. +.IP "\fB\-\-warn\-explicit\-parallel\-conflicts or \-\-Wp\fR" 4 +.IX Item "--warn-explicit-parallel-conflicts or --Wp" +Produce warning messages when questionable parallel constructs are +encountered. +.IP "\fB\-\-no\-warn\-explicit\-parallel\-conflicts or \-\-Wnp\fR" 4 +.IX Item "--no-warn-explicit-parallel-conflicts or --Wnp" +Do not produce warning messages when questionable parallel constructs are +encountered. +.PP +The following options are available when as is configured for the +Motorola 68000 series. +.IP "\fB\-l\fR" 4 +.IX Item "-l" +Shorten references to undefined symbols, to one word instead of two. +.IP "\fB\-m68000 | \-m68008 | \-m68010 | \-m68020 | \-m68030\fR" 4 +.IX Item "-m68000 | -m68008 | -m68010 | -m68020 | -m68030" +.PD 0 +.IP "\fB| \-m68040 | \-m68060 | \-m68302 | \-m68331 | \-m68332\fR" 4 +.IX Item "| -m68040 | -m68060 | -m68302 | -m68331 | -m68332" +.IP "\fB| \-m68333 | \-m68340 | \-mcpu32 | \-m5200\fR" 4 +.IX Item "| -m68333 | -m68340 | -mcpu32 | -m5200" +.PD +Specify what processor in the 68000 family is the target. The default +is normally the 68020, but this can be changed at configuration time. +.IP "\fB\-m68881 | \-m68882 | \-mno\-68881 | \-mno\-68882\fR" 4 +.IX Item "-m68881 | -m68882 | -mno-68881 | -mno-68882" +The target machine does (or does not) have a floating-point coprocessor. +The default is to assume a coprocessor for 68020, 68030, and cpu32. Although +the basic 68000 is not compatible with the 68881, a combination of the +two can be specified, since it's possible to do emulation of the +coprocessor instructions with the main processor. +.IP "\fB\-m68851 | \-mno\-68851\fR" 4 +.IX Item "-m68851 | -mno-68851" +The target machine does (or does not) have a memory-management +unit coprocessor. The default is to assume an \s-1MMU\s0 for 68020 and up. +.PP +For details about the \s-1PDP\-11\s0 machine dependent features options, +see \fBPDP\-11\-Options\fR. +.IP "\fB\-mpic | \-mno\-pic\fR" 4 +.IX Item "-mpic | -mno-pic" +Generate position-independent (or position-dependent) code. The +default is \fB\-mpic\fR. +.IP "\fB\-mall\fR" 4 +.IX Item "-mall" +.PD 0 +.IP "\fB\-mall\-extensions\fR" 4 +.IX Item "-mall-extensions" +.PD +Enable all instruction set extensions. This is the default. +.IP "\fB\-mno\-extensions\fR" 4 +.IX Item "-mno-extensions" +Disable all instruction set extensions. +.IP "\fB\-m\fR\fIextension\fR \fB| \-mno\-\fR\fIextension\fR" 4 +.IX Item "-mextension | -mno-extension" +Enable (or disable) a particular instruction set extension. +.IP "\fB\-m\fR\fIcpu\fR" 4 +.IX Item "-mcpu" +Enable the instruction set extensions supported by a particular \s-1CPU\s0, and +disable all other extensions. +.IP "\fB\-m\fR\fImachine\fR" 4 +.IX Item "-mmachine" +Enable the instruction set extensions supported by a particular machine +model, and disable all other extensions. +.PP +The following options are available when as is configured for +a picoJava processor. +.IP "\fB\-mb\fR" 4 +.IX Item "-mb" +Generate \*(L"big endian\*(R" format output. +.IP "\fB\-ml\fR" 4 +.IX Item "-ml" +Generate \*(L"little endian\*(R" format output. +.PP +The following options are available when as is configured for the +Motorola 68HC11 or 68HC12 series. +.IP "\fB\-m68hc11 | \-m68hc12 | \-m68hcs12\fR" 4 +.IX Item "-m68hc11 | -m68hc12 | -m68hcs12" +Specify what processor is the target. The default is +defined by the configuration option when building the assembler. +.IP "\fB\-mshort\fR" 4 +.IX Item "-mshort" +Specify to use the 16\-bit integer \s-1ABI\s0. +.IP "\fB\-mlong\fR" 4 +.IX Item "-mlong" +Specify to use the 32\-bit integer \s-1ABI\s0. +.IP "\fB\-mshort\-double\fR" 4 +.IX Item "-mshort-double" +Specify to use the 32\-bit double \s-1ABI\s0. +.IP "\fB\-mlong\-double\fR" 4 +.IX Item "-mlong-double" +Specify to use the 64\-bit double \s-1ABI\s0. +.IP "\fB\-\-force\-long\-branches\fR" 4 +.IX Item "--force-long-branches" +Relative branches are turned into absolute ones. This concerns +conditional branches, unconditional branches and branches to a +sub routine. +.IP "\fB\-S | \-\-short\-branches\fR" 4 +.IX Item "-S | --short-branches" +Do not turn relative branches into absolute ones +when the offset is out of range. +.IP "\fB\-\-strict\-direct\-mode\fR" 4 +.IX Item "--strict-direct-mode" +Do not turn the direct addressing mode into extended addressing mode +when the instruction does not support direct addressing mode. +.IP "\fB\-\-print\-insn\-syntax\fR" 4 +.IX Item "--print-insn-syntax" +Print the syntax of instruction in case of error. +.IP "\fB\-\-print\-opcodes\fR" 4 +.IX Item "--print-opcodes" +print the list of instructions with syntax and then exit. +.IP "\fB\-\-generate\-example\fR" 4 +.IX Item "--generate-example" +print an example of instruction for each possible instruction and then exit. +This option is only useful for testing \fBas\fR. +.PP +The following options are available when \fBas\fR is configured +for the \s-1SPARC\s0 architecture: +.IP "\fB\-Av6 | \-Av7 | \-Av8 | \-Asparclet | \-Asparclite\fR" 4 +.IX Item "-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite" +.PD 0 +.IP "\fB\-Av8plus | \-Av8plusa | \-Av9 | \-Av9a\fR" 4 +.IX Item "-Av8plus | -Av8plusa | -Av9 | -Av9a" +.PD +Explicitly select a variant of the \s-1SPARC\s0 architecture. +.Sp +\&\fB\-Av8plus\fR and \fB\-Av8plusa\fR select a 32 bit environment. +\&\fB\-Av9\fR and \fB\-Av9a\fR select a 64 bit environment. +.Sp +\&\fB\-Av8plusa\fR and \fB\-Av9a\fR enable the \s-1SPARC\s0 V9 instruction set with +UltraSPARC extensions. +.IP "\fB\-xarch=v8plus | \-xarch=v8plusa\fR" 4 +.IX Item "-xarch=v8plus | -xarch=v8plusa" +For compatibility with the Solaris v9 assembler. These options are +equivalent to \-Av8plus and \-Av8plusa, respectively. +.IP "\fB\-bump\fR" 4 +.IX Item "-bump" +Warn when the assembler switches to another architecture. +.PP +The following options are available when as is configured for the 'c54x +architecture. +.IP "\fB\-mfar\-mode\fR" 4 +.IX Item "-mfar-mode" +Enable extended addressing mode. All addresses and relocations will assume +extended addressing (usually 23 bits). +.IP "\fB\-mcpu=\fR\fI\s-1CPU_VERSION\s0\fR" 4 +.IX Item "-mcpu=CPU_VERSION" +Sets the \s-1CPU\s0 version being compiled for. +.IP "\fB\-merrors\-to\-file\fR \fI\s-1FILENAME\s0\fR" 4 +.IX Item "-merrors-to-file FILENAME" +Redirect error output to a file, for broken systems which don't support such +behaviour in the shell. +.PP +The following options are available when as is configured for +a \s-1MIPS\s0 processor. +.IP "\fB\-G\fR \fInum\fR" 4 +.IX Item "-G num" +This option sets the largest size of an object that can be referenced +implicitly with the \f(CW\*(C`gp\*(C'\fR register. It is only accepted for targets that +use \s-1ECOFF\s0 format, such as a DECstation running Ultrix. The default value is 8. +.IP "\fB\-EB\fR" 4 +.IX Item "-EB" +Generate \*(L"big endian\*(R" format output. +.IP "\fB\-EL\fR" 4 +.IX Item "-EL" +Generate \*(L"little endian\*(R" format output. +.IP "\fB\-mips1\fR" 4 +.IX Item "-mips1" +.PD 0 +.IP "\fB\-mips2\fR" 4 +.IX Item "-mips2" +.IP "\fB\-mips3\fR" 4 +.IX Item "-mips3" +.IP "\fB\-mips4\fR" 4 +.IX Item "-mips4" +.IP "\fB\-mips5\fR" 4 +.IX Item "-mips5" +.IP "\fB\-mips32\fR" 4 +.IX Item "-mips32" +.IP "\fB\-mips32r2\fR" 4 +.IX Item "-mips32r2" +.IP "\fB\-mips64\fR" 4 +.IX Item "-mips64" +.IP "\fB\-mips64r2\fR" 4 +.IX Item "-mips64r2" +.PD +Generate code for a particular \s-1MIPS\s0 Instruction Set Architecture level. +\&\fB\-mips1\fR is an alias for \fB\-march=r3000\fR, \fB\-mips2\fR is an +alias for \fB\-march=r6000\fR, \fB\-mips3\fR is an alias for +\&\fB\-march=r4000\fR and \fB\-mips4\fR is an alias for \fB\-march=r8000\fR. +\&\fB\-mips5\fR, \fB\-mips32\fR, \fB\-mips32r2\fR, \fB\-mips64\fR, and +\&\fB\-mips64r2\fR +correspond to generic +\&\fB\s-1MIPS\s0 V\fR, \fB\s-1MIPS32\s0\fR, \fB\s-1MIPS32\s0 Release 2\fR, \fB\s-1MIPS64\s0\fR, +and \fB\s-1MIPS64\s0 Release 2\fR +\&\s-1ISA\s0 processors, respectively. +.IP "\fB\-march=\fR\fI\s-1CPU\s0\fR" 4 +.IX Item "-march=CPU" +Generate code for a particular \s-1MIPS\s0 cpu. +.IP "\fB\-mtune=\fR\fIcpu\fR" 4 +.IX Item "-mtune=cpu" +Schedule and tune for a particular \s-1MIPS\s0 cpu. +.IP "\fB\-mfix7000\fR" 4 +.IX Item "-mfix7000" +.PD 0 +.IP "\fB\-mno\-fix7000\fR" 4 +.IX Item "-mno-fix7000" +.PD +Cause nops to be inserted if the read of the destination register +of an mfhi or mflo instruction occurs in the following two instructions. +.IP "\fB\-mdebug\fR" 4 +.IX Item "-mdebug" +.PD 0 +.IP "\fB\-no\-mdebug\fR" 4 +.IX Item "-no-mdebug" +.PD +Cause stabs-style debugging output to go into an ECOFF-style .mdebug +section instead of the standard \s-1ELF\s0 .stabs sections. +.IP "\fB\-mpdr\fR" 4 +.IX Item "-mpdr" +.PD 0 +.IP "\fB\-mno\-pdr\fR" 4 +.IX Item "-mno-pdr" +.PD +Control generation of \f(CW\*(C`.pdr\*(C'\fR sections. +.IP "\fB\-mgp32\fR" 4 +.IX Item "-mgp32" +.PD 0 +.IP "\fB\-mfp32\fR" 4 +.IX Item "-mfp32" +.PD +The register sizes are normally inferred from the \s-1ISA\s0 and \s-1ABI\s0, but these +flags force a certain group of registers to be treated as 32 bits wide at +all times. \fB\-mgp32\fR controls the size of general-purpose registers +and \fB\-mfp32\fR controls the size of floating-point registers. +.IP "\fB\-mips16\fR" 4 +.IX Item "-mips16" +.PD 0 +.IP "\fB\-no\-mips16\fR" 4 +.IX Item "-no-mips16" +.PD +Generate code for the \s-1MIPS\s0 16 processor. This is equivalent to putting +\&\f(CW\*(C`.set mips16\*(C'\fR at the start of the assembly file. \fB\-no\-mips16\fR +turns off this option. +.IP "\fB\-msmartmips\fR" 4 +.IX Item "-msmartmips" +.PD 0 +.IP "\fB\-mno\-smartmips\fR" 4 +.IX Item "-mno-smartmips" +.PD +Enables the SmartMIPS extension to the \s-1MIPS32\s0 instruction set. This is +equivalent to putting \f(CW\*(C`.set smartmips\*(C'\fR at the start of the assembly file. +\&\fB\-mno\-smartmips\fR turns off this option. +.IP "\fB\-mips3d\fR" 4 +.IX Item "-mips3d" +.PD 0 +.IP "\fB\-no\-mips3d\fR" 4 +.IX Item "-no-mips3d" +.PD +Generate code for the \s-1MIPS\-3D\s0 Application Specific Extension. +This tells the assembler to accept \s-1MIPS\-3D\s0 instructions. +\&\fB\-no\-mips3d\fR turns off this option. +.IP "\fB\-mdmx\fR" 4 +.IX Item "-mdmx" +.PD 0 +.IP "\fB\-no\-mdmx\fR" 4 +.IX Item "-no-mdmx" +.PD +Generate code for the \s-1MDMX\s0 Application Specific Extension. +This tells the assembler to accept \s-1MDMX\s0 instructions. +\&\fB\-no\-mdmx\fR turns off this option. +.IP "\fB\-mdsp\fR" 4 +.IX Item "-mdsp" +.PD 0 +.IP "\fB\-mno\-dsp\fR" 4 +.IX Item "-mno-dsp" +.PD +Generate code for the \s-1DSP\s0 Release 1 Application Specific Extension. +This tells the assembler to accept \s-1DSP\s0 Release 1 instructions. +\&\fB\-mno\-dsp\fR turns off this option. +.IP "\fB\-mdspr2\fR" 4 +.IX Item "-mdspr2" +.PD 0 +.IP "\fB\-mno\-dspr2\fR" 4 +.IX Item "-mno-dspr2" +.PD +Generate code for the \s-1DSP\s0 Release 2 Application Specific Extension. +This option implies \-mdsp. +This tells the assembler to accept \s-1DSP\s0 Release 2 instructions. +\&\fB\-mno\-dspr2\fR turns off this option. +.IP "\fB\-mmt\fR" 4 +.IX Item "-mmt" +.PD 0 +.IP "\fB\-mno\-mt\fR" 4 +.IX Item "-mno-mt" +.PD +Generate code for the \s-1MT\s0 Application Specific Extension. +This tells the assembler to accept \s-1MT\s0 instructions. +\&\fB\-mno\-mt\fR turns off this option. +.IP "\fB\-\-construct\-floats\fR" 4 +.IX Item "--construct-floats" +.PD 0 +.IP "\fB\-\-no\-construct\-floats\fR" 4 +.IX Item "--no-construct-floats" +.PD +The \fB\-\-no\-construct\-floats\fR option disables the construction of +double width floating point constants by loading the two halves of the +value into the two single width floating point registers that make up +the double width register. By default \fB\-\-construct\-floats\fR is +selected, allowing construction of these floating point constants. +.IP "\fB\-\-emulation=\fR\fIname\fR" 4 +.IX Item "--emulation=name" +This option causes \fBas\fR to emulate \fBas\fR configured +for some other target, in all respects, including output format (choosing +between \s-1ELF\s0 and \s-1ECOFF\s0 only), handling of pseudo-opcodes which may generate +debugging information or store symbol table information, and default +endianness. The available configuration names are: \fBmipsecoff\fR, +\&\fBmipself\fR, \fBmipslecoff\fR, \fBmipsbecoff\fR, \fBmipslelf\fR, +\&\fBmipsbelf\fR. The first two do not alter the default endianness from that +of the primary target for which the assembler was configured; the others change +the default to little\- or big-endian as indicated by the \fBb\fR or \fBl\fR +in the name. Using \fB\-EB\fR or \fB\-EL\fR will override the endianness +selection in any case. +.Sp +This option is currently supported only when the primary target +\&\fBas\fR is configured for is a \s-1MIPS\s0 \s-1ELF\s0 or \s-1ECOFF\s0 target. +Furthermore, the primary target or others specified with +\&\fB\-\-enable\-targets=...\fR at configuration time must include support for +the other format, if both are to be available. For example, the Irix 5 +configuration includes support for both. +.Sp +Eventually, this option will support more configurations, with more +fine-grained control over the assembler's behavior, and will be supported for +more processors. +.IP "\fB\-nocpp\fR" 4 +.IX Item "-nocpp" +\&\fBas\fR ignores this option. It is accepted for compatibility with +the native tools. +.IP "\fB\-\-trap\fR" 4 +.IX Item "--trap" +.PD 0 +.IP "\fB\-\-no\-trap\fR" 4 +.IX Item "--no-trap" +.IP "\fB\-\-break\fR" 4 +.IX Item "--break" +.IP "\fB\-\-no\-break\fR" 4 +.IX Item "--no-break" +.PD +Control how to deal with multiplication overflow and division by zero. +\&\fB\-\-trap\fR or \fB\-\-no\-break\fR (which are synonyms) take a trap exception +(and only work for Instruction Set Architecture level 2 and higher); +\&\fB\-\-break\fR or \fB\-\-no\-trap\fR (also synonyms, and the default) take a +break exception. +.IP "\fB\-n\fR" 4 +.IX Item "-n" +When this option is used, \fBas\fR will issue a warning every +time it generates a nop instruction from a macro. +.PP +The following options are available when as is configured for +an MCore processor. +.IP "\fB\-jsri2bsr\fR" 4 +.IX Item "-jsri2bsr" +.PD 0 +.IP "\fB\-nojsri2bsr\fR" 4 +.IX Item "-nojsri2bsr" +.PD +Enable or disable the \s-1JSRI\s0 to \s-1BSR\s0 transformation. By default this is enabled. +The command line option \fB\-nojsri2bsr\fR can be used to disable it. +.IP "\fB\-sifilter\fR" 4 +.IX Item "-sifilter" +.PD 0 +.IP "\fB\-nosifilter\fR" 4 +.IX Item "-nosifilter" +.PD +Enable or disable the silicon filter behaviour. By default this is disabled. +The default can be overridden by the \fB\-sifilter\fR command line option. +.IP "\fB\-relax\fR" 4 +.IX Item "-relax" +Alter jump instructions for long displacements. +.IP "\fB\-mcpu=[210|340]\fR" 4 +.IX Item "-mcpu=[210|340]" +Select the cpu type on the target hardware. This controls which instructions +can be assembled. +.IP "\fB\-EB\fR" 4 +.IX Item "-EB" +Assemble for a big endian target. +.IP "\fB\-EL\fR" 4 +.IX Item "-EL" +Assemble for a little endian target. +.PP +See the info pages for documentation of the MMIX-specific options. +.PP +See the info pages for documentation of the RX-specific options. +.PP +The following options are available when as is configured for the s390 +processor family. +.IP "\fB\-m31\fR" 4 +.IX Item "-m31" +.PD 0 +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.PD +Select the word size, either 31/32 bits or 64 bits. +.IP "\fB\-mesa\fR" 4 +.IX Item "-mesa" +.PD 0 +.IP "\fB\-mzarch\fR" 4 +.IX Item "-mzarch" +.PD +Select the architecture mode, either the Enterprise System +Architecture (esa) or the z/Architecture mode (zarch). +.IP "\fB\-march=\fR\fIprocessor\fR" 4 +.IX Item "-march=processor" +Specify which s390 processor variant is the target, \fBg6\fR, \fBg6\fR, +\&\fBz900\fR, \fBz990\fR, \fBz9\-109\fR, \fBz9\-ec\fR, or \fBz10\fR. +.IP "\fB\-mregnames\fR" 4 +.IX Item "-mregnames" +.PD 0 +.IP "\fB\-mno\-regnames\fR" 4 +.IX Item "-mno-regnames" +.PD +Allow or disallow symbolic names for registers. +.IP "\fB\-mwarn\-areg\-zero\fR" 4 +.IX Item "-mwarn-areg-zero" +Warn whenever the operand for a base or index register has been specified +but evaluates to zero. +.PP +The following options are available when as is configured for a +\&\s-1TMS320C6000\s0 processor. +.IP "\fB\-march=\fR\fIarch\fR" 4 +.IX Item "-march=arch" +Enable (only) instructions from architecture \fIarch\fR. By default, +all instructions are permitted. +.Sp +The following values of \fIarch\fR are accepted: \f(CW\*(C`c62x\*(C'\fR, +\&\f(CW\*(C`c64x\*(C'\fR, \f(CW\*(C`c64x+\*(C'\fR, \f(CW\*(C`c67x\*(C'\fR, \f(CW\*(C`c67x+\*(C'\fR, \f(CW\*(C`c674x\*(C'\fR. +.IP "\fB\-matomic\fR" 4 +.IX Item "-matomic" +.PD 0 +.IP "\fB\-mno\-atomic\fR" 4 +.IX Item "-mno-atomic" +.PD +Enable or disable the optional C64x+ atomic operation instructions. +By default, they are enabled if no \fB\-march\fR option is given, or +if an architecture is specified with \fB\-march\fR that implies +these instructions are present (currently, there are no such +architectures); they are disabled if an architecture is specified with +\&\fB\-march\fR on which the instructions are optional or not +present. This option overrides such a default from the architecture, +independent of the order in which the \fB\-march\fR or +\&\fB\-matomic\fR or \fB\-mno\-atomic\fR options are passed. +.IP "\fB\-mdsbt\fR" 4 +.IX Item "-mdsbt" +.PD 0 +.IP "\fB\-mno\-dsbt\fR" 4 +.IX Item "-mno-dsbt" +.PD +The \fB\-mdsbt\fR option causes the assembler to generate the +\&\f(CW\*(C`Tag_ABI_DSBT\*(C'\fR attribute with a value of 1, indicating that the +code is using \s-1DSBT\s0 addressing. The \fB\-mno\-dsbt\fR option, the +default, causes the tag to have a value of 0, indicating that the code +does not use \s-1DSBT\s0 addressing. The linker will emit a warning if +objects of different type (\s-1DSBT\s0 and non-DSBT) are linked together. +.IP "\fB\-mpid=no\fR" 4 +.IX Item "-mpid=no" +.PD 0 +.IP "\fB\-mpid=near\fR" 4 +.IX Item "-mpid=near" +.IP "\fB\-mpid=far\fR" 4 +.IX Item "-mpid=far" +.PD +The \fB\-mpid=\fR option causes the assembler to generate the +\&\f(CW\*(C`Tag_ABI_PID\*(C'\fR attribute with a value indicating the form of data +addressing used by the code. \fB\-mpid=no\fR, the default, +indicates position-dependent data addressing, \fB\-mpid=near\fR +indicates position-independent addressing with \s-1GOT\s0 accesses using near +\&\s-1DP\s0 addressing, and \fB\-mpid=far\fR indicates position-independent +addressing with \s-1GOT\s0 accesses using far \s-1DP\s0 addressing. The linker will +emit a warning if objects built with different settings of this option +are linked together. +.IP "\fB\-mpic\fR" 4 +.IX Item "-mpic" +.PD 0 +.IP "\fB\-mno\-pic\fR" 4 +.IX Item "-mno-pic" +.PD +The \fB\-mpic\fR option causes the assembler to generate the +\&\f(CW\*(C`Tag_ABI_PIC\*(C'\fR attribute with a value of 1, indicating that the +code is using position-independent code addressing, The +\&\f(CW\*(C`\-mno\-pic\*(C'\fR option, the default, causes the tag to have a value of +0, indicating position-dependent code addressing. The linker will +emit a warning if objects of different type (position-dependent and +position-independent) are linked together. +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +.PD 0 +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +.PD +Generate code for the specified endianness. The default is +little-endian. +.PP +The following options are available when as is configured for +an Xtensa processor. +.IP "\fB\-\-text\-section\-literals | \-\-no\-text\-section\-literals\fR" 4 +.IX Item "--text-section-literals | --no-text-section-literals" +With \fB\-\-text\-section\-literals\fR, literal pools are interspersed +in the text section. The default is +\&\fB\-\-no\-text\-section\-literals\fR, which places literals in a +separate section in the output file. These options only affect literals +referenced via PC-relative \f(CW\*(C`L32R\*(C'\fR instructions; literals for +absolute mode \f(CW\*(C`L32R\*(C'\fR instructions are handled separately. +.IP "\fB\-\-absolute\-literals | \-\-no\-absolute\-literals\fR" 4 +.IX Item "--absolute-literals | --no-absolute-literals" +Indicate to the assembler whether \f(CW\*(C`L32R\*(C'\fR instructions use absolute +or PC-relative addressing. The default is to assume absolute addressing +if the Xtensa processor includes the absolute \f(CW\*(C`L32R\*(C'\fR addressing +option. Otherwise, only the PC-relative \f(CW\*(C`L32R\*(C'\fR mode can be used. +.IP "\fB\-\-target\-align | \-\-no\-target\-align\fR" 4 +.IX Item "--target-align | --no-target-align" +Enable or disable automatic alignment to reduce branch penalties at the +expense of some code density. The default is \fB\-\-target\-align\fR. +.IP "\fB\-\-longcalls | \-\-no\-longcalls\fR" 4 +.IX Item "--longcalls | --no-longcalls" +Enable or disable transformation of call instructions to allow calls +across a greater range of addresses. The default is +\&\fB\-\-no\-longcalls\fR. +.IP "\fB\-\-transform | \-\-no\-transform\fR" 4 +.IX Item "--transform | --no-transform" +Enable or disable all assembler transformations of Xtensa instructions. +The default is \fB\-\-transform\fR; +\&\fB\-\-no\-transform\fR should be used only in the rare cases when the +instructions must be exactly as specified in the assembly source. +.IP "\fB\-\-rename\-section\fR \fIoldname\fR\fB=\fR\fInewname\fR" 4 +.IX Item "--rename-section oldname=newname" +When generating output sections, rename the \fIoldname\fR section to +\&\fInewname\fR. +.PP +The following options are available when as is configured for +a Z80 family processor. +.IP "\fB\-z80\fR" 4 +.IX Item "-z80" +Assemble for Z80 processor. +.IP "\fB\-r800\fR" 4 +.IX Item "-r800" +Assemble for R800 processor. +.IP "\fB\-ignore\-undocumented\-instructions\fR" 4 +.IX Item "-ignore-undocumented-instructions" +.PD 0 +.IP "\fB\-Wnud\fR" 4 +.IX Item "-Wnud" +.PD +Assemble undocumented Z80 instructions that also work on R800 without warning. +.IP "\fB\-ignore\-unportable\-instructions\fR" 4 +.IX Item "-ignore-unportable-instructions" +.PD 0 +.IP "\fB\-Wnup\fR" 4 +.IX Item "-Wnup" +.PD +Assemble all undocumented Z80 instructions without warning. +.IP "\fB\-warn\-undocumented\-instructions\fR" 4 +.IX Item "-warn-undocumented-instructions" +.PD 0 +.IP "\fB\-Wud\fR" 4 +.IX Item "-Wud" +.PD +Issue a warning for undocumented Z80 instructions that also work on R800. +.IP "\fB\-warn\-unportable\-instructions\fR" 4 +.IX Item "-warn-unportable-instructions" +.PD 0 +.IP "\fB\-Wup\fR" 4 +.IX Item "-Wup" +.PD +Issue a warning for undocumented Z80 instructions that do not work on R800. +.IP "\fB\-forbid\-undocumented\-instructions\fR" 4 +.IX Item "-forbid-undocumented-instructions" +.PD 0 +.IP "\fB\-Fud\fR" 4 +.IX Item "-Fud" +.PD +Treat all undocumented instructions as errors. +.IP "\fB\-forbid\-unportable\-instructions\fR" 4 +.IX Item "-forbid-unportable-instructions" +.PD 0 +.IP "\fB\-Fup\fR" 4 +.IX Item "-Fup" +.PD +Treat undocumented Z80 instructions that do not work on R800 as errors. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fIgcc\fR\|(1), \fIld\fR\|(1), and the Info entries for \fIbinutils\fR and \fIld\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +2000, 2001, 2002, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 +or any later version published by the Free Software Foundation; +with no Invariant Sections, with no Front-Cover Texts, and with no +Back-Cover Texts. A copy of the license is included in the +section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". diff --git a/share/man/man1/arm-eabi-c++filt.1 b/share/man/man1/arm-eabi-c++filt.1 new file mode 100644 index 0000000..c228449 --- /dev/null +++ b/share/man/man1/arm-eabi-c++filt.1 @@ -0,0 +1,346 @@ +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "C++FILT 1" +.TH C++FILT 1 "2010-12-08" "binutils-2.21" "GNU Development Tools" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +c++filt \- Demangle C++ and Java symbols. +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +c++filt [\fB\-_\fR|\fB\-\-strip\-underscores\fR] + [\fB\-n\fR|\fB\-\-no\-strip\-underscores\fR] + [\fB\-p\fR|\fB\-\-no\-params\fR] + [\fB\-t\fR|\fB\-\-types\fR] + [\fB\-i\fR|\fB\-\-no\-verbose\fR] + [\fB\-s\fR \fIformat\fR|\fB\-\-format=\fR\fIformat\fR] + [\fB\-\-help\fR] [\fB\-\-version\fR] [\fIsymbol\fR...] +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +The \*(C+ and Java languages provide function overloading, which means +that you can write many functions with the same name, providing that +each function takes parameters of different types. In order to be +able to distinguish these similarly named functions \*(C+ and Java +encode them into a low-level assembler name which uniquely identifies +each different version. This process is known as \fImangling\fR. The +\&\fBc++filt\fR +[1] +program does the inverse mapping: it decodes (\fIdemangles\fR) low-level +names into user-level names so that they can be read. +.PP +Every alphanumeric word (consisting of letters, digits, underscores, +dollars, or periods) seen in the input is a potential mangled name. +If the name decodes into a \*(C+ name, the \*(C+ name replaces the +low-level name in the output, otherwise the original word is output. +In this way you can pass an entire assembler source file, containing +mangled names, through \fBc++filt\fR and see the same source file +containing demangled names. +.PP +You can also use \fBc++filt\fR to decipher individual symbols by +passing them on the command line: +.PP +.Vb 1 +\& c++filt <symbol> +.Ve +.PP +If no \fIsymbol\fR arguments are given, \fBc++filt\fR reads symbol +names from the standard input instead. All the results are printed on +the standard output. The difference between reading names from the +command line versus reading names from the standard input is that +command line arguments are expected to be just mangled names and no +checking is performed to separate them from surrounding text. Thus +for example: +.PP +.Vb 1 +\& c++filt \-n _Z1fv +.Ve +.PP +will work and demangle the name to \*(L"f()\*(R" whereas: +.PP +.Vb 1 +\& c++filt \-n _Z1fv, +.Ve +.PP +will not work. (Note the extra comma at the end of the mangled +name which makes it invalid). This command however will work: +.PP +.Vb 1 +\& echo _Z1fv, | c++filt \-n +.Ve +.PP +and will display \*(L"f(),\*(R", i.e., the demangled name followed by a +trailing comma. This behaviour is because when the names are read +from the standard input it is expected that they might be part of an +assembler source file where there might be extra, extraneous +characters trailing after a mangled name. For example: +.PP +.Vb 1 +\& .type _Z1fv, @function +.Ve +.SH "OPTIONS" +.IX Header "OPTIONS" +.IP "\fB\-_\fR" 4 +.IX Item "-_" +.PD 0 +.IP "\fB\-\-strip\-underscores\fR" 4 +.IX Item "--strip-underscores" +.PD +On some systems, both the C and \*(C+ compilers put an underscore in front +of every name. For example, the C name \f(CW\*(C`foo\*(C'\fR gets the low-level +name \f(CW\*(C`_foo\*(C'\fR. This option removes the initial underscore. Whether +\&\fBc++filt\fR removes the underscore by default is target dependent. +.IP "\fB\-n\fR" 4 +.IX Item "-n" +.PD 0 +.IP "\fB\-\-no\-strip\-underscores\fR" 4 +.IX Item "--no-strip-underscores" +.PD +Do not remove the initial underscore. +.IP "\fB\-p\fR" 4 +.IX Item "-p" +.PD 0 +.IP "\fB\-\-no\-params\fR" 4 +.IX Item "--no-params" +.PD +When demangling the name of a function, do not display the types of +the function's parameters. +.IP "\fB\-t\fR" 4 +.IX Item "-t" +.PD 0 +.IP "\fB\-\-types\fR" 4 +.IX Item "--types" +.PD +Attempt to demangle types as well as function names. This is disabled +by default since mangled types are normally only used internally in +the compiler, and they can be confused with non-mangled names. For example, +a function called \*(L"a\*(R" treated as a mangled type name would be +demangled to \*(L"signed char\*(R". +.IP "\fB\-i\fR" 4 +.IX Item "-i" +.PD 0 +.IP "\fB\-\-no\-verbose\fR" 4 +.IX Item "--no-verbose" +.PD +Do not include implementation details (if any) in the demangled +output. +.IP "\fB\-s\fR \fIformat\fR" 4 +.IX Item "-s format" +.PD 0 +.IP "\fB\-\-format=\fR\fIformat\fR" 4 +.IX Item "--format=format" +.PD +\&\fBc++filt\fR can decode various methods of mangling, used by +different compilers. The argument to this option selects which +method it uses: +.RS 4 +.ie n .IP """auto""" 4 +.el .IP "\f(CWauto\fR" 4 +.IX Item "auto" +Automatic selection based on executable (the default method) +.ie n .IP """gnu""" 4 +.el .IP "\f(CWgnu\fR" 4 +.IX Item "gnu" +the one used by the \s-1GNU\s0 \*(C+ compiler (g++) +.ie n .IP """lucid""" 4 +.el .IP "\f(CWlucid\fR" 4 +.IX Item "lucid" +the one used by the Lucid compiler (lcc) +.ie n .IP """arm""" 4 +.el .IP "\f(CWarm\fR" 4 +.IX Item "arm" +the one specified by the \*(C+ Annotated Reference Manual +.ie n .IP """hp""" 4 +.el .IP "\f(CWhp\fR" 4 +.IX Item "hp" +the one used by the \s-1HP\s0 compiler (aCC) +.ie n .IP """edg""" 4 +.el .IP "\f(CWedg\fR" 4 +.IX Item "edg" +the one used by the \s-1EDG\s0 compiler +.ie n .IP """gnu\-v3""" 4 +.el .IP "\f(CWgnu\-v3\fR" 4 +.IX Item "gnu-v3" +the one used by the \s-1GNU\s0 \*(C+ compiler (g++) with the V3 \s-1ABI\s0. +.ie n .IP """java""" 4 +.el .IP "\f(CWjava\fR" 4 +.IX Item "java" +the one used by the \s-1GNU\s0 Java compiler (gcj) +.ie n .IP """gnat""" 4 +.el .IP "\f(CWgnat\fR" 4 +.IX Item "gnat" +the one used by the \s-1GNU\s0 Ada compiler (\s-1GNAT\s0). +.RE +.RS 4 +.RE +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +Print a summary of the options to \fBc++filt\fR and exit. +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +Print the version number of \fBc++filt\fR and exit. +.IP "\fB@\fR\fIfile\fR" 4 +.IX Item "@file" +Read command-line options from \fIfile\fR. The options read are +inserted in place of the original @\fIfile\fR option. If \fIfile\fR +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +.Sp +Options in \fIfile\fR are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The \fIfile\fR may itself contain additional +@\fIfile\fR options; any such options will be processed recursively. +.SH "FOOTNOTES" +.IX Header "FOOTNOTES" +.IP "1." 4 +MS-DOS does not allow \f(CW\*(C`+\*(C'\fR characters in file names, so on +MS-DOS this program is named \fB\s-1CXXFILT\s0\fR. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +the Info entries for \fIbinutils\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 +or any later version published by the Free Software Foundation; +with no Invariant Sections, with no Front-Cover Texts, and with no +Back-Cover Texts. A copy of the license is included in the +section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". diff --git a/share/man/man1/arm-eabi-cpp.1 b/share/man/man1/arm-eabi-cpp.1 new file mode 100644 index 0000000..41af757 --- /dev/null +++ b/share/man/man1/arm-eabi-cpp.1 @@ -0,0 +1,992 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "CPP 1" +.TH CPP 1 "2012-01-06" "gcc-4.6.x-google" "GNU" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +cpp \- The C Preprocessor +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +cpp [\fB\-D\fR\fImacro\fR[=\fIdefn\fR]...] [\fB\-U\fR\fImacro\fR] + [\fB\-I\fR\fIdir\fR...] [\fB\-iquote\fR\fIdir\fR...] + [\fB\-W\fR\fIwarn\fR...] + [\fB\-M\fR|\fB\-MM\fR] [\fB\-MG\fR] [\fB\-MF\fR \fIfilename\fR] + [\fB\-MP\fR] [\fB\-MQ\fR \fItarget\fR...] + [\fB\-MT\fR \fItarget\fR...] + [\fB\-P\fR] [\fB\-fno\-working\-directory\fR] + [\fB\-x\fR \fIlanguage\fR] [\fB\-std=\fR\fIstandard\fR] + \fIinfile\fR \fIoutfile\fR +.PP +Only the most useful options are listed here; see below for the remainder. +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +The C preprocessor, often known as \fIcpp\fR, is a \fImacro processor\fR +that is used automatically by the C compiler to transform your program +before compilation. It is called a macro processor because it allows +you to define \fImacros\fR, which are brief abbreviations for longer +constructs. +.PP +The C preprocessor is intended to be used only with C, \*(C+, and +Objective-C source code. In the past, it has been abused as a general +text processor. It will choke on input which does not obey C's lexical +rules. For example, apostrophes will be interpreted as the beginning of +character constants, and cause errors. Also, you cannot rely on it +preserving characteristics of the input which are not significant to +C\-family languages. If a Makefile is preprocessed, all the hard tabs +will be removed, and the Makefile will not work. +.PP +Having said that, you can often get away with using cpp on things which +are not C. Other Algol-ish programming languages are often safe +(Pascal, Ada, etc.) So is assembly, with caution. \fB\-traditional\-cpp\fR +mode preserves more white space, and is otherwise more permissive. Many +of the problems can be avoided by writing C or \*(C+ style comments +instead of native language comments, and keeping macros simple. +.PP +Wherever possible, you should use a preprocessor geared to the language +you are writing in. Modern versions of the \s-1GNU\s0 assembler have macro +facilities. Most high level programming languages have their own +conditional compilation and inclusion mechanism. If all else fails, +try a true general text processor, such as \s-1GNU\s0 M4. +.PP +C preprocessors vary in some details. This manual discusses the \s-1GNU\s0 C +preprocessor, which provides a small superset of the features of \s-1ISO\s0 +Standard C. In its default mode, the \s-1GNU\s0 C preprocessor does not do a +few things required by the standard. These are features which are +rarely, if ever, used, and may cause surprising changes to the meaning +of a program which does not expect them. To get strict \s-1ISO\s0 Standard C, +you should use the \fB\-std=c90\fR, \fB\-std=c99\fR or +\&\fB\-std=c1x\fR options, depending +on which version of the standard you want. To get all the mandatory +diagnostics, you must also use \fB\-pedantic\fR. +.PP +This manual describes the behavior of the \s-1ISO\s0 preprocessor. To +minimize gratuitous differences, where the \s-1ISO\s0 preprocessor's +behavior does not conflict with traditional semantics, the +traditional preprocessor should behave the same way. The various +differences that do exist are detailed in the section \fBTraditional +Mode\fR. +.PP +For clarity, unless noted otherwise, references to \fB\s-1CPP\s0\fR in this +manual refer to \s-1GNU\s0 \s-1CPP\s0. +.SH "OPTIONS" +.IX Header "OPTIONS" +The C preprocessor expects two file names as arguments, \fIinfile\fR and +\&\fIoutfile\fR. The preprocessor reads \fIinfile\fR together with any +other files it specifies with \fB#include\fR. All the output generated +by the combined input files is written in \fIoutfile\fR. +.PP +Either \fIinfile\fR or \fIoutfile\fR may be \fB\-\fR, which as +\&\fIinfile\fR means to read from standard input and as \fIoutfile\fR +means to write to standard output. Also, if either file is omitted, it +means the same as if \fB\-\fR had been specified for that file. +.PP +Unless otherwise noted, or the option ends in \fB=\fR, all options +which take an argument may have that argument appear either immediately +after the option, or with a space between option and argument: +\&\fB\-Ifoo\fR and \fB\-I foo\fR have the same effect. +.PP +Many options have multi-letter names; therefore multiple single-letter +options may \fInot\fR be grouped: \fB\-dM\fR is very different from +\&\fB\-d\ \-M\fR. +.IP "\fB\-D\fR \fIname\fR" 4 +.IX Item "-D name" +Predefine \fIname\fR as a macro, with definition \f(CW1\fR. +.IP "\fB\-D\fR \fIname\fR\fB=\fR\fIdefinition\fR" 4 +.IX Item "-D name=definition" +The contents of \fIdefinition\fR are tokenized and processed as if +they appeared during translation phase three in a \fB#define\fR +directive. In particular, the definition will be truncated by +embedded newline characters. +.Sp +If you are invoking the preprocessor from a shell or shell-like +program you may need to use the shell's quoting syntax to protect +characters such as spaces that have a meaning in the shell syntax. +.Sp +If you wish to define a function-like macro on the command line, write +its argument list with surrounding parentheses before the equals sign +(if any). Parentheses are meaningful to most shells, so you will need +to quote the option. With \fBsh\fR and \fBcsh\fR, +\&\fB\-D'\fR\fIname\fR\fB(\fR\fIargs...\fR\fB)=\fR\fIdefinition\fR\fB'\fR works. +.Sp +\&\fB\-D\fR and \fB\-U\fR options are processed in the order they +are given on the command line. All \fB\-imacros\fR \fIfile\fR and +\&\fB\-include\fR \fIfile\fR options are processed after all +\&\fB\-D\fR and \fB\-U\fR options. +.IP "\fB\-U\fR \fIname\fR" 4 +.IX Item "-U name" +Cancel any previous definition of \fIname\fR, either built in or +provided with a \fB\-D\fR option. +.IP "\fB\-undef\fR" 4 +.IX Item "-undef" +Do not predefine any system-specific or GCC-specific macros. The +standard predefined macros remain defined. +.IP "\fB\-I\fR \fIdir\fR" 4 +.IX Item "-I dir" +Add the directory \fIdir\fR to the list of directories to be searched +for header files. +.Sp +Directories named by \fB\-I\fR are searched before the standard +system include directories. If the directory \fIdir\fR is a standard +system include directory, the option is ignored to ensure that the +default search order for system directories and the special treatment +of system headers are not defeated +\&. +If \fIdir\fR begins with \f(CW\*(C`=\*(C'\fR, then the \f(CW\*(C`=\*(C'\fR will be replaced +by the sysroot prefix; see \fB\-\-sysroot\fR and \fB\-isysroot\fR. +.IP "\fB\-o\fR \fIfile\fR" 4 +.IX Item "-o file" +Write output to \fIfile\fR. This is the same as specifying \fIfile\fR +as the second non-option argument to \fBcpp\fR. \fBgcc\fR has a +different interpretation of a second non-option argument, so you must +use \fB\-o\fR to specify the output file. +.IP "\fB\-Wall\fR" 4 +.IX Item "-Wall" +Turns on all optional warnings which are desirable for normal code. +At present this is \fB\-Wcomment\fR, \fB\-Wtrigraphs\fR, +\&\fB\-Wmultichar\fR and a warning about integer promotion causing a +change of sign in \f(CW\*(C`#if\*(C'\fR expressions. Note that many of the +preprocessor's warnings are on by default and have no options to +control them. +.IP "\fB\-Wcomment\fR" 4 +.IX Item "-Wcomment" +.PD 0 +.IP "\fB\-Wcomments\fR" 4 +.IX Item "-Wcomments" +.PD +Warn whenever a comment-start sequence \fB/*\fR appears in a \fB/*\fR +comment, or whenever a backslash-newline appears in a \fB//\fR comment. +(Both forms have the same effect.) +.IP "\fB\-Wtrigraphs\fR" 4 +.IX Item "-Wtrigraphs" +Most trigraphs in comments cannot affect the meaning of the program. +However, a trigraph that would form an escaped newline (\fB??/\fR at +the end of a line) can, by changing where the comment begins or ends. +Therefore, only trigraphs that would form escaped newlines produce +warnings inside a comment. +.Sp +This option is implied by \fB\-Wall\fR. If \fB\-Wall\fR is not +given, this option is still enabled unless trigraphs are enabled. To +get trigraph conversion without warnings, but get the other +\&\fB\-Wall\fR warnings, use \fB\-trigraphs \-Wall \-Wno\-trigraphs\fR. +.IP "\fB\-Wtraditional\fR" 4 +.IX Item "-Wtraditional" +Warn about certain constructs that behave differently in traditional and +\&\s-1ISO\s0 C. Also warn about \s-1ISO\s0 C constructs that have no traditional C +equivalent, and problematic constructs which should be avoided. +.IP "\fB\-Wundef\fR" 4 +.IX Item "-Wundef" +Warn whenever an identifier which is not a macro is encountered in an +\&\fB#if\fR directive, outside of \fBdefined\fR. Such identifiers are +replaced with zero. +.IP "\fB\-Wunused\-macros\fR" 4 +.IX Item "-Wunused-macros" +Warn about macros defined in the main file that are unused. A macro +is \fIused\fR if it is expanded or tested for existence at least once. +The preprocessor will also warn if the macro has not been used at the +time it is redefined or undefined. +.Sp +Built-in macros, macros defined on the command line, and macros +defined in include files are not warned about. +.Sp +\&\fINote:\fR If a macro is actually used, but only used in skipped +conditional blocks, then \s-1CPP\s0 will report it as unused. To avoid the +warning in such a case, you might improve the scope of the macro's +definition by, for example, moving it into the first skipped block. +Alternatively, you could provide a dummy use with something like: +.Sp +.Vb 2 +\& #if defined the_macro_causing_the_warning +\& #endif +.Ve +.IP "\fB\-Wendif\-labels\fR" 4 +.IX Item "-Wendif-labels" +Warn whenever an \fB#else\fR or an \fB#endif\fR are followed by text. +This usually happens in code of the form +.Sp +.Vb 5 +\& #if FOO +\& ... +\& #else FOO +\& ... +\& #endif FOO +.Ve +.Sp +The second and third \f(CW\*(C`FOO\*(C'\fR should be in comments, but often are not +in older programs. This warning is on by default. +.IP "\fB\-Werror\fR" 4 +.IX Item "-Werror" +Make all warnings into hard errors. Source code which triggers warnings +will be rejected. +.IP "\fB\-Wsystem\-headers\fR" 4 +.IX Item "-Wsystem-headers" +Issue warnings for code in system headers. These are normally unhelpful +in finding bugs in your own code, therefore suppressed. If you are +responsible for the system library, you may want to see them. +.IP "\fB\-w\fR" 4 +.IX Item "-w" +Suppress all warnings, including those which \s-1GNU\s0 \s-1CPP\s0 issues by default. +.IP "\fB\-pedantic\fR" 4 +.IX Item "-pedantic" +Issue all the mandatory diagnostics listed in the C standard. Some of +them are left out by default, since they trigger frequently on harmless +code. +.IP "\fB\-pedantic\-errors\fR" 4 +.IX Item "-pedantic-errors" +Issue all the mandatory diagnostics, and make all mandatory diagnostics +into errors. This includes mandatory diagnostics that \s-1GCC\s0 issues +without \fB\-pedantic\fR but treats as warnings. +.IP "\fB\-M\fR" 4 +.IX Item "-M" +Instead of outputting the result of preprocessing, output a rule +suitable for \fBmake\fR describing the dependencies of the main +source file. The preprocessor outputs one \fBmake\fR rule containing +the object file name for that source file, a colon, and the names of all +the included files, including those coming from \fB\-include\fR or +\&\fB\-imacros\fR command line options. +.Sp +Unless specified explicitly (with \fB\-MT\fR or \fB\-MQ\fR), the +object file name consists of the name of the source file with any +suffix replaced with object file suffix and with any leading directory +parts removed. If there are many included files then the rule is +split into several lines using \fB\e\fR\-newline. The rule has no +commands. +.Sp +This option does not suppress the preprocessor's debug output, such as +\&\fB\-dM\fR. To avoid mixing such debug output with the dependency +rules you should explicitly specify the dependency output file with +\&\fB\-MF\fR, or use an environment variable like +\&\fB\s-1DEPENDENCIES_OUTPUT\s0\fR. Debug output +will still be sent to the regular output stream as normal. +.Sp +Passing \fB\-M\fR to the driver implies \fB\-E\fR, and suppresses +warnings with an implicit \fB\-w\fR. +.IP "\fB\-MM\fR" 4 +.IX Item "-MM" +Like \fB\-M\fR but do not mention header files that are found in +system header directories, nor header files that are included, +directly or indirectly, from such a header. +.Sp +This implies that the choice of angle brackets or double quotes in an +\&\fB#include\fR directive does not in itself determine whether that +header will appear in \fB\-MM\fR dependency output. This is a +slight change in semantics from \s-1GCC\s0 versions 3.0 and earlier. +.IP "\fB\-MF\fR \fIfile\fR" 4 +.IX Item "-MF file" +When used with \fB\-M\fR or \fB\-MM\fR, specifies a +file to write the dependencies to. If no \fB\-MF\fR switch is given +the preprocessor sends the rules to the same place it would have sent +preprocessed output. +.Sp +When used with the driver options \fB\-MD\fR or \fB\-MMD\fR, +\&\fB\-MF\fR overrides the default dependency output file. +.IP "\fB\-MG\fR" 4 +.IX Item "-MG" +In conjunction with an option such as \fB\-M\fR requesting +dependency generation, \fB\-MG\fR assumes missing header files are +generated files and adds them to the dependency list without raising +an error. The dependency filename is taken directly from the +\&\f(CW\*(C`#include\*(C'\fR directive without prepending any path. \fB\-MG\fR +also suppresses preprocessed output, as a missing header file renders +this useless. +.Sp +This feature is used in automatic updating of makefiles. +.IP "\fB\-MP\fR" 4 +.IX Item "-MP" +This option instructs \s-1CPP\s0 to add a phony target for each dependency +other than the main file, causing each to depend on nothing. These +dummy rules work around errors \fBmake\fR gives if you remove header +files without updating the \fIMakefile\fR to match. +.Sp +This is typical output: +.Sp +.Vb 1 +\& test.o: test.c test.h +\& +\& test.h: +.Ve +.IP "\fB\-MT\fR \fItarget\fR" 4 +.IX Item "-MT target" +Change the target of the rule emitted by dependency generation. By +default \s-1CPP\s0 takes the name of the main input file, deletes any +directory components and any file suffix such as \fB.c\fR, and +appends the platform's usual object suffix. The result is the target. +.Sp +An \fB\-MT\fR option will set the target to be exactly the string you +specify. If you want multiple targets, you can specify them as a single +argument to \fB\-MT\fR, or use multiple \fB\-MT\fR options. +.Sp +For example, \fB\-MT\ '$(objpfx)foo.o'\fR might give +.Sp +.Vb 1 +\& $(objpfx)foo.o: foo.c +.Ve +.IP "\fB\-MQ\fR \fItarget\fR" 4 +.IX Item "-MQ target" +Same as \fB\-MT\fR, but it quotes any characters which are special to +Make. \fB\-MQ\ '$(objpfx)foo.o'\fR gives +.Sp +.Vb 1 +\& $$(objpfx)foo.o: foo.c +.Ve +.Sp +The default target is automatically quoted, as if it were given with +\&\fB\-MQ\fR. +.IP "\fB\-MD\fR" 4 +.IX Item "-MD" +\&\fB\-MD\fR is equivalent to \fB\-M \-MF\fR \fIfile\fR, except that +\&\fB\-E\fR is not implied. The driver determines \fIfile\fR based on +whether an \fB\-o\fR option is given. If it is, the driver uses its +argument but with a suffix of \fI.d\fR, otherwise it takes the name +of the input file, removes any directory components and suffix, and +applies a \fI.d\fR suffix. +.Sp +If \fB\-MD\fR is used in conjunction with \fB\-E\fR, any +\&\fB\-o\fR switch is understood to specify the dependency output file, but if used without \fB\-E\fR, each \fB\-o\fR +is understood to specify a target object file. +.Sp +Since \fB\-E\fR is not implied, \fB\-MD\fR can be used to generate +a dependency output file as a side-effect of the compilation process. +.IP "\fB\-MMD\fR" 4 +.IX Item "-MMD" +Like \fB\-MD\fR except mention only user header files, not system +header files. +.IP "\fB\-x c\fR" 4 +.IX Item "-x c" +.PD 0 +.IP "\fB\-x c++\fR" 4 +.IX Item "-x c++" +.IP "\fB\-x objective-c\fR" 4 +.IX Item "-x objective-c" +.IP "\fB\-x assembler-with-cpp\fR" 4 +.IX Item "-x assembler-with-cpp" +.PD +Specify the source language: C, \*(C+, Objective-C, or assembly. This has +nothing to do with standards conformance or extensions; it merely +selects which base syntax to expect. If you give none of these options, +cpp will deduce the language from the extension of the source file: +\&\fB.c\fR, \fB.cc\fR, \fB.m\fR, or \fB.S\fR. Some other common +extensions for \*(C+ and assembly are also recognized. If cpp does not +recognize the extension, it will treat the file as C; this is the most +generic mode. +.Sp +\&\fINote:\fR Previous versions of cpp accepted a \fB\-lang\fR option +which selected both the language and the standards conformance level. +This option has been removed, because it conflicts with the \fB\-l\fR +option. +.IP "\fB\-std=\fR\fIstandard\fR" 4 +.IX Item "-std=standard" +.PD 0 +.IP "\fB\-ansi\fR" 4 +.IX Item "-ansi" +.PD +Specify the standard to which the code should conform. Currently \s-1CPP\s0 +knows about C and \*(C+ standards; others may be added in the future. +.Sp +\&\fIstandard\fR +may be one of: +.RS 4 +.ie n .IP """c90""" 4 +.el .IP "\f(CWc90\fR" 4 +.IX Item "c90" +.PD 0 +.ie n .IP """c89""" 4 +.el .IP "\f(CWc89\fR" 4 +.IX Item "c89" +.ie n .IP """iso9899:1990""" 4 +.el .IP "\f(CWiso9899:1990\fR" 4 +.IX Item "iso9899:1990" +.PD +The \s-1ISO\s0 C standard from 1990. \fBc90\fR is the customary shorthand for +this version of the standard. +.Sp +The \fB\-ansi\fR option is equivalent to \fB\-std=c90\fR. +.ie n .IP """iso9899:199409""" 4 +.el .IP "\f(CWiso9899:199409\fR" 4 +.IX Item "iso9899:199409" +The 1990 C standard, as amended in 1994. +.ie n .IP """iso9899:1999""" 4 +.el .IP "\f(CWiso9899:1999\fR" 4 +.IX Item "iso9899:1999" +.PD 0 +.ie n .IP """c99""" 4 +.el .IP "\f(CWc99\fR" 4 +.IX Item "c99" +.ie n .IP """iso9899:199x""" 4 +.el .IP "\f(CWiso9899:199x\fR" 4 +.IX Item "iso9899:199x" +.ie n .IP """c9x""" 4 +.el .IP "\f(CWc9x\fR" 4 +.IX Item "c9x" +.PD +The revised \s-1ISO\s0 C standard, published in December 1999. Before +publication, this was known as C9X. +.ie n .IP """c1x""" 4 +.el .IP "\f(CWc1x\fR" 4 +.IX Item "c1x" +The next version of the \s-1ISO\s0 C standard, still under development. +.ie n .IP """gnu90""" 4 +.el .IP "\f(CWgnu90\fR" 4 +.IX Item "gnu90" +.PD 0 +.ie n .IP """gnu89""" 4 +.el .IP "\f(CWgnu89\fR" 4 +.IX Item "gnu89" +.PD +The 1990 C standard plus \s-1GNU\s0 extensions. This is the default. +.ie n .IP """gnu99""" 4 +.el .IP "\f(CWgnu99\fR" 4 +.IX Item "gnu99" +.PD 0 +.ie n .IP """gnu9x""" 4 +.el .IP "\f(CWgnu9x\fR" 4 +.IX Item "gnu9x" +.PD +The 1999 C standard plus \s-1GNU\s0 extensions. +.ie n .IP """gnu1x""" 4 +.el .IP "\f(CWgnu1x\fR" 4 +.IX Item "gnu1x" +The next version of the \s-1ISO\s0 C standard, still under development, plus +\&\s-1GNU\s0 extensions. +.ie n .IP """c++98""" 4 +.el .IP "\f(CWc++98\fR" 4 +.IX Item "c++98" +The 1998 \s-1ISO\s0 \*(C+ standard plus amendments. +.ie n .IP """gnu++98""" 4 +.el .IP "\f(CWgnu++98\fR" 4 +.IX Item "gnu++98" +The same as \fB\-std=c++98\fR plus \s-1GNU\s0 extensions. This is the +default for \*(C+ code. +.RE +.RS 4 +.RE +.IP "\fB\-I\-\fR" 4 +.IX Item "-I-" +Split the include path. Any directories specified with \fB\-I\fR +options before \fB\-I\-\fR are searched only for headers requested with +\&\f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR; they are not searched for +\&\f(CW\*(C`#include\ <\f(CIfile\f(CW>\*(C'\fR. If additional directories are +specified with \fB\-I\fR options after the \fB\-I\-\fR, those +directories are searched for all \fB#include\fR directives. +.Sp +In addition, \fB\-I\-\fR inhibits the use of the directory of the current +file directory as the first search directory for \f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR. +.Sp +This option has been deprecated. +.IP "\fB\-nostdinc\fR" 4 +.IX Item "-nostdinc" +Do not search the standard system directories for header files. +Only the directories you have specified with \fB\-I\fR options +(and the directory of the current file, if appropriate) are searched. +.IP "\fB\-nostdinc++\fR" 4 +.IX Item "-nostdinc++" +Do not search for header files in the \*(C+\-specific standard directories, +but do still search the other standard directories. (This option is +used when building the \*(C+ library.) +.IP "\fB\-include\fR \fIfile\fR" 4 +.IX Item "-include file" +Process \fIfile\fR as if \f(CW\*(C`#include "file"\*(C'\fR appeared as the first +line of the primary source file. However, the first directory searched +for \fIfile\fR is the preprocessor's working directory \fIinstead of\fR +the directory containing the main source file. If not found there, it +is searched for in the remainder of the \f(CW\*(C`#include "..."\*(C'\fR search +chain as normal. +.Sp +If multiple \fB\-include\fR options are given, the files are included +in the order they appear on the command line. +.IP "\fB\-imacros\fR \fIfile\fR" 4 +.IX Item "-imacros file" +Exactly like \fB\-include\fR, except that any output produced by +scanning \fIfile\fR is thrown away. Macros it defines remain defined. +This allows you to acquire all the macros from a header without also +processing its declarations. +.Sp +All files specified by \fB\-imacros\fR are processed before all files +specified by \fB\-include\fR. +.IP "\fB\-idirafter\fR \fIdir\fR" 4 +.IX Item "-idirafter dir" +Search \fIdir\fR for header files, but do it \fIafter\fR all +directories specified with \fB\-I\fR and the standard system directories +have been exhausted. \fIdir\fR is treated as a system include directory. +If \fIdir\fR begins with \f(CW\*(C`=\*(C'\fR, then the \f(CW\*(C`=\*(C'\fR will be replaced +by the sysroot prefix; see \fB\-\-sysroot\fR and \fB\-isysroot\fR. +.IP "\fB\-iprefix\fR \fIprefix\fR" 4 +.IX Item "-iprefix prefix" +Specify \fIprefix\fR as the prefix for subsequent \fB\-iwithprefix\fR +options. If the prefix represents a directory, you should include the +final \fB/\fR. +.IP "\fB\-iwithprefix\fR \fIdir\fR" 4 +.IX Item "-iwithprefix dir" +.PD 0 +.IP "\fB\-iwithprefixbefore\fR \fIdir\fR" 4 +.IX Item "-iwithprefixbefore dir" +.PD +Append \fIdir\fR to the prefix specified previously with +\&\fB\-iprefix\fR, and add the resulting directory to the include search +path. \fB\-iwithprefixbefore\fR puts it in the same place \fB\-I\fR +would; \fB\-iwithprefix\fR puts it where \fB\-idirafter\fR would. +.IP "\fB\-isysroot\fR \fIdir\fR" 4 +.IX Item "-isysroot dir" +This option is like the \fB\-\-sysroot\fR option, but applies only to +header files (except for Darwin targets, where it applies to both header +files and libraries). See the \fB\-\-sysroot\fR option for more +information. +.IP "\fB\-imultilib\fR \fIdir\fR" 4 +.IX Item "-imultilib dir" +Use \fIdir\fR as a subdirectory of the directory containing +target-specific \*(C+ headers. +.IP "\fB\-isystem\fR \fIdir\fR" 4 +.IX Item "-isystem dir" +Search \fIdir\fR for header files, after all directories specified by +\&\fB\-I\fR but before the standard system directories. Mark it +as a system directory, so that it gets the same special treatment as +is applied to the standard system directories. +.Sp +If \fIdir\fR begins with \f(CW\*(C`=\*(C'\fR, then the \f(CW\*(C`=\*(C'\fR will be replaced +by the sysroot prefix; see \fB\-\-sysroot\fR and \fB\-isysroot\fR. +.IP "\fB\-iquote\fR \fIdir\fR" 4 +.IX Item "-iquote dir" +Search \fIdir\fR only for header files requested with +\&\f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR; they are not searched for +\&\f(CW\*(C`#include\ <\f(CIfile\f(CW>\*(C'\fR, before all directories specified by +\&\fB\-I\fR and before the standard system directories. +.Sp +If \fIdir\fR begins with \f(CW\*(C`=\*(C'\fR, then the \f(CW\*(C`=\*(C'\fR will be replaced +by the sysroot prefix; see \fB\-\-sysroot\fR and \fB\-isysroot\fR. +.IP "\fB\-fdirectives\-only\fR" 4 +.IX Item "-fdirectives-only" +When preprocessing, handle directives, but do not expand macros. +.Sp +The option's behavior depends on the \fB\-E\fR and \fB\-fpreprocessed\fR +options. +.Sp +With \fB\-E\fR, preprocessing is limited to the handling of directives +such as \f(CW\*(C`#define\*(C'\fR, \f(CW\*(C`#ifdef\*(C'\fR, and \f(CW\*(C`#error\*(C'\fR. Other +preprocessor operations, such as macro expansion and trigraph +conversion are not performed. In addition, the \fB\-dD\fR option is +implicitly enabled. +.Sp +With \fB\-fpreprocessed\fR, predefinition of command line and most +builtin macros is disabled. Macros such as \f(CW\*(C`_\|_LINE_\|_\*(C'\fR, which are +contextually dependent, are handled normally. This enables compilation of +files previously preprocessed with \f(CW\*(C`\-E \-fdirectives\-only\*(C'\fR. +.Sp +With both \fB\-E\fR and \fB\-fpreprocessed\fR, the rules for +\&\fB\-fpreprocessed\fR take precedence. This enables full preprocessing of +files previously preprocessed with \f(CW\*(C`\-E \-fdirectives\-only\*(C'\fR. +.IP "\fB\-fdollars\-in\-identifiers\fR" 4 +.IX Item "-fdollars-in-identifiers" +Accept \fB$\fR in identifiers. +.IP "\fB\-fextended\-identifiers\fR" 4 +.IX Item "-fextended-identifiers" +Accept universal character names in identifiers. This option is +experimental; in a future version of \s-1GCC\s0, it will be enabled by +default for C99 and \*(C+. +.IP "\fB\-fpreprocessed\fR" 4 +.IX Item "-fpreprocessed" +Indicate to the preprocessor that the input file has already been +preprocessed. This suppresses things like macro expansion, trigraph +conversion, escaped newline splicing, and processing of most directives. +The preprocessor still recognizes and removes comments, so that you can +pass a file preprocessed with \fB\-C\fR to the compiler without +problems. In this mode the integrated preprocessor is little more than +a tokenizer for the front ends. +.Sp +\&\fB\-fpreprocessed\fR is implicit if the input file has one of the +extensions \fB.i\fR, \fB.ii\fR or \fB.mi\fR. These are the +extensions that \s-1GCC\s0 uses for preprocessed files created by +\&\fB\-save\-temps\fR. +.IP "\fB\-ftabstop=\fR\fIwidth\fR" 4 +.IX Item "-ftabstop=width" +Set the distance between tab stops. This helps the preprocessor report +correct column numbers in warnings or errors, even if tabs appear on the +line. If the value is less than 1 or greater than 100, the option is +ignored. The default is 8. +.IP "\fB\-fexec\-charset=\fR\fIcharset\fR" 4 +.IX Item "-fexec-charset=charset" +Set the execution character set, used for string and character +constants. The default is \s-1UTF\-8\s0. \fIcharset\fR can be any encoding +supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine. +.IP "\fB\-fwide\-exec\-charset=\fR\fIcharset\fR" 4 +.IX Item "-fwide-exec-charset=charset" +Set the wide execution character set, used for wide string and +character constants. The default is \s-1UTF\-32\s0 or \s-1UTF\-16\s0, whichever +corresponds to the width of \f(CW\*(C`wchar_t\*(C'\fR. As with +\&\fB\-fexec\-charset\fR, \fIcharset\fR can be any encoding supported +by the system's \f(CW\*(C`iconv\*(C'\fR library routine; however, you will have +problems with encodings that do not fit exactly in \f(CW\*(C`wchar_t\*(C'\fR. +.IP "\fB\-finput\-charset=\fR\fIcharset\fR" 4 +.IX Item "-finput-charset=charset" +Set the input character set, used for translation from the character +set of the input file to the source character set used by \s-1GCC\s0. If the +locale does not specify, or \s-1GCC\s0 cannot get this information from the +locale, the default is \s-1UTF\-8\s0. This can be overridden by either the locale +or this command line option. Currently the command line option takes +precedence if there's a conflict. \fIcharset\fR can be any encoding +supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine. +.IP "\fB\-fworking\-directory\fR" 4 +.IX Item "-fworking-directory" +Enable generation of linemarkers in the preprocessor output that will +let the compiler know the current working directory at the time of +preprocessing. When this option is enabled, the preprocessor will +emit, after the initial linemarker, a second linemarker with the +current working directory followed by two slashes. \s-1GCC\s0 will use this +directory, when it's present in the preprocessed input, as the +directory emitted as the current working directory in some debugging +information formats. This option is implicitly enabled if debugging +information is enabled, but this can be inhibited with the negated +form \fB\-fno\-working\-directory\fR. If the \fB\-P\fR flag is +present in the command line, this option has no effect, since no +\&\f(CW\*(C`#line\*(C'\fR directives are emitted whatsoever. +.IP "\fB\-fno\-show\-column\fR" 4 +.IX Item "-fno-show-column" +Do not print column numbers in diagnostics. This may be necessary if +diagnostics are being scanned by a program that does not understand the +column numbers, such as \fBdejagnu\fR. +.IP "\fB\-A\fR \fIpredicate\fR\fB=\fR\fIanswer\fR" 4 +.IX Item "-A predicate=answer" +Make an assertion with the predicate \fIpredicate\fR and answer +\&\fIanswer\fR. This form is preferred to the older form \fB\-A\fR +\&\fIpredicate\fR\fB(\fR\fIanswer\fR\fB)\fR, which is still supported, because +it does not use shell special characters. +.IP "\fB\-A \-\fR\fIpredicate\fR\fB=\fR\fIanswer\fR" 4 +.IX Item "-A -predicate=answer" +Cancel an assertion with the predicate \fIpredicate\fR and answer +\&\fIanswer\fR. +.IP "\fB\-dCHARS\fR" 4 +.IX Item "-dCHARS" +\&\fI\s-1CHARS\s0\fR is a sequence of one or more of the following characters, +and must not be preceded by a space. Other characters are interpreted +by the compiler proper, or reserved for future versions of \s-1GCC\s0, and so +are silently ignored. If you specify characters whose behavior +conflicts, the result is undefined. +.RS 4 +.IP "\fBM\fR" 4 +.IX Item "M" +Instead of the normal output, generate a list of \fB#define\fR +directives for all the macros defined during the execution of the +preprocessor, including predefined macros. This gives you a way of +finding out what is predefined in your version of the preprocessor. +Assuming you have no file \fIfoo.h\fR, the command +.Sp +.Vb 1 +\& touch foo.h; cpp \-dM foo.h +.Ve +.Sp +will show all the predefined macros. +.Sp +If you use \fB\-dM\fR without the \fB\-E\fR option, \fB\-dM\fR is +interpreted as a synonym for \fB\-fdump\-rtl\-mach\fR. +.IP "\fBD\fR" 4 +.IX Item "D" +Like \fBM\fR except in two respects: it does \fInot\fR include the +predefined macros, and it outputs \fIboth\fR the \fB#define\fR +directives and the result of preprocessing. Both kinds of output go to +the standard output file. +.IP "\fBN\fR" 4 +.IX Item "N" +Like \fBD\fR, but emit only the macro names, not their expansions. +.IP "\fBI\fR" 4 +.IX Item "I" +Output \fB#include\fR directives in addition to the result of +preprocessing. +.IP "\fBU\fR" 4 +.IX Item "U" +Like \fBD\fR except that only macros that are expanded, or whose +definedness is tested in preprocessor directives, are output; the +output is delayed until the use or test of the macro; and +\&\fB#undef\fR directives are also output for macros tested but +undefined at the time. +.RE +.RS 4 +.RE +.IP "\fB\-P\fR" 4 +.IX Item "-P" +Inhibit generation of linemarkers in the output from the preprocessor. +This might be useful when running the preprocessor on something that is +not C code, and will be sent to a program which might be confused by the +linemarkers. +.IP "\fB\-C\fR" 4 +.IX Item "-C" +Do not discard comments. All comments are passed through to the output +file, except for comments in processed directives, which are deleted +along with the directive. +.Sp +You should be prepared for side effects when using \fB\-C\fR; it +causes the preprocessor to treat comments as tokens in their own right. +For example, comments appearing at the start of what would be a +directive line have the effect of turning that line into an ordinary +source line, since the first token on the line is no longer a \fB#\fR. +.IP "\fB\-CC\fR" 4 +.IX Item "-CC" +Do not discard comments, including during macro expansion. This is +like \fB\-C\fR, except that comments contained within macros are +also passed through to the output file where the macro is expanded. +.Sp +In addition to the side-effects of the \fB\-C\fR option, the +\&\fB\-CC\fR option causes all \*(C+\-style comments inside a macro +to be converted to C\-style comments. This is to prevent later use +of that macro from inadvertently commenting out the remainder of +the source line. +.Sp +The \fB\-CC\fR option is generally used to support lint comments. +.IP "\fB\-traditional\-cpp\fR" 4 +.IX Item "-traditional-cpp" +Try to imitate the behavior of old-fashioned C preprocessors, as +opposed to \s-1ISO\s0 C preprocessors. +.IP "\fB\-trigraphs\fR" 4 +.IX Item "-trigraphs" +Process trigraph sequences. +.IP "\fB\-remap\fR" 4 +.IX Item "-remap" +Enable special code to work around file systems which only permit very +short file names, such as MS-DOS. +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +.PD 0 +.IP "\fB\-\-target\-help\fR" 4 +.IX Item "--target-help" +.PD +Print text describing all the command line options instead of +preprocessing anything. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +Verbose mode. Print out \s-1GNU\s0 \s-1CPP\s0's version number at the beginning of +execution, and report the final form of the include path. +.IP "\fB\-H\fR" 4 +.IX Item "-H" +Print the name of each header file used, in addition to other normal +activities. Each name is indented to show how deep in the +\&\fB#include\fR stack it is. Precompiled header files are also +printed, even if they are found to be invalid; an invalid precompiled +header file is printed with \fB...x\fR and a valid one with \fB...!\fR . +.IP "\fB\-version\fR" 4 +.IX Item "-version" +.PD 0 +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +.PD +Print out \s-1GNU\s0 \s-1CPP\s0's version number. With one dash, proceed to +preprocess as normal. With two dashes, exit immediately. +.SH "ENVIRONMENT" +.IX Header "ENVIRONMENT" +This section describes the environment variables that affect how \s-1CPP\s0 +operates. You can use them to specify directories or prefixes to use +when searching for include files, or to control dependency output. +.PP +Note that you can also specify places to search using options such as +\&\fB\-I\fR, and control dependency output with options like +\&\fB\-M\fR. These take precedence over +environment variables, which in turn take precedence over the +configuration of \s-1GCC\s0. +.IP "\fB\s-1CPATH\s0\fR" 4 +.IX Item "CPATH" +.PD 0 +.IP "\fBC_INCLUDE_PATH\fR" 4 +.IX Item "C_INCLUDE_PATH" +.IP "\fB\s-1CPLUS_INCLUDE_PATH\s0\fR" 4 +.IX Item "CPLUS_INCLUDE_PATH" +.IP "\fB\s-1OBJC_INCLUDE_PATH\s0\fR" 4 +.IX Item "OBJC_INCLUDE_PATH" +.PD +Each variable's value is a list of directories separated by a special +character, much like \fB\s-1PATH\s0\fR, in which to look for header files. +The special character, \f(CW\*(C`PATH_SEPARATOR\*(C'\fR, is target-dependent and +determined at \s-1GCC\s0 build time. For Microsoft Windows-based targets it is a +semicolon, and for almost all other targets it is a colon. +.Sp +\&\fB\s-1CPATH\s0\fR specifies a list of directories to be searched as if +specified with \fB\-I\fR, but after any paths given with \fB\-I\fR +options on the command line. This environment variable is used +regardless of which language is being preprocessed. +.Sp +The remaining environment variables apply only when preprocessing the +particular language indicated. Each specifies a list of directories +to be searched as if specified with \fB\-isystem\fR, but after any +paths given with \fB\-isystem\fR options on the command line. +.Sp +In all these variables, an empty element instructs the compiler to +search its current working directory. Empty elements can appear at the +beginning or end of a path. For instance, if the value of +\&\fB\s-1CPATH\s0\fR is \f(CW\*(C`:/special/include\*(C'\fR, that has the same +effect as \fB\-I.\ \-I/special/include\fR. +.IP "\fB\s-1DEPENDENCIES_OUTPUT\s0\fR" 4 +.IX Item "DEPENDENCIES_OUTPUT" +If this variable is set, its value specifies how to output +dependencies for Make based on the non-system header files processed +by the compiler. System header files are ignored in the dependency +output. +.Sp +The value of \fB\s-1DEPENDENCIES_OUTPUT\s0\fR can be just a file name, in +which case the Make rules are written to that file, guessing the target +name from the source file name. Or the value can have the form +\&\fIfile\fR\fB \fR\fItarget\fR, in which case the rules are written to +file \fIfile\fR using \fItarget\fR as the target name. +.Sp +In other words, this environment variable is equivalent to combining +the options \fB\-MM\fR and \fB\-MF\fR, +with an optional \fB\-MT\fR switch too. +.IP "\fB\s-1SUNPRO_DEPENDENCIES\s0\fR" 4 +.IX Item "SUNPRO_DEPENDENCIES" +This variable is the same as \fB\s-1DEPENDENCIES_OUTPUT\s0\fR (see above), +except that system header files are not ignored, so it implies +\&\fB\-M\fR rather than \fB\-MM\fR. However, the dependence on the +main input file is omitted. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fIgpl\fR\|(7), \fIgfdl\fR\|(7), \fIfsf\-funding\fR\|(7), +\&\fIgcc\fR\|(1), \fIas\fR\|(1), \fIld\fR\|(1), and the Info entries for \fIcpp\fR, \fIgcc\fR, and +\&\fIbinutils\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, +1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, +2008, 2009, 2010, 2011 +Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 or +any later version published by the Free Software Foundation. A copy of +the license is included in the +man page \fIgfdl\fR\|(7). +This manual contains no Invariant Sections. The Front-Cover Texts are +(a) (see below), and the Back-Cover Texts are (b) (see below). +.PP +(a) The \s-1FSF\s0's Front-Cover Text is: +.PP +.Vb 1 +\& A GNU Manual +.Ve +.PP +(b) The \s-1FSF\s0's Back-Cover Text is: +.PP +.Vb 3 +\& You have freedom to copy and modify this GNU Manual, like GNU +\& software. Copies published by the Free Software Foundation raise +\& funds for GNU development. +.Ve diff --git a/share/man/man1/arm-eabi-dlltool.1 b/share/man/man1/arm-eabi-dlltool.1 new file mode 100644 index 0000000..37d7cf2 --- /dev/null +++ b/share/man/man1/arm-eabi-dlltool.1 @@ -0,0 +1,531 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "DLLTOOL 1" +.TH DLLTOOL 1 " " "binutils-2.21" "GNU Development Tools" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +dlltool \- Create files needed to build and use DLLs. +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +dlltool [\fB\-d\fR|\fB\-\-input\-def\fR \fIdef-file-name\fR] + [\fB\-b\fR|\fB\-\-base\-file\fR \fIbase-file-name\fR] + [\fB\-e\fR|\fB\-\-output\-exp\fR \fIexports-file-name\fR] + [\fB\-z\fR|\fB\-\-output\-def\fR \fIdef-file-name\fR] + [\fB\-l\fR|\fB\-\-output\-lib\fR \fIlibrary-file-name\fR] + [\fB\-y\fR|\fB\-\-output\-delaylib\fR \fIlibrary-file-name\fR] + [\fB\-\-export\-all\-symbols\fR] [\fB\-\-no\-export\-all\-symbols\fR] + [\fB\-\-exclude\-symbols\fR \fIlist\fR] + [\fB\-\-no\-default\-excludes\fR] + [\fB\-S\fR|\fB\-\-as\fR \fIpath-to-assembler\fR] [\fB\-f\fR|\fB\-\-as\-flags\fR \fIoptions\fR] + [\fB\-D\fR|\fB\-\-dllname\fR \fIname\fR] [\fB\-m\fR|\fB\-\-machine\fR \fImachine\fR] + [\fB\-a\fR|\fB\-\-add\-indirect\fR] + [\fB\-U\fR|\fB\-\-add\-underscore\fR] [\fB\-\-add\-stdcall\-underscore\fR] + [\fB\-k\fR|\fB\-\-kill\-at\fR] [\fB\-A\fR|\fB\-\-add\-stdcall\-alias\fR] + [\fB\-p\fR|\fB\-\-ext\-prefix\-alias\fR \fIprefix\fR] + [\fB\-x\fR|\fB\-\-no\-idata4\fR] [\fB\-c\fR|\fB\-\-no\-idata5\fR] + [\fB\-\-use\-nul\-prefixed\-import\-tables\fR] + [\fB\-I\fR|\fB\-\-identify\fR \fIlibrary-file-name\fR] [\fB\-\-identify\-strict\fR] + [\fB\-i\fR|\fB\-\-interwork\fR] + [\fB\-n\fR|\fB\-\-nodelete\fR] [\fB\-t\fR|\fB\-\-temp\-prefix\fR \fIprefix\fR] + [\fB\-v\fR|\fB\-\-verbose\fR] + [\fB\-h\fR|\fB\-\-help\fR] [\fB\-V\fR|\fB\-\-version\fR] + [\fB\-\-no\-leading\-underscore\fR] [\fB\-\-leading\-underscore\fR] + [object\-file ...] +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +\&\fBdlltool\fR reads its inputs, which can come from the \fB\-d\fR and +\&\fB\-b\fR options as well as object files specified on the command +line. It then processes these inputs and if the \fB\-e\fR option has +been specified it creates a exports file. If the \fB\-l\fR option +has been specified it creates a library file and if the \fB\-z\fR option +has been specified it creates a def file. Any or all of the \fB\-e\fR, +\&\fB\-l\fR and \fB\-z\fR options can be present in one invocation of +dlltool. +.PP +When creating a \s-1DLL\s0, along with the source for the \s-1DLL\s0, it is necessary +to have three other files. \fBdlltool\fR can help with the creation of +these files. +.PP +The first file is a \fI.def\fR file which specifies which functions are +exported from the \s-1DLL\s0, which functions the \s-1DLL\s0 imports, and so on. This +is a text file and can be created by hand, or \fBdlltool\fR can be used +to create it using the \fB\-z\fR option. In this case \fBdlltool\fR +will scan the object files specified on its command line looking for +those functions which have been specially marked as being exported and +put entries for them in the \fI.def\fR file it creates. +.PP +In order to mark a function as being exported from a \s-1DLL\s0, it needs to +have an \fB\-export:<name_of_function>\fR entry in the \fB.drectve\fR +section of the object file. This can be done in C by using the +\&\fIasm()\fR operator: +.PP +.Vb 2 +\& asm (".section .drectve"); +\& asm (".ascii \e"\-export:my_func\e""); +\& +\& int my_func (void) { ... } +.Ve +.PP +The second file needed for \s-1DLL\s0 creation is an exports file. This file +is linked with the object files that make up the body of the \s-1DLL\s0 and it +handles the interface between the \s-1DLL\s0 and the outside world. This is a +binary file and it can be created by giving the \fB\-e\fR option to +\&\fBdlltool\fR when it is creating or reading in a \fI.def\fR file. +.PP +The third file needed for \s-1DLL\s0 creation is the library file that programs +will link with in order to access the functions in the \s-1DLL\s0 (an `import +library'). This file can be created by giving the \fB\-l\fR option to +dlltool when it is creating or reading in a \fI.def\fR file. +.PP +If the \fB\-y\fR option is specified, dlltool generates a delay-import +library that can be used instead of the normal import library to allow +a program to link to the dll only as soon as an imported function is +called for the first time. The resulting executable will need to be +linked to the static delayimp library containing _\|\fI_delayLoadHelper2()\fR, +which in turn will import LoadLibraryA and GetProcAddress from kernel32. +.PP +\&\fBdlltool\fR builds the library file by hand, but it builds the +exports file by creating temporary files containing assembler statements +and then assembling these. The \fB\-S\fR command line option can be +used to specify the path to the assembler that dlltool will use, +and the \fB\-f\fR option can be used to pass specific flags to that +assembler. The \fB\-n\fR can be used to prevent dlltool from deleting +these temporary assembler files when it is done, and if \fB\-n\fR is +specified twice then this will prevent dlltool from deleting the +temporary object files it used to build the library. +.PP +Here is an example of creating a \s-1DLL\s0 from a source file \fBdll.c\fR and +also creating a program (from an object file called \fBprogram.o\fR) +that uses that \s-1DLL:\s0 +.PP +.Vb 4 +\& gcc \-c dll.c +\& dlltool \-e exports.o \-l dll.lib dll.o +\& gcc dll.o exports.o \-o dll.dll +\& gcc program.o dll.lib \-o program +.Ve +.PP +\&\fBdlltool\fR may also be used to query an existing import library +to determine the name of the \s-1DLL\s0 to which it is associated. See the +description of the \fB\-I\fR or \fB\-\-identify\fR option. +.SH "OPTIONS" +.IX Header "OPTIONS" +The command line options have the following meanings: +.IP "\fB\-d\fR \fIfilename\fR" 4 +.IX Item "-d filename" +.PD 0 +.IP "\fB\-\-input\-def\fR \fIfilename\fR" 4 +.IX Item "--input-def filename" +.PD +Specifies the name of a \fI.def\fR file to be read in and processed. +.IP "\fB\-b\fR \fIfilename\fR" 4 +.IX Item "-b filename" +.PD 0 +.IP "\fB\-\-base\-file\fR \fIfilename\fR" 4 +.IX Item "--base-file filename" +.PD +Specifies the name of a base file to be read in and processed. The +contents of this file will be added to the relocation section in the +exports file generated by dlltool. +.IP "\fB\-e\fR \fIfilename\fR" 4 +.IX Item "-e filename" +.PD 0 +.IP "\fB\-\-output\-exp\fR \fIfilename\fR" 4 +.IX Item "--output-exp filename" +.PD +Specifies the name of the export file to be created by dlltool. +.IP "\fB\-z\fR \fIfilename\fR" 4 +.IX Item "-z filename" +.PD 0 +.IP "\fB\-\-output\-def\fR \fIfilename\fR" 4 +.IX Item "--output-def filename" +.PD +Specifies the name of the \fI.def\fR file to be created by dlltool. +.IP "\fB\-l\fR \fIfilename\fR" 4 +.IX Item "-l filename" +.PD 0 +.IP "\fB\-\-output\-lib\fR \fIfilename\fR" 4 +.IX Item "--output-lib filename" +.PD +Specifies the name of the library file to be created by dlltool. +.IP "\fB\-y\fR \fIfilename\fR" 4 +.IX Item "-y filename" +.PD 0 +.IP "\fB\-\-output\-delaylib\fR \fIfilename\fR" 4 +.IX Item "--output-delaylib filename" +.PD +Specifies the name of the delay-import library file to be created by dlltool. +.IP "\fB\-\-export\-all\-symbols\fR" 4 +.IX Item "--export-all-symbols" +Treat all global and weak defined symbols found in the input object +files as symbols to be exported. There is a small list of symbols which +are not exported by default; see the \fB\-\-no\-default\-excludes\fR +option. You may add to the list of symbols to not export by using the +\&\fB\-\-exclude\-symbols\fR option. +.IP "\fB\-\-no\-export\-all\-symbols\fR" 4 +.IX Item "--no-export-all-symbols" +Only export symbols explicitly listed in an input \fI.def\fR file or in +\&\fB.drectve\fR sections in the input object files. This is the default +behaviour. The \fB.drectve\fR sections are created by \fBdllexport\fR +attributes in the source code. +.IP "\fB\-\-exclude\-symbols\fR \fIlist\fR" 4 +.IX Item "--exclude-symbols list" +Do not export the symbols in \fIlist\fR. This is a list of symbol names +separated by comma or colon characters. The symbol names should not +contain a leading underscore. This is only meaningful when +\&\fB\-\-export\-all\-symbols\fR is used. +.IP "\fB\-\-no\-default\-excludes\fR" 4 +.IX Item "--no-default-excludes" +When \fB\-\-export\-all\-symbols\fR is used, it will by default avoid +exporting certain special symbols. The current list of symbols to avoid +exporting is \fBDllMain@12\fR, \fBDllEntryPoint@0\fR, +\&\fBimpure_ptr\fR. You may use the \fB\-\-no\-default\-excludes\fR option +to go ahead and export these special symbols. This is only meaningful +when \fB\-\-export\-all\-symbols\fR is used. +.IP "\fB\-S\fR \fIpath\fR" 4 +.IX Item "-S path" +.PD 0 +.IP "\fB\-\-as\fR \fIpath\fR" 4 +.IX Item "--as path" +.PD +Specifies the path, including the filename, of the assembler to be used +to create the exports file. +.IP "\fB\-f\fR \fIoptions\fR" 4 +.IX Item "-f options" +.PD 0 +.IP "\fB\-\-as\-flags\fR \fIoptions\fR" 4 +.IX Item "--as-flags options" +.PD +Specifies any specific command line options to be passed to the +assembler when building the exports file. This option will work even if +the \fB\-S\fR option is not used. This option only takes one argument, +and if it occurs more than once on the command line, then later +occurrences will override earlier occurrences. So if it is necessary to +pass multiple options to the assembler they should be enclosed in +double quotes. +.IP "\fB\-D\fR \fIname\fR" 4 +.IX Item "-D name" +.PD 0 +.IP "\fB\-\-dll\-name\fR \fIname\fR" 4 +.IX Item "--dll-name name" +.PD +Specifies the name to be stored in the \fI.def\fR file as the name of +the \s-1DLL\s0 when the \fB\-e\fR option is used. If this option is not +present, then the filename given to the \fB\-e\fR option will be +used as the name of the \s-1DLL\s0. +.IP "\fB\-m\fR \fImachine\fR" 4 +.IX Item "-m machine" +.PD 0 +.IP "\fB\-machine\fR \fImachine\fR" 4 +.IX Item "-machine machine" +.PD +Specifies the type of machine for which the library file should be +built. \fBdlltool\fR has a built in default type, depending upon how +it was created, but this option can be used to override that. This is +normally only useful when creating DLLs for an \s-1ARM\s0 processor, when the +contents of the \s-1DLL\s0 are actually encode using Thumb instructions. +.IP "\fB\-a\fR" 4 +.IX Item "-a" +.PD 0 +.IP "\fB\-\-add\-indirect\fR" 4 +.IX Item "--add-indirect" +.PD +Specifies that when \fBdlltool\fR is creating the exports file it +should add a section which allows the exported functions to be +referenced without using the import library. Whatever the hell that +means! +.IP "\fB\-U\fR" 4 +.IX Item "-U" +.PD 0 +.IP "\fB\-\-add\-underscore\fR" 4 +.IX Item "--add-underscore" +.PD +Specifies that when \fBdlltool\fR is creating the exports file it +should prepend an underscore to the names of \fIall\fR exported symbols. +.IP "\fB\-\-no\-leading\-underscore\fR" 4 +.IX Item "--no-leading-underscore" +.PD 0 +.IP "\fB\-\-leading\-underscore\fR" 4 +.IX Item "--leading-underscore" +.PD +Specifies whether standard symbol should be forced to be prefixed, or +not. +.IP "\fB\-\-add\-stdcall\-underscore\fR" 4 +.IX Item "--add-stdcall-underscore" +Specifies that when \fBdlltool\fR is creating the exports file it +should prepend an underscore to the names of exported \fIstdcall\fR +functions. Variable names and non-stdcall function names are not modified. +This option is useful when creating GNU-compatible import libs for third +party DLLs that were built with MS-Windows tools. +.IP "\fB\-k\fR" 4 +.IX Item "-k" +.PD 0 +.IP "\fB\-\-kill\-at\fR" 4 +.IX Item "--kill-at" +.PD +Specifies that when \fBdlltool\fR is creating the exports file it +should not append the string \fB@ <number>\fR. These numbers are +called ordinal numbers and they represent another way of accessing the +function in a \s-1DLL\s0, other than by name. +.IP "\fB\-A\fR" 4 +.IX Item "-A" +.PD 0 +.IP "\fB\-\-add\-stdcall\-alias\fR" 4 +.IX Item "--add-stdcall-alias" +.PD +Specifies that when \fBdlltool\fR is creating the exports file it +should add aliases for stdcall symbols without \fB@ <number>\fR +in addition to the symbols with \fB@ <number>\fR. +.IP "\fB\-p\fR" 4 +.IX Item "-p" +.PD 0 +.IP "\fB\-\-ext\-prefix\-alias\fR \fIprefix\fR" 4 +.IX Item "--ext-prefix-alias prefix" +.PD +Causes \fBdlltool\fR to create external aliases for all \s-1DLL\s0 +imports with the specified prefix. The aliases are created for both +external and import symbols with no leading underscore. +.IP "\fB\-x\fR" 4 +.IX Item "-x" +.PD 0 +.IP "\fB\-\-no\-idata4\fR" 4 +.IX Item "--no-idata4" +.PD +Specifies that when \fBdlltool\fR is creating the exports and library +files it should omit the \f(CW\*(C`.idata4\*(C'\fR section. This is for compatibility +with certain operating systems. +.IP "\fB\-\-use\-nul\-prefixed\-import\-tables\fR" 4 +.IX Item "--use-nul-prefixed-import-tables" +Specifies that when \fBdlltool\fR is creating the exports and library +files it should prefix the \f(CW\*(C`.idata4\*(C'\fR and \f(CW\*(C`.idata5\*(C'\fR by zero an +element. This emulates old gnu import library generation of +\&\f(CW\*(C`dlltool\*(C'\fR. By default this option is turned off. +.IP "\fB\-c\fR" 4 +.IX Item "-c" +.PD 0 +.IP "\fB\-\-no\-idata5\fR" 4 +.IX Item "--no-idata5" +.PD +Specifies that when \fBdlltool\fR is creating the exports and library +files it should omit the \f(CW\*(C`.idata5\*(C'\fR section. This is for compatibility +with certain operating systems. +.IP "\fB\-I\fR \fIfilename\fR" 4 +.IX Item "-I filename" +.PD 0 +.IP "\fB\-\-identify\fR \fIfilename\fR" 4 +.IX Item "--identify filename" +.PD +Specifies that \fBdlltool\fR should inspect the import library +indicated by \fIfilename\fR and report, on \f(CW\*(C`stdout\*(C'\fR, the name(s) +of the associated \s-1DLL\s0(s). This can be performed in addition to any +other operations indicated by the other options and arguments. +\&\fBdlltool\fR fails if the import library does not exist or is not +actually an import library. See also \fB\-\-identify\-strict\fR. +.IP "\fB\-\-identify\-strict\fR" 4 +.IX Item "--identify-strict" +Modifies the behavior of the \fB\-\-identify\fR option, such +that an error is reported if \fIfilename\fR is associated with +more than one \s-1DLL\s0. +.IP "\fB\-i\fR" 4 +.IX Item "-i" +.PD 0 +.IP "\fB\-\-interwork\fR" 4 +.IX Item "--interwork" +.PD +Specifies that \fBdlltool\fR should mark the objects in the library +file and exports file that it produces as supporting interworking +between \s-1ARM\s0 and Thumb code. +.IP "\fB\-n\fR" 4 +.IX Item "-n" +.PD 0 +.IP "\fB\-\-nodelete\fR" 4 +.IX Item "--nodelete" +.PD +Makes \fBdlltool\fR preserve the temporary assembler files it used to +create the exports file. If this option is repeated then dlltool will +also preserve the temporary object files it uses to create the library +file. +.IP "\fB\-t\fR \fIprefix\fR" 4 +.IX Item "-t prefix" +.PD 0 +.IP "\fB\-\-temp\-prefix\fR \fIprefix\fR" 4 +.IX Item "--temp-prefix prefix" +.PD +Makes \fBdlltool\fR use \fIprefix\fR when constructing the names of +temporary assembler and object files. By default, the temp file prefix +is generated from the pid. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +.PD 0 +.IP "\fB\-\-verbose\fR" 4 +.IX Item "--verbose" +.PD +Make dlltool describe what it is doing. +.IP "\fB\-h\fR" 4 +.IX Item "-h" +.PD 0 +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +.PD +Displays a list of command line options and then exits. +.IP "\fB\-V\fR" 4 +.IX Item "-V" +.PD 0 +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +.PD +Displays dlltool's version number and then exits. +.IP "\fB@\fR\fIfile\fR" 4 +.IX Item "@file" +Read command-line options from \fIfile\fR. The options read are +inserted in place of the original @\fIfile\fR option. If \fIfile\fR +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +.Sp +Options in \fIfile\fR are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The \fIfile\fR may itself contain additional +@\fIfile\fR options; any such options will be processed recursively. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +The Info pages for \fIbinutils\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 +or any later version published by the Free Software Foundation; +with no Invariant Sections, with no Front-Cover Texts, and with no +Back-Cover Texts. A copy of the license is included in the +section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". diff --git a/share/man/man1/arm-eabi-elfedit.1 b/share/man/man1/arm-eabi-elfedit.1 new file mode 100644 index 0000000..dc21437 --- /dev/null +++ b/share/man/man1/arm-eabi-elfedit.1 @@ -0,0 +1,233 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "ELFEDIT 1" +.TH ELFEDIT 1 " " "binutils-2.21" "GNU Development Tools" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +elfedit \- Update the ELF header of ELF files. +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +elfedit [\fB\-\-input\-mach=\fR\fImachine\fR] + [\fB\-\-input\-type=\fR\fItype\fR] + [\fB\-\-input\-osabi=\fR\fIosbi\fR] + \fB\-\-output\-mach=\fR\fImachine\fR + \fB\-\-output\-type=\fR\fItype\fR + \fB\-\-output\-osabi=\fR\fIosbi\fR + [\fB\-v\fR|\fB\-\-version\fR] + [\fB\-h\fR|\fB\-\-help\fR] + \fIelffile\fR... +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +\&\fBelfedit\fR updates the \s-1ELF\s0 header of \s-1ELF\s0 files which have +the matching \s-1ELF\s0 machine and file types. The options control how and +which fields in the \s-1ELF\s0 header should be updated. +.PP +\&\fIelffile\fR... are the \s-1ELF\s0 files to be updated. 32\-bit and +64\-bit \s-1ELF\s0 files are supported, as are archives containing \s-1ELF\s0 files. +.SH "OPTIONS" +.IX Header "OPTIONS" +The long and short forms of options, shown here as alternatives, are +equivalent. At least one of the \fB\-\-output\-mach\fR, +\&\fB\-\-output\-type\fR and \fB\-\-output\-osabi\fR options must be given. +.IP "\fB\-\-input\-mach=\fR\fImachine\fR" 4 +.IX Item "--input-mach=machine" +Set the matching input \s-1ELF\s0 machine type to \fImachine\fR. If +\&\fB\-\-input\-mach\fR isn't specified, it will match any \s-1ELF\s0 +machine types. +.Sp +The supported \s-1ELF\s0 machine types are, \fIL1OM\fR and \fIx86\-64\fR. +.IP "\fB\-\-output\-mach=\fR\fImachine\fR" 4 +.IX Item "--output-mach=machine" +Change the \s-1ELF\s0 machine type in the \s-1ELF\s0 header to \fImachine\fR. The +supported \s-1ELF\s0 machine types are the same as \fB\-\-input\-mach\fR. +.IP "\fB\-\-input\-type=\fR\fItype\fR" 4 +.IX Item "--input-type=type" +Set the matching input \s-1ELF\s0 file type to \fItype\fR. If +\&\fB\-\-input\-type\fR isn't specified, it will match any \s-1ELF\s0 file types. +.Sp +The supported \s-1ELF\s0 file types are, \fIrel\fR, \fIexec\fR and \fIdyn\fR. +.IP "\fB\-\-output\-type=\fR\fItype\fR" 4 +.IX Item "--output-type=type" +Change the \s-1ELF\s0 file type in the \s-1ELF\s0 header to \fItype\fR. The +supported \s-1ELF\s0 types are the same as \fB\-\-input\-type\fR. +.IP "\fB\-\-input\-osabi=\fR\fIosabi\fR" 4 +.IX Item "--input-osabi=osabi" +Set the matching input \s-1ELF\s0 file \s-1OSABI\s0 to \fIosbi\fR. If +\&\fB\-\-input\-osabi\fR isn't specified, it will match any \s-1ELF\s0 OSABIs. +.Sp +The supported \s-1ELF\s0 OSABIs are, \fInone\fR, \fI\s-1HPUX\s0\fR, \fINetBSD\fR, +\&\fILinux\fR, \fIHurd\fR, \fISolaris\fR, \fI\s-1AIX\s0\fR, \fIIrix\fR, +\&\fIFreeBSD\fR, \fI\s-1TRU64\s0\fR, \fIModesto\fR, \fIOpenBSD\fR, \fIOpenVMS\fR, +\&\fI\s-1NSK\s0\fR, \fI\s-1AROS\s0\fR and \fIFenixOS\fR. +.IP "\fB\-\-output\-osabi=\fR\fIosabi\fR" 4 +.IX Item "--output-osabi=osabi" +Change the \s-1ELF\s0 \s-1OSABI\s0 in the \s-1ELF\s0 header to \fItype\fR. The +supported \s-1ELF\s0 \s-1OSABI\s0 are the same as \fB\-\-input\-osabi\fR. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +.PD 0 +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +.PD +Display the version number of \fBelfedit\fR. +.IP "\fB\-h\fR" 4 +.IX Item "-h" +.PD 0 +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +.PD +Display the command line options understood by \fBelfedit\fR. +.IP "\fB@\fR\fIfile\fR" 4 +.IX Item "@file" +Read command-line options from \fIfile\fR. The options read are +inserted in place of the original @\fIfile\fR option. If \fIfile\fR +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +.Sp +Options in \fIfile\fR are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The \fIfile\fR may itself contain additional +@\fIfile\fR options; any such options will be processed recursively. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fIreadelf\fR\|(1), and the Info entries for \fIbinutils\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 +or any later version published by the Free Software Foundation; +with no Invariant Sections, with no Front-Cover Texts, and with no +Back-Cover Texts. A copy of the license is included in the +section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". diff --git a/share/man/man1/arm-eabi-g++.1 b/share/man/man1/arm-eabi-g++.1 new file mode 100644 index 0000000..d08d4ac --- /dev/null +++ b/share/man/man1/arm-eabi-g++.1 @@ -0,0 +1,17818 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "GCC 1" +.TH GCC 1 "2012-01-06" "gcc-4.6.x-google" "GNU" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +gcc \- GNU project C and C++ compiler +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +gcc [\fB\-c\fR|\fB\-S\fR|\fB\-E\fR] [\fB\-std=\fR\fIstandard\fR] + [\fB\-g\fR] [\fB\-pg\fR] [\fB\-O\fR\fIlevel\fR] + [\fB\-W\fR\fIwarn\fR...] [\fB\-pedantic\fR] + [\fB\-I\fR\fIdir\fR...] [\fB\-L\fR\fIdir\fR...] + [\fB\-D\fR\fImacro\fR[=\fIdefn\fR]...] [\fB\-U\fR\fImacro\fR] + [\fB\-f\fR\fIoption\fR...] [\fB\-m\fR\fImachine-option\fR...] + [\fB\-o\fR \fIoutfile\fR] [@\fIfile\fR] \fIinfile\fR... +.PP +Only the most useful options are listed here; see below for the +remainder. \fBg++\fR accepts mostly the same options as \fBgcc\fR. +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +When you invoke \s-1GCC\s0, it normally does preprocessing, compilation, +assembly and linking. The \*(L"overall options\*(R" allow you to stop this +process at an intermediate stage. For example, the \fB\-c\fR option +says not to run the linker. Then the output consists of object files +output by the assembler. +.PP +Other options are passed on to one stage of processing. Some options +control the preprocessor and others the compiler itself. Yet other +options control the assembler and linker; most of these are not +documented here, since you rarely need to use any of them. +.PP +Most of the command line options that you can use with \s-1GCC\s0 are useful +for C programs; when an option is only useful with another language +(usually \*(C+), the explanation says so explicitly. If the description +for a particular option does not mention a source language, you can use +that option with all supported languages. +.PP +The \fBgcc\fR program accepts options and file names as operands. Many +options have multi-letter names; therefore multiple single-letter options +may \fInot\fR be grouped: \fB\-dv\fR is very different from \fB\-d\ \-v\fR. +.PP +You can mix options and other arguments. For the most part, the order +you use doesn't matter. Order does matter when you use several +options of the same kind; for example, if you specify \fB\-L\fR more +than once, the directories are searched in the order specified. Also, +the placement of the \fB\-l\fR option is significant. +.PP +Many options have long names starting with \fB\-f\fR or with +\&\fB\-W\fR\-\-\-for example, +\&\fB\-fmove\-loop\-invariants\fR, \fB\-Wformat\fR and so on. Most of +these have both positive and negative forms; the negative form of +\&\fB\-ffoo\fR would be \fB\-fno\-foo\fR. This manual documents +only one of these two forms, whichever one is not the default. +.SH "OPTIONS" +.IX Header "OPTIONS" +.SS "Option Summary" +.IX Subsection "Option Summary" +Here is a summary of all the options, grouped by type. Explanations are +in the following sections. +.IP "\fIOverall Options\fR" 4 +.IX Item "Overall Options" +\&\fB\-c \-S \-E \-o\fR \fIfile\fR \fB\-no\-canonical\-prefixes +\&\-pipe \-pass\-exit\-codes +\&\-x\fR \fIlanguage\fR \fB\-v \-### \-\-help\fR[\fB=\fR\fIclass\fR[\fB,...\fR]] \fB\-\-target\-help +\&\-\-version \-wrapper @\fR\fIfile\fR \fB\-fplugin=\fR\fIfile\fR \fB\-fplugin\-arg\-\fR\fIname\fR\fB=\fR\fIarg\fR +\&\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] \-fdump\-go\-spec=\fIfile\fR +.IP "\fIC Language Options\fR" 4 +.IX Item "C Language Options" +\&\fB\-ansi \-std=\fR\fIstandard\fR \fB\-fgnu89\-inline +\&\-aux\-info\fR \fIfilename\fR +\&\fB\-fno\-asm \-fno\-builtin \-fno\-builtin\-\fR\fIfunction\fR +\&\fB\-fhosted \-ffreestanding \-fopenmp \-fms\-extensions \-fplan9\-extensions +\&\-trigraphs \-no\-integrated\-cpp \-traditional \-traditional\-cpp +\&\-fallow\-single\-precision \-fcond\-mismatch \-flax\-vector\-conversions +\&\-fsigned\-bitfields \-fsigned\-char +\&\-funsigned\-bitfields \-funsigned\-char\fR +.IP "\fI\*(C+ Language Options\fR" 4 +.IX Item " Language Options" +\&\fB\-fabi\-version=\fR\fIn\fR \fB\-fno\-access\-control \-fcheck\-new +\&\-fconserve\-space \-fconstexpr\-depth=\fR\fIn\fR \fB\-ffriend\-injection +\&\-fno\-elide\-constructors +\&\-fno\-enforce\-eh\-specs +\&\-ffor\-scope \-fno\-for\-scope \-fno\-gnu\-keywords +\&\-fno\-implicit\-templates +\&\-fno\-implicit\-inline\-templates +\&\-fno\-implement\-inlines \-fms\-extensions +\&\-fno\-nonansi\-builtins \-fnothrow\-opt \-fno\-operator\-names +\&\-fno\-optional\-diags \-fpermissive +\&\-fno\-pretty\-templates +\&\-frepo \-fno\-rtti \-fstats \-ftemplate\-depth=\fR\fIn\fR +\&\fB\-fno\-threadsafe\-statics \-fuse\-cxa\-atexit \-fno\-weak \-nostdinc++ +\&\-fno\-default\-inline \-fvisibility\-inlines\-hidden +\&\-fvisibility\-ms\-compat +\&\-Wabi \-Wconversion\-null \-Wctor\-dtor\-privacy +\&\-Wnoexcept \-Wnon\-virtual\-dtor \-Wreorder +\&\-Weffc++ \-Wstrict\-null\-sentinel +\&\-Wno\-non\-template\-friend \-Wold\-style\-cast +\&\-Woverloaded\-virtual \-Wno\-pmf\-conversions +\&\-Wsign\-promo\fR +.IP "\fIObjective-C and Objective\-\*(C+ Language Options\fR" 4 +.IX Item "Objective-C and Objective- Language Options" +\&\fB\-fconstant\-string\-class=\fR\fIclass-name\fR +\&\fB\-fgnu\-runtime \-fnext\-runtime +\&\-fno\-nil\-receivers +\&\-fobjc\-abi\-version=\fR\fIn\fR +\&\fB\-fobjc\-call\-cxx\-cdtors +\&\-fobjc\-direct\-dispatch +\&\-fobjc\-exceptions +\&\-fobjc\-gc +\&\-fobjc\-nilcheck +\&\-fobjc\-std=objc1 +\&\-freplace\-objc\-classes +\&\-fzero\-link +\&\-gen\-decls +\&\-Wassign\-intercept +\&\-Wno\-protocol \-Wselector +\&\-Wstrict\-selector\-match +\&\-Wundeclared\-selector\fR +.IP "\fILanguage Independent Options\fR" 4 +.IX Item "Language Independent Options" +\&\fB\-fmessage\-length=\fR\fIn\fR +\&\fB\-fdiagnostics\-show\-location=\fR[\fBonce\fR|\fBevery-line\fR] +\&\fB\-fno\-diagnostics\-show\-option\fR +.IP "\fIWarning Options\fR" 4 +.IX Item "Warning Options" +\&\fB\-fsyntax\-only \-fmax\-errors=\fR\fIn\fR \fB\-pedantic +\&\-pedantic\-errors +\&\-w \-Wextra \-Wall \-Waddress \-Waggregate\-return \-Warray\-bounds +\&\-Wno\-attributes \-Wno\-builtin\-macro\-redefined +\&\-Wc++\-compat \-Wc++0x\-compat \-Wcast\-align \-Wcast\-qual +\&\-Wchar\-subscripts \-Wclobbered \-Wcomment +\&\-Wconversion \-Wcoverage\-mismatch \-Wno\-cpp \-Wno\-deprecated +\&\-Wno\-deprecated\-declarations \-Wdisabled\-optimization +\&\-Wno\-div\-by\-zero \-Wdouble\-promotion \-Wempty\-body \-Wenum\-compare +\&\-Wno\-endif\-labels \-Werror \-Werror=* +\&\-Wfatal\-errors \-Wfloat\-equal \-Wformat \-Wformat=2 +\&\-Wno\-format\-contains\-nul \-Wno\-format\-extra\-args \-Wformat\-nonliteral +\&\-Wformat\-security \-Wformat\-y2k +\&\-Wframe\-larger\-than=\fR\fIlen\fR \fB\-Wjump\-misses\-init \-Wignored\-qualifiers +\&\-Wimplicit \-Wimplicit\-function\-declaration \-Wimplicit\-int +\&\-Winit\-self \-Winline \-Wmaybe\-uninitialized +\&\-Wno\-int\-to\-pointer\-cast \-Wno\-invalid\-offsetof +\&\-Winvalid\-pch \-Wlarger\-than=\fR\fIlen\fR \fB\-Wunsafe\-loop\-optimizations +\&\-Wlogical\-op \-Wlong\-long +\&\-Wmain \-Wmaybe\-uninitialized \-Wmissing\-braces \-Wmissing\-field\-initializers +\&\-Wmissing\-format\-attribute \-Wmissing\-include\-dirs +\&\-Wno\-mudflap +\&\-Wno\-multichar \-Wnonnull \-Wno\-overflow +\&\-Woverlength\-strings \-Wpacked \-Wpacked\-bitfield\-compat \-Wpadded +\&\-Wparentheses \-Wpedantic\-ms\-format \-Wno\-pedantic\-ms\-format +\&\-Wpointer\-arith \-Wno\-pointer\-to\-int\-cast +\&\-Wreal\-conversion \-Wredundant\-decls \-Wreturn\-type \-Wripa\-opt\-mismatch +\&\-Wself\-assign \-Wself\-assign\-non\-pod \-Wsequence\-point \-Wshadow +\&\-Wshadow\-compatible\-local \-Wshadow\-local +\&\-Wsign\-compare \-Wsign\-conversion \-Wstack\-protector +\&\-Wstrict\-aliasing \-Wstrict\-aliasing=n +\&\-Wstrict\-overflow \-Wstrict\-overflow=\fR\fIn\fR +\&\fB\-Wsuggest\-attribute=\fR[\fBpure\fR|\fBconst\fR|\fBnoreturn\fR] +\&\fB\-Wswitch \-Wswitch\-default \-Wswitch\-enum \-Wsync\-nand +\&\-Wsystem\-headers \-Wthread\-safety \-Wthread\-unguarded\-var +\&\-Wthread\-unguarded\-func \-Wthread\-mismatched\-lock\-order +\&\-Wthread\-mismatched\-lock\-acq\-rel \-Wthread\-reentrant\-lock +\&\-Wthread\-unsupported\-lock\-name \-Wthread\-attr\-bind\-param +\&\-Wtrampolines \-Wtrigraphs \-Wtype\-limits \-Wundef +\&\-Wuninitialized \-Wunknown\-pragmas \-Wno\-pragmas +\&\-Wunsuffixed\-float\-constants \-Wunused \-Wunused\-function +\&\-Wunused\-label \-Wunused\-parameter \-Wno\-unused\-result \-Wunused\-value +\&\-Wunused\-variable \-Wunused\-but\-set\-parameter \-Wunused\-but\-set\-variable +\&\-Wvariadic\-macros \-Wvla \-Wvolatile\-register\-var \-Wwrite\-strings\fR +.IP "\fIC and Objective-C-only Warning Options\fR" 4 +.IX Item "C and Objective-C-only Warning Options" +\&\fB\-Wbad\-function\-cast \-Wmissing\-declarations +\&\-Wmissing\-parameter\-type \-Wmissing\-prototypes \-Wnested\-externs +\&\-Wold\-style\-declaration \-Wold\-style\-definition +\&\-Wstrict\-prototypes \-Wtraditional \-Wtraditional\-conversion +\&\-Wdeclaration\-after\-statement \-Wpointer\-sign\fR +.IP "\fIDebugging Options\fR" 4 +.IX Item "Debugging Options" +\&\fB\-d\fR\fIletters\fR \fB\-dumpspecs \-dumpmachine \-dumpversion +\&\-fdbg\-cnt\-list \-fdbg\-cnt=\fR\fIcounter-value-list\fR +\&\fB\-fdisable\-ipa\-\fR\fIpass_name\fR +\&\fB\-fdisable\-rtl\-\fR\fIpass_name\fR +\&\fB\-fdisable\-rtl\-\fR\fIpass-name\fR\fB=\fR\fIrange-list\fR +\&\fB\-fdisable\-tree\-\fR\fIpass_name\fR +\&\fB\-fdisable\-tree\-\fR\fIpass-name\fR\fB=\fR\fIrange-list\fR +\&\fB\-fdump\-noaddr \-fdump\-unnumbered \-fdump\-unnumbered\-links +\&\-fdump\-translation\-unit\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-class\-hierarchy\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-ipa\-all \-fdump\-ipa\-cgraph \-fdump\-ipa\-inline +\&\-fdump\-passes +\&\-fdump\-statistics +\&\-fdump\-tree\-all +\&\-fdump\-tree\-original\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-optimized\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-cfg \-fdump\-tree\-vcg \-fdump\-tree\-alias +\&\-fdump\-tree\-ch +\&\-fdump\-tree\-ssa\fR[\fB\-\fR\fIn\fR] \fB\-fdump\-tree\-pre\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-ccp\fR[\fB\-\fR\fIn\fR] \fB\-fdump\-tree\-dce\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-gimple\fR[\fB\-raw\fR] \fB\-fdump\-tree\-mudflap\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-dom\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-dse\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-phiprop\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-phiopt\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-forwprop\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-copyrename\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-nrv \-fdump\-tree\-vect +\&\-fdump\-tree\-sink +\&\-fdump\-tree\-sra\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-forwprop\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-fre\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-vrp\fR[\fB\-\fR\fIn\fR] +\&\fB\-ftree\-vectorizer\-verbose=\fR\fIn\fR +\&\fB\-fdump\-tree\-storeccp\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-final\-insns=\fR\fIfile\fR +\&\fB\-fcompare\-debug\fR[\fB=\fR\fIopts\fR] \fB\-fcompare\-debug\-second +\&\-feliminate\-dwarf2\-dups \-feliminate\-unused\-debug\-types +\&\-feliminate\-unused\-debug\-symbols \-femit\-class\-debug\-always +\&\-fenable\-icf\-debug +\&\-fenable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR +\&\fB\-fenable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR +\&\fB\-fdebug\-types\-section +\&\-fmem\-report \-fpre\-ipa\-mem\-report \-fpost\-ipa\-mem\-report \-fprofile\-arcs +\&\-frandom\-seed=\fR\fIstring\fR \fB\-fsched\-verbose=\fR\fIn\fR +\&\fB\-fsel\-sched\-verbose \-fsel\-sched\-dump\-cfg \-fsel\-sched\-pipelining\-verbose +\&\-fstack\-usage \-ftest\-coverage \-ftime\-report \-fvar\-tracking +\&\-fvar\-tracking\-assignments \-fvar\-tracking\-assignments\-toggle +\&\-g \-g\fR\fIlevel\fR \fB\-gtoggle \-gcoff \-gdwarf\-\fR\fIversion\fR +\&\fB\-ggdb \-gmlt \-gstabs \-gstabs+ \-gstrict\-dwarf \-gno\-strict\-dwarf +\&\-gvms \-gxcoff \-gxcoff+ +\&\-fno\-merge\-debug\-strings \-fno\-dwarf2\-cfi\-asm +\&\-fdebug\-prefix\-map=\fR\fIold\fR\fB=\fR\fInew\fR +\&\fB\-femit\-struct\-debug\-baseonly \-femit\-struct\-debug\-reduced +\&\-femit\-struct\-debug\-detailed\fR[\fB=\fR\fIspec-list\fR] +\&\fB\-p \-pg \-print\-file\-name=\fR\fIlibrary\fR \fB\-print\-libgcc\-file\-name +\&\-print\-multi\-directory \-print\-multi\-lib \-print\-multi\-os\-directory +\&\-print\-prog\-name=\fR\fIprogram\fR \fB\-print\-search\-dirs \-Q +\&\-print\-sysroot \-print\-sysroot\-headers\-suffix +\&\-save\-temps \-save\-temps=cwd \-save\-temps=obj \-time\fR[\fB=\fR\fIfile\fR] +.IP "\fIOptimization Options\fR" 4 +.IX Item "Optimization Options" +\&\fB\-falign\-functions[=\fR\fIn\fR\fB] \-falign\-jumps[=\fR\fIn\fR\fB] +\&\-falign\-labels[=\fR\fIn\fR\fB] \-falign\-loops[=\fR\fIn\fR\fB] \-fassociative\-math +\&\-fauto\-inc\-dec \-fbranch\-probabilities \-fbranch\-target\-load\-optimize +\&\-fbranch\-target\-load\-optimize2 \-fbtr\-bb\-exclusive \-fcaller\-saves +\&\-fcallgraph\-profiles\-sections \-fcheck\-data\-deps \-fclone\-hot\-version\-paths +\&\-fcombine\-stack\-adjustments \-fconserve\-stack +\&\-fcompare\-elim \-fcprop\-registers \-fcrossjumping +\&\-fcse\-follow\-jumps \-fcse\-skip\-blocks \-fcx\-fortran\-rules +\&\-fcx\-limited\-range +\&\-fdata\-sections \-fdce \-fdce \-fdelayed\-branch +\&\-fdelete\-null\-pointer\-checks \-fdse \-fdevirtualize \-fdse +\&\-fearly\-inlining \-fipa\-sra \-fexpensive\-optimizations \-ffast\-math +\&\-ffinite\-math\-only \-ffloat\-store \-fexcess\-precision=\fR\fIstyle\fR +\&\fB\-fforward\-propagate \-ffp\-contract=\fR\fIstyle\fR \fB\-ffunction\-sections +\&\-fgcse \-fgcse\-after\-reload \-fgcse\-las \-fgcse\-lm \-fgraphite\-identity +\&\-fgcse\-sm \-fif\-conversion \-fif\-conversion2 \-findirect\-inlining +\&\-finline\-functions \-finline\-functions\-called\-once \-finline\-limit=\fR\fIn\fR +\&\fB\-finline\-small\-functions \-fipa\-cp \-fipa\-cp\-clone \-fipa\-matrix\-reorg +\&\-fipa\-pta \-fipa\-profile \-fipa\-pure\-const \-fipa\-reference +\&\-fipa\-struct\-reorg \-fira\-algorithm=\fR\fIalgorithm\fR +\&\fB\-fira\-region=\fR\fIregion\fR +\&\fB\-fira\-loop\-pressure \-fno\-ira\-share\-save\-slots +\&\-fno\-ira\-share\-spill\-slots \-fira\-verbose=\fR\fIn\fR +\&\fB\-fivopts \-fkeep\-inline\-functions \-fkeep\-static\-consts +\&\-floop\-block \-floop\-flatten \-floop\-interchange \-floop\-strip\-mine +\&\-floop\-parallelize\-all \-flto \-flto\-compression\-level +\&\-flto\-partition=\fR\fIalg\fR \fB\-flto\-report \-fmerge\-all\-constants +\&\-fmerge\-constants \-fmodulo\-sched \-fmodulo\-sched\-allow\-regmoves +\&\-fmove\-loop\-invariants fmudflap \-fmudflapir \-fmudflapth \-fno\-branch\-count\-reg +\&\-fno\-default\-inline +\&\-fno\-defer\-pop \-fno\-function\-cse \-fno\-guess\-branch\-probability +\&\-fno\-inline \-fno\-math\-errno \-fno\-peephole \-fno\-peephole2 +\&\-fno\-sched\-interblock \-fno\-sched\-spec \-fno\-signed\-zeros +\&\-fno\-toplevel\-reorder \-fno\-trapping\-math \-fno\-zero\-initialized\-in\-bss +\&\-fomit\-frame\-pointer \-foptimize\-register\-move \-foptimize\-sibling\-calls +\&\-fpartial\-inlining \-fpeel\-loops \-fpredictive\-commoning +\&\-fprefetch\-loop\-arrays +\&\-fprofile\-correction \-fprofile\-dir=\fR\fIpath\fR \fB\-fprofile\-generate +\&\-fprofile\-generate=\fR\fIpath\fR \fB\-fprofile\-generate\-sampling +\&\-fprofile\-use \-fprofile\-use=\fR\fIpath\fR \fB\-fprofile\-values +\&\-fpmu\-profile\-generate=\fR\fIpmuoption\fR +\&\fB\-fpmu\-profile\-use=\fR\fIpmuoption\fR +\&\fB\-freciprocal\-math \-fregmove \-frename\-registers \-freorder\-blocks +\&\-frecord\-gcc\-switches\-in\-elf +\&\-freorder\-blocks\-and\-partition \-freorder\-functions +\&\-frerun\-cse\-after\-loop \-freschedule\-modulo\-scheduled\-loops +\&\-fripa \-fripa\-disallow\-asm\-modules \-fripa\-disallow\-opt\-mismatch +\&\-fripa\-no\-promote\-always\-inline\-func \-fripa\-verbose +\&\-fripa\-peel\-size\-limit \-fripa\-unroll\-size\-limit \-frounding\-math +\&\-fsched2\-use\-superblocks \-fsched\-pressure +\&\-fsched\-spec\-load \-fsched\-spec\-load\-dangerous +\&\-fsched\-stalled\-insns\-dep[=\fR\fIn\fR\fB] \-fsched\-stalled\-insns[=\fR\fIn\fR\fB] +\&\-fsched\-group\-heuristic \-fsched\-critical\-path\-heuristic +\&\-fsched\-spec\-insn\-heuristic \-fsched\-rank\-heuristic +\&\-fsched\-last\-insn\-heuristic \-fsched\-dep\-count\-heuristic +\&\-fschedule\-insns \-fschedule\-insns2 \-fsection\-anchors +\&\-fselective\-scheduling \-fselective\-scheduling2 +\&\-fsel\-sched\-pipelining \-fsel\-sched\-pipelining\-outer\-loops +\&\-fsignaling\-nans \-fsingle\-precision\-constant \-fsplit\-ivs\-in\-unroller +\&\-fsplit\-wide\-types \-fstack\-protector \-fstack\-protector\-all +\&\-fstack\-protector\-strong \-fstrict\-aliasing \-fstrict\-overflow +\&\-fthread\-jumps \-ftracer \-ftree\-bit\-ccp +\&\-ftree\-builtin\-call\-dce \-ftree\-ccp \-ftree\-ch \-ftree\-copy\-prop +\&\-ftree\-copyrename \-ftree\-dce \-ftree\-dominator\-opts \-ftree\-dse +\&\-ftree\-forwprop \-ftree\-fre \-ftree\-loop\-if\-convert +\&\-ftree\-loop\-if\-convert\-stores \-ftree\-loop\-im +\&\-ftree\-phiprop \-ftree\-loop\-distribution \-ftree\-loop\-distribute\-patterns +\&\-ftree\-loop\-ivcanon \-ftree\-loop\-linear \-ftree\-loop\-optimize +\&\-ftree\-parallelize\-loops=\fR\fIn\fR \fB\-ftree\-pre \-ftree\-pta \-ftree\-reassoc +\&\-ftree\-sink \-ftree\-sra \-ftree\-switch\-conversion +\&\-ftree\-ter \-ftree\-vect\-loop\-version \-ftree\-vectorize \-ftree\-vrp +\&\-funit\-at\-a\-time \-funroll\-all\-loops \-funroll\-loops +\&\-funsafe\-loop\-optimizations \-funsafe\-math\-optimizations \-funswitch\-loops +\&\-fvariable\-expansion\-in\-unroller \-fvect\-cost\-model \-fvpt \-fweb +\&\-fwhole\-program \-fwpa \-fuse\-ld \-fuse\-linker\-plugin +\&\-\-param\fR \fIname\fR\fB=\fR\fIvalue\fR +\&\fB\-O \-O0 \-O1 \-O2 \-O3 \-Os \-Ofast\fR +.IP "\fIPreprocessor Options\fR" 4 +.IX Item "Preprocessor Options" +\&\fB\-A\fR\fIquestion\fR\fB=\fR\fIanswer\fR +\&\fB\-A\-\fR\fIquestion\fR[\fB=\fR\fIanswer\fR] +\&\fB\-C \-dD \-dI \-dM \-dN +\&\-D\fR\fImacro\fR[\fB=\fR\fIdefn\fR] \fB\-E \-H +\&\-idirafter\fR \fIdir\fR +\&\fB\-include\fR \fIfile\fR \fB\-imacros\fR \fIfile\fR +\&\fB\-iprefix\fR \fIfile\fR \fB\-iwithprefix\fR \fIdir\fR +\&\fB\-iwithprefixbefore\fR \fIdir\fR \fB\-isystem\fR \fIdir\fR +\&\fB\-imultilib\fR \fIdir\fR \fB\-isysroot\fR \fIdir\fR +\&\fB\-M \-MM \-MF \-MG \-MP \-MQ \-MT \-nostdinc +\&\-P \-fworking\-directory \-remap +\&\-trigraphs \-undef \-U\fR\fImacro\fR \fB\-Wp,\fR\fIoption\fR +\&\fB\-Xpreprocessor\fR \fIoption\fR +.IP "\fIAssembler Option\fR" 4 +.IX Item "Assembler Option" +\&\fB\-Wa,\fR\fIoption\fR \fB\-Xassembler\fR \fIoption\fR +.IP "\fILinker Options\fR" 4 +.IX Item "Linker Options" +\&\fIobject-file-name\fR \fB\-l\fR\fIlibrary\fR +\&\fB\-nostartfiles \-nodefaultlibs \-nostdlib \-pie \-rdynamic +\&\-s \-static \-static\-libgcc \-static\-libstdc++ \-shared +\&\-shared\-libgcc \-symbolic +\&\-T\fR \fIscript\fR \fB\-Wl,\fR\fIoption\fR \fB\-Xlinker\fR \fIoption\fR +\&\fB\-u\fR \fIsymbol\fR +.IP "\fIDirectory Options\fR" 4 +.IX Item "Directory Options" +\&\fB\-B\fR\fIprefix\fR \fB\-I\fR\fIdir\fR \fB\-iplugindir=\fR\fIdir\fR +\&\-iquote\fIdir\fR \-L\fIdir\fR \-specs=\fIfile\fR \-I\- +\&\-\-sysroot=\fIdir\fR +.IP "\fIMachine Dependent Options\fR" 4 +.IX Item "Machine Dependent Options" +\&\fI\s-1ARC\s0 Options\fR +\&\fB\-EB \-EL +\&\-mmangle\-cpu \-mcpu=\fR\fIcpu\fR \fB\-mtext=\fR\fItext-section\fR +\&\fB\-mdata=\fR\fIdata-section\fR \fB\-mrodata=\fR\fIreadonly-data-section\fR +.Sp +\&\fI\s-1ARM\s0 Options\fR +\&\fB\-mapcs\-frame \-mno\-apcs\-frame +\&\-mabi=\fR\fIname\fR +\&\fB\-mapcs\-stack\-check \-mno\-apcs\-stack\-check +\&\-mapcs\-float \-mno\-apcs\-float +\&\-mapcs\-reentrant \-mno\-apcs\-reentrant +\&\-msched\-prolog \-mno\-sched\-prolog +\&\-mlittle\-endian \-mbig\-endian \-mwords\-little\-endian +\&\-mfloat\-abi=\fR\fIname\fR \fB\-msoft\-float \-mhard\-float \-mfpe +\&\-mfp16\-format=\fR\fIname\fR +\&\fB\-mthumb\-interwork \-mno\-thumb\-interwork +\&\-mcpu=\fR\fIname\fR \fB\-march=\fR\fIname\fR \fB\-mfpu=\fR\fIname\fR +\&\fB\-mstructure\-size\-boundary=\fR\fIn\fR +\&\fB\-mabort\-on\-noreturn +\&\-mlong\-calls \-mno\-long\-calls +\&\-msingle\-pic\-base \-mno\-single\-pic\-base +\&\-mpic\-register=\fR\fIreg\fR +\&\fB\-mnop\-fun\-dllimport +\&\-mcirrus\-fix\-invalid\-insns \-mno\-cirrus\-fix\-invalid\-insns +\&\-mpoke\-function\-name +\&\-mthumb \-marm +\&\-mtpcs\-frame \-mtpcs\-leaf\-frame +\&\-mcaller\-super\-interworking \-mcallee\-super\-interworking +\&\-mtp=\fR\fIname\fR +\&\fB\-mword\-relocations +\&\-mfix\-cortex\-m3\-ldrd\fR +.Sp +\&\fI\s-1AVR\s0 Options\fR +\&\fB\-mmcu=\fR\fImcu\fR \fB\-mno\-interrupts +\&\-mcall\-prologues \-mtiny\-stack \-mint8\fR +.Sp +\&\fIBlackfin Options\fR +\&\fB\-mcpu=\fR\fIcpu\fR[\fB\-\fR\fIsirevision\fR] +\&\fB\-msim \-momit\-leaf\-frame\-pointer \-mno\-omit\-leaf\-frame\-pointer +\&\-mspecld\-anomaly \-mno\-specld\-anomaly \-mcsync\-anomaly \-mno\-csync\-anomaly +\&\-mlow\-64k \-mno\-low64k \-mstack\-check\-l1 \-mid\-shared\-library +\&\-mno\-id\-shared\-library \-mshared\-library\-id=\fR\fIn\fR +\&\fB\-mleaf\-id\-shared\-library \-mno\-leaf\-id\-shared\-library +\&\-msep\-data \-mno\-sep\-data \-mlong\-calls \-mno\-long\-calls +\&\-mfast\-fp \-minline\-plt \-mmulticore \-mcorea \-mcoreb \-msdram +\&\-micplb\fR +.Sp +\&\fI\s-1CRIS\s0 Options\fR +\&\fB\-mcpu=\fR\fIcpu\fR \fB\-march=\fR\fIcpu\fR \fB\-mtune=\fR\fIcpu\fR +\&\fB\-mmax\-stack\-frame=\fR\fIn\fR \fB\-melinux\-stacksize=\fR\fIn\fR +\&\fB\-metrax4 \-metrax100 \-mpdebug \-mcc\-init \-mno\-side\-effects +\&\-mstack\-align \-mdata\-align \-mconst\-align +\&\-m32\-bit \-m16\-bit \-m8\-bit \-mno\-prologue\-epilogue \-mno\-gotplt +\&\-melf \-maout \-melinux \-mlinux \-sim \-sim2 +\&\-mmul\-bug\-workaround \-mno\-mul\-bug\-workaround\fR +.Sp +\&\fI\s-1CRX\s0 Options\fR +\&\fB\-mmac \-mpush\-args\fR +.Sp +\&\fIDarwin Options\fR +\&\fB\-all_load \-allowable_client \-arch \-arch_errors_fatal +\&\-arch_only \-bind_at_load \-bundle \-bundle_loader +\&\-client_name \-compatibility_version \-current_version +\&\-dead_strip +\&\-dependency\-file \-dylib_file \-dylinker_install_name +\&\-dynamic \-dynamiclib \-exported_symbols_list +\&\-filelist \-flat_namespace \-force_cpusubtype_ALL +\&\-force_flat_namespace \-headerpad_max_install_names +\&\-iframework +\&\-image_base \-init \-install_name \-keep_private_externs +\&\-multi_module \-multiply_defined \-multiply_defined_unused +\&\-noall_load \-no_dead_strip_inits_and_terms +\&\-nofixprebinding \-nomultidefs \-noprebind \-noseglinkedit +\&\-pagezero_size \-prebind \-prebind_all_twolevel_modules +\&\-private_bundle \-read_only_relocs \-sectalign +\&\-sectobjectsymbols \-whyload \-seg1addr +\&\-sectcreate \-sectobjectsymbols \-sectorder +\&\-segaddr \-segs_read_only_addr \-segs_read_write_addr +\&\-seg_addr_table \-seg_addr_table_filename \-seglinkedit +\&\-segprot \-segs_read_only_addr \-segs_read_write_addr +\&\-single_module \-static \-sub_library \-sub_umbrella +\&\-twolevel_namespace \-umbrella \-undefined +\&\-unexported_symbols_list \-weak_reference_mismatches +\&\-whatsloaded \-F \-gused \-gfull \-mmacosx\-version\-min=\fR\fIversion\fR +\&\fB\-mkernel \-mone\-byte\-bool\fR +.Sp +\&\fI\s-1DEC\s0 Alpha Options\fR +\&\fB\-mno\-fp\-regs \-msoft\-float \-malpha\-as \-mgas +\&\-mieee \-mieee\-with\-inexact \-mieee\-conformant +\&\-mfp\-trap\-mode=\fR\fImode\fR \fB\-mfp\-rounding\-mode=\fR\fImode\fR +\&\fB\-mtrap\-precision=\fR\fImode\fR \fB\-mbuild\-constants +\&\-mcpu=\fR\fIcpu-type\fR \fB\-mtune=\fR\fIcpu-type\fR +\&\fB\-mbwx \-mmax \-mfix \-mcix +\&\-mfloat\-vax \-mfloat\-ieee +\&\-mexplicit\-relocs \-msmall\-data \-mlarge\-data +\&\-msmall\-text \-mlarge\-text +\&\-mmemory\-latency=\fR\fItime\fR +.Sp +\&\fI\s-1DEC\s0 Alpha/VMS Options\fR +\&\fB\-mvms\-return\-codes \-mdebug\-main=\fR\fIprefix\fR \fB\-mmalloc64\fR +.Sp +\&\fI\s-1FR30\s0 Options\fR +\&\fB\-msmall\-model \-mno\-lsim\fR +.Sp +\&\fI\s-1FRV\s0 Options\fR +\&\fB\-mgpr\-32 \-mgpr\-64 \-mfpr\-32 \-mfpr\-64 +\&\-mhard\-float \-msoft\-float +\&\-malloc\-cc \-mfixed\-cc \-mdword \-mno\-dword +\&\-mdouble \-mno\-double +\&\-mmedia \-mno\-media \-mmuladd \-mno\-muladd +\&\-mfdpic \-minline\-plt \-mgprel\-ro \-multilib\-library\-pic +\&\-mlinked\-fp \-mlong\-calls \-malign\-labels +\&\-mlibrary\-pic \-macc\-4 \-macc\-8 +\&\-mpack \-mno\-pack \-mno\-eflags \-mcond\-move \-mno\-cond\-move +\&\-moptimize\-membar \-mno\-optimize\-membar +\&\-mscc \-mno\-scc \-mcond\-exec \-mno\-cond\-exec +\&\-mvliw\-branch \-mno\-vliw\-branch +\&\-mmulti\-cond\-exec \-mno\-multi\-cond\-exec \-mnested\-cond\-exec +\&\-mno\-nested\-cond\-exec \-mtomcat\-stats +\&\-mTLS \-mtls +\&\-mcpu=\fR\fIcpu\fR +.Sp +\&\fIGNU/Linux Options\fR +\&\fB\-mglibc \-muclibc \-mbionic \-mandroid +\&\-tno\-android\-cc \-tno\-android\-ld\fR +.Sp +\&\fIH8/300 Options\fR +\&\fB\-mrelax \-mh \-ms \-mn \-mint32 \-malign\-300\fR +.Sp +\&\fI\s-1HPPA\s0 Options\fR +\&\fB\-march=\fR\fIarchitecture-type\fR +\&\fB\-mbig\-switch \-mdisable\-fpregs \-mdisable\-indexing +\&\-mfast\-indirect\-calls \-mgas \-mgnu\-ld \-mhp\-ld +\&\-mfixed\-range=\fR\fIregister-range\fR +\&\fB\-mjump\-in\-delay \-mlinker\-opt \-mlong\-calls +\&\-mlong\-load\-store \-mno\-big\-switch \-mno\-disable\-fpregs +\&\-mno\-disable\-indexing \-mno\-fast\-indirect\-calls \-mno\-gas +\&\-mno\-jump\-in\-delay \-mno\-long\-load\-store +\&\-mno\-portable\-runtime \-mno\-soft\-float +\&\-mno\-space\-regs \-msoft\-float \-mpa\-risc\-1\-0 +\&\-mpa\-risc\-1\-1 \-mpa\-risc\-2\-0 \-mportable\-runtime +\&\-mschedule=\fR\fIcpu-type\fR \fB\-mspace\-regs \-msio \-mwsio +\&\-munix=\fR\fIunix-std\fR \fB\-nolibdld \-static \-threads\fR +.Sp +\&\fIi386 and x86\-64 Options\fR +\&\fB\-mtune=\fR\fIcpu-type\fR \fB\-march=\fR\fIcpu-type\fR +\&\fB\-mfpmath=\fR\fIunit\fR +\&\fB\-masm=\fR\fIdialect\fR \fB\-mno\-fancy\-math\-387 +\&\-mno\-fp\-ret\-in\-387 \-msoft\-float +\&\-mno\-wide\-multiply \-mrtd \-malign\-double +\&\-mpreferred\-stack\-boundary=\fR\fInum\fR +\&\fB\-mincoming\-stack\-boundary=\fR\fInum\fR +\&\fB\-mcld \-mcx16 \-msahf \-mmovbe \-mcrc32 \-mrecip \-mvzeroupper +\&\-mmmx \-msse \-msse2 \-msse3 \-mssse3 \-msse4.1 \-msse4.2 \-msse4 \-mavx +\&\-maes \-mpclmul \-mfsgsbase \-mrdrnd \-mf16c \-mfused\-madd +\&\-msse4a \-m3dnow \-mpopcnt \-mabm \-mbmi \-mtbm \-mfma4 \-mxop \-mlwp +\&\-mthreads \-mno\-align\-stringops \-minline\-all\-stringops +\&\-minline\-stringops\-dynamically \-mstringop\-strategy=\fR\fIalg\fR +\&\fB\-mpush\-args \-maccumulate\-outgoing\-args \-m128bit\-long\-double +\&\-m96bit\-long\-double \-mregparm=\fR\fInum\fR \fB\-msseregparm +\&\-mveclibabi=\fR\fItype\fR \fB\-mvect8\-ret\-in\-mem +\&\-mpc32 \-mpc64 \-mpc80 \-mstackrealign +\&\-momit\-leaf\-frame\-pointer \-mno\-red\-zone \-mno\-tls\-direct\-seg\-refs +\&\-mcmodel=\fR\fIcode-model\fR \fB\-mabi=\fR\fIname\fR +\&\fB\-m32 \-m64 \-mlarge\-data\-threshold=\fR\fInum\fR +\&\fB\-msse2avx \-mfentry \-m8bit\-idiv +\&\-mavx256\-split\-unaligned\-load \-mavx256\-split\-unaligned\-store\fR +.Sp +\&\fIi386 and x86\-64 Windows Options\fR +\&\fB\-mconsole \-mcygwin \-mno\-cygwin \-mdll +\&\-mnop\-fun\-dllimport \-mthread +\&\-municode \-mwin32 \-mwindows \-fno\-set\-stack\-executable\fR +.Sp +\&\fI\s-1IA\-64\s0 Options\fR +\&\fB\-mbig\-endian \-mlittle\-endian \-mgnu\-as \-mgnu\-ld \-mno\-pic +\&\-mvolatile\-asm\-stop \-mregister\-names \-msdata \-mno\-sdata +\&\-mconstant\-gp \-mauto\-pic \-mfused\-madd +\&\-minline\-float\-divide\-min\-latency +\&\-minline\-float\-divide\-max\-throughput +\&\-mno\-inline\-float\-divide +\&\-minline\-int\-divide\-min\-latency +\&\-minline\-int\-divide\-max\-throughput +\&\-mno\-inline\-int\-divide +\&\-minline\-sqrt\-min\-latency \-minline\-sqrt\-max\-throughput +\&\-mno\-inline\-sqrt +\&\-mdwarf2\-asm \-mearly\-stop\-bits +\&\-mfixed\-range=\fR\fIregister-range\fR \fB\-mtls\-size=\fR\fItls-size\fR +\&\fB\-mtune=\fR\fIcpu-type\fR \fB\-milp32 \-mlp64 +\&\-msched\-br\-data\-spec \-msched\-ar\-data\-spec \-msched\-control\-spec +\&\-msched\-br\-in\-data\-spec \-msched\-ar\-in\-data\-spec \-msched\-in\-control\-spec +\&\-msched\-spec\-ldc \-msched\-spec\-control\-ldc +\&\-msched\-prefer\-non\-data\-spec\-insns \-msched\-prefer\-non\-control\-spec\-insns +\&\-msched\-stop\-bits\-after\-every\-cycle \-msched\-count\-spec\-in\-critical\-path +\&\-msel\-sched\-dont\-check\-control\-spec \-msched\-fp\-mem\-deps\-zero\-cost +\&\-msched\-max\-memory\-insns\-hard\-limit \-msched\-max\-memory\-insns=\fR\fImax-insns\fR +.Sp +\&\fI\s-1IA\-64/VMS\s0 Options\fR +\&\fB\-mvms\-return\-codes \-mdebug\-main=\fR\fIprefix\fR \fB\-mmalloc64\fR +.Sp +\&\fI\s-1LM32\s0 Options\fR +\&\fB\-mbarrel\-shift\-enabled \-mdivide\-enabled \-mmultiply\-enabled +\&\-msign\-extend\-enabled \-muser\-enabled\fR +.Sp +\&\fIM32R/D Options\fR +\&\fB\-m32r2 \-m32rx \-m32r +\&\-mdebug +\&\-malign\-loops \-mno\-align\-loops +\&\-missue\-rate=\fR\fInumber\fR +\&\fB\-mbranch\-cost=\fR\fInumber\fR +\&\fB\-mmodel=\fR\fIcode-size-model-type\fR +\&\fB\-msdata=\fR\fIsdata-type\fR +\&\fB\-mno\-flush\-func \-mflush\-func=\fR\fIname\fR +\&\fB\-mno\-flush\-trap \-mflush\-trap=\fR\fInumber\fR +\&\fB\-G\fR \fInum\fR +.Sp +\&\fIM32C Options\fR +\&\fB\-mcpu=\fR\fIcpu\fR \fB\-msim \-memregs=\fR\fInumber\fR +.Sp +\&\fIM680x0 Options\fR +\&\fB\-march=\fR\fIarch\fR \fB\-mcpu=\fR\fIcpu\fR \fB\-mtune=\fR\fItune\fR +\&\fB\-m68000 \-m68020 \-m68020\-40 \-m68020\-60 \-m68030 \-m68040 +\&\-m68060 \-mcpu32 \-m5200 \-m5206e \-m528x \-m5307 \-m5407 +\&\-mcfv4e \-mbitfield \-mno\-bitfield \-mc68000 \-mc68020 +\&\-mnobitfield \-mrtd \-mno\-rtd \-mdiv \-mno\-div \-mshort +\&\-mno\-short \-mhard\-float \-m68881 \-msoft\-float \-mpcrel +\&\-malign\-int \-mstrict\-align \-msep\-data \-mno\-sep\-data +\&\-mshared\-library\-id=n \-mid\-shared\-library \-mno\-id\-shared\-library +\&\-mxgot \-mno\-xgot\fR +.Sp +\&\fIM68hc1x Options\fR +\&\fB\-m6811 \-m6812 \-m68hc11 \-m68hc12 \-m68hcs12 +\&\-mauto\-incdec \-minmax \-mlong\-calls \-mshort +\&\-msoft\-reg\-count=\fR\fIcount\fR +.Sp +\&\fIMCore Options\fR +\&\fB\-mhardlit \-mno\-hardlit \-mdiv \-mno\-div \-mrelax\-immediates +\&\-mno\-relax\-immediates \-mwide\-bitfields \-mno\-wide\-bitfields +\&\-m4byte\-functions \-mno\-4byte\-functions \-mcallgraph\-data +\&\-mno\-callgraph\-data \-mslow\-bytes \-mno\-slow\-bytes \-mno\-lsim +\&\-mlittle\-endian \-mbig\-endian \-m210 \-m340 \-mstack\-increment\fR +.Sp +\&\fIMeP Options\fR +\&\fB\-mabsdiff \-mall\-opts \-maverage \-mbased=\fR\fIn\fR \fB\-mbitops +\&\-mc=\fR\fIn\fR \fB\-mclip \-mconfig=\fR\fIname\fR \fB\-mcop \-mcop32 \-mcop64 \-mivc2 +\&\-mdc \-mdiv \-meb \-mel \-mio\-volatile \-ml \-mleadz \-mm \-mminmax +\&\-mmult \-mno\-opts \-mrepeat \-ms \-msatur \-msdram \-msim \-msimnovec \-mtf +\&\-mtiny=\fR\fIn\fR +.Sp +\&\fIMicroBlaze Options\fR +\&\fB\-msoft\-float \-mhard\-float \-msmall\-divides \-mcpu=\fR\fIcpu\fR +\&\fB\-mmemcpy \-mxl\-soft\-mul \-mxl\-soft\-div \-mxl\-barrel\-shift +\&\-mxl\-pattern\-compare \-mxl\-stack\-check \-mxl\-gp\-opt \-mno\-clearbss +\&\-mxl\-multiply\-high \-mxl\-float\-convert \-mxl\-float\-sqrt +\&\-mxl\-mode\-\fR\fIapp-model\fR +.Sp +\&\fI\s-1MIPS\s0 Options\fR +\&\fB\-EL \-EB \-march=\fR\fIarch\fR \fB\-mtune=\fR\fIarch\fR +\&\fB\-mips1 \-mips2 \-mips3 \-mips4 \-mips32 \-mips32r2 +\&\-mips64 \-mips64r2 +\&\-mips16 \-mno\-mips16 \-mflip\-mips16 +\&\-minterlink\-mips16 \-mno\-interlink\-mips16 +\&\-mabi=\fR\fIabi\fR \fB\-mabicalls \-mno\-abicalls +\&\-mshared \-mno\-shared \-mplt \-mno\-plt \-mxgot \-mno\-xgot +\&\-mgp32 \-mgp64 \-mfp32 \-mfp64 \-mhard\-float \-msoft\-float +\&\-msingle\-float \-mdouble\-float \-mdsp \-mno\-dsp \-mdspr2 \-mno\-dspr2 +\&\-mfpu=\fR\fIfpu-type\fR +\&\fB\-msmartmips \-mno\-smartmips +\&\-mpaired\-single \-mno\-paired\-single \-mdmx \-mno\-mdmx +\&\-mips3d \-mno\-mips3d \-mmt \-mno\-mt \-mllsc \-mno\-llsc +\&\-mlong64 \-mlong32 \-msym32 \-mno\-sym32 +\&\-G\fR\fInum\fR \fB\-mlocal\-sdata \-mno\-local\-sdata +\&\-mextern\-sdata \-mno\-extern\-sdata \-mgpopt \-mno\-gopt +\&\-membedded\-data \-mno\-embedded\-data +\&\-muninit\-const\-in\-rodata \-mno\-uninit\-const\-in\-rodata +\&\-mcode\-readable=\fR\fIsetting\fR +\&\fB\-msplit\-addresses \-mno\-split\-addresses +\&\-mexplicit\-relocs \-mno\-explicit\-relocs +\&\-mcheck\-zero\-division \-mno\-check\-zero\-division +\&\-mdivide\-traps \-mdivide\-breaks +\&\-mmemcpy \-mno\-memcpy \-mlong\-calls \-mno\-long\-calls +\&\-mmad \-mno\-mad \-mfused\-madd \-mno\-fused\-madd \-nocpp +\&\-mfix\-r4000 \-mno\-fix\-r4000 \-mfix\-r4400 \-mno\-fix\-r4400 +\&\-mfix\-r10000 \-mno\-fix\-r10000 \-mfix\-vr4120 \-mno\-fix\-vr4120 +\&\-mfix\-vr4130 \-mno\-fix\-vr4130 \-mfix\-sb1 \-mno\-fix\-sb1 +\&\-mflush\-func=\fR\fIfunc\fR \fB\-mno\-flush\-func +\&\-mbranch\-cost=\fR\fInum\fR \fB\-mbranch\-likely \-mno\-branch\-likely +\&\-mfp\-exceptions \-mno\-fp\-exceptions +\&\-mvr4130\-align \-mno\-vr4130\-align \-msynci \-mno\-synci +\&\-mrelax\-pic\-calls \-mno\-relax\-pic\-calls \-mmcount\-ra\-address\fR +.Sp +\&\fI\s-1MMIX\s0 Options\fR +\&\fB\-mlibfuncs \-mno\-libfuncs \-mepsilon \-mno\-epsilon \-mabi=gnu +\&\-mabi=mmixware \-mzero\-extend \-mknuthdiv \-mtoplevel\-symbols +\&\-melf \-mbranch\-predict \-mno\-branch\-predict \-mbase\-addresses +\&\-mno\-base\-addresses \-msingle\-exit \-mno\-single\-exit\fR +.Sp +\&\fI\s-1MN10300\s0 Options\fR +\&\fB\-mmult\-bug \-mno\-mult\-bug +\&\-mno\-am33 \-mam33 \-mam33\-2 \-mam34 +\&\-mtune=\fR\fIcpu-type\fR +\&\fB\-mreturn\-pointer\-on\-d0 +\&\-mno\-crt0 \-mrelax \-mliw\fR +.Sp +\&\fI\s-1PDP\-11\s0 Options\fR +\&\fB\-mfpu \-msoft\-float \-mac0 \-mno\-ac0 \-m40 \-m45 \-m10 +\&\-mbcopy \-mbcopy\-builtin \-mint32 \-mno\-int16 +\&\-mint16 \-mno\-int32 \-mfloat32 \-mno\-float64 +\&\-mfloat64 \-mno\-float32 \-mabshi \-mno\-abshi +\&\-mbranch\-expensive \-mbranch\-cheap +\&\-munix\-asm \-mdec\-asm\fR +.Sp +\&\fIpicoChip Options\fR +\&\fB\-mae=\fR\fIae_type\fR \fB\-mvliw\-lookahead=\fR\fIN\fR +\&\fB\-msymbol\-as\-address \-mno\-inefficient\-warnings\fR +.Sp +\&\fIPowerPC Options\fR +See \s-1RS/6000\s0 and PowerPC Options. +.Sp +\&\fI\s-1RS/6000\s0 and PowerPC Options\fR +\&\fB\-mcpu=\fR\fIcpu-type\fR +\&\fB\-mtune=\fR\fIcpu-type\fR +\&\fB\-mcmodel=\fR\fIcode-model\fR +\&\fB\-mpower \-mno\-power \-mpower2 \-mno\-power2 +\&\-mpowerpc \-mpowerpc64 \-mno\-powerpc +\&\-maltivec \-mno\-altivec +\&\-mpowerpc\-gpopt \-mno\-powerpc\-gpopt +\&\-mpowerpc\-gfxopt \-mno\-powerpc\-gfxopt +\&\-mmfcrf \-mno\-mfcrf \-mpopcntb \-mno\-popcntb \-mpopcntd \-mno\-popcntd +\&\-mfprnd \-mno\-fprnd +\&\-mcmpb \-mno\-cmpb \-mmfpgpr \-mno\-mfpgpr \-mhard\-dfp \-mno\-hard\-dfp +\&\-mnew\-mnemonics \-mold\-mnemonics +\&\-mfull\-toc \-mminimal\-toc \-mno\-fp\-in\-toc \-mno\-sum\-in\-toc +\&\-m64 \-m32 \-mxl\-compat \-mno\-xl\-compat \-mpe +\&\-malign\-power \-malign\-natural +\&\-msoft\-float \-mhard\-float \-mmultiple \-mno\-multiple +\&\-msingle\-float \-mdouble\-float \-msimple\-fpu +\&\-mstring \-mno\-string \-mupdate \-mno\-update +\&\-mavoid\-indexed\-addresses \-mno\-avoid\-indexed\-addresses +\&\-mfused\-madd \-mno\-fused\-madd \-mbit\-align \-mno\-bit\-align +\&\-mstrict\-align \-mno\-strict\-align \-mrelocatable +\&\-mno\-relocatable \-mrelocatable\-lib \-mno\-relocatable\-lib +\&\-mtoc \-mno\-toc \-mlittle \-mlittle\-endian \-mbig \-mbig\-endian +\&\-mdynamic\-no\-pic \-maltivec \-mswdiv \-msingle\-pic\-base +\&\-mprioritize\-restricted\-insns=\fR\fIpriority\fR +\&\fB\-msched\-costly\-dep=\fR\fIdependence_type\fR +\&\fB\-minsert\-sched\-nops=\fR\fIscheme\fR +\&\fB\-mcall\-sysv \-mcall\-netbsd +\&\-maix\-struct\-return \-msvr4\-struct\-return +\&\-mabi=\fR\fIabi-type\fR \fB\-msecure\-plt \-mbss\-plt +\&\-mblock\-move\-inline\-limit=\fR\fInum\fR +\&\fB\-misel \-mno\-isel +\&\-misel=yes \-misel=no +\&\-mspe \-mno\-spe +\&\-mspe=yes \-mspe=no +\&\-mpaired +\&\-mgen\-cell\-microcode \-mwarn\-cell\-microcode +\&\-mvrsave \-mno\-vrsave +\&\-mmulhw \-mno\-mulhw +\&\-mdlmzb \-mno\-dlmzb +\&\-mfloat\-gprs=yes \-mfloat\-gprs=no \-mfloat\-gprs=single \-mfloat\-gprs=double +\&\-mprototype \-mno\-prototype +\&\-msim \-mmvme \-mads \-myellowknife \-memb \-msdata +\&\-msdata=\fR\fIopt\fR \fB\-mvxworks \-G\fR \fInum\fR \fB\-pthread +\&\-mrecip \-mrecip=\fR\fIopt\fR \fB\-mno\-recip \-mrecip\-precision +\&\-mno\-recip\-precision +\&\-mveclibabi=\fR\fItype\fR \fB\-mfriz \-mno\-friz\fR +.Sp +\&\fI\s-1RX\s0 Options\fR +\&\fB\-m64bit\-doubles \-m32bit\-doubles \-fpu \-nofpu +\&\-mcpu= +\&\-mbig\-endian\-data \-mlittle\-endian\-data +\&\-msmall\-data +\&\-msim \-mno\-sim +\&\-mas100\-syntax \-mno\-as100\-syntax +\&\-mrelax +\&\-mmax\-constant\-size= +\&\-mint\-register= +\&\-msave\-acc\-in\-interrupts\fR +.Sp +\&\fIS/390 and zSeries Options\fR +\&\fB\-mtune=\fR\fIcpu-type\fR \fB\-march=\fR\fIcpu-type\fR +\&\fB\-mhard\-float \-msoft\-float \-mhard\-dfp \-mno\-hard\-dfp +\&\-mlong\-double\-64 \-mlong\-double\-128 +\&\-mbackchain \-mno\-backchain \-mpacked\-stack \-mno\-packed\-stack +\&\-msmall\-exec \-mno\-small\-exec \-mmvcle \-mno\-mvcle +\&\-m64 \-m31 \-mdebug \-mno\-debug \-mesa \-mzarch +\&\-mtpf\-trace \-mno\-tpf\-trace \-mfused\-madd \-mno\-fused\-madd +\&\-mwarn\-framesize \-mwarn\-dynamicstack \-mstack\-size \-mstack\-guard\fR +.Sp +\&\fIScore Options\fR +\&\fB\-meb \-mel +\&\-mnhwloop +\&\-muls +\&\-mmac +\&\-mscore5 \-mscore5u \-mscore7 \-mscore7d\fR +.Sp +\&\fI\s-1SH\s0 Options\fR +\&\fB\-m1 \-m2 \-m2e +\&\-m2a\-nofpu \-m2a\-single\-only \-m2a\-single \-m2a +\&\-m3 \-m3e +\&\-m4\-nofpu \-m4\-single\-only \-m4\-single \-m4 +\&\-m4a\-nofpu \-m4a\-single\-only \-m4a\-single \-m4a \-m4al +\&\-m5\-64media \-m5\-64media\-nofpu +\&\-m5\-32media \-m5\-32media\-nofpu +\&\-m5\-compact \-m5\-compact\-nofpu +\&\-mb \-ml \-mdalign \-mrelax +\&\-mbigtable \-mfmovd \-mhitachi \-mrenesas \-mno\-renesas \-mnomacsave +\&\-mieee \-mbitops \-misize \-minline\-ic_invalidate \-mpadstruct \-mspace +\&\-mprefergot \-musermode \-multcost=\fR\fInumber\fR \fB\-mdiv=\fR\fIstrategy\fR +\&\fB\-mdivsi3_libfunc=\fR\fIname\fR \fB\-mfixed\-range=\fR\fIregister-range\fR +\&\fB\-madjust\-unroll \-mindexed\-addressing \-mgettrcost=\fR\fInumber\fR \fB\-mpt\-fixed +\&\-maccumulate\-outgoing\-args \-minvalid\-symbols\fR +.Sp +\&\fISolaris 2 Options\fR +\&\fB\-mimpure\-text \-mno\-impure\-text +\&\-threads \-pthreads \-pthread\fR +.Sp +\&\fI\s-1SPARC\s0 Options\fR +\&\fB\-mcpu=\fR\fIcpu-type\fR +\&\fB\-mtune=\fR\fIcpu-type\fR +\&\fB\-mcmodel=\fR\fIcode-model\fR +\&\fB\-m32 \-m64 \-mapp\-regs \-mno\-app\-regs +\&\-mfaster\-structs \-mno\-faster\-structs +\&\-mfpu \-mno\-fpu \-mhard\-float \-msoft\-float +\&\-mhard\-quad\-float \-msoft\-quad\-float +\&\-mlittle\-endian +\&\-mstack\-bias \-mno\-stack\-bias +\&\-munaligned\-doubles \-mno\-unaligned\-doubles +\&\-mv8plus \-mno\-v8plus \-mvis \-mno\-vis +\&\-mfix\-at697f\fR +.Sp +\&\fI\s-1SPU\s0 Options\fR +\&\fB\-mwarn\-reloc \-merror\-reloc +\&\-msafe\-dma \-munsafe\-dma +\&\-mbranch\-hints +\&\-msmall\-mem \-mlarge\-mem \-mstdmain +\&\-mfixed\-range=\fR\fIregister-range\fR +\&\fB\-mea32 \-mea64 +\&\-maddress\-space\-conversion \-mno\-address\-space\-conversion +\&\-mcache\-size=\fR\fIcache-size\fR +\&\fB\-matomic\-updates \-mno\-atomic\-updates\fR +.Sp +\&\fISystem V Options\fR +\&\fB\-Qy \-Qn \-YP,\fR\fIpaths\fR \fB\-Ym,\fR\fIdir\fR +.Sp +\&\fIV850 Options\fR +\&\fB\-mlong\-calls \-mno\-long\-calls \-mep \-mno\-ep +\&\-mprolog\-function \-mno\-prolog\-function \-mspace +\&\-mtda=\fR\fIn\fR \fB\-msda=\fR\fIn\fR \fB\-mzda=\fR\fIn\fR +\&\fB\-mapp\-regs \-mno\-app\-regs +\&\-mdisable\-callt \-mno\-disable\-callt +\&\-mv850e2v3 +\&\-mv850e2 +\&\-mv850e1 \-mv850es +\&\-mv850e +\&\-mv850 \-mbig\-switch\fR +.Sp +\&\fI\s-1VAX\s0 Options\fR +\&\fB\-mg \-mgnu \-munix\fR +.Sp +\&\fIVxWorks Options\fR +\&\fB\-mrtp \-non\-static \-Bstatic \-Bdynamic +\&\-Xbind\-lazy \-Xbind\-now\fR +.Sp +\&\fIx86\-64 Options\fR +See i386 and x86\-64 Options. +.Sp +\&\fIXstormy16 Options\fR +\&\fB\-msim\fR +.Sp +\&\fIXtensa Options\fR +\&\fB\-mconst16 \-mno\-const16 +\&\-mfused\-madd \-mno\-fused\-madd +\&\-mforce\-no\-pic +\&\-mserialize\-volatile \-mno\-serialize\-volatile +\&\-mtext\-section\-literals \-mno\-text\-section\-literals +\&\-mtarget\-align \-mno\-target\-align +\&\-mlongcalls \-mno\-longcalls\fR +.Sp +\&\fIzSeries Options\fR +See S/390 and zSeries Options. +.IP "\fICode Generation Options\fR" 4 +.IX Item "Code Generation Options" +\&\fB\-fcall\-saved\-\fR\fIreg\fR \fB\-fcall\-used\-\fR\fIreg\fR +\&\fB\-ffixed\-\fR\fIreg\fR \fB\-fexceptions +\&\-fnon\-call\-exceptions \-funwind\-tables +\&\-fasynchronous\-unwind\-tables +\&\-finhibit\-size\-directive \-finstrument\-functions +\&\-finstrument\-functions\-exclude\-function\-list=\fR\fIsym\fR\fB,\fR\fIsym\fR\fB,... +\&\-finstrument\-functions\-exclude\-file\-list=\fR\fIfile\fR\fB,\fR\fIfile\fR\fB,... +\&\-fno\-common \-fno\-ident +\&\-fpcc\-struct\-return \-fpic \-fPIC \-fpie \-fPIE +\&\-fno\-jump\-tables +\&\-frecord\-gcc\-switches +\&\-freg\-struct\-return \-fshort\-enums +\&\-fshort\-double \-fshort\-wchar +\&\-fverbose\-asm \-fpack\-struct[=\fR\fIn\fR\fB] \-fstack\-check +\&\-fstack\-limit\-register=\fR\fIreg\fR \fB\-fstack\-limit\-symbol=\fR\fIsym\fR +\&\fB\-fno\-stack\-limit \-fsplit\-stack +\&\-fleading\-underscore \-ftls\-model=\fR\fImodel\fR +\&\fB\-ftrapv \-fwrapv \-fbounds\-check +\&\-fvisibility \-fstrict\-volatile\-bitfields\fR +.SS "Options Controlling the Kind of Output" +.IX Subsection "Options Controlling the Kind of Output" +Compilation can involve up to four stages: preprocessing, compilation +proper, assembly and linking, always in that order. \s-1GCC\s0 is capable of +preprocessing and compiling several files either into several +assembler input files, or into one assembler input file; then each +assembler input file produces an object file, and linking combines all +the object files (those newly compiled, and those specified as input) +into an executable file. +.PP +For any given input file, the file name suffix determines what kind of +compilation is done: +.IP "\fIfile\fR\fB.c\fR" 4 +.IX Item "file.c" +C source code which must be preprocessed. +.IP "\fIfile\fR\fB.i\fR" 4 +.IX Item "file.i" +C source code which should not be preprocessed. +.IP "\fIfile\fR\fB.ii\fR" 4 +.IX Item "file.ii" +\&\*(C+ source code which should not be preprocessed. +.IP "\fIfile\fR\fB.m\fR" 4 +.IX Item "file.m" +Objective-C source code. Note that you must link with the \fIlibobjc\fR +library to make an Objective-C program work. +.IP "\fIfile\fR\fB.mi\fR" 4 +.IX Item "file.mi" +Objective-C source code which should not be preprocessed. +.IP "\fIfile\fR\fB.mm\fR" 4 +.IX Item "file.mm" +.PD 0 +.IP "\fIfile\fR\fB.M\fR" 4 +.IX Item "file.M" +.PD +Objective\-\*(C+ source code. Note that you must link with the \fIlibobjc\fR +library to make an Objective\-\*(C+ program work. Note that \fB.M\fR refers +to a literal capital M. +.IP "\fIfile\fR\fB.mii\fR" 4 +.IX Item "file.mii" +Objective\-\*(C+ source code which should not be preprocessed. +.IP "\fIfile\fR\fB.h\fR" 4 +.IX Item "file.h" +C, \*(C+, Objective-C or Objective\-\*(C+ header file to be turned into a +precompiled header (default), or C, \*(C+ header file to be turned into an +Ada spec (via the \fB\-fdump\-ada\-spec\fR switch). +.IP "\fIfile\fR\fB.cc\fR" 4 +.IX Item "file.cc" +.PD 0 +.IP "\fIfile\fR\fB.cp\fR" 4 +.IX Item "file.cp" +.IP "\fIfile\fR\fB.cxx\fR" 4 +.IX Item "file.cxx" +.IP "\fIfile\fR\fB.cpp\fR" 4 +.IX Item "file.cpp" +.IP "\fIfile\fR\fB.CPP\fR" 4 +.IX Item "file.CPP" +.IP "\fIfile\fR\fB.c++\fR" 4 +.IX Item "file.c++" +.IP "\fIfile\fR\fB.C\fR" 4 +.IX Item "file.C" +.PD +\&\*(C+ source code which must be preprocessed. Note that in \fB.cxx\fR, +the last two letters must both be literally \fBx\fR. Likewise, +\&\fB.C\fR refers to a literal capital C. +.IP "\fIfile\fR\fB.mm\fR" 4 +.IX Item "file.mm" +.PD 0 +.IP "\fIfile\fR\fB.M\fR" 4 +.IX Item "file.M" +.PD +Objective\-\*(C+ source code which must be preprocessed. +.IP "\fIfile\fR\fB.mii\fR" 4 +.IX Item "file.mii" +Objective\-\*(C+ source code which should not be preprocessed. +.IP "\fIfile\fR\fB.hh\fR" 4 +.IX Item "file.hh" +.PD 0 +.IP "\fIfile\fR\fB.H\fR" 4 +.IX Item "file.H" +.IP "\fIfile\fR\fB.hp\fR" 4 +.IX Item "file.hp" +.IP "\fIfile\fR\fB.hxx\fR" 4 +.IX Item "file.hxx" +.IP "\fIfile\fR\fB.hpp\fR" 4 +.IX Item "file.hpp" +.IP "\fIfile\fR\fB.HPP\fR" 4 +.IX Item "file.HPP" +.IP "\fIfile\fR\fB.h++\fR" 4 +.IX Item "file.h++" +.IP "\fIfile\fR\fB.tcc\fR" 4 +.IX Item "file.tcc" +.PD +\&\*(C+ header file to be turned into a precompiled header or Ada spec. +.IP "\fIfile\fR\fB.f\fR" 4 +.IX Item "file.f" +.PD 0 +.IP "\fIfile\fR\fB.for\fR" 4 +.IX Item "file.for" +.IP "\fIfile\fR\fB.ftn\fR" 4 +.IX Item "file.ftn" +.PD +Fixed form Fortran source code which should not be preprocessed. +.IP "\fIfile\fR\fB.F\fR" 4 +.IX Item "file.F" +.PD 0 +.IP "\fIfile\fR\fB.FOR\fR" 4 +.IX Item "file.FOR" +.IP "\fIfile\fR\fB.fpp\fR" 4 +.IX Item "file.fpp" +.IP "\fIfile\fR\fB.FPP\fR" 4 +.IX Item "file.FPP" +.IP "\fIfile\fR\fB.FTN\fR" 4 +.IX Item "file.FTN" +.PD +Fixed form Fortran source code which must be preprocessed (with the traditional +preprocessor). +.IP "\fIfile\fR\fB.f90\fR" 4 +.IX Item "file.f90" +.PD 0 +.IP "\fIfile\fR\fB.f95\fR" 4 +.IX Item "file.f95" +.IP "\fIfile\fR\fB.f03\fR" 4 +.IX Item "file.f03" +.IP "\fIfile\fR\fB.f08\fR" 4 +.IX Item "file.f08" +.PD +Free form Fortran source code which should not be preprocessed. +.IP "\fIfile\fR\fB.F90\fR" 4 +.IX Item "file.F90" +.PD 0 +.IP "\fIfile\fR\fB.F95\fR" 4 +.IX Item "file.F95" +.IP "\fIfile\fR\fB.F03\fR" 4 +.IX Item "file.F03" +.IP "\fIfile\fR\fB.F08\fR" 4 +.IX Item "file.F08" +.PD +Free form Fortran source code which must be preprocessed (with the +traditional preprocessor). +.IP "\fIfile\fR\fB.go\fR" 4 +.IX Item "file.go" +Go source code. +.IP "\fIfile\fR\fB.ads\fR" 4 +.IX Item "file.ads" +Ada source code file which contains a library unit declaration (a +declaration of a package, subprogram, or generic, or a generic +instantiation), or a library unit renaming declaration (a package, +generic, or subprogram renaming declaration). Such files are also +called \fIspecs\fR. +.IP "\fIfile\fR\fB.adb\fR" 4 +.IX Item "file.adb" +Ada source code file containing a library unit body (a subprogram or +package body). Such files are also called \fIbodies\fR. +.IP "\fIfile\fR\fB.s\fR" 4 +.IX Item "file.s" +Assembler code. +.IP "\fIfile\fR\fB.S\fR" 4 +.IX Item "file.S" +.PD 0 +.IP "\fIfile\fR\fB.sx\fR" 4 +.IX Item "file.sx" +.PD +Assembler code which must be preprocessed. +.IP "\fIother\fR" 4 +.IX Item "other" +An object file to be fed straight into linking. +Any file name with no recognized suffix is treated this way. +.PP +You can specify the input language explicitly with the \fB\-x\fR option: +.IP "\fB\-x\fR \fIlanguage\fR" 4 +.IX Item "-x language" +Specify explicitly the \fIlanguage\fR for the following input files +(rather than letting the compiler choose a default based on the file +name suffix). This option applies to all following input files until +the next \fB\-x\fR option. Possible values for \fIlanguage\fR are: +.Sp +.Vb 9 +\& c c\-header cpp\-output +\& c++ c++\-header c++\-cpp\-output +\& objective\-c objective\-c\-header objective\-c\-cpp\-output +\& objective\-c++ objective\-c++\-header objective\-c++\-cpp\-output +\& assembler assembler\-with\-cpp +\& ada +\& f77 f77\-cpp\-input f95 f95\-cpp\-input +\& go +\& java +.Ve +.IP "\fB\-x none\fR" 4 +.IX Item "-x none" +Turn off any specification of a language, so that subsequent files are +handled according to their file name suffixes (as they are if \fB\-x\fR +has not been used at all). +.IP "\fB\-pass\-exit\-codes\fR" 4 +.IX Item "-pass-exit-codes" +Normally the \fBgcc\fR program will exit with the code of 1 if any +phase of the compiler returns a non-success return code. If you specify +\&\fB\-pass\-exit\-codes\fR, the \fBgcc\fR program will instead return with +numerically highest error produced by any phase that returned an error +indication. The C, \*(C+, and Fortran frontends return 4, if an internal +compiler error is encountered. +.PP +If you only want some of the stages of compilation, you can use +\&\fB\-x\fR (or filename suffixes) to tell \fBgcc\fR where to start, and +one of the options \fB\-c\fR, \fB\-S\fR, or \fB\-E\fR to say where +\&\fBgcc\fR is to stop. Note that some combinations (for example, +\&\fB\-x cpp-output \-E\fR) instruct \fBgcc\fR to do nothing at all. +.IP "\fB\-c\fR" 4 +.IX Item "-c" +Compile or assemble the source files, but do not link. The linking +stage simply is not done. The ultimate output is in the form of an +object file for each source file. +.Sp +By default, the object file name for a source file is made by replacing +the suffix \fB.c\fR, \fB.i\fR, \fB.s\fR, etc., with \fB.o\fR. +.Sp +Unrecognized input files, not requiring compilation or assembly, are +ignored. +.IP "\fB\-S\fR" 4 +.IX Item "-S" +Stop after the stage of compilation proper; do not assemble. The output +is in the form of an assembler code file for each non-assembler input +file specified. +.Sp +By default, the assembler file name for a source file is made by +replacing the suffix \fB.c\fR, \fB.i\fR, etc., with \fB.s\fR. +.Sp +Input files that don't require compilation are ignored. +.IP "\fB\-E\fR" 4 +.IX Item "-E" +Stop after the preprocessing stage; do not run the compiler proper. The +output is in the form of preprocessed source code, which is sent to the +standard output. +.Sp +Input files which don't require preprocessing are ignored. +.IP "\fB\-o\fR \fIfile\fR" 4 +.IX Item "-o file" +Place output in file \fIfile\fR. This applies regardless to whatever +sort of output is being produced, whether it be an executable file, +an object file, an assembler file or preprocessed C code. +.Sp +If \fB\-o\fR is not specified, the default is to put an executable +file in \fIa.out\fR, the object file for +\&\fI\fIsource\fI.\fIsuffix\fI\fR in \fI\fIsource\fI.o\fR, its +assembler file in \fI\fIsource\fI.s\fR, a precompiled header file in +\&\fI\fIsource\fI.\fIsuffix\fI.gch\fR, and all preprocessed C source on +standard output. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +Print (on standard error output) the commands executed to run the stages +of compilation. Also print the version number of the compiler driver +program and of the preprocessor and the compiler proper. +.IP "\fB\-###\fR" 4 +.IX Item "-###" +Like \fB\-v\fR except the commands are not executed and arguments +are quoted unless they contain only alphanumeric characters or \f(CW\*(C`./\-_\*(C'\fR. +This is useful for shell scripts to capture the driver-generated command lines. +.IP "\fB\-pipe\fR" 4 +.IX Item "-pipe" +Use pipes rather than temporary files for communication between the +various stages of compilation. This fails to work on some systems where +the assembler is unable to read from a pipe; but the \s-1GNU\s0 assembler has +no trouble. +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +Print (on the standard output) a description of the command line options +understood by \fBgcc\fR. If the \fB\-v\fR option is also specified +then \fB\-\-help\fR will also be passed on to the various processes +invoked by \fBgcc\fR, so that they can display the command line options +they accept. If the \fB\-Wextra\fR option has also been specified +(prior to the \fB\-\-help\fR option), then command line options which +have no documentation associated with them will also be displayed. +.IP "\fB\-\-target\-help\fR" 4 +.IX Item "--target-help" +Print (on the standard output) a description of target-specific command +line options for each tool. For some targets extra target-specific +information may also be printed. +.IP "\fB\-\-help={\fR\fIclass\fR|[\fB^\fR]\fIqualifier\fR\fB}\fR[\fB,...\fR]" 4 +.IX Item "--help={class|[^]qualifier}[,...]" +Print (on the standard output) a description of the command line +options understood by the compiler that fit into all specified classes +and qualifiers. These are the supported classes: +.RS 4 +.IP "\fBoptimizers\fR" 4 +.IX Item "optimizers" +This will display all of the optimization options supported by the +compiler. +.IP "\fBwarnings\fR" 4 +.IX Item "warnings" +This will display all of the options controlling warning messages +produced by the compiler. +.IP "\fBtarget\fR" 4 +.IX Item "target" +This will display target-specific options. Unlike the +\&\fB\-\-target\-help\fR option however, target-specific options of the +linker and assembler will not be displayed. This is because those +tools do not currently support the extended \fB\-\-help=\fR syntax. +.IP "\fBparams\fR" 4 +.IX Item "params" +This will display the values recognized by the \fB\-\-param\fR +option. +.IP "\fIlanguage\fR" 4 +.IX Item "language" +This will display the options supported for \fIlanguage\fR, where +\&\fIlanguage\fR is the name of one of the languages supported in this +version of \s-1GCC\s0. +.IP "\fBcommon\fR" 4 +.IX Item "common" +This will display the options that are common to all languages. +.RE +.RS 4 +.Sp +These are the supported qualifiers: +.IP "\fBundocumented\fR" 4 +.IX Item "undocumented" +Display only those options which are undocumented. +.IP "\fBjoined\fR" 4 +.IX Item "joined" +Display options which take an argument that appears after an equal +sign in the same continuous piece of text, such as: +\&\fB\-\-help=target\fR. +.IP "\fBseparate\fR" 4 +.IX Item "separate" +Display options which take an argument that appears as a separate word +following the original option, such as: \fB\-o output-file\fR. +.RE +.RS 4 +.Sp +Thus for example to display all the undocumented target-specific +switches supported by the compiler the following can be used: +.Sp +.Vb 1 +\& \-\-help=target,undocumented +.Ve +.Sp +The sense of a qualifier can be inverted by prefixing it with the +\&\fB^\fR character, so for example to display all binary warning +options (i.e., ones that are either on or off and that do not take an +argument), which have a description the following can be used: +.Sp +.Vb 1 +\& \-\-help=warnings,^joined,^undocumented +.Ve +.Sp +The argument to \fB\-\-help=\fR should not consist solely of inverted +qualifiers. +.Sp +Combining several classes is possible, although this usually +restricts the output by so much that there is nothing to display. One +case where it does work however is when one of the classes is +\&\fItarget\fR. So for example to display all the target-specific +optimization options the following can be used: +.Sp +.Vb 1 +\& \-\-help=target,optimizers +.Ve +.Sp +The \fB\-\-help=\fR option can be repeated on the command line. Each +successive use will display its requested class of options, skipping +those that have already been displayed. +.Sp +If the \fB\-Q\fR option appears on the command line before the +\&\fB\-\-help=\fR option, then the descriptive text displayed by +\&\fB\-\-help=\fR is changed. Instead of describing the displayed +options, an indication is given as to whether the option is enabled, +disabled or set to a specific value (assuming that the compiler +knows this at the point where the \fB\-\-help=\fR option is used). +.Sp +Here is a truncated example from the \s-1ARM\s0 port of \fBgcc\fR: +.Sp +.Vb 5 +\& % gcc \-Q \-mabi=2 \-\-help=target \-c +\& The following options are target specific: +\& \-mabi= 2 +\& \-mabort\-on\-noreturn [disabled] +\& \-mapcs [disabled] +.Ve +.Sp +The output is sensitive to the effects of previous command line +options, so for example it is possible to find out which optimizations +are enabled at \fB\-O2\fR by using: +.Sp +.Vb 1 +\& \-Q \-O2 \-\-help=optimizers +.Ve +.Sp +Alternatively you can discover which binary optimizations are enabled +by \fB\-O3\fR by using: +.Sp +.Vb 3 +\& gcc \-c \-Q \-O3 \-\-help=optimizers > /tmp/O3\-opts +\& gcc \-c \-Q \-O2 \-\-help=optimizers > /tmp/O2\-opts +\& diff /tmp/O2\-opts /tmp/O3\-opts | grep enabled +.Ve +.RE +.IP "\fB\-canonical\-prefixes\fR" 4 +.IX Item "-canonical-prefixes" +Always expand any symbolic links, resolve references to \fB/../\fR +or \fB/./\fR, and make the path absolute when generating a relative +prefix. +.IP "\fB\-no\-canonical\-prefixes\fR" 4 +.IX Item "-no-canonical-prefixes" +Never expand any symbolic links, resolve references to \fB/../\fR +or \fB/./\fR, or make the path absolute when generating a relative +prefix. If neither \fB\-canonical\-prefixes\fR nor +\&\fB\-nocanonical\-prefixes\fR is given, \s-1GCC\s0 tries to set an appropriate +default by looking for a target-specific subdirectory alongside the +directory containing the compiler driver. +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +Display the version number and copyrights of the invoked \s-1GCC\s0. +.IP "\fB\-wrapper\fR" 4 +.IX Item "-wrapper" +Invoke all subcommands under a wrapper program. The name of the +wrapper program and its parameters are passed as a comma separated +list. +.Sp +.Vb 1 +\& gcc \-c t.c \-wrapper gdb,\-\-args +.Ve +.Sp +This will invoke all subprograms of \fBgcc\fR under +\&\fBgdb \-\-args\fR, thus the invocation of \fBcc1\fR will be +\&\fBgdb \-\-args cc1 ...\fR. +.IP "\fB\-fplugin=\fR\fIname\fR\fB.so\fR" 4 +.IX Item "-fplugin=name.so" +Load the plugin code in file \fIname\fR.so, assumed to be a +shared object to be dlopen'd by the compiler. The base name of +the shared object file is used to identify the plugin for the +purposes of argument parsing (See +\&\fB\-fplugin\-arg\-\fR\fIname\fR\fB\-\fR\fIkey\fR\fB=\fR\fIvalue\fR below). +Each plugin should define the callback functions specified in the +Plugins \s-1API\s0. +.IP "\fB\-fplugin\-arg\-\fR\fIname\fR\fB\-\fR\fIkey\fR\fB=\fR\fIvalue\fR" 4 +.IX Item "-fplugin-arg-name-key=value" +Define an argument called \fIkey\fR with a value of \fIvalue\fR +for the plugin called \fIname\fR. +.IP "\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR]" 4 +.IX Item "-fdump-ada-spec[-slim]" +For C and \*(C+ source and include files, generate corresponding Ada +specs. +.IP "\fB\-fdump\-go\-spec=\fR\fIfile\fR" 4 +.IX Item "-fdump-go-spec=file" +For input files in any language, generate corresponding Go +declarations in \fIfile\fR. This generates Go \f(CW\*(C`const\*(C'\fR, +\&\f(CW\*(C`type\*(C'\fR, \f(CW\*(C`var\*(C'\fR, and \f(CW\*(C`func\*(C'\fR declarations which may be a +useful way to start writing a Go interface to code written in some +other language. +.IP "\fB@\fR\fIfile\fR" 4 +.IX Item "@file" +Read command-line options from \fIfile\fR. The options read are +inserted in place of the original @\fIfile\fR option. If \fIfile\fR +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +.Sp +Options in \fIfile\fR are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The \fIfile\fR may itself contain additional +@\fIfile\fR options; any such options will be processed recursively. +.SS "Compiling \*(C+ Programs" +.IX Subsection "Compiling Programs" +\&\*(C+ source files conventionally use one of the suffixes \fB.C\fR, +\&\fB.cc\fR, \fB.cpp\fR, \fB.CPP\fR, \fB.c++\fR, \fB.cp\fR, or +\&\fB.cxx\fR; \*(C+ header files often use \fB.hh\fR, \fB.hpp\fR, +\&\fB.H\fR, or (for shared template code) \fB.tcc\fR; and +preprocessed \*(C+ files use the suffix \fB.ii\fR. \s-1GCC\s0 recognizes +files with these names and compiles them as \*(C+ programs even if you +call the compiler the same way as for compiling C programs (usually +with the name \fBgcc\fR). +.PP +However, the use of \fBgcc\fR does not add the \*(C+ library. +\&\fBg++\fR is a program that calls \s-1GCC\s0 and treats \fB.c\fR, +\&\fB.h\fR and \fB.i\fR files as \*(C+ source files instead of C source +files unless \fB\-x\fR is used, and automatically specifies linking +against the \*(C+ library. This program is also useful when +precompiling a C header file with a \fB.h\fR extension for use in \*(C+ +compilations. On many systems, \fBg++\fR is also installed with +the name \fBc++\fR. +.PP +When you compile \*(C+ programs, you may specify many of the same +command-line options that you use for compiling programs in any +language; or command-line options meaningful for C and related +languages; or options that are meaningful only for \*(C+ programs. +.SS "Options Controlling C Dialect" +.IX Subsection "Options Controlling C Dialect" +The following options control the dialect of C (or languages derived +from C, such as \*(C+, Objective-C and Objective\-\*(C+) that the compiler +accepts: +.IP "\fB\-ansi\fR" 4 +.IX Item "-ansi" +In C mode, this is equivalent to \fB\-std=c90\fR. In \*(C+ mode, it is +equivalent to \fB\-std=c++98\fR. +.Sp +This turns off certain features of \s-1GCC\s0 that are incompatible with \s-1ISO\s0 +C90 (when compiling C code), or of standard \*(C+ (when compiling \*(C+ code), +such as the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR keywords, and +predefined macros such as \f(CW\*(C`unix\*(C'\fR and \f(CW\*(C`vax\*(C'\fR that identify the +type of system you are using. It also enables the undesirable and +rarely used \s-1ISO\s0 trigraph feature. For the C compiler, +it disables recognition of \*(C+ style \fB//\fR comments as well as +the \f(CW\*(C`inline\*(C'\fR keyword. +.Sp +The alternate keywords \f(CW\*(C`_\|_asm_\|_\*(C'\fR, \f(CW\*(C`_\|_extension_\|_\*(C'\fR, +\&\f(CW\*(C`_\|_inline_\|_\*(C'\fR and \f(CW\*(C`_\|_typeof_\|_\*(C'\fR continue to work despite +\&\fB\-ansi\fR. You would not want to use them in an \s-1ISO\s0 C program, of +course, but it is useful to put them in header files that might be included +in compilations done with \fB\-ansi\fR. Alternate predefined macros +such as \f(CW\*(C`_\|_unix_\|_\*(C'\fR and \f(CW\*(C`_\|_vax_\|_\*(C'\fR are also available, with or +without \fB\-ansi\fR. +.Sp +The \fB\-ansi\fR option does not cause non-ISO programs to be +rejected gratuitously. For that, \fB\-pedantic\fR is required in +addition to \fB\-ansi\fR. +.Sp +The macro \f(CW\*(C`_\|_STRICT_ANSI_\|_\*(C'\fR is predefined when the \fB\-ansi\fR +option is used. Some header files may notice this macro and refrain +from declaring certain functions or defining certain macros that the +\&\s-1ISO\s0 standard doesn't call for; this is to avoid interfering with any +programs that might use these names for other things. +.Sp +Functions that would normally be built in but do not have semantics +defined by \s-1ISO\s0 C (such as \f(CW\*(C`alloca\*(C'\fR and \f(CW\*(C`ffs\*(C'\fR) are not built-in +functions when \fB\-ansi\fR is used. +.IP "\fB\-std=\fR" 4 +.IX Item "-std=" +Determine the language standard. This option +is currently only supported when compiling C or \*(C+. +.Sp +The compiler can accept several base standards, such as \fBc90\fR or +\&\fBc++98\fR, and \s-1GNU\s0 dialects of those standards, such as +\&\fBgnu90\fR or \fBgnu++98\fR. By specifying a base standard, the +compiler will accept all programs following that standard and those +using \s-1GNU\s0 extensions that do not contradict it. For example, +\&\fB\-std=c90\fR turns off certain features of \s-1GCC\s0 that are +incompatible with \s-1ISO\s0 C90, such as the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR +keywords, but not other \s-1GNU\s0 extensions that do not have a meaning in +\&\s-1ISO\s0 C90, such as omitting the middle term of a \f(CW\*(C`?:\*(C'\fR +expression. On the other hand, by specifying a \s-1GNU\s0 dialect of a +standard, all features the compiler support are enabled, even when +those features change the meaning of the base standard and some +strict-conforming programs may be rejected. The particular standard +is used by \fB\-pedantic\fR to identify which features are \s-1GNU\s0 +extensions given that version of the standard. For example +\&\fB\-std=gnu90 \-pedantic\fR would warn about \*(C+ style \fB//\fR +comments, while \fB\-std=gnu99 \-pedantic\fR would not. +.Sp +A value for this option must be provided; possible values are +.RS 4 +.IP "\fBc90\fR" 4 +.IX Item "c90" +.PD 0 +.IP "\fBc89\fR" 4 +.IX Item "c89" +.IP "\fBiso9899:1990\fR" 4 +.IX Item "iso9899:1990" +.PD +Support all \s-1ISO\s0 C90 programs (certain \s-1GNU\s0 extensions that conflict +with \s-1ISO\s0 C90 are disabled). Same as \fB\-ansi\fR for C code. +.IP "\fBiso9899:199409\fR" 4 +.IX Item "iso9899:199409" +\&\s-1ISO\s0 C90 as modified in amendment 1. +.IP "\fBc99\fR" 4 +.IX Item "c99" +.PD 0 +.IP "\fBc9x\fR" 4 +.IX Item "c9x" +.IP "\fBiso9899:1999\fR" 4 +.IX Item "iso9899:1999" +.IP "\fBiso9899:199x\fR" 4 +.IX Item "iso9899:199x" +.PD +\&\s-1ISO\s0 C99. Note that this standard is not yet fully supported; see +<\fBhttp://gcc.gnu.org/gcc\-4.6/c99status.html\fR> for more information. The +names \fBc9x\fR and \fBiso9899:199x\fR are deprecated. +.IP "\fBc1x\fR" 4 +.IX Item "c1x" +\&\s-1ISO\s0 C1X, the draft of the next revision of the \s-1ISO\s0 C standard. +Support is limited and experimental and features enabled by this +option may be changed or removed if changed in or removed from the +standard draft. +.IP "\fBgnu90\fR" 4 +.IX Item "gnu90" +.PD 0 +.IP "\fBgnu89\fR" 4 +.IX Item "gnu89" +.PD +\&\s-1GNU\s0 dialect of \s-1ISO\s0 C90 (including some C99 features). This +is the default for C code. +.IP "\fBgnu99\fR" 4 +.IX Item "gnu99" +.PD 0 +.IP "\fBgnu9x\fR" 4 +.IX Item "gnu9x" +.PD +\&\s-1GNU\s0 dialect of \s-1ISO\s0 C99. When \s-1ISO\s0 C99 is fully implemented in \s-1GCC\s0, +this will become the default. The name \fBgnu9x\fR is deprecated. +.IP "\fBgnu1x\fR" 4 +.IX Item "gnu1x" +\&\s-1GNU\s0 dialect of \s-1ISO\s0 C1X. Support is limited and experimental and +features enabled by this option may be changed or removed if changed +in or removed from the standard draft. +.IP "\fBc++98\fR" 4 +.IX Item "c++98" +The 1998 \s-1ISO\s0 \*(C+ standard plus amendments. Same as \fB\-ansi\fR for +\&\*(C+ code. +.IP "\fBgnu++98\fR" 4 +.IX Item "gnu++98" +\&\s-1GNU\s0 dialect of \fB\-std=c++98\fR. This is the default for +\&\*(C+ code. +.IP "\fBc++0x\fR" 4 +.IX Item "c++0x" +The working draft of the upcoming \s-1ISO\s0 \*(C+0x standard. This option +enables experimental features that are likely to be included in +\&\*(C+0x. The working draft is constantly changing, and any feature that is +enabled by this flag may be removed from future versions of \s-1GCC\s0 if it is +not part of the \*(C+0x standard. +.IP "\fBgnu++0x\fR" 4 +.IX Item "gnu++0x" +\&\s-1GNU\s0 dialect of \fB\-std=c++0x\fR. This option enables +experimental features that may be removed in future versions of \s-1GCC\s0. +.RE +.RS 4 +.RE +.IP "\fB\-fgnu89\-inline\fR" 4 +.IX Item "-fgnu89-inline" +The option \fB\-fgnu89\-inline\fR tells \s-1GCC\s0 to use the traditional +\&\s-1GNU\s0 semantics for \f(CW\*(C`inline\*(C'\fR functions when in C99 mode. + This option +is accepted and ignored by \s-1GCC\s0 versions 4.1.3 up to but not including +4.3. In \s-1GCC\s0 versions 4.3 and later it changes the behavior of \s-1GCC\s0 in +C99 mode. Using this option is roughly equivalent to adding the +\&\f(CW\*(C`gnu_inline\*(C'\fR function attribute to all inline functions. +.Sp +The option \fB\-fno\-gnu89\-inline\fR explicitly tells \s-1GCC\s0 to use the +C99 semantics for \f(CW\*(C`inline\*(C'\fR when in C99 or gnu99 mode (i.e., it +specifies the default behavior). This option was first supported in +\&\s-1GCC\s0 4.3. This option is not supported in \fB\-std=c90\fR or +\&\fB\-std=gnu90\fR mode. +.Sp +The preprocessor macros \f(CW\*(C`_\|_GNUC_GNU_INLINE_\|_\*(C'\fR and +\&\f(CW\*(C`_\|_GNUC_STDC_INLINE_\|_\*(C'\fR may be used to check which semantics are +in effect for \f(CW\*(C`inline\*(C'\fR functions. +.IP "\fB\-aux\-info\fR \fIfilename\fR" 4 +.IX Item "-aux-info filename" +Output to the given filename prototyped declarations for all functions +declared and/or defined in a translation unit, including those in header +files. This option is silently ignored in any language other than C. +.Sp +Besides declarations, the file indicates, in comments, the origin of +each declaration (source file and line), whether the declaration was +implicit, prototyped or unprototyped (\fBI\fR, \fBN\fR for new or +\&\fBO\fR for old, respectively, in the first character after the line +number and the colon), and whether it came from a declaration or a +definition (\fBC\fR or \fBF\fR, respectively, in the following +character). In the case of function definitions, a K&R\-style list of +arguments followed by their declarations is also provided, inside +comments, after the declaration. +.IP "\fB\-fno\-asm\fR" 4 +.IX Item "-fno-asm" +Do not recognize \f(CW\*(C`asm\*(C'\fR, \f(CW\*(C`inline\*(C'\fR or \f(CW\*(C`typeof\*(C'\fR as a +keyword, so that code can use these words as identifiers. You can use +the keywords \f(CW\*(C`_\|_asm_\|_\*(C'\fR, \f(CW\*(C`_\|_inline_\|_\*(C'\fR and \f(CW\*(C`_\|_typeof_\|_\*(C'\fR +instead. \fB\-ansi\fR implies \fB\-fno\-asm\fR. +.Sp +In \*(C+, this switch only affects the \f(CW\*(C`typeof\*(C'\fR keyword, since +\&\f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`inline\*(C'\fR are standard keywords. You may want to +use the \fB\-fno\-gnu\-keywords\fR flag instead, which has the same +effect. In C99 mode (\fB\-std=c99\fR or \fB\-std=gnu99\fR), this +switch only affects the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR keywords, since +\&\f(CW\*(C`inline\*(C'\fR is a standard keyword in \s-1ISO\s0 C99. +.IP "\fB\-fno\-builtin\fR" 4 +.IX Item "-fno-builtin" +.PD 0 +.IP "\fB\-fno\-builtin\-\fR\fIfunction\fR" 4 +.IX Item "-fno-builtin-function" +.PD +Don't recognize built-in functions that do not begin with +\&\fB_\|_builtin_\fR as prefix. +.Sp +\&\s-1GCC\s0 normally generates special code to handle certain built-in functions +more efficiently; for instance, calls to \f(CW\*(C`alloca\*(C'\fR may become single +instructions that adjust the stack directly, and calls to \f(CW\*(C`memcpy\*(C'\fR +may become inline copy loops. The resulting code is often both smaller +and faster, but since the function calls no longer appear as such, you +cannot set a breakpoint on those calls, nor can you change the behavior +of the functions by linking with a different library. In addition, +when a function is recognized as a built-in function, \s-1GCC\s0 may use +information about that function to warn about problems with calls to +that function, or to generate more efficient code, even if the +resulting code still contains calls to that function. For example, +warnings are given with \fB\-Wformat\fR for bad calls to +\&\f(CW\*(C`printf\*(C'\fR, when \f(CW\*(C`printf\*(C'\fR is built in, and \f(CW\*(C`strlen\*(C'\fR is +known not to modify global memory. +.Sp +With the \fB\-fno\-builtin\-\fR\fIfunction\fR option +only the built-in function \fIfunction\fR is +disabled. \fIfunction\fR must not begin with \fB_\|_builtin_\fR. If a +function is named that is not built-in in this version of \s-1GCC\s0, this +option is ignored. There is no corresponding +\&\fB\-fbuiltin\-\fR\fIfunction\fR option; if you wish to enable +built-in functions selectively when using \fB\-fno\-builtin\fR or +\&\fB\-ffreestanding\fR, you may define macros such as: +.Sp +.Vb 2 +\& #define abs(n) _\|_builtin_abs ((n)) +\& #define strcpy(d, s) _\|_builtin_strcpy ((d), (s)) +.Ve +.IP "\fB\-fhosted\fR" 4 +.IX Item "-fhosted" +Assert that compilation takes place in a hosted environment. This implies +\&\fB\-fbuiltin\fR. A hosted environment is one in which the +entire standard library is available, and in which \f(CW\*(C`main\*(C'\fR has a return +type of \f(CW\*(C`int\*(C'\fR. Examples are nearly everything except a kernel. +This is equivalent to \fB\-fno\-freestanding\fR. +.IP "\fB\-ffreestanding\fR" 4 +.IX Item "-ffreestanding" +Assert that compilation takes place in a freestanding environment. This +implies \fB\-fno\-builtin\fR. A freestanding environment +is one in which the standard library may not exist, and program startup may +not necessarily be at \f(CW\*(C`main\*(C'\fR. The most obvious example is an \s-1OS\s0 kernel. +This is equivalent to \fB\-fno\-hosted\fR. +.IP "\fB\-fopenmp\fR" 4 +.IX Item "-fopenmp" +Enable handling of OpenMP directives \f(CW\*(C`#pragma omp\*(C'\fR in C/\*(C+ and +\&\f(CW\*(C`!$omp\*(C'\fR in Fortran. When \fB\-fopenmp\fR is specified, the +compiler generates parallel code according to the OpenMP Application +Program Interface v3.0 <\fBhttp://www.openmp.org/\fR>. This option +implies \fB\-pthread\fR, and thus is only supported on targets that +have support for \fB\-pthread\fR. +.IP "\fB\-fms\-extensions\fR" 4 +.IX Item "-fms-extensions" +Accept some non-standard constructs used in Microsoft header files. +.Sp +In \*(C+ code, this allows member names in structures to be similar +to previous types declarations. +.Sp +.Vb 4 +\& typedef int UOW; +\& struct ABC { +\& UOW UOW; +\& }; +.Ve +.Sp +Some cases of unnamed fields in structures and unions are only +accepted with this option. +.IP "\fB\-fplan9\-extensions\fR" 4 +.IX Item "-fplan9-extensions" +Accept some non-standard constructs used in Plan 9 code. +.Sp +This enables \fB\-fms\-extensions\fR, permits passing pointers to +structures with anonymous fields to functions which expect pointers to +elements of the type of the field, and permits referring to anonymous +fields declared using a typedef. This is only +supported for C, not \*(C+. +.IP "\fB\-trigraphs\fR" 4 +.IX Item "-trigraphs" +Support \s-1ISO\s0 C trigraphs. The \fB\-ansi\fR option (and \fB\-std\fR +options for strict \s-1ISO\s0 C conformance) implies \fB\-trigraphs\fR. +.IP "\fB\-no\-integrated\-cpp\fR" 4 +.IX Item "-no-integrated-cpp" +Performs a compilation in two passes: preprocessing and compiling. This +option allows a user supplied \*(L"cc1\*(R", \*(L"cc1plus\*(R", or \*(L"cc1obj\*(R" via the +\&\fB\-B\fR option. The user supplied compilation step can then add in +an additional preprocessing step after normal preprocessing but before +compiling. The default is to use the integrated cpp (internal cpp) +.Sp +The semantics of this option will change if \*(L"cc1\*(R", \*(L"cc1plus\*(R", and +\&\*(L"cc1obj\*(R" are merged. +.IP "\fB\-traditional\fR" 4 +.IX Item "-traditional" +.PD 0 +.IP "\fB\-traditional\-cpp\fR" 4 +.IX Item "-traditional-cpp" +.PD +Formerly, these options caused \s-1GCC\s0 to attempt to emulate a pre-standard +C compiler. They are now only supported with the \fB\-E\fR switch. +The preprocessor continues to support a pre-standard mode. See the \s-1GNU\s0 +\&\s-1CPP\s0 manual for details. +.IP "\fB\-fcond\-mismatch\fR" 4 +.IX Item "-fcond-mismatch" +Allow conditional expressions with mismatched types in the second and +third arguments. The value of such an expression is void. This option +is not supported for \*(C+. +.IP "\fB\-flax\-vector\-conversions\fR" 4 +.IX Item "-flax-vector-conversions" +Allow implicit conversions between vectors with differing numbers of +elements and/or incompatible element types. This option should not be +used for new code. +.IP "\fB\-funsigned\-char\fR" 4 +.IX Item "-funsigned-char" +Let the type \f(CW\*(C`char\*(C'\fR be unsigned, like \f(CW\*(C`unsigned char\*(C'\fR. +.Sp +Each kind of machine has a default for what \f(CW\*(C`char\*(C'\fR should +be. It is either like \f(CW\*(C`unsigned char\*(C'\fR by default or like +\&\f(CW\*(C`signed char\*(C'\fR by default. +.Sp +Ideally, a portable program should always use \f(CW\*(C`signed char\*(C'\fR or +\&\f(CW\*(C`unsigned char\*(C'\fR when it depends on the signedness of an object. +But many programs have been written to use plain \f(CW\*(C`char\*(C'\fR and +expect it to be signed, or expect it to be unsigned, depending on the +machines they were written for. This option, and its inverse, let you +make such a program work with the opposite default. +.Sp +The type \f(CW\*(C`char\*(C'\fR is always a distinct type from each of +\&\f(CW\*(C`signed char\*(C'\fR or \f(CW\*(C`unsigned char\*(C'\fR, even though its behavior +is always just like one of those two. +.IP "\fB\-fsigned\-char\fR" 4 +.IX Item "-fsigned-char" +Let the type \f(CW\*(C`char\*(C'\fR be signed, like \f(CW\*(C`signed char\*(C'\fR. +.Sp +Note that this is equivalent to \fB\-fno\-unsigned\-char\fR, which is +the negative form of \fB\-funsigned\-char\fR. Likewise, the option +\&\fB\-fno\-signed\-char\fR is equivalent to \fB\-funsigned\-char\fR. +.IP "\fB\-fsigned\-bitfields\fR" 4 +.IX Item "-fsigned-bitfields" +.PD 0 +.IP "\fB\-funsigned\-bitfields\fR" 4 +.IX Item "-funsigned-bitfields" +.IP "\fB\-fno\-signed\-bitfields\fR" 4 +.IX Item "-fno-signed-bitfields" +.IP "\fB\-fno\-unsigned\-bitfields\fR" 4 +.IX Item "-fno-unsigned-bitfields" +.PD +These options control whether a bit-field is signed or unsigned, when the +declaration does not use either \f(CW\*(C`signed\*(C'\fR or \f(CW\*(C`unsigned\*(C'\fR. By +default, such a bit-field is signed, because this is consistent: the +basic integer types such as \f(CW\*(C`int\*(C'\fR are signed types. +.SS "Options Controlling \*(C+ Dialect" +.IX Subsection "Options Controlling Dialect" +This section describes the command-line options that are only meaningful +for \*(C+ programs; but you can also use most of the \s-1GNU\s0 compiler options +regardless of what language your program is in. For example, you +might compile a file \f(CW\*(C`firstClass.C\*(C'\fR like this: +.PP +.Vb 1 +\& g++ \-g \-frepo \-O \-c firstClass.C +.Ve +.PP +In this example, only \fB\-frepo\fR is an option meant +only for \*(C+ programs; you can use the other options with any +language supported by \s-1GCC\s0. +.PP +Here is a list of options that are \fIonly\fR for compiling \*(C+ programs: +.IP "\fB\-fabi\-version=\fR\fIn\fR" 4 +.IX Item "-fabi-version=n" +Use version \fIn\fR of the \*(C+ \s-1ABI\s0. Version 2 is the version of the +\&\*(C+ \s-1ABI\s0 that first appeared in G++ 3.4. Version 1 is the version of +the \*(C+ \s-1ABI\s0 that first appeared in G++ 3.2. Version 0 will always be +the version that conforms most closely to the \*(C+ \s-1ABI\s0 specification. +Therefore, the \s-1ABI\s0 obtained using version 0 will change as \s-1ABI\s0 bugs +are fixed. +.Sp +The default is version 2. +.Sp +Version 3 corrects an error in mangling a constant address as a +template argument. +.Sp +Version 4 implements a standard mangling for vector types. +.Sp +Version 5 corrects the mangling of attribute const/volatile on +function pointer types, decltype of a plain decl, and use of a +function parameter in the declaration of another parameter. +.Sp +See also \fB\-Wabi\fR. +.IP "\fB\-fno\-access\-control\fR" 4 +.IX Item "-fno-access-control" +Turn off all access checking. This switch is mainly useful for working +around bugs in the access control code. +.IP "\fB\-fcheck\-new\fR" 4 +.IX Item "-fcheck-new" +Check that the pointer returned by \f(CW\*(C`operator new\*(C'\fR is non-null +before attempting to modify the storage allocated. This check is +normally unnecessary because the \*(C+ standard specifies that +\&\f(CW\*(C`operator new\*(C'\fR will only return \f(CW0\fR if it is declared +\&\fB\f(BIthrow()\fB\fR, in which case the compiler will always check the +return value even without this option. In all other cases, when +\&\f(CW\*(C`operator new\*(C'\fR has a non-empty exception specification, memory +exhaustion is signalled by throwing \f(CW\*(C`std::bad_alloc\*(C'\fR. See also +\&\fBnew (nothrow)\fR. +.IP "\fB\-fconserve\-space\fR" 4 +.IX Item "-fconserve-space" +Put uninitialized or runtime-initialized global variables into the +common segment, as C does. This saves space in the executable at the +cost of not diagnosing duplicate definitions. If you compile with this +flag and your program mysteriously crashes after \f(CW\*(C`main()\*(C'\fR has +completed, you may have an object that is being destroyed twice because +two definitions were merged. +.Sp +This option is no longer useful on most targets, now that support has +been added for putting variables into \s-1BSS\s0 without making them common. +.IP "\fB\-fconstexpr\-depth=\fR\fIn\fR" 4 +.IX Item "-fconstexpr-depth=n" +Set the maximum nested evaluation depth for \*(C+0x constexpr functions +to \fIn\fR. A limit is needed to detect endless recursion during +constant expression evaluation. The minimum specified by the standard +is 512. +.IP "\fB\-fno\-deduce\-init\-list\fR" 4 +.IX Item "-fno-deduce-init-list" +Disable deduction of a template type parameter as +std::initializer_list from a brace-enclosed initializer list, i.e. +.Sp +.Vb 4 +\& template <class T> auto forward(T t) \-> decltype (realfn (t)) +\& { +\& return realfn (t); +\& } +\& +\& void f() +\& { +\& forward({1,2}); // call forward<std::initializer_list<int>> +\& } +.Ve +.Sp +This option is present because this deduction is an extension to the +current specification in the \*(C+0x working draft, and there was +some concern about potential overload resolution problems. +.IP "\fB\-ffriend\-injection\fR" 4 +.IX Item "-ffriend-injection" +Inject friend functions into the enclosing namespace, so that they are +visible outside the scope of the class in which they are declared. +Friend functions were documented to work this way in the old Annotated +\&\*(C+ Reference Manual, and versions of G++ before 4.1 always worked +that way. However, in \s-1ISO\s0 \*(C+ a friend function which is not declared +in an enclosing scope can only be found using argument dependent +lookup. This option causes friends to be injected as they were in +earlier releases. +.Sp +This option is for compatibility, and may be removed in a future +release of G++. +.IP "\fB\-fno\-elide\-constructors\fR" 4 +.IX Item "-fno-elide-constructors" +The \*(C+ standard allows an implementation to omit creating a temporary +which is only used to initialize another object of the same type. +Specifying this option disables that optimization, and forces G++ to +call the copy constructor in all cases. +.IP "\fB\-fno\-enforce\-eh\-specs\fR" 4 +.IX Item "-fno-enforce-eh-specs" +Don't generate code to check for violation of exception specifications +at runtime. This option violates the \*(C+ standard, but may be useful +for reducing code size in production builds, much like defining +\&\fB\s-1NDEBUG\s0\fR. This does not give user code permission to throw +exceptions in violation of the exception specifications; the compiler +will still optimize based on the specifications, so throwing an +unexpected exception will result in undefined behavior. +.IP "\fB\-ffor\-scope\fR" 4 +.IX Item "-ffor-scope" +.PD 0 +.IP "\fB\-fno\-for\-scope\fR" 4 +.IX Item "-fno-for-scope" +.PD +If \fB\-ffor\-scope\fR is specified, the scope of variables declared in +a \fIfor-init-statement\fR is limited to the \fBfor\fR loop itself, +as specified by the \*(C+ standard. +If \fB\-fno\-for\-scope\fR is specified, the scope of variables declared in +a \fIfor-init-statement\fR extends to the end of the enclosing scope, +as was the case in old versions of G++, and other (traditional) +implementations of \*(C+. +.Sp +The default if neither flag is given to follow the standard, +but to allow and give a warning for old-style code that would +otherwise be invalid, or have different behavior. +.IP "\fB\-fno\-gnu\-keywords\fR" 4 +.IX Item "-fno-gnu-keywords" +Do not recognize \f(CW\*(C`typeof\*(C'\fR as a keyword, so that code can use this +word as an identifier. You can use the keyword \f(CW\*(C`_\|_typeof_\|_\*(C'\fR instead. +\&\fB\-ansi\fR implies \fB\-fno\-gnu\-keywords\fR. +.IP "\fB\-fno\-implicit\-templates\fR" 4 +.IX Item "-fno-implicit-templates" +Never emit code for non-inline templates which are instantiated +implicitly (i.e. by use); only emit code for explicit instantiations. +.IP "\fB\-fno\-implicit\-inline\-templates\fR" 4 +.IX Item "-fno-implicit-inline-templates" +Don't emit code for implicit instantiations of inline templates, either. +The default is to handle inlines differently so that compiles with and +without optimization will need the same set of explicit instantiations. +.IP "\fB\-fno\-implement\-inlines\fR" 4 +.IX Item "-fno-implement-inlines" +To save space, do not emit out-of-line copies of inline functions +controlled by \fB#pragma implementation\fR. This will cause linker +errors if these functions are not inlined everywhere they are called. +.IP "\fB\-fms\-extensions\fR" 4 +.IX Item "-fms-extensions" +Disable pedantic warnings about constructs used in \s-1MFC\s0, such as implicit +int and getting a pointer to member function via non-standard syntax. +.IP "\fB\-fno\-nonansi\-builtins\fR" 4 +.IX Item "-fno-nonansi-builtins" +Disable built-in declarations of functions that are not mandated by +\&\s-1ANSI/ISO\s0 C. These include \f(CW\*(C`ffs\*(C'\fR, \f(CW\*(C`alloca\*(C'\fR, \f(CW\*(C`_exit\*(C'\fR, +\&\f(CW\*(C`index\*(C'\fR, \f(CW\*(C`bzero\*(C'\fR, \f(CW\*(C`conjf\*(C'\fR, and other related functions. +.IP "\fB\-fnothrow\-opt\fR" 4 +.IX Item "-fnothrow-opt" +Treat a \f(CW\*(C`throw()\*(C'\fR exception specification as though it were a +\&\f(CW\*(C`noexcept\*(C'\fR specification to reduce or eliminate the text size +overhead relative to a function with no exception specification. If +the function has local variables of types with non-trivial +destructors, the exception specification will actually make the +function smaller because the \s-1EH\s0 cleanups for those variables can be +optimized away. The semantic effect is that an exception thrown out of +a function with such an exception specification will result in a call +to \f(CW\*(C`terminate\*(C'\fR rather than \f(CW\*(C`unexpected\*(C'\fR. +.IP "\fB\-fno\-operator\-names\fR" 4 +.IX Item "-fno-operator-names" +Do not treat the operator name keywords \f(CW\*(C`and\*(C'\fR, \f(CW\*(C`bitand\*(C'\fR, +\&\f(CW\*(C`bitor\*(C'\fR, \f(CW\*(C`compl\*(C'\fR, \f(CW\*(C`not\*(C'\fR, \f(CW\*(C`or\*(C'\fR and \f(CW\*(C`xor\*(C'\fR as +synonyms as keywords. +.IP "\fB\-fno\-optional\-diags\fR" 4 +.IX Item "-fno-optional-diags" +Disable diagnostics that the standard says a compiler does not need to +issue. Currently, the only such diagnostic issued by G++ is the one for +a name having multiple meanings within a class. +.IP "\fB\-fpermissive\fR" 4 +.IX Item "-fpermissive" +Downgrade some diagnostics about nonconformant code from errors to +warnings. Thus, using \fB\-fpermissive\fR will allow some +nonconforming code to compile. +.IP "\fB\-fno\-pretty\-templates\fR" 4 +.IX Item "-fno-pretty-templates" +When an error message refers to a specialization of a function +template, the compiler will normally print the signature of the +template followed by the template arguments and any typedefs or +typenames in the signature (e.g. \f(CW\*(C`void f(T) [with T = int]\*(C'\fR +rather than \f(CW\*(C`void f(int)\*(C'\fR) so that it's clear which template is +involved. When an error message refers to a specialization of a class +template, the compiler will omit any template arguments which match +the default template arguments for that template. If either of these +behaviors make it harder to understand the error message rather than +easier, using \fB\-fno\-pretty\-templates\fR will disable them. +.IP "\fB\-frepo\fR" 4 +.IX Item "-frepo" +Enable automatic template instantiation at link time. This option also +implies \fB\-fno\-implicit\-templates\fR. +.IP "\fB\-fno\-rtti\fR" 4 +.IX Item "-fno-rtti" +Disable generation of information about every class with virtual +functions for use by the \*(C+ runtime type identification features +(\fBdynamic_cast\fR and \fBtypeid\fR). If you don't use those parts +of the language, you can save some space by using this flag. Note that +exception handling uses the same information, but it will generate it as +needed. The \fBdynamic_cast\fR operator can still be used for casts that +do not require runtime type information, i.e. casts to \f(CW\*(C`void *\*(C'\fR or to +unambiguous base classes. +.IP "\fB\-fstats\fR" 4 +.IX Item "-fstats" +Emit statistics about front-end processing at the end of the compilation. +This information is generally only useful to the G++ development team. +.IP "\fB\-fstrict\-enums\fR" 4 +.IX Item "-fstrict-enums" +Allow the compiler to optimize using the assumption that a value of +enumeration type can only be one of the values of the enumeration (as +defined in the \*(C+ standard; basically, a value which can be +represented in the minimum number of bits needed to represent all the +enumerators). This assumption may not be valid if the program uses a +cast to convert an arbitrary integer value to the enumeration type. +.IP "\fB\-ftemplate\-depth=\fR\fIn\fR" 4 +.IX Item "-ftemplate-depth=n" +Set the maximum instantiation depth for template classes to \fIn\fR. +A limit on the template instantiation depth is needed to detect +endless recursions during template class instantiation. \s-1ANSI/ISO\s0 \*(C+ +conforming programs must not rely on a maximum depth greater than 17 +(changed to 1024 in \*(C+0x). +.IP "\fB\-fno\-threadsafe\-statics\fR" 4 +.IX Item "-fno-threadsafe-statics" +Do not emit the extra code to use the routines specified in the \*(C+ +\&\s-1ABI\s0 for thread-safe initialization of local statics. You can use this +option to reduce code size slightly in code that doesn't need to be +thread-safe. +.IP "\fB\-fuse\-cxa\-atexit\fR" 4 +.IX Item "-fuse-cxa-atexit" +Register destructors for objects with static storage duration with the +\&\f(CW\*(C`_\|_cxa_atexit\*(C'\fR function rather than the \f(CW\*(C`atexit\*(C'\fR function. +This option is required for fully standards-compliant handling of static +destructors, but will only work if your C library supports +\&\f(CW\*(C`_\|_cxa_atexit\*(C'\fR. +.IP "\fB\-fno\-use\-cxa\-get\-exception\-ptr\fR" 4 +.IX Item "-fno-use-cxa-get-exception-ptr" +Don't use the \f(CW\*(C`_\|_cxa_get_exception_ptr\*(C'\fR runtime routine. This +will cause \f(CW\*(C`std::uncaught_exception\*(C'\fR to be incorrect, but is necessary +if the runtime routine is not available. +.IP "\fB\-fvisibility\-inlines\-hidden\fR" 4 +.IX Item "-fvisibility-inlines-hidden" +This switch declares that the user does not attempt to compare +pointers to inline methods where the addresses of the two functions +were taken in different shared objects. +.Sp +The effect of this is that \s-1GCC\s0 may, effectively, mark inline methods with +\&\f(CW\*(C`_\|_attribute_\|_ ((visibility ("hidden")))\*(C'\fR so that they do not +appear in the export table of a \s-1DSO\s0 and do not require a \s-1PLT\s0 indirection +when used within the \s-1DSO\s0. Enabling this option can have a dramatic effect +on load and link times of a \s-1DSO\s0 as it massively reduces the size of the +dynamic export table when the library makes heavy use of templates. +.Sp +The behavior of this switch is not quite the same as marking the +methods as hidden directly, because it does not affect static variables +local to the function or cause the compiler to deduce that +the function is defined in only one shared object. +.Sp +You may mark a method as having a visibility explicitly to negate the +effect of the switch for that method. For example, if you do want to +compare pointers to a particular inline method, you might mark it as +having default visibility. Marking the enclosing class with explicit +visibility will have no effect. +.Sp +Explicitly instantiated inline methods are unaffected by this option +as their linkage might otherwise cross a shared library boundary. +.IP "\fB\-fvisibility\-ms\-compat\fR" 4 +.IX Item "-fvisibility-ms-compat" +This flag attempts to use visibility settings to make \s-1GCC\s0's \*(C+ +linkage model compatible with that of Microsoft Visual Studio. +.Sp +The flag makes these changes to \s-1GCC\s0's linkage model: +.RS 4 +.IP "1." 4 +It sets the default visibility to \f(CW\*(C`hidden\*(C'\fR, like +\&\fB\-fvisibility=hidden\fR. +.IP "2." 4 +Types, but not their members, are not hidden by default. +.IP "3." 4 +The One Definition Rule is relaxed for types without explicit +visibility specifications which are defined in more than one different +shared object: those declarations are permitted if they would have +been permitted when this option was not used. +.RE +.RS 4 +.Sp +In new code it is better to use \fB\-fvisibility=hidden\fR and +export those classes which are intended to be externally visible. +Unfortunately it is possible for code to rely, perhaps accidentally, +on the Visual Studio behavior. +.Sp +Among the consequences of these changes are that static data members +of the same type with the same name but defined in different shared +objects will be different, so changing one will not change the other; +and that pointers to function members defined in different shared +objects may not compare equal. When this flag is given, it is a +violation of the \s-1ODR\s0 to define types with the same name differently. +.RE +.IP "\fB\-fno\-weak\fR" 4 +.IX Item "-fno-weak" +Do not use weak symbol support, even if it is provided by the linker. +By default, G++ will use weak symbols if they are available. This +option exists only for testing, and should not be used by end-users; +it will result in inferior code and has no benefits. This option may +be removed in a future release of G++. +.IP "\fB\-nostdinc++\fR" 4 +.IX Item "-nostdinc++" +Do not search for header files in the standard directories specific to +\&\*(C+, but do still search the other standard directories. (This option +is used when building the \*(C+ library.) +.PP +In addition, these optimization, warning, and code generation options +have meanings only for \*(C+ programs: +.IP "\fB\-fno\-default\-inline\fR" 4 +.IX Item "-fno-default-inline" +Do not assume \fBinline\fR for functions defined inside a class scope. + Note that these +functions will have linkage like inline functions; they just won't be +inlined by default. +.IP "\fB\-Wabi\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wabi (C, Objective-C, and Objective- only)" +Warn when G++ generates code that is probably not compatible with the +vendor-neutral \*(C+ \s-1ABI\s0. Although an effort has been made to warn about +all such cases, there are probably some cases that are not warned about, +even though G++ is generating incompatible code. There may also be +cases where warnings are emitted even though the code that is generated +will be compatible. +.Sp +You should rewrite your code to avoid these warnings if you are +concerned about the fact that code generated by G++ may not be binary +compatible with code generated by other compilers. +.Sp +The known incompatibilities in \fB\-fabi\-version=2\fR (the default) include: +.RS 4 +.IP "\(bu" 4 +A template with a non-type template parameter of reference type is +mangled incorrectly: +.Sp +.Vb 3 +\& extern int N; +\& template <int &> struct S {}; +\& void n (S<N>) {2} +.Ve +.Sp +This is fixed in \fB\-fabi\-version=3\fR. +.IP "\(bu" 4 +\&\s-1SIMD\s0 vector types declared using \f(CW\*(C`_\|_attribute ((vector_size))\*(C'\fR are +mangled in a non-standard way that does not allow for overloading of +functions taking vectors of different sizes. +.Sp +The mangling is changed in \fB\-fabi\-version=4\fR. +.RE +.RS 4 +.Sp +The known incompatibilities in \fB\-fabi\-version=1\fR include: +.IP "\(bu" 4 +Incorrect handling of tail-padding for bit-fields. G++ may attempt to +pack data into the same byte as a base class. For example: +.Sp +.Vb 2 +\& struct A { virtual void f(); int f1 : 1; }; +\& struct B : public A { int f2 : 1; }; +.Ve +.Sp +In this case, G++ will place \f(CW\*(C`B::f2\*(C'\fR into the same byte +as\f(CW\*(C`A::f1\*(C'\fR; other compilers will not. You can avoid this problem +by explicitly padding \f(CW\*(C`A\*(C'\fR so that its size is a multiple of the +byte size on your platform; that will cause G++ and other compilers to +layout \f(CW\*(C`B\*(C'\fR identically. +.IP "\(bu" 4 +Incorrect handling of tail-padding for virtual bases. G++ does not use +tail padding when laying out virtual bases. For example: +.Sp +.Vb 3 +\& struct A { virtual void f(); char c1; }; +\& struct B { B(); char c2; }; +\& struct C : public A, public virtual B {}; +.Ve +.Sp +In this case, G++ will not place \f(CW\*(C`B\*(C'\fR into the tail-padding for +\&\f(CW\*(C`A\*(C'\fR; other compilers will. You can avoid this problem by +explicitly padding \f(CW\*(C`A\*(C'\fR so that its size is a multiple of its +alignment (ignoring virtual base classes); that will cause G++ and other +compilers to layout \f(CW\*(C`C\*(C'\fR identically. +.IP "\(bu" 4 +Incorrect handling of bit-fields with declared widths greater than that +of their underlying types, when the bit-fields appear in a union. For +example: +.Sp +.Vb 1 +\& union U { int i : 4096; }; +.Ve +.Sp +Assuming that an \f(CW\*(C`int\*(C'\fR does not have 4096 bits, G++ will make the +union too small by the number of bits in an \f(CW\*(C`int\*(C'\fR. +.IP "\(bu" 4 +Empty classes can be placed at incorrect offsets. For example: +.Sp +.Vb 1 +\& struct A {}; +\& +\& struct B { +\& A a; +\& virtual void f (); +\& }; +\& +\& struct C : public B, public A {}; +.Ve +.Sp +G++ will place the \f(CW\*(C`A\*(C'\fR base class of \f(CW\*(C`C\*(C'\fR at a nonzero offset; +it should be placed at offset zero. G++ mistakenly believes that the +\&\f(CW\*(C`A\*(C'\fR data member of \f(CW\*(C`B\*(C'\fR is already at offset zero. +.IP "\(bu" 4 +Names of template functions whose types involve \f(CW\*(C`typename\*(C'\fR or +template template parameters can be mangled incorrectly. +.Sp +.Vb 2 +\& template <typename Q> +\& void f(typename Q::X) {} +\& +\& template <template <typename> class Q> +\& void f(typename Q<int>::X) {} +.Ve +.Sp +Instantiations of these templates may be mangled incorrectly. +.RE +.RS 4 +.Sp +It also warns psABI related changes. The known psABI changes at this +point include: +.IP "\(bu" 4 +For SYSV/x86\-64, when passing union with long double, it is changed to +pass in memory as specified in psABI. For example: +.Sp +.Vb 4 +\& union U { +\& long double ld; +\& int i; +\& }; +.Ve +.Sp +\&\f(CW\*(C`union U\*(C'\fR will always be passed in memory. +.RE +.RS 4 +.RE +.IP "\fB\-Wctor\-dtor\-privacy\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wctor-dtor-privacy ( and Objective- only)" +Warn when a class seems unusable because all the constructors or +destructors in that class are private, and it has neither friends nor +public static member functions. +.IP "\fB\-Wnoexcept\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wnoexcept ( and Objective- only)" +Warn when a noexcept-expression evaluates to false because of a call +to a function that does not have a non-throwing exception +specification (i.e. \fB\f(BIthrow()\fB\fR or \fBnoexcept\fR) but is known by +the compiler to never throw an exception. +.IP "\fB\-Wnon\-virtual\-dtor\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wnon-virtual-dtor ( and Objective- only)" +Warn when a class has virtual functions and accessible non-virtual +destructor, in which case it would be possible but unsafe to delete +an instance of a derived class through a pointer to the base class. +This warning is also enabled if \-Weffc++ is specified. +.IP "\fB\-Wreorder\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wreorder ( and Objective- only)" +Warn when the order of member initializers given in the code does not +match the order in which they must be executed. For instance: +.Sp +.Vb 5 +\& struct A { +\& int i; +\& int j; +\& A(): j (0), i (1) { } +\& }; +.Ve +.Sp +The compiler will rearrange the member initializers for \fBi\fR +and \fBj\fR to match the declaration order of the members, emitting +a warning to that effect. This warning is enabled by \fB\-Wall\fR. +.PP +The following \fB\-W...\fR options are not affected by \fB\-Wall\fR. +.IP "\fB\-Weffc++\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Weffc++ ( and Objective- only)" +Warn about violations of the following style guidelines from Scott Meyers' +\&\fIEffective \*(C+\fR book: +.RS 4 +.IP "\(bu" 4 +Item 11: Define a copy constructor and an assignment operator for classes +with dynamically allocated memory. +.IP "\(bu" 4 +Item 12: Prefer initialization to assignment in constructors. +.IP "\(bu" 4 +Item 14: Make destructors virtual in base classes. +.IP "\(bu" 4 +Item 15: Have \f(CW\*(C`operator=\*(C'\fR return a reference to \f(CW*this\fR. +.IP "\(bu" 4 +Item 23: Don't try to return a reference when you must return an object. +.RE +.RS 4 +.Sp +Also warn about violations of the following style guidelines from +Scott Meyers' \fIMore Effective \*(C+\fR book: +.IP "\(bu" 4 +Item 6: Distinguish between prefix and postfix forms of increment and +decrement operators. +.IP "\(bu" 4 +Item 7: Never overload \f(CW\*(C`&&\*(C'\fR, \f(CW\*(C`||\*(C'\fR, or \f(CW\*(C`,\*(C'\fR. +.RE +.RS 4 +.Sp +When selecting this option, be aware that the standard library +headers do not obey all of these guidelines; use \fBgrep \-v\fR +to filter out those warnings. +.RE +.IP "\fB\-Wstrict\-null\-sentinel\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wstrict-null-sentinel ( and Objective- only)" +Warn also about the use of an uncasted \f(CW\*(C`NULL\*(C'\fR as sentinel. When +compiling only with \s-1GCC\s0 this is a valid sentinel, as \f(CW\*(C`NULL\*(C'\fR is defined +to \f(CW\*(C`_\|_null\*(C'\fR. Although it is a null pointer constant not a null pointer, +it is guaranteed to be of the same size as a pointer. But this use is +not portable across different compilers. +.IP "\fB\-Wno\-non\-template\-friend\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-non-template-friend ( and Objective- only)" +Disable warnings when non-templatized friend functions are declared +within a template. Since the advent of explicit template specification +support in G++, if the name of the friend is an unqualified-id (i.e., +\&\fBfriend foo(int)\fR), the \*(C+ language specification demands that the +friend declare or define an ordinary, nontemplate function. (Section +14.5.3). Before G++ implemented explicit specification, unqualified-ids +could be interpreted as a particular specialization of a templatized +function. Because this non-conforming behavior is no longer the default +behavior for G++, \fB\-Wnon\-template\-friend\fR allows the compiler to +check existing code for potential trouble spots and is on by default. +This new compiler behavior can be turned off with +\&\fB\-Wno\-non\-template\-friend\fR which keeps the conformant compiler code +but disables the helpful warning. +.IP "\fB\-Wold\-style\-cast\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wold-style-cast ( and Objective- only)" +Warn if an old-style (C\-style) cast to a non-void type is used within +a \*(C+ program. The new-style casts (\fBdynamic_cast\fR, +\&\fBstatic_cast\fR, \fBreinterpret_cast\fR, and \fBconst_cast\fR) are +less vulnerable to unintended effects and much easier to search for. +.IP "\fB\-Woverloaded\-virtual\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Woverloaded-virtual ( and Objective- only)" +Warn when a function declaration hides virtual functions from a +base class. For example, in: +.Sp +.Vb 3 +\& struct A { +\& virtual void f(); +\& }; +\& +\& struct B: public A { +\& void f(int); +\& }; +.Ve +.Sp +the \f(CW\*(C`A\*(C'\fR class version of \f(CW\*(C`f\*(C'\fR is hidden in \f(CW\*(C`B\*(C'\fR, and code +like: +.Sp +.Vb 2 +\& B* b; +\& b\->f(); +.Ve +.Sp +will fail to compile. +.IP "\fB\-Wno\-pmf\-conversions\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-pmf-conversions ( and Objective- only)" +Disable the diagnostic for converting a bound pointer to member function +to a plain pointer. +.IP "\fB\-Wsign\-promo\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wsign-promo ( and Objective- only)" +Warn when overload resolution chooses a promotion from unsigned or +enumerated type to a signed type, over a conversion to an unsigned type of +the same size. Previous versions of G++ would try to preserve +unsignedness, but the standard mandates the current behavior. +.Sp +.Vb 4 +\& struct A { +\& operator int (); +\& A& operator = (int); +\& }; +\& +\& main () +\& { +\& A a,b; +\& a = b; +\& } +.Ve +.Sp +In this example, G++ will synthesize a default \fBA& operator = +(const A&);\fR, while cfront will use the user-defined \fBoperator =\fR. +.SS "Options Controlling Objective-C and Objective\-\*(C+ Dialects" +.IX Subsection "Options Controlling Objective-C and Objective- Dialects" +(\s-1NOTE:\s0 This manual does not describe the Objective-C and Objective\-\*(C+ +languages themselves. +.PP +This section describes the command-line options that are only meaningful +for Objective-C and Objective\-\*(C+ programs, but you can also use most of +the language-independent \s-1GNU\s0 compiler options. +For example, you might compile a file \f(CW\*(C`some_class.m\*(C'\fR like this: +.PP +.Vb 1 +\& gcc \-g \-fgnu\-runtime \-O \-c some_class.m +.Ve +.PP +In this example, \fB\-fgnu\-runtime\fR is an option meant only for +Objective-C and Objective\-\*(C+ programs; you can use the other options with +any language supported by \s-1GCC\s0. +.PP +Note that since Objective-C is an extension of the C language, Objective-C +compilations may also use options specific to the C front-end (e.g., +\&\fB\-Wtraditional\fR). Similarly, Objective\-\*(C+ compilations may use +\&\*(C+\-specific options (e.g., \fB\-Wabi\fR). +.PP +Here is a list of options that are \fIonly\fR for compiling Objective-C +and Objective\-\*(C+ programs: +.IP "\fB\-fconstant\-string\-class=\fR\fIclass-name\fR" 4 +.IX Item "-fconstant-string-class=class-name" +Use \fIclass-name\fR as the name of the class to instantiate for each +literal string specified with the syntax \f(CW\*(C`@"..."\*(C'\fR. The default +class name is \f(CW\*(C`NXConstantString\*(C'\fR if the \s-1GNU\s0 runtime is being used, and +\&\f(CW\*(C`NSConstantString\*(C'\fR if the NeXT runtime is being used (see below). The +\&\fB\-fconstant\-cfstrings\fR option, if also present, will override the +\&\fB\-fconstant\-string\-class\fR setting and cause \f(CW\*(C`@"..."\*(C'\fR literals +to be laid out as constant CoreFoundation strings. +.IP "\fB\-fgnu\-runtime\fR" 4 +.IX Item "-fgnu-runtime" +Generate object code compatible with the standard \s-1GNU\s0 Objective-C +runtime. This is the default for most types of systems. +.IP "\fB\-fnext\-runtime\fR" 4 +.IX Item "-fnext-runtime" +Generate output compatible with the NeXT runtime. This is the default +for NeXT-based systems, including Darwin and Mac \s-1OS\s0 X. The macro +\&\f(CW\*(C`_\|_NEXT_RUNTIME_\|_\*(C'\fR is predefined if (and only if) this option is +used. +.IP "\fB\-fno\-nil\-receivers\fR" 4 +.IX Item "-fno-nil-receivers" +Assume that all Objective-C message dispatches (\f(CW\*(C`[receiver +message:arg]\*(C'\fR) in this translation unit ensure that the receiver is +not \f(CW\*(C`nil\*(C'\fR. This allows for more efficient entry points in the +runtime to be used. This option is only available in conjunction with +the NeXT runtime and \s-1ABI\s0 version 0 or 1. +.IP "\fB\-fobjc\-abi\-version=\fR\fIn\fR" 4 +.IX Item "-fobjc-abi-version=n" +Use version \fIn\fR of the Objective-C \s-1ABI\s0 for the selected runtime. +This option is currently supported only for the NeXT runtime. In that +case, Version 0 is the traditional (32\-bit) \s-1ABI\s0 without support for +properties and other Objective-C 2.0 additions. Version 1 is the +traditional (32\-bit) \s-1ABI\s0 with support for properties and other +Objective-C 2.0 additions. Version 2 is the modern (64\-bit) \s-1ABI\s0. If +nothing is specified, the default is Version 0 on 32\-bit target +machines, and Version 2 on 64\-bit target machines. +.IP "\fB\-fobjc\-call\-cxx\-cdtors\fR" 4 +.IX Item "-fobjc-call-cxx-cdtors" +For each Objective-C class, check if any of its instance variables is a +\&\*(C+ object with a non-trivial default constructor. If so, synthesize a +special \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR instance method that will run +non-trivial default constructors on any such instance variables, in order, +and then return \f(CW\*(C`self\*(C'\fR. Similarly, check if any instance variable +is a \*(C+ object with a non-trivial destructor, and if so, synthesize a +special \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR method that will run +all such default destructors, in reverse order. +.Sp +The \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR and \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR +methods thusly generated will only operate on instance variables +declared in the current Objective-C class, and not those inherited +from superclasses. It is the responsibility of the Objective-C +runtime to invoke all such methods in an object's inheritance +hierarchy. The \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR methods will be invoked +by the runtime immediately after a new object instance is allocated; +the \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR methods will be invoked immediately +before the runtime deallocates an object instance. +.Sp +As of this writing, only the NeXT runtime on Mac \s-1OS\s0 X 10.4 and later has +support for invoking the \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR and +\&\f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR methods. +.IP "\fB\-fobjc\-direct\-dispatch\fR" 4 +.IX Item "-fobjc-direct-dispatch" +Allow fast jumps to the message dispatcher. On Darwin this is +accomplished via the comm page. +.IP "\fB\-fobjc\-exceptions\fR" 4 +.IX Item "-fobjc-exceptions" +Enable syntactic support for structured exception handling in +Objective-C, similar to what is offered by \*(C+ and Java. This option +is required to use the Objective-C keywords \f(CW@try\fR, +\&\f(CW@throw\fR, \f(CW@catch\fR, \f(CW@finally\fR and +\&\f(CW@synchronized\fR. This option is available with both the \s-1GNU\s0 +runtime and the NeXT runtime (but not available in conjunction with +the NeXT runtime on Mac \s-1OS\s0 X 10.2 and earlier). +.IP "\fB\-fobjc\-gc\fR" 4 +.IX Item "-fobjc-gc" +Enable garbage collection (\s-1GC\s0) in Objective-C and Objective\-\*(C+ +programs. This option is only available with the NeXT runtime; the +\&\s-1GNU\s0 runtime has a different garbage collection implementation that +does not require special compiler flags. +.IP "\fB\-fobjc\-nilcheck\fR" 4 +.IX Item "-fobjc-nilcheck" +For the NeXT runtime with version 2 of the \s-1ABI\s0, check for a nil +receiver in method invocations before doing the actual method call. +This is the default and can be disabled using +\&\fB\-fno\-objc\-nilcheck\fR. Class methods and super calls are never +checked for nil in this way no matter what this flag is set to. +Currently this flag does nothing when the \s-1GNU\s0 runtime, or an older +version of the NeXT runtime \s-1ABI\s0, is used. +.IP "\fB\-fobjc\-std=objc1\fR" 4 +.IX Item "-fobjc-std=objc1" +Conform to the language syntax of Objective-C 1.0, the language +recognized by \s-1GCC\s0 4.0. This only affects the Objective-C additions to +the C/\*(C+ language; it does not affect conformance to C/\*(C+ standards, +which is controlled by the separate C/\*(C+ dialect option flags. When +this option is used with the Objective-C or Objective\-\*(C+ compiler, +any Objective-C syntax that is not recognized by \s-1GCC\s0 4.0 is rejected. +This is useful if you need to make sure that your Objective-C code can +be compiled with older versions of \s-1GCC\s0. +.IP "\fB\-freplace\-objc\-classes\fR" 4 +.IX Item "-freplace-objc-classes" +Emit a special marker instructing \fB\f(BIld\fB\|(1)\fR not to statically link in +the resulting object file, and allow \fB\f(BIdyld\fB\|(1)\fR to load it in at +run time instead. This is used in conjunction with the Fix-and-Continue +debugging mode, where the object file in question may be recompiled and +dynamically reloaded in the course of program execution, without the need +to restart the program itself. Currently, Fix-and-Continue functionality +is only available in conjunction with the NeXT runtime on Mac \s-1OS\s0 X 10.3 +and later. +.IP "\fB\-fzero\-link\fR" 4 +.IX Item "-fzero-link" +When compiling for the NeXT runtime, the compiler ordinarily replaces calls +to \f(CW\*(C`objc_getClass("...")\*(C'\fR (when the name of the class is known at +compile time) with static class references that get initialized at load time, +which improves run-time performance. Specifying the \fB\-fzero\-link\fR flag +suppresses this behavior and causes calls to \f(CW\*(C`objc_getClass("...")\*(C'\fR +to be retained. This is useful in Zero-Link debugging mode, since it allows +for individual class implementations to be modified during program execution. +The \s-1GNU\s0 runtime currently always retains calls to \f(CW\*(C`objc_get_class("...")\*(C'\fR +regardless of command line options. +.IP "\fB\-gen\-decls\fR" 4 +.IX Item "-gen-decls" +Dump interface declarations for all classes seen in the source file to a +file named \fI\fIsourcename\fI.decl\fR. +.IP "\fB\-Wassign\-intercept\fR (Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wassign-intercept (Objective-C and Objective- only)" +Warn whenever an Objective-C assignment is being intercepted by the +garbage collector. +.IP "\fB\-Wno\-protocol\fR (Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-protocol (Objective-C and Objective- only)" +If a class is declared to implement a protocol, a warning is issued for +every method in the protocol that is not implemented by the class. The +default behavior is to issue a warning for every method not explicitly +implemented in the class, even if a method implementation is inherited +from the superclass. If you use the \fB\-Wno\-protocol\fR option, then +methods inherited from the superclass are considered to be implemented, +and no warning is issued for them. +.IP "\fB\-Wselector\fR (Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wselector (Objective-C and Objective- only)" +Warn if multiple methods of different types for the same selector are +found during compilation. The check is performed on the list of methods +in the final stage of compilation. Additionally, a check is performed +for each selector appearing in a \f(CW\*(C`@selector(...)\*(C'\fR +expression, and a corresponding method for that selector has been found +during compilation. Because these checks scan the method table only at +the end of compilation, these warnings are not produced if the final +stage of compilation is not reached, for example because an error is +found during compilation, or because the \fB\-fsyntax\-only\fR option is +being used. +.IP "\fB\-Wstrict\-selector\-match\fR (Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wstrict-selector-match (Objective-C and Objective- only)" +Warn if multiple methods with differing argument and/or return types are +found for a given selector when attempting to send a message using this +selector to a receiver of type \f(CW\*(C`id\*(C'\fR or \f(CW\*(C`Class\*(C'\fR. When this flag +is off (which is the default behavior), the compiler will omit such warnings +if any differences found are confined to types which share the same size +and alignment. +.IP "\fB\-Wundeclared\-selector\fR (Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wundeclared-selector (Objective-C and Objective- only)" +Warn if a \f(CW\*(C`@selector(...)\*(C'\fR expression referring to an +undeclared selector is found. A selector is considered undeclared if no +method with that name has been declared before the +\&\f(CW\*(C`@selector(...)\*(C'\fR expression, either explicitly in an +\&\f(CW@interface\fR or \f(CW@protocol\fR declaration, or implicitly in +an \f(CW@implementation\fR section. This option always performs its +checks as soon as a \f(CW\*(C`@selector(...)\*(C'\fR expression is found, +while \fB\-Wselector\fR only performs its checks in the final stage of +compilation. This also enforces the coding style convention +that methods and selectors must be declared before being used. +.IP "\fB\-print\-objc\-runtime\-info\fR" 4 +.IX Item "-print-objc-runtime-info" +Generate C header describing the largest structure that is passed by +value, if any. +.SS "Options to Control Diagnostic Messages Formatting" +.IX Subsection "Options to Control Diagnostic Messages Formatting" +Traditionally, diagnostic messages have been formatted irrespective of +the output device's aspect (e.g. its width, ...). The options described +below can be used to control the diagnostic messages formatting +algorithm, e.g. how many characters per line, how often source location +information should be reported. Right now, only the \*(C+ front end can +honor these options. However it is expected, in the near future, that +the remaining front ends would be able to digest them correctly. +.IP "\fB\-fmessage\-length=\fR\fIn\fR" 4 +.IX Item "-fmessage-length=n" +Try to format error messages so that they fit on lines of about \fIn\fR +characters. The default is 72 characters for \fBg++\fR and 0 for the rest of +the front ends supported by \s-1GCC\s0. If \fIn\fR is zero, then no +line-wrapping will be done; each error message will appear on a single +line. +.IP "\fB\-fdiagnostics\-show\-location=once\fR" 4 +.IX Item "-fdiagnostics-show-location=once" +Only meaningful in line-wrapping mode. Instructs the diagnostic messages +reporter to emit \fIonce\fR source location information; that is, in +case the message is too long to fit on a single physical line and has to +be wrapped, the source location won't be emitted (as prefix) again, +over and over, in subsequent continuation lines. This is the default +behavior. +.IP "\fB\-fdiagnostics\-show\-location=every\-line\fR" 4 +.IX Item "-fdiagnostics-show-location=every-line" +Only meaningful in line-wrapping mode. Instructs the diagnostic +messages reporter to emit the same source location information (as +prefix) for physical lines that result from the process of breaking +a message which is too long to fit on a single line. +.IP "\fB\-fno\-diagnostics\-show\-option\fR" 4 +.IX Item "-fno-diagnostics-show-option" +By default, each diagnostic emitted includes text which indicates the +command line option that directly controls the diagnostic (if such an +option is known to the diagnostic machinery). Specifying the +\&\fB\-fno\-diagnostics\-show\-option\fR flag suppresses that behavior. +.IP "\fB\-Wcoverage\-mismatch\fR" 4 +.IX Item "-Wcoverage-mismatch" +Warn if feedback profiles do not match when using the +\&\fB\-fprofile\-use\fR option. +If a source file was changed between \fB\-fprofile\-gen\fR and +\&\fB\-fprofile\-use\fR, the files with the profile feedback can fail +to match the source file and \s-1GCC\s0 can not use the profile feedback +information. By default, this warning is enabled and is treated as an +error. \fB\-Wno\-coverage\-mismatch\fR can be used to disable the +warning or \fB\-Wno\-error=coverage\-mismatch\fR can be used to +disable the error. Disable the error for this warning can result in +poorly optimized code, so disabling the error is useful only in the +case of very minor changes such as bug fixes to an existing code-base. +Completely disabling the warning is not recommended. +.SS "Options to Request or Suppress Warnings" +.IX Subsection "Options to Request or Suppress Warnings" +Warnings are diagnostic messages that report constructions which +are not inherently erroneous but which are risky or suggest there +may have been an error. +.PP +The following language-independent options do not enable specific +warnings but control the kinds of diagnostics produced by \s-1GCC\s0. +.IP "\fB\-fsyntax\-only\fR" 4 +.IX Item "-fsyntax-only" +Check the code for syntax errors, but don't do anything beyond that. +.IP "\fB\-fmax\-errors=\fR\fIn\fR" 4 +.IX Item "-fmax-errors=n" +Limits the maximum number of error messages to \fIn\fR, at which point +\&\s-1GCC\s0 bails out rather than attempting to continue processing the source +code. If \fIn\fR is 0 (the default), there is no limit on the number +of error messages produced. If \fB\-Wfatal\-errors\fR is also +specified, then \fB\-Wfatal\-errors\fR takes precedence over this +option. +.IP "\fB\-w\fR" 4 +.IX Item "-w" +Inhibit all warning messages. +.IP "\fB\-Werror\fR" 4 +.IX Item "-Werror" +Make all warnings into errors. +.IP "\fB\-Werror=\fR" 4 +.IX Item "-Werror=" +Make the specified warning into an error. The specifier for a warning +is appended, for example \fB\-Werror=switch\fR turns the warnings +controlled by \fB\-Wswitch\fR into errors. This switch takes a +negative form, to be used to negate \fB\-Werror\fR for specific +warnings, for example \fB\-Wno\-error=switch\fR makes +\&\fB\-Wswitch\fR warnings not be errors, even when \fB\-Werror\fR +is in effect. +.Sp +The warning message for each controllable warning includes the +option which controls the warning. That option can then be used with +\&\fB\-Werror=\fR and \fB\-Wno\-error=\fR as described above. +(Printing of the option in the warning message can be disabled using the +\&\fB\-fno\-diagnostics\-show\-option\fR flag.) +.Sp +Note that specifying \fB\-Werror=\fR\fIfoo\fR automatically implies +\&\fB\-W\fR\fIfoo\fR. However, \fB\-Wno\-error=\fR\fIfoo\fR does not +imply anything. +.IP "\fB\-Wfatal\-errors\fR" 4 +.IX Item "-Wfatal-errors" +This option causes the compiler to abort compilation on the first error +occurred rather than trying to keep going and printing further error +messages. +.PP +You can request many specific warnings with options beginning +\&\fB\-W\fR, for example \fB\-Wimplicit\fR to request warnings on +implicit declarations. Each of these specific warning options also +has a negative form beginning \fB\-Wno\-\fR to turn off warnings; for +example, \fB\-Wno\-implicit\fR. This manual lists only one of the +two forms, whichever is not the default. For further, +language-specific options also refer to \fB\*(C+ Dialect Options\fR and +\&\fBObjective-C and Objective\-\*(C+ Dialect Options\fR. +.PP +When an unrecognized warning option is requested (e.g., +\&\fB\-Wunknown\-warning\fR), \s-1GCC\s0 will emit a diagnostic stating +that the option is not recognized. However, if the \fB\-Wno\-\fR form +is used, the behavior is slightly different: No diagnostic will be +produced for \fB\-Wno\-unknown\-warning\fR unless other diagnostics +are being produced. This allows the use of new \fB\-Wno\-\fR options +with old compilers, but if something goes wrong, the compiler will +warn that an unrecognized option was used. +.IP "\fB\-pedantic\fR" 4 +.IX Item "-pedantic" +Issue all the warnings demanded by strict \s-1ISO\s0 C and \s-1ISO\s0 \*(C+; +reject all programs that use forbidden extensions, and some other +programs that do not follow \s-1ISO\s0 C and \s-1ISO\s0 \*(C+. For \s-1ISO\s0 C, follows the +version of the \s-1ISO\s0 C standard specified by any \fB\-std\fR option used. +.Sp +Valid \s-1ISO\s0 C and \s-1ISO\s0 \*(C+ programs should compile properly with or without +this option (though a rare few will require \fB\-ansi\fR or a +\&\fB\-std\fR option specifying the required version of \s-1ISO\s0 C). However, +without this option, certain \s-1GNU\s0 extensions and traditional C and \*(C+ +features are supported as well. With this option, they are rejected. +.Sp +\&\fB\-pedantic\fR does not cause warning messages for use of the +alternate keywords whose names begin and end with \fB_\|_\fR. Pedantic +warnings are also disabled in the expression that follows +\&\f(CW\*(C`_\|_extension_\|_\*(C'\fR. However, only system header files should use +these escape routes; application programs should avoid them. +.Sp +Some users try to use \fB\-pedantic\fR to check programs for strict \s-1ISO\s0 +C conformance. They soon find that it does not do quite what they want: +it finds some non-ISO practices, but not all\-\-\-only those for which +\&\s-1ISO\s0 C \fIrequires\fR a diagnostic, and some others for which +diagnostics have been added. +.Sp +A feature to report any failure to conform to \s-1ISO\s0 C might be useful in +some instances, but would require considerable additional work and would +be quite different from \fB\-pedantic\fR. We don't have plans to +support such a feature in the near future. +.Sp +Where the standard specified with \fB\-std\fR represents a \s-1GNU\s0 +extended dialect of C, such as \fBgnu90\fR or \fBgnu99\fR, there is a +corresponding \fIbase standard\fR, the version of \s-1ISO\s0 C on which the \s-1GNU\s0 +extended dialect is based. Warnings from \fB\-pedantic\fR are given +where they are required by the base standard. (It would not make sense +for such warnings to be given only for features not in the specified \s-1GNU\s0 +C dialect, since by definition the \s-1GNU\s0 dialects of C include all +features the compiler supports with the given option, and there would be +nothing to warn about.) +.IP "\fB\-pedantic\-errors\fR" 4 +.IX Item "-pedantic-errors" +Like \fB\-pedantic\fR, except that errors are produced rather than +warnings. +.IP "\fB\-Wall\fR" 4 +.IX Item "-Wall" +This enables all the warnings about constructions that some users +consider questionable, and that are easy to avoid (or modify to +prevent the warning), even in conjunction with macros. This also +enables some language-specific warnings described in \fB\*(C+ Dialect +Options\fR and \fBObjective-C and Objective\-\*(C+ Dialect Options\fR. +.Sp +\&\fB\-Wall\fR turns on the following warning flags: +.Sp +\&\fB\-Waddress +\&\-Warray\-bounds\fR (only with\fB \fR\fB\-O2\fR) +\&\fB\-Wc++0x\-compat +\&\-Wchar\-subscripts +\&\-Wenum\-compare\fR (in C/Objc; this is on by default in \*(C+) +\&\fB\-Wimplicit\-int\fR (C and Objective-C only) +\&\fB\-Wimplicit\-function\-declaration\fR (C and Objective-C only) +\&\fB\-Wcomment +\&\-Wformat +\&\-Wmain\fR (only for C/ObjC and unless\fB \fR\fB\-ffreestanding\fR) +\&\fB\-Wmaybe\-uninitialized +\&\-Wmissing\-braces +\&\-Wnonnull +\&\-Wparentheses +\&\-Wpointer\-sign +\&\-Wreorder +\&\-Wreturn\-type +\&\-Wripa\-opt\-mismatch +\&\-Wsequence\-point +\&\-Wsign\-compare\fR (only in \*(C+) +\&\fB\-Wstrict\-aliasing +\&\-Wstrict\-overflow=1 +\&\-Wswitch +\&\-Wtrigraphs +\&\-Wuninitialized +\&\-Wunknown\-pragmas +\&\-Wunused\-function +\&\-Wunused\-label +\&\-Wunused\-value +\&\-Wunused\-variable +\&\-Wvolatile\-register\-var\fR +.Sp +Note that some warning flags are not implied by \fB\-Wall\fR. Some of +them warn about constructions that users generally do not consider +questionable, but which occasionally you might wish to check for; +others warn about constructions that are necessary or hard to avoid in +some cases, and there is no simple way to modify the code to suppress +the warning. Some of them are enabled by \fB\-Wextra\fR but many of +them must be enabled individually. +.IP "\fB\-Wextra\fR" 4 +.IX Item "-Wextra" +This enables some extra warning flags that are not enabled by +\&\fB\-Wall\fR. (This option used to be called \fB\-W\fR. The older +name is still supported, but the newer name is more descriptive.) +.Sp +\&\fB\-Wclobbered +\&\-Wempty\-body +\&\-Wignored\-qualifiers +\&\-Wmissing\-field\-initializers +\&\-Wmissing\-parameter\-type\fR (C only) +\&\fB\-Wold\-style\-declaration\fR (C only) +\&\fB\-Woverride\-init +\&\-Wsign\-compare +\&\-Wtype\-limits +\&\-Wuninitialized +\&\-Wunused\-parameter\fR (only with\fB \fR\fB\-Wunused\fR\fB \fRor\fB \fR\fB\-Wall\fR) +\&\fB\-Wunused\-but\-set\-parameter\fR (only with\fB \fR\fB\-Wunused\fR\fB \fRor\fB \fR\fB\-Wall\fR) \fB \fR +.Sp +The option \fB\-Wextra\fR also prints warning messages for the +following cases: +.RS 4 +.IP "\(bu" 4 +A pointer is compared against integer zero with \fB<\fR, \fB<=\fR, +\&\fB>\fR, or \fB>=\fR. +.IP "\(bu" 4 +(\*(C+ only) An enumerator and a non-enumerator both appear in a +conditional expression. +.IP "\(bu" 4 +(\*(C+ only) Ambiguous virtual bases. +.IP "\(bu" 4 +(\*(C+ only) Subscripting an array which has been declared \fBregister\fR. +.IP "\(bu" 4 +(\*(C+ only) Taking the address of a variable which has been declared +\&\fBregister\fR. +.IP "\(bu" 4 +(\*(C+ only) A base class is not initialized in a derived class' copy +constructor. +.RE +.RS 4 +.RE +.IP "\fB\-Wchar\-subscripts\fR" 4 +.IX Item "-Wchar-subscripts" +Warn if an array subscript has type \f(CW\*(C`char\*(C'\fR. This is a common cause +of error, as programmers often forget that this type is signed on some +machines. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wcomment\fR" 4 +.IX Item "-Wcomment" +Warn whenever a comment-start sequence \fB/*\fR appears in a \fB/*\fR +comment, or whenever a Backslash-Newline appears in a \fB//\fR comment. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wno\-cpp\fR" 4 +.IX Item "-Wno-cpp" +(C, Objective-C, \*(C+, Objective\-\*(C+ and Fortran only) +.Sp +Suppress warning messages emitted by \f(CW\*(C`#warning\*(C'\fR directives. +.IP "\fB\-Wdouble\-promotion\fR (C, \*(C+, Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wdouble-promotion (C, , Objective-C and Objective- only)" +Give a warning when a value of type \f(CW\*(C`float\*(C'\fR is implicitly +promoted to \f(CW\*(C`double\*(C'\fR. CPUs with a 32\-bit \*(L"single-precision\*(R" +floating-point unit implement \f(CW\*(C`float\*(C'\fR in hardware, but emulate +\&\f(CW\*(C`double\*(C'\fR in software. On such a machine, doing computations +using \f(CW\*(C`double\*(C'\fR values is much more expensive because of the +overhead required for software emulation. +.Sp +It is easy to accidentally do computations with \f(CW\*(C`double\*(C'\fR because +floating-point literals are implicitly of type \f(CW\*(C`double\*(C'\fR. For +example, in: +.Sp +.Vb 4 +\& float area(float radius) +\& { +\& return 3.14159 * radius * radius; +\& } +.Ve +.Sp +the compiler will perform the entire computation with \f(CW\*(C`double\*(C'\fR +because the floating-point literal is a \f(CW\*(C`double\*(C'\fR. +.IP "\fB\-Wformat\fR" 4 +.IX Item "-Wformat" +Check calls to \f(CW\*(C`printf\*(C'\fR and \f(CW\*(C`scanf\*(C'\fR, etc., to make sure that +the arguments supplied have types appropriate to the format string +specified, and that the conversions specified in the format string make +sense. This includes standard functions, and others specified by format +attributes, in the \f(CW\*(C`printf\*(C'\fR, +\&\f(CW\*(C`scanf\*(C'\fR, \f(CW\*(C`strftime\*(C'\fR and \f(CW\*(C`strfmon\*(C'\fR (an X/Open extension, +not in the C standard) families (or other target-specific families). +Which functions are checked without format attributes having been +specified depends on the standard version selected, and such checks of +functions without the attribute specified are disabled by +\&\fB\-ffreestanding\fR or \fB\-fno\-builtin\fR. +.Sp +The formats are checked against the format features supported by \s-1GNU\s0 +libc version 2.2. These include all \s-1ISO\s0 C90 and C99 features, as well +as features from the Single Unix Specification and some \s-1BSD\s0 and \s-1GNU\s0 +extensions. Other library implementations may not support all these +features; \s-1GCC\s0 does not support warning about features that go beyond a +particular library's limitations. However, if \fB\-pedantic\fR is used +with \fB\-Wformat\fR, warnings will be given about format features not +in the selected standard version (but not for \f(CW\*(C`strfmon\*(C'\fR formats, +since those are not in any version of the C standard). +.Sp +Since \fB\-Wformat\fR also checks for null format arguments for +several functions, \fB\-Wformat\fR also implies \fB\-Wnonnull\fR. +.Sp +\&\fB\-Wformat\fR is included in \fB\-Wall\fR. For more control over some +aspects of format checking, the options \fB\-Wformat\-y2k\fR, +\&\fB\-Wno\-format\-extra\-args\fR, \fB\-Wno\-format\-zero\-length\fR, +\&\fB\-Wformat\-nonliteral\fR, \fB\-Wformat\-security\fR, and +\&\fB\-Wformat=2\fR are available, but are not included in \fB\-Wall\fR. +.IP "\fB\-Wformat\-y2k\fR" 4 +.IX Item "-Wformat-y2k" +If \fB\-Wformat\fR is specified, also warn about \f(CW\*(C`strftime\*(C'\fR +formats which may yield only a two-digit year. +.IP "\fB\-Wno\-format\-contains\-nul\fR" 4 +.IX Item "-Wno-format-contains-nul" +If \fB\-Wformat\fR is specified, do not warn about format strings that +contain \s-1NUL\s0 bytes. +.IP "\fB\-Wno\-format\-extra\-args\fR" 4 +.IX Item "-Wno-format-extra-args" +If \fB\-Wformat\fR is specified, do not warn about excess arguments to a +\&\f(CW\*(C`printf\*(C'\fR or \f(CW\*(C`scanf\*(C'\fR format function. The C standard specifies +that such arguments are ignored. +.Sp +Where the unused arguments lie between used arguments that are +specified with \fB$\fR operand number specifications, normally +warnings are still given, since the implementation could not know what +type to pass to \f(CW\*(C`va_arg\*(C'\fR to skip the unused arguments. However, +in the case of \f(CW\*(C`scanf\*(C'\fR formats, this option will suppress the +warning if the unused arguments are all pointers, since the Single +Unix Specification says that such unused arguments are allowed. +.IP "\fB\-Wno\-format\-zero\-length\fR (C and Objective-C only)" 4 +.IX Item "-Wno-format-zero-length (C and Objective-C only)" +If \fB\-Wformat\fR is specified, do not warn about zero-length formats. +The C standard specifies that zero-length formats are allowed. +.IP "\fB\-Wformat\-nonliteral\fR" 4 +.IX Item "-Wformat-nonliteral" +If \fB\-Wformat\fR is specified, also warn if the format string is not a +string literal and so cannot be checked, unless the format function +takes its format arguments as a \f(CW\*(C`va_list\*(C'\fR. +.IP "\fB\-Wformat\-security\fR" 4 +.IX Item "-Wformat-security" +If \fB\-Wformat\fR is specified, also warn about uses of format +functions that represent possible security problems. At present, this +warns about calls to \f(CW\*(C`printf\*(C'\fR and \f(CW\*(C`scanf\*(C'\fR functions where the +format string is not a string literal and there are no format arguments, +as in \f(CW\*(C`printf (foo);\*(C'\fR. This may be a security hole if the format +string came from untrusted input and contains \fB\f(CB%n\fB\fR. (This is +currently a subset of what \fB\-Wformat\-nonliteral\fR warns about, but +in future warnings may be added to \fB\-Wformat\-security\fR that are not +included in \fB\-Wformat\-nonliteral\fR.) +.IP "\fB\-Wformat=2\fR" 4 +.IX Item "-Wformat=2" +Enable \fB\-Wformat\fR plus format checks not included in +\&\fB\-Wformat\fR. Currently equivalent to \fB\-Wformat +\&\-Wformat\-nonliteral \-Wformat\-security \-Wformat\-y2k\fR. +.IP "\fB\-Wnonnull\fR (C, \*(C+, Objective-C, and Objective\-\*(C+ only)" 4 +.IX Item "-Wnonnull (C, , Objective-C, and Objective- only)" +Warn about passing a null pointer for arguments marked as +requiring a non-null value by the \f(CW\*(C`nonnull\*(C'\fR function attribute. +.Sp +\&\fB\-Wnonnull\fR is included in \fB\-Wall\fR and \fB\-Wformat\fR. It +can be disabled with the \fB\-Wno\-nonnull\fR option. +.IP "\fB\-Winit\-self\fR (C, \*(C+, Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Winit-self (C, , Objective-C and Objective- only)" +Warn about uninitialized variables which are initialized with themselves. +Note this option can only be used with the \fB\-Wuninitialized\fR option. +.Sp +For example, \s-1GCC\s0 will warn about \f(CW\*(C`i\*(C'\fR being uninitialized in the +following snippet only when \fB\-Winit\-self\fR has been specified: +.Sp +.Vb 5 +\& int f() +\& { +\& int i = i; +\& return i; +\& } +.Ve +.IP "\fB\-Wimplicit\-int\fR (C and Objective-C only)" 4 +.IX Item "-Wimplicit-int (C and Objective-C only)" +Warn when a declaration does not specify a type. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wimplicit\-function\-declaration\fR (C and Objective-C only)" 4 +.IX Item "-Wimplicit-function-declaration (C and Objective-C only)" +Give a warning whenever a function is used before being declared. In +C99 mode (\fB\-std=c99\fR or \fB\-std=gnu99\fR), this warning is +enabled by default and it is made into an error by +\&\fB\-pedantic\-errors\fR. This warning is also enabled by +\&\fB\-Wall\fR. +.IP "\fB\-Wimplicit\fR (C and Objective-C only)" 4 +.IX Item "-Wimplicit (C and Objective-C only)" +Same as \fB\-Wimplicit\-int\fR and \fB\-Wimplicit\-function\-declaration\fR. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wignored\-qualifiers\fR (C and \*(C+ only)" 4 +.IX Item "-Wignored-qualifiers (C and only)" +Warn if the return type of a function has a type qualifier +such as \f(CW\*(C`const\*(C'\fR. For \s-1ISO\s0 C such a type qualifier has no effect, +since the value returned by a function is not an lvalue. +For \*(C+, the warning is only emitted for scalar types or \f(CW\*(C`void\*(C'\fR. +\&\s-1ISO\s0 C prohibits qualified \f(CW\*(C`void\*(C'\fR return types on function +definitions, so such return types always receive a warning +even without this option. +.Sp +This warning is also enabled by \fB\-Wextra\fR. +.IP "\fB\-Wmain\fR" 4 +.IX Item "-Wmain" +Warn if the type of \fBmain\fR is suspicious. \fBmain\fR should be +a function with external linkage, returning int, taking either zero +arguments, two, or three arguments of appropriate types. This warning +is enabled by default in \*(C+ and is enabled by either \fB\-Wall\fR +or \fB\-pedantic\fR. +.IP "\fB\-Wmissing\-braces\fR" 4 +.IX Item "-Wmissing-braces" +Warn if an aggregate or union initializer is not fully bracketed. In +the following example, the initializer for \fBa\fR is not fully +bracketed, but that for \fBb\fR is fully bracketed. +.Sp +.Vb 2 +\& int a[2][2] = { 0, 1, 2, 3 }; +\& int b[2][2] = { { 0, 1 }, { 2, 3 } }; +.Ve +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wmissing\-include\-dirs\fR (C, \*(C+, Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wmissing-include-dirs (C, , Objective-C and Objective- only)" +Warn if a user-supplied include directory does not exist. +.IP "\fB\-Wparentheses\fR" 4 +.IX Item "-Wparentheses" +Warn if parentheses are omitted in certain contexts, such +as when there is an assignment in a context where a truth value +is expected, or when operators are nested whose precedence people +often get confused about. +.Sp +Also warn if a comparison like \fBx<=y<=z\fR appears; this is +equivalent to \fB(x<=y ? 1 : 0) <= z\fR, which is a different +interpretation from that of ordinary mathematical notation. +.Sp +Also warn about constructions where there may be confusion to which +\&\f(CW\*(C`if\*(C'\fR statement an \f(CW\*(C`else\*(C'\fR branch belongs. Here is an example of +such a case: +.Sp +.Vb 7 +\& { +\& if (a) +\& if (b) +\& foo (); +\& else +\& bar (); +\& } +.Ve +.Sp +In C/\*(C+, every \f(CW\*(C`else\*(C'\fR branch belongs to the innermost possible +\&\f(CW\*(C`if\*(C'\fR statement, which in this example is \f(CW\*(C`if (b)\*(C'\fR. This is +often not what the programmer expected, as illustrated in the above +example by indentation the programmer chose. When there is the +potential for this confusion, \s-1GCC\s0 will issue a warning when this flag +is specified. To eliminate the warning, add explicit braces around +the innermost \f(CW\*(C`if\*(C'\fR statement so there is no way the \f(CW\*(C`else\*(C'\fR +could belong to the enclosing \f(CW\*(C`if\*(C'\fR. The resulting code would +look like this: +.Sp +.Vb 9 +\& { +\& if (a) +\& { +\& if (b) +\& foo (); +\& else +\& bar (); +\& } +\& } +.Ve +.Sp +Also warn for dangerous uses of the +?: with omitted middle operand \s-1GNU\s0 extension. When the condition +in the ?: operator is a boolean expression the omitted value will +be always 1. Often the user expects it to be a value computed +inside the conditional expression instead. +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wsequence\-point\fR" 4 +.IX Item "-Wsequence-point" +Warn about code that may have undefined semantics because of violations +of sequence point rules in the C and \*(C+ standards. +.Sp +The C and \*(C+ standards defines the order in which expressions in a C/\*(C+ +program are evaluated in terms of \fIsequence points\fR, which represent +a partial ordering between the execution of parts of the program: those +executed before the sequence point, and those executed after it. These +occur after the evaluation of a full expression (one which is not part +of a larger expression), after the evaluation of the first operand of a +\&\f(CW\*(C`&&\*(C'\fR, \f(CW\*(C`||\*(C'\fR, \f(CW\*(C`? :\*(C'\fR or \f(CW\*(C`,\*(C'\fR (comma) operator, before a +function is called (but after the evaluation of its arguments and the +expression denoting the called function), and in certain other places. +Other than as expressed by the sequence point rules, the order of +evaluation of subexpressions of an expression is not specified. All +these rules describe only a partial order rather than a total order, +since, for example, if two functions are called within one expression +with no sequence point between them, the order in which the functions +are called is not specified. However, the standards committee have +ruled that function calls do not overlap. +.Sp +It is not specified when between sequence points modifications to the +values of objects take effect. Programs whose behavior depends on this +have undefined behavior; the C and \*(C+ standards specify that \*(L"Between +the previous and next sequence point an object shall have its stored +value modified at most once by the evaluation of an expression. +Furthermore, the prior value shall be read only to determine the value +to be stored.\*(R". If a program breaks these rules, the results on any +particular implementation are entirely unpredictable. +.Sp +Examples of code with undefined behavior are \f(CW\*(C`a = a++;\*(C'\fR, \f(CW\*(C`a[n] += b[n++]\*(C'\fR and \f(CW\*(C`a[i++] = i;\*(C'\fR. Some more complicated cases are not +diagnosed by this option, and it may give an occasional false positive +result, but in general it has been found fairly effective at detecting +this sort of problem in programs. +.Sp +The standard is worded confusingly, therefore there is some debate +over the precise meaning of the sequence point rules in subtle cases. +Links to discussions of the problem, including proposed formal +definitions, may be found on the \s-1GCC\s0 readings page, at +<\fBhttp://gcc.gnu.org/readings.html\fR>. +.Sp +This warning is enabled by \fB\-Wall\fR for C and \*(C+. +.IP "\fB\-Wself\-assign\fR" 4 +.IX Item "-Wself-assign" +Warn about self-assignment and self-initialization. This warning is intended +for detecting accidental self-assignment due to typos, and therefore does +not warn on a statement that is semantically a self-assignment after +constant folding. Here is an example of what will trigger a self-assign +warning and what will not: +.Sp +.Vb 6 +\& void func() +\& { +\& int i = 2; +\& int x = x; /* warn */ +\& float f = 5.0; +\& double a[3]; +\& +\& i = i + 0; /* not warn */ +\& f = f / 1; /* not warn */ +\& a[1] = a[1]; /* warn */ +\& i += 0; /* not warn */ +\& } +.Ve +.Sp +In \*(C+ it will not warn on self-assignment of non-POD variables unless +\&\fB\-Wself\-assign\-non\-pod\fR is also enabled. +.IP "\fB\-Wself\-assign\-non\-pod\fR" 4 +.IX Item "-Wself-assign-non-pod" +Warn about self-assignment of non-POD variables. This is a \*(C+\-specific +warning and only effective when \fB\-Wself\-assign\fR is enabled. +.Sp +There are cases where self-assignment might be intentional. For example, +a \*(C+ programmer might write code to test whether an overloaded +\&\f(CW\*(C`operator=\*(C'\fR works when the same object is assigned to itself. +One way to work around the self-assign warning in such cases when this flag +is enabled is using the functional form \f(CW\*(C`object.operator=(object)\*(C'\fR +instead of the assignment form \f(CW\*(C`object = object\*(C'\fR, as shown in the +following example. +.Sp +.Vb 3 +\& void test_func() +\& { +\& MyType t; +\& +\& t.operator=(t); // not warn +\& t = t; // warn +\& } +.Ve +.IP "\fB\-Wreturn\-type\fR" 4 +.IX Item "-Wreturn-type" +Warn whenever a function is defined with a return-type that defaults +to \f(CW\*(C`int\*(C'\fR. Also warn about any \f(CW\*(C`return\*(C'\fR statement with no +return-value in a function whose return-type is not \f(CW\*(C`void\*(C'\fR +(falling off the end of the function body is considered returning +without a value), and about a \f(CW\*(C`return\*(C'\fR statement with an +expression in a function whose return-type is \f(CW\*(C`void\*(C'\fR. +.Sp +For \*(C+, a function without return type always produces a diagnostic +message, even when \fB\-Wno\-return\-type\fR is specified. The only +exceptions are \fBmain\fR and functions defined in system headers. +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wripa\-opt\-mismatch\fR" 4 +.IX Item "-Wripa-opt-mismatch" +When doing an \s-1FDO\s0 build with \fB\-fprofile\-use\fR and \fB\-fripa\fR, +warn if importing an axuiliary module that was built with a different +\&\s-1GCC\s0 command line during the profile-generate phase than the primary +module. +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wswitch\fR" 4 +.IX Item "-Wswitch" +Warn whenever a \f(CW\*(C`switch\*(C'\fR statement has an index of enumerated type +and lacks a \f(CW\*(C`case\*(C'\fR for one or more of the named codes of that +enumeration. (The presence of a \f(CW\*(C`default\*(C'\fR label prevents this +warning.) \f(CW\*(C`case\*(C'\fR labels outside the enumeration range also +provoke warnings when this option is used (even if there is a +\&\f(CW\*(C`default\*(C'\fR label). +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wswitch\-default\fR" 4 +.IX Item "-Wswitch-default" +Warn whenever a \f(CW\*(C`switch\*(C'\fR statement does not have a \f(CW\*(C`default\*(C'\fR +case. +.IP "\fB\-Wswitch\-enum\fR" 4 +.IX Item "-Wswitch-enum" +Warn whenever a \f(CW\*(C`switch\*(C'\fR statement has an index of enumerated type +and lacks a \f(CW\*(C`case\*(C'\fR for one or more of the named codes of that +enumeration. \f(CW\*(C`case\*(C'\fR labels outside the enumeration range also +provoke warnings when this option is used. The only difference +between \fB\-Wswitch\fR and this option is that this option gives a +warning about an omitted enumeration code even if there is a +\&\f(CW\*(C`default\*(C'\fR label. +.IP "\fB\-Wsync\-nand\fR (C and \*(C+ only)" 4 +.IX Item "-Wsync-nand (C and only)" +Warn when \f(CW\*(C`_\|_sync_fetch_and_nand\*(C'\fR and \f(CW\*(C`_\|_sync_nand_and_fetch\*(C'\fR +built-in functions are used. These functions changed semantics in \s-1GCC\s0 4.4. +.IP "\fB\-Wthread\-safety\fR" 4 +.IX Item "-Wthread-safety" +Warn about potential thread safety issues when the code is annotated with +thread safety attributes. +.IP "\fBWthread-unguarded-var\fR" 4 +.IX Item "Wthread-unguarded-var" +Warn about shared variables not properly protected by locks specified in the +attributes. This flag is effective only with \fB\-Wthread\-safety\fR and +enabled by default. +.IP "\fBWthread-unguarded-func\fR" 4 +.IX Item "Wthread-unguarded-func" +Warn about function calls not properly protected by locks specified in the +attributes. This flag is effective only with \fB\-Wthread\-safety\fR and +enabled by default. +.IP "\fBWthread-mismatched-lock-order\fR" 4 +.IX Item "Wthread-mismatched-lock-order" +Warn about lock acquisition order inconsistent with what specified in the +attributes. This flag is effective only with \fB\-Wthread\-safety\fR and +enabled by default. +.IP "\fBWthread-mismatched-lock-acq-rel\fR" 4 +.IX Item "Wthread-mismatched-lock-acq-rel" +Warn about mismatched lock acquisition and release. This flag is effective only +with \fB\-Wthread\-safety\fR and enabled by default. +.IP "\fBWthread-reentrant-lock\fR" 4 +.IX Item "Wthread-reentrant-lock" +Warn about a lock being acquired recursively. This flag is effective only +with \fB\-Wthread\-safety\fR and enabled by default. +.IP "\fBWthread-unsupported-lock-name\fR" 4 +.IX Item "Wthread-unsupported-lock-name" +Warn about uses of unsupported lock names in attributes. This flag is effective +only with \fB\-Wthread\-safety\fR and disabled by default. +.IP "\fBWthread-attr-bind-param\fR" 4 +.IX Item "Wthread-attr-bind-param" +Make the thread safety analysis try to bind the function parameters used in +the attributes. This flag is effective only with \fB\-Wthread\-safety\fR +and enabled by default. +.IP "\fB\-Wtrigraphs\fR" 4 +.IX Item "-Wtrigraphs" +Warn if any trigraphs are encountered that might change the meaning of +the program (trigraphs within comments are not warned about). +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wunused\-but\-set\-parameter\fR" 4 +.IX Item "-Wunused-but-set-parameter" +Warn whenever a function parameter is assigned to, but otherwise unused +(aside from its declaration). +.Sp +To suppress this warning use the \fBunused\fR attribute. +.Sp +This warning is also enabled by \fB\-Wunused\fR together with +\&\fB\-Wextra\fR. +.IP "\fB\-Wunused\-but\-set\-variable\fR" 4 +.IX Item "-Wunused-but-set-variable" +Warn whenever a local variable is assigned to, but otherwise unused +(aside from its declaration). +This warning is enabled by \fB\-Wall\fR. +.Sp +To suppress this warning use the \fBunused\fR attribute. +.Sp +This warning is also enabled by \fB\-Wunused\fR, which is enabled +by \fB\-Wall\fR. +.IP "\fB\-Wunused\-function\fR" 4 +.IX Item "-Wunused-function" +Warn whenever a static function is declared but not defined or a +non-inline static function is unused. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wunused\-label\fR" 4 +.IX Item "-Wunused-label" +Warn whenever a label is declared but not used. +This warning is enabled by \fB\-Wall\fR. +.Sp +To suppress this warning use the \fBunused\fR attribute. +.IP "\fB\-Wunused\-parameter\fR" 4 +.IX Item "-Wunused-parameter" +Warn whenever a function parameter is unused aside from its declaration. +.Sp +To suppress this warning use the \fBunused\fR attribute. +.IP "\fB\-Wno\-unused\-result\fR" 4 +.IX Item "-Wno-unused-result" +Do not warn if a caller of a function marked with attribute +\&\f(CW\*(C`warn_unused_result\*(C'\fR does not use +its return value. The default is \fB\-Wunused\-result\fR. +.IP "\fB\-Wunused\-variable\fR" 4 +.IX Item "-Wunused-variable" +Warn whenever a local variable or non-constant static variable is unused +aside from its declaration. +This warning is enabled by \fB\-Wall\fR. +.Sp +To suppress this warning use the \fBunused\fR attribute. +.Sp +Note that a classic way to avoid \fB\-Wunused\-variable\fR warning is +using \f(CW\*(C`x = x\*(C'\fR, but that does not work with \fB\-Wself\-assign\fR. +Use \f(CW\*(C`(void) x\*(C'\fR or \f(CW\*(C`static_cast<void>(x)\*(C'\fR instead. +.IP "\fB\-Wunused\-value\fR" 4 +.IX Item "-Wunused-value" +Warn whenever a statement computes a result that is explicitly not +used. To suppress this warning cast the unused expression to +\&\fBvoid\fR. This includes an expression-statement or the left-hand +side of a comma expression that contains no side effects. For example, +an expression such as \fBx[i,j]\fR will cause a warning, while +\&\fBx[(void)i,j]\fR will not. +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wunused\fR" 4 +.IX Item "-Wunused" +All the above \fB\-Wunused\fR options combined. +.Sp +In order to get a warning about an unused function parameter, you must +either specify \fB\-Wextra \-Wunused\fR (note that \fB\-Wall\fR implies +\&\fB\-Wunused\fR), or separately specify \fB\-Wunused\-parameter\fR. +.IP "\fB\-Wuninitialized\fR" 4 +.IX Item "-Wuninitialized" +Warn if an automatic variable is used without first being initialized +or if a variable may be clobbered by a \f(CW\*(C`setjmp\*(C'\fR call. In \*(C+, +warn if a non-static reference or non-static \fBconst\fR member +appears in a class without constructors. +.Sp +If you want to warn about code which uses the uninitialized value of the +variable in its own initializer, use the \fB\-Winit\-self\fR option. +.Sp +These warnings occur for individual uninitialized or clobbered +elements of structure, union or array variables as well as for +variables which are uninitialized or clobbered as a whole. They do +not occur for variables or elements declared \f(CW\*(C`volatile\*(C'\fR. Because +these warnings depend on optimization, the exact variables or elements +for which there are warnings will depend on the precise optimization +options and version of \s-1GCC\s0 used. +.Sp +Note that there may be no warning about a variable that is used only +to compute a value that itself is never used, because such +computations may be deleted by data flow analysis before the warnings +are printed. +.IP "\fB\-Wmaybe\-uninitialized\fR" 4 +.IX Item "-Wmaybe-uninitialized" +For an automatic variable, if there exists a path from the function +entry to a use of the variable that is initialized, but there exist +some other paths the variable is not initialized, the compiler will +emit a warning if it can not prove the uninitialized paths do not +happen at runtime. These warnings are made optional because \s-1GCC\s0 is +not smart enough to see all the reasons why the code might be correct +despite appearing to have an error. Here is one example of how +this can happen: +.Sp +.Vb 12 +\& { +\& int x; +\& switch (y) +\& { +\& case 1: x = 1; +\& break; +\& case 2: x = 4; +\& break; +\& case 3: x = 5; +\& } +\& foo (x); +\& } +.Ve +.Sp +If the value of \f(CW\*(C`y\*(C'\fR is always 1, 2 or 3, then \f(CW\*(C`x\*(C'\fR is +always initialized, but \s-1GCC\s0 doesn't know this. To suppress the +warning, the user needs to provide a default case with \fIassert\fR\|(0) or +similar code. +.Sp +This option also warns when a non-volatile automatic variable might be +changed by a call to \f(CW\*(C`longjmp\*(C'\fR. These warnings as well are possible +only in optimizing compilation. +.Sp +The compiler sees only the calls to \f(CW\*(C`setjmp\*(C'\fR. It cannot know +where \f(CW\*(C`longjmp\*(C'\fR will be called; in fact, a signal handler could +call it at any point in the code. As a result, you may get a warning +even when there is in fact no problem because \f(CW\*(C`longjmp\*(C'\fR cannot +in fact be called at the place which would cause a problem. +.Sp +Some spurious warnings can be avoided if you declare all the functions +you use that never return as \f(CW\*(C`noreturn\*(C'\fR. +.Sp +This warning is enabled by \fB\-Wall\fR or \fB\-Wextra\fR. +.IP "\fB\-Wunknown\-pragmas\fR" 4 +.IX Item "-Wunknown-pragmas" +Warn when a #pragma directive is encountered which is not understood by +\&\s-1GCC\s0. If this command line option is used, warnings will even be issued +for unknown pragmas in system header files. This is not the case if +the warnings were only enabled by the \fB\-Wall\fR command line option. +.IP "\fB\-Wno\-pragmas\fR" 4 +.IX Item "-Wno-pragmas" +Do not warn about misuses of pragmas, such as incorrect parameters, +invalid syntax, or conflicts between pragmas. See also +\&\fB\-Wunknown\-pragmas\fR. +.IP "\fB\-Wstrict\-aliasing\fR" 4 +.IX Item "-Wstrict-aliasing" +This option is only active when \fB\-fstrict\-aliasing\fR is active. +It warns about code which might break the strict aliasing rules that the +compiler is using for optimization. The warning does not catch all +cases, but does attempt to catch the more common pitfalls. It is +included in \fB\-Wall\fR. +It is equivalent to \fB\-Wstrict\-aliasing=3\fR +.IP "\fB\-Wstrict\-aliasing=n\fR" 4 +.IX Item "-Wstrict-aliasing=n" +This option is only active when \fB\-fstrict\-aliasing\fR is active. +It warns about code which might break the strict aliasing rules that the +compiler is using for optimization. +Higher levels correspond to higher accuracy (fewer false positives). +Higher levels also correspond to more effort, similar to the way \-O works. +\&\fB\-Wstrict\-aliasing\fR is equivalent to \fB\-Wstrict\-aliasing=n\fR, +with n=3. +.Sp +Level 1: Most aggressive, quick, least accurate. +Possibly useful when higher levels +do not warn but \-fstrict\-aliasing still breaks the code, as it has very few +false negatives. However, it has many false positives. +Warns for all pointer conversions between possibly incompatible types, +even if never dereferenced. Runs in the frontend only. +.Sp +Level 2: Aggressive, quick, not too precise. +May still have many false positives (not as many as level 1 though), +and few false negatives (but possibly more than level 1). +Unlike level 1, it only warns when an address is taken. Warns about +incomplete types. Runs in the frontend only. +.Sp +Level 3 (default for \fB\-Wstrict\-aliasing\fR): +Should have very few false positives and few false +negatives. Slightly slower than levels 1 or 2 when optimization is enabled. +Takes care of the common pun+dereference pattern in the frontend: +\&\f(CW\*(C`*(int*)&some_float\*(C'\fR. +If optimization is enabled, it also runs in the backend, where it deals +with multiple statement cases using flow-sensitive points-to information. +Only warns when the converted pointer is dereferenced. +Does not warn about incomplete types. +.IP "\fB\-Wstrict\-overflow\fR" 4 +.IX Item "-Wstrict-overflow" +.PD 0 +.IP "\fB\-Wstrict\-overflow=\fR\fIn\fR" 4 +.IX Item "-Wstrict-overflow=n" +.PD +This option is only active when \fB\-fstrict\-overflow\fR is active. +It warns about cases where the compiler optimizes based on the +assumption that signed overflow does not occur. Note that it does not +warn about all cases where the code might overflow: it only warns +about cases where the compiler implements some optimization. Thus +this warning depends on the optimization level. +.Sp +An optimization which assumes that signed overflow does not occur is +perfectly safe if the values of the variables involved are such that +overflow never does, in fact, occur. Therefore this warning can +easily give a false positive: a warning about code which is not +actually a problem. To help focus on important issues, several +warning levels are defined. No warnings are issued for the use of +undefined signed overflow when estimating how many iterations a loop +will require, in particular when determining whether a loop will be +executed at all. +.RS 4 +.IP "\fB\-Wstrict\-overflow=1\fR" 4 +.IX Item "-Wstrict-overflow=1" +Warn about cases which are both questionable and easy to avoid. For +example: \f(CW\*(C`x + 1 > x\*(C'\fR; with \fB\-fstrict\-overflow\fR, the +compiler will simplify this to \f(CW1\fR. This level of +\&\fB\-Wstrict\-overflow\fR is enabled by \fB\-Wall\fR; higher levels +are not, and must be explicitly requested. +.IP "\fB\-Wstrict\-overflow=2\fR" 4 +.IX Item "-Wstrict-overflow=2" +Also warn about other cases where a comparison is simplified to a +constant. For example: \f(CW\*(C`abs (x) >= 0\*(C'\fR. This can only be +simplified when \fB\-fstrict\-overflow\fR is in effect, because +\&\f(CW\*(C`abs (INT_MIN)\*(C'\fR overflows to \f(CW\*(C`INT_MIN\*(C'\fR, which is less than +zero. \fB\-Wstrict\-overflow\fR (with no level) is the same as +\&\fB\-Wstrict\-overflow=2\fR. +.IP "\fB\-Wstrict\-overflow=3\fR" 4 +.IX Item "-Wstrict-overflow=3" +Also warn about other cases where a comparison is simplified. For +example: \f(CW\*(C`x + 1 > 1\*(C'\fR will be simplified to \f(CW\*(C`x > 0\*(C'\fR. +.IP "\fB\-Wstrict\-overflow=4\fR" 4 +.IX Item "-Wstrict-overflow=4" +Also warn about other simplifications not covered by the above cases. +For example: \f(CW\*(C`(x * 10) / 5\*(C'\fR will be simplified to \f(CW\*(C`x * 2\*(C'\fR. +.IP "\fB\-Wstrict\-overflow=5\fR" 4 +.IX Item "-Wstrict-overflow=5" +Also warn about cases where the compiler reduces the magnitude of a +constant involved in a comparison. For example: \f(CW\*(C`x + 2 > y\*(C'\fR will +be simplified to \f(CW\*(C`x + 1 >= y\*(C'\fR. This is reported only at the +highest warning level because this simplification applies to many +comparisons, so this warning level will give a very large number of +false positives. +.RE +.RS 4 +.RE +.IP "\fB\-Wsuggest\-attribute=\fR[\fBpure\fR|\fBconst\fR|\fBnoreturn\fR]" 4 +.IX Item "-Wsuggest-attribute=[pure|const|noreturn]" +Warn for cases where adding an attribute may be beneficial. The +attributes currently supported are listed below. +.RS 4 +.IP "\fB\-Wsuggest\-attribute=pure\fR" 4 +.IX Item "-Wsuggest-attribute=pure" +.PD 0 +.IP "\fB\-Wsuggest\-attribute=const\fR" 4 +.IX Item "-Wsuggest-attribute=const" +.IP "\fB\-Wsuggest\-attribute=noreturn\fR" 4 +.IX Item "-Wsuggest-attribute=noreturn" +.PD +Warn about functions which might be candidates for attributes +\&\f(CW\*(C`pure\*(C'\fR, \f(CW\*(C`const\*(C'\fR or \f(CW\*(C`noreturn\*(C'\fR. The compiler only warns for +functions visible in other compilation units or (in the case of \f(CW\*(C`pure\*(C'\fR and +\&\f(CW\*(C`const\*(C'\fR) if it cannot prove that the function returns normally. A function +returns normally if it doesn't contain an infinite loop nor returns abnormally +by throwing, calling \f(CW\*(C`abort()\*(C'\fR or trapping. This analysis requires option +\&\fB\-fipa\-pure\-const\fR, which is enabled by default at \fB\-O\fR and +higher. Higher optimization levels improve the accuracy of the analysis. +.RE +.RS 4 +.RE +.IP "\fB\-Warray\-bounds\fR" 4 +.IX Item "-Warray-bounds" +This option is only active when \fB\-ftree\-vrp\fR is active +(default for \fB\-O2\fR and above). It warns about subscripts to arrays +that are always out of bounds. This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wno\-div\-by\-zero\fR" 4 +.IX Item "-Wno-div-by-zero" +Do not warn about compile-time integer division by zero. Floating point +division by zero is not warned about, as it can be a legitimate way of +obtaining infinities and NaNs. +.IP "\fB\-Wsystem\-headers\fR" 4 +.IX Item "-Wsystem-headers" +Print warning messages for constructs found in system header files. +Warnings from system headers are normally suppressed, on the assumption +that they usually do not indicate real problems and would only make the +compiler output harder to read. Using this command line option tells +\&\s-1GCC\s0 to emit warnings from system headers as if they occurred in user +code. However, note that using \fB\-Wall\fR in conjunction with this +option will \fInot\fR warn about unknown pragmas in system +headers\-\-\-for that, \fB\-Wunknown\-pragmas\fR must also be used. +.IP "\fB\-Wtrampolines\fR" 4 +.IX Item "-Wtrampolines" +.Vb 1 +\& Warn about trampolines generated for pointers to nested functions. +\& +\& A trampoline is a small piece of data or code that is created at run +\& time on the stack when the address of a nested function is taken, and +\& is used to call the nested function indirectly. For some targets, it +\& is made up of data only and thus requires no special treatment. But, +\& for most targets, it is made up of code and thus requires the stack +\& to be made executable in order for the program to work properly. +.Ve +.IP "\fB\-Wfloat\-equal\fR" 4 +.IX Item "-Wfloat-equal" +Warn if floating point values are used in equality comparisons. +.Sp +The idea behind this is that sometimes it is convenient (for the +programmer) to consider floating-point values as approximations to +infinitely precise real numbers. If you are doing this, then you need +to compute (by analyzing the code, or in some other way) the maximum or +likely maximum error that the computation introduces, and allow for it +when performing comparisons (and when producing output, but that's a +different problem). In particular, instead of testing for equality, you +would check to see whether the two values have ranges that overlap; and +this is done with the relational operators, so equality comparisons are +probably mistaken. +.IP "\fB\-Wtraditional\fR (C and Objective-C only)" 4 +.IX Item "-Wtraditional (C and Objective-C only)" +Warn about certain constructs that behave differently in traditional and +\&\s-1ISO\s0 C. Also warn about \s-1ISO\s0 C constructs that have no traditional C +equivalent, and/or problematic constructs which should be avoided. +.RS 4 +.IP "\(bu" 4 +Macro parameters that appear within string literals in the macro body. +In traditional C macro replacement takes place within string literals, +but does not in \s-1ISO\s0 C. +.IP "\(bu" 4 +In traditional C, some preprocessor directives did not exist. +Traditional preprocessors would only consider a line to be a directive +if the \fB#\fR appeared in column 1 on the line. Therefore +\&\fB\-Wtraditional\fR warns about directives that traditional C +understands but would ignore because the \fB#\fR does not appear as the +first character on the line. It also suggests you hide directives like +\&\fB#pragma\fR not understood by traditional C by indenting them. Some +traditional implementations would not recognize \fB#elif\fR, so it +suggests avoiding it altogether. +.IP "\(bu" 4 +A function-like macro that appears without arguments. +.IP "\(bu" 4 +The unary plus operator. +.IP "\(bu" 4 +The \fBU\fR integer constant suffix, or the \fBF\fR or \fBL\fR floating point +constant suffixes. (Traditional C does support the \fBL\fR suffix on integer +constants.) Note, these suffixes appear in macros defined in the system +headers of most modern systems, e.g. the \fB_MIN\fR/\fB_MAX\fR macros in \f(CW\*(C`<limits.h>\*(C'\fR. +Use of these macros in user code might normally lead to spurious +warnings, however \s-1GCC\s0's integrated preprocessor has enough context to +avoid warning in these cases. +.IP "\(bu" 4 +A function declared external in one block and then used after the end of +the block. +.IP "\(bu" 4 +A \f(CW\*(C`switch\*(C'\fR statement has an operand of type \f(CW\*(C`long\*(C'\fR. +.IP "\(bu" 4 +A non\-\f(CW\*(C`static\*(C'\fR function declaration follows a \f(CW\*(C`static\*(C'\fR one. +This construct is not accepted by some traditional C compilers. +.IP "\(bu" 4 +The \s-1ISO\s0 type of an integer constant has a different width or +signedness from its traditional type. This warning is only issued if +the base of the constant is ten. I.e. hexadecimal or octal values, which +typically represent bit patterns, are not warned about. +.IP "\(bu" 4 +Usage of \s-1ISO\s0 string concatenation is detected. +.IP "\(bu" 4 +Initialization of automatic aggregates. +.IP "\(bu" 4 +Identifier conflicts with labels. Traditional C lacks a separate +namespace for labels. +.IP "\(bu" 4 +Initialization of unions. If the initializer is zero, the warning is +omitted. This is done under the assumption that the zero initializer in +user code appears conditioned on e.g. \f(CW\*(C`_\|_STDC_\|_\*(C'\fR to avoid missing +initializer warnings and relies on default initialization to zero in the +traditional C case. +.IP "\(bu" 4 +Conversions by prototypes between fixed/floating point values and vice +versa. The absence of these prototypes when compiling with traditional +C would cause serious problems. This is a subset of the possible +conversion warnings, for the full set use \fB\-Wtraditional\-conversion\fR. +.IP "\(bu" 4 +Use of \s-1ISO\s0 C style function definitions. This warning intentionally is +\&\fInot\fR issued for prototype declarations or variadic functions +because these \s-1ISO\s0 C features will appear in your code when using +libiberty's traditional C compatibility macros, \f(CW\*(C`PARAMS\*(C'\fR and +\&\f(CW\*(C`VPARAMS\*(C'\fR. This warning is also bypassed for nested functions +because that feature is already a \s-1GCC\s0 extension and thus not relevant to +traditional C compatibility. +.RE +.RS 4 +.RE +.IP "\fB\-Wtraditional\-conversion\fR (C and Objective-C only)" 4 +.IX Item "-Wtraditional-conversion (C and Objective-C only)" +Warn if a prototype causes a type conversion that is different from what +would happen to the same argument in the absence of a prototype. This +includes conversions of fixed point to floating and vice versa, and +conversions changing the width or signedness of a fixed point argument +except when the same as the default promotion. +.IP "\fB\-Wdeclaration\-after\-statement\fR (C and Objective-C only)" 4 +.IX Item "-Wdeclaration-after-statement (C and Objective-C only)" +Warn when a declaration is found after a statement in a block. This +construct, known from \*(C+, was introduced with \s-1ISO\s0 C99 and is by default +allowed in \s-1GCC\s0. It is not supported by \s-1ISO\s0 C90 and was not supported by +\&\s-1GCC\s0 versions before \s-1GCC\s0 3.0. +.IP "\fB\-Wundef\fR" 4 +.IX Item "-Wundef" +Warn if an undefined identifier is evaluated in an \fB#if\fR directive. +.IP "\fB\-Wno\-endif\-labels\fR" 4 +.IX Item "-Wno-endif-labels" +Do not warn whenever an \fB#else\fR or an \fB#endif\fR are followed by text. +.IP "\fB\-Wshadow\fR" 4 +.IX Item "-Wshadow" +Warn whenever a local variable or type declaration shadows another variable, +parameter, type, or class member (in \*(C+), or whenever a built-in function +is shadowed. Note that in \*(C+, the compiler will not warn if a local variable +shadows a struct/class/enum, but will warn if it shadows an explicit typedef. +.IP "\fB\-Wshadow\-local\fR" 4 +.IX Item "-Wshadow-local" +Warn when a local variable shadows another local variable or parameter. +.IP "\fB\-Wshadow\-compatible\-local\fR" 4 +.IX Item "-Wshadow-compatible-local" +Warn when a local variable shadows another local variable or parameter +whose type is compatible with that of the shadowing variable. In \*(C+, +type compatibility here means the type of the shadowing variable can be +converted to that of the shadowed variable. The creation of this flag +(in addition to \fB\-Wshadow\-local\fR) is based on the idea that when +a local variable shadows another one of incompatible type, it is most +likely intentional, not a bug or typo, as shown in the following example: +.Sp +.Vb 8 +\& for (SomeIterator i = SomeObj.begin(); i != SomeObj.end(); ++i) +\& { +\& for (int i = 0; i < N; ++i) +\& { +\& ... +\& } +\& ... +\& } +.Ve +.Sp +Since the two variable \f(CW\*(C`i\*(C'\fR in the example above have incompatible types, +enabling only \fB\-Wshadow\-compatible\-local\fR will not emit a warning. +Because their types are incompatible, if a programmer accidentally uses one +in place of the other, type checking will catch that and emit an error or +warning. So not warning (about shadowing) in this case will not lead to +undetected bugs. Use of this flag instead of \fB\-Wshadow\-local\fR can +possibly reduce the number of warnings triggered by intentional shadowing. +.IP "\fB\-Wlarger\-than=\fR\fIlen\fR" 4 +.IX Item "-Wlarger-than=len" +Warn whenever an object of larger than \fIlen\fR bytes is defined. +.IP "\fB\-Wframe\-larger\-than=\fR\fIlen\fR" 4 +.IX Item "-Wframe-larger-than=len" +Warn if the size of a function frame is larger than \fIlen\fR bytes. +The computation done to determine the stack frame size is approximate +and not conservative. +The actual requirements may be somewhat greater than \fIlen\fR +even if you do not get a warning. In addition, any space allocated +via \f(CW\*(C`alloca\*(C'\fR, variable-length arrays, or related constructs +is not included by the compiler when determining +whether or not to issue a warning. +.IP "\fB\-Wunsafe\-loop\-optimizations\fR" 4 +.IX Item "-Wunsafe-loop-optimizations" +Warn if the loop cannot be optimized because the compiler could not +assume anything on the bounds of the loop indices. With +\&\fB\-funsafe\-loop\-optimizations\fR warn if the compiler made +such assumptions. +.IP "\fB\-Wno\-pedantic\-ms\-format\fR (MinGW targets only)" 4 +.IX Item "-Wno-pedantic-ms-format (MinGW targets only)" +Disables the warnings about non-ISO \f(CW\*(C`printf\*(C'\fR / \f(CW\*(C`scanf\*(C'\fR format +width specifiers \f(CW\*(C`I32\*(C'\fR, \f(CW\*(C`I64\*(C'\fR, and \f(CW\*(C`I\*(C'\fR used on Windows targets +depending on the \s-1MS\s0 runtime, when you are using the options \fB\-Wformat\fR +and \fB\-pedantic\fR without gnu-extensions. +.IP "\fB\-Wpointer\-arith\fR" 4 +.IX Item "-Wpointer-arith" +Warn about anything that depends on the \*(L"size of\*(R" a function type or +of \f(CW\*(C`void\*(C'\fR. \s-1GNU\s0 C assigns these types a size of 1, for +convenience in calculations with \f(CW\*(C`void *\*(C'\fR pointers and pointers +to functions. In \*(C+, warn also when an arithmetic operation involves +\&\f(CW\*(C`NULL\*(C'\fR. This warning is also enabled by \fB\-pedantic\fR. +.IP "\fB\-Wtype\-limits\fR" 4 +.IX Item "-Wtype-limits" +Warn if a comparison is always true or always false due to the limited +range of the data type, but do not warn for constant expressions. For +example, warn if an unsigned variable is compared against zero with +\&\fB<\fR or \fB>=\fR. This warning is also enabled by +\&\fB\-Wextra\fR. +.IP "\fB\-Wbad\-function\-cast\fR (C and Objective-C only)" 4 +.IX Item "-Wbad-function-cast (C and Objective-C only)" +Warn whenever a function call is cast to a non-matching type. +For example, warn if \f(CW\*(C`int malloc()\*(C'\fR is cast to \f(CW\*(C`anything *\*(C'\fR. +.IP "\fB\-Wc++\-compat\fR (C and Objective-C only)" 4 +.IX Item "-Wc++-compat (C and Objective-C only)" +Warn about \s-1ISO\s0 C constructs that are outside of the common subset of +\&\s-1ISO\s0 C and \s-1ISO\s0 \*(C+, e.g. request for implicit conversion from +\&\f(CW\*(C`void *\*(C'\fR to a pointer to non\-\f(CW\*(C`void\*(C'\fR type. +.IP "\fB\-Wc++0x\-compat\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wc++0x-compat ( and Objective- only)" +Warn about \*(C+ constructs whose meaning differs between \s-1ISO\s0 \*(C+ 1998 and +\&\s-1ISO\s0 \*(C+ 200x, e.g., identifiers in \s-1ISO\s0 \*(C+ 1998 that will become keywords +in \s-1ISO\s0 \*(C+ 200x. This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wcast\-qual\fR" 4 +.IX Item "-Wcast-qual" +Warn whenever a pointer is cast so as to remove a type qualifier from +the target type. For example, warn if a \f(CW\*(C`const char *\*(C'\fR is cast +to an ordinary \f(CW\*(C`char *\*(C'\fR. +.Sp +Also warn when making a cast which introduces a type qualifier in an +unsafe way. For example, casting \f(CW\*(C`char **\*(C'\fR to \f(CW\*(C`const char **\*(C'\fR +is unsafe, as in this example: +.Sp +.Vb 6 +\& /* p is char ** value. */ +\& const char **q = (const char **) p; +\& /* Assignment of readonly string to const char * is OK. */ +\& *q = "string"; +\& /* Now char** pointer points to read\-only memory. */ +\& **p = \*(Aqb\*(Aq; +.Ve +.IP "\fB\-Wcast\-align\fR" 4 +.IX Item "-Wcast-align" +Warn whenever a pointer is cast such that the required alignment of the +target is increased. For example, warn if a \f(CW\*(C`char *\*(C'\fR is cast to +an \f(CW\*(C`int *\*(C'\fR on machines where integers can only be accessed at +two\- or four-byte boundaries. +.IP "\fB\-Wwrite\-strings\fR" 4 +.IX Item "-Wwrite-strings" +When compiling C, give string constants the type \f(CW\*(C`const +char[\f(CIlength\f(CW]\*(C'\fR so that copying the address of one into a +non\-\f(CW\*(C`const\*(C'\fR \f(CW\*(C`char *\*(C'\fR pointer will get a warning. These +warnings will help you find at compile time code that can try to write +into a string constant, but only if you have been very careful about +using \f(CW\*(C`const\*(C'\fR in declarations and prototypes. Otherwise, it will +just be a nuisance. This is why we did not make \fB\-Wall\fR request +these warnings. +.Sp +When compiling \*(C+, warn about the deprecated conversion from string +literals to \f(CW\*(C`char *\*(C'\fR. This warning is enabled by default for \*(C+ +programs. +.IP "\fB\-Wclobbered\fR" 4 +.IX Item "-Wclobbered" +Warn for variables that might be changed by \fBlongjmp\fR or +\&\fBvfork\fR. This warning is also enabled by \fB\-Wextra\fR. +.IP "\fB\-Wconversion\fR" 4 +.IX Item "-Wconversion" +Warn for implicit conversions that may alter a value. This includes +conversions between real and integer, like \f(CW\*(C`abs (x)\*(C'\fR when +\&\f(CW\*(C`x\*(C'\fR is \f(CW\*(C`double\*(C'\fR; conversions between signed and unsigned, +like \f(CW\*(C`unsigned ui = \-1\*(C'\fR; and conversions to smaller types, like +\&\f(CW\*(C`sqrtf (M_PI)\*(C'\fR. Do not warn for explicit casts like \f(CW\*(C`abs +((int) x)\*(C'\fR and \f(CW\*(C`ui = (unsigned) \-1\*(C'\fR, or if the value is not +changed by the conversion like in \f(CW\*(C`abs (2.0)\*(C'\fR. Warnings about +conversions between signed and unsigned integers can be disabled by +using \fB\-Wno\-sign\-conversion\fR. +.Sp +For \*(C+, also warn for confusing overload resolution for user-defined +conversions; and conversions that will never use a type conversion +operator: conversions to \f(CW\*(C`void\*(C'\fR, the same type, a base class or a +reference to them. Warnings about conversions between signed and +unsigned integers are disabled by default in \*(C+ unless +\&\fB\-Wsign\-conversion\fR is explicitly enabled. +.IP "\fB\-Wno\-conversion\-null\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-conversion-null ( and Objective- only)" +Do not warn for conversions between \f(CW\*(C`NULL\*(C'\fR and non-pointer +types. \fB\-Wconversion\-null\fR is enabled by default. +.IP "\fB\-Wreal\-conversion\fR" 4 +.IX Item "-Wreal-conversion" +Warn for implicit type conversions from real (\f(CW\*(C`double\*(C'\fR or \f(CW\*(C`float\*(C'\fR) +to integral values. +.IP "\fB\-Wempty\-body\fR" 4 +.IX Item "-Wempty-body" +Warn if an empty body occurs in an \fBif\fR, \fBelse\fR or \fBdo +while\fR statement. This warning is also enabled by \fB\-Wextra\fR. +.IP "\fB\-Wenum\-compare\fR" 4 +.IX Item "-Wenum-compare" +Warn about a comparison between values of different enum types. In \*(C+ +this warning is enabled by default. In C this warning is enabled by +\&\fB\-Wall\fR. +.IP "\fB\-Wjump\-misses\-init\fR (C, Objective-C only)" 4 +.IX Item "-Wjump-misses-init (C, Objective-C only)" +Warn if a \f(CW\*(C`goto\*(C'\fR statement or a \f(CW\*(C`switch\*(C'\fR statement jumps +forward across the initialization of a variable, or jumps backward to a +label after the variable has been initialized. This only warns about +variables which are initialized when they are declared. This warning is +only supported for C and Objective C; in \*(C+ this sort of branch is an +error in any case. +.Sp +\&\fB\-Wjump\-misses\-init\fR is included in \fB\-Wc++\-compat\fR. It +can be disabled with the \fB\-Wno\-jump\-misses\-init\fR option. +.IP "\fB\-Wsign\-compare\fR" 4 +.IX Item "-Wsign-compare" +Warn when a comparison between signed and unsigned values could produce +an incorrect result when the signed value is converted to unsigned. +This warning is also enabled by \fB\-Wextra\fR; to get the other warnings +of \fB\-Wextra\fR without this warning, use \fB\-Wextra \-Wno\-sign\-compare\fR. +.IP "\fB\-Wsign\-conversion\fR" 4 +.IX Item "-Wsign-conversion" +Warn for implicit conversions that may change the sign of an integer +value, like assigning a signed integer expression to an unsigned +integer variable. An explicit cast silences the warning. In C, this +option is enabled also by \fB\-Wconversion\fR. +.IP "\fB\-Waddress\fR" 4 +.IX Item "-Waddress" +Warn about suspicious uses of memory addresses. These include using +the address of a function in a conditional expression, such as +\&\f(CW\*(C`void func(void); if (func)\*(C'\fR, and comparisons against the memory +address of a string literal, such as \f(CW\*(C`if (x == "abc")\*(C'\fR. Such +uses typically indicate a programmer error: the address of a function +always evaluates to true, so their use in a conditional usually +indicate that the programmer forgot the parentheses in a function +call; and comparisons against string literals result in unspecified +behavior and are not portable in C, so they usually indicate that the +programmer intended to use \f(CW\*(C`strcmp\*(C'\fR. This warning is enabled by +\&\fB\-Wall\fR. +.IP "\fB\-Wlogical\-op\fR" 4 +.IX Item "-Wlogical-op" +Warn about suspicious uses of logical operators in expressions. +This includes using logical operators in contexts where a +bit-wise operator is likely to be expected. +.IP "\fB\-Waggregate\-return\fR" 4 +.IX Item "-Waggregate-return" +Warn if any functions that return structures or unions are defined or +called. (In languages where you can return an array, this also elicits +a warning.) +.IP "\fB\-Wno\-attributes\fR" 4 +.IX Item "-Wno-attributes" +Do not warn if an unexpected \f(CW\*(C`_\|_attribute_\|_\*(C'\fR is used, such as +unrecognized attributes, function attributes applied to variables, +etc. This will not stop errors for incorrect use of supported +attributes. +.IP "\fB\-Wno\-builtin\-macro\-redefined\fR" 4 +.IX Item "-Wno-builtin-macro-redefined" +Do not warn if certain built-in macros are redefined. This suppresses +warnings for redefinition of \f(CW\*(C`_\|_TIMESTAMP_\|_\*(C'\fR, \f(CW\*(C`_\|_TIME_\|_\*(C'\fR, +\&\f(CW\*(C`_\|_DATE_\|_\*(C'\fR, \f(CW\*(C`_\|_FILE_\|_\*(C'\fR, and \f(CW\*(C`_\|_BASE_FILE_\|_\*(C'\fR. +.IP "\fB\-Wstrict\-prototypes\fR (C and Objective-C only)" 4 +.IX Item "-Wstrict-prototypes (C and Objective-C only)" +Warn if a function is declared or defined without specifying the +argument types. (An old-style function definition is permitted without +a warning if preceded by a declaration which specifies the argument +types.) +.IP "\fB\-Wold\-style\-declaration\fR (C and Objective-C only)" 4 +.IX Item "-Wold-style-declaration (C and Objective-C only)" +Warn for obsolescent usages, according to the C Standard, in a +declaration. For example, warn if storage-class specifiers like +\&\f(CW\*(C`static\*(C'\fR are not the first things in a declaration. This warning +is also enabled by \fB\-Wextra\fR. +.IP "\fB\-Wold\-style\-definition\fR (C and Objective-C only)" 4 +.IX Item "-Wold-style-definition (C and Objective-C only)" +Warn if an old-style function definition is used. A warning is given +even if there is a previous prototype. +.IP "\fB\-Wmissing\-parameter\-type\fR (C and Objective-C only)" 4 +.IX Item "-Wmissing-parameter-type (C and Objective-C only)" +A function parameter is declared without a type specifier in K&R\-style +functions: +.Sp +.Vb 1 +\& void foo(bar) { } +.Ve +.Sp +This warning is also enabled by \fB\-Wextra\fR. +.IP "\fB\-Wmissing\-prototypes\fR (C and Objective-C only)" 4 +.IX Item "-Wmissing-prototypes (C and Objective-C only)" +Warn if a global function is defined without a previous prototype +declaration. This warning is issued even if the definition itself +provides a prototype. The aim is to detect global functions that fail +to be declared in header files. +.IP "\fB\-Wmissing\-declarations\fR" 4 +.IX Item "-Wmissing-declarations" +Warn if a global function is defined without a previous declaration. +Do so even if the definition itself provides a prototype. +Use this option to detect global functions that are not declared in +header files. In \*(C+, no warnings are issued for function templates, +or for inline functions, or for functions in anonymous namespaces. +.IP "\fB\-Wmissing\-field\-initializers\fR" 4 +.IX Item "-Wmissing-field-initializers" +Warn if a structure's initializer has some fields missing. For +example, the following code would cause such a warning, because +\&\f(CW\*(C`x.h\*(C'\fR is implicitly zero: +.Sp +.Vb 2 +\& struct s { int f, g, h; }; +\& struct s x = { 3, 4 }; +.Ve +.Sp +This option does not warn about designated initializers, so the following +modification would not trigger a warning: +.Sp +.Vb 2 +\& struct s { int f, g, h; }; +\& struct s x = { .f = 3, .g = 4 }; +.Ve +.Sp +This warning is included in \fB\-Wextra\fR. To get other \fB\-Wextra\fR +warnings without this one, use \fB\-Wextra \-Wno\-missing\-field\-initializers\fR. +.IP "\fB\-Wmissing\-format\-attribute\fR" 4 +.IX Item "-Wmissing-format-attribute" +Warn about function pointers which might be candidates for \f(CW\*(C`format\*(C'\fR +attributes. Note these are only possible candidates, not absolute ones. +\&\s-1GCC\s0 will guess that function pointers with \f(CW\*(C`format\*(C'\fR attributes that +are used in assignment, initialization, parameter passing or return +statements should have a corresponding \f(CW\*(C`format\*(C'\fR attribute in the +resulting type. I.e. the left-hand side of the assignment or +initialization, the type of the parameter variable, or the return type +of the containing function respectively should also have a \f(CW\*(C`format\*(C'\fR +attribute to avoid the warning. +.Sp +\&\s-1GCC\s0 will also warn about function definitions which might be +candidates for \f(CW\*(C`format\*(C'\fR attributes. Again, these are only +possible candidates. \s-1GCC\s0 will guess that \f(CW\*(C`format\*(C'\fR attributes +might be appropriate for any function that calls a function like +\&\f(CW\*(C`vprintf\*(C'\fR or \f(CW\*(C`vscanf\*(C'\fR, but this might not always be the +case, and some functions for which \f(CW\*(C`format\*(C'\fR attributes are +appropriate may not be detected. +.IP "\fB\-Wno\-multichar\fR" 4 +.IX Item "-Wno-multichar" +Do not warn if a multicharacter constant (\fB'\s-1FOOF\s0'\fR) is used. +Usually they indicate a typo in the user's code, as they have +implementation-defined values, and should not be used in portable code. +.IP "\fB\-Wnormalized=<none|id|nfc|nfkc>\fR" 4 +.IX Item "-Wnormalized=<none|id|nfc|nfkc>" +In \s-1ISO\s0 C and \s-1ISO\s0 \*(C+, two identifiers are different if they are +different sequences of characters. However, sometimes when characters +outside the basic \s-1ASCII\s0 character set are used, you can have two +different character sequences that look the same. To avoid confusion, +the \s-1ISO\s0 10646 standard sets out some \fInormalization rules\fR which +when applied ensure that two sequences that look the same are turned into +the same sequence. \s-1GCC\s0 can warn you if you are using identifiers which +have not been normalized; this option controls that warning. +.Sp +There are four levels of warning that \s-1GCC\s0 supports. The default is +\&\fB\-Wnormalized=nfc\fR, which warns about any identifier which is +not in the \s-1ISO\s0 10646 \*(L"C\*(R" normalized form, \fI\s-1NFC\s0\fR. \s-1NFC\s0 is the +recommended form for most uses. +.Sp +Unfortunately, there are some characters which \s-1ISO\s0 C and \s-1ISO\s0 \*(C+ allow +in identifiers that when turned into \s-1NFC\s0 aren't allowable as +identifiers. That is, there's no way to use these symbols in portable +\&\s-1ISO\s0 C or \*(C+ and have all your identifiers in \s-1NFC\s0. +\&\fB\-Wnormalized=id\fR suppresses the warning for these characters. +It is hoped that future versions of the standards involved will correct +this, which is why this option is not the default. +.Sp +You can switch the warning off for all characters by writing +\&\fB\-Wnormalized=none\fR. You would only want to do this if you +were using some other normalization scheme (like \*(L"D\*(R"), because +otherwise you can easily create bugs that are literally impossible to see. +.Sp +Some characters in \s-1ISO\s0 10646 have distinct meanings but look identical +in some fonts or display methodologies, especially once formatting has +been applied. For instance \f(CW\*(C`\eu207F\*(C'\fR, \*(L"\s-1SUPERSCRIPT\s0 \s-1LATIN\s0 \s-1SMALL\s0 +\&\s-1LETTER\s0 N\*(R", will display just like a regular \f(CW\*(C`n\*(C'\fR which has been +placed in a superscript. \s-1ISO\s0 10646 defines the \fI\s-1NFKC\s0\fR +normalization scheme to convert all these into a standard form as +well, and \s-1GCC\s0 will warn if your code is not in \s-1NFKC\s0 if you use +\&\fB\-Wnormalized=nfkc\fR. This warning is comparable to warning +about every identifier that contains the letter O because it might be +confused with the digit 0, and so is not the default, but may be +useful as a local coding convention if the programming environment is +unable to be fixed to display these characters distinctly. +.IP "\fB\-Wno\-deprecated\fR" 4 +.IX Item "-Wno-deprecated" +Do not warn about usage of deprecated features. +.IP "\fB\-Wno\-deprecated\-declarations\fR" 4 +.IX Item "-Wno-deprecated-declarations" +Do not warn about uses of functions, +variables, and types marked as deprecated by using the \f(CW\*(C`deprecated\*(C'\fR +attribute. +.IP "\fB\-Wno\-overflow\fR" 4 +.IX Item "-Wno-overflow" +Do not warn about compile-time overflow in constant expressions. +.IP "\fB\-Woverride\-init\fR (C and Objective-C only)" 4 +.IX Item "-Woverride-init (C and Objective-C only)" +Warn if an initialized field without side effects is overridden when +using designated initializers. +.Sp +This warning is included in \fB\-Wextra\fR. To get other +\&\fB\-Wextra\fR warnings without this one, use \fB\-Wextra +\&\-Wno\-override\-init\fR. +.IP "\fB\-Wpacked\fR" 4 +.IX Item "-Wpacked" +Warn if a structure is given the packed attribute, but the packed +attribute has no effect on the layout or size of the structure. +Such structures may be mis-aligned for little benefit. For +instance, in this code, the variable \f(CW\*(C`f.x\*(C'\fR in \f(CW\*(C`struct bar\*(C'\fR +will be misaligned even though \f(CW\*(C`struct bar\*(C'\fR does not itself +have the packed attribute: +.Sp +.Vb 8 +\& struct foo { +\& int x; +\& char a, b, c, d; +\& } _\|_attribute_\|_((packed)); +\& struct bar { +\& char z; +\& struct foo f; +\& }; +.Ve +.IP "\fB\-Wpacked\-bitfield\-compat\fR" 4 +.IX Item "-Wpacked-bitfield-compat" +The 4.1, 4.2 and 4.3 series of \s-1GCC\s0 ignore the \f(CW\*(C`packed\*(C'\fR attribute +on bit-fields of type \f(CW\*(C`char\*(C'\fR. This has been fixed in \s-1GCC\s0 4.4 but +the change can lead to differences in the structure layout. \s-1GCC\s0 +informs you when the offset of such a field has changed in \s-1GCC\s0 4.4. +For example there is no longer a 4\-bit padding between field \f(CW\*(C`a\*(C'\fR +and \f(CW\*(C`b\*(C'\fR in this structure: +.Sp +.Vb 5 +\& struct foo +\& { +\& char a:4; +\& char b:8; +\& } _\|_attribute_\|_ ((packed)); +.Ve +.Sp +This warning is enabled by default. Use +\&\fB\-Wno\-packed\-bitfield\-compat\fR to disable this warning. +.IP "\fB\-Wpadded\fR" 4 +.IX Item "-Wpadded" +Warn if padding is included in a structure, either to align an element +of the structure or to align the whole structure. Sometimes when this +happens it is possible to rearrange the fields of the structure to +reduce the padding and so make the structure smaller. +.IP "\fB\-Wredundant\-decls\fR" 4 +.IX Item "-Wredundant-decls" +Warn if anything is declared more than once in the same scope, even in +cases where multiple declaration is valid and changes nothing. +.IP "\fB\-Wnested\-externs\fR (C and Objective-C only)" 4 +.IX Item "-Wnested-externs (C and Objective-C only)" +Warn if an \f(CW\*(C`extern\*(C'\fR declaration is encountered within a function. +.IP "\fB\-Winline\fR" 4 +.IX Item "-Winline" +Warn if a function can not be inlined and it was declared as inline. +Even with this option, the compiler will not warn about failures to +inline functions declared in system headers. +.Sp +The compiler uses a variety of heuristics to determine whether or not +to inline a function. For example, the compiler takes into account +the size of the function being inlined and the amount of inlining +that has already been done in the current function. Therefore, +seemingly insignificant changes in the source program can cause the +warnings produced by \fB\-Winline\fR to appear or disappear. +.IP "\fB\-Wno\-invalid\-offsetof\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-invalid-offsetof ( and Objective- only)" +Suppress warnings from applying the \fBoffsetof\fR macro to a non-POD +type. According to the 1998 \s-1ISO\s0 \*(C+ standard, applying \fBoffsetof\fR +to a non-POD type is undefined. In existing \*(C+ implementations, +however, \fBoffsetof\fR typically gives meaningful results even when +applied to certain kinds of non-POD types. (Such as a simple +\&\fBstruct\fR that fails to be a \s-1POD\s0 type only by virtue of having a +constructor.) This flag is for users who are aware that they are +writing nonportable code and who have deliberately chosen to ignore the +warning about it. +.Sp +The restrictions on \fBoffsetof\fR may be relaxed in a future version +of the \*(C+ standard. +.IP "\fB\-Wno\-int\-to\-pointer\-cast\fR" 4 +.IX Item "-Wno-int-to-pointer-cast" +Suppress warnings from casts to pointer type of an integer of a +different size. In \*(C+, casting to a pointer type of smaller size is +an error. \fBWint-to-pointer-cast\fR is enabled by default. +.IP "\fBmax-lipo-mem\fR" 4 +.IX Item "max-lipo-mem" +When importing auxiliary modules during profile-use, check current +memory consumption after parsing each auxiliary module. If it exceeds +this limit (specified in kb), don't import any more auxiliary modules. +Specifying a value of 0 means don't enforce this limit. This parameter +is only useful when using \fB\-fprofile\-use\fR and \fB\-fripa\fR. +.IP "\fB\-Wno\-pointer\-to\-int\-cast\fR (C and Objective-C only)" 4 +.IX Item "-Wno-pointer-to-int-cast (C and Objective-C only)" +Suppress warnings from casts from a pointer to an integer type of a +different size. +.IP "\fB\-Winvalid\-pch\fR" 4 +.IX Item "-Winvalid-pch" +Warn if a precompiled header is found in +the search path but can't be used. +.IP "\fB\-Wlong\-long\fR" 4 +.IX Item "-Wlong-long" +Warn if \fBlong long\fR type is used. This is enabled by either +\&\fB\-pedantic\fR or \fB\-Wtraditional\fR in \s-1ISO\s0 C90 and \*(C+98 +modes. To inhibit the warning messages, use \fB\-Wno\-long\-long\fR. +.IP "\fB\-Wvariadic\-macros\fR" 4 +.IX Item "-Wvariadic-macros" +Warn if variadic macros are used in pedantic \s-1ISO\s0 C90 mode, or the \s-1GNU\s0 +alternate syntax when in pedantic \s-1ISO\s0 C99 mode. This is default. +To inhibit the warning messages, use \fB\-Wno\-variadic\-macros\fR. +.IP "\fB\-Wvla\fR" 4 +.IX Item "-Wvla" +Warn if variable length array is used in the code. +\&\fB\-Wno\-vla\fR will prevent the \fB\-pedantic\fR warning of +the variable length array. +.IP "\fB\-Wvolatile\-register\-var\fR" 4 +.IX Item "-Wvolatile-register-var" +Warn if a register variable is declared volatile. The volatile +modifier does not inhibit all optimizations that may eliminate reads +and/or writes to register variables. This warning is enabled by +\&\fB\-Wall\fR. +.IP "\fB\-Wdisabled\-optimization\fR" 4 +.IX Item "-Wdisabled-optimization" +Warn if a requested optimization pass is disabled. This warning does +not generally indicate that there is anything wrong with your code; it +merely indicates that \s-1GCC\s0's optimizers were unable to handle the code +effectively. Often, the problem is that your code is too big or too +complex; \s-1GCC\s0 will refuse to optimize programs when the optimization +itself is likely to take inordinate amounts of time. +.IP "\fB\-Wpointer\-sign\fR (C and Objective-C only)" 4 +.IX Item "-Wpointer-sign (C and Objective-C only)" +Warn for pointer argument passing or assignment with different signedness. +This option is only supported for C and Objective-C. It is implied by +\&\fB\-Wall\fR and by \fB\-pedantic\fR, which can be disabled with +\&\fB\-Wno\-pointer\-sign\fR. +.IP "\fB\-Wstack\-protector\fR" 4 +.IX Item "-Wstack-protector" +This option is only active when \fB\-fstack\-protector\fR is active. It +warns about functions that will not be protected against stack smashing. +.IP "\fB\-Wno\-mudflap\fR" 4 +.IX Item "-Wno-mudflap" +Suppress warnings about constructs that cannot be instrumented by +\&\fB\-fmudflap\fR. +.IP "\fB\-Woverlength\-strings\fR" 4 +.IX Item "-Woverlength-strings" +Warn about string constants which are longer than the \*(L"minimum +maximum\*(R" length specified in the C standard. Modern compilers +generally allow string constants which are much longer than the +standard's minimum limit, but very portable programs should avoid +using longer strings. +.Sp +The limit applies \fIafter\fR string constant concatenation, and does +not count the trailing \s-1NUL\s0. In C90, the limit was 509 characters; in +C99, it was raised to 4095. \*(C+98 does not specify a normative +minimum maximum, so we do not diagnose overlength strings in \*(C+. +.Sp +This option is implied by \fB\-pedantic\fR, and can be disabled with +\&\fB\-Wno\-overlength\-strings\fR. +.IP "\fB\-Wunsuffixed\-float\-constants\fR (C and Objective-C only)" 4 +.IX Item "-Wunsuffixed-float-constants (C and Objective-C only)" +\&\s-1GCC\s0 will issue a warning for any floating constant that does not have +a suffix. When used together with \fB\-Wsystem\-headers\fR it will +warn about such constants in system header files. This can be useful +when preparing code to use with the \f(CW\*(C`FLOAT_CONST_DECIMAL64\*(C'\fR pragma +from the decimal floating-point extension to C99. +.SS "Options for Debugging Your Program or \s-1GCC\s0" +.IX Subsection "Options for Debugging Your Program or GCC" +\&\s-1GCC\s0 has various special options that are used for debugging +either your program or \s-1GCC:\s0 +.IP "\fB\-g\fR" 4 +.IX Item "-g" +Produce debugging information in the operating system's native format +(stabs, \s-1COFF\s0, \s-1XCOFF\s0, or \s-1DWARF\s0 2). \s-1GDB\s0 can work with this debugging +information. +.Sp +On most systems that use stabs format, \fB\-g\fR enables use of extra +debugging information that only \s-1GDB\s0 can use; this extra information +makes debugging work better in \s-1GDB\s0 but will probably make other debuggers +crash or +refuse to read the program. If you want to control for certain whether +to generate the extra information, use \fB\-gstabs+\fR, \fB\-gstabs\fR, +\&\fB\-gxcoff+\fR, \fB\-gxcoff\fR, or \fB\-gvms\fR (see below). +.Sp +\&\s-1GCC\s0 allows you to use \fB\-g\fR with +\&\fB\-O\fR. The shortcuts taken by optimized code may occasionally +produce surprising results: some variables you declared may not exist +at all; flow of control may briefly move where you did not expect it; +some statements may not be executed because they compute constant +results or their values were already at hand; some statements may +execute in different places because they were moved out of loops. +.Sp +Nevertheless it proves possible to debug optimized output. This makes +it reasonable to use the optimizer for programs that might have bugs. +.Sp +The following options are useful when \s-1GCC\s0 is generated with the +capability for more than one debugging format. +.IP "\fB\-ggdb\fR" 4 +.IX Item "-ggdb" +Produce debugging information for use by \s-1GDB\s0. This means to use the +most expressive format available (\s-1DWARF\s0 2, stabs, or the native format +if neither of those are supported), including \s-1GDB\s0 extensions if at all +possible. +.IP "\fB\-gstabs\fR" 4 +.IX Item "-gstabs" +Produce debugging information in stabs format (if that is supported), +without \s-1GDB\s0 extensions. This is the format used by \s-1DBX\s0 on most \s-1BSD\s0 +systems. On \s-1MIPS\s0, Alpha and System V Release 4 systems this option +produces stabs debugging output which is not understood by \s-1DBX\s0 or \s-1SDB\s0. +On System V Release 4 systems this option requires the \s-1GNU\s0 assembler. +.IP "\fB\-feliminate\-unused\-debug\-symbols\fR" 4 +.IX Item "-feliminate-unused-debug-symbols" +Produce debugging information in stabs format (if that is supported), +for only symbols that are actually used. +.IP "\fB\-femit\-class\-debug\-always\fR" 4 +.IX Item "-femit-class-debug-always" +Instead of emitting debugging information for a \*(C+ class in only one +object file, emit it in all object files using the class. This option +should be used only with debuggers that are unable to handle the way \s-1GCC\s0 +normally emits debugging information for classes because using this +option will increase the size of debugging information by as much as a +factor of two. +.IP "\fB\-gstabs+\fR" 4 +.IX Item "-gstabs+" +Produce debugging information in stabs format (if that is supported), +using \s-1GNU\s0 extensions understood only by the \s-1GNU\s0 debugger (\s-1GDB\s0). The +use of these extensions is likely to make other debuggers crash or +refuse to read the program. +.IP "\fB\-gcoff\fR" 4 +.IX Item "-gcoff" +Produce debugging information in \s-1COFF\s0 format (if that is supported). +This is the format used by \s-1SDB\s0 on most System V systems prior to +System V Release 4. +.IP "\fB\-gxcoff\fR" 4 +.IX Item "-gxcoff" +Produce debugging information in \s-1XCOFF\s0 format (if that is supported). +This is the format used by the \s-1DBX\s0 debugger on \s-1IBM\s0 \s-1RS/6000\s0 systems. +.IP "\fB\-gxcoff+\fR" 4 +.IX Item "-gxcoff+" +Produce debugging information in \s-1XCOFF\s0 format (if that is supported), +using \s-1GNU\s0 extensions understood only by the \s-1GNU\s0 debugger (\s-1GDB\s0). The +use of these extensions is likely to make other debuggers crash or +refuse to read the program, and may cause assemblers other than the \s-1GNU\s0 +assembler (\s-1GAS\s0) to fail with an error. +.IP "\fB\-gdwarf\-\fR\fIversion\fR" 4 +.IX Item "-gdwarf-version" +Produce debugging information in \s-1DWARF\s0 format (if that is +supported). This is the format used by \s-1DBX\s0 on \s-1IRIX\s0 6. The value +of \fIversion\fR may be either 2, 3 or 4; the default version is 2. +.Sp +Note that with \s-1DWARF\s0 version 2 some ports require, and will always +use, some non-conflicting \s-1DWARF\s0 3 extensions in the unwind tables. +.Sp +Version 4 may require \s-1GDB\s0 7.0 and \fB\-fvar\-tracking\-assignments\fR +for maximum benefit. +.IP "\fB\-gstrict\-dwarf\fR" 4 +.IX Item "-gstrict-dwarf" +Disallow using extensions of later \s-1DWARF\s0 standard version than selected +with \fB\-gdwarf\-\fR\fIversion\fR. On most targets using non-conflicting +\&\s-1DWARF\s0 extensions from later standard versions is allowed. +.IP "\fB\-gno\-strict\-dwarf\fR" 4 +.IX Item "-gno-strict-dwarf" +Allow using extensions of later \s-1DWARF\s0 standard version than selected with +\&\fB\-gdwarf\-\fR\fIversion\fR. +.IP "\fB\-gvms\fR" 4 +.IX Item "-gvms" +Produce debugging information in \s-1VMS\s0 debug format (if that is +supported). This is the format used by \s-1DEBUG\s0 on \s-1VMS\s0 systems. +.IP "\fB\-g\fR\fIlevel\fR" 4 +.IX Item "-glevel" +.PD 0 +.IP "\fB\-ggdb\fR\fIlevel\fR" 4 +.IX Item "-ggdblevel" +.IP "\fB\-gstabs\fR\fIlevel\fR" 4 +.IX Item "-gstabslevel" +.IP "\fB\-gcoff\fR\fIlevel\fR" 4 +.IX Item "-gcofflevel" +.IP "\fB\-gxcoff\fR\fIlevel\fR" 4 +.IX Item "-gxcofflevel" +.IP "\fB\-gvms\fR\fIlevel\fR" 4 +.IX Item "-gvmslevel" +.PD +Request debugging information and also use \fIlevel\fR to specify how +much information. The default level is 2. +.Sp +Level 0 produces no debug information at all. Thus, \fB\-g0\fR negates +\&\fB\-g\fR. +.Sp +Level 1 produces minimal information, enough for making backtraces in +parts of the program that you don't plan to debug. This includes +descriptions of functions and external variables, but no information +about local variables and no line numbers. +.Sp +Level 3 includes extra information, such as all the macro definitions +present in the program. Some debuggers support macro expansion when +you use \fB\-g3\fR. +.Sp +\&\fB\-gdwarf\-2\fR does not accept a concatenated debug level, because +\&\s-1GCC\s0 used to support an option \fB\-gdwarf\fR that meant to generate +debug information in version 1 of the \s-1DWARF\s0 format (which is very +different from version 2), and it would have been too confusing. That +debug format is long obsolete, but the option cannot be changed now. +Instead use an additional \fB\-g\fR\fIlevel\fR option to change the +debug level for \s-1DWARF\s0. +.IP "\fB\-gmlt\fR" 4 +.IX Item "-gmlt" +Produce a minimal line table, with level 1 debugging information plus +information about inlined functions and line numbers. +.IP "\fB\-gtoggle\fR" 4 +.IX Item "-gtoggle" +Turn off generation of debug info, if leaving out this option would have +generated it, or turn it on at level 2 otherwise. The position of this +argument in the command line does not matter, it takes effect after all +other options are processed, and it does so only once, no matter how +many times it is given. This is mainly intended to be used with +\&\fB\-fcompare\-debug\fR. +.IP "\fB\-fdump\-final\-insns\fR[\fB=\fR\fIfile\fR]" 4 +.IX Item "-fdump-final-insns[=file]" +Dump the final internal representation (\s-1RTL\s0) to \fIfile\fR. If the +optional argument is omitted (or if \fIfile\fR is \f(CW\*(C`.\*(C'\fR), the name +of the dump file will be determined by appending \f(CW\*(C`.gkd\*(C'\fR to the +compilation output file name. +.IP "\fB\-fcompare\-debug\fR[\fB=\fR\fIopts\fR]" 4 +.IX Item "-fcompare-debug[=opts]" +If no error occurs during compilation, run the compiler a second time, +adding \fIopts\fR and \fB\-fcompare\-debug\-second\fR to the arguments +passed to the second compilation. Dump the final internal +representation in both compilations, and print an error if they differ. +.Sp +If the equal sign is omitted, the default \fB\-gtoggle\fR is used. +.Sp +The environment variable \fB\s-1GCC_COMPARE_DEBUG\s0\fR, if defined, non-empty +and nonzero, implicitly enables \fB\-fcompare\-debug\fR. If +\&\fB\s-1GCC_COMPARE_DEBUG\s0\fR is defined to a string starting with a dash, +then it is used for \fIopts\fR, otherwise the default \fB\-gtoggle\fR +is used. +.Sp +\&\fB\-fcompare\-debug=\fR, with the equal sign but without \fIopts\fR, +is equivalent to \fB\-fno\-compare\-debug\fR, which disables the dumping +of the final representation and the second compilation, preventing even +\&\fB\s-1GCC_COMPARE_DEBUG\s0\fR from taking effect. +.Sp +To verify full coverage during \fB\-fcompare\-debug\fR testing, set +\&\fB\s-1GCC_COMPARE_DEBUG\s0\fR to say \fB\-fcompare\-debug\-not\-overridden\fR, +which \s-1GCC\s0 will reject as an invalid option in any actual compilation +(rather than preprocessing, assembly or linking). To get just a +warning, setting \fB\s-1GCC_COMPARE_DEBUG\s0\fR to \fB\-w%n\-fcompare\-debug +not overridden\fR will do. +.IP "\fB\-fcompare\-debug\-second\fR" 4 +.IX Item "-fcompare-debug-second" +This option is implicitly passed to the compiler for the second +compilation requested by \fB\-fcompare\-debug\fR, along with options to +silence warnings, and omitting other options that would cause +side-effect compiler outputs to files or to the standard output. Dump +files and preserved temporary files are renamed so as to contain the +\&\f(CW\*(C`.gk\*(C'\fR additional extension during the second compilation, to avoid +overwriting those generated by the first. +.Sp +When this option is passed to the compiler driver, it causes the +\&\fIfirst\fR compilation to be skipped, which makes it useful for little +other than debugging the compiler proper. +.IP "\fB\-feliminate\-dwarf2\-dups\fR" 4 +.IX Item "-feliminate-dwarf2-dups" +Compress \s-1DWARF2\s0 debugging information by eliminating duplicated +information about each symbol. This option only makes sense when +generating \s-1DWARF2\s0 debugging information with \fB\-gdwarf\-2\fR. +.IP "\fB\-femit\-struct\-debug\-baseonly\fR" 4 +.IX Item "-femit-struct-debug-baseonly" +Emit debug information for struct-like types +only when the base name of the compilation source file +matches the base name of file in which the struct was defined. +.Sp +This option substantially reduces the size of debugging information, +but at significant potential loss in type information to the debugger. +See \fB\-femit\-struct\-debug\-reduced\fR for a less aggressive option. +See \fB\-femit\-struct\-debug\-detailed\fR for more detailed control. +.Sp +This option works only with \s-1DWARF\s0 2. +.IP "\fB\-femit\-struct\-debug\-reduced\fR" 4 +.IX Item "-femit-struct-debug-reduced" +Emit debug information for struct-like types +only when the base name of the compilation source file +matches the base name of file in which the type was defined, +unless the struct is a template or defined in a system header. +.Sp +This option significantly reduces the size of debugging information, +with some potential loss in type information to the debugger. +See \fB\-femit\-struct\-debug\-baseonly\fR for a more aggressive option. +See \fB\-femit\-struct\-debug\-detailed\fR for more detailed control. +.Sp +This option works only with \s-1DWARF\s0 2. +.IP "\fB\-femit\-struct\-debug\-detailed\fR[\fB=\fR\fIspec-list\fR]" 4 +.IX Item "-femit-struct-debug-detailed[=spec-list]" +Specify the struct-like types +for which the compiler will generate debug information. +The intent is to reduce duplicate struct debug information +between different object files within the same program. +.Sp +This option is a detailed version of +\&\fB\-femit\-struct\-debug\-reduced\fR and \fB\-femit\-struct\-debug\-baseonly\fR, +which will serve for most needs. +.Sp +A specification has the syntax[\fBdir:\fR|\fBind:\fR][\fBord:\fR|\fBgen:\fR](\fBany\fR|\fBsys\fR|\fBbase\fR|\fBnone\fR) +.Sp +The optional first word limits the specification to +structs that are used directly (\fBdir:\fR) or used indirectly (\fBind:\fR). +A struct type is used directly when it is the type of a variable, member. +Indirect uses arise through pointers to structs. +That is, when use of an incomplete struct would be legal, the use is indirect. +An example is +\&\fBstruct one direct; struct two * indirect;\fR. +.Sp +The optional second word limits the specification to +ordinary structs (\fBord:\fR) or generic structs (\fBgen:\fR). +Generic structs are a bit complicated to explain. +For \*(C+, these are non-explicit specializations of template classes, +or non-template classes within the above. +Other programming languages have generics, +but \fB\-femit\-struct\-debug\-detailed\fR does not yet implement them. +.Sp +The third word specifies the source files for those +structs for which the compiler will emit debug information. +The values \fBnone\fR and \fBany\fR have the normal meaning. +The value \fBbase\fR means that +the base of name of the file in which the type declaration appears +must match the base of the name of the main compilation file. +In practice, this means that +types declared in \fIfoo.c\fR and \fIfoo.h\fR will have debug information, +but types declared in other header will not. +The value \fBsys\fR means those types satisfying \fBbase\fR +or declared in system or compiler headers. +.Sp +You may need to experiment to determine the best settings for your application. +.Sp +The default is \fB\-femit\-struct\-debug\-detailed=all\fR. +.Sp +This option works only with \s-1DWARF\s0 2. +.IP "\fB\-fenable\-icf\-debug\fR" 4 +.IX Item "-fenable-icf-debug" +Generate additional debug information to support identical code folding (\s-1ICF\s0). +This option only works with \s-1DWARF\s0 version 2 or higher. +.IP "\fB\-fno\-merge\-debug\-strings\fR" 4 +.IX Item "-fno-merge-debug-strings" +Direct the linker to not merge together strings in the debugging +information which are identical in different object files. Merging is +not supported by all assemblers or linkers. Merging decreases the size +of the debug information in the output file at the cost of increasing +link processing time. Merging is enabled by default. +.IP "\fB\-fdebug\-prefix\-map=\fR\fIold\fR\fB=\fR\fInew\fR" 4 +.IX Item "-fdebug-prefix-map=old=new" +When compiling files in directory \fI\fIold\fI\fR, record debugging +information describing them as in \fI\fInew\fI\fR instead. +.IP "\fB\-fno\-dwarf2\-cfi\-asm\fR" 4 +.IX Item "-fno-dwarf2-cfi-asm" +Emit \s-1DWARF\s0 2 unwind info as compiler generated \f(CW\*(C`.eh_frame\*(C'\fR section +instead of using \s-1GAS\s0 \f(CW\*(C`.cfi_*\*(C'\fR directives. +.IP "\fB\-p\fR" 4 +.IX Item "-p" +Generate extra code to write profile information suitable for the +analysis program \fBprof\fR. You must use this option when compiling +the source files you want data about, and you must also use it when +linking. +.IP "\fB\-pg\fR" 4 +.IX Item "-pg" +Generate extra code to write profile information suitable for the +analysis program \fBgprof\fR. You must use this option when compiling +the source files you want data about, and you must also use it when +linking. +.IP "\fB\-Q\fR" 4 +.IX Item "-Q" +Makes the compiler print out each function name as it is compiled, and +print some statistics about each pass when it finishes. +.IP "\fB\-ftime\-report\fR" 4 +.IX Item "-ftime-report" +Makes the compiler print some statistics about the time consumed by each +pass when it finishes. +.IP "\fB\-fmem\-report\fR" 4 +.IX Item "-fmem-report" +Makes the compiler print some statistics about permanent memory +allocation when it finishes. +.IP "\fB\-fpre\-ipa\-mem\-report\fR" 4 +.IX Item "-fpre-ipa-mem-report" +.PD 0 +.IP "\fB\-fpost\-ipa\-mem\-report\fR" 4 +.IX Item "-fpost-ipa-mem-report" +.PD +Makes the compiler print some statistics about permanent memory +allocation before or after interprocedural optimization. +.IP "\fB\-fstack\-usage\fR" 4 +.IX Item "-fstack-usage" +Makes the compiler output stack usage information for the program, on a +per-function basis. The filename for the dump is made by appending +\&\fI.su\fR to the \fIauxname\fR. \fIauxname\fR is generated from the name of +the output file, if explicitly specified and it is not an executable, +otherwise it is the basename of the source file. An entry is made up +of three fields: +.RS 4 +.IP "\(bu" 4 +The name of the function. +.IP "\(bu" 4 +A number of bytes. +.IP "\(bu" 4 +One or more qualifiers: \f(CW\*(C`static\*(C'\fR, \f(CW\*(C`dynamic\*(C'\fR, \f(CW\*(C`bounded\*(C'\fR. +.RE +.RS 4 +.Sp +The qualifier \f(CW\*(C`static\*(C'\fR means that the function manipulates the stack +statically: a fixed number of bytes are allocated for the frame on function +entry and released on function exit; no stack adjustments are otherwise made +in the function. The second field is this fixed number of bytes. +.Sp +The qualifier \f(CW\*(C`dynamic\*(C'\fR means that the function manipulates the stack +dynamically: in addition to the static allocation described above, stack +adjustments are made in the body of the function, for example to push/pop +arguments around function calls. If the qualifier \f(CW\*(C`bounded\*(C'\fR is also +present, the amount of these adjustments is bounded at compile-time and +the second field is an upper bound of the total amount of stack used by +the function. If it is not present, the amount of these adjustments is +not bounded at compile-time and the second field only represents the +bounded part. +.RE +.IP "\fB\-fprofile\-arcs\fR" 4 +.IX Item "-fprofile-arcs" +Add code so that program flow \fIarcs\fR are instrumented. During +execution the program records how many times each branch and call is +executed and how many times it is taken or returns. When the compiled +program exits it saves this data to a file called +\&\fI\fIauxname\fI.gcda\fR for each source file. The data may be used for +profile-directed optimizations (\fB\-fbranch\-probabilities\fR), or for +test coverage analysis (\fB\-ftest\-coverage\fR). Each object file's +\&\fIauxname\fR is generated from the name of the output file, if +explicitly specified and it is not the final executable, otherwise it is +the basename of the source file. In both cases any suffix is removed +(e.g. \fIfoo.gcda\fR for input file \fIdir/foo.c\fR, or +\&\fIdir/foo.gcda\fR for output file specified as \fB\-o dir/foo.o\fR). +.IP "\fB\-\-coverage\fR" 4 +.IX Item "--coverage" +This option is used to compile and link code instrumented for coverage +analysis. The option is a synonym for \fB\-fprofile\-arcs\fR +\&\fB\-ftest\-coverage\fR (when compiling) and \fB\-lgcov\fR (when +linking). See the documentation for those options for more details. +.RS 4 +.IP "\(bu" 4 +Compile the source files with \fB\-fprofile\-arcs\fR plus optimization +and code generation options. For test coverage analysis, use the +additional \fB\-ftest\-coverage\fR option. You do not need to profile +every source file in a program. +.IP "\(bu" 4 +Link your object files with \fB\-lgcov\fR or \fB\-fprofile\-arcs\fR +(the latter implies the former). +.IP "\(bu" 4 +Run the program on a representative workload to generate the arc profile +information. This may be repeated any number of times. You can run +concurrent instances of your program, and provided that the file system +supports locking, the data files will be correctly updated. Also +\&\f(CW\*(C`fork\*(C'\fR calls are detected and correctly handled (double counting +will not happen). +.IP "\(bu" 4 +For profile-directed optimizations, compile the source files again with +the same optimization and code generation options plus +\&\fB\-fbranch\-probabilities\fR. +.IP "\(bu" 4 +For test coverage analysis, use \fBgcov\fR to produce human readable +information from the \fI.gcno\fR and \fI.gcda\fR files. Refer to the +\&\fBgcov\fR documentation for further information. +.RE +.RS 4 +.Sp +With \fB\-fprofile\-arcs\fR, for each function of your program \s-1GCC\s0 +creates a program flow graph, then finds a spanning tree for the graph. +Only arcs that are not on the spanning tree have to be instrumented: the +compiler adds code to count the number of times that these arcs are +executed. When an arc is the only exit or only entrance to a block, the +instrumentation code can be added to the block; otherwise, a new basic +block must be created to hold the instrumentation code. +.RE +.IP "\fB\-ftest\-coverage\fR" 4 +.IX Item "-ftest-coverage" +Produce a notes file that the \fBgcov\fR code-coverage utility can use to +show program coverage. Each source file's note file is called +\&\fI\fIauxname\fI.gcno\fR. Refer to the \fB\-fprofile\-arcs\fR option +above for a description of \fIauxname\fR and instructions on how to +generate test coverage data. Coverage data will match the source files +more closely, if you do not optimize. +.IP "\fB\-fdbg\-cnt\-list\fR" 4 +.IX Item "-fdbg-cnt-list" +Print the name and the counter upper bound for all debug counters. +.IP "\fB\-fdbg\-cnt=\fR\fIcounter-value-list\fR" 4 +.IX Item "-fdbg-cnt=counter-value-list" +Set the internal debug counter upper bound. \fIcounter-value-list\fR +is a comma-separated list of \fIname\fR:\fIvalue\fR pairs +which sets the upper bound of each debug counter \fIname\fR to \fIvalue\fR. +All debug counters have the initial upper bound of \fI\s-1UINT_MAX\s0\fR, +thus \fIdbg_cnt()\fR returns true always unless the upper bound is set by this option. +e.g. With \-fdbg\-cnt=dce:10,tail_call:0 +dbg_cnt(dce) will return true only for first 10 invocations +.IP "\fB\-fenable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR" 4 +.IX Item "-fenable-kind-pass" +.PD 0 +.IP "\fB\-fdisable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR" 4 +.IX Item "-fdisable-kind-pass=range-list" +.PD +This is a set of debugging options that are used to explicitly disable/enable +optimization passes. For compiler users, regular options for enabling/disabling +passes should be used instead. +.RS 4 +.IP "*<\-fdisable\-ipa\-\fIpass\fR>" 4 +.IX Item "*<-fdisable-ipa-pass>" +Disable ipa pass \fIpass\fR. \fIpass\fR is the pass name. If the same pass is +statically invoked in the compiler multiple times, the pass name should be +appended with a sequential number starting from 1. +.IP "*<\-fdisable\-rtl\-\fIpass\fR>" 4 +.IX Item "*<-fdisable-rtl-pass>" +.PD 0 +.IP "*<\-fdisable\-rtl\-\fIpass\fR=\fIrange-list\fR>" 4 +.IX Item "*<-fdisable-rtl-pass=range-list>" +.PD +Disable rtl pass \fIpass\fR. \fIpass\fR is the pass name. If the same pass is +statically invoked in the compiler multiple times, the pass name should be +appended with a sequential number starting from 1. \fIrange-list\fR is a comma +seperated list of function ranges or assembler names. Each range is a number +pair seperated by a colon. The range is inclusive in both ends. If the range +is trivial, the number pair can be simplified as a single number. If the +function's cgraph node's \fIuid\fR is falling within one of the specified ranges, +the \fIpass\fR is disabled for that function. The \fIuid\fR is shown in the +function header of a dump file, and the pass names can be dumped by using +option \fB\-fdump\-passes\fR. +.IP "*<\-fdisable\-tree\-\fIpass\fR>" 4 +.IX Item "*<-fdisable-tree-pass>" +.PD 0 +.IP "*<\-fdisable\-tree\-\fIpass\fR=\fIrange-list\fR>" 4 +.IX Item "*<-fdisable-tree-pass=range-list>" +.PD +Disable tree pass \fIpass\fR. See \fB\-fdisable\-rtl\fR for the description of +option arguments. +.IP "*<\-fenable\-ipa\-\fIpass\fR>" 4 +.IX Item "*<-fenable-ipa-pass>" +Enable ipa pass \fIpass\fR. \fIpass\fR is the pass name. If the same pass is +statically invoked in the compiler multiple times, the pass name should be +appended with a sequential number starting from 1. +.IP "*<\-fenable\-rtl\-\fIpass\fR>" 4 +.IX Item "*<-fenable-rtl-pass>" +.PD 0 +.IP "*<\-fenable\-rtl\-\fIpass\fR=\fIrange-list\fR>" 4 +.IX Item "*<-fenable-rtl-pass=range-list>" +.PD +Enable rtl pass \fIpass\fR. See \fB\-fdisable\-rtl\fR for option argument +description and examples. +.IP "*<\-fenable\-tree\-\fIpass\fR>" 4 +.IX Item "*<-fenable-tree-pass>" +.PD 0 +.IP "*<\-fenable\-tree\-\fIpass\fR=\fIrange-list\fR>" 4 +.IX Item "*<-fenable-tree-pass=range-list>" +.PD +Enable tree pass \fIpass\fR. See \fB\-fdisable\-rtl\fR for the description +of option arguments. +.Sp +.Vb 10 +\& # disable ccp1 for all functions +\& \-fdisable\-tree\-ccp1 +\& # disable complete unroll for function whose cgraph node uid is 1 +\& \-fenable\-tree\-cunroll=1 +\& # disable gcse2 for functions at the following ranges [1,1], +\& # [300,400], and [400,1000] +\& # disable gcse2 for functions foo and foo2 +\& \-fdisable\-rtl\-gcse2=foo,foo2 +\& # disable early inlining +\& \-fdisable\-tree\-einline +\& # disable ipa inlining +\& \-fdisable\-ipa\-inline +\& # enable tree full unroll +\& \-fenable\-tree\-unroll +.Ve +.RE +.RS 4 +.RE +.IP "\fB\-d\fR\fIletters\fR" 4 +.IX Item "-dletters" +.PD 0 +.IP "\fB\-fdump\-rtl\-\fR\fIpass\fR" 4 +.IX Item "-fdump-rtl-pass" +.PD +Says to make debugging dumps during compilation at times specified by +\&\fIletters\fR. This is used for debugging the RTL-based passes of the +compiler. The file names for most of the dumps are made by appending +a pass number and a word to the \fIdumpname\fR, and the files are +created in the directory of the output file. Note that the pass +number is computed statically as passes get registered into the pass +manager. Thus the numbering is not related to the dynamic order of +execution of passes. In particular, a pass installed by a plugin +could have a number over 200 even if it executed quite early. +\&\fIdumpname\fR is generated from the name of the output file, if +explicitly specified and it is not an executable, otherwise it is the +basename of the source file. These switches may have different effects +when \fB\-E\fR is used for preprocessing. +.Sp +Debug dumps can be enabled with a \fB\-fdump\-rtl\fR switch or some +\&\fB\-d\fR option \fIletters\fR. Here are the possible +letters for use in \fIpass\fR and \fIletters\fR, and their meanings: +.RS 4 +.IP "\fB\-fdump\-rtl\-alignments\fR" 4 +.IX Item "-fdump-rtl-alignments" +Dump after branch alignments have been computed. +.IP "\fB\-fdump\-rtl\-asmcons\fR" 4 +.IX Item "-fdump-rtl-asmcons" +Dump after fixing rtl statements that have unsatisfied in/out constraints. +.IP "\fB\-fdump\-rtl\-auto_inc_dec\fR" 4 +.IX Item "-fdump-rtl-auto_inc_dec" +Dump after auto-inc-dec discovery. This pass is only run on +architectures that have auto inc or auto dec instructions. +.IP "\fB\-fdump\-rtl\-barriers\fR" 4 +.IX Item "-fdump-rtl-barriers" +Dump after cleaning up the barrier instructions. +.IP "\fB\-fdump\-rtl\-bbpart\fR" 4 +.IX Item "-fdump-rtl-bbpart" +Dump after partitioning hot and cold basic blocks. +.IP "\fB\-fdump\-rtl\-bbro\fR" 4 +.IX Item "-fdump-rtl-bbro" +Dump after block reordering. +.IP "\fB\-fdump\-rtl\-btl1\fR" 4 +.IX Item "-fdump-rtl-btl1" +.PD 0 +.IP "\fB\-fdump\-rtl\-btl2\fR" 4 +.IX Item "-fdump-rtl-btl2" +.PD +\&\fB\-fdump\-rtl\-btl1\fR and \fB\-fdump\-rtl\-btl2\fR enable dumping +after the two branch +target load optimization passes. +.IP "\fB\-fdump\-rtl\-bypass\fR" 4 +.IX Item "-fdump-rtl-bypass" +Dump after jump bypassing and control flow optimizations. +.IP "\fB\-fdump\-rtl\-combine\fR" 4 +.IX Item "-fdump-rtl-combine" +Dump after the \s-1RTL\s0 instruction combination pass. +.IP "\fB\-fdump\-rtl\-compgotos\fR" 4 +.IX Item "-fdump-rtl-compgotos" +Dump after duplicating the computed gotos. +.IP "\fB\-fdump\-rtl\-ce1\fR" 4 +.IX Item "-fdump-rtl-ce1" +.PD 0 +.IP "\fB\-fdump\-rtl\-ce2\fR" 4 +.IX Item "-fdump-rtl-ce2" +.IP "\fB\-fdump\-rtl\-ce3\fR" 4 +.IX Item "-fdump-rtl-ce3" +.PD +\&\fB\-fdump\-rtl\-ce1\fR, \fB\-fdump\-rtl\-ce2\fR, and +\&\fB\-fdump\-rtl\-ce3\fR enable dumping after the three +if conversion passes. +.IP "\fB\-fdump\-rtl\-cprop_hardreg\fR" 4 +.IX Item "-fdump-rtl-cprop_hardreg" +Dump after hard register copy propagation. +.IP "\fB\-fdump\-rtl\-csa\fR" 4 +.IX Item "-fdump-rtl-csa" +Dump after combining stack adjustments. +.IP "\fB\-fdump\-rtl\-cse1\fR" 4 +.IX Item "-fdump-rtl-cse1" +.PD 0 +.IP "\fB\-fdump\-rtl\-cse2\fR" 4 +.IX Item "-fdump-rtl-cse2" +.PD +\&\fB\-fdump\-rtl\-cse1\fR and \fB\-fdump\-rtl\-cse2\fR enable dumping after +the two common sub-expression elimination passes. +.IP "\fB\-fdump\-rtl\-dce\fR" 4 +.IX Item "-fdump-rtl-dce" +Dump after the standalone dead code elimination passes. +.IP "\fB\-fdump\-rtl\-dbr\fR" 4 +.IX Item "-fdump-rtl-dbr" +Dump after delayed branch scheduling. +.IP "\fB\-fdump\-rtl\-dce1\fR" 4 +.IX Item "-fdump-rtl-dce1" +.PD 0 +.IP "\fB\-fdump\-rtl\-dce2\fR" 4 +.IX Item "-fdump-rtl-dce2" +.PD +\&\fB\-fdump\-rtl\-dce1\fR and \fB\-fdump\-rtl\-dce2\fR enable dumping after +the two dead store elimination passes. +.IP "\fB\-fdump\-rtl\-eh\fR" 4 +.IX Item "-fdump-rtl-eh" +Dump after finalization of \s-1EH\s0 handling code. +.IP "\fB\-fdump\-rtl\-eh_ranges\fR" 4 +.IX Item "-fdump-rtl-eh_ranges" +Dump after conversion of \s-1EH\s0 handling range regions. +.IP "\fB\-fdump\-rtl\-expand\fR" 4 +.IX Item "-fdump-rtl-expand" +Dump after \s-1RTL\s0 generation. +.IP "\fB\-fdump\-rtl\-fwprop1\fR" 4 +.IX Item "-fdump-rtl-fwprop1" +.PD 0 +.IP "\fB\-fdump\-rtl\-fwprop2\fR" 4 +.IX Item "-fdump-rtl-fwprop2" +.PD +\&\fB\-fdump\-rtl\-fwprop1\fR and \fB\-fdump\-rtl\-fwprop2\fR enable +dumping after the two forward propagation passes. +.IP "\fB\-fdump\-rtl\-gcse1\fR" 4 +.IX Item "-fdump-rtl-gcse1" +.PD 0 +.IP "\fB\-fdump\-rtl\-gcse2\fR" 4 +.IX Item "-fdump-rtl-gcse2" +.PD +\&\fB\-fdump\-rtl\-gcse1\fR and \fB\-fdump\-rtl\-gcse2\fR enable dumping +after global common subexpression elimination. +.IP "\fB\-fdump\-rtl\-init\-regs\fR" 4 +.IX Item "-fdump-rtl-init-regs" +Dump after the initialization of the registers. +.IP "\fB\-fdump\-rtl\-initvals\fR" 4 +.IX Item "-fdump-rtl-initvals" +Dump after the computation of the initial value sets. +.IP "\fB\-fdump\-rtl\-into_cfglayout\fR" 4 +.IX Item "-fdump-rtl-into_cfglayout" +Dump after converting to cfglayout mode. +.IP "\fB\-fdump\-rtl\-ira\fR" 4 +.IX Item "-fdump-rtl-ira" +Dump after iterated register allocation. +.IP "\fB\-fdump\-rtl\-jump\fR" 4 +.IX Item "-fdump-rtl-jump" +Dump after the second jump optimization. +.IP "\fB\-fdump\-rtl\-loop2\fR" 4 +.IX Item "-fdump-rtl-loop2" +\&\fB\-fdump\-rtl\-loop2\fR enables dumping after the rtl +loop optimization passes. +.IP "\fB\-fdump\-rtl\-mach\fR" 4 +.IX Item "-fdump-rtl-mach" +Dump after performing the machine dependent reorganization pass, if that +pass exists. +.IP "\fB\-fdump\-rtl\-mode_sw\fR" 4 +.IX Item "-fdump-rtl-mode_sw" +Dump after removing redundant mode switches. +.IP "\fB\-fdump\-rtl\-rnreg\fR" 4 +.IX Item "-fdump-rtl-rnreg" +Dump after register renumbering. +.IP "\fB\-fdump\-rtl\-outof_cfglayout\fR" 4 +.IX Item "-fdump-rtl-outof_cfglayout" +Dump after converting from cfglayout mode. +.IP "\fB\-fdump\-rtl\-peephole2\fR" 4 +.IX Item "-fdump-rtl-peephole2" +Dump after the peephole pass. +.IP "\fB\-fdump\-rtl\-postreload\fR" 4 +.IX Item "-fdump-rtl-postreload" +Dump after post-reload optimizations. +.IP "\fB\-fdump\-rtl\-pro_and_epilogue\fR" 4 +.IX Item "-fdump-rtl-pro_and_epilogue" +Dump after generating the function pro and epilogues. +.IP "\fB\-fdump\-rtl\-regmove\fR" 4 +.IX Item "-fdump-rtl-regmove" +Dump after the register move pass. +.IP "\fB\-fdump\-rtl\-sched1\fR" 4 +.IX Item "-fdump-rtl-sched1" +.PD 0 +.IP "\fB\-fdump\-rtl\-sched2\fR" 4 +.IX Item "-fdump-rtl-sched2" +.PD +\&\fB\-fdump\-rtl\-sched1\fR and \fB\-fdump\-rtl\-sched2\fR enable dumping +after the basic block scheduling passes. +.IP "\fB\-fdump\-rtl\-see\fR" 4 +.IX Item "-fdump-rtl-see" +Dump after sign extension elimination. +.IP "\fB\-fdump\-rtl\-seqabstr\fR" 4 +.IX Item "-fdump-rtl-seqabstr" +Dump after common sequence discovery. +.IP "\fB\-fdump\-rtl\-shorten\fR" 4 +.IX Item "-fdump-rtl-shorten" +Dump after shortening branches. +.IP "\fB\-fdump\-rtl\-sibling\fR" 4 +.IX Item "-fdump-rtl-sibling" +Dump after sibling call optimizations. +.IP "\fB\-fdump\-rtl\-split1\fR" 4 +.IX Item "-fdump-rtl-split1" +.PD 0 +.IP "\fB\-fdump\-rtl\-split2\fR" 4 +.IX Item "-fdump-rtl-split2" +.IP "\fB\-fdump\-rtl\-split3\fR" 4 +.IX Item "-fdump-rtl-split3" +.IP "\fB\-fdump\-rtl\-split4\fR" 4 +.IX Item "-fdump-rtl-split4" +.IP "\fB\-fdump\-rtl\-split5\fR" 4 +.IX Item "-fdump-rtl-split5" +.PD +\&\fB\-fdump\-rtl\-split1\fR, \fB\-fdump\-rtl\-split2\fR, +\&\fB\-fdump\-rtl\-split3\fR, \fB\-fdump\-rtl\-split4\fR and +\&\fB\-fdump\-rtl\-split5\fR enable dumping after five rounds of +instruction splitting. +.IP "\fB\-fdump\-rtl\-sms\fR" 4 +.IX Item "-fdump-rtl-sms" +Dump after modulo scheduling. This pass is only run on some +architectures. +.IP "\fB\-fdump\-rtl\-stack\fR" 4 +.IX Item "-fdump-rtl-stack" +Dump after conversion from \s-1GCC\s0's \*(L"flat register file\*(R" registers to the +x87's stack-like registers. This pass is only run on x86 variants. +.IP "\fB\-fdump\-rtl\-subreg1\fR" 4 +.IX Item "-fdump-rtl-subreg1" +.PD 0 +.IP "\fB\-fdump\-rtl\-subreg2\fR" 4 +.IX Item "-fdump-rtl-subreg2" +.PD +\&\fB\-fdump\-rtl\-subreg1\fR and \fB\-fdump\-rtl\-subreg2\fR enable dumping after +the two subreg expansion passes. +.IP "\fB\-fdump\-rtl\-unshare\fR" 4 +.IX Item "-fdump-rtl-unshare" +Dump after all rtl has been unshared. +.IP "\fB\-fdump\-rtl\-vartrack\fR" 4 +.IX Item "-fdump-rtl-vartrack" +Dump after variable tracking. +.IP "\fB\-fdump\-rtl\-vregs\fR" 4 +.IX Item "-fdump-rtl-vregs" +Dump after converting virtual registers to hard registers. +.IP "\fB\-fdump\-rtl\-web\fR" 4 +.IX Item "-fdump-rtl-web" +Dump after live range splitting. +.IP "\fB\-fdump\-rtl\-regclass\fR" 4 +.IX Item "-fdump-rtl-regclass" +.PD 0 +.IP "\fB\-fdump\-rtl\-subregs_of_mode_init\fR" 4 +.IX Item "-fdump-rtl-subregs_of_mode_init" +.IP "\fB\-fdump\-rtl\-subregs_of_mode_finish\fR" 4 +.IX Item "-fdump-rtl-subregs_of_mode_finish" +.IP "\fB\-fdump\-rtl\-dfinit\fR" 4 +.IX Item "-fdump-rtl-dfinit" +.IP "\fB\-fdump\-rtl\-dfinish\fR" 4 +.IX Item "-fdump-rtl-dfinish" +.PD +These dumps are defined but always produce empty files. +.IP "\fB\-fdump\-rtl\-all\fR" 4 +.IX Item "-fdump-rtl-all" +Produce all the dumps listed above. +.IP "\fB\-dA\fR" 4 +.IX Item "-dA" +Annotate the assembler output with miscellaneous debugging information. +.IP "\fB\-dD\fR" 4 +.IX Item "-dD" +Dump all macro definitions, at the end of preprocessing, in addition to +normal output. +.IP "\fB\-dH\fR" 4 +.IX Item "-dH" +Produce a core dump whenever an error occurs. +.IP "\fB\-dm\fR" 4 +.IX Item "-dm" +Print statistics on memory usage, at the end of the run, to +standard error. +.IP "\fB\-dp\fR" 4 +.IX Item "-dp" +Annotate the assembler output with a comment indicating which +pattern and alternative was used. The length of each instruction is +also printed. +.IP "\fB\-dP\fR" 4 +.IX Item "-dP" +Dump the \s-1RTL\s0 in the assembler output as a comment before each instruction. +Also turns on \fB\-dp\fR annotation. +.IP "\fB\-dv\fR" 4 +.IX Item "-dv" +For each of the other indicated dump files (\fB\-fdump\-rtl\-\fR\fIpass\fR), +dump a representation of the control flow graph suitable for viewing with \s-1VCG\s0 +to \fI\fIfile\fI.\fIpass\fI.vcg\fR. +.IP "\fB\-dx\fR" 4 +.IX Item "-dx" +Just generate \s-1RTL\s0 for a function instead of compiling it. Usually used +with \fB\-fdump\-rtl\-expand\fR. +.RE +.RS 4 +.RE +.IP "\fB\-fdump\-noaddr\fR" 4 +.IX Item "-fdump-noaddr" +When doing debugging dumps, suppress address output. This makes it more +feasible to use diff on debugging dumps for compiler invocations with +different compiler binaries and/or different +text / bss / data / heap / stack / dso start locations. +.IP "\fB\-fdump\-unnumbered\fR" 4 +.IX Item "-fdump-unnumbered" +When doing debugging dumps, suppress instruction numbers and address output. +This makes it more feasible to use diff on debugging dumps for compiler +invocations with different options, in particular with and without +\&\fB\-g\fR. +.IP "\fB\-fdump\-unnumbered\-links\fR" 4 +.IX Item "-fdump-unnumbered-links" +When doing debugging dumps (see \fB\-d\fR option above), suppress +instruction numbers for the links to the previous and next instructions +in a sequence. +.IP "\fB\-fdump\-translation\-unit\fR (\*(C+ only)" 4 +.IX Item "-fdump-translation-unit ( only)" +.PD 0 +.IP "\fB\-fdump\-translation\-unit\-\fR\fIoptions\fR\fB \fR(\*(C+ only)" 4 +.IX Item "-fdump-translation-unit-options ( only)" +.PD +Dump a representation of the tree structure for the entire translation +unit to a file. The file name is made by appending \fI.tu\fR to the +source file name, and the file is created in the same directory as the +output file. If the \fB\-\fR\fIoptions\fR form is used, \fIoptions\fR +controls the details of the dump as described for the +\&\fB\-fdump\-tree\fR options. +.IP "\fB\-fdump\-class\-hierarchy\fR (\*(C+ only)" 4 +.IX Item "-fdump-class-hierarchy ( only)" +.PD 0 +.IP "\fB\-fdump\-class\-hierarchy\-\fR\fIoptions\fR\fB \fR(\*(C+ only)" 4 +.IX Item "-fdump-class-hierarchy-options ( only)" +.PD +Dump a representation of each class's hierarchy and virtual function +table layout to a file. The file name is made by appending +\&\fI.class\fR to the source file name, and the file is created in the +same directory as the output file. If the \fB\-\fR\fIoptions\fR form +is used, \fIoptions\fR controls the details of the dump as described +for the \fB\-fdump\-tree\fR options. +.IP "\fB\-fdump\-ipa\-\fR\fIswitch\fR" 4 +.IX Item "-fdump-ipa-switch" +Control the dumping at various stages of inter-procedural analysis +language tree to a file. The file name is generated by appending a +switch specific suffix to the source file name, and the file is created +in the same directory as the output file. The following dumps are +possible: +.RS 4 +.IP "\fBall\fR" 4 +.IX Item "all" +Enables all inter-procedural analysis dumps. +.IP "\fBcgraph\fR" 4 +.IX Item "cgraph" +Dumps information about call-graph optimization, unused function removal, +and inlining decisions. +.IP "\fBinline\fR" 4 +.IX Item "inline" +Dump after function inlining. +.RE +.RS 4 +.RE +.IP "\fB\-fdump\-passes\fR" 4 +.IX Item "-fdump-passes" +Dump the list of optimization passes that are turned on and off by +the current command line options. +.IP "\fB\-fdump\-statistics\-\fR\fIoption\fR" 4 +.IX Item "-fdump-statistics-option" +Enable and control dumping of pass statistics in a separate file. The +file name is generated by appending a suffix ending in +\&\fB.statistics\fR to the source file name, and the file is created in +the same directory as the output file. If the \fB\-\fR\fIoption\fR +form is used, \fB\-stats\fR will cause counters to be summed over the +whole compilation unit while \fB\-details\fR will dump every event as +the passes generate them. The default with no option is to sum +counters for each function compiled. +.IP "\fB\-fdump\-tree\-\fR\fIswitch\fR" 4 +.IX Item "-fdump-tree-switch" +.PD 0 +.IP "\fB\-fdump\-tree\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR" 4 +.IX Item "-fdump-tree-switch-options" +.PD +Control the dumping at various stages of processing the intermediate +language tree to a file. The file name is generated by appending a +switch specific suffix to the source file name, and the file is +created in the same directory as the output file. If the +\&\fB\-\fR\fIoptions\fR form is used, \fIoptions\fR is a list of +\&\fB\-\fR separated options that control the details of the dump. Not +all options are applicable to all dumps, those which are not +meaningful will be ignored. The following options are available +.RS 4 +.IP "\fBaddress\fR" 4 +.IX Item "address" +Print the address of each node. Usually this is not meaningful as it +changes according to the environment and source file. Its primary use +is for tying up a dump file with a debug environment. +.IP "\fBasmname\fR" 4 +.IX Item "asmname" +If \f(CW\*(C`DECL_ASSEMBLER_NAME\*(C'\fR has been set for a given decl, use that +in the dump instead of \f(CW\*(C`DECL_NAME\*(C'\fR. Its primary use is ease of +use working backward from mangled names in the assembly file. +.IP "\fBslim\fR" 4 +.IX Item "slim" +Inhibit dumping of members of a scope or body of a function merely +because that scope has been reached. Only dump such items when they +are directly reachable by some other path. When dumping pretty-printed +trees, this option inhibits dumping the bodies of control structures. +.IP "\fBraw\fR" 4 +.IX Item "raw" +Print a raw representation of the tree. By default, trees are +pretty-printed into a C\-like representation. +.IP "\fBdetails\fR" 4 +.IX Item "details" +Enable more detailed dumps (not honored by every dump option). +.IP "\fBstats\fR" 4 +.IX Item "stats" +Enable dumping various statistics about the pass (not honored by every dump +option). +.IP "\fBblocks\fR" 4 +.IX Item "blocks" +Enable showing basic block boundaries (disabled in raw dumps). +.IP "\fBvops\fR" 4 +.IX Item "vops" +Enable showing virtual operands for every statement. +.IP "\fBlineno\fR" 4 +.IX Item "lineno" +Enable showing line numbers for statements. +.IP "\fBuid\fR" 4 +.IX Item "uid" +Enable showing the unique \s-1ID\s0 (\f(CW\*(C`DECL_UID\*(C'\fR) for each variable. +.IP "\fBverbose\fR" 4 +.IX Item "verbose" +Enable showing the tree dump for each statement. +.IP "\fBeh\fR" 4 +.IX Item "eh" +Enable showing the \s-1EH\s0 region number holding each statement. +.IP "\fBall\fR" 4 +.IX Item "all" +Turn on all options, except \fBraw\fR, \fBslim\fR, \fBverbose\fR +and \fBlineno\fR. +.RE +.RS 4 +.Sp +The following tree dumps are possible: +.IP "\fBoriginal\fR" 4 +.IX Item "original" +Dump before any tree based optimization, to \fI\fIfile\fI.original\fR. +.IP "\fBoptimized\fR" 4 +.IX Item "optimized" +Dump after all tree based optimization, to \fI\fIfile\fI.optimized\fR. +.IP "\fBgimple\fR" 4 +.IX Item "gimple" +Dump each function before and after the gimplification pass to a file. The +file name is made by appending \fI.gimple\fR to the source file name. +.IP "\fBcfg\fR" 4 +.IX Item "cfg" +Dump the control flow graph of each function to a file. The file name is +made by appending \fI.cfg\fR to the source file name. +.IP "\fBvcg\fR" 4 +.IX Item "vcg" +Dump the control flow graph of each function to a file in \s-1VCG\s0 format. The +file name is made by appending \fI.vcg\fR to the source file name. Note +that if the file contains more than one function, the generated file cannot +be used directly by \s-1VCG\s0. You will need to cut and paste each function's +graph into its own separate file first. +.IP "\fBch\fR" 4 +.IX Item "ch" +Dump each function after copying loop headers. The file name is made by +appending \fI.ch\fR to the source file name. +.IP "\fBssa\fR" 4 +.IX Item "ssa" +Dump \s-1SSA\s0 related information to a file. The file name is made by appending +\&\fI.ssa\fR to the source file name. +.IP "\fBalias\fR" 4 +.IX Item "alias" +Dump aliasing information for each function. The file name is made by +appending \fI.alias\fR to the source file name. +.IP "\fBccp\fR" 4 +.IX Item "ccp" +Dump each function after \s-1CCP\s0. The file name is made by appending +\&\fI.ccp\fR to the source file name. +.IP "\fBstoreccp\fR" 4 +.IX Item "storeccp" +Dump each function after STORE-CCP. The file name is made by appending +\&\fI.storeccp\fR to the source file name. +.IP "\fBpre\fR" 4 +.IX Item "pre" +Dump trees after partial redundancy elimination. The file name is made +by appending \fI.pre\fR to the source file name. +.IP "\fBfre\fR" 4 +.IX Item "fre" +Dump trees after full redundancy elimination. The file name is made +by appending \fI.fre\fR to the source file name. +.IP "\fBcopyprop\fR" 4 +.IX Item "copyprop" +Dump trees after copy propagation. The file name is made +by appending \fI.copyprop\fR to the source file name. +.IP "\fBstore_copyprop\fR" 4 +.IX Item "store_copyprop" +Dump trees after store copy-propagation. The file name is made +by appending \fI.store_copyprop\fR to the source file name. +.IP "\fBdce\fR" 4 +.IX Item "dce" +Dump each function after dead code elimination. The file name is made by +appending \fI.dce\fR to the source file name. +.IP "\fBmudflap\fR" 4 +.IX Item "mudflap" +Dump each function after adding mudflap instrumentation. The file name is +made by appending \fI.mudflap\fR to the source file name. +.IP "\fBsra\fR" 4 +.IX Item "sra" +Dump each function after performing scalar replacement of aggregates. The +file name is made by appending \fI.sra\fR to the source file name. +.IP "\fBsink\fR" 4 +.IX Item "sink" +Dump each function after performing code sinking. The file name is made +by appending \fI.sink\fR to the source file name. +.IP "\fBdom\fR" 4 +.IX Item "dom" +Dump each function after applying dominator tree optimizations. The file +name is made by appending \fI.dom\fR to the source file name. +.IP "\fBdse\fR" 4 +.IX Item "dse" +Dump each function after applying dead store elimination. The file +name is made by appending \fI.dse\fR to the source file name. +.IP "\fBphiopt\fR" 4 +.IX Item "phiopt" +Dump each function after optimizing \s-1PHI\s0 nodes into straightline code. The file +name is made by appending \fI.phiopt\fR to the source file name. +.IP "\fBforwprop\fR" 4 +.IX Item "forwprop" +Dump each function after forward propagating single use variables. The file +name is made by appending \fI.forwprop\fR to the source file name. +.IP "\fBcopyrename\fR" 4 +.IX Item "copyrename" +Dump each function after applying the copy rename optimization. The file +name is made by appending \fI.copyrename\fR to the source file name. +.IP "\fBnrv\fR" 4 +.IX Item "nrv" +Dump each function after applying the named return value optimization on +generic trees. The file name is made by appending \fI.nrv\fR to the source +file name. +.IP "\fBvect\fR" 4 +.IX Item "vect" +Dump each function after applying vectorization of loops. The file name is +made by appending \fI.vect\fR to the source file name. +.IP "\fBslp\fR" 4 +.IX Item "slp" +Dump each function after applying vectorization of basic blocks. The file name +is made by appending \fI.slp\fR to the source file name. +.IP "\fBvrp\fR" 4 +.IX Item "vrp" +Dump each function after Value Range Propagation (\s-1VRP\s0). The file name +is made by appending \fI.vrp\fR to the source file name. +.IP "\fBall\fR" 4 +.IX Item "all" +Enable all the available tree dumps with the flags provided in this option. +.RE +.RS 4 +.RE +.IP "\fB\-ftree\-vectorizer\-verbose=\fR\fIn\fR" 4 +.IX Item "-ftree-vectorizer-verbose=n" +This option controls the amount of debugging output the vectorizer prints. +This information is written to standard error, unless +\&\fB\-fdump\-tree\-all\fR or \fB\-fdump\-tree\-vect\fR is specified, +in which case it is output to the usual dump listing file, \fI.vect\fR. +For \fIn\fR=0 no diagnostic information is reported. +If \fIn\fR=1 the vectorizer reports each loop that got vectorized, +and the total number of loops that got vectorized. +If \fIn\fR=2 the vectorizer also reports non-vectorized loops that passed +the first analysis phase (vect_analyze_loop_form) \- i.e. countable, +inner-most, single-bb, single\-entry/exit loops. This is the same verbosity +level that \fB\-fdump\-tree\-vect\-stats\fR uses. +Higher verbosity levels mean either more information dumped for each +reported loop, or same amount of information reported for more loops: +if \fIn\fR=3, vectorizer cost model information is reported. +If \fIn\fR=4, alignment related information is added to the reports. +If \fIn\fR=5, data-references related information (e.g. memory dependences, +memory access-patterns) is added to the reports. +If \fIn\fR=6, the vectorizer reports also non-vectorized inner-most loops +that did not pass the first analysis phase (i.e., may not be countable, or +may have complicated control-flow). +If \fIn\fR=7, the vectorizer reports also non-vectorized nested loops. +If \fIn\fR=8, \s-1SLP\s0 related information is added to the reports. +For \fIn\fR=9, all the information the vectorizer generates during its +analysis and transformation is reported. This is the same verbosity level +that \fB\-fdump\-tree\-vect\-details\fR uses. +.IP "\fB\-frandom\-seed=\fR\fIstring\fR" 4 +.IX Item "-frandom-seed=string" +This option provides a seed that \s-1GCC\s0 uses when it would otherwise use +random numbers. It is used to generate certain symbol names +that have to be different in every compiled file. It is also used to +place unique stamps in coverage data files and the object files that +produce them. You can use the \fB\-frandom\-seed\fR option to produce +reproducibly identical object files. +.Sp +The \fIstring\fR should be different for every file you compile. +.IP "\fB\-fsched\-verbose=\fR\fIn\fR" 4 +.IX Item "-fsched-verbose=n" +On targets that use instruction scheduling, this option controls the +amount of debugging output the scheduler prints. This information is +written to standard error, unless \fB\-fdump\-rtl\-sched1\fR or +\&\fB\-fdump\-rtl\-sched2\fR is specified, in which case it is output +to the usual dump listing file, \fI.sched1\fR or \fI.sched2\fR +respectively. However for \fIn\fR greater than nine, the output is +always printed to standard error. +.Sp +For \fIn\fR greater than zero, \fB\-fsched\-verbose\fR outputs the +same information as \fB\-fdump\-rtl\-sched1\fR and \fB\-fdump\-rtl\-sched2\fR. +For \fIn\fR greater than one, it also output basic block probabilities, +detailed ready list information and unit/insn info. For \fIn\fR greater +than two, it includes \s-1RTL\s0 at abort point, control-flow and regions info. +And for \fIn\fR over four, \fB\-fsched\-verbose\fR also includes +dependence info. +.IP "\fB\-save\-temps\fR" 4 +.IX Item "-save-temps" +.PD 0 +.IP "\fB\-save\-temps=cwd\fR" 4 +.IX Item "-save-temps=cwd" +.PD +Store the usual \*(L"temporary\*(R" intermediate files permanently; place them +in the current directory and name them based on the source file. Thus, +compiling \fIfoo.c\fR with \fB\-c \-save\-temps\fR would produce files +\&\fIfoo.i\fR and \fIfoo.s\fR, as well as \fIfoo.o\fR. This creates a +preprocessed \fIfoo.i\fR output file even though the compiler now +normally uses an integrated preprocessor. +.Sp +When used in combination with the \fB\-x\fR command line option, +\&\fB\-save\-temps\fR is sensible enough to avoid over writing an +input source file with the same extension as an intermediate file. +The corresponding intermediate file may be obtained by renaming the +source file before using \fB\-save\-temps\fR. +.Sp +If you invoke \s-1GCC\s0 in parallel, compiling several different source +files that share a common base name in different subdirectories or the +same source file compiled for multiple output destinations, it is +likely that the different parallel compilers will interfere with each +other, and overwrite the temporary files. For instance: +.Sp +.Vb 2 +\& gcc \-save\-temps \-o outdir1/foo.o indir1/foo.c& +\& gcc \-save\-temps \-o outdir2/foo.o indir2/foo.c& +.Ve +.Sp +may result in \fIfoo.i\fR and \fIfoo.o\fR being written to +simultaneously by both compilers. +.IP "\fB\-save\-temps=obj\fR" 4 +.IX Item "-save-temps=obj" +Store the usual \*(L"temporary\*(R" intermediate files permanently. If the +\&\fB\-o\fR option is used, the temporary files are based on the +object file. If the \fB\-o\fR option is not used, the +\&\fB\-save\-temps=obj\fR switch behaves like \fB\-save\-temps\fR. +.Sp +For example: +.Sp +.Vb 3 +\& gcc \-save\-temps=obj \-c foo.c +\& gcc \-save\-temps=obj \-c bar.c \-o dir/xbar.o +\& gcc \-save\-temps=obj foobar.c \-o dir2/yfoobar +.Ve +.Sp +would create \fIfoo.i\fR, \fIfoo.s\fR, \fIdir/xbar.i\fR, +\&\fIdir/xbar.s\fR, \fIdir2/yfoobar.i\fR, \fIdir2/yfoobar.s\fR, and +\&\fIdir2/yfoobar.o\fR. +.IP "\fB\-time\fR[\fB=\fR\fIfile\fR]" 4 +.IX Item "-time[=file]" +Report the \s-1CPU\s0 time taken by each subprocess in the compilation +sequence. For C source files, this is the compiler proper and assembler +(plus the linker if linking is done). +.Sp +Without the specification of an output file, the output looks like this: +.Sp +.Vb 2 +\& # cc1 0.12 0.01 +\& # as 0.00 0.01 +.Ve +.Sp +The first number on each line is the \*(L"user time\*(R", that is time spent +executing the program itself. The second number is \*(L"system time\*(R", +time spent executing operating system routines on behalf of the program. +Both numbers are in seconds. +.Sp +With the specification of an output file, the output is appended to the +named file, and it looks like this: +.Sp +.Vb 2 +\& 0.12 0.01 cc1 <options> +\& 0.00 0.01 as <options> +.Ve +.Sp +The \*(L"user time\*(R" and the \*(L"system time\*(R" are moved before the program +name, and the options passed to the program are displayed, so that one +can later tell what file was being compiled, and with which options. +.IP "\fB\-fvar\-tracking\fR" 4 +.IX Item "-fvar-tracking" +Run variable tracking pass. It computes where variables are stored at each +position in code. Better debugging information is then generated +(if the debugging information format supports this information). +.Sp +It is enabled by default when compiling with optimization (\fB\-Os\fR, +\&\fB\-O\fR, \fB\-O2\fR, ...), debugging information (\fB\-g\fR) and +the debug info format supports it. +.IP "\fB\-fvar\-tracking\-assignments\fR" 4 +.IX Item "-fvar-tracking-assignments" +Annotate assignments to user variables early in the compilation and +attempt to carry the annotations over throughout the compilation all the +way to the end, in an attempt to improve debug information while +optimizing. Use of \fB\-gdwarf\-4\fR is recommended along with it. +.Sp +It can be enabled even if var-tracking is disabled, in which case +annotations will be created and maintained, but discarded at the end. +.IP "\fB\-fvar\-tracking\-assignments\-toggle\fR" 4 +.IX Item "-fvar-tracking-assignments-toggle" +Toggle \fB\-fvar\-tracking\-assignments\fR, in the same way that +\&\fB\-gtoggle\fR toggles \fB\-g\fR. +.IP "\fB\-print\-file\-name=\fR\fIlibrary\fR" 4 +.IX Item "-print-file-name=library" +Print the full absolute name of the library file \fIlibrary\fR that +would be used when linking\-\-\-and don't do anything else. With this +option, \s-1GCC\s0 does not compile or link anything; it just prints the +file name. +.IP "\fB\-print\-multi\-directory\fR" 4 +.IX Item "-print-multi-directory" +Print the directory name corresponding to the multilib selected by any +other switches present in the command line. This directory is supposed +to exist in \fB\s-1GCC_EXEC_PREFIX\s0\fR. +.IP "\fB\-print\-multi\-lib\fR" 4 +.IX Item "-print-multi-lib" +Print the mapping from multilib directory names to compiler switches +that enable them. The directory name is separated from the switches by +\&\fB;\fR, and each switch starts with an \fB@\fR instead of the +\&\fB\-\fR, without spaces between multiple switches. This is supposed to +ease shell-processing. +.IP "\fB\-print\-multi\-os\-directory\fR" 4 +.IX Item "-print-multi-os-directory" +Print the path to \s-1OS\s0 libraries for the selected +multilib, relative to some \fIlib\fR subdirectory. If \s-1OS\s0 libraries are +present in the \fIlib\fR subdirectory and no multilibs are used, this is +usually just \fI.\fR, if \s-1OS\s0 libraries are present in \fIlib\fIsuffix\fI\fR +sibling directories this prints e.g. \fI../lib64\fR, \fI../lib\fR or +\&\fI../lib32\fR, or if \s-1OS\s0 libraries are present in \fIlib/\fIsubdir\fI\fR +subdirectories it prints e.g. \fIamd64\fR, \fIsparcv9\fR or \fIev6\fR. +.IP "\fB\-print\-prog\-name=\fR\fIprogram\fR" 4 +.IX Item "-print-prog-name=program" +Like \fB\-print\-file\-name\fR, but searches for a program such as \fBcpp\fR. +.IP "\fB\-print\-libgcc\-file\-name\fR" 4 +.IX Item "-print-libgcc-file-name" +Same as \fB\-print\-file\-name=libgcc.a\fR. +.Sp +This is useful when you use \fB\-nostdlib\fR or \fB\-nodefaultlibs\fR +but you do want to link with \fIlibgcc.a\fR. You can do +.Sp +.Vb 1 +\& gcc \-nostdlib <files>... \`gcc \-print\-libgcc\-file\-name\` +.Ve +.IP "\fB\-print\-search\-dirs\fR" 4 +.IX Item "-print-search-dirs" +Print the name of the configured installation directory and a list of +program and library directories \fBgcc\fR will search\-\-\-and don't do anything else. +.Sp +This is useful when \fBgcc\fR prints the error message +\&\fBinstallation problem, cannot exec cpp0: No such file or directory\fR. +To resolve this you either need to put \fIcpp0\fR and the other compiler +components where \fBgcc\fR expects to find them, or you can set the environment +variable \fB\s-1GCC_EXEC_PREFIX\s0\fR to the directory where you installed them. +Don't forget the trailing \fB/\fR. +.IP "\fB\-print\-sysroot\fR" 4 +.IX Item "-print-sysroot" +Print the target sysroot directory that will be used during +compilation. This is the target sysroot specified either at configure +time or using the \fB\-\-sysroot\fR option, possibly with an extra +suffix that depends on compilation options. If no target sysroot is +specified, the option prints nothing. +.IP "\fB\-print\-sysroot\-headers\-suffix\fR" 4 +.IX Item "-print-sysroot-headers-suffix" +Print the suffix added to the target sysroot when searching for +headers, or give an error if the compiler is not configured with such +a suffix\-\-\-and don't do anything else. +.IP "\fB\-dumpmachine\fR" 4 +.IX Item "-dumpmachine" +Print the compiler's target machine (for example, +\&\fBi686\-pc\-linux\-gnu\fR)\-\-\-and don't do anything else. +.IP "\fB\-dumpversion\fR" 4 +.IX Item "-dumpversion" +Print the compiler version (for example, \fB3.0\fR)\-\-\-and don't do +anything else. +.IP "\fB\-dumpspecs\fR" 4 +.IX Item "-dumpspecs" +Print the compiler's built-in specs\-\-\-and don't do anything else. (This +is used when \s-1GCC\s0 itself is being built.) +.IP "\fB\-feliminate\-unused\-debug\-types\fR" 4 +.IX Item "-feliminate-unused-debug-types" +Normally, when producing \s-1DWARF2\s0 output, \s-1GCC\s0 will emit debugging +information for all types declared in a compilation +unit, regardless of whether or not they are actually used +in that compilation unit. Sometimes this is useful, such as +if, in the debugger, you want to cast a value to a type that is +not actually used in your program (but is declared). More often, +however, this results in a significant amount of wasted space. +With this option, \s-1GCC\s0 will avoid producing debug symbol output +for types that are nowhere used in the source file being compiled. +.SS "Options That Control Optimization" +.IX Subsection "Options That Control Optimization" +These options control various sorts of optimizations. +.PP +Without any optimization option, the compiler's goal is to reduce the +cost of compilation and to make debugging produce the expected +results. Statements are independent: if you stop the program with a +breakpoint between statements, you can then assign a new value to any +variable or change the program counter to any other statement in the +function and get exactly the results you would expect from the source +code. +.PP +Turning on optimization flags makes the compiler attempt to improve +the performance and/or code size at the expense of compilation time +and possibly the ability to debug the program. +.PP +The compiler performs optimization based on the knowledge it has of the +program. Compiling multiple files at once to a single output file mode allows +the compiler to use information gained from all of the files when compiling +each of them. +.PP +Not all optimizations are controlled directly by a flag. Only +optimizations that have a flag are listed in this section. +.PP +Most optimizations are only enabled if an \fB\-O\fR level is set on +the command line. Otherwise they are disabled, even if individual +optimization flags are specified. +.PP +Depending on the target and how \s-1GCC\s0 was configured, a slightly different +set of optimizations may be enabled at each \fB\-O\fR level than +those listed here. You can invoke \s-1GCC\s0 with \fB\-Q \-\-help=optimizers\fR +to find out the exact set of optimizations that are enabled at each level. +.IP "\fB\-O\fR" 4 +.IX Item "-O" +.PD 0 +.IP "\fB\-O1\fR" 4 +.IX Item "-O1" +.PD +Optimize. Optimizing compilation takes somewhat more time, and a lot +more memory for a large function. +.Sp +With \fB\-O\fR, the compiler tries to reduce code size and execution +time, without performing any optimizations that take a great deal of +compilation time. +.Sp +\&\fB\-O\fR turns on the following optimization flags: +.Sp +\&\fB\-fauto\-inc\-dec +\&\-fcompare\-elim +\&\-fcprop\-registers +\&\-fdce +\&\-fdefer\-pop +\&\-fdelayed\-branch +\&\-fdse +\&\-fguess\-branch\-probability +\&\-fif\-conversion2 +\&\-fif\-conversion +\&\-fipa\-pure\-const +\&\-fipa\-profile +\&\-fipa\-reference +\&\-fmerge\-constants +\&\-fsplit\-wide\-types +\&\-ftree\-bit\-ccp +\&\-ftree\-builtin\-call\-dce +\&\-ftree\-ccp +\&\-ftree\-ch +\&\-ftree\-copyrename +\&\-ftree\-dce +\&\-ftree\-dominator\-opts +\&\-ftree\-dse +\&\-ftree\-forwprop +\&\-ftree\-fre +\&\-ftree\-phiprop +\&\-ftree\-sra +\&\-ftree\-pta +\&\-ftree\-ter +\&\-funit\-at\-a\-time\fR +.Sp +\&\fB\-O\fR also turns on \fB\-fomit\-frame\-pointer\fR on machines +where doing so does not interfere with debugging. +.IP "\fB\-O2\fR" 4 +.IX Item "-O2" +Optimize even more. \s-1GCC\s0 performs nearly all supported optimizations +that do not involve a space-speed tradeoff. +As compared to \fB\-O\fR, this option increases both compilation time +and the performance of the generated code. +.Sp +\&\fB\-O2\fR turns on all optimization flags specified by \fB\-O\fR. It +also turns on the following optimization flags: +\&\fB\-fthread\-jumps +\&\-falign\-functions \-falign\-jumps +\&\-falign\-loops \-falign\-labels +\&\-fcaller\-saves +\&\-fcrossjumping +\&\-fcse\-follow\-jumps \-fcse\-skip\-blocks +\&\-fdelete\-null\-pointer\-checks +\&\-fdevirtualize +\&\-fexpensive\-optimizations +\&\-fgcse \-fgcse\-lm +\&\-finline\-small\-functions +\&\-findirect\-inlining +\&\-fipa\-sra +\&\-foptimize\-sibling\-calls +\&\-fpartial\-inlining +\&\-fpeephole2 +\&\-fregmove +\&\-freorder\-blocks \-freorder\-functions +\&\-frerun\-cse\-after\-loop +\&\-fsched\-interblock \-fsched\-spec +\&\-fschedule\-insns \-fschedule\-insns2 +\&\-fstrict\-aliasing \-fstrict\-overflow +\&\-ftree\-switch\-conversion +\&\-ftree\-pre +\&\-ftree\-vrp\fR +.Sp +Please note the warning under \fB\-fgcse\fR about +invoking \fB\-O2\fR on programs that use computed gotos. +.IP "\fB\-O3\fR" 4 +.IX Item "-O3" +Optimize yet more. \fB\-O3\fR turns on all optimizations specified +by \fB\-O2\fR and also turns on the \fB\-finline\-functions\fR, +\&\fB\-funswitch\-loops\fR, \fB\-fpredictive\-commoning\fR, +\&\fB\-fgcse\-after\-reload\fR, \fB\-ftree\-vectorize\fR and +\&\fB\-fipa\-cp\-clone\fR options. +.IP "\fB\-O0\fR" 4 +.IX Item "-O0" +Reduce compilation time and make debugging produce the expected +results. This is the default. +.IP "\fB\-Os\fR" 4 +.IX Item "-Os" +Optimize for size. \fB\-Os\fR enables all \fB\-O2\fR optimizations that +do not typically increase code size. It also performs further +optimizations designed to reduce code size. +.Sp +\&\fB\-Os\fR disables the following optimization flags: +\&\fB\-falign\-functions \-falign\-jumps \-falign\-loops +\&\-falign\-labels \-freorder\-blocks \-freorder\-blocks\-and\-partition +\&\-fprefetch\-loop\-arrays \-ftree\-vect\-loop\-version\fR +.IP "\fB\-Ofast\fR" 4 +.IX Item "-Ofast" +Disregard strict standards compliance. \fB\-Ofast\fR enables all +\&\fB\-O3\fR optimizations. It also enables optimizations that are not +valid for all standard compliant programs. +It turns on \fB\-ffast\-math\fR. +.Sp +If you use multiple \fB\-O\fR options, with or without level numbers, +the last such option is the one that is effective. +.PP +Options of the form \fB\-f\fR\fIflag\fR specify machine-independent +flags. Most flags have both positive and negative forms; the negative +form of \fB\-ffoo\fR would be \fB\-fno\-foo\fR. In the table +below, only one of the forms is listed\-\-\-the one you typically will +use. You can figure out the other form by either removing \fBno\-\fR +or adding it. +.PP +The following options control specific optimizations. They are either +activated by \fB\-O\fR options or are related to ones that are. You +can use the following flags in the rare cases when \*(L"fine-tuning\*(R" of +optimizations to be performed is desired. +.IP "\fB\-fno\-default\-inline\fR" 4 +.IX Item "-fno-default-inline" +Do not make member functions inline by default merely because they are +defined inside the class scope (\*(C+ only). Otherwise, when you specify +\&\fB\-O\fR, member functions defined inside class scope are compiled +inline by default; i.e., you don't need to add \fBinline\fR in front of +the member function name. +.IP "\fB\-fno\-defer\-pop\fR" 4 +.IX Item "-fno-defer-pop" +Always pop the arguments to each function call as soon as that function +returns. For machines which must pop arguments after a function call, +the compiler normally lets arguments accumulate on the stack for several +function calls and pops them all at once. +.Sp +Disabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fforward\-propagate\fR" 4 +.IX Item "-fforward-propagate" +Perform a forward propagation pass on \s-1RTL\s0. The pass tries to combine two +instructions and checks if the result can be simplified. If loop unrolling +is active, two passes are performed and the second is scheduled after +loop unrolling. +.Sp +This option is enabled by default at optimization levels \fB\-O\fR, +\&\fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-ffp\-contract=\fR\fIstyle\fR" 4 +.IX Item "-ffp-contract=style" +\&\fB\-ffp\-contract=off\fR disables floating-point expression contraction. +\&\fB\-ffp\-contract=fast\fR enables floating-point expression contraction +such as forming of fused multiply-add operations if the target has +native support for them. +\&\fB\-ffp\-contract=on\fR enables floating-point expression contraction +if allowed by the language standard. This is currently not implemented +and treated equal to \fB\-ffp\-contract=off\fR. +.Sp +The default is \fB\-ffp\-contract=fast\fR. +.IP "\fB\-fomit\-frame\-pointer\fR" 4 +.IX Item "-fomit-frame-pointer" +Don't keep the frame pointer in a register for functions that +don't need one. This avoids the instructions to save, set up and +restore frame pointers; it also makes an extra register available +in many functions. \fBIt also makes debugging impossible on +some machines.\fR +.Sp +On some machines, such as the \s-1VAX\s0, this flag has no effect, because +the standard calling sequence automatically handles the frame pointer +and nothing is saved by pretending it doesn't exist. The +machine-description macro \f(CW\*(C`FRAME_POINTER_REQUIRED\*(C'\fR controls +whether a target machine supports this flag. +.Sp +Starting with \s-1GCC\s0 version 4.6, the default setting (when not optimizing for +size) for 32\-bit Linux x86 and 32\-bit Darwin x86 targets has been changed to +\&\fB\-fomit\-frame\-pointer\fR. The default can be reverted to +\&\fB\-fno\-omit\-frame\-pointer\fR by configuring \s-1GCC\s0 with the +\&\fB\-\-enable\-frame\-pointer\fR configure option. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-foptimize\-sibling\-calls\fR" 4 +.IX Item "-foptimize-sibling-calls" +Optimize sibling and tail recursive calls. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fno\-inline\fR" 4 +.IX Item "-fno-inline" +Don't pay attention to the \f(CW\*(C`inline\*(C'\fR keyword. Normally this option +is used to keep the compiler from expanding any functions inline. +Note that if you are not optimizing, no functions can be expanded inline. +.IP "\fB\-finline\-small\-functions\fR" 4 +.IX Item "-finline-small-functions" +Integrate functions into their callers when their body is smaller than expected +function call code (so overall size of program gets smaller). The compiler +heuristically decides which functions are simple enough to be worth integrating +in this way. +.Sp +Enabled at level \fB\-O2\fR. +.IP "\fB\-findirect\-inlining\fR" 4 +.IX Item "-findirect-inlining" +Inline also indirect calls that are discovered to be known at compile +time thanks to previous inlining. This option has any effect only +when inlining itself is turned on by the \fB\-finline\-functions\fR +or \fB\-finline\-small\-functions\fR options. +.Sp +Enabled at level \fB\-O2\fR. +.IP "\fB\-finline\-functions\fR" 4 +.IX Item "-finline-functions" +Integrate all simple functions into their callers. The compiler +heuristically decides which functions are simple enough to be worth +integrating in this way. +.Sp +If all calls to a given function are integrated, and the function is +declared \f(CW\*(C`static\*(C'\fR, then the function is normally not output as +assembler code in its own right. +.Sp +Enabled at level \fB\-O3\fR. +.IP "\fB\-finline\-functions\-called\-once\fR" 4 +.IX Item "-finline-functions-called-once" +Consider all \f(CW\*(C`static\*(C'\fR functions called once for inlining into their +caller even if they are not marked \f(CW\*(C`inline\*(C'\fR. If a call to a given +function is integrated, then the function is not output as assembler code +in its own right. +.Sp +Enabled at levels \fB\-O1\fR, \fB\-O2\fR, \fB\-O3\fR and \fB\-Os\fR. +.IP "\fB\-fearly\-inlining\fR" 4 +.IX Item "-fearly-inlining" +Inline functions marked by \f(CW\*(C`always_inline\*(C'\fR and functions whose body seems +smaller than the function call overhead early before doing +\&\fB\-fprofile\-generate\fR instrumentation and real inlining pass. Doing so +makes profiling significantly cheaper and usually inlining faster on programs +having large chains of nested wrapper functions. +.Sp +Enabled by default. +.IP "\fB\-fipa\-sra\fR" 4 +.IX Item "-fipa-sra" +Perform interprocedural scalar replacement of aggregates, removal of +unused parameters and replacement of parameters passed by reference +by parameters passed by value. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR and \fB\-Os\fR. +.IP "\fB\-finline\-limit=\fR\fIn\fR" 4 +.IX Item "-finline-limit=n" +By default, \s-1GCC\s0 limits the size of functions that can be inlined. This flag +allows coarse control of this limit. \fIn\fR is the size of functions that +can be inlined in number of pseudo instructions. +.Sp +Inlining is actually controlled by a number of parameters, which may be +specified individually by using \fB\-\-param\fR \fIname\fR\fB=\fR\fIvalue\fR. +The \fB\-finline\-limit=\fR\fIn\fR option sets some of these parameters +as follows: +.RS 4 +.IP "\fBmax-inline-insns-single\fR" 4 +.IX Item "max-inline-insns-single" +is set to \fIn\fR/2. +.IP "\fBmax-inline-insns-auto\fR" 4 +.IX Item "max-inline-insns-auto" +is set to \fIn\fR/2. +.RE +.RS 4 +.Sp +See below for a documentation of the individual +parameters controlling inlining and for the defaults of these parameters. +.Sp +\&\fINote:\fR there may be no value to \fB\-finline\-limit\fR that results +in default behavior. +.Sp +\&\fINote:\fR pseudo instruction represents, in this particular context, an +abstract measurement of function's size. In no way does it represent a count +of assembly instructions and as such its exact meaning might change from one +release to an another. +.RE +.IP "\fB\-fno\-keep\-inline\-dllexport\fR" 4 +.IX Item "-fno-keep-inline-dllexport" +This is a more fine-grained version of \fB\-fkeep\-inline\-functions\fR, +which applies only to functions that are declared using the \f(CW\*(C`dllexport\*(C'\fR +attribute or declspec +.IP "\fB\-fkeep\-inline\-functions\fR" 4 +.IX Item "-fkeep-inline-functions" +In C, emit \f(CW\*(C`static\*(C'\fR functions that are declared \f(CW\*(C`inline\*(C'\fR +into the object file, even if the function has been inlined into all +of its callers. This switch does not affect functions using the +\&\f(CW\*(C`extern inline\*(C'\fR extension in \s-1GNU\s0 C90. In \*(C+, emit any and all +inline functions into the object file. +.IP "\fB\-fkeep\-static\-consts\fR" 4 +.IX Item "-fkeep-static-consts" +Emit variables declared \f(CW\*(C`static const\*(C'\fR when optimization isn't turned +on, even if the variables aren't referenced. +.Sp +\&\s-1GCC\s0 enables this option by default. If you want to force the compiler to +check if the variable was referenced, regardless of whether or not +optimization is turned on, use the \fB\-fno\-keep\-static\-consts\fR option. +.IP "\fB\-fmerge\-constants\fR" 4 +.IX Item "-fmerge-constants" +Attempt to merge identical constants (string constants and floating point +constants) across compilation units. +.Sp +This option is the default for optimized compilation if the assembler and +linker support it. Use \fB\-fno\-merge\-constants\fR to inhibit this +behavior. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fmerge\-all\-constants\fR" 4 +.IX Item "-fmerge-all-constants" +Attempt to merge identical constants and identical variables. +.Sp +This option implies \fB\-fmerge\-constants\fR. In addition to +\&\fB\-fmerge\-constants\fR this considers e.g. even constant initialized +arrays or initialized constant variables with integral or floating point +types. Languages like C or \*(C+ require each variable, including multiple +instances of the same variable in recursive calls, to have distinct locations, +so using this option will result in non-conforming +behavior. +.IP "\fB\-fmodulo\-sched\fR" 4 +.IX Item "-fmodulo-sched" +Perform swing modulo scheduling immediately before the first scheduling +pass. This pass looks at innermost loops and reorders their +instructions by overlapping different iterations. +.IP "\fB\-fmodulo\-sched\-allow\-regmoves\fR" 4 +.IX Item "-fmodulo-sched-allow-regmoves" +Perform more aggressive \s-1SMS\s0 based modulo scheduling with register moves +allowed. By setting this flag certain anti-dependences edges will be +deleted which will trigger the generation of reg-moves based on the +life-range analysis. This option is effective only with +\&\fB\-fmodulo\-sched\fR enabled. +.IP "\fB\-fno\-branch\-count\-reg\fR" 4 +.IX Item "-fno-branch-count-reg" +Do not use \*(L"decrement and branch\*(R" instructions on a count register, +but instead generate a sequence of instructions that decrement a +register, compare it against zero, then branch based upon the result. +This option is only meaningful on architectures that support such +instructions, which include x86, PowerPC, \s-1IA\-64\s0 and S/390. +.Sp +The default is \fB\-fbranch\-count\-reg\fR. +.IP "\fB\-fno\-function\-cse\fR" 4 +.IX Item "-fno-function-cse" +Do not put function addresses in registers; make each instruction that +calls a constant function contain the function's address explicitly. +.Sp +This option results in less efficient code, but some strange hacks +that alter the assembler output may be confused by the optimizations +performed when this option is not used. +.Sp +The default is \fB\-ffunction\-cse\fR +.IP "\fB\-fno\-zero\-initialized\-in\-bss\fR" 4 +.IX Item "-fno-zero-initialized-in-bss" +If the target supports a \s-1BSS\s0 section, \s-1GCC\s0 by default puts variables that +are initialized to zero into \s-1BSS\s0. This can save space in the resulting +code. +.Sp +This option turns off this behavior because some programs explicitly +rely on variables going to the data section. E.g., so that the +resulting executable can find the beginning of that section and/or make +assumptions based on that. +.Sp +The default is \fB\-fzero\-initialized\-in\-bss\fR. +.IP "\fB\-fmudflap \-fmudflapth \-fmudflapir\fR" 4 +.IX Item "-fmudflap -fmudflapth -fmudflapir" +For front-ends that support it (C and \*(C+), instrument all risky +pointer/array dereferencing operations, some standard library +string/heap functions, and some other associated constructs with +range/validity tests. Modules so instrumented should be immune to +buffer overflows, invalid heap use, and some other classes of C/\*(C+ +programming errors. The instrumentation relies on a separate runtime +library (\fIlibmudflap\fR), which will be linked into a program if +\&\fB\-fmudflap\fR is given at link time. Run-time behavior of the +instrumented program is controlled by the \fB\s-1MUDFLAP_OPTIONS\s0\fR +environment variable. See \f(CW\*(C`env MUDFLAP_OPTIONS=\-help a.out\*(C'\fR +for its options. +.Sp +Use \fB\-fmudflapth\fR instead of \fB\-fmudflap\fR to compile and to +link if your program is multi-threaded. Use \fB\-fmudflapir\fR, in +addition to \fB\-fmudflap\fR or \fB\-fmudflapth\fR, if +instrumentation should ignore pointer reads. This produces less +instrumentation (and therefore faster execution) and still provides +some protection against outright memory corrupting writes, but allows +erroneously read data to propagate within a program. +.IP "\fB\-fthread\-jumps\fR" 4 +.IX Item "-fthread-jumps" +Perform optimizations where we check to see if a jump branches to a +location where another comparison subsumed by the first is found. If +so, the first branch is redirected to either the destination of the +second branch or a point immediately following it, depending on whether +the condition is known to be true or false. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fsplit\-wide\-types\fR" 4 +.IX Item "-fsplit-wide-types" +When using a type that occupies multiple registers, such as \f(CW\*(C`long +long\*(C'\fR on a 32\-bit system, split the registers apart and allocate them +independently. This normally generates better code for those types, +but may make debugging more difficult. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, +\&\fB\-Os\fR. +.IP "\fB\-fcse\-follow\-jumps\fR" 4 +.IX Item "-fcse-follow-jumps" +In common subexpression elimination (\s-1CSE\s0), scan through jump instructions +when the target of the jump is not reached by any other path. For +example, when \s-1CSE\s0 encounters an \f(CW\*(C`if\*(C'\fR statement with an +\&\f(CW\*(C`else\*(C'\fR clause, \s-1CSE\s0 will follow the jump when the condition +tested is false. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fcse\-skip\-blocks\fR" 4 +.IX Item "-fcse-skip-blocks" +This is similar to \fB\-fcse\-follow\-jumps\fR, but causes \s-1CSE\s0 to +follow jumps which conditionally skip over blocks. When \s-1CSE\s0 +encounters a simple \f(CW\*(C`if\*(C'\fR statement with no else clause, +\&\fB\-fcse\-skip\-blocks\fR causes \s-1CSE\s0 to follow the jump around the +body of the \f(CW\*(C`if\*(C'\fR. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-frerun\-cse\-after\-loop\fR" 4 +.IX Item "-frerun-cse-after-loop" +Re-run common subexpression elimination after loop optimizations has been +performed. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fgcse\fR" 4 +.IX Item "-fgcse" +Perform a global common subexpression elimination pass. +This pass also performs global constant and copy propagation. +.Sp +\&\fINote:\fR When compiling a program using computed gotos, a \s-1GCC\s0 +extension, you may get better runtime performance if you disable +the global common subexpression elimination pass by adding +\&\fB\-fno\-gcse\fR to the command line. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fgcse\-lm\fR" 4 +.IX Item "-fgcse-lm" +When \fB\-fgcse\-lm\fR is enabled, global common subexpression elimination will +attempt to move loads which are only killed by stores into themselves. This +allows a loop containing a load/store sequence to be changed to a load outside +the loop, and a copy/store within the loop. +.Sp +Enabled by default when gcse is enabled. +.IP "\fB\-fgcse\-sm\fR" 4 +.IX Item "-fgcse-sm" +When \fB\-fgcse\-sm\fR is enabled, a store motion pass is run after +global common subexpression elimination. This pass will attempt to move +stores out of loops. When used in conjunction with \fB\-fgcse\-lm\fR, +loops containing a load/store sequence can be changed to a load before +the loop and a store after the loop. +.Sp +Not enabled at any optimization level. +.IP "\fB\-fgcse\-las\fR" 4 +.IX Item "-fgcse-las" +When \fB\-fgcse\-las\fR is enabled, the global common subexpression +elimination pass eliminates redundant loads that come after stores to the +same memory location (both partial and full redundancies). +.Sp +Not enabled at any optimization level. +.IP "\fB\-fgcse\-after\-reload\fR" 4 +.IX Item "-fgcse-after-reload" +When \fB\-fgcse\-after\-reload\fR is enabled, a redundant load elimination +pass is performed after reload. The purpose of this pass is to cleanup +redundant spilling. +.IP "\fB\-funsafe\-loop\-optimizations\fR" 4 +.IX Item "-funsafe-loop-optimizations" +If given, the loop optimizer will assume that loop indices do not +overflow, and that the loops with nontrivial exit condition are not +infinite. This enables a wider range of loop optimizations even if +the loop optimizer itself cannot prove that these assumptions are valid. +Using \fB\-Wunsafe\-loop\-optimizations\fR, the compiler will warn you +if it finds this kind of loop. +.IP "\fB\-fcrossjumping\fR" 4 +.IX Item "-fcrossjumping" +Perform cross-jumping transformation. This transformation unifies equivalent code and save code size. The +resulting code may or may not perform better than without cross-jumping. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fauto\-inc\-dec\fR" 4 +.IX Item "-fauto-inc-dec" +Combine increments or decrements of addresses with memory accesses. +This pass is always skipped on architectures that do not have +instructions to support this. Enabled by default at \fB\-O\fR and +higher on architectures that support this. +.IP "\fB\-fdce\fR" 4 +.IX Item "-fdce" +Perform dead code elimination (\s-1DCE\s0) on \s-1RTL\s0. +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fdse\fR" 4 +.IX Item "-fdse" +Perform dead store elimination (\s-1DSE\s0) on \s-1RTL\s0. +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fif\-conversion\fR" 4 +.IX Item "-fif-conversion" +Attempt to transform conditional jumps into branch-less equivalents. This +include use of conditional moves, min, max, set flags and abs instructions, and +some tricks doable by standard arithmetics. The use of conditional execution +on chips where it is available is controlled by \f(CW\*(C`if\-conversion2\*(C'\fR. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fif\-conversion2\fR" 4 +.IX Item "-fif-conversion2" +Use conditional execution (where available) to transform conditional jumps into +branch-less equivalents. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fdelete\-null\-pointer\-checks\fR" 4 +.IX Item "-fdelete-null-pointer-checks" +Assume that programs cannot safely dereference null pointers, and that +no code or data element resides there. This enables simple constant +folding optimizations at all optimization levels. In addition, other +optimization passes in \s-1GCC\s0 use this flag to control global dataflow +analyses that eliminate useless checks for null pointers; these assume +that if a pointer is checked after it has already been dereferenced, +it cannot be null. +.Sp +Note however that in some environments this assumption is not true. +Use \fB\-fno\-delete\-null\-pointer\-checks\fR to disable this optimization +for programs which depend on that behavior. +.Sp +Some targets, especially embedded ones, disable this option at all levels. +Otherwise it is enabled at all levels: \fB\-O0\fR, \fB\-O1\fR, +\&\fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. Passes that use the information +are enabled independently at different optimization levels. +.IP "\fB\-fdevirtualize\fR" 4 +.IX Item "-fdevirtualize" +Attempt to convert calls to virtual functions to direct calls. This +is done both within a procedure and interprocedurally as part of +indirect inlining (\f(CW\*(C`\-findirect\-inlining\*(C'\fR) and interprocedural constant +propagation (\fB\-fipa\-cp\fR). +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fexpensive\-optimizations\fR" 4 +.IX Item "-fexpensive-optimizations" +Perform a number of minor optimizations that are relatively expensive. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-foptimize\-register\-move\fR" 4 +.IX Item "-foptimize-register-move" +.PD 0 +.IP "\fB\-fregmove\fR" 4 +.IX Item "-fregmove" +.PD +Attempt to reassign register numbers in move instructions and as +operands of other simple instructions in order to maximize the amount of +register tying. This is especially helpful on machines with two-operand +instructions. +.Sp +Note \fB\-fregmove\fR and \fB\-foptimize\-register\-move\fR are the same +optimization. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fira\-algorithm=\fR\fIalgorithm\fR" 4 +.IX Item "-fira-algorithm=algorithm" +Use specified coloring algorithm for the integrated register +allocator. The \fIalgorithm\fR argument should be \f(CW\*(C`priority\*(C'\fR or +\&\f(CW\*(C`CB\*(C'\fR. The first algorithm specifies Chow's priority coloring, +the second one specifies Chaitin-Briggs coloring. The second +algorithm can be unimplemented for some architectures. If it is +implemented, it is the default because Chaitin-Briggs coloring as a +rule generates a better code. +.IP "\fB\-fira\-region=\fR\fIregion\fR" 4 +.IX Item "-fira-region=region" +Use specified regions for the integrated register allocator. The +\&\fIregion\fR argument should be one of \f(CW\*(C`all\*(C'\fR, \f(CW\*(C`mixed\*(C'\fR, or +\&\f(CW\*(C`one\*(C'\fR. The first value means using all loops as register +allocation regions, the second value which is the default means using +all loops except for loops with small register pressure as the +regions, and third one means using all function as a single region. +The first value can give best result for machines with small size and +irregular register set, the third one results in faster and generates +decent code and the smallest size code, and the default value usually +give the best results in most cases and for most architectures. +.IP "\fB\-fira\-loop\-pressure\fR" 4 +.IX Item "-fira-loop-pressure" +Use \s-1IRA\s0 to evaluate register pressure in loops for decision to move +loop invariants. Usage of this option usually results in generation +of faster and smaller code on machines with big register files (>= 32 +registers) but it can slow compiler down. +.Sp +This option is enabled at level \fB\-O3\fR for some targets. +.IP "\fB\-fno\-ira\-share\-save\-slots\fR" 4 +.IX Item "-fno-ira-share-save-slots" +Switch off sharing stack slots used for saving call used hard +registers living through a call. Each hard register will get a +separate stack slot and as a result function stack frame will be +bigger. +.IP "\fB\-fno\-ira\-share\-spill\-slots\fR" 4 +.IX Item "-fno-ira-share-spill-slots" +Switch off sharing stack slots allocated for pseudo-registers. Each +pseudo-register which did not get a hard register will get a separate +stack slot and as a result function stack frame will be bigger. +.IP "\fB\-fira\-verbose=\fR\fIn\fR" 4 +.IX Item "-fira-verbose=n" +Set up how verbose dump file for the integrated register allocator +will be. Default value is 5. If the value is greater or equal to 10, +the dump file will be stderr as if the value were \fIn\fR minus 10. +.IP "\fB\-fdelayed\-branch\fR" 4 +.IX Item "-fdelayed-branch" +If supported for the target machine, attempt to reorder instructions +to exploit instruction slots available after delayed branch +instructions. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fschedule\-insns\fR" 4 +.IX Item "-fschedule-insns" +If supported for the target machine, attempt to reorder instructions to +eliminate execution stalls due to required data being unavailable. This +helps machines that have slow floating point or memory load instructions +by allowing other instructions to be issued until the result of the load +or floating point instruction is required. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-fschedule\-insns2\fR" 4 +.IX Item "-fschedule-insns2" +Similar to \fB\-fschedule\-insns\fR, but requests an additional pass of +instruction scheduling after register allocation has been done. This is +especially useful on machines with a relatively small number of +registers and where memory load instructions take more than one cycle. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fno\-sched\-interblock\fR" 4 +.IX Item "-fno-sched-interblock" +Don't schedule instructions across basic blocks. This is normally +enabled by default when scheduling before register allocation, i.e. +with \fB\-fschedule\-insns\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fno\-sched\-spec\fR" 4 +.IX Item "-fno-sched-spec" +Don't allow speculative motion of non-load instructions. This is normally +enabled by default when scheduling before register allocation, i.e. +with \fB\-fschedule\-insns\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-pressure\fR" 4 +.IX Item "-fsched-pressure" +Enable register pressure sensitive insn scheduling before the register +allocation. This only makes sense when scheduling before register +allocation is enabled, i.e. with \fB\-fschedule\-insns\fR or at +\&\fB\-O2\fR or higher. Usage of this option can improve the +generated code and decrease its size by preventing register pressure +increase above the number of available hard registers and as a +consequence register spills in the register allocation. +.IP "\fB\-fsched\-spec\-load\fR" 4 +.IX Item "-fsched-spec-load" +Allow speculative motion of some load instructions. This only makes +sense when scheduling before register allocation, i.e. with +\&\fB\-fschedule\-insns\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-spec\-load\-dangerous\fR" 4 +.IX Item "-fsched-spec-load-dangerous" +Allow speculative motion of more load instructions. This only makes +sense when scheduling before register allocation, i.e. with +\&\fB\-fschedule\-insns\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-stalled\-insns\fR" 4 +.IX Item "-fsched-stalled-insns" +.PD 0 +.IP "\fB\-fsched\-stalled\-insns=\fR\fIn\fR" 4 +.IX Item "-fsched-stalled-insns=n" +.PD +Define how many insns (if any) can be moved prematurely from the queue +of stalled insns into the ready list, during the second scheduling pass. +\&\fB\-fno\-sched\-stalled\-insns\fR means that no insns will be moved +prematurely, \fB\-fsched\-stalled\-insns=0\fR means there is no limit +on how many queued insns can be moved prematurely. +\&\fB\-fsched\-stalled\-insns\fR without a value is equivalent to +\&\fB\-fsched\-stalled\-insns=1\fR. +.IP "\fB\-fsched\-stalled\-insns\-dep\fR" 4 +.IX Item "-fsched-stalled-insns-dep" +.PD 0 +.IP "\fB\-fsched\-stalled\-insns\-dep=\fR\fIn\fR" 4 +.IX Item "-fsched-stalled-insns-dep=n" +.PD +Define how many insn groups (cycles) will be examined for a dependency +on a stalled insn that is candidate for premature removal from the queue +of stalled insns. This has an effect only during the second scheduling pass, +and only if \fB\-fsched\-stalled\-insns\fR is used. +\&\fB\-fno\-sched\-stalled\-insns\-dep\fR is equivalent to +\&\fB\-fsched\-stalled\-insns\-dep=0\fR. +\&\fB\-fsched\-stalled\-insns\-dep\fR without a value is equivalent to +\&\fB\-fsched\-stalled\-insns\-dep=1\fR. +.IP "\fB\-fsched2\-use\-superblocks\fR" 4 +.IX Item "-fsched2-use-superblocks" +When scheduling after register allocation, do use superblock scheduling +algorithm. Superblock scheduling allows motion across basic block boundaries +resulting on faster schedules. This option is experimental, as not all machine +descriptions used by \s-1GCC\s0 model the \s-1CPU\s0 closely enough to avoid unreliable +results from the algorithm. +.Sp +This only makes sense when scheduling after register allocation, i.e. with +\&\fB\-fschedule\-insns2\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-group\-heuristic\fR" 4 +.IX Item "-fsched-group-heuristic" +Enable the group heuristic in the scheduler. This heuristic favors +the instruction that belongs to a schedule group. This is enabled +by default when scheduling is enabled, i.e. with \fB\-fschedule\-insns\fR +or \fB\-fschedule\-insns2\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-critical\-path\-heuristic\fR" 4 +.IX Item "-fsched-critical-path-heuristic" +Enable the critical-path heuristic in the scheduler. This heuristic favors +instructions on the critical path. This is enabled by default when +scheduling is enabled, i.e. with \fB\-fschedule\-insns\fR +or \fB\-fschedule\-insns2\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-spec\-insn\-heuristic\fR" 4 +.IX Item "-fsched-spec-insn-heuristic" +Enable the speculative instruction heuristic in the scheduler. This +heuristic favors speculative instructions with greater dependency weakness. +This is enabled by default when scheduling is enabled, i.e. +with \fB\-fschedule\-insns\fR or \fB\-fschedule\-insns2\fR +or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-rank\-heuristic\fR" 4 +.IX Item "-fsched-rank-heuristic" +Enable the rank heuristic in the scheduler. This heuristic favors +the instruction belonging to a basic block with greater size or frequency. +This is enabled by default when scheduling is enabled, i.e. +with \fB\-fschedule\-insns\fR or \fB\-fschedule\-insns2\fR or +at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-last\-insn\-heuristic\fR" 4 +.IX Item "-fsched-last-insn-heuristic" +Enable the last-instruction heuristic in the scheduler. This heuristic +favors the instruction that is less dependent on the last instruction +scheduled. This is enabled by default when scheduling is enabled, +i.e. with \fB\-fschedule\-insns\fR or \fB\-fschedule\-insns2\fR or +at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-dep\-count\-heuristic\fR" 4 +.IX Item "-fsched-dep-count-heuristic" +Enable the dependent-count heuristic in the scheduler. This heuristic +favors the instruction that has more instructions depending on it. +This is enabled by default when scheduling is enabled, i.e. +with \fB\-fschedule\-insns\fR or \fB\-fschedule\-insns2\fR or +at \fB\-O2\fR or higher. +.IP "\fB\-freschedule\-modulo\-scheduled\-loops\fR" 4 +.IX Item "-freschedule-modulo-scheduled-loops" +The modulo scheduling comes before the traditional scheduling, if a loop +was modulo scheduled we may want to prevent the later scheduling passes +from changing its schedule, we use this option to control that. +.IP "\fB\-fselective\-scheduling\fR" 4 +.IX Item "-fselective-scheduling" +Schedule instructions using selective scheduling algorithm. Selective +scheduling runs instead of the first scheduler pass. +.IP "\fB\-fselective\-scheduling2\fR" 4 +.IX Item "-fselective-scheduling2" +Schedule instructions using selective scheduling algorithm. Selective +scheduling runs instead of the second scheduler pass. +.IP "\fB\-fsel\-sched\-pipelining\fR" 4 +.IX Item "-fsel-sched-pipelining" +Enable software pipelining of innermost loops during selective scheduling. +This option has no effect until one of \fB\-fselective\-scheduling\fR or +\&\fB\-fselective\-scheduling2\fR is turned on. +.IP "\fB\-fsel\-sched\-pipelining\-outer\-loops\fR" 4 +.IX Item "-fsel-sched-pipelining-outer-loops" +When pipelining loops during selective scheduling, also pipeline outer loops. +This option has no effect until \fB\-fsel\-sched\-pipelining\fR is turned on. +.IP "\fB\-fcaller\-saves\fR" 4 +.IX Item "-fcaller-saves" +Enable values to be allocated in registers that will be clobbered by +function calls, by emitting extra instructions to save and restore the +registers around such calls. Such allocation is done only when it +seems to result in better code than would otherwise be produced. +.Sp +This option is always enabled by default on certain machines, usually +those which have no call-preserved registers to use instead. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fcombine\-stack\-adjustments\fR" 4 +.IX Item "-fcombine-stack-adjustments" +Tracks stack adjustments (pushes and pops) and stack memory references +and then tries to find ways to combine them. +.Sp +Enabled by default at \fB\-O1\fR and higher. +.IP "\fB\-fconserve\-stack\fR" 4 +.IX Item "-fconserve-stack" +Attempt to minimize stack usage. The compiler will attempt to use less +stack space, even if that makes the program slower. This option +implies setting the \fBlarge-stack-frame\fR parameter to 100 +and the \fBlarge-stack-frame-growth\fR parameter to 400. +.IP "\fB\-ftree\-reassoc\fR" 4 +.IX Item "-ftree-reassoc" +Perform reassociation on trees. This flag is enabled by default +at \fB\-O\fR and higher. +.IP "\fB\-ftree\-pre\fR" 4 +.IX Item "-ftree-pre" +Perform partial redundancy elimination (\s-1PRE\s0) on trees. This flag is +enabled by default at \fB\-O2\fR and \fB\-O3\fR. +.IP "\fB\-ftree\-forwprop\fR" 4 +.IX Item "-ftree-forwprop" +Perform forward propagation on trees. This flag is enabled by default +at \fB\-O\fR and higher. +.IP "\fB\-ftree\-fre\fR" 4 +.IX Item "-ftree-fre" +Perform full redundancy elimination (\s-1FRE\s0) on trees. The difference +between \s-1FRE\s0 and \s-1PRE\s0 is that \s-1FRE\s0 only considers expressions +that are computed on all paths leading to the redundant computation. +This analysis is faster than \s-1PRE\s0, though it exposes fewer redundancies. +This flag is enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-phiprop\fR" 4 +.IX Item "-ftree-phiprop" +Perform hoisting of loads from conditional pointers on trees. This +pass is enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-copy\-prop\fR" 4 +.IX Item "-ftree-copy-prop" +Perform copy propagation on trees. This pass eliminates unnecessary +copy operations. This flag is enabled by default at \fB\-O\fR and +higher. +.IP "\fB\-fipa\-pure\-const\fR" 4 +.IX Item "-fipa-pure-const" +Discover which functions are pure or constant. +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fipa\-reference\fR" 4 +.IX Item "-fipa-reference" +Discover which static variables do not escape cannot escape the +compilation unit. +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fipa\-struct\-reorg\fR" 4 +.IX Item "-fipa-struct-reorg" +Perform structure reorganization optimization, that change C\-like structures +layout in order to better utilize spatial locality. This transformation is +affective for programs containing arrays of structures. Available in two +compilation modes: profile-based (enabled with \fB\-fprofile\-generate\fR) +or static (which uses built-in heuristics). It works only in whole program +mode, so it requires \fB\-fwhole\-program\fR to be +enabled. Structures considered \fBcold\fR by this transformation are not +affected (see \fB\-\-param struct\-reorg\-cold\-struct\-ratio=\fR\fIvalue\fR). +.Sp +With this flag, the program debug info reflects a new structure layout. +.IP "\fB\-fipa\-pta\fR" 4 +.IX Item "-fipa-pta" +Perform interprocedural pointer analysis and interprocedural modification +and reference analysis. This option can cause excessive memory and +compile-time usage on large compilation units. It is not enabled by +default at any optimization level. +.IP "\fB\-fipa\-profile\fR" 4 +.IX Item "-fipa-profile" +Perform interprocedural profile propagation. The functions called only from +cold functions are marked as cold. Also functions executed once (such as +\&\f(CW\*(C`cold\*(C'\fR, \f(CW\*(C`noreturn\*(C'\fR, static constructors or destructors) are identified. Cold +functions and loop less parts of functions executed once are then optimized for +size. +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fipa\-cp\fR" 4 +.IX Item "-fipa-cp" +Perform interprocedural constant propagation. +This optimization analyzes the program to determine when values passed +to functions are constants and then optimizes accordingly. +This optimization can substantially increase performance +if the application has constants passed to functions. +This flag is enabled by default at \fB\-O2\fR, \fB\-Os\fR and \fB\-O3\fR. +.IP "\fB\-fipa\-cp\-clone\fR" 4 +.IX Item "-fipa-cp-clone" +Perform function cloning to make interprocedural constant propagation stronger. +When enabled, interprocedural constant propagation will perform function cloning +when externally visible function can be called with constant arguments. +Because this optimization can create multiple copies of functions, +it may significantly increase code size +(see \fB\-\-param ipcp\-unit\-growth=\fR\fIvalue\fR). +This flag is enabled by default at \fB\-O3\fR. +.IP "\fB\-fipa\-matrix\-reorg\fR" 4 +.IX Item "-fipa-matrix-reorg" +Perform matrix flattening and transposing. +Matrix flattening tries to replace an m\-dimensional matrix +with its equivalent n\-dimensional matrix, where n < m. +This reduces the level of indirection needed for accessing the elements +of the matrix. The second optimization is matrix transposing that +attempts to change the order of the matrix's dimensions in order to +improve cache locality. +Both optimizations need the \fB\-fwhole\-program\fR flag. +Transposing is enabled only if profiling information is available. +.IP "\fB\-ftree\-sink\fR" 4 +.IX Item "-ftree-sink" +Perform forward store motion on trees. This flag is +enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-bit\-ccp\fR" 4 +.IX Item "-ftree-bit-ccp" +Perform sparse conditional bit constant propagation on trees and propagate +pointer alignment information. +This pass only operates on local scalar variables and is enabled by default +at \fB\-O\fR and higher. It requires that \fB\-ftree\-ccp\fR is enabled. +.IP "\fB\-ftree\-ccp\fR" 4 +.IX Item "-ftree-ccp" +Perform sparse conditional constant propagation (\s-1CCP\s0) on trees. This +pass only operates on local scalar variables and is enabled by default +at \fB\-O\fR and higher. +.IP "\fB\-ftree\-switch\-conversion\fR" 4 +.IX Item "-ftree-switch-conversion" +Perform conversion of simple initializations in a switch to +initializations from a scalar array. This flag is enabled by default +at \fB\-O2\fR and higher. +.IP "\fB\-ftree\-dce\fR" 4 +.IX Item "-ftree-dce" +Perform dead code elimination (\s-1DCE\s0) on trees. This flag is enabled by +default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-builtin\-call\-dce\fR" 4 +.IX Item "-ftree-builtin-call-dce" +Perform conditional dead code elimination (\s-1DCE\s0) for calls to builtin functions +that may set \f(CW\*(C`errno\*(C'\fR but are otherwise side-effect free. This flag is +enabled by default at \fB\-O2\fR and higher if \fB\-Os\fR is not also +specified. +.IP "\fB\-ftree\-dominator\-opts\fR" 4 +.IX Item "-ftree-dominator-opts" +Perform a variety of simple scalar cleanups (constant/copy +propagation, redundancy elimination, range propagation and expression +simplification) based on a dominator tree traversal. This also +performs jump threading (to reduce jumps to jumps). This flag is +enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-dse\fR" 4 +.IX Item "-ftree-dse" +Perform dead store elimination (\s-1DSE\s0) on trees. A dead store is a store into +a memory location which will later be overwritten by another store without +any intervening loads. In this case the earlier store can be deleted. This +flag is enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-ch\fR" 4 +.IX Item "-ftree-ch" +Perform loop header copying on trees. This is beneficial since it increases +effectiveness of code motion optimizations. It also saves one jump. This flag +is enabled by default at \fB\-O\fR and higher. It is not enabled +for \fB\-Os\fR, since it usually increases code size. +.IP "\fB\-ftree\-loop\-optimize\fR" 4 +.IX Item "-ftree-loop-optimize" +Perform loop optimizations on trees. This flag is enabled by default +at \fB\-O\fR and higher. +.IP "\fB\-ftree\-loop\-linear\fR" 4 +.IX Item "-ftree-loop-linear" +Perform loop interchange transformations on tree. Same as +\&\fB\-floop\-interchange\fR. To use this code transformation, \s-1GCC\s0 has +to be configured with \fB\-\-with\-ppl\fR and \fB\-\-with\-cloog\fR to +enable the Graphite loop transformation infrastructure. +.IP "\fB\-floop\-interchange\fR" 4 +.IX Item "-floop-interchange" +Perform loop interchange transformations on loops. Interchanging two +nested loops switches the inner and outer loops. For example, given a +loop like: +.Sp +.Vb 5 +\& DO J = 1, M +\& DO I = 1, N +\& A(J, I) = A(J, I) * C +\& ENDDO +\& ENDDO +.Ve +.Sp +loop interchange will transform the loop as if the user had written: +.Sp +.Vb 5 +\& DO I = 1, N +\& DO J = 1, M +\& A(J, I) = A(J, I) * C +\& ENDDO +\& ENDDO +.Ve +.Sp +which can be beneficial when \f(CW\*(C`N\*(C'\fR is larger than the caches, +because in Fortran, the elements of an array are stored in memory +contiguously by column, and the original loop iterates over rows, +potentially creating at each access a cache miss. This optimization +applies to all the languages supported by \s-1GCC\s0 and is not limited to +Fortran. To use this code transformation, \s-1GCC\s0 has to be configured +with \fB\-\-with\-ppl\fR and \fB\-\-with\-cloog\fR to enable the +Graphite loop transformation infrastructure. +.IP "\fB\-floop\-strip\-mine\fR" 4 +.IX Item "-floop-strip-mine" +Perform loop strip mining transformations on loops. Strip mining +splits a loop into two nested loops. The outer loop has strides +equal to the strip size and the inner loop has strides of the +original loop within a strip. The strip length can be changed +using the \fBloop-block-tile-size\fR parameter. For example, +given a loop like: +.Sp +.Vb 3 +\& DO I = 1, N +\& A(I) = A(I) + C +\& ENDDO +.Ve +.Sp +loop strip mining will transform the loop as if the user had written: +.Sp +.Vb 5 +\& DO II = 1, N, 51 +\& DO I = II, min (II + 50, N) +\& A(I) = A(I) + C +\& ENDDO +\& ENDDO +.Ve +.Sp +This optimization applies to all the languages supported by \s-1GCC\s0 and is +not limited to Fortran. To use this code transformation, \s-1GCC\s0 has to +be configured with \fB\-\-with\-ppl\fR and \fB\-\-with\-cloog\fR to +enable the Graphite loop transformation infrastructure. +.IP "\fB\-floop\-block\fR" 4 +.IX Item "-floop-block" +Perform loop blocking transformations on loops. Blocking strip mines +each loop in the loop nest such that the memory accesses of the +element loops fit inside caches. The strip length can be changed +using the \fBloop-block-tile-size\fR parameter. For example, given +a loop like: +.Sp +.Vb 5 +\& DO I = 1, N +\& DO J = 1, M +\& A(J, I) = B(I) + C(J) +\& ENDDO +\& ENDDO +.Ve +.Sp +loop blocking will transform the loop as if the user had written: +.Sp +.Vb 9 +\& DO II = 1, N, 51 +\& DO JJ = 1, M, 51 +\& DO I = II, min (II + 50, N) +\& DO J = JJ, min (JJ + 50, M) +\& A(J, I) = B(I) + C(J) +\& ENDDO +\& ENDDO +\& ENDDO +\& ENDDO +.Ve +.Sp +which can be beneficial when \f(CW\*(C`M\*(C'\fR is larger than the caches, +because the innermost loop will iterate over a smaller amount of data +that can be kept in the caches. This optimization applies to all the +languages supported by \s-1GCC\s0 and is not limited to Fortran. To use this +code transformation, \s-1GCC\s0 has to be configured with \fB\-\-with\-ppl\fR +and \fB\-\-with\-cloog\fR to enable the Graphite loop transformation +infrastructure. +.IP "\fB\-fgraphite\-identity\fR" 4 +.IX Item "-fgraphite-identity" +Enable the identity transformation for graphite. For every SCoP we generate +the polyhedral representation and transform it back to gimple. Using +\&\fB\-fgraphite\-identity\fR we can check the costs or benefits of the +\&\s-1GIMPLE\s0 \-> \s-1GRAPHITE\s0 \-> \s-1GIMPLE\s0 transformation. Some minimal optimizations +are also performed by the code generator CLooG, like index splitting and +dead code elimination in loops. +.IP "\fB\-floop\-flatten\fR" 4 +.IX Item "-floop-flatten" +Removes the loop nesting structure: transforms the loop nest into a +single loop. This transformation can be useful to vectorize all the +levels of the loop nest. +.IP "\fB\-floop\-parallelize\-all\fR" 4 +.IX Item "-floop-parallelize-all" +Use the Graphite data dependence analysis to identify loops that can +be parallelized. Parallelize all the loops that can be analyzed to +not contain loop carried dependences without checking that it is +profitable to parallelize the loops. +.IP "\fB\-fcheck\-data\-deps\fR" 4 +.IX Item "-fcheck-data-deps" +Compare the results of several data dependence analyzers. This option +is used for debugging the data dependence analyzers. +.IP "\fB\-ftree\-loop\-if\-convert\fR" 4 +.IX Item "-ftree-loop-if-convert" +Attempt to transform conditional jumps in the innermost loops to +branch-less equivalents. The intent is to remove control-flow from +the innermost loops in order to improve the ability of the +vectorization pass to handle these loops. This is enabled by default +if vectorization is enabled. +.IP "\fB\-ftree\-loop\-if\-convert\-stores\fR" 4 +.IX Item "-ftree-loop-if-convert-stores" +Attempt to also if-convert conditional jumps containing memory writes. +This transformation can be unsafe for multi-threaded programs as it +transforms conditional memory writes into unconditional memory writes. +For example, +.Sp +.Vb 3 +\& for (i = 0; i < N; i++) +\& if (cond) +\& A[i] = expr; +.Ve +.Sp +would be transformed to +.Sp +.Vb 2 +\& for (i = 0; i < N; i++) +\& A[i] = cond ? expr : A[i]; +.Ve +.Sp +potentially producing data races. +.IP "\fB\-ftree\-loop\-distribution\fR" 4 +.IX Item "-ftree-loop-distribution" +Perform loop distribution. This flag can improve cache performance on +big loop bodies and allow further loop optimizations, like +parallelization or vectorization, to take place. For example, the loop +.Sp +.Vb 4 +\& DO I = 1, N +\& A(I) = B(I) + C +\& D(I) = E(I) * F +\& ENDDO +.Ve +.Sp +is transformed to +.Sp +.Vb 6 +\& DO I = 1, N +\& A(I) = B(I) + C +\& ENDDO +\& DO I = 1, N +\& D(I) = E(I) * F +\& ENDDO +.Ve +.IP "\fB\-ftree\-loop\-distribute\-patterns\fR" 4 +.IX Item "-ftree-loop-distribute-patterns" +Perform loop distribution of patterns that can be code generated with +calls to a library. This flag is enabled by default at \fB\-O3\fR. +.Sp +This pass distributes the initialization loops and generates a call to +memset zero. For example, the loop +.Sp +.Vb 4 +\& DO I = 1, N +\& A(I) = 0 +\& B(I) = A(I) + I +\& ENDDO +.Ve +.Sp +is transformed to +.Sp +.Vb 6 +\& DO I = 1, N +\& A(I) = 0 +\& ENDDO +\& DO I = 1, N +\& B(I) = A(I) + I +\& ENDDO +.Ve +.Sp +and the initialization loop is transformed into a call to memset zero. +.IP "\fB\-ftree\-loop\-im\fR" 4 +.IX Item "-ftree-loop-im" +Perform loop invariant motion on trees. This pass moves only invariants that +would be hard to handle at \s-1RTL\s0 level (function calls, operations that expand to +nontrivial sequences of insns). With \fB\-funswitch\-loops\fR it also moves +operands of conditions that are invariant out of the loop, so that we can use +just trivial invariantness analysis in loop unswitching. The pass also includes +store motion. +.IP "\fB\-ftree\-loop\-ivcanon\fR" 4 +.IX Item "-ftree-loop-ivcanon" +Create a canonical counter for number of iterations in the loop for that +determining number of iterations requires complicated analysis. Later +optimizations then may determine the number easily. Useful especially +in connection with unrolling. +.IP "\fB\-fivopts\fR" 4 +.IX Item "-fivopts" +Perform induction variable optimizations (strength reduction, induction +variable merging and induction variable elimination) on trees. +.IP "\fB\-ftree\-parallelize\-loops=n\fR" 4 +.IX Item "-ftree-parallelize-loops=n" +Parallelize loops, i.e., split their iteration space to run in n threads. +This is only possible for loops whose iterations are independent +and can be arbitrarily reordered. The optimization is only +profitable on multiprocessor machines, for loops that are CPU-intensive, +rather than constrained e.g. by memory bandwidth. This option +implies \fB\-pthread\fR, and thus is only supported on targets +that have support for \fB\-pthread\fR. +.IP "\fB\-ftree\-pta\fR" 4 +.IX Item "-ftree-pta" +Perform function-local points-to analysis on trees. This flag is +enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-sra\fR" 4 +.IX Item "-ftree-sra" +Perform scalar replacement of aggregates. This pass replaces structure +references with scalars to prevent committing structures to memory too +early. This flag is enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-copyrename\fR" 4 +.IX Item "-ftree-copyrename" +Perform copy renaming on trees. This pass attempts to rename compiler +temporaries to other variables at copy locations, usually resulting in +variable names which more closely resemble the original variables. This flag +is enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-ter\fR" 4 +.IX Item "-ftree-ter" +Perform temporary expression replacement during the \s-1SSA\-\s0>normal phase. Single +use/single def temporaries are replaced at their use location with their +defining expression. This results in non-GIMPLE code, but gives the expanders +much more complex trees to work on resulting in better \s-1RTL\s0 generation. This is +enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-vectorize\fR" 4 +.IX Item "-ftree-vectorize" +Perform loop vectorization on trees. This flag is enabled by default at +\&\fB\-O3\fR. +.IP "\fB\-ftree\-slp\-vectorize\fR" 4 +.IX Item "-ftree-slp-vectorize" +Perform basic block vectorization on trees. This flag is enabled by default at +\&\fB\-O3\fR and when \fB\-ftree\-vectorize\fR is enabled. +.IP "\fB\-ftree\-vect\-loop\-version\fR" 4 +.IX Item "-ftree-vect-loop-version" +Perform loop versioning when doing loop vectorization on trees. When a loop +appears to be vectorizable except that data alignment or data dependence cannot +be determined at compile time then vectorized and non-vectorized versions of +the loop are generated along with runtime checks for alignment or dependence +to control which version is executed. This option is enabled by default +except at level \fB\-Os\fR where it is disabled. +.IP "\fB\-fvect\-cost\-model\fR" 4 +.IX Item "-fvect-cost-model" +Enable cost model for vectorization. +.IP "\fB\-ftree\-vrp\fR" 4 +.IX Item "-ftree-vrp" +Perform Value Range Propagation on trees. This is similar to the +constant propagation pass, but instead of values, ranges of values are +propagated. This allows the optimizers to remove unnecessary range +checks like array bound checks and null pointer checks. This is +enabled by default at \fB\-O2\fR and higher. Null pointer check +elimination is only done if \fB\-fdelete\-null\-pointer\-checks\fR is +enabled. +.IP "\fB\-ftracer\fR" 4 +.IX Item "-ftracer" +Perform tail duplication to enlarge superblock size. This transformation +simplifies the control flow of the function allowing other optimizations to do +better job. +.IP "\fB\-funroll\-loops\fR" 4 +.IX Item "-funroll-loops" +Unroll loops whose number of iterations can be determined at compile +time or upon entry to the loop. \fB\-funroll\-loops\fR implies +\&\fB\-frerun\-cse\-after\-loop\fR. This option makes code larger, +and may or may not make it run faster. +.IP "\fB\-funroll\-all\-loops\fR" 4 +.IX Item "-funroll-all-loops" +Unroll all loops, even if their number of iterations is uncertain when +the loop is entered. This usually makes programs run more slowly. +\&\fB\-funroll\-all\-loops\fR implies the same options as +\&\fB\-funroll\-loops\fR, +.IP "\fB\-fsplit\-ivs\-in\-unroller\fR" 4 +.IX Item "-fsplit-ivs-in-unroller" +Enables expressing of values of induction variables in later iterations +of the unrolled loop using the value in the first iteration. This breaks +long dependency chains, thus improving efficiency of the scheduling passes. +.Sp +Combination of \fB\-fweb\fR and \s-1CSE\s0 is often sufficient to obtain the +same effect. However in cases the loop body is more complicated than +a single basic block, this is not reliable. It also does not work at all +on some of the architectures due to restrictions in the \s-1CSE\s0 pass. +.Sp +This optimization is enabled by default. +.IP "\fB\-fvariable\-expansion\-in\-unroller\fR" 4 +.IX Item "-fvariable-expansion-in-unroller" +With this option, the compiler will create multiple copies of some +local variables when unrolling a loop which can result in superior code. +.IP "\fB\-fpartial\-inlining\fR" 4 +.IX Item "-fpartial-inlining" +Inline parts of functions. This option has any effect only +when inlining itself is turned on by the \fB\-finline\-functions\fR +or \fB\-finline\-small\-functions\fR options. +.Sp +Enabled at level \fB\-O2\fR. +.IP "\fB\-fpredictive\-commoning\fR" 4 +.IX Item "-fpredictive-commoning" +Perform predictive commoning optimization, i.e., reusing computations +(especially memory loads and stores) performed in previous +iterations of loops. +.Sp +This option is enabled at level \fB\-O3\fR. +.IP "\fB\-fprefetch\-loop\-arrays\fR" 4 +.IX Item "-fprefetch-loop-arrays" +If supported by the target machine, generate instructions to prefetch +memory to improve the performance of loops that access large arrays. +.Sp +This option may generate better or worse code; results are highly +dependent on the structure of loops within the source code. +.Sp +Disabled at level \fB\-Os\fR. +.IP "\fB\-fno\-peephole\fR" 4 +.IX Item "-fno-peephole" +.PD 0 +.IP "\fB\-fno\-peephole2\fR" 4 +.IX Item "-fno-peephole2" +.PD +Disable any machine-specific peephole optimizations. The difference +between \fB\-fno\-peephole\fR and \fB\-fno\-peephole2\fR is in how they +are implemented in the compiler; some targets use one, some use the +other, a few use both. +.Sp +\&\fB\-fpeephole\fR is enabled by default. +\&\fB\-fpeephole2\fR enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fno\-guess\-branch\-probability\fR" 4 +.IX Item "-fno-guess-branch-probability" +Do not guess branch probabilities using heuristics. +.Sp +\&\s-1GCC\s0 will use heuristics to guess branch probabilities if they are +not provided by profiling feedback (\fB\-fprofile\-arcs\fR). These +heuristics are based on the control flow graph. If some branch probabilities +are specified by \fB_\|_builtin_expect\fR, then the heuristics will be +used to guess branch probabilities for the rest of the control flow graph, +taking the \fB_\|_builtin_expect\fR info into account. The interactions +between the heuristics and \fB_\|_builtin_expect\fR can be complex, and in +some cases, it may be useful to disable the heuristics so that the effects +of \fB_\|_builtin_expect\fR are easier to understand. +.Sp +The default is \fB\-fguess\-branch\-probability\fR at levels +\&\fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-freorder\-blocks\fR" 4 +.IX Item "-freorder-blocks" +Reorder basic blocks in the compiled function in order to reduce number of +taken branches and improve code locality. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-freorder\-blocks\-and\-partition\fR" 4 +.IX Item "-freorder-blocks-and-partition" +In addition to reordering basic blocks in the compiled function, in order +to reduce number of taken branches, partitions hot and cold basic blocks +into separate sections of the assembly and .o files, to improve +paging and cache locality performance. +.Sp +This optimization is automatically turned off in the presence of +exception handling, for linkonce sections, for functions with a user-defined +section attribute and on any architecture that does not support named +sections. +.IP "\fB\-freorder\-functions\fR" 4 +.IX Item "-freorder-functions" +Reorder functions in the object file in order to +improve code locality. This is implemented by using special +subsections \f(CW\*(C`.text.hot\*(C'\fR for most frequently executed functions and +\&\f(CW\*(C`.text.unlikely\*(C'\fR for unlikely executed functions. Reordering is done by +the linker so object file format must support named sections and linker must +place them in a reasonable way. +.Sp +Also profile feedback must be available in to make this option effective. See +\&\fB\-fprofile\-arcs\fR for details. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fstrict\-aliasing\fR" 4 +.IX Item "-fstrict-aliasing" +Allow the compiler to assume the strictest aliasing rules applicable to +the language being compiled. For C (and \*(C+), this activates +optimizations based on the type of expressions. In particular, an +object of one type is assumed never to reside at the same address as an +object of a different type, unless the types are almost the same. For +example, an \f(CW\*(C`unsigned int\*(C'\fR can alias an \f(CW\*(C`int\*(C'\fR, but not a +\&\f(CW\*(C`void*\*(C'\fR or a \f(CW\*(C`double\*(C'\fR. A character type may alias any other +type. +.Sp +Pay special attention to code like this: +.Sp +.Vb 4 +\& union a_union { +\& int i; +\& double d; +\& }; +\& +\& int f() { +\& union a_union t; +\& t.d = 3.0; +\& return t.i; +\& } +.Ve +.Sp +The practice of reading from a different union member than the one most +recently written to (called \*(L"type-punning\*(R") is common. Even with +\&\fB\-fstrict\-aliasing\fR, type-punning is allowed, provided the memory +is accessed through the union type. So, the code above will work as +expected. However, this code might not: +.Sp +.Vb 7 +\& int f() { +\& union a_union t; +\& int* ip; +\& t.d = 3.0; +\& ip = &t.i; +\& return *ip; +\& } +.Ve +.Sp +Similarly, access by taking the address, casting the resulting pointer +and dereferencing the result has undefined behavior, even if the cast +uses a union type, e.g.: +.Sp +.Vb 4 +\& int f() { +\& double d = 3.0; +\& return ((union a_union *) &d)\->i; +\& } +.Ve +.Sp +The \fB\-fstrict\-aliasing\fR option is enabled at levels +\&\fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fstrict\-overflow\fR" 4 +.IX Item "-fstrict-overflow" +Allow the compiler to assume strict signed overflow rules, depending +on the language being compiled. For C (and \*(C+) this means that +overflow when doing arithmetic with signed numbers is undefined, which +means that the compiler may assume that it will not happen. This +permits various optimizations. For example, the compiler will assume +that an expression like \f(CW\*(C`i + 10 > i\*(C'\fR will always be true for +signed \f(CW\*(C`i\*(C'\fR. This assumption is only valid if signed overflow is +undefined, as the expression is false if \f(CW\*(C`i + 10\*(C'\fR overflows when +using twos complement arithmetic. When this option is in effect any +attempt to determine whether an operation on signed numbers will +overflow must be written carefully to not actually involve overflow. +.Sp +This option also allows the compiler to assume strict pointer +semantics: given a pointer to an object, if adding an offset to that +pointer does not produce a pointer to the same object, the addition is +undefined. This permits the compiler to conclude that \f(CW\*(C`p + u > +p\*(C'\fR is always true for a pointer \f(CW\*(C`p\*(C'\fR and unsigned integer +\&\f(CW\*(C`u\*(C'\fR. This assumption is only valid because pointer wraparound is +undefined, as the expression is false if \f(CW\*(C`p + u\*(C'\fR overflows using +twos complement arithmetic. +.Sp +See also the \fB\-fwrapv\fR option. Using \fB\-fwrapv\fR means +that integer signed overflow is fully defined: it wraps. When +\&\fB\-fwrapv\fR is used, there is no difference between +\&\fB\-fstrict\-overflow\fR and \fB\-fno\-strict\-overflow\fR for +integers. With \fB\-fwrapv\fR certain types of overflow are +permitted. For example, if the compiler gets an overflow when doing +arithmetic on constants, the overflowed value can still be used with +\&\fB\-fwrapv\fR, but not otherwise. +.Sp +The \fB\-fstrict\-overflow\fR option is enabled at levels +\&\fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-falign\-functions\fR" 4 +.IX Item "-falign-functions" +.PD 0 +.IP "\fB\-falign\-functions=\fR\fIn\fR" 4 +.IX Item "-falign-functions=n" +.PD +Align the start of functions to the next power-of-two greater than +\&\fIn\fR, skipping up to \fIn\fR bytes. For instance, +\&\fB\-falign\-functions=32\fR aligns functions to the next 32\-byte +boundary, but \fB\-falign\-functions=24\fR would align to the next +32\-byte boundary only if this can be done by skipping 23 bytes or less. +.Sp +\&\fB\-fno\-align\-functions\fR and \fB\-falign\-functions=1\fR are +equivalent and mean that functions will not be aligned. +.Sp +Some assemblers only support this flag when \fIn\fR is a power of two; +in that case, it is rounded up. +.Sp +If \fIn\fR is not specified or is zero, use a machine-dependent default. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-falign\-labels\fR" 4 +.IX Item "-falign-labels" +.PD 0 +.IP "\fB\-falign\-labels=\fR\fIn\fR" 4 +.IX Item "-falign-labels=n" +.PD +Align all branch targets to a power-of-two boundary, skipping up to +\&\fIn\fR bytes like \fB\-falign\-functions\fR. This option can easily +make code slower, because it must insert dummy operations for when the +branch target is reached in the usual flow of the code. +.Sp +\&\fB\-fno\-align\-labels\fR and \fB\-falign\-labels=1\fR are +equivalent and mean that labels will not be aligned. +.Sp +If \fB\-falign\-loops\fR or \fB\-falign\-jumps\fR are applicable and +are greater than this value, then their values are used instead. +.Sp +If \fIn\fR is not specified or is zero, use a machine-dependent default +which is very likely to be \fB1\fR, meaning no alignment. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-falign\-loops\fR" 4 +.IX Item "-falign-loops" +.PD 0 +.IP "\fB\-falign\-loops=\fR\fIn\fR" 4 +.IX Item "-falign-loops=n" +.PD +Align loops to a power-of-two boundary, skipping up to \fIn\fR bytes +like \fB\-falign\-functions\fR. The hope is that the loop will be +executed many times, which will make up for any execution of the dummy +operations. +.Sp +\&\fB\-fno\-align\-loops\fR and \fB\-falign\-loops=1\fR are +equivalent and mean that loops will not be aligned. +.Sp +If \fIn\fR is not specified or is zero, use a machine-dependent default. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-falign\-jumps\fR" 4 +.IX Item "-falign-jumps" +.PD 0 +.IP "\fB\-falign\-jumps=\fR\fIn\fR" 4 +.IX Item "-falign-jumps=n" +.PD +Align branch targets to a power-of-two boundary, for branch targets +where the targets can only be reached by jumping, skipping up to \fIn\fR +bytes like \fB\-falign\-functions\fR. In this case, no dummy operations +need be executed. +.Sp +\&\fB\-fno\-align\-jumps\fR and \fB\-falign\-jumps=1\fR are +equivalent and mean that loops will not be aligned. +.Sp +If \fIn\fR is not specified or is zero, use a machine-dependent default. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-funit\-at\-a\-time\fR" 4 +.IX Item "-funit-at-a-time" +This option is left for compatibility reasons. \fB\-funit\-at\-a\-time\fR +has no effect, while \fB\-fno\-unit\-at\-a\-time\fR implies +\&\fB\-fno\-toplevel\-reorder\fR and \fB\-fno\-section\-anchors\fR. +.Sp +Enabled by default. +.IP "\fB\-fno\-toplevel\-reorder\fR" 4 +.IX Item "-fno-toplevel-reorder" +Do not reorder top-level functions, variables, and \f(CW\*(C`asm\*(C'\fR +statements. Output them in the same order that they appear in the +input file. When this option is used, unreferenced static variables +will not be removed. This option is intended to support existing code +which relies on a particular ordering. For new code, it is better to +use attributes. +.Sp +Enabled at level \fB\-O0\fR. When disabled explicitly, it also imply +\&\fB\-fno\-section\-anchors\fR that is otherwise enabled at \fB\-O0\fR on some +targets. +.IP "\fB\-fweb\fR" 4 +.IX Item "-fweb" +Constructs webs as commonly used for register allocation purposes and assign +each web individual pseudo register. This allows the register allocation pass +to operate on pseudos directly, but also strengthens several other optimization +passes, such as \s-1CSE\s0, loop optimizer and trivial dead code remover. It can, +however, make debugging impossible, since variables will no longer stay in a +\&\*(L"home register\*(R". +.Sp +Enabled by default with \fB\-funroll\-loops\fR. +.IP "\fB\-fwhole\-program\fR" 4 +.IX Item "-fwhole-program" +Assume that the current compilation unit represents the whole program being +compiled. All public functions and variables with the exception of \f(CW\*(C`main\*(C'\fR +and those merged by attribute \f(CW\*(C`externally_visible\*(C'\fR become static functions +and in effect are optimized more aggressively by interprocedural optimizers. If \fBgold\fR is used as the linker plugin, \f(CW\*(C`externally_visible\*(C'\fR attributes are automatically added to functions (not variable yet due to a current \fBgold\fR issue) that are accessed outside of \s-1LTO\s0 objects according to resolution file produced by \fBgold\fR. For other linkers that cannot generate resolution file, explicit \f(CW\*(C`externally_visible\*(C'\fR attributes are still necessary. +While this option is equivalent to proper use of the \f(CW\*(C`static\*(C'\fR keyword for +programs consisting of a single file, in combination with option +\&\fB\-flto\fR this flag can be used to +compile many smaller scale programs since the functions and variables become +local for the whole combined compilation unit, not for the single source file +itself. +.Sp +This option implies \fB\-fwhole\-file\fR for Fortran programs. +.IP "\fB\-flto[=\fR\fIn\fR\fB]\fR" 4 +.IX Item "-flto[=n]" +This option runs the standard link-time optimizer. When invoked +with source code, it generates \s-1GIMPLE\s0 (one of \s-1GCC\s0's internal +representations) and writes it to special \s-1ELF\s0 sections in the object +file. When the object files are linked together, all the function +bodies are read from these \s-1ELF\s0 sections and instantiated as if they +had been part of the same translation unit. +.Sp +To use the link-time optimizer, \fB\-flto\fR needs to be specified at +compile time and during the final link. For example: +.Sp +.Vb 3 +\& gcc \-c \-O2 \-flto foo.c +\& gcc \-c \-O2 \-flto bar.c +\& gcc \-o myprog \-flto \-O2 foo.o bar.o +.Ve +.Sp +The first two invocations to \s-1GCC\s0 save a bytecode representation +of \s-1GIMPLE\s0 into special \s-1ELF\s0 sections inside \fIfoo.o\fR and +\&\fIbar.o\fR. The final invocation reads the \s-1GIMPLE\s0 bytecode from +\&\fIfoo.o\fR and \fIbar.o\fR, merges the two files into a single +internal image, and compiles the result as usual. Since both +\&\fIfoo.o\fR and \fIbar.o\fR are merged into a single image, this +causes all the interprocedural analyses and optimizations in \s-1GCC\s0 to +work across the two files as if they were a single one. This means, +for example, that the inliner is able to inline functions in +\&\fIbar.o\fR into functions in \fIfoo.o\fR and vice-versa. +.Sp +Another (simpler) way to enable link-time optimization is: +.Sp +.Vb 1 +\& gcc \-o myprog \-flto \-O2 foo.c bar.c +.Ve +.Sp +The above generates bytecode for \fIfoo.c\fR and \fIbar.c\fR, +merges them together into a single \s-1GIMPLE\s0 representation and optimizes +them as usual to produce \fImyprog\fR. +.Sp +The only important thing to keep in mind is that to enable link-time +optimizations the \fB\-flto\fR flag needs to be passed to both the +compile and the link commands. +.Sp +To make whole program optimization effective, it is necessary to make +certain whole program assumptions. The compiler needs to know +what functions and variables can be accessed by libraries and runtime +outside of the link-time optimized unit. When supported by the linker, +the linker plugin (see \fB\-fuse\-linker\-plugin\fR) passes information +to the compiler about used and externally visible symbols. When +the linker plugin is not available, \fB\-fwhole\-program\fR should be +used to allow the compiler to make these assumptions, which leads +to more aggressive optimization decisions. +.Sp +Note that when a file is compiled with \fB\-flto\fR, the generated +object file is larger than a regular object file because it +contains \s-1GIMPLE\s0 bytecodes and the usual final code. This means that +object files with \s-1LTO\s0 information can be linked as normal object +files; if \fB\-flto\fR is not passed to the linker, no +interprocedural optimizations are applied. +.Sp +Additionally, the optimization flags used to compile individual files +are not necessarily related to those used at link time. For instance, +.Sp +.Vb 3 +\& gcc \-c \-O0 \-flto foo.c +\& gcc \-c \-O0 \-flto bar.c +\& gcc \-o myprog \-flto \-O3 foo.o bar.o +.Ve +.Sp +This produces individual object files with unoptimized assembler +code, but the resulting binary \fImyprog\fR is optimized at +\&\fB\-O3\fR. If, instead, the final binary is generated without +\&\fB\-flto\fR, then \fImyprog\fR is not optimized. +.Sp +When producing the final binary with \fB\-flto\fR, \s-1GCC\s0 only +applies link-time optimizations to those files that contain bytecode. +Therefore, you can mix and match object files and libraries with +\&\s-1GIMPLE\s0 bytecodes and final object code. \s-1GCC\s0 automatically selects +which files to optimize in \s-1LTO\s0 mode and which files to link without +further processing. +.Sp +There are some code generation flags that \s-1GCC\s0 preserves when +generating bytecodes, as they need to be used during the final link +stage. Currently, the following options are saved into the \s-1GIMPLE\s0 +bytecode files: \fB\-fPIC\fR, \fB\-fcommon\fR and all the +\&\fB\-m\fR target flags. +.Sp +At link time, these options are read in and reapplied. Note that the +current implementation makes no attempt to recognize conflicting +values for these options. If different files have conflicting option +values (e.g., one file is compiled with \fB\-fPIC\fR and another +isn't), the compiler simply uses the last value read from the +bytecode files. It is recommended, then, that you compile all the files +participating in the same link with the same options. +.Sp +If \s-1LTO\s0 encounters objects with C linkage declared with incompatible +types in separate translation units to be linked together (undefined +behavior according to \s-1ISO\s0 C99 6.2.7), a non-fatal diagnostic may be +issued. The behavior is still undefined at runtime. +.Sp +Another feature of \s-1LTO\s0 is that it is possible to apply interprocedural +optimizations on files written in different languages. This requires +support in the language front end. Currently, the C, \*(C+ and +Fortran front ends are capable of emitting \s-1GIMPLE\s0 bytecodes, so +something like this should work: +.Sp +.Vb 4 +\& gcc \-c \-flto foo.c +\& g++ \-c \-flto bar.cc +\& gfortran \-c \-flto baz.f90 +\& g++ \-o myprog \-flto \-O3 foo.o bar.o baz.o \-lgfortran +.Ve +.Sp +Notice that the final link is done with \fBg++\fR to get the \*(C+ +runtime libraries and \fB\-lgfortran\fR is added to get the Fortran +runtime libraries. In general, when mixing languages in \s-1LTO\s0 mode, you +should use the same link command options as when mixing languages in a +regular (non-LTO) compilation; all you need to add is \fB\-flto\fR to +all the compile and link commands. +.Sp +If object files containing \s-1GIMPLE\s0 bytecode are stored in a library archive, say +\&\fIlibfoo.a\fR, it is possible to extract and use them in an \s-1LTO\s0 link if you +are using a linker with plugin support. To enable this feature, use +the flag \fB\-fuse\-linker\-plugin\fR at link time: +.Sp +.Vb 1 +\& gcc \-o myprog \-O2 \-flto \-fuse\-linker\-plugin a.o b.o \-lfoo +.Ve +.Sp +With the linker plugin enabled, the linker extracts the needed +\&\s-1GIMPLE\s0 files from \fIlibfoo.a\fR and passes them on to the running \s-1GCC\s0 +to make them part of the aggregated \s-1GIMPLE\s0 image to be optimized. +.Sp +If you are not using a linker with plugin support and/or do not +enable the linker plugin, then the objects inside \fIlibfoo.a\fR +are extracted and linked as usual, but they do not participate +in the \s-1LTO\s0 optimization process. +.Sp +Link-time optimizations do not require the presence of the whole program to +operate. If the program does not require any symbols to be exported, it is +possible to combine \fB\-flto\fR and \fB\-fwhole\-program\fR to allow +the interprocedural optimizers to use more aggressive assumptions which may +lead to improved optimization opportunities. +Use of \fB\-fwhole\-program\fR is not needed when linker plugin is +active (see \fB\-fuse\-linker\-plugin\fR). +.Sp +The current implementation of \s-1LTO\s0 makes no +attempt to generate bytecode that is portable between different +types of hosts. The bytecode files are versioned and there is a +strict version check, so bytecode files generated in one version of +\&\s-1GCC\s0 will not work with an older/newer version of \s-1GCC\s0. +.Sp +Link-time optimization does not work well with generation of debugging +information. Combining \fB\-flto\fR with +\&\fB\-g\fR is currently experimental and expected to produce wrong +results. +.Sp +If you specify the optional \fIn\fR, the optimization and code +generation done at link time is executed in parallel using \fIn\fR +parallel jobs by utilizing an installed \fBmake\fR program. The +environment variable \fB\s-1MAKE\s0\fR may be used to override the program +used. The default value for \fIn\fR is 1. +.Sp +You can also specify \fB\-flto=jobserver\fR to use \s-1GNU\s0 make's +job server mode to determine the number of parallel jobs. This +is useful when the Makefile calling \s-1GCC\s0 is already executing in parallel. +You must prepend a \fB+\fR to the command recipe in the parent Makefile +for this to work. This option likely only works if \fB\s-1MAKE\s0\fR is +\&\s-1GNU\s0 make. +.Sp +This option is disabled by default. +.IP "\fB\-flto\-partition=\fR\fIalg\fR" 4 +.IX Item "-flto-partition=alg" +Specify the partitioning algorithm used by the link-time optimizer. +The value is either \f(CW\*(C`1to1\*(C'\fR to specify a partitioning mirroring +the original source files or \f(CW\*(C`balanced\*(C'\fR to specify partitioning +into equally sized chunks (whenever possible). Specifying \f(CW\*(C`none\*(C'\fR +as an algorithm disables partitioning and streaming completely. The +default value is \f(CW\*(C`balanced\*(C'\fR. +.IP "\fB\-flto\-compression\-level=\fR\fIn\fR" 4 +.IX Item "-flto-compression-level=n" +This option specifies the level of compression used for intermediate +language written to \s-1LTO\s0 object files, and is only meaningful in +conjunction with \s-1LTO\s0 mode (\fB\-flto\fR). Valid +values are 0 (no compression) to 9 (maximum compression). Values +outside this range are clamped to either 0 or 9. If the option is not +given, a default balanced compression setting is used. +.IP "\fB\-flto\-report\fR" 4 +.IX Item "-flto-report" +Prints a report with internal details on the workings of the link-time +optimizer. The contents of this report vary from version to version. +It is meant to be useful to \s-1GCC\s0 developers when processing object +files in \s-1LTO\s0 mode (via \fB\-flto\fR). +.Sp +Disabled by default. +.IP "\fB\-fuse\-linker\-plugin\fR" 4 +.IX Item "-fuse-linker-plugin" +Enables the use of a linker plugin during link-time optimization. This +option relies on the linker plugin support in linker that is available in gold +or in \s-1GNU\s0 ld 2.21 or newer. +.Sp +This option enables the extraction of object files with \s-1GIMPLE\s0 bytecode out +of library archives. This improves the quality of optimization by exposing +more code to the link-time optimizer. This information specifies what +symbols can be accessed externally (by non-LTO object or during dynamic +linking). Resulting code quality improvements on binaries (and shared +libraries that use hidden visibility) are similar to \f(CW\*(C`\-fwhole\-program\*(C'\fR. +See \fB\-flto\fR for a description of the effect of this flag and how to +use it. +.Sp +This option is enabled by default when \s-1LTO\s0 support in \s-1GCC\s0 is enabled +and \s-1GCC\s0 was configured for use with +a linker supporting plugins (\s-1GNU\s0 ld 2.21 or newer or gold). +.IP "\fB\-fcompare\-elim\fR" 4 +.IX Item "-fcompare-elim" +After register allocation and post-register allocation instruction splitting, +identify arithmetic instructions that compute processor flags similar to a +comparison operation based on that arithmetic. If possible, eliminate the +explicit comparison operation. +.Sp +This pass only applies to certain targets that cannot explicitly represent +the comparison operation before register allocation is complete. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fuse\-ld=gold\fR" 4 +.IX Item "-fuse-ld=gold" +Use the \fBgold\fR linker instead of the default linker. +This option is only necessary if \s-1GCC\s0 has been configured with +\&\fB\-\-enable\-gold\fR and \fB\-\-enable\-ld=default\fR. +.IP "\fB\-fuse\-ld=bfd\fR" 4 +.IX Item "-fuse-ld=bfd" +Use the \fBld.bfd\fR linker instead of the default linker. +This option is only necessary if \s-1GCC\s0 has been configured with +\&\fB\-\-enable\-gold\fR and \fB\-\-enable\-ld\fR. +.IP "\fB\-fcprop\-registers\fR" 4 +.IX Item "-fcprop-registers" +After register allocation and post-register allocation instruction splitting, +we perform a copy-propagation pass to try to reduce scheduling dependencies +and occasionally eliminate the copy. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fprofile\-correction\fR" 4 +.IX Item "-fprofile-correction" +Profiles collected using an instrumented binary for multi-threaded programs may +be inconsistent due to missed counter updates. When this option is specified, +\&\s-1GCC\s0 will use heuristics to correct or smooth out such inconsistencies. By +default, \s-1GCC\s0 will emit an error message when an inconsistent profile is detected. +.IP "\fB\-fprofile\-dir=\fR\fIpath\fR" 4 +.IX Item "-fprofile-dir=path" +Set the directory to search for the profile data files in to \fIpath\fR. +This option affects only the profile data generated by +\&\fB\-fprofile\-generate\fR, \fB\-ftest\-coverage\fR, \fB\-fprofile\-arcs\fR +and used by \fB\-fprofile\-use\fR and \fB\-fbranch\-probabilities\fR +and its related options. Both absolute and relative paths can be used. +By default, \s-1GCC\s0 will use the current directory as \fIpath\fR, thus the +profile data file will appear in the same directory as the object file. +.IP "\fB\-fprofile\-generate\fR" 4 +.IX Item "-fprofile-generate" +.PD 0 +.IP "\fB\-fprofile\-generate=\fR\fIpath\fR" 4 +.IX Item "-fprofile-generate=path" +.PD +Enable options usually used for instrumenting application to produce +profile useful for later recompilation with profile feedback based +optimization. You must use \fB\-fprofile\-generate\fR both when +compiling and when linking your program. +.Sp +The following options are enabled: \f(CW\*(C`\-fprofile\-arcs\*(C'\fR, \f(CW\*(C`\-fprofile\-values\*(C'\fR, \f(CW\*(C`\-fvpt\*(C'\fR. +.Sp +If \fIpath\fR is specified, \s-1GCC\s0 will look at the \fIpath\fR to find +the profile feedback data files. See \fB\-fprofile\-dir\fR. +.IP "\fB\-fprofile\-generate\-sampling\fR" 4 +.IX Item "-fprofile-generate-sampling" +Enable sampling for instrumented binaries. Instead of recording every event, +record only every N\-th event, where N (the sampling rate) can be set either +at compile time using +\&\fB\-\-param profile\-generate\-sampling\-rate=\fR\fIvalue\fR, or +at execution start time through environment variable \fB\s-1GCOV_SAMPLING_RATE\s0\fR. +.Sp +At this time sampling applies only to branch counters. A sampling rate of 100 +decreases instrumentated binary slowdown from up to 20x for heavily threaded +applications down to around 2x. \fB\-fprofile\-correction\fR is always +needed with sampling. +.IP "\fB\-fprofile\-use\fR" 4 +.IX Item "-fprofile-use" +.PD 0 +.IP "\fB\-fprofile\-use=\fR\fIpath\fR" 4 +.IX Item "-fprofile-use=path" +.PD +Enable profile feedback directed optimizations, and optimizations +generally profitable only with profile feedback available. +.Sp +The following options are enabled: \f(CW\*(C`\-fbranch\-probabilities\*(C'\fR, \f(CW\*(C`\-fvpt\*(C'\fR, +\&\f(CW\*(C`\-funroll\-loops\*(C'\fR, \f(CW\*(C`\-fpeel\-loops\*(C'\fR. +.Sp +By default, \s-1GCC\s0 emits an error message if the feedback profiles do not +match the source code. This error can be turned into a warning by using +\&\fB\-Wcoverage\-mismatch\fR. Note this may result in poorly optimized +code. +.Sp +If \fIpath\fR is specified, \s-1GCC\s0 will look at the \fIpath\fR to find +the profile feedback data files. See \fB\-fprofile\-dir\fR. +.IP "\fB\-fpmu\-profile\-generate=\fR\fIpmuoption\fR" 4 +.IX Item "-fpmu-profile-generate=pmuoption" +Enable performance monitoring unit (\s-1PMU\s0) profiling. This collects +hardware counter data corresponding to \fIpmuoption\fR. Currently +only \fIload-latency\fR and \fIbranch-mispredict\fR are supported +using pfmon tool. You must use \fB\-fpmu\-profile\-generate\fR both +when compiling and when linking your program. This \s-1PMU\s0 profile data +may later be used by the compiler during optimizations as well can be +displayed using coverage tool gcov. The params variable +\&\*(L"pmu_profile_n_addresses\*(R" can be used to restrict \s-1PMU\s0 data collection +to only this many addresses. +.IP "\fB\-fpmu\-profile\-use=\fR\fIpmuoption\fR" 4 +.IX Item "-fpmu-profile-use=pmuoption" +Enable performance monitoring unit (\s-1PMU\s0) profiling based +optimizations. Currently only \fIload-latency\fR and +\&\fIbranch-mispredict\fR are supported. +.IP "\fB\-fripa\fR" 4 +.IX Item "-fripa" +Perform dynamic inter-procedural analysis. This is used in conjunction with +the \fB\-fprofile\-generate\fR and \fB\-fprofile\-use\fR options. +During the \fB\-fprofile\-generate\fR phase, this flag turns on some additional +instrumentation code that enables dynamic call-graph analysis. +During the \fB\-fprofile\-use\fR phase, this flag enables cross-module +optimizations such as inlining. +.IP "\fB\-fripa\-disallow\-asm\-modules\fR" 4 +.IX Item "-fripa-disallow-asm-modules" +During profile-gen, if this flag is enabled, and the module has asm statements, +arrange so that a bit recording this information will be set in the profile +feedback data file. +During profile-use, if this flag is enabled, and the same bit in auxiliary +module's profile feedback data is set, don't import this auxiliary module. +If this is the primary module, don't export it. +.IP "\fB\-fripa\-disallow\-opt\-mismatch\fR" 4 +.IX Item "-fripa-disallow-opt-mismatch" +Don't import an auxiliary module, if the \s-1GCC\s0 command line options used for this +auxiliary module during the profile-generate stage were different from those used +for the primary module. Note that any mismatches in warning-related options are +ignored for this comparison. +.IP "\fB\-fripa\-no\-promote\-always\-inline\-func\fR" 4 +.IX Item "-fripa-no-promote-always-inline-func" +Do not promote static functions with always inline attribute in \s-1LIPO\s0 compilation. +.IP "\fB\-fripa\-verbose\fR" 4 +.IX Item "-fripa-verbose" +Enable printing of verbose information about dynamic inter-procedural optimizations. +This is used in conjunction with the \fB\-fripa\fR. +.IP "\fB\-fripa\-peel\-size\-limit\fR" 4 +.IX Item "-fripa-peel-size-limit" +Limit loop peeling of non-const non-FP loops in a \s-1LIPO\s0 compilation under estimates +of a large code footprint. Enabled by default under \fB\-fripa\fR. Code size +estimation and thresholds are controlled by the \fBcodesize-hotness-threshold\fR +and \fBunrollpeel-codesize-threshold\fR parameters. +.IP "\fB\-fripa\-unroll\-size\-limit\fR" 4 +.IX Item "-fripa-unroll-size-limit" +Limit loop unrolling of non-const non-FP loops in a \s-1LIPO\s0 compilation under estimates +of a large code footprint. Enabled by default under \fB\-fripa\fR. Code size +estimation and thresholds are controlled by the \fBcodesize-hotness-threshold\fR +and \fBunrollpeel-codesize-threshold\fR parameters. +.IP "\fB\-fcallgraph\-profiles\-sections\fR" 4 +.IX Item "-fcallgraph-profiles-sections" +Emit call graph edge profile counts in .note.callgraph.text sections. This is +used in conjunction with \fB\-fprofile\-use\fR. A new .note.callgraph.text +section is created for each function. This section lists every callee and the +number of times it is called. The params variable +\&\*(L"note-cgraph-section-edge-threshold\*(R" can be used to only list edges above a +certain threshold. +.IP "\fB\-frecord\-gcc\-switches\-in\-elf\fR" 4 +.IX Item "-frecord-gcc-switches-in-elf" +Record the command line options in the .gnu.switches.text elf section for sample +based \s-1LIPO\s0 to do module grouping. +.PP +The following options control compiler behavior regarding floating +point arithmetic. These options trade off between speed and +correctness. All must be specifically enabled. +.IP "\fB\-ffloat\-store\fR" 4 +.IX Item "-ffloat-store" +Do not store floating point variables in registers, and inhibit other +options that might change whether a floating point value is taken from a +register or memory. +.Sp +This option prevents undesirable excess precision on machines such as +the 68000 where the floating registers (of the 68881) keep more +precision than a \f(CW\*(C`double\*(C'\fR is supposed to have. Similarly for the +x86 architecture. For most programs, the excess precision does only +good, but a few programs rely on the precise definition of \s-1IEEE\s0 floating +point. Use \fB\-ffloat\-store\fR for such programs, after modifying +them to store all pertinent intermediate computations into variables. +.IP "\fB\-fexcess\-precision=\fR\fIstyle\fR" 4 +.IX Item "-fexcess-precision=style" +This option allows further control over excess precision on machines +where floating-point registers have more precision than the \s-1IEEE\s0 +\&\f(CW\*(C`float\*(C'\fR and \f(CW\*(C`double\*(C'\fR types and the processor does not +support operations rounding to those types. By default, +\&\fB\-fexcess\-precision=fast\fR is in effect; this means that +operations are carried out in the precision of the registers and that +it is unpredictable when rounding to the types specified in the source +code takes place. When compiling C, if +\&\fB\-fexcess\-precision=standard\fR is specified then excess +precision will follow the rules specified in \s-1ISO\s0 C99; in particular, +both casts and assignments cause values to be rounded to their +semantic types (whereas \fB\-ffloat\-store\fR only affects +assignments). This option is enabled by default for C if a strict +conformance option such as \fB\-std=c99\fR is used. +.Sp +\&\fB\-fexcess\-precision=standard\fR is not implemented for languages +other than C, and has no effect if +\&\fB\-funsafe\-math\-optimizations\fR or \fB\-ffast\-math\fR is +specified. On the x86, it also has no effect if \fB\-mfpmath=sse\fR +or \fB\-mfpmath=sse+387\fR is specified; in the former case, \s-1IEEE\s0 +semantics apply without excess precision, and in the latter, rounding +is unpredictable. +.IP "\fB\-ffast\-math\fR" 4 +.IX Item "-ffast-math" +Sets \fB\-fno\-math\-errno\fR, \fB\-funsafe\-math\-optimizations\fR, +\&\fB\-ffinite\-math\-only\fR, \fB\-fno\-rounding\-math\fR, +\&\fB\-fno\-signaling\-nans\fR and \fB\-fcx\-limited\-range\fR. +.Sp +This option causes the preprocessor macro \f(CW\*(C`_\|_FAST_MATH_\|_\*(C'\fR to be defined. +.Sp +This option is not turned on by any \fB\-O\fR option besides +\&\fB\-Ofast\fR since it can result in incorrect output for programs +which depend on an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications +for math functions. It may, however, yield faster code for programs +that do not require the guarantees of these specifications. +.IP "\fB\-fno\-math\-errno\fR" 4 +.IX Item "-fno-math-errno" +Do not set \s-1ERRNO\s0 after calling math functions that are executed +with a single instruction, e.g., sqrt. A program that relies on +\&\s-1IEEE\s0 exceptions for math error handling may want to use this flag +for speed while maintaining \s-1IEEE\s0 arithmetic compatibility. +.Sp +This option is not turned on by any \fB\-O\fR option since +it can result in incorrect output for programs which depend on +an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for +math functions. It may, however, yield faster code for programs +that do not require the guarantees of these specifications. +.Sp +The default is \fB\-fmath\-errno\fR. +.Sp +On Darwin systems, the math library never sets \f(CW\*(C`errno\*(C'\fR. There is +therefore no reason for the compiler to consider the possibility that +it might, and \fB\-fno\-math\-errno\fR is the default. +.IP "\fB\-funsafe\-math\-optimizations\fR" 4 +.IX Item "-funsafe-math-optimizations" +Allow optimizations for floating-point arithmetic that (a) assume +that arguments and results are valid and (b) may violate \s-1IEEE\s0 or +\&\s-1ANSI\s0 standards. When used at link-time, it may include libraries +or startup files that change the default \s-1FPU\s0 control word or other +similar optimizations. +.Sp +This option is not turned on by any \fB\-O\fR option since +it can result in incorrect output for programs which depend on +an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for +math functions. It may, however, yield faster code for programs +that do not require the guarantees of these specifications. +Enables \fB\-fno\-signed\-zeros\fR, \fB\-fno\-trapping\-math\fR, +\&\fB\-fassociative\-math\fR and \fB\-freciprocal\-math\fR. +.Sp +The default is \fB\-fno\-unsafe\-math\-optimizations\fR. +.IP "\fB\-fassociative\-math\fR" 4 +.IX Item "-fassociative-math" +Allow re-association of operands in series of floating-point operations. +This violates the \s-1ISO\s0 C and \*(C+ language standard by possibly changing +computation result. \s-1NOTE:\s0 re-ordering may change the sign of zero as +well as ignore NaNs and inhibit or create underflow or overflow (and +thus cannot be used on a code which relies on rounding behavior like +\&\f(CW\*(C`(x + 2**52) \- 2**52)\*(C'\fR. May also reorder floating-point comparisons +and thus may not be used when ordered comparisons are required. +This option requires that both \fB\-fno\-signed\-zeros\fR and +\&\fB\-fno\-trapping\-math\fR be in effect. Moreover, it doesn't make +much sense with \fB\-frounding\-math\fR. For Fortran the option +is automatically enabled when both \fB\-fno\-signed\-zeros\fR and +\&\fB\-fno\-trapping\-math\fR are in effect. +.Sp +The default is \fB\-fno\-associative\-math\fR. +.IP "\fB\-freciprocal\-math\fR" 4 +.IX Item "-freciprocal-math" +Allow the reciprocal of a value to be used instead of dividing by +the value if this enables optimizations. For example \f(CW\*(C`x / y\*(C'\fR +can be replaced with \f(CW\*(C`x * (1/y)\*(C'\fR which is useful if \f(CW\*(C`(1/y)\*(C'\fR +is subject to common subexpression elimination. Note that this loses +precision and increases the number of flops operating on the value. +.Sp +The default is \fB\-fno\-reciprocal\-math\fR. +.IP "\fB\-ffinite\-math\-only\fR" 4 +.IX Item "-ffinite-math-only" +Allow optimizations for floating-point arithmetic that assume +that arguments and results are not NaNs or +\-Infs. +.Sp +This option is not turned on by any \fB\-O\fR option since +it can result in incorrect output for programs which depend on +an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for +math functions. It may, however, yield faster code for programs +that do not require the guarantees of these specifications. +.Sp +The default is \fB\-fno\-finite\-math\-only\fR. +.IP "\fB\-fno\-signed\-zeros\fR" 4 +.IX Item "-fno-signed-zeros" +Allow optimizations for floating point arithmetic that ignore the +signedness of zero. \s-1IEEE\s0 arithmetic specifies the behavior of +distinct +0.0 and \-0.0 values, which then prohibits simplification +of expressions such as x+0.0 or 0.0*x (even with \fB\-ffinite\-math\-only\fR). +This option implies that the sign of a zero result isn't significant. +.Sp +The default is \fB\-fsigned\-zeros\fR. +.IP "\fB\-fno\-trapping\-math\fR" 4 +.IX Item "-fno-trapping-math" +Compile code assuming that floating-point operations cannot generate +user-visible traps. These traps include division by zero, overflow, +underflow, inexact result and invalid operation. This option requires +that \fB\-fno\-signaling\-nans\fR be in effect. Setting this option may +allow faster code if one relies on \*(L"non-stop\*(R" \s-1IEEE\s0 arithmetic, for example. +.Sp +This option should never be turned on by any \fB\-O\fR option since +it can result in incorrect output for programs which depend on +an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for +math functions. +.Sp +The default is \fB\-ftrapping\-math\fR. +.IP "\fB\-frounding\-math\fR" 4 +.IX Item "-frounding-math" +Disable transformations and optimizations that assume default floating +point rounding behavior. This is round-to-zero for all floating point +to integer conversions, and round-to-nearest for all other arithmetic +truncations. This option should be specified for programs that change +the \s-1FP\s0 rounding mode dynamically, or that may be executed with a +non-default rounding mode. This option disables constant folding of +floating point expressions at compile-time (which may be affected by +rounding mode) and arithmetic transformations that are unsafe in the +presence of sign-dependent rounding modes. +.Sp +The default is \fB\-fno\-rounding\-math\fR. +.Sp +This option is experimental and does not currently guarantee to +disable all \s-1GCC\s0 optimizations that are affected by rounding mode. +Future versions of \s-1GCC\s0 may provide finer control of this setting +using C99's \f(CW\*(C`FENV_ACCESS\*(C'\fR pragma. This command line option +will be used to specify the default state for \f(CW\*(C`FENV_ACCESS\*(C'\fR. +.IP "\fB\-fsignaling\-nans\fR" 4 +.IX Item "-fsignaling-nans" +Compile code assuming that \s-1IEEE\s0 signaling NaNs may generate user-visible +traps during floating-point operations. Setting this option disables +optimizations that may change the number of exceptions visible with +signaling NaNs. This option implies \fB\-ftrapping\-math\fR. +.Sp +This option causes the preprocessor macro \f(CW\*(C`_\|_SUPPORT_SNAN_\|_\*(C'\fR to +be defined. +.Sp +The default is \fB\-fno\-signaling\-nans\fR. +.Sp +This option is experimental and does not currently guarantee to +disable all \s-1GCC\s0 optimizations that affect signaling NaN behavior. +.IP "\fB\-fsingle\-precision\-constant\fR" 4 +.IX Item "-fsingle-precision-constant" +Treat floating point constant as single precision constant instead of +implicitly converting it to double precision constant. +.IP "\fB\-fcx\-limited\-range\fR" 4 +.IX Item "-fcx-limited-range" +When enabled, this option states that a range reduction step is not +needed when performing complex division. Also, there is no checking +whether the result of a complex multiplication or division is \f(CW\*(C`NaN ++ I*NaN\*(C'\fR, with an attempt to rescue the situation in that case. The +default is \fB\-fno\-cx\-limited\-range\fR, but is enabled by +\&\fB\-ffast\-math\fR. +.Sp +This option controls the default setting of the \s-1ISO\s0 C99 +\&\f(CW\*(C`CX_LIMITED_RANGE\*(C'\fR pragma. Nevertheless, the option applies to +all languages. +.IP "\fB\-fcx\-fortran\-rules\fR" 4 +.IX Item "-fcx-fortran-rules" +Complex multiplication and division follow Fortran rules. Range +reduction is done as part of complex division, but there is no checking +whether the result of a complex multiplication or division is \f(CW\*(C`NaN ++ I*NaN\*(C'\fR, with an attempt to rescue the situation in that case. +.Sp +The default is \fB\-fno\-cx\-fortran\-rules\fR. +.IP "\fBmin-mcf-cancel-iters\fR" 4 +.IX Item "min-mcf-cancel-iters" +The minimum number of iterations of negative cycle cancellation during +\&\s-1MCF\s0 profile correction before early termination. This parameter is +only useful when using \fB\-fprofile\-correction\fR. +.PP +The following options control optimizations that may improve +performance, but are not enabled by any \fB\-O\fR options. This +section includes experimental options that may produce broken code. +.IP "\fB\-fbranch\-probabilities\fR" 4 +.IX Item "-fbranch-probabilities" +After running a program compiled with \fB\-fprofile\-arcs\fR, you can compile it a second time using +\&\fB\-fbranch\-probabilities\fR, to improve optimizations based on +the number of times each branch was taken. When the program +compiled with \fB\-fprofile\-arcs\fR exits it saves arc execution +counts to a file called \fI\fIsourcename\fI.gcda\fR for each source +file. The information in this data file is very dependent on the +structure of the generated code, so you must use the same source code +and the same optimization options for both compilations. +.Sp +With \fB\-fbranch\-probabilities\fR, \s-1GCC\s0 puts a +\&\fB\s-1REG_BR_PROB\s0\fR note on each \fB\s-1JUMP_INSN\s0\fR and \fB\s-1CALL_INSN\s0\fR. +These can be used to improve optimization. Currently, they are only +used in one place: in \fIreorg.c\fR, instead of guessing which path a +branch is most likely to take, the \fB\s-1REG_BR_PROB\s0\fR values are used to +exactly determine which path is taken more often. +.IP "\fB\-fclone\-hot\-version\-paths\fR" 4 +.IX Item "-fclone-hot-version-paths" +When multi-version calls are made using \fB_\|_builtin_dispatch\fR, this flag +enables cloning and hoisting of hot multiversioned paths. +.IP "\fB\-fprofile\-values\fR" 4 +.IX Item "-fprofile-values" +If combined with \fB\-fprofile\-arcs\fR, it adds code so that some +data about values of expressions in the program is gathered. +.Sp +With \fB\-fbranch\-probabilities\fR, it reads back the data gathered +from profiling values of expressions for usage in optimizations. +.Sp +Enabled with \fB\-fprofile\-generate\fR and \fB\-fprofile\-use\fR. +.IP "\fB\-fvpt\fR" 4 +.IX Item "-fvpt" +If combined with \fB\-fprofile\-arcs\fR, it instructs the compiler to add +a code to gather information about values of expressions. +.Sp +With \fB\-fbranch\-probabilities\fR, it reads back the data gathered +and actually performs the optimizations based on them. +Currently the optimizations include specialization of division operation +using the knowledge about the value of the denominator. +.IP "\fB\-frename\-registers\fR" 4 +.IX Item "-frename-registers" +Attempt to avoid false dependencies in scheduled code by making use +of registers left over after register allocation. This optimization +will most benefit processors with lots of registers. Depending on the +debug information format adopted by the target, however, it can +make debugging impossible, since variables will no longer stay in +a \*(L"home register\*(R". +.Sp +Enabled by default with \fB\-funroll\-loops\fR and \fB\-fpeel\-loops\fR. +.IP "\fB\-ftracer\fR" 4 +.IX Item "-ftracer" +Perform tail duplication to enlarge superblock size. This transformation +simplifies the control flow of the function allowing other optimizations to do +better job. +.Sp +Enabled with \fB\-fprofile\-use\fR. +.IP "\fB\-funroll\-loops\fR" 4 +.IX Item "-funroll-loops" +Unroll loops whose number of iterations can be determined at compile time or +upon entry to the loop. \fB\-funroll\-loops\fR implies +\&\fB\-frerun\-cse\-after\-loop\fR, \fB\-fweb\fR and \fB\-frename\-registers\fR. +It also turns on complete loop peeling (i.e. complete removal of loops with +small constant number of iterations). This option makes code larger, and may +or may not make it run faster. +.Sp +Enabled with \fB\-fprofile\-use\fR. +.IP "\fB\-funroll\-all\-loops\fR" 4 +.IX Item "-funroll-all-loops" +Unroll all loops, even if their number of iterations is uncertain when +the loop is entered. This usually makes programs run more slowly. +\&\fB\-funroll\-all\-loops\fR implies the same options as +\&\fB\-funroll\-loops\fR. +.IP "\fB\-fpeel\-loops\fR" 4 +.IX Item "-fpeel-loops" +Peels the loops for that there is enough information that they do not +roll much (from profile feedback). It also turns on complete loop peeling +(i.e. complete removal of loops with small constant number of iterations). +.Sp +Enabled with \fB\-fprofile\-use\fR. +.IP "\fB\-fmove\-loop\-invariants\fR" 4 +.IX Item "-fmove-loop-invariants" +Enables the loop invariant motion pass in the \s-1RTL\s0 loop optimizer. Enabled +at level \fB\-O1\fR +.IP "\fB\-funswitch\-loops\fR" 4 +.IX Item "-funswitch-loops" +Move branches with loop invariant conditions out of the loop, with duplicates +of the loop on both branches (modified according to result of the condition). +.IP "\fB\-ffunction\-sections\fR" 4 +.IX Item "-ffunction-sections" +.PD 0 +.IP "\fB\-fdata\-sections\fR" 4 +.IX Item "-fdata-sections" +.PD +Place each function or data item into its own section in the output +file if the target supports arbitrary sections. The name of the +function or the name of the data item determines the section's name +in the output file. +.Sp +Use these options on systems where the linker can perform optimizations +to improve locality of reference in the instruction space. Most systems +using the \s-1ELF\s0 object format and \s-1SPARC\s0 processors running Solaris 2 have +linkers with such optimizations. \s-1AIX\s0 may have these optimizations in +the future. +.Sp +Only use these options when there are significant benefits from doing +so. When you specify these options, the assembler and linker will +create larger object and executable files and will also be slower. +You will not be able to use \f(CW\*(C`gprof\*(C'\fR on all systems if you +specify this option and you may have problems with debugging if +you specify both this option and \fB\-g\fR. +.IP "\fB\-fbranch\-target\-load\-optimize\fR" 4 +.IX Item "-fbranch-target-load-optimize" +Perform branch target register load optimization before prologue / epilogue +threading. +The use of target registers can typically be exposed only during reload, +thus hoisting loads out of loops and doing inter-block scheduling needs +a separate optimization pass. +.IP "\fB\-fbranch\-target\-load\-optimize2\fR" 4 +.IX Item "-fbranch-target-load-optimize2" +Perform branch target register load optimization after prologue / epilogue +threading. +.IP "\fB\-fbtr\-bb\-exclusive\fR" 4 +.IX Item "-fbtr-bb-exclusive" +When performing branch target register load optimization, don't reuse +branch target registers in within any basic block. +.IP "\fB\-fstack\-protector\fR" 4 +.IX Item "-fstack-protector" +Emit extra code to check for buffer overflows, such as stack smashing +attacks. This is done by adding a guard variable to functions with +vulnerable objects. This includes functions that call alloca, and +functions with buffers larger than 8 bytes. The guards are initialized +when a function is entered and then checked when the function exits. +If a guard check fails, an error message is printed and the program exits. +.IP "\fB\-fstack\-protector\-all\fR" 4 +.IX Item "-fstack-protector-all" +Like \fB\-fstack\-protector\fR except that all functions are protected. +.IP "\fB\-fstack\-protector\-strong\fR" 4 +.IX Item "-fstack-protector-strong" +Like \fB\-fstack\-protector\fR but includes additional functions to be +protected \- those that have local array definitions, or have references to +local frame addresses. +.IP "\fB\-fsection\-anchors\fR" 4 +.IX Item "-fsection-anchors" +Try to reduce the number of symbolic address calculations by using +shared \*(L"anchor\*(R" symbols to address nearby objects. This transformation +can help to reduce the number of \s-1GOT\s0 entries and \s-1GOT\s0 accesses on some +targets. +.Sp +For example, the implementation of the following function \f(CW\*(C`foo\*(C'\fR: +.Sp +.Vb 2 +\& static int a, b, c; +\& int foo (void) { return a + b + c; } +.Ve +.Sp +would usually calculate the addresses of all three variables, but if you +compile it with \fB\-fsection\-anchors\fR, it will access the variables +from a common anchor point instead. The effect is similar to the +following pseudocode (which isn't valid C): +.Sp +.Vb 5 +\& int foo (void) +\& { +\& register int *xr = &x; +\& return xr[&a \- &x] + xr[&b \- &x] + xr[&c \- &x]; +\& } +.Ve +.Sp +Not all targets support this option. +.IP "\fB\-\-param\fR \fIname\fR\fB=\fR\fIvalue\fR" 4 +.IX Item "--param name=value" +In some places, \s-1GCC\s0 uses various constants to control the amount of +optimization that is done. For example, \s-1GCC\s0 will not inline functions +that contain more that a certain number of instructions. You can +control some of these constants on the command-line using the +\&\fB\-\-param\fR option. +.Sp +The names of specific parameters, and the meaning of the values, are +tied to the internals of the compiler, and are subject to change +without notice in future releases. +.Sp +In each case, the \fIvalue\fR is an integer. The allowable choices for +\&\fIname\fR are given in the following table: +.RS 4 +.IP "\fBstruct-reorg-cold-struct-ratio\fR" 4 +.IX Item "struct-reorg-cold-struct-ratio" +The threshold ratio (as a percentage) between a structure frequency +and the frequency of the hottest structure in the program. This parameter +is used by struct-reorg optimization enabled by \fB\-fipa\-struct\-reorg\fR. +We say that if the ratio of a structure frequency, calculated by profiling, +to the hottest structure frequency in the program is less than this +parameter, then structure reorganization is not applied to this structure. +The default is 10. +.IP "\fBpredictable-branch-outcome\fR" 4 +.IX Item "predictable-branch-outcome" +When branch is predicted to be taken with probability lower than this threshold +(in percent), then it is considered well predictable. The default is 10. +.IP "\fBmax-crossjump-edges\fR" 4 +.IX Item "max-crossjump-edges" +The maximum number of incoming edges to consider for crossjumping. +The algorithm used by \fB\-fcrossjumping\fR is O(N^2) in +the number of edges incoming to each block. Increasing values mean +more aggressive optimization, making the compile time increase with +probably small improvement in executable size. +.IP "\fBmin-crossjump-insns\fR" 4 +.IX Item "min-crossjump-insns" +The minimum number of instructions which must be matched at the end +of two blocks before crossjumping will be performed on them. This +value is ignored in the case where all instructions in the block being +crossjumped from are matched. The default value is 5. +.IP "\fBmax-grow-copy-bb-insns\fR" 4 +.IX Item "max-grow-copy-bb-insns" +The maximum code size expansion factor when copying basic blocks +instead of jumping. The expansion is relative to a jump instruction. +The default value is 8. +.IP "\fBmax-goto-duplication-insns\fR" 4 +.IX Item "max-goto-duplication-insns" +The maximum number of instructions to duplicate to a block that jumps +to a computed goto. To avoid O(N^2) behavior in a number of +passes, \s-1GCC\s0 factors computed gotos early in the compilation process, +and unfactors them as late as possible. Only computed jumps at the +end of a basic blocks with no more than max-goto-duplication-insns are +unfactored. The default value is 8. +.IP "\fBmax-delay-slot-insn-search\fR" 4 +.IX Item "max-delay-slot-insn-search" +The maximum number of instructions to consider when looking for an +instruction to fill a delay slot. If more than this arbitrary number of +instructions is searched, the time savings from filling the delay slot +will be minimal so stop searching. Increasing values mean more +aggressive optimization, making the compile time increase with probably +small improvement in executable run time. +.IP "\fBmax-delay-slot-live-search\fR" 4 +.IX Item "max-delay-slot-live-search" +When trying to fill delay slots, the maximum number of instructions to +consider when searching for a block with valid live register +information. Increasing this arbitrarily chosen value means more +aggressive optimization, increasing the compile time. This parameter +should be removed when the delay slot code is rewritten to maintain the +control-flow graph. +.IP "\fBmax-gcse-memory\fR" 4 +.IX Item "max-gcse-memory" +The approximate maximum amount of memory that will be allocated in +order to perform the global common subexpression elimination +optimization. If more memory than specified is required, the +optimization will not be done. +.IP "\fBmax-gcse-insertion-ratio\fR" 4 +.IX Item "max-gcse-insertion-ratio" +If the ratio of expression insertions to deletions is larger than this value +for any expression, then \s-1RTL\s0 \s-1PRE\s0 will insert or remove the expression and thus +leave partially redundant computations in the instruction stream. The default value is 20. +.IP "\fBmax-pending-list-length\fR" 4 +.IX Item "max-pending-list-length" +The maximum number of pending dependencies scheduling will allow +before flushing the current state and starting over. Large functions +with few branches or calls can create excessively large lists which +needlessly consume memory and resources. +.IP "\fBmax-inline-insns-single\fR" 4 +.IX Item "max-inline-insns-single" +Several parameters control the tree inliner used in gcc. +This number sets the maximum number of instructions (counted in \s-1GCC\s0's +internal representation) in a single function that the tree inliner +will consider for inlining. This only affects functions declared +inline and methods implemented in a class declaration (\*(C+). +The default value is 400. +.IP "\fBmax-inline-insns-auto\fR" 4 +.IX Item "max-inline-insns-auto" +When you use \fB\-finline\-functions\fR (included in \fB\-O3\fR), +a lot of functions that would otherwise not be considered for inlining +by the compiler will be investigated. To those functions, a different +(more restrictive) limit compared to functions declared inline can +be applied. +The default value is 40. +.IP "\fBmversn-clone-depth\fR" 4 +.IX Item "mversn-clone-depth" +When using \fB\-fclone\-hot\-version\-paths\fR, hot function paths are multi\- +versioned via cloning. This parameter specifies the maximum length of the +call graph path that can be cloned. The default value is 2. +.IP "\fBnum-mversn-clones\fR" 4 +.IX Item "num-mversn-clones" +When using \fB\-fclone\-hot\-version\-paths\fR, hot function paths are multi\- +versioned via cloning. This parameter specifies the maximum number of +functions that can be cloned. The default value is 10. +.IP "\fBlarge-function-insns\fR" 4 +.IX Item "large-function-insns" +The limit specifying really large functions. For functions larger than this +limit after inlining, inlining is constrained by +\&\fB\-\-param large-function-growth\fR. This parameter is useful primarily +to avoid extreme compilation time caused by non-linear algorithms used by the +backend. +The default value is 2700. +.IP "\fBlarge-function-growth\fR" 4 +.IX Item "large-function-growth" +Specifies maximal growth of large function caused by inlining in percents. +The default value is 100 which limits large function growth to 2.0 times +the original size. +.IP "\fBlarge-unit-insns\fR" 4 +.IX Item "large-unit-insns" +The limit specifying large translation unit. Growth caused by inlining of +units larger than this limit is limited by \fB\-\-param inline-unit-growth\fR. +For small units this might be too tight (consider unit consisting of function A +that is inline and B that just calls A three time. If B is small relative to +A, the growth of unit is 300\e% and yet such inlining is very sane. For very +large units consisting of small inlineable functions however the overall unit +growth limit is needed to avoid exponential explosion of code size. Thus for +smaller units, the size is increased to \fB\-\-param large-unit-insns\fR +before applying \fB\-\-param inline-unit-growth\fR. The default is 10000 +.IP "\fBinline-unit-growth\fR" 4 +.IX Item "inline-unit-growth" +Specifies maximal overall growth of the compilation unit caused by inlining. +The default value is 30 which limits unit growth to 1.3 times the original +size. +.IP "\fBipcp-unit-growth\fR" 4 +.IX Item "ipcp-unit-growth" +Specifies maximal overall growth of the compilation unit caused by +interprocedural constant propagation. The default value is 10 which limits +unit growth to 1.1 times the original size. +.IP "\fBlarge-stack-frame\fR" 4 +.IX Item "large-stack-frame" +The limit specifying large stack frames. While inlining the algorithm is trying +to not grow past this limit too much. Default value is 256 bytes. +.IP "\fBlarge-stack-frame-growth\fR" 4 +.IX Item "large-stack-frame-growth" +Specifies maximal growth of large stack frames caused by inlining in percents. +The default value is 1000 which limits large stack frame growth to 11 times +the original size. +.IP "\fBmax-inline-insns-recursive\fR" 4 +.IX Item "max-inline-insns-recursive" +.PD 0 +.IP "\fBmax-inline-insns-recursive-auto\fR" 4 +.IX Item "max-inline-insns-recursive-auto" +.PD +Specifies maximum number of instructions out-of-line copy of self recursive inline +function can grow into by performing recursive inlining. +.Sp +For functions declared inline \fB\-\-param max-inline-insns-recursive\fR is +taken into account. For function not declared inline, recursive inlining +happens only when \fB\-finline\-functions\fR (included in \fB\-O3\fR) is +enabled and \fB\-\-param max-inline-insns-recursive-auto\fR is used. The +default value is 450. +.IP "\fBmax-inline-recursive-depth\fR" 4 +.IX Item "max-inline-recursive-depth" +.PD 0 +.IP "\fBmax-inline-recursive-depth-auto\fR" 4 +.IX Item "max-inline-recursive-depth-auto" +.PD +Specifies maximum recursion depth used by the recursive inlining. +.Sp +For functions declared inline \fB\-\-param max-inline-recursive-depth\fR is +taken into account. For function not declared inline, recursive inlining +happens only when \fB\-finline\-functions\fR (included in \fB\-O3\fR) is +enabled and \fB\-\-param max-inline-recursive-depth-auto\fR is used. The +default value is 8. +.IP "\fBmin-inline-recursive-probability\fR" 4 +.IX Item "min-inline-recursive-probability" +Recursive inlining is profitable only for function having deep recursion +in average and can hurt for function having little recursion depth by +increasing the prologue size or complexity of function body to other +optimizers. +.Sp +When profile feedback is available (see \fB\-fprofile\-generate\fR) the actual +recursion depth can be guessed from probability that function will recurse via +given call expression. This parameter limits inlining only to call expression +whose probability exceeds given threshold (in percents). The default value is +10. +.IP "\fBearly-inlining-insns\fR" 4 +.IX Item "early-inlining-insns" +Specify growth that early inliner can make. In effect it increases amount of +inlining for code having large abstraction penalty. The default value is 10. +.IP "\fBmax-early-inliner-iterations\fR" 4 +.IX Item "max-early-inliner-iterations" +.PD 0 +.IP "\fBmax-early-inliner-iterations\fR" 4 +.IX Item "max-early-inliner-iterations" +.PD +Limit of iterations of early inliner. This basically bounds number of nested +indirect calls early inliner can resolve. Deeper chains are still handled by +late inlining. +.IP "\fBcomdat-sharing-probability\fR" 4 +.IX Item "comdat-sharing-probability" +.PD 0 +.IP "\fBcomdat-sharing-probability\fR" 4 +.IX Item "comdat-sharing-probability" +.PD +Probability (in percent) that \*(C+ inline function with comdat visibility +will be shared across multiple compilation units. The default value is 20. +.IP "\fBmin-vect-loop-bound\fR" 4 +.IX Item "min-vect-loop-bound" +The minimum number of iterations under which a loop will not get vectorized +when \fB\-ftree\-vectorize\fR is used. The number of iterations after +vectorization needs to be greater than the value specified by this option +to allow vectorization. The default value is 0. +.IP "\fBgcse-cost-distance-ratio\fR" 4 +.IX Item "gcse-cost-distance-ratio" +Scaling factor in calculation of maximum distance an expression +can be moved by \s-1GCSE\s0 optimizations. This is currently supported only in the +code hoisting pass. The bigger the ratio, the more aggressive code hoisting +will be with simple expressions, i.e., the expressions which have cost +less than \fBgcse-unrestricted-cost\fR. Specifying 0 will disable +hoisting of simple expressions. The default value is 10. +.IP "\fBgcse-unrestricted-cost\fR" 4 +.IX Item "gcse-unrestricted-cost" +Cost, roughly measured as the cost of a single typical machine +instruction, at which \s-1GCSE\s0 optimizations will not constrain +the distance an expression can travel. This is currently +supported only in the code hoisting pass. The lesser the cost, +the more aggressive code hoisting will be. Specifying 0 will +allow all expressions to travel unrestricted distances. +The default value is 3. +.IP "\fBmax-hoist-depth\fR" 4 +.IX Item "max-hoist-depth" +The depth of search in the dominator tree for expressions to hoist. +This is used to avoid quadratic behavior in hoisting algorithm. +The value of 0 will avoid limiting the search, but may slow down compilation +of huge functions. The default value is 30. +.IP "\fBmax-unrolled-insns\fR" 4 +.IX Item "max-unrolled-insns" +The maximum number of instructions that a loop should have if that loop +is unrolled, and if the loop is unrolled, it determines how many times +the loop code is unrolled. +.IP "\fBmax-average-unrolled-insns\fR" 4 +.IX Item "max-average-unrolled-insns" +The maximum number of instructions biased by probabilities of their execution +that a loop should have if that loop is unrolled, and if the loop is unrolled, +it determines how many times the loop code is unrolled. +.IP "\fBmax-unroll-times\fR" 4 +.IX Item "max-unroll-times" +The maximum number of unrollings of a single loop. +.IP "\fBmax-peeled-insns\fR" 4 +.IX Item "max-peeled-insns" +The maximum number of instructions that a loop should have if that loop +is peeled, and if the loop is peeled, it determines how many times +the loop code is peeled. +.IP "\fBmax-peel-times\fR" 4 +.IX Item "max-peel-times" +The maximum number of peelings of a single loop. +.IP "\fBmax-completely-peeled-insns\fR" 4 +.IX Item "max-completely-peeled-insns" +The maximum number of insns of a completely peeled loop. +.IP "\fBmax-completely-peeled-insns-feedback\fR" 4 +.IX Item "max-completely-peeled-insns-feedback" +The maximum number of insns of a completely peeled loop when profile +feedback is available and the loop is hot. Because of the real +profiles, this value may set to be larger for hot loops. Its default +value is 600. +.IP "\fBmax-once-peeled-insns\fR" 4 +.IX Item "max-once-peeled-insns" +The maximum number of insns of a peeled loop that rolls only once. +.IP "\fBmax-once-peeled-insns-feedback\fR" 4 +.IX Item "max-once-peeled-insns-feedback" +The maximum number of insns of a peeled loop when profile feedback is +available and the loop is hot. Because of the real profiles, this +value may set to be larger for hot loops. The default value is 600. +.IP "\fBmax-completely-peel-times\fR" 4 +.IX Item "max-completely-peel-times" +The maximum number of iterations of a loop to be suitable for complete peeling. +.IP "\fBmax-completely-peel-times-feedback\fR" 4 +.IX Item "max-completely-peel-times-feedback" +The maximum number of iterations of a loop to be suitable for complete +peeling when profile feedback is available and the loop is +hot. Because of the real profiles, this value may set to be larger for +hot loops. Its default value is 16. +.IP "\fBmax-completely-peel-loop-nest-depth\fR" 4 +.IX Item "max-completely-peel-loop-nest-depth" +The maximum depth of a loop nest suitable for complete peeling. +.IP "\fBcodesize-hotness-threshold\fR" 4 +.IX Item "codesize-hotness-threshold" +The minimum profile count of basic blocks to look at when estimating +the code size footprint of the call graph in a \s-1LIPO\s0 compile. +.IP "\fBunrollpeel-codesize-threshold\fR" 4 +.IX Item "unrollpeel-codesize-threshold" +Maximum \s-1LIPO\s0 code size footprint estimate for loop unrolling and peeling. +.IP "\fBmax-unswitch-insns\fR" 4 +.IX Item "max-unswitch-insns" +The maximum number of insns of an unswitched loop. +.IP "\fBmax-unswitch-level\fR" 4 +.IX Item "max-unswitch-level" +The maximum number of branches unswitched in a single loop. +.IP "\fBlim-expensive\fR" 4 +.IX Item "lim-expensive" +The minimum cost of an expensive expression in the loop invariant motion. +.IP "\fBiv-consider-all-candidates-bound\fR" 4 +.IX Item "iv-consider-all-candidates-bound" +Bound on number of candidates for induction variables below that +all candidates are considered for each use in induction variable +optimizations. Only the most relevant candidates are considered +if there are more candidates, to avoid quadratic time complexity. +.IP "\fBiv-max-considered-uses\fR" 4 +.IX Item "iv-max-considered-uses" +The induction variable optimizations give up on loops that contain more +induction variable uses. +.IP "\fBiv-always-prune-cand-set-bound\fR" 4 +.IX Item "iv-always-prune-cand-set-bound" +If number of candidates in the set is smaller than this value, +we always try to remove unnecessary ivs from the set during its +optimization when a new iv is added to the set. +.IP "\fBscev-max-expr-size\fR" 4 +.IX Item "scev-max-expr-size" +Bound on size of expressions used in the scalar evolutions analyzer. +Large expressions slow the analyzer. +.IP "\fBscev-max-expr-complexity\fR" 4 +.IX Item "scev-max-expr-complexity" +Bound on the complexity of the expressions in the scalar evolutions analyzer. +Complex expressions slow the analyzer. +.IP "\fBomega-max-vars\fR" 4 +.IX Item "omega-max-vars" +The maximum number of variables in an Omega constraint system. +The default value is 128. +.IP "\fBomega-max-geqs\fR" 4 +.IX Item "omega-max-geqs" +The maximum number of inequalities in an Omega constraint system. +The default value is 256. +.IP "\fBomega-max-eqs\fR" 4 +.IX Item "omega-max-eqs" +The maximum number of equalities in an Omega constraint system. +The default value is 128. +.IP "\fBomega-max-wild-cards\fR" 4 +.IX Item "omega-max-wild-cards" +The maximum number of wildcard variables that the Omega solver will +be able to insert. The default value is 18. +.IP "\fBomega-hash-table-size\fR" 4 +.IX Item "omega-hash-table-size" +The size of the hash table in the Omega solver. The default value is +550. +.IP "\fBomega-max-keys\fR" 4 +.IX Item "omega-max-keys" +The maximal number of keys used by the Omega solver. The default +value is 500. +.IP "\fBomega-eliminate-redundant-constraints\fR" 4 +.IX Item "omega-eliminate-redundant-constraints" +When set to 1, use expensive methods to eliminate all redundant +constraints. The default value is 0. +.IP "\fBvect-max-version-for-alignment-checks\fR" 4 +.IX Item "vect-max-version-for-alignment-checks" +The maximum number of runtime checks that can be performed when +doing loop versioning for alignment in the vectorizer. See option +ftree-vect-loop-version for more information. +.IP "\fBvect-max-version-for-alias-checks\fR" 4 +.IX Item "vect-max-version-for-alias-checks" +The maximum number of runtime checks that can be performed when +doing loop versioning for alias in the vectorizer. See option +ftree-vect-loop-version for more information. +.IP "\fBmax-iterations-to-track\fR" 4 +.IX Item "max-iterations-to-track" +The maximum number of iterations of a loop the brute force algorithm +for analysis of # of iterations of the loop tries to evaluate. +.IP "\fBhot-bb-count-fraction\fR" 4 +.IX Item "hot-bb-count-fraction" +Select fraction of the maximal count of repetitions of basic block in program +given basic block needs to have to be considered hot. +.IP "\fBhot-bb-frequency-fraction\fR" 4 +.IX Item "hot-bb-frequency-fraction" +Select fraction of the entry block frequency of executions of basic block in +function given basic block needs to have to be considered hot +.IP "\fBmax-predicted-iterations\fR" 4 +.IX Item "max-predicted-iterations" +The maximum number of loop iterations we predict statically. This is useful +in cases where function contain single loop with known bound and other loop +with unknown. We predict the known number of iterations correctly, while +the unknown number of iterations average to roughly 10. This means that the +loop without bounds would appear artificially cold relative to the other one. +.IP "\fBalign-threshold\fR" 4 +.IX Item "align-threshold" +Select fraction of the maximal frequency of executions of basic block in +function given basic block will get aligned. +.IP "\fBalign-loop-iterations\fR" 4 +.IX Item "align-loop-iterations" +A loop expected to iterate at lest the selected number of iterations will get +aligned. +.IP "\fBtracer-dynamic-coverage\fR" 4 +.IX Item "tracer-dynamic-coverage" +.PD 0 +.IP "\fBtracer-dynamic-coverage-feedback\fR" 4 +.IX Item "tracer-dynamic-coverage-feedback" +.PD +This value is used to limit superblock formation once the given percentage of +executed instructions is covered. This limits unnecessary code size +expansion. +.Sp +The \fBtracer-dynamic-coverage-feedback\fR is used only when profile +feedback is available. The real profiles (as opposed to statically estimated +ones) are much less balanced allowing the threshold to be larger value. +.IP "\fBtracer-max-code-growth\fR" 4 +.IX Item "tracer-max-code-growth" +Stop tail duplication once code growth has reached given percentage. This is +rather hokey argument, as most of the duplicates will be eliminated later in +cross jumping, so it may be set to much higher values than is the desired code +growth. +.IP "\fBtracer-min-branch-ratio\fR" 4 +.IX Item "tracer-min-branch-ratio" +Stop reverse growth when the reverse probability of best edge is less than this +threshold (in percent). +.IP "\fBtracer-min-branch-ratio\fR" 4 +.IX Item "tracer-min-branch-ratio" +.PD 0 +.IP "\fBtracer-min-branch-ratio-feedback\fR" 4 +.IX Item "tracer-min-branch-ratio-feedback" +.PD +Stop forward growth if the best edge do have probability lower than this +threshold. +.Sp +Similarly to \fBtracer-dynamic-coverage\fR two values are present, one for +compilation for profile feedback and one for compilation without. The value +for compilation with profile feedback needs to be more conservative (higher) in +order to make tracer effective. +.IP "\fBmax-cse-path-length\fR" 4 +.IX Item "max-cse-path-length" +Maximum number of basic blocks on path that cse considers. The default is 10. +.IP "\fBmax-cse-insns\fR" 4 +.IX Item "max-cse-insns" +The maximum instructions \s-1CSE\s0 process before flushing. The default is 1000. +.IP "\fBggc-min-expand\fR" 4 +.IX Item "ggc-min-expand" +\&\s-1GCC\s0 uses a garbage collector to manage its own memory allocation. This +parameter specifies the minimum percentage by which the garbage +collector's heap should be allowed to expand between collections. +Tuning this may improve compilation speed; it has no effect on code +generation. +.Sp +The default is 30% + 70% * (\s-1RAM/1GB\s0) with an upper bound of 100% when +\&\s-1RAM\s0 >= 1GB. If \f(CW\*(C`getrlimit\*(C'\fR is available, the notion of \*(L"\s-1RAM\s0\*(R" is +the smallest of actual \s-1RAM\s0 and \f(CW\*(C`RLIMIT_DATA\*(C'\fR or \f(CW\*(C`RLIMIT_AS\*(C'\fR. If +\&\s-1GCC\s0 is not able to calculate \s-1RAM\s0 on a particular platform, the lower +bound of 30% is used. Setting this parameter and +\&\fBggc-min-heapsize\fR to zero causes a full collection to occur at +every opportunity. This is extremely slow, but can be useful for +debugging. +.IP "\fBggc-min-heapsize\fR" 4 +.IX Item "ggc-min-heapsize" +Minimum size of the garbage collector's heap before it begins bothering +to collect garbage. The first collection occurs after the heap expands +by \fBggc-min-expand\fR% beyond \fBggc-min-heapsize\fR. Again, +tuning this may improve compilation speed, and has no effect on code +generation. +.Sp +The default is the smaller of \s-1RAM/8\s0, \s-1RLIMIT_RSS\s0, or a limit which +tries to ensure that \s-1RLIMIT_DATA\s0 or \s-1RLIMIT_AS\s0 are not exceeded, but +with a lower bound of 4096 (four megabytes) and an upper bound of +131072 (128 megabytes). If \s-1GCC\s0 is not able to calculate \s-1RAM\s0 on a +particular platform, the lower bound is used. Setting this parameter +very large effectively disables garbage collection. Setting this +parameter and \fBggc-min-expand\fR to zero causes a full collection +to occur at every opportunity. +.IP "\fBmax-reload-search-insns\fR" 4 +.IX Item "max-reload-search-insns" +The maximum number of instruction reload should look backward for equivalent +register. Increasing values mean more aggressive optimization, making the +compile time increase with probably slightly better performance. The default +value is 100. +.IP "\fBmax-cselib-memory-locations\fR" 4 +.IX Item "max-cselib-memory-locations" +The maximum number of memory locations cselib should take into account. +Increasing values mean more aggressive optimization, making the compile time +increase with probably slightly better performance. The default value is 500. +.IP "\fBreorder-blocks-duplicate\fR" 4 +.IX Item "reorder-blocks-duplicate" +.PD 0 +.IP "\fBreorder-blocks-duplicate-feedback\fR" 4 +.IX Item "reorder-blocks-duplicate-feedback" +.PD +Used by basic block reordering pass to decide whether to use unconditional +branch or duplicate the code on its destination. Code is duplicated when its +estimated size is smaller than this value multiplied by the estimated size of +unconditional jump in the hot spots of the program. +.Sp +The \fBreorder-block-duplicate-feedback\fR is used only when profile +feedback is available and may be set to higher values than +\&\fBreorder-block-duplicate\fR since information about the hot spots is more +accurate. +.IP "\fBmax-sched-ready-insns\fR" 4 +.IX Item "max-sched-ready-insns" +The maximum number of instructions ready to be issued the scheduler should +consider at any given time during the first scheduling pass. Increasing +values mean more thorough searches, making the compilation time increase +with probably little benefit. The default value is 100. +.IP "\fBmax-sched-region-blocks\fR" 4 +.IX Item "max-sched-region-blocks" +The maximum number of blocks in a region to be considered for +interblock scheduling. The default value is 10. +.IP "\fBmax-pipeline-region-blocks\fR" 4 +.IX Item "max-pipeline-region-blocks" +The maximum number of blocks in a region to be considered for +pipelining in the selective scheduler. The default value is 15. +.IP "\fBmax-sched-region-insns\fR" 4 +.IX Item "max-sched-region-insns" +The maximum number of insns in a region to be considered for +interblock scheduling. The default value is 100. +.IP "\fBmax-pipeline-region-insns\fR" 4 +.IX Item "max-pipeline-region-insns" +The maximum number of insns in a region to be considered for +pipelining in the selective scheduler. The default value is 200. +.IP "\fBmin-spec-prob\fR" 4 +.IX Item "min-spec-prob" +The minimum probability (in percents) of reaching a source block +for interblock speculative scheduling. The default value is 40. +.IP "\fBmax-sched-extend-regions-iters\fR" 4 +.IX Item "max-sched-extend-regions-iters" +The maximum number of iterations through \s-1CFG\s0 to extend regions. +0 \- disable region extension, +N \- do at most N iterations. +The default value is 0. +.IP "\fBmax-sched-insn-conflict-delay\fR" 4 +.IX Item "max-sched-insn-conflict-delay" +The maximum conflict delay for an insn to be considered for speculative motion. +The default value is 3. +.IP "\fBsched-spec-prob-cutoff\fR" 4 +.IX Item "sched-spec-prob-cutoff" +The minimal probability of speculation success (in percents), so that +speculative insn will be scheduled. +The default value is 40. +.IP "\fBsched-mem-true-dep-cost\fR" 4 +.IX Item "sched-mem-true-dep-cost" +Minimal distance (in \s-1CPU\s0 cycles) between store and load targeting same +memory locations. The default value is 1. +.IP "\fBselsched-max-lookahead\fR" 4 +.IX Item "selsched-max-lookahead" +The maximum size of the lookahead window of selective scheduling. It is a +depth of search for available instructions. +The default value is 50. +.IP "\fBselsched-max-sched-times\fR" 4 +.IX Item "selsched-max-sched-times" +The maximum number of times that an instruction will be scheduled during +selective scheduling. This is the limit on the number of iterations +through which the instruction may be pipelined. The default value is 2. +.IP "\fBselsched-max-insns-to-rename\fR" 4 +.IX Item "selsched-max-insns-to-rename" +The maximum number of best instructions in the ready list that are considered +for renaming in the selective scheduler. The default value is 2. +.IP "\fBmax-last-value-rtl\fR" 4 +.IX Item "max-last-value-rtl" +The maximum size measured as number of RTLs that can be recorded in an expression +in combiner for a pseudo register as last known value of that register. The default +is 10000. +.IP "\fBinteger-share-limit\fR" 4 +.IX Item "integer-share-limit" +Small integer constants can use a shared data structure, reducing the +compiler's memory usage and increasing its speed. This sets the maximum +value of a shared integer constant. The default value is 256. +.IP "\fBmin-virtual-mappings\fR" 4 +.IX Item "min-virtual-mappings" +Specifies the minimum number of virtual mappings in the incremental +\&\s-1SSA\s0 updater that should be registered to trigger the virtual mappings +heuristic defined by virtual-mappings-ratio. The default value is +100. +.IP "\fBvirtual-mappings-ratio\fR" 4 +.IX Item "virtual-mappings-ratio" +If the number of virtual mappings is virtual-mappings-ratio bigger +than the number of virtual symbols to be updated, then the incremental +\&\s-1SSA\s0 updater switches to a full update for those symbols. The default +ratio is 3. +.IP "\fBssp-buffer-size\fR" 4 +.IX Item "ssp-buffer-size" +The minimum size of buffers (i.e. arrays) that will receive stack smashing +protection when \fB\-fstack\-protection\fR is used. +.IP "\fBmax-jump-thread-duplication-stmts\fR" 4 +.IX Item "max-jump-thread-duplication-stmts" +Maximum number of statements allowed in a block that needs to be +duplicated when threading jumps. +.IP "\fBmax-fields-for-field-sensitive\fR" 4 +.IX Item "max-fields-for-field-sensitive" +Maximum number of fields in a structure we will treat in +a field sensitive manner during pointer analysis. The default is zero +for \-O0, and \-O1 and 100 for \-Os, \-O2, and \-O3. +.IP "\fBprefetch-latency\fR" 4 +.IX Item "prefetch-latency" +Estimate on average number of instructions that are executed before +prefetch finishes. The distance we prefetch ahead is proportional +to this constant. Increasing this number may also lead to less +streams being prefetched (see \fBsimultaneous-prefetches\fR). +.IP "\fBsimultaneous-prefetches\fR" 4 +.IX Item "simultaneous-prefetches" +Maximum number of prefetches that can run at the same time. +.IP "\fBl1\-cache\-line\-size\fR" 4 +.IX Item "l1-cache-line-size" +The size of cache line in L1 cache, in bytes. +.IP "\fBl1\-cache\-size\fR" 4 +.IX Item "l1-cache-size" +The size of L1 cache, in kilobytes. +.IP "\fBl2\-cache\-size\fR" 4 +.IX Item "l2-cache-size" +The size of L2 cache, in kilobytes. +.IP "\fBmin-insn-to-prefetch-ratio\fR" 4 +.IX Item "min-insn-to-prefetch-ratio" +The minimum ratio between the number of instructions and the +number of prefetches to enable prefetching in a loop. +.IP "\fBprefetch-min-insn-to-mem-ratio\fR" 4 +.IX Item "prefetch-min-insn-to-mem-ratio" +The minimum ratio between the number of instructions and the +number of memory references to enable prefetching in a loop. +.IP "\fBuse-canonical-types\fR" 4 +.IX Item "use-canonical-types" +Whether the compiler should use the \*(L"canonical\*(R" type system. By +default, this should always be 1, which uses a more efficient internal +mechanism for comparing types in \*(C+ and Objective\-\*(C+. However, if +bugs in the canonical type system are causing compilation failures, +set this value to 0 to disable canonical types. +.IP "\fBswitch-conversion-max-branch-ratio\fR" 4 +.IX Item "switch-conversion-max-branch-ratio" +Switch initialization conversion will refuse to create arrays that are +bigger than \fBswitch-conversion-max-branch-ratio\fR times the number of +branches in the switch. +.IP "\fBmax-partial-antic-length\fR" 4 +.IX Item "max-partial-antic-length" +Maximum length of the partial antic set computed during the tree +partial redundancy elimination optimization (\fB\-ftree\-pre\fR) when +optimizing at \fB\-O3\fR and above. For some sorts of source code +the enhanced partial redundancy elimination optimization can run away, +consuming all of the memory available on the host machine. This +parameter sets a limit on the length of the sets that are computed, +which prevents the runaway behavior. Setting a value of 0 for +this parameter will allow an unlimited set length. +.IP "\fBsccvn-max-scc-size\fR" 4 +.IX Item "sccvn-max-scc-size" +Maximum size of a strongly connected component (\s-1SCC\s0) during \s-1SCCVN\s0 +processing. If this limit is hit, \s-1SCCVN\s0 processing for the whole +function will not be done and optimizations depending on it will +be disabled. The default maximum \s-1SCC\s0 size is 10000. +.IP "\fBira-max-loops-num\fR" 4 +.IX Item "ira-max-loops-num" +\&\s-1IRA\s0 uses a regional register allocation by default. If a function +contains loops more than number given by the parameter, only at most +given number of the most frequently executed loops will form regions +for the regional register allocation. The default value of the +parameter is 100. +.IP "\fBira-max-conflict-table-size\fR" 4 +.IX Item "ira-max-conflict-table-size" +Although \s-1IRA\s0 uses a sophisticated algorithm of compression conflict +table, the table can be still big for huge functions. If the conflict +table for a function could be more than size in \s-1MB\s0 given by the +parameter, the conflict table is not built and faster, simpler, and +lower quality register allocation algorithm will be used. The +algorithm do not use pseudo-register conflicts. The default value of +the parameter is 2000. +.IP "\fBira-loop-reserved-regs\fR" 4 +.IX Item "ira-loop-reserved-regs" +\&\s-1IRA\s0 can be used to evaluate more accurate register pressure in loops +for decision to move loop invariants (see \fB\-O3\fR). The number +of available registers reserved for some other purposes is described +by this parameter. The default value of the parameter is 2 which is +minimal number of registers needed for execution of typical +instruction. This value is the best found from numerous experiments. +.IP "\fBloop-invariant-max-bbs-in-loop\fR" 4 +.IX Item "loop-invariant-max-bbs-in-loop" +Loop invariant motion can be very expensive, both in compile time and +in amount of needed compile time memory, with very large loops. Loops +with more basic blocks than this parameter won't have loop invariant +motion optimization performed on them. The default value of the +parameter is 1000 for \-O1 and 10000 for \-O2 and above. +.IP "\fBmax-vartrack-size\fR" 4 +.IX Item "max-vartrack-size" +Sets a maximum number of hash table slots to use during variable +tracking dataflow analysis of any function. If this limit is exceeded +with variable tracking at assignments enabled, analysis for that +function is retried without it, after removing all debug insns from +the function. If the limit is exceeded even without debug insns, var +tracking analysis is completely disabled for the function. Setting +the parameter to zero makes it unlimited. +.IP "\fBmin-nondebug-insn-uid\fR" 4 +.IX Item "min-nondebug-insn-uid" +Use uids starting at this parameter for nondebug insns. The range below +the parameter is reserved exclusively for debug insns created by +\&\fB\-fvar\-tracking\-assignments\fR, but debug insns may get +(non-overlapping) uids above it if the reserved range is exhausted. +.IP "\fBipa-sra-ptr-growth-factor\fR" 4 +.IX Item "ipa-sra-ptr-growth-factor" +IPA-SRA will replace a pointer to an aggregate with one or more new +parameters only when their cumulative size is less or equal to +\&\fBipa-sra-ptr-growth-factor\fR times the size of the original +pointer parameter. +.IP "\fBgraphite-max-nb-scop-params\fR" 4 +.IX Item "graphite-max-nb-scop-params" +To avoid exponential effects in the Graphite loop transforms, the +number of parameters in a Static Control Part (SCoP) is bounded. The +default value is 10 parameters. A variable whose value is unknown at +compile time and defined outside a SCoP is a parameter of the SCoP. +.IP "\fBgraphite-max-bbs-per-function\fR" 4 +.IX Item "graphite-max-bbs-per-function" +To avoid exponential effects in the detection of SCoPs, the size of +the functions analyzed by Graphite is bounded. The default value is +100 basic blocks. +.IP "\fBloop-block-tile-size\fR" 4 +.IX Item "loop-block-tile-size" +Loop blocking or strip mining transforms, enabled with +\&\fB\-floop\-block\fR or \fB\-floop\-strip\-mine\fR, strip mine each +loop in the loop nest by a given number of iterations. The strip +length can be changed using the \fBloop-block-tile-size\fR +parameter. The default value is 51 iterations. +.IP "\fBdevirt-type-list-size\fR" 4 +.IX Item "devirt-type-list-size" +IPA-CP attempts to track all possible types passed to a function's +parameter in order to perform devirtualization. +\&\fBdevirt-type-list-size\fR is the maximum number of types it +stores per a single formal parameter of a function. +.IP "\fBlto-partitions\fR" 4 +.IX Item "lto-partitions" +Specify desired number of partitions produced during \s-1WHOPR\s0 compilation. +The number of partitions should exceed the number of CPUs used for compilation. +The default value is 32. +.IP "\fBlto-minpartition\fR" 4 +.IX Item "lto-minpartition" +Size of minimal partition for \s-1WHOPR\s0 (in estimated instructions). +This prevents expenses of splitting very small programs into too many +partitions. +.IP "\fBcxx-max-namespaces-for-diagnostic-help\fR" 4 +.IX Item "cxx-max-namespaces-for-diagnostic-help" +The maximum number of namespaces to consult for suggestions when \*(C+ +name lookup fails for an identifier. The default is 1000. +.RE +.RS 4 +.RE +.SS "Options Controlling the Preprocessor" +.IX Subsection "Options Controlling the Preprocessor" +These options control the C preprocessor, which is run on each C source +file before actual compilation. +.PP +If you use the \fB\-E\fR option, nothing is done except preprocessing. +Some of these options make sense only together with \fB\-E\fR because +they cause the preprocessor output to be unsuitable for actual +compilation. +.IP "\fB\-Wp,\fR\fIoption\fR" 4 +.IX Item "-Wp,option" +You can use \fB\-Wp,\fR\fIoption\fR to bypass the compiler driver +and pass \fIoption\fR directly through to the preprocessor. If +\&\fIoption\fR contains commas, it is split into multiple options at the +commas. However, many options are modified, translated or interpreted +by the compiler driver before being passed to the preprocessor, and +\&\fB\-Wp\fR forcibly bypasses this phase. The preprocessor's direct +interface is undocumented and subject to change, so whenever possible +you should avoid using \fB\-Wp\fR and let the driver handle the +options instead. +.IP "\fB\-Xpreprocessor\fR \fIoption\fR" 4 +.IX Item "-Xpreprocessor option" +Pass \fIoption\fR as an option to the preprocessor. You can use this to +supply system-specific preprocessor options which \s-1GCC\s0 does not know how to +recognize. +.Sp +If you want to pass an option that takes an argument, you must use +\&\fB\-Xpreprocessor\fR twice, once for the option and once for the argument. +.IP "\fB\-D\fR \fIname\fR" 4 +.IX Item "-D name" +Predefine \fIname\fR as a macro, with definition \f(CW1\fR. +.IP "\fB\-D\fR \fIname\fR\fB=\fR\fIdefinition\fR" 4 +.IX Item "-D name=definition" +The contents of \fIdefinition\fR are tokenized and processed as if +they appeared during translation phase three in a \fB#define\fR +directive. In particular, the definition will be truncated by +embedded newline characters. +.Sp +If you are invoking the preprocessor from a shell or shell-like +program you may need to use the shell's quoting syntax to protect +characters such as spaces that have a meaning in the shell syntax. +.Sp +If you wish to define a function-like macro on the command line, write +its argument list with surrounding parentheses before the equals sign +(if any). Parentheses are meaningful to most shells, so you will need +to quote the option. With \fBsh\fR and \fBcsh\fR, +\&\fB\-D'\fR\fIname\fR\fB(\fR\fIargs...\fR\fB)=\fR\fIdefinition\fR\fB'\fR works. +.Sp +\&\fB\-D\fR and \fB\-U\fR options are processed in the order they +are given on the command line. All \fB\-imacros\fR \fIfile\fR and +\&\fB\-include\fR \fIfile\fR options are processed after all +\&\fB\-D\fR and \fB\-U\fR options. +.IP "\fB\-U\fR \fIname\fR" 4 +.IX Item "-U name" +Cancel any previous definition of \fIname\fR, either built in or +provided with a \fB\-D\fR option. +.IP "\fB\-undef\fR" 4 +.IX Item "-undef" +Do not predefine any system-specific or GCC-specific macros. The +standard predefined macros remain defined. +.IP "\fB\-I\fR \fIdir\fR" 4 +.IX Item "-I dir" +Add the directory \fIdir\fR to the list of directories to be searched +for header files. +Directories named by \fB\-I\fR are searched before the standard +system include directories. If the directory \fIdir\fR is a standard +system include directory, the option is ignored to ensure that the +default search order for system directories and the special treatment +of system headers are not defeated +\&. +If \fIdir\fR begins with \f(CW\*(C`=\*(C'\fR, then the \f(CW\*(C`=\*(C'\fR will be replaced +by the sysroot prefix; see \fB\-\-sysroot\fR and \fB\-isysroot\fR. +.IP "\fB\-o\fR \fIfile\fR" 4 +.IX Item "-o file" +Write output to \fIfile\fR. This is the same as specifying \fIfile\fR +as the second non-option argument to \fBcpp\fR. \fBgcc\fR has a +different interpretation of a second non-option argument, so you must +use \fB\-o\fR to specify the output file. +.IP "\fB\-Wall\fR" 4 +.IX Item "-Wall" +Turns on all optional warnings which are desirable for normal code. +At present this is \fB\-Wcomment\fR, \fB\-Wtrigraphs\fR, +\&\fB\-Wmultichar\fR and a warning about integer promotion causing a +change of sign in \f(CW\*(C`#if\*(C'\fR expressions. Note that many of the +preprocessor's warnings are on by default and have no options to +control them. +.IP "\fB\-Wcomment\fR" 4 +.IX Item "-Wcomment" +.PD 0 +.IP "\fB\-Wcomments\fR" 4 +.IX Item "-Wcomments" +.PD +Warn whenever a comment-start sequence \fB/*\fR appears in a \fB/*\fR +comment, or whenever a backslash-newline appears in a \fB//\fR comment. +(Both forms have the same effect.) +.IP "\fB\-Wtrigraphs\fR" 4 +.IX Item "-Wtrigraphs" +Most trigraphs in comments cannot affect the meaning of the program. +However, a trigraph that would form an escaped newline (\fB??/\fR at +the end of a line) can, by changing where the comment begins or ends. +Therefore, only trigraphs that would form escaped newlines produce +warnings inside a comment. +.Sp +This option is implied by \fB\-Wall\fR. If \fB\-Wall\fR is not +given, this option is still enabled unless trigraphs are enabled. To +get trigraph conversion without warnings, but get the other +\&\fB\-Wall\fR warnings, use \fB\-trigraphs \-Wall \-Wno\-trigraphs\fR. +.IP "\fB\-Wtraditional\fR" 4 +.IX Item "-Wtraditional" +Warn about certain constructs that behave differently in traditional and +\&\s-1ISO\s0 C. Also warn about \s-1ISO\s0 C constructs that have no traditional C +equivalent, and problematic constructs which should be avoided. +.IP "\fB\-Wundef\fR" 4 +.IX Item "-Wundef" +Warn whenever an identifier which is not a macro is encountered in an +\&\fB#if\fR directive, outside of \fBdefined\fR. Such identifiers are +replaced with zero. +.IP "\fB\-Wunused\-macros\fR" 4 +.IX Item "-Wunused-macros" +Warn about macros defined in the main file that are unused. A macro +is \fIused\fR if it is expanded or tested for existence at least once. +The preprocessor will also warn if the macro has not been used at the +time it is redefined or undefined. +.Sp +Built-in macros, macros defined on the command line, and macros +defined in include files are not warned about. +.Sp +\&\fINote:\fR If a macro is actually used, but only used in skipped +conditional blocks, then \s-1CPP\s0 will report it as unused. To avoid the +warning in such a case, you might improve the scope of the macro's +definition by, for example, moving it into the first skipped block. +Alternatively, you could provide a dummy use with something like: +.Sp +.Vb 2 +\& #if defined the_macro_causing_the_warning +\& #endif +.Ve +.IP "\fB\-Wendif\-labels\fR" 4 +.IX Item "-Wendif-labels" +Warn whenever an \fB#else\fR or an \fB#endif\fR are followed by text. +This usually happens in code of the form +.Sp +.Vb 5 +\& #if FOO +\& ... +\& #else FOO +\& ... +\& #endif FOO +.Ve +.Sp +The second and third \f(CW\*(C`FOO\*(C'\fR should be in comments, but often are not +in older programs. This warning is on by default. +.IP "\fB\-Werror\fR" 4 +.IX Item "-Werror" +Make all warnings into hard errors. Source code which triggers warnings +will be rejected. +.IP "\fB\-Wsystem\-headers\fR" 4 +.IX Item "-Wsystem-headers" +Issue warnings for code in system headers. These are normally unhelpful +in finding bugs in your own code, therefore suppressed. If you are +responsible for the system library, you may want to see them. +.IP "\fB\-w\fR" 4 +.IX Item "-w" +Suppress all warnings, including those which \s-1GNU\s0 \s-1CPP\s0 issues by default. +.IP "\fB\-pedantic\fR" 4 +.IX Item "-pedantic" +Issue all the mandatory diagnostics listed in the C standard. Some of +them are left out by default, since they trigger frequently on harmless +code. +.IP "\fB\-pedantic\-errors\fR" 4 +.IX Item "-pedantic-errors" +Issue all the mandatory diagnostics, and make all mandatory diagnostics +into errors. This includes mandatory diagnostics that \s-1GCC\s0 issues +without \fB\-pedantic\fR but treats as warnings. +.IP "\fB\-M\fR" 4 +.IX Item "-M" +Instead of outputting the result of preprocessing, output a rule +suitable for \fBmake\fR describing the dependencies of the main +source file. The preprocessor outputs one \fBmake\fR rule containing +the object file name for that source file, a colon, and the names of all +the included files, including those coming from \fB\-include\fR or +\&\fB\-imacros\fR command line options. +.Sp +Unless specified explicitly (with \fB\-MT\fR or \fB\-MQ\fR), the +object file name consists of the name of the source file with any +suffix replaced with object file suffix and with any leading directory +parts removed. If there are many included files then the rule is +split into several lines using \fB\e\fR\-newline. The rule has no +commands. +.Sp +This option does not suppress the preprocessor's debug output, such as +\&\fB\-dM\fR. To avoid mixing such debug output with the dependency +rules you should explicitly specify the dependency output file with +\&\fB\-MF\fR, or use an environment variable like +\&\fB\s-1DEPENDENCIES_OUTPUT\s0\fR. Debug output +will still be sent to the regular output stream as normal. +.Sp +Passing \fB\-M\fR to the driver implies \fB\-E\fR, and suppresses +warnings with an implicit \fB\-w\fR. +.IP "\fB\-MM\fR" 4 +.IX Item "-MM" +Like \fB\-M\fR but do not mention header files that are found in +system header directories, nor header files that are included, +directly or indirectly, from such a header. +.Sp +This implies that the choice of angle brackets or double quotes in an +\&\fB#include\fR directive does not in itself determine whether that +header will appear in \fB\-MM\fR dependency output. This is a +slight change in semantics from \s-1GCC\s0 versions 3.0 and earlier. +.IP "\fB\-MF\fR \fIfile\fR" 4 +.IX Item "-MF file" +When used with \fB\-M\fR or \fB\-MM\fR, specifies a +file to write the dependencies to. If no \fB\-MF\fR switch is given +the preprocessor sends the rules to the same place it would have sent +preprocessed output. +.Sp +When used with the driver options \fB\-MD\fR or \fB\-MMD\fR, +\&\fB\-MF\fR overrides the default dependency output file. +.IP "\fB\-MG\fR" 4 +.IX Item "-MG" +In conjunction with an option such as \fB\-M\fR requesting +dependency generation, \fB\-MG\fR assumes missing header files are +generated files and adds them to the dependency list without raising +an error. The dependency filename is taken directly from the +\&\f(CW\*(C`#include\*(C'\fR directive without prepending any path. \fB\-MG\fR +also suppresses preprocessed output, as a missing header file renders +this useless. +.Sp +This feature is used in automatic updating of makefiles. +.IP "\fB\-MP\fR" 4 +.IX Item "-MP" +This option instructs \s-1CPP\s0 to add a phony target for each dependency +other than the main file, causing each to depend on nothing. These +dummy rules work around errors \fBmake\fR gives if you remove header +files without updating the \fIMakefile\fR to match. +.Sp +This is typical output: +.Sp +.Vb 1 +\& test.o: test.c test.h +\& +\& test.h: +.Ve +.IP "\fB\-MT\fR \fItarget\fR" 4 +.IX Item "-MT target" +Change the target of the rule emitted by dependency generation. By +default \s-1CPP\s0 takes the name of the main input file, deletes any +directory components and any file suffix such as \fB.c\fR, and +appends the platform's usual object suffix. The result is the target. +.Sp +An \fB\-MT\fR option will set the target to be exactly the string you +specify. If you want multiple targets, you can specify them as a single +argument to \fB\-MT\fR, or use multiple \fB\-MT\fR options. +.Sp +For example, \fB\-MT\ '$(objpfx)foo.o'\fR might give +.Sp +.Vb 1 +\& $(objpfx)foo.o: foo.c +.Ve +.IP "\fB\-MQ\fR \fItarget\fR" 4 +.IX Item "-MQ target" +Same as \fB\-MT\fR, but it quotes any characters which are special to +Make. \fB\-MQ\ '$(objpfx)foo.o'\fR gives +.Sp +.Vb 1 +\& $$(objpfx)foo.o: foo.c +.Ve +.Sp +The default target is automatically quoted, as if it were given with +\&\fB\-MQ\fR. +.IP "\fB\-MD\fR" 4 +.IX Item "-MD" +\&\fB\-MD\fR is equivalent to \fB\-M \-MF\fR \fIfile\fR, except that +\&\fB\-E\fR is not implied. The driver determines \fIfile\fR based on +whether an \fB\-o\fR option is given. If it is, the driver uses its +argument but with a suffix of \fI.d\fR, otherwise it takes the name +of the input file, removes any directory components and suffix, and +applies a \fI.d\fR suffix. +.Sp +If \fB\-MD\fR is used in conjunction with \fB\-E\fR, any +\&\fB\-o\fR switch is understood to specify the dependency output file, but if used without \fB\-E\fR, each \fB\-o\fR +is understood to specify a target object file. +.Sp +Since \fB\-E\fR is not implied, \fB\-MD\fR can be used to generate +a dependency output file as a side-effect of the compilation process. +.IP "\fB\-MMD\fR" 4 +.IX Item "-MMD" +Like \fB\-MD\fR except mention only user header files, not system +header files. +.IP "\fB\-fpch\-deps\fR" 4 +.IX Item "-fpch-deps" +When using precompiled headers, this flag +will cause the dependency-output flags to also list the files from the +precompiled header's dependencies. If not specified only the +precompiled header would be listed and not the files that were used to +create it because those files are not consulted when a precompiled +header is used. +.IP "\fB\-fpch\-preprocess\fR" 4 +.IX Item "-fpch-preprocess" +This option allows use of a precompiled header together with \fB\-E\fR. It inserts a special \f(CW\*(C`#pragma\*(C'\fR, +\&\f(CW\*(C`#pragma GCC pch_preprocess "\f(CIfilename\f(CW"\*(C'\fR in the output to mark +the place where the precompiled header was found, and its \fIfilename\fR. +When \fB\-fpreprocessed\fR is in use, \s-1GCC\s0 recognizes this \f(CW\*(C`#pragma\*(C'\fR +and loads the \s-1PCH\s0. +.Sp +This option is off by default, because the resulting preprocessed output +is only really suitable as input to \s-1GCC\s0. It is switched on by +\&\fB\-save\-temps\fR. +.Sp +You should not write this \f(CW\*(C`#pragma\*(C'\fR in your own code, but it is +safe to edit the filename if the \s-1PCH\s0 file is available in a different +location. The filename may be absolute or it may be relative to \s-1GCC\s0's +current directory. +.IP "\fB\-x c\fR" 4 +.IX Item "-x c" +.PD 0 +.IP "\fB\-x c++\fR" 4 +.IX Item "-x c++" +.IP "\fB\-x objective-c\fR" 4 +.IX Item "-x objective-c" +.IP "\fB\-x assembler-with-cpp\fR" 4 +.IX Item "-x assembler-with-cpp" +.PD +Specify the source language: C, \*(C+, Objective-C, or assembly. This has +nothing to do with standards conformance or extensions; it merely +selects which base syntax to expect. If you give none of these options, +cpp will deduce the language from the extension of the source file: +\&\fB.c\fR, \fB.cc\fR, \fB.m\fR, or \fB.S\fR. Some other common +extensions for \*(C+ and assembly are also recognized. If cpp does not +recognize the extension, it will treat the file as C; this is the most +generic mode. +.Sp +\&\fINote:\fR Previous versions of cpp accepted a \fB\-lang\fR option +which selected both the language and the standards conformance level. +This option has been removed, because it conflicts with the \fB\-l\fR +option. +.IP "\fB\-std=\fR\fIstandard\fR" 4 +.IX Item "-std=standard" +.PD 0 +.IP "\fB\-ansi\fR" 4 +.IX Item "-ansi" +.PD +Specify the standard to which the code should conform. Currently \s-1CPP\s0 +knows about C and \*(C+ standards; others may be added in the future. +.Sp +\&\fIstandard\fR +may be one of: +.RS 4 +.ie n .IP """c90""" 4 +.el .IP "\f(CWc90\fR" 4 +.IX Item "c90" +.PD 0 +.ie n .IP """c89""" 4 +.el .IP "\f(CWc89\fR" 4 +.IX Item "c89" +.ie n .IP """iso9899:1990""" 4 +.el .IP "\f(CWiso9899:1990\fR" 4 +.IX Item "iso9899:1990" +.PD +The \s-1ISO\s0 C standard from 1990. \fBc90\fR is the customary shorthand for +this version of the standard. +.Sp +The \fB\-ansi\fR option is equivalent to \fB\-std=c90\fR. +.ie n .IP """iso9899:199409""" 4 +.el .IP "\f(CWiso9899:199409\fR" 4 +.IX Item "iso9899:199409" +The 1990 C standard, as amended in 1994. +.ie n .IP """iso9899:1999""" 4 +.el .IP "\f(CWiso9899:1999\fR" 4 +.IX Item "iso9899:1999" +.PD 0 +.ie n .IP """c99""" 4 +.el .IP "\f(CWc99\fR" 4 +.IX Item "c99" +.ie n .IP """iso9899:199x""" 4 +.el .IP "\f(CWiso9899:199x\fR" 4 +.IX Item "iso9899:199x" +.ie n .IP """c9x""" 4 +.el .IP "\f(CWc9x\fR" 4 +.IX Item "c9x" +.PD +The revised \s-1ISO\s0 C standard, published in December 1999. Before +publication, this was known as C9X. +.ie n .IP """c1x""" 4 +.el .IP "\f(CWc1x\fR" 4 +.IX Item "c1x" +The next version of the \s-1ISO\s0 C standard, still under development. +.ie n .IP """gnu90""" 4 +.el .IP "\f(CWgnu90\fR" 4 +.IX Item "gnu90" +.PD 0 +.ie n .IP """gnu89""" 4 +.el .IP "\f(CWgnu89\fR" 4 +.IX Item "gnu89" +.PD +The 1990 C standard plus \s-1GNU\s0 extensions. This is the default. +.ie n .IP """gnu99""" 4 +.el .IP "\f(CWgnu99\fR" 4 +.IX Item "gnu99" +.PD 0 +.ie n .IP """gnu9x""" 4 +.el .IP "\f(CWgnu9x\fR" 4 +.IX Item "gnu9x" +.PD +The 1999 C standard plus \s-1GNU\s0 extensions. +.ie n .IP """gnu1x""" 4 +.el .IP "\f(CWgnu1x\fR" 4 +.IX Item "gnu1x" +The next version of the \s-1ISO\s0 C standard, still under development, plus +\&\s-1GNU\s0 extensions. +.ie n .IP """c++98""" 4 +.el .IP "\f(CWc++98\fR" 4 +.IX Item "c++98" +The 1998 \s-1ISO\s0 \*(C+ standard plus amendments. +.ie n .IP """gnu++98""" 4 +.el .IP "\f(CWgnu++98\fR" 4 +.IX Item "gnu++98" +The same as \fB\-std=c++98\fR plus \s-1GNU\s0 extensions. This is the +default for \*(C+ code. +.RE +.RS 4 +.RE +.IP "\fB\-I\-\fR" 4 +.IX Item "-I-" +Split the include path. Any directories specified with \fB\-I\fR +options before \fB\-I\-\fR are searched only for headers requested with +\&\f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR; they are not searched for +\&\f(CW\*(C`#include\ <\f(CIfile\f(CW>\*(C'\fR. If additional directories are +specified with \fB\-I\fR options after the \fB\-I\-\fR, those +directories are searched for all \fB#include\fR directives. +.Sp +In addition, \fB\-I\-\fR inhibits the use of the directory of the current +file directory as the first search directory for \f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR. +This option has been deprecated. +.IP "\fB\-nostdinc\fR" 4 +.IX Item "-nostdinc" +Do not search the standard system directories for header files. +Only the directories you have specified with \fB\-I\fR options +(and the directory of the current file, if appropriate) are searched. +.IP "\fB\-nostdinc++\fR" 4 +.IX Item "-nostdinc++" +Do not search for header files in the \*(C+\-specific standard directories, +but do still search the other standard directories. (This option is +used when building the \*(C+ library.) +.IP "\fB\-include\fR \fIfile\fR" 4 +.IX Item "-include file" +Process \fIfile\fR as if \f(CW\*(C`#include "file"\*(C'\fR appeared as the first +line of the primary source file. However, the first directory searched +for \fIfile\fR is the preprocessor's working directory \fIinstead of\fR +the directory containing the main source file. If not found there, it +is searched for in the remainder of the \f(CW\*(C`#include "..."\*(C'\fR search +chain as normal. +.Sp +If multiple \fB\-include\fR options are given, the files are included +in the order they appear on the command line. +.IP "\fB\-imacros\fR \fIfile\fR" 4 +.IX Item "-imacros file" +Exactly like \fB\-include\fR, except that any output produced by +scanning \fIfile\fR is thrown away. Macros it defines remain defined. +This allows you to acquire all the macros from a header without also +processing its declarations. +.Sp +All files specified by \fB\-imacros\fR are processed before all files +specified by \fB\-include\fR. +.IP "\fB\-idirafter\fR \fIdir\fR" 4 +.IX Item "-idirafter dir" +Search \fIdir\fR for header files, but do it \fIafter\fR all +directories specified with \fB\-I\fR and the standard system directories +have been exhausted. \fIdir\fR is treated as a system include directory. +If \fIdir\fR begins with \f(CW\*(C`=\*(C'\fR, then the \f(CW\*(C`=\*(C'\fR will be replaced +by the sysroot prefix; see \fB\-\-sysroot\fR and \fB\-isysroot\fR. +.IP "\fB\-iprefix\fR \fIprefix\fR" 4 +.IX Item "-iprefix prefix" +Specify \fIprefix\fR as the prefix for subsequent \fB\-iwithprefix\fR +options. If the prefix represents a directory, you should include the +final \fB/\fR. +.IP "\fB\-iwithprefix\fR \fIdir\fR" 4 +.IX Item "-iwithprefix dir" +.PD 0 +.IP "\fB\-iwithprefixbefore\fR \fIdir\fR" 4 +.IX Item "-iwithprefixbefore dir" +.PD +Append \fIdir\fR to the prefix specified previously with +\&\fB\-iprefix\fR, and add the resulting directory to the include search +path. \fB\-iwithprefixbefore\fR puts it in the same place \fB\-I\fR +would; \fB\-iwithprefix\fR puts it where \fB\-idirafter\fR would. +.IP "\fB\-isysroot\fR \fIdir\fR" 4 +.IX Item "-isysroot dir" +This option is like the \fB\-\-sysroot\fR option, but applies only to +header files (except for Darwin targets, where it applies to both header +files and libraries). See the \fB\-\-sysroot\fR option for more +information. +.IP "\fB\-imultilib\fR \fIdir\fR" 4 +.IX Item "-imultilib dir" +Use \fIdir\fR as a subdirectory of the directory containing +target-specific \*(C+ headers. +.IP "\fB\-isystem\fR \fIdir\fR" 4 +.IX Item "-isystem dir" +Search \fIdir\fR for header files, after all directories specified by +\&\fB\-I\fR but before the standard system directories. Mark it +as a system directory, so that it gets the same special treatment as +is applied to the standard system directories. +If \fIdir\fR begins with \f(CW\*(C`=\*(C'\fR, then the \f(CW\*(C`=\*(C'\fR will be replaced +by the sysroot prefix; see \fB\-\-sysroot\fR and \fB\-isysroot\fR. +.IP "\fB\-iquote\fR \fIdir\fR" 4 +.IX Item "-iquote dir" +Search \fIdir\fR only for header files requested with +\&\f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR; they are not searched for +\&\f(CW\*(C`#include\ <\f(CIfile\f(CW>\*(C'\fR, before all directories specified by +\&\fB\-I\fR and before the standard system directories. +If \fIdir\fR begins with \f(CW\*(C`=\*(C'\fR, then the \f(CW\*(C`=\*(C'\fR will be replaced +by the sysroot prefix; see \fB\-\-sysroot\fR and \fB\-isysroot\fR. +.IP "\fB\-fdirectives\-only\fR" 4 +.IX Item "-fdirectives-only" +When preprocessing, handle directives, but do not expand macros. +.Sp +The option's behavior depends on the \fB\-E\fR and \fB\-fpreprocessed\fR +options. +.Sp +With \fB\-E\fR, preprocessing is limited to the handling of directives +such as \f(CW\*(C`#define\*(C'\fR, \f(CW\*(C`#ifdef\*(C'\fR, and \f(CW\*(C`#error\*(C'\fR. Other +preprocessor operations, such as macro expansion and trigraph +conversion are not performed. In addition, the \fB\-dD\fR option is +implicitly enabled. +.Sp +With \fB\-fpreprocessed\fR, predefinition of command line and most +builtin macros is disabled. Macros such as \f(CW\*(C`_\|_LINE_\|_\*(C'\fR, which are +contextually dependent, are handled normally. This enables compilation of +files previously preprocessed with \f(CW\*(C`\-E \-fdirectives\-only\*(C'\fR. +.Sp +With both \fB\-E\fR and \fB\-fpreprocessed\fR, the rules for +\&\fB\-fpreprocessed\fR take precedence. This enables full preprocessing of +files previously preprocessed with \f(CW\*(C`\-E \-fdirectives\-only\*(C'\fR. +.IP "\fB\-fdollars\-in\-identifiers\fR" 4 +.IX Item "-fdollars-in-identifiers" +Accept \fB$\fR in identifiers. +.IP "\fB\-fextended\-identifiers\fR" 4 +.IX Item "-fextended-identifiers" +Accept universal character names in identifiers. This option is +experimental; in a future version of \s-1GCC\s0, it will be enabled by +default for C99 and \*(C+. +.IP "\fB\-fpreprocessed\fR" 4 +.IX Item "-fpreprocessed" +Indicate to the preprocessor that the input file has already been +preprocessed. This suppresses things like macro expansion, trigraph +conversion, escaped newline splicing, and processing of most directives. +The preprocessor still recognizes and removes comments, so that you can +pass a file preprocessed with \fB\-C\fR to the compiler without +problems. In this mode the integrated preprocessor is little more than +a tokenizer for the front ends. +.Sp +\&\fB\-fpreprocessed\fR is implicit if the input file has one of the +extensions \fB.i\fR, \fB.ii\fR or \fB.mi\fR. These are the +extensions that \s-1GCC\s0 uses for preprocessed files created by +\&\fB\-save\-temps\fR. +.IP "\fB\-ftabstop=\fR\fIwidth\fR" 4 +.IX Item "-ftabstop=width" +Set the distance between tab stops. This helps the preprocessor report +correct column numbers in warnings or errors, even if tabs appear on the +line. If the value is less than 1 or greater than 100, the option is +ignored. The default is 8. +.IP "\fB\-fexec\-charset=\fR\fIcharset\fR" 4 +.IX Item "-fexec-charset=charset" +Set the execution character set, used for string and character +constants. The default is \s-1UTF\-8\s0. \fIcharset\fR can be any encoding +supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine. +.IP "\fB\-fwide\-exec\-charset=\fR\fIcharset\fR" 4 +.IX Item "-fwide-exec-charset=charset" +Set the wide execution character set, used for wide string and +character constants. The default is \s-1UTF\-32\s0 or \s-1UTF\-16\s0, whichever +corresponds to the width of \f(CW\*(C`wchar_t\*(C'\fR. As with +\&\fB\-fexec\-charset\fR, \fIcharset\fR can be any encoding supported +by the system's \f(CW\*(C`iconv\*(C'\fR library routine; however, you will have +problems with encodings that do not fit exactly in \f(CW\*(C`wchar_t\*(C'\fR. +.IP "\fB\-finput\-charset=\fR\fIcharset\fR" 4 +.IX Item "-finput-charset=charset" +Set the input character set, used for translation from the character +set of the input file to the source character set used by \s-1GCC\s0. If the +locale does not specify, or \s-1GCC\s0 cannot get this information from the +locale, the default is \s-1UTF\-8\s0. This can be overridden by either the locale +or this command line option. Currently the command line option takes +precedence if there's a conflict. \fIcharset\fR can be any encoding +supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine. +.IP "\fB\-fworking\-directory\fR" 4 +.IX Item "-fworking-directory" +Enable generation of linemarkers in the preprocessor output that will +let the compiler know the current working directory at the time of +preprocessing. When this option is enabled, the preprocessor will +emit, after the initial linemarker, a second linemarker with the +current working directory followed by two slashes. \s-1GCC\s0 will use this +directory, when it's present in the preprocessed input, as the +directory emitted as the current working directory in some debugging +information formats. This option is implicitly enabled if debugging +information is enabled, but this can be inhibited with the negated +form \fB\-fno\-working\-directory\fR. If the \fB\-P\fR flag is +present in the command line, this option has no effect, since no +\&\f(CW\*(C`#line\*(C'\fR directives are emitted whatsoever. +.IP "\fB\-fno\-show\-column\fR" 4 +.IX Item "-fno-show-column" +Do not print column numbers in diagnostics. This may be necessary if +diagnostics are being scanned by a program that does not understand the +column numbers, such as \fBdejagnu\fR. +.IP "\fB\-A\fR \fIpredicate\fR\fB=\fR\fIanswer\fR" 4 +.IX Item "-A predicate=answer" +Make an assertion with the predicate \fIpredicate\fR and answer +\&\fIanswer\fR. This form is preferred to the older form \fB\-A\fR +\&\fIpredicate\fR\fB(\fR\fIanswer\fR\fB)\fR, which is still supported, because +it does not use shell special characters. +.IP "\fB\-A \-\fR\fIpredicate\fR\fB=\fR\fIanswer\fR" 4 +.IX Item "-A -predicate=answer" +Cancel an assertion with the predicate \fIpredicate\fR and answer +\&\fIanswer\fR. +.IP "\fB\-dCHARS\fR" 4 +.IX Item "-dCHARS" +\&\fI\s-1CHARS\s0\fR is a sequence of one or more of the following characters, +and must not be preceded by a space. Other characters are interpreted +by the compiler proper, or reserved for future versions of \s-1GCC\s0, and so +are silently ignored. If you specify characters whose behavior +conflicts, the result is undefined. +.RS 4 +.IP "\fBM\fR" 4 +.IX Item "M" +Instead of the normal output, generate a list of \fB#define\fR +directives for all the macros defined during the execution of the +preprocessor, including predefined macros. This gives you a way of +finding out what is predefined in your version of the preprocessor. +Assuming you have no file \fIfoo.h\fR, the command +.Sp +.Vb 1 +\& touch foo.h; cpp \-dM foo.h +.Ve +.Sp +will show all the predefined macros. +.Sp +If you use \fB\-dM\fR without the \fB\-E\fR option, \fB\-dM\fR is +interpreted as a synonym for \fB\-fdump\-rtl\-mach\fR. +.IP "\fBD\fR" 4 +.IX Item "D" +Like \fBM\fR except in two respects: it does \fInot\fR include the +predefined macros, and it outputs \fIboth\fR the \fB#define\fR +directives and the result of preprocessing. Both kinds of output go to +the standard output file. +.IP "\fBN\fR" 4 +.IX Item "N" +Like \fBD\fR, but emit only the macro names, not their expansions. +.IP "\fBI\fR" 4 +.IX Item "I" +Output \fB#include\fR directives in addition to the result of +preprocessing. +.IP "\fBU\fR" 4 +.IX Item "U" +Like \fBD\fR except that only macros that are expanded, or whose +definedness is tested in preprocessor directives, are output; the +output is delayed until the use or test of the macro; and +\&\fB#undef\fR directives are also output for macros tested but +undefined at the time. +.RE +.RS 4 +.RE +.IP "\fB\-P\fR" 4 +.IX Item "-P" +Inhibit generation of linemarkers in the output from the preprocessor. +This might be useful when running the preprocessor on something that is +not C code, and will be sent to a program which might be confused by the +linemarkers. +.IP "\fB\-C\fR" 4 +.IX Item "-C" +Do not discard comments. All comments are passed through to the output +file, except for comments in processed directives, which are deleted +along with the directive. +.Sp +You should be prepared for side effects when using \fB\-C\fR; it +causes the preprocessor to treat comments as tokens in their own right. +For example, comments appearing at the start of what would be a +directive line have the effect of turning that line into an ordinary +source line, since the first token on the line is no longer a \fB#\fR. +.IP "\fB\-CC\fR" 4 +.IX Item "-CC" +Do not discard comments, including during macro expansion. This is +like \fB\-C\fR, except that comments contained within macros are +also passed through to the output file where the macro is expanded. +.Sp +In addition to the side-effects of the \fB\-C\fR option, the +\&\fB\-CC\fR option causes all \*(C+\-style comments inside a macro +to be converted to C\-style comments. This is to prevent later use +of that macro from inadvertently commenting out the remainder of +the source line. +.Sp +The \fB\-CC\fR option is generally used to support lint comments. +.IP "\fB\-traditional\-cpp\fR" 4 +.IX Item "-traditional-cpp" +Try to imitate the behavior of old-fashioned C preprocessors, as +opposed to \s-1ISO\s0 C preprocessors. +.IP "\fB\-trigraphs\fR" 4 +.IX Item "-trigraphs" +Process trigraph sequences. +These are three-character sequences, all starting with \fB??\fR, that +are defined by \s-1ISO\s0 C to stand for single characters. For example, +\&\fB??/\fR stands for \fB\e\fR, so \fB'??/n'\fR is a character +constant for a newline. By default, \s-1GCC\s0 ignores trigraphs, but in +standard-conforming modes it converts them. See the \fB\-std\fR and +\&\fB\-ansi\fR options. +.Sp +The nine trigraphs and their replacements are +.Sp +.Vb 2 +\& Trigraph: ??( ??) ??< ??> ??= ??/ ??\*(Aq ??! ??\- +\& Replacement: [ ] { } # \e ^ | ~ +.Ve +.IP "\fB\-remap\fR" 4 +.IX Item "-remap" +Enable special code to work around file systems which only permit very +short file names, such as MS-DOS. +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +.PD 0 +.IP "\fB\-\-target\-help\fR" 4 +.IX Item "--target-help" +.PD +Print text describing all the command line options instead of +preprocessing anything. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +Verbose mode. Print out \s-1GNU\s0 \s-1CPP\s0's version number at the beginning of +execution, and report the final form of the include path. +.IP "\fB\-H\fR" 4 +.IX Item "-H" +Print the name of each header file used, in addition to other normal +activities. Each name is indented to show how deep in the +\&\fB#include\fR stack it is. Precompiled header files are also +printed, even if they are found to be invalid; an invalid precompiled +header file is printed with \fB...x\fR and a valid one with \fB...!\fR . +.IP "\fB\-version\fR" 4 +.IX Item "-version" +.PD 0 +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +.PD +Print out \s-1GNU\s0 \s-1CPP\s0's version number. With one dash, proceed to +preprocess as normal. With two dashes, exit immediately. +.SS "Passing Options to the Assembler" +.IX Subsection "Passing Options to the Assembler" +You can pass options to the assembler. +.IP "\fB\-Wa,\fR\fIoption\fR" 4 +.IX Item "-Wa,option" +Pass \fIoption\fR as an option to the assembler. If \fIoption\fR +contains commas, it is split into multiple options at the commas. +.IP "\fB\-Xassembler\fR \fIoption\fR" 4 +.IX Item "-Xassembler option" +Pass \fIoption\fR as an option to the assembler. You can use this to +supply system-specific assembler options which \s-1GCC\s0 does not know how to +recognize. +.Sp +If you want to pass an option that takes an argument, you must use +\&\fB\-Xassembler\fR twice, once for the option and once for the argument. +.IP "\fBprofile-generate-sampling-rate\fR" 4 +.IX Item "profile-generate-sampling-rate" +Set the sampling rate with \fB\-fprofile\-generate\-sampling\fR. +.SS "Options for Linking" +.IX Subsection "Options for Linking" +These options come into play when the compiler links object files into +an executable output file. They are meaningless if the compiler is +not doing a link step. +.IP "\fIobject-file-name\fR" 4 +.IX Item "object-file-name" +A file name that does not end in a special recognized suffix is +considered to name an object file or library. (Object files are +distinguished from libraries by the linker according to the file +contents.) If linking is done, these object files are used as input +to the linker. +.IP "\fB\-c\fR" 4 +.IX Item "-c" +.PD 0 +.IP "\fB\-S\fR" 4 +.IX Item "-S" +.IP "\fB\-E\fR" 4 +.IX Item "-E" +.PD +If any of these options is used, then the linker is not run, and +object file names should not be used as arguments. +.IP "\fB\-l\fR\fIlibrary\fR" 4 +.IX Item "-llibrary" +.PD 0 +.IP "\fB\-l\fR \fIlibrary\fR" 4 +.IX Item "-l library" +.PD +Search the library named \fIlibrary\fR when linking. (The second +alternative with the library as a separate argument is only for +\&\s-1POSIX\s0 compliance and is not recommended.) +.Sp +It makes a difference where in the command you write this option; the +linker searches and processes libraries and object files in the order they +are specified. Thus, \fBfoo.o \-lz bar.o\fR searches library \fBz\fR +after file \fIfoo.o\fR but before \fIbar.o\fR. If \fIbar.o\fR refers +to functions in \fBz\fR, those functions may not be loaded. +.Sp +The linker searches a standard list of directories for the library, +which is actually a file named \fIlib\fIlibrary\fI.a\fR. The linker +then uses this file as if it had been specified precisely by name. +.Sp +The directories searched include several standard system directories +plus any that you specify with \fB\-L\fR. +.Sp +Normally the files found this way are library files\-\-\-archive files +whose members are object files. The linker handles an archive file by +scanning through it for members which define symbols that have so far +been referenced but not defined. But if the file that is found is an +ordinary object file, it is linked in the usual fashion. The only +difference between using an \fB\-l\fR option and specifying a file name +is that \fB\-l\fR surrounds \fIlibrary\fR with \fBlib\fR and \fB.a\fR +and searches several directories. +.IP "\fB\-lobjc\fR" 4 +.IX Item "-lobjc" +You need this special case of the \fB\-l\fR option in order to +link an Objective-C or Objective\-\*(C+ program. +.IP "\fB\-nostartfiles\fR" 4 +.IX Item "-nostartfiles" +Do not use the standard system startup files when linking. +The standard system libraries are used normally, unless \fB\-nostdlib\fR +or \fB\-nodefaultlibs\fR is used. +.IP "\fB\-nodefaultlibs\fR" 4 +.IX Item "-nodefaultlibs" +Do not use the standard system libraries when linking. +Only the libraries you specify will be passed to the linker, options +specifying linkage of the system libraries, such as \f(CW\*(C`\-static\-libgcc\*(C'\fR +or \f(CW\*(C`\-shared\-libgcc\*(C'\fR, will be ignored. +The standard startup files are used normally, unless \fB\-nostartfiles\fR +is used. The compiler may generate calls to \f(CW\*(C`memcmp\*(C'\fR, +\&\f(CW\*(C`memset\*(C'\fR, \f(CW\*(C`memcpy\*(C'\fR and \f(CW\*(C`memmove\*(C'\fR. +These entries are usually resolved by entries in +libc. These entry points should be supplied through some other +mechanism when this option is specified. +.IP "\fB\-nostdlib\fR" 4 +.IX Item "-nostdlib" +Do not use the standard system startup files or libraries when linking. +No startup files and only the libraries you specify will be passed to +the linker, options specifying linkage of the system libraries, such as +\&\f(CW\*(C`\-static\-libgcc\*(C'\fR or \f(CW\*(C`\-shared\-libgcc\*(C'\fR, will be ignored. +The compiler may generate calls to \f(CW\*(C`memcmp\*(C'\fR, \f(CW\*(C`memset\*(C'\fR, +\&\f(CW\*(C`memcpy\*(C'\fR and \f(CW\*(C`memmove\*(C'\fR. +These entries are usually resolved by entries in +libc. These entry points should be supplied through some other +mechanism when this option is specified. +.Sp +One of the standard libraries bypassed by \fB\-nostdlib\fR and +\&\fB\-nodefaultlibs\fR is \fIlibgcc.a\fR, a library of internal subroutines +that \s-1GCC\s0 uses to overcome shortcomings of particular machines, or special +needs for some languages. +.Sp +In most cases, you need \fIlibgcc.a\fR even when you want to avoid +other standard libraries. In other words, when you specify \fB\-nostdlib\fR +or \fB\-nodefaultlibs\fR you should usually specify \fB\-lgcc\fR as well. +This ensures that you have no unresolved references to internal \s-1GCC\s0 +library subroutines. (For example, \fB_\|_main\fR, used to ensure \*(C+ +constructors will be called.) +.IP "\fB\-pie\fR" 4 +.IX Item "-pie" +Produce a position independent executable on targets which support it. +For predictable results, you must also specify the same set of options +that were used to generate code (\fB\-fpie\fR, \fB\-fPIE\fR, +or model suboptions) when you specify this option. +.IP "\fB\-rdynamic\fR" 4 +.IX Item "-rdynamic" +Pass the flag \fB\-export\-dynamic\fR to the \s-1ELF\s0 linker, on targets +that support it. This instructs the linker to add all symbols, not +only used ones, to the dynamic symbol table. This option is needed +for some uses of \f(CW\*(C`dlopen\*(C'\fR or to allow obtaining backtraces +from within a program. +.IP "\fB\-s\fR" 4 +.IX Item "-s" +Remove all symbol table and relocation information from the executable. +.IP "\fB\-static\fR" 4 +.IX Item "-static" +On systems that support dynamic linking, this prevents linking with the shared +libraries. On other systems, this option has no effect. +.IP "\fB\-shared\fR" 4 +.IX Item "-shared" +Produce a shared object which can then be linked with other objects to +form an executable. Not all systems support this option. For predictable +results, you must also specify the same set of options that were used to +generate code (\fB\-fpic\fR, \fB\-fPIC\fR, or model suboptions) +when you specify this option.[1] +.IP "\fB\-shared\-libgcc\fR" 4 +.IX Item "-shared-libgcc" +.PD 0 +.IP "\fB\-static\-libgcc\fR" 4 +.IX Item "-static-libgcc" +.PD +On systems that provide \fIlibgcc\fR as a shared library, these options +force the use of either the shared or static version respectively. +If no shared version of \fIlibgcc\fR was built when the compiler was +configured, these options have no effect. +.Sp +There are several situations in which an application should use the +shared \fIlibgcc\fR instead of the static version. The most common +of these is when the application wishes to throw and catch exceptions +across different shared libraries. In that case, each of the libraries +as well as the application itself should use the shared \fIlibgcc\fR. +.Sp +Therefore, the G++ and \s-1GCJ\s0 drivers automatically add +\&\fB\-shared\-libgcc\fR whenever you build a shared library or a main +executable, because \*(C+ and Java programs typically use exceptions, so +this is the right thing to do. +.Sp +If, instead, you use the \s-1GCC\s0 driver to create shared libraries, you may +find that they will not always be linked with the shared \fIlibgcc\fR. +If \s-1GCC\s0 finds, at its configuration time, that you have a non-GNU linker +or a \s-1GNU\s0 linker that does not support option \fB\-\-eh\-frame\-hdr\fR, +it will link the shared version of \fIlibgcc\fR into shared libraries +by default. Otherwise, it will take advantage of the linker and optimize +away the linking with the shared version of \fIlibgcc\fR, linking with +the static version of libgcc by default. This allows exceptions to +propagate through such shared libraries, without incurring relocation +costs at library load time. +.Sp +However, if a library or main executable is supposed to throw or catch +exceptions, you must link it using the G++ or \s-1GCJ\s0 driver, as appropriate +for the languages used in the program, or using the option +\&\fB\-shared\-libgcc\fR, such that it is linked with the shared +\&\fIlibgcc\fR. +.IP "\fB\-static\-libstdc++\fR" 4 +.IX Item "-static-libstdc++" +When the \fBg++\fR program is used to link a \*(C+ program, it will +normally automatically link against \fBlibstdc++\fR. If +\&\fIlibstdc++\fR is available as a shared library, and the +\&\fB\-static\fR option is not used, then this will link against the +shared version of \fIlibstdc++\fR. That is normally fine. However, it +is sometimes useful to freeze the version of \fIlibstdc++\fR used by +the program without going all the way to a fully static link. The +\&\fB\-static\-libstdc++\fR option directs the \fBg++\fR driver to +link \fIlibstdc++\fR statically, without necessarily linking other +libraries statically. +.IP "\fB\-symbolic\fR" 4 +.IX Item "-symbolic" +Bind references to global symbols when building a shared object. Warn +about any unresolved references (unless overridden by the link editor +option \fB\-Xlinker \-z \-Xlinker defs\fR). Only a few systems support +this option. +.IP "\fB\-T\fR \fIscript\fR" 4 +.IX Item "-T script" +Use \fIscript\fR as the linker script. This option is supported by most +systems using the \s-1GNU\s0 linker. On some targets, such as bare-board +targets without an operating system, the \fB\-T\fR option may be required +when linking to avoid references to undefined symbols. +.IP "\fB\-Xlinker\fR \fIoption\fR" 4 +.IX Item "-Xlinker option" +Pass \fIoption\fR as an option to the linker. You can use this to +supply system-specific linker options which \s-1GCC\s0 does not know how to +recognize. +.Sp +If you want to pass an option that takes a separate argument, you must use +\&\fB\-Xlinker\fR twice, once for the option and once for the argument. +For example, to pass \fB\-assert definitions\fR, you must write +\&\fB\-Xlinker \-assert \-Xlinker definitions\fR. It does not work to write +\&\fB\-Xlinker \*(L"\-assert definitions\*(R"\fR, because this passes the entire +string as a single argument, which is not what the linker expects. +.Sp +When using the \s-1GNU\s0 linker, it is usually more convenient to pass +arguments to linker options using the \fIoption\fR\fB=\fR\fIvalue\fR +syntax than as separate arguments. For example, you can specify +\&\fB\-Xlinker \-Map=output.map\fR rather than +\&\fB\-Xlinker \-Map \-Xlinker output.map\fR. Other linkers may not support +this syntax for command-line options. +.IP "\fB\-Wl,\fR\fIoption\fR" 4 +.IX Item "-Wl,option" +Pass \fIoption\fR as an option to the linker. If \fIoption\fR contains +commas, it is split into multiple options at the commas. You can use this +syntax to pass an argument to the option. +For example, \fB\-Wl,\-Map,output.map\fR passes \fB\-Map output.map\fR to the +linker. When using the \s-1GNU\s0 linker, you can also get the same effect with +\&\fB\-Wl,\-Map=output.map\fR. +.IP "\fB\-u\fR \fIsymbol\fR" 4 +.IX Item "-u symbol" +Pretend the symbol \fIsymbol\fR is undefined, to force linking of +library modules to define it. You can use \fB\-u\fR multiple times with +different symbols to force loading of additional library modules. +.SS "Options for Directory Search" +.IX Subsection "Options for Directory Search" +These options specify directories to search for header files, for +libraries and for parts of the compiler: +.IP "\fB\-I\fR\fIdir\fR" 4 +.IX Item "-Idir" +Add the directory \fIdir\fR to the head of the list of directories to be +searched for header files. This can be used to override a system header +file, substituting your own version, since these directories are +searched before the system header file directories. However, you should +not use this option to add directories that contain vendor-supplied +system header files (use \fB\-isystem\fR for that). If you use more than +one \fB\-I\fR option, the directories are scanned in left-to-right +order; the standard system directories come after. +.Sp +If a standard system include directory, or a directory specified with +\&\fB\-isystem\fR, is also specified with \fB\-I\fR, the \fB\-I\fR +option will be ignored. The directory will still be searched but as a +system directory at its normal position in the system include chain. +This is to ensure that \s-1GCC\s0's procedure to fix buggy system headers and +the ordering for the include_next directive are not inadvertently changed. +If you really need to change the search order for system directories, +use the \fB\-nostdinc\fR and/or \fB\-isystem\fR options. +.IP "\fB\-iplugindir=\fR\fIdir\fR" 4 +.IX Item "-iplugindir=dir" +Set the directory to search for plugins which are passed +by \fB\-fplugin=\fR\fIname\fR instead of +\&\fB\-fplugin=\fR\fIpath\fR\fB/\fR\fIname\fR\fB.so\fR. This option is not meant +to be used by the user, but only passed by the driver. +.IP "\fB\-iquote\fR\fIdir\fR" 4 +.IX Item "-iquotedir" +Add the directory \fIdir\fR to the head of the list of directories to +be searched for header files only for the case of \fB#include +"\fR\fIfile\fR\fB"\fR; they are not searched for \fB#include <\fR\fIfile\fR\fB>\fR, +otherwise just like \fB\-I\fR. +.IP "\fB\-L\fR\fIdir\fR" 4 +.IX Item "-Ldir" +Add directory \fIdir\fR to the list of directories to be searched +for \fB\-l\fR. +.IP "\fB\-B\fR\fIprefix\fR" 4 +.IX Item "-Bprefix" +This option specifies where to find the executables, libraries, +include files, and data files of the compiler itself. +.Sp +The compiler driver program runs one or more of the subprograms +\&\fIcpp\fR, \fIcc1\fR, \fIas\fR and \fIld\fR. It tries +\&\fIprefix\fR as a prefix for each program it tries to run, both with and +without \fImachine\fR\fB/\fR\fIversion\fR\fB/\fR. +.Sp +For each subprogram to be run, the compiler driver first tries the +\&\fB\-B\fR prefix, if any. If that name is not found, or if \fB\-B\fR +was not specified, the driver tries two standard prefixes, which are +\&\fI/usr/lib/gcc/\fR and \fI/usr/local/lib/gcc/\fR. If neither of +those results in a file name that is found, the unmodified program +name is searched for using the directories specified in your +\&\fB\s-1PATH\s0\fR environment variable. +.Sp +The compiler will check to see if the path provided by the \fB\-B\fR +refers to a directory, and if necessary it will add a directory +separator character at the end of the path. +.Sp +\&\fB\-B\fR prefixes that effectively specify directory names also apply +to libraries in the linker, because the compiler translates these +options into \fB\-L\fR options for the linker. They also apply to +includes files in the preprocessor, because the compiler translates these +options into \fB\-isystem\fR options for the preprocessor. In this case, +the compiler appends \fBinclude\fR to the prefix. +.Sp +The run-time support file \fIlibgcc.a\fR can also be searched for using +the \fB\-B\fR prefix, if needed. If it is not found there, the two +standard prefixes above are tried, and that is all. The file is left +out of the link if it is not found by those means. +.Sp +Another way to specify a prefix much like the \fB\-B\fR prefix is to use +the environment variable \fB\s-1GCC_EXEC_PREFIX\s0\fR. +.Sp +As a special kludge, if the path provided by \fB\-B\fR is +\&\fI[dir/]stage\fIN\fI/\fR, where \fIN\fR is a number in the range 0 to +9, then it will be replaced by \fI[dir/]include\fR. This is to help +with boot-strapping the compiler. +.IP "\fB\-specs=\fR\fIfile\fR" 4 +.IX Item "-specs=file" +Process \fIfile\fR after the compiler reads in the standard \fIspecs\fR +file, in order to override the defaults that the \fIgcc\fR driver +program uses when determining what switches to pass to \fIcc1\fR, +\&\fIcc1plus\fR, \fIas\fR, \fIld\fR, etc. More than one +\&\fB\-specs=\fR\fIfile\fR can be specified on the command line, and they +are processed in order, from left to right. +.IP "\fB\-\-sysroot=\fR\fIdir\fR" 4 +.IX Item "--sysroot=dir" +Use \fIdir\fR as the logical root directory for headers and libraries. +For example, if the compiler would normally search for headers in +\&\fI/usr/include\fR and libraries in \fI/usr/lib\fR, it will instead +search \fI\fIdir\fI/usr/include\fR and \fI\fIdir\fI/usr/lib\fR. +.Sp +If you use both this option and the \fB\-isysroot\fR option, then +the \fB\-\-sysroot\fR option will apply to libraries, but the +\&\fB\-isysroot\fR option will apply to header files. +.Sp +The \s-1GNU\s0 linker (beginning with version 2.16) has the necessary support +for this option. If your linker does not support this option, the +header file aspect of \fB\-\-sysroot\fR will still work, but the +library aspect will not. +.IP "\fB\-I\-\fR" 4 +.IX Item "-I-" +This option has been deprecated. Please use \fB\-iquote\fR instead for +\&\fB\-I\fR directories before the \fB\-I\-\fR and remove the \fB\-I\-\fR. +Any directories you specify with \fB\-I\fR options before the \fB\-I\-\fR +option are searched only for the case of \fB#include "\fR\fIfile\fR\fB"\fR; +they are not searched for \fB#include <\fR\fIfile\fR\fB>\fR. +.Sp +If additional directories are specified with \fB\-I\fR options after +the \fB\-I\-\fR, these directories are searched for all \fB#include\fR +directives. (Ordinarily \fIall\fR \fB\-I\fR directories are used +this way.) +.Sp +In addition, the \fB\-I\-\fR option inhibits the use of the current +directory (where the current input file came from) as the first search +directory for \fB#include "\fR\fIfile\fR\fB"\fR. There is no way to +override this effect of \fB\-I\-\fR. With \fB\-I.\fR you can specify +searching the directory which was current when the compiler was +invoked. That is not exactly the same as what the preprocessor does +by default, but it is often satisfactory. +.Sp +\&\fB\-I\-\fR does not inhibit the use of the standard system directories +for header files. Thus, \fB\-I\-\fR and \fB\-nostdinc\fR are +independent. +.SS "Specifying Target Machine and Compiler Version" +.IX Subsection "Specifying Target Machine and Compiler Version" +The usual way to run \s-1GCC\s0 is to run the executable called \fBgcc\fR, or +\&\fImachine\fR\fB\-gcc\fR when cross-compiling, or +\&\fImachine\fR\fB\-gcc\-\fR\fIversion\fR to run a version other than the +one that was installed last. +.SS "Hardware Models and Configurations" +.IX Subsection "Hardware Models and Configurations" +Each target machine types can have its own +special options, starting with \fB\-m\fR, to choose among various +hardware models or configurations\-\-\-for example, 68010 vs 68020, +floating coprocessor or none. A single installed version of the +compiler can compile for any model or configuration, according to the +options specified. +.PP +Some configurations of the compiler also support additional special +options, usually for compatibility with other compilers on the same +platform. +.PP +\fI\s-1ARC\s0 Options\fR +.IX Subsection "ARC Options" +.PP +These options are defined for \s-1ARC\s0 implementations: +.IP "\fB\-EL\fR" 4 +.IX Item "-EL" +Compile code for little endian mode. This is the default. +.IP "\fB\-EB\fR" 4 +.IX Item "-EB" +Compile code for big endian mode. +.IP "\fB\-mmangle\-cpu\fR" 4 +.IX Item "-mmangle-cpu" +Prepend the name of the \s-1CPU\s0 to all public symbol names. +In multiple-processor systems, there are many \s-1ARC\s0 variants with different +instruction and register set characteristics. This flag prevents code +compiled for one \s-1CPU\s0 to be linked with code compiled for another. +No facility exists for handling variants that are \*(L"almost identical\*(R". +This is an all or nothing option. +.IP "\fB\-mcpu=\fR\fIcpu\fR" 4 +.IX Item "-mcpu=cpu" +Compile code for \s-1ARC\s0 variant \fIcpu\fR. +Which variants are supported depend on the configuration. +All variants support \fB\-mcpu=base\fR, this is the default. +.IP "\fB\-mtext=\fR\fItext-section\fR" 4 +.IX Item "-mtext=text-section" +.PD 0 +.IP "\fB\-mdata=\fR\fIdata-section\fR" 4 +.IX Item "-mdata=data-section" +.IP "\fB\-mrodata=\fR\fIreadonly-data-section\fR" 4 +.IX Item "-mrodata=readonly-data-section" +.PD +Put functions, data, and readonly data in \fItext-section\fR, +\&\fIdata-section\fR, and \fIreadonly-data-section\fR respectively +by default. This can be overridden with the \f(CW\*(C`section\*(C'\fR attribute. +.PP +\fI\s-1ARM\s0 Options\fR +.IX Subsection "ARM Options" +.PP +These \fB\-m\fR options are defined for Advanced \s-1RISC\s0 Machines (\s-1ARM\s0) +architectures: +.IP "\fB\-mabi=\fR\fIname\fR" 4 +.IX Item "-mabi=name" +Generate code for the specified \s-1ABI\s0. Permissible values are: \fBapcs-gnu\fR, +\&\fBatpcs\fR, \fBaapcs\fR, \fBaapcs-linux\fR and \fBiwmmxt\fR. +.IP "\fB\-mapcs\-frame\fR" 4 +.IX Item "-mapcs-frame" +Generate a stack frame that is compliant with the \s-1ARM\s0 Procedure Call +Standard for all functions, even if this is not strictly necessary for +correct execution of the code. Specifying \fB\-fomit\-frame\-pointer\fR +with this option will cause the stack frames not to be generated for +leaf functions. The default is \fB\-mno\-apcs\-frame\fR. +.IP "\fB\-mapcs\fR" 4 +.IX Item "-mapcs" +This is a synonym for \fB\-mapcs\-frame\fR. +.IP "\fB\-mthumb\-interwork\fR" 4 +.IX Item "-mthumb-interwork" +Generate code which supports calling between the \s-1ARM\s0 and Thumb +instruction sets. Without this option the two instruction sets cannot +be reliably used inside one program. The default is +\&\fB\-mno\-thumb\-interwork\fR, since slightly larger code is generated +when \fB\-mthumb\-interwork\fR is specified. +.IP "\fB\-mno\-sched\-prolog\fR" 4 +.IX Item "-mno-sched-prolog" +Prevent the reordering of instructions in the function prolog, or the +merging of those instruction with the instructions in the function's +body. This means that all functions will start with a recognizable set +of instructions (or in fact one of a choice from a small set of +different function prologues), and this information can be used to +locate the start if functions inside an executable piece of code. The +default is \fB\-msched\-prolog\fR. +.IP "\fB\-mfloat\-abi=\fR\fIname\fR" 4 +.IX Item "-mfloat-abi=name" +Specifies which floating-point \s-1ABI\s0 to use. Permissible values +are: \fBsoft\fR, \fBsoftfp\fR and \fBhard\fR. +.Sp +Specifying \fBsoft\fR causes \s-1GCC\s0 to generate output containing +library calls for floating-point operations. +\&\fBsoftfp\fR allows the generation of code using hardware floating-point +instructions, but still uses the soft-float calling conventions. +\&\fBhard\fR allows generation of floating-point instructions +and uses FPU-specific calling conventions. +.Sp +The default depends on the specific target configuration. Note that +the hard-float and soft-float ABIs are not link-compatible; you must +compile your entire program with the same \s-1ABI\s0, and link with a +compatible set of libraries. +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +Equivalent to \fB\-mfloat\-abi=hard\fR. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Equivalent to \fB\-mfloat\-abi=soft\fR. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +Generate code for a processor running in little-endian mode. This is +the default for all standard configurations. +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +Generate code for a processor running in big-endian mode; the default is +to compile code for a little-endian processor. +.IP "\fB\-mwords\-little\-endian\fR" 4 +.IX Item "-mwords-little-endian" +This option only applies when generating code for big-endian processors. +Generate code for a little-endian word order but a big-endian byte +order. That is, a byte order of the form \fB32107654\fR. Note: this +option should only be used if you require compatibility with code for +big-endian \s-1ARM\s0 processors generated by versions of the compiler prior to +2.8. +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +This specifies the name of the target \s-1ARM\s0 processor. \s-1GCC\s0 uses this name +to determine what kind of instructions it can emit when generating +assembly code. Permissible names are: \fBarm2\fR, \fBarm250\fR, +\&\fBarm3\fR, \fBarm6\fR, \fBarm60\fR, \fBarm600\fR, \fBarm610\fR, +\&\fBarm620\fR, \fBarm7\fR, \fBarm7m\fR, \fBarm7d\fR, \fBarm7dm\fR, +\&\fBarm7di\fR, \fBarm7dmi\fR, \fBarm70\fR, \fBarm700\fR, +\&\fBarm700i\fR, \fBarm710\fR, \fBarm710c\fR, \fBarm7100\fR, +\&\fBarm720\fR, +\&\fBarm7500\fR, \fBarm7500fe\fR, \fBarm7tdmi\fR, \fBarm7tdmi\-s\fR, +\&\fBarm710t\fR, \fBarm720t\fR, \fBarm740t\fR, +\&\fBstrongarm\fR, \fBstrongarm110\fR, \fBstrongarm1100\fR, +\&\fBstrongarm1110\fR, +\&\fBarm8\fR, \fBarm810\fR, \fBarm9\fR, \fBarm9e\fR, \fBarm920\fR, +\&\fBarm920t\fR, \fBarm922t\fR, \fBarm946e\-s\fR, \fBarm966e\-s\fR, +\&\fBarm968e\-s\fR, \fBarm926ej\-s\fR, \fBarm940t\fR, \fBarm9tdmi\fR, +\&\fBarm10tdmi\fR, \fBarm1020t\fR, \fBarm1026ej\-s\fR, +\&\fBarm10e\fR, \fBarm1020e\fR, \fBarm1022e\fR, +\&\fBarm1136j\-s\fR, \fBarm1136jf\-s\fR, \fBmpcore\fR, \fBmpcorenovfp\fR, +\&\fBarm1156t2\-s\fR, \fBarm1156t2f\-s\fR, \fBarm1176jz\-s\fR, \fBarm1176jzf\-s\fR, +\&\fBcortex\-a5\fR, \fBcortex\-a8\fR, \fBcortex\-a9\fR, \fBcortex\-a15\fR, +\&\fBcortex\-r4\fR, \fBcortex\-r4f\fR, \fBcortex\-m4\fR, \fBcortex\-m3\fR, +\&\fBcortex\-m1\fR, +\&\fBcortex\-m0\fR, +\&\fBxscale\fR, \fBiwmmxt\fR, \fBiwmmxt2\fR, \fBep9312\fR. +.IP "\fB\-mtune=\fR\fIname\fR" 4 +.IX Item "-mtune=name" +This option is very similar to the \fB\-mcpu=\fR option, except that +instead of specifying the actual target processor type, and hence +restricting which instructions can be used, it specifies that \s-1GCC\s0 should +tune the performance of the code as if the target were of the type +specified in this option, but still choosing the instructions that it +will generate based on the \s-1CPU\s0 specified by a \fB\-mcpu=\fR option. +For some \s-1ARM\s0 implementations better performance can be obtained by using +this option. +.IP "\fB\-march=\fR\fIname\fR" 4 +.IX Item "-march=name" +This specifies the name of the target \s-1ARM\s0 architecture. \s-1GCC\s0 uses this +name to determine what kind of instructions it can emit when generating +assembly code. This option can be used in conjunction with or instead +of the \fB\-mcpu=\fR option. Permissible names are: \fBarmv2\fR, +\&\fBarmv2a\fR, \fBarmv3\fR, \fBarmv3m\fR, \fBarmv4\fR, \fBarmv4t\fR, +\&\fBarmv5\fR, \fBarmv5t\fR, \fBarmv5e\fR, \fBarmv5te\fR, +\&\fBarmv6\fR, \fBarmv6j\fR, +\&\fBarmv6t2\fR, \fBarmv6z\fR, \fBarmv6zk\fR, \fBarmv6\-m\fR, +\&\fBarmv7\fR, \fBarmv7\-a\fR, \fBarmv7\-r\fR, \fBarmv7\-m\fR, +\&\fBiwmmxt\fR, \fBiwmmxt2\fR, \fBep9312\fR. +.IP "\fB\-mfpu=\fR\fIname\fR" 4 +.IX Item "-mfpu=name" +.PD 0 +.IP "\fB\-mfpe=\fR\fInumber\fR" 4 +.IX Item "-mfpe=number" +.IP "\fB\-mfp=\fR\fInumber\fR" 4 +.IX Item "-mfp=number" +.PD +This specifies what floating point hardware (or hardware emulation) is +available on the target. Permissible names are: \fBfpa\fR, \fBfpe2\fR, +\&\fBfpe3\fR, \fBmaverick\fR, \fBvfp\fR, \fBvfpv3\fR, \fBvfpv3\-fp16\fR, +\&\fBvfpv3\-d16\fR, \fBvfpv3\-d16\-fp16\fR, \fBvfpv3xd\fR, \fBvfpv3xd\-fp16\fR, +\&\fBneon\fR, \fBneon\-fp16\fR, \fBvfpv4\fR, \fBvfpv4\-d16\fR, +\&\fBfpv4\-sp\-d16\fR and \fBneon\-vfpv4\fR. +\&\fB\-mfp\fR and \fB\-mfpe\fR are synonyms for +\&\fB\-mfpu\fR=\fBfpe\fR\fInumber\fR, for compatibility with older versions +of \s-1GCC\s0. +.Sp +If \fB\-msoft\-float\fR is specified this specifies the format of +floating point values. +.Sp +If the selected floating-point hardware includes the \s-1NEON\s0 extension +(e.g. \fB\-mfpu\fR=\fBneon\fR), note that floating-point +operations will not be used by \s-1GCC\s0's auto-vectorization pass unless +\&\fB\-funsafe\-math\-optimizations\fR is also specified. This is +because \s-1NEON\s0 hardware does not fully implement the \s-1IEEE\s0 754 standard for +floating-point arithmetic (in particular denormal values are treated as +zero), so the use of \s-1NEON\s0 instructions may lead to a loss of precision. +.IP "\fB\-mfp16\-format=\fR\fIname\fR" 4 +.IX Item "-mfp16-format=name" +Specify the format of the \f(CW\*(C`_\|_fp16\*(C'\fR half-precision floating-point type. +Permissible names are \fBnone\fR, \fBieee\fR, and \fBalternative\fR; +the default is \fBnone\fR, in which case the \f(CW\*(C`_\|_fp16\*(C'\fR type is not +defined. +.IP "\fB\-mstructure\-size\-boundary=\fR\fIn\fR" 4 +.IX Item "-mstructure-size-boundary=n" +The size of all structures and unions will be rounded up to a multiple +of the number of bits set by this option. Permissible values are 8, 32 +and 64. The default value varies for different toolchains. For the \s-1COFF\s0 +targeted toolchain the default value is 8. A value of 64 is only allowed +if the underlying \s-1ABI\s0 supports it. +.Sp +Specifying the larger number can produce faster, more efficient code, but +can also increase the size of the program. Different values are potentially +incompatible. Code compiled with one value cannot necessarily expect to +work with code or libraries compiled with another value, if they exchange +information using structures or unions. +.IP "\fB\-mabort\-on\-noreturn\fR" 4 +.IX Item "-mabort-on-noreturn" +Generate a call to the function \f(CW\*(C`abort\*(C'\fR at the end of a +\&\f(CW\*(C`noreturn\*(C'\fR function. It will be executed if the function tries to +return. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +.PD 0 +.IP "\fB\-mno\-long\-calls\fR" 4 +.IX Item "-mno-long-calls" +.PD +Tells the compiler to perform function calls by first loading the +address of the function into a register and then performing a subroutine +call on this register. This switch is needed if the target function +will lie outside of the 64 megabyte addressing range of the offset based +version of subroutine call instruction. +.Sp +Even if this switch is enabled, not all function calls will be turned +into long calls. The heuristic is that static functions, functions +which have the \fBshort-call\fR attribute, functions that are inside +the scope of a \fB#pragma no_long_calls\fR directive and functions whose +definitions have already been compiled within the current compilation +unit, will not be turned into long calls. The exception to this rule is +that weak function definitions, functions with the \fBlong-call\fR +attribute or the \fBsection\fR attribute, and functions that are within +the scope of a \fB#pragma long_calls\fR directive, will always be +turned into long calls. +.Sp +This feature is not enabled by default. Specifying +\&\fB\-mno\-long\-calls\fR will restore the default behavior, as will +placing the function calls within the scope of a \fB#pragma +long_calls_off\fR directive. Note these switches have no effect on how +the compiler generates code to handle function calls via function +pointers. +.IP "\fB\-msingle\-pic\-base\fR" 4 +.IX Item "-msingle-pic-base" +Treat the register used for \s-1PIC\s0 addressing as read-only, rather than +loading it in the prologue for each function. The run-time system is +responsible for initializing this register with an appropriate value +before execution begins. +.IP "\fB\-mpic\-register=\fR\fIreg\fR" 4 +.IX Item "-mpic-register=reg" +Specify the register to be used for \s-1PIC\s0 addressing. The default is R10 +unless stack-checking is enabled, when R9 is used. +.IP "\fB\-mcirrus\-fix\-invalid\-insns\fR" 4 +.IX Item "-mcirrus-fix-invalid-insns" +Insert NOPs into the instruction stream to in order to work around +problems with invalid Maverick instruction combinations. This option +is only valid if the \fB\-mcpu=ep9312\fR option has been used to +enable generation of instructions for the Cirrus Maverick floating +point co-processor. This option is not enabled by default, since the +problem is only present in older Maverick implementations. The default +can be re-enabled by use of the \fB\-mno\-cirrus\-fix\-invalid\-insns\fR +switch. +.IP "\fB\-mpoke\-function\-name\fR" 4 +.IX Item "-mpoke-function-name" +Write the name of each function into the text section, directly +preceding the function prologue. The generated code is similar to this: +.Sp +.Vb 9 +\& t0 +\& .ascii "arm_poke_function_name", 0 +\& .align +\& t1 +\& .word 0xff000000 + (t1 \- t0) +\& arm_poke_function_name +\& mov ip, sp +\& stmfd sp!, {fp, ip, lr, pc} +\& sub fp, ip, #4 +.Ve +.Sp +When performing a stack backtrace, code can inspect the value of +\&\f(CW\*(C`pc\*(C'\fR stored at \f(CW\*(C`fp + 0\*(C'\fR. If the trace function then looks at +location \f(CW\*(C`pc \- 12\*(C'\fR and the top 8 bits are set, then we know that +there is a function name embedded immediately preceding this location +and has length \f(CW\*(C`((pc[\-3]) & 0xff000000)\*(C'\fR. +.IP "\fB\-mthumb\fR" 4 +.IX Item "-mthumb" +Generate code for the Thumb instruction set. The default is to +use the 32\-bit \s-1ARM\s0 instruction set. +This option automatically enables either 16\-bit Thumb\-1 or +mixed 16/32\-bit Thumb\-2 instructions based on the \fB\-mcpu=\fR\fIname\fR +and \fB\-march=\fR\fIname\fR options. This option is not passed to the +assembler. If you want to force assembler files to be interpreted as Thumb code, +either add a \fB.thumb\fR directive to the source or pass the \fB\-mthumb\fR +option directly to the assembler by prefixing it with \fB\-Wa\fR. +.IP "\fB\-mtpcs\-frame\fR" 4 +.IX Item "-mtpcs-frame" +Generate a stack frame that is compliant with the Thumb Procedure Call +Standard for all non-leaf functions. (A leaf function is one that does +not call any other functions.) The default is \fB\-mno\-tpcs\-frame\fR. +.IP "\fB\-mtpcs\-leaf\-frame\fR" 4 +.IX Item "-mtpcs-leaf-frame" +Generate a stack frame that is compliant with the Thumb Procedure Call +Standard for all leaf functions. (A leaf function is one that does +not call any other functions.) The default is \fB\-mno\-apcs\-leaf\-frame\fR. +.IP "\fB\-mcallee\-super\-interworking\fR" 4 +.IX Item "-mcallee-super-interworking" +Gives all externally visible functions in the file being compiled an \s-1ARM\s0 +instruction set header which switches to Thumb mode before executing the +rest of the function. This allows these functions to be called from +non-interworking code. This option is not valid in \s-1AAPCS\s0 configurations +because interworking is enabled by default. +.IP "\fB\-mcaller\-super\-interworking\fR" 4 +.IX Item "-mcaller-super-interworking" +Allows calls via function pointers (including virtual functions) to +execute correctly regardless of whether the target code has been +compiled for interworking or not. There is a small overhead in the cost +of executing a function pointer if this option is enabled. This option +is not valid in \s-1AAPCS\s0 configurations because interworking is enabled +by default. +.IP "\fB\-mtp=\fR\fIname\fR" 4 +.IX Item "-mtp=name" +Specify the access model for the thread local storage pointer. The valid +models are \fBsoft\fR, which generates calls to \f(CW\*(C`_\|_aeabi_read_tp\*(C'\fR, +\&\fBcp15\fR, which fetches the thread pointer from \f(CW\*(C`cp15\*(C'\fR directly +(supported in the arm6k architecture), and \fBauto\fR, which uses the +best available method for the selected processor. The default setting is +\&\fBauto\fR. +.IP "\fB\-mword\-relocations\fR" 4 +.IX Item "-mword-relocations" +Only generate absolute relocations on word sized values (i.e. R_ARM_ABS32). +This is enabled by default on targets (uClinux, SymbianOS) where the runtime +loader imposes this restriction, and when \fB\-fpic\fR or \fB\-fPIC\fR +is specified. +.IP "\fB\-mfix\-cortex\-m3\-ldrd\fR" 4 +.IX Item "-mfix-cortex-m3-ldrd" +Some Cortex\-M3 cores can cause data corruption when \f(CW\*(C`ldrd\*(C'\fR instructions +with overlapping destination and base registers are used. This option avoids +generating these instructions. This option is enabled by default when +\&\fB\-mcpu=cortex\-m3\fR is specified. +.PP +\fI\s-1AVR\s0 Options\fR +.IX Subsection "AVR Options" +.PP +These options are defined for \s-1AVR\s0 implementations: +.IP "\fB\-mmcu=\fR\fImcu\fR" 4 +.IX Item "-mmcu=mcu" +Specify \s-1ATMEL\s0 \s-1AVR\s0 instruction set or \s-1MCU\s0 type. +.Sp +Instruction set avr1 is for the minimal \s-1AVR\s0 core, not supported by the C +compiler, only for assembler programs (\s-1MCU\s0 types: at90s1200, attiny10, +attiny11, attiny12, attiny15, attiny28). +.Sp +Instruction set avr2 (default) is for the classic \s-1AVR\s0 core with up to +8K program memory space (\s-1MCU\s0 types: at90s2313, at90s2323, attiny22, +at90s2333, at90s2343, at90s4414, at90s4433, at90s4434, at90s8515, +at90c8534, at90s8535). +.Sp +Instruction set avr3 is for the classic \s-1AVR\s0 core with up to 128K program +memory space (\s-1MCU\s0 types: atmega103, atmega603, at43usb320, at76c711). +.Sp +Instruction set avr4 is for the enhanced \s-1AVR\s0 core with up to 8K program +memory space (\s-1MCU\s0 types: atmega8, atmega83, atmega85). +.Sp +Instruction set avr5 is for the enhanced \s-1AVR\s0 core with up to 128K program +memory space (\s-1MCU\s0 types: atmega16, atmega161, atmega163, atmega32, atmega323, +atmega64, atmega128, at43usb355, at94k). +.IP "\fB\-mno\-interrupts\fR" 4 +.IX Item "-mno-interrupts" +Generated code is not compatible with hardware interrupts. +Code size will be smaller. +.IP "\fB\-mcall\-prologues\fR" 4 +.IX Item "-mcall-prologues" +Functions prologues/epilogues expanded as call to appropriate +subroutines. Code size will be smaller. +.IP "\fB\-mtiny\-stack\fR" 4 +.IX Item "-mtiny-stack" +Change only the low 8 bits of the stack pointer. +.IP "\fB\-mint8\fR" 4 +.IX Item "-mint8" +Assume int to be 8 bit integer. This affects the sizes of all types: A +char will be 1 byte, an int will be 1 byte, a long will be 2 bytes +and long long will be 4 bytes. Please note that this option does not +comply to the C standards, but it will provide you with smaller code +size. +.PP +\f(CW\*(C`EIND\*(C'\fR and Devices with more than 128k Bytes of Flash +.IX Subsection "EIND and Devices with more than 128k Bytes of Flash" +.PP +Pointers in the implementation are 16 bits wide. +The address of a function or label is represented as word address so +that indirect jumps and calls can address any code address in the +range of 64k words. +.PP +In order to faciliate indirect jump on devices with more than 128k +bytes of program memory space, there is a special function register called +\&\f(CW\*(C`EIND\*(C'\fR that serves as most significant part of the target address +when \f(CW\*(C`EICALL\*(C'\fR or \f(CW\*(C`EIJMP\*(C'\fR instructions are used. +.PP +Indirect jumps and calls on these devices are handled as follows and +are subject to some limitations: +.IP "\(bu" 4 +The compiler never sets \f(CW\*(C`EIND\*(C'\fR. +.IP "\(bu" 4 +The startup code from libgcc never sets \f(CW\*(C`EIND\*(C'\fR. +Notice that startup code is a blend of code from libgcc and avr-libc. +For the impact of avr-libc on \f(CW\*(C`EIND\*(C'\fR, see the +avr-libc\ user\ manual (\f(CW\*(C`http://nongnu.org/avr\-libc/user\-manual\*(C'\fR). +.IP "\(bu" 4 +The compiler uses \f(CW\*(C`EIND\*(C'\fR implicitely in \f(CW\*(C`EICALL\*(C'\fR/\f(CW\*(C`EIJMP\*(C'\fR +instructions or might read \f(CW\*(C`EIND\*(C'\fR directly. +.IP "\(bu" 4 +The compiler assumes that \f(CW\*(C`EIND\*(C'\fR never changes during the startup +code or run of the application. In particular, \f(CW\*(C`EIND\*(C'\fR is not +saved/restored in function or interrupt service routine +prologue/epilogue. +.IP "\(bu" 4 +It is legitimate for user-specific startup code to set up \f(CW\*(C`EIND\*(C'\fR +early, for example by means of initialization code located in +section \f(CW\*(C`.init3\*(C'\fR, and thus prior to general startup code that +initializes \s-1RAM\s0 and calls constructors. +.IP "\(bu" 4 +For indirect calls to functions and computed goto, the linker will +generate \fIstubs\fR. Stubs are jump pads sometimes also called +\&\fItrampolines\fR. Thus, the indirect call/jump will jump to such a stub. +The stub contains a direct jump to the desired address. +.IP "\(bu" 4 +Stubs will be generated automatically by the linker if +the following two conditions are met: +.RS 4 +.ie n .IP "\-<The address of a label is taken by means of the ""gs"" modifier>" 4 +.el .IP "\-<The address of a label is taken by means of the \f(CWgs\fR modifier>" 4 +.IX Item "-<The address of a label is taken by means of the gs modifier>" +(short for \fIgenerate stubs\fR) like so: +.Sp +.Vb 2 +\& LDI r24, lo8(gs(<func>)) +\& LDI r25, hi8(gs(<func>)) +.Ve +.IP "\-<The final location of that label is in a code segment>" 4 +.IX Item "-<The final location of that label is in a code segment>" +\&\fIoutside\fR the segment where the stubs are located. +.RE +.RS 4 +.RE +.IP "\(bu" 4 +The compiler will emit such \f(CW\*(C`gs\*(C'\fR modifiers for code labels in the +following situations: +.RS 4 +.IP "\-<Taking address of a function or code label.>" 4 +.IX Item "-<Taking address of a function or code label.>" +.PD 0 +.IP "\-<Computed goto.>" 4 +.IX Item "-<Computed goto.>" +.IP "\-<If prologue-save function is used, see \fB\-mcall\-prologues\fR>" 4 +.IX Item "-<If prologue-save function is used, see -mcall-prologues>" +.PD +command line option. +.IP "\-<Switch/case dispatch tables. If you do not want such dispatch>" 4 +.IX Item "-<Switch/case dispatch tables. If you do not want such dispatch>" +tables you can specify the \fB\-fno\-jump\-tables\fR command line option. +.IP "\-<C and \*(C+ constructors/destructors called during startup/shutdown.>" 4 +.IX Item "-<C and constructors/destructors called during startup/shutdown.>" +.PD 0 +.ie n .IP "\-<If the tools hit a ""gs()"" modifier explained above.>" 4 +.el .IP "\-<If the tools hit a \f(CWgs()\fR modifier explained above.>" 4 +.IX Item "-<If the tools hit a gs() modifier explained above.>" +.RE +.RS 4 +.RE +.IP "\(bu" 4 +.PD +The default linker script is arranged for code with \f(CW\*(C`EIND = 0\*(C'\fR. +If code is supposed to work for a setup with \f(CW\*(C`EIND != 0\*(C'\fR, a custom +linker script has to be used in order to place the sections whose +name start with \f(CW\*(C`.trampolines\*(C'\fR into the segment where \f(CW\*(C`EIND\*(C'\fR +points to. +.IP "\(bu" 4 +Jumping to non-symbolic addresses like so is \fInot\fR supported: +.Sp +.Vb 5 +\& int main (void) +\& { +\& /* Call function at word address 0x2 */ +\& return ((int(*)(void)) 0x2)(); +\& } +.Ve +.Sp +Instead, a stub has to be set up: +.Sp +.Vb 3 +\& int main (void) +\& { +\& extern int func_4 (void); +\& +\& /* Call function at byte address 0x4 */ +\& return func_4(); +\& } +.Ve +.Sp +and the application be linked with \f(CW\*(C`\-Wl,\-\-defsym,func_4=0x4\*(C'\fR. +Alternatively, \f(CW\*(C`func_4\*(C'\fR can be defined in the linker script. +.PP +\fIBlackfin Options\fR +.IX Subsection "Blackfin Options" +.IP "\fB\-mcpu=\fR\fIcpu\fR[\fB\-\fR\fIsirevision\fR]" 4 +.IX Item "-mcpu=cpu[-sirevision]" +Specifies the name of the target Blackfin processor. Currently, \fIcpu\fR +can be one of \fBbf512\fR, \fBbf514\fR, \fBbf516\fR, \fBbf518\fR, +\&\fBbf522\fR, \fBbf523\fR, \fBbf524\fR, \fBbf525\fR, \fBbf526\fR, +\&\fBbf527\fR, \fBbf531\fR, \fBbf532\fR, \fBbf533\fR, +\&\fBbf534\fR, \fBbf536\fR, \fBbf537\fR, \fBbf538\fR, \fBbf539\fR, +\&\fBbf542\fR, \fBbf544\fR, \fBbf547\fR, \fBbf548\fR, \fBbf549\fR, +\&\fBbf542m\fR, \fBbf544m\fR, \fBbf547m\fR, \fBbf548m\fR, \fBbf549m\fR, +\&\fBbf561\fR. +The optional \fIsirevision\fR specifies the silicon revision of the target +Blackfin processor. Any workarounds available for the targeted silicon revision +will be enabled. If \fIsirevision\fR is \fBnone\fR, no workarounds are enabled. +If \fIsirevision\fR is \fBany\fR, all workarounds for the targeted processor +will be enabled. The \f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR macro is defined to two +hexadecimal digits representing the major and minor numbers in the silicon +revision. If \fIsirevision\fR is \fBnone\fR, the \f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR +is not defined. If \fIsirevision\fR is \fBany\fR, the +\&\f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR is defined to be \f(CW0xffff\fR. +If this optional \fIsirevision\fR is not used, \s-1GCC\s0 assumes the latest known +silicon revision of the targeted Blackfin processor. +.Sp +Support for \fBbf561\fR is incomplete. For \fBbf561\fR, +Only the processor macro is defined. +Without this option, \fBbf532\fR is used as the processor by default. +The corresponding predefined processor macros for \fIcpu\fR is to +be defined. And for \fBbfin-elf\fR toolchain, this causes the hardware \s-1BSP\s0 +provided by libgloss to be linked in if \fB\-msim\fR is not given. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Specifies that the program will be run on the simulator. This causes +the simulator \s-1BSP\s0 provided by libgloss to be linked in. This option +has effect only for \fBbfin-elf\fR toolchain. +Certain other options, such as \fB\-mid\-shared\-library\fR and +\&\fB\-mfdpic\fR, imply \fB\-msim\fR. +.IP "\fB\-momit\-leaf\-frame\-pointer\fR" 4 +.IX Item "-momit-leaf-frame-pointer" +Don't keep the frame pointer in a register for leaf functions. This +avoids the instructions to save, set up and restore frame pointers and +makes an extra register available in leaf functions. The option +\&\fB\-fomit\-frame\-pointer\fR removes the frame pointer for all functions +which might make debugging harder. +.IP "\fB\-mspecld\-anomaly\fR" 4 +.IX Item "-mspecld-anomaly" +When enabled, the compiler will ensure that the generated code does not +contain speculative loads after jump instructions. If this option is used, +\&\f(CW\*(C`_\|_WORKAROUND_SPECULATIVE_LOADS\*(C'\fR is defined. +.IP "\fB\-mno\-specld\-anomaly\fR" 4 +.IX Item "-mno-specld-anomaly" +Don't generate extra code to prevent speculative loads from occurring. +.IP "\fB\-mcsync\-anomaly\fR" 4 +.IX Item "-mcsync-anomaly" +When enabled, the compiler will ensure that the generated code does not +contain \s-1CSYNC\s0 or \s-1SSYNC\s0 instructions too soon after conditional branches. +If this option is used, \f(CW\*(C`_\|_WORKAROUND_SPECULATIVE_SYNCS\*(C'\fR is defined. +.IP "\fB\-mno\-csync\-anomaly\fR" 4 +.IX Item "-mno-csync-anomaly" +Don't generate extra code to prevent \s-1CSYNC\s0 or \s-1SSYNC\s0 instructions from +occurring too soon after a conditional branch. +.IP "\fB\-mlow\-64k\fR" 4 +.IX Item "-mlow-64k" +When enabled, the compiler is free to take advantage of the knowledge that +the entire program fits into the low 64k of memory. +.IP "\fB\-mno\-low\-64k\fR" 4 +.IX Item "-mno-low-64k" +Assume that the program is arbitrarily large. This is the default. +.IP "\fB\-mstack\-check\-l1\fR" 4 +.IX Item "-mstack-check-l1" +Do stack checking using information placed into L1 scratchpad memory by the +uClinux kernel. +.IP "\fB\-mid\-shared\-library\fR" 4 +.IX Item "-mid-shared-library" +Generate code that supports shared libraries via the library \s-1ID\s0 method. +This allows for execute in place and shared libraries in an environment +without virtual memory management. This option implies \fB\-fPIC\fR. +With a \fBbfin-elf\fR target, this option implies \fB\-msim\fR. +.IP "\fB\-mno\-id\-shared\-library\fR" 4 +.IX Item "-mno-id-shared-library" +Generate code that doesn't assume \s-1ID\s0 based shared libraries are being used. +This is the default. +.IP "\fB\-mleaf\-id\-shared\-library\fR" 4 +.IX Item "-mleaf-id-shared-library" +Generate code that supports shared libraries via the library \s-1ID\s0 method, +but assumes that this library or executable won't link against any other +\&\s-1ID\s0 shared libraries. That allows the compiler to use faster code for jumps +and calls. +.IP "\fB\-mno\-leaf\-id\-shared\-library\fR" 4 +.IX Item "-mno-leaf-id-shared-library" +Do not assume that the code being compiled won't link against any \s-1ID\s0 shared +libraries. Slower code will be generated for jump and call insns. +.IP "\fB\-mshared\-library\-id=n\fR" 4 +.IX Item "-mshared-library-id=n" +Specified the identification number of the \s-1ID\s0 based shared library being +compiled. Specifying a value of 0 will generate more compact code, specifying +other values will force the allocation of that number to the current +library but is no more space or time efficient than omitting this option. +.IP "\fB\-msep\-data\fR" 4 +.IX Item "-msep-data" +Generate code that allows the data segment to be located in a different +area of memory from the text segment. This allows for execute in place in +an environment without virtual memory management by eliminating relocations +against the text section. +.IP "\fB\-mno\-sep\-data\fR" 4 +.IX Item "-mno-sep-data" +Generate code that assumes that the data segment follows the text segment. +This is the default. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +.PD 0 +.IP "\fB\-mno\-long\-calls\fR" 4 +.IX Item "-mno-long-calls" +.PD +Tells the compiler to perform function calls by first loading the +address of the function into a register and then performing a subroutine +call on this register. This switch is needed if the target function +will lie outside of the 24 bit addressing range of the offset based +version of subroutine call instruction. +.Sp +This feature is not enabled by default. Specifying +\&\fB\-mno\-long\-calls\fR will restore the default behavior. Note these +switches have no effect on how the compiler generates code to handle +function calls via function pointers. +.IP "\fB\-mfast\-fp\fR" 4 +.IX Item "-mfast-fp" +Link with the fast floating-point library. This library relaxes some of +the \s-1IEEE\s0 floating-point standard's rules for checking inputs against +Not-a-Number (\s-1NAN\s0), in the interest of performance. +.IP "\fB\-minline\-plt\fR" 4 +.IX Item "-minline-plt" +Enable inlining of \s-1PLT\s0 entries in function calls to functions that are +not known to bind locally. It has no effect without \fB\-mfdpic\fR. +.IP "\fB\-mmulticore\fR" 4 +.IX Item "-mmulticore" +Build standalone application for multicore Blackfin processor. Proper +start files and link scripts will be used to support multicore. +This option defines \f(CW\*(C`_\|_BFIN_MULTICORE\*(C'\fR. It can only be used with +\&\fB\-mcpu=bf561\fR[\fB\-\fR\fIsirevision\fR]. It can be used with +\&\fB\-mcorea\fR or \fB\-mcoreb\fR. If it's used without +\&\fB\-mcorea\fR or \fB\-mcoreb\fR, single application/dual core +programming model is used. In this model, the main function of Core B +should be named as coreb_main. If it's used with \fB\-mcorea\fR or +\&\fB\-mcoreb\fR, one application per core programming model is used. +If this option is not used, single core application programming +model is used. +.IP "\fB\-mcorea\fR" 4 +.IX Item "-mcorea" +Build standalone application for Core A of \s-1BF561\s0 when using +one application per core programming model. Proper start files +and link scripts will be used to support Core A. This option +defines \f(CW\*(C`_\|_BFIN_COREA\*(C'\fR. It must be used with \fB\-mmulticore\fR. +.IP "\fB\-mcoreb\fR" 4 +.IX Item "-mcoreb" +Build standalone application for Core B of \s-1BF561\s0 when using +one application per core programming model. Proper start files +and link scripts will be used to support Core B. This option +defines \f(CW\*(C`_\|_BFIN_COREB\*(C'\fR. When this option is used, coreb_main +should be used instead of main. It must be used with +\&\fB\-mmulticore\fR. +.IP "\fB\-msdram\fR" 4 +.IX Item "-msdram" +Build standalone application for \s-1SDRAM\s0. Proper start files and +link scripts will be used to put the application into \s-1SDRAM\s0. +Loader should initialize \s-1SDRAM\s0 before loading the application +into \s-1SDRAM\s0. This option defines \f(CW\*(C`_\|_BFIN_SDRAM\*(C'\fR. +.IP "\fB\-micplb\fR" 4 +.IX Item "-micplb" +Assume that ICPLBs are enabled at runtime. This has an effect on certain +anomaly workarounds. For Linux targets, the default is to assume ICPLBs +are enabled; for standalone applications the default is off. +.PP +\fI\s-1CRIS\s0 Options\fR +.IX Subsection "CRIS Options" +.PP +These options are defined specifically for the \s-1CRIS\s0 ports. +.IP "\fB\-march=\fR\fIarchitecture-type\fR" 4 +.IX Item "-march=architecture-type" +.PD 0 +.IP "\fB\-mcpu=\fR\fIarchitecture-type\fR" 4 +.IX Item "-mcpu=architecture-type" +.PD +Generate code for the specified architecture. The choices for +\&\fIarchitecture-type\fR are \fBv3\fR, \fBv8\fR and \fBv10\fR for +respectively \s-1ETRAX\s0\ 4, \s-1ETRAX\s0\ 100, and \s-1ETRAX\s0\ 100\ \s-1LX\s0. +Default is \fBv0\fR except for cris-axis-linux-gnu, where the default is +\&\fBv10\fR. +.IP "\fB\-mtune=\fR\fIarchitecture-type\fR" 4 +.IX Item "-mtune=architecture-type" +Tune to \fIarchitecture-type\fR everything applicable about the generated +code, except for the \s-1ABI\s0 and the set of available instructions. The +choices for \fIarchitecture-type\fR are the same as for +\&\fB\-march=\fR\fIarchitecture-type\fR. +.IP "\fB\-mmax\-stack\-frame=\fR\fIn\fR" 4 +.IX Item "-mmax-stack-frame=n" +Warn when the stack frame of a function exceeds \fIn\fR bytes. +.IP "\fB\-metrax4\fR" 4 +.IX Item "-metrax4" +.PD 0 +.IP "\fB\-metrax100\fR" 4 +.IX Item "-metrax100" +.PD +The options \fB\-metrax4\fR and \fB\-metrax100\fR are synonyms for +\&\fB\-march=v3\fR and \fB\-march=v8\fR respectively. +.IP "\fB\-mmul\-bug\-workaround\fR" 4 +.IX Item "-mmul-bug-workaround" +.PD 0 +.IP "\fB\-mno\-mul\-bug\-workaround\fR" 4 +.IX Item "-mno-mul-bug-workaround" +.PD +Work around a bug in the \f(CW\*(C`muls\*(C'\fR and \f(CW\*(C`mulu\*(C'\fR instructions for \s-1CPU\s0 +models where it applies. This option is active by default. +.IP "\fB\-mpdebug\fR" 4 +.IX Item "-mpdebug" +Enable CRIS-specific verbose debug-related information in the assembly +code. This option also has the effect to turn off the \fB#NO_APP\fR +formatted-code indicator to the assembler at the beginning of the +assembly file. +.IP "\fB\-mcc\-init\fR" 4 +.IX Item "-mcc-init" +Do not use condition-code results from previous instruction; always emit +compare and test instructions before use of condition codes. +.IP "\fB\-mno\-side\-effects\fR" 4 +.IX Item "-mno-side-effects" +Do not emit instructions with side-effects in addressing modes other than +post-increment. +.IP "\fB\-mstack\-align\fR" 4 +.IX Item "-mstack-align" +.PD 0 +.IP "\fB\-mno\-stack\-align\fR" 4 +.IX Item "-mno-stack-align" +.IP "\fB\-mdata\-align\fR" 4 +.IX Item "-mdata-align" +.IP "\fB\-mno\-data\-align\fR" 4 +.IX Item "-mno-data-align" +.IP "\fB\-mconst\-align\fR" 4 +.IX Item "-mconst-align" +.IP "\fB\-mno\-const\-align\fR" 4 +.IX Item "-mno-const-align" +.PD +These options (no-options) arranges (eliminate arrangements) for the +stack-frame, individual data and constants to be aligned for the maximum +single data access size for the chosen \s-1CPU\s0 model. The default is to +arrange for 32\-bit alignment. \s-1ABI\s0 details such as structure layout are +not affected by these options. +.IP "\fB\-m32\-bit\fR" 4 +.IX Item "-m32-bit" +.PD 0 +.IP "\fB\-m16\-bit\fR" 4 +.IX Item "-m16-bit" +.IP "\fB\-m8\-bit\fR" 4 +.IX Item "-m8-bit" +.PD +Similar to the stack\- data\- and const-align options above, these options +arrange for stack-frame, writable data and constants to all be 32\-bit, +16\-bit or 8\-bit aligned. The default is 32\-bit alignment. +.IP "\fB\-mno\-prologue\-epilogue\fR" 4 +.IX Item "-mno-prologue-epilogue" +.PD 0 +.IP "\fB\-mprologue\-epilogue\fR" 4 +.IX Item "-mprologue-epilogue" +.PD +With \fB\-mno\-prologue\-epilogue\fR, the normal function prologue and +epilogue that sets up the stack-frame are omitted and no return +instructions or return sequences are generated in the code. Use this +option only together with visual inspection of the compiled code: no +warnings or errors are generated when call-saved registers must be saved, +or storage for local variable needs to be allocated. +.IP "\fB\-mno\-gotplt\fR" 4 +.IX Item "-mno-gotplt" +.PD 0 +.IP "\fB\-mgotplt\fR" 4 +.IX Item "-mgotplt" +.PD +With \fB\-fpic\fR and \fB\-fPIC\fR, don't generate (do generate) +instruction sequences that load addresses for functions from the \s-1PLT\s0 part +of the \s-1GOT\s0 rather than (traditional on other architectures) calls to the +\&\s-1PLT\s0. The default is \fB\-mgotplt\fR. +.IP "\fB\-melf\fR" 4 +.IX Item "-melf" +Legacy no-op option only recognized with the cris-axis-elf and +cris-axis-linux-gnu targets. +.IP "\fB\-mlinux\fR" 4 +.IX Item "-mlinux" +Legacy no-op option only recognized with the cris-axis-linux-gnu target. +.IP "\fB\-sim\fR" 4 +.IX Item "-sim" +This option, recognized for the cris-axis-elf arranges +to link with input-output functions from a simulator library. Code, +initialized data and zero-initialized data are allocated consecutively. +.IP "\fB\-sim2\fR" 4 +.IX Item "-sim2" +Like \fB\-sim\fR, but pass linker options to locate initialized data at +0x40000000 and zero-initialized data at 0x80000000. +.PP +\fI\s-1CRX\s0 Options\fR +.IX Subsection "CRX Options" +.PP +These options are defined specifically for the \s-1CRX\s0 ports. +.IP "\fB\-mmac\fR" 4 +.IX Item "-mmac" +Enable the use of multiply-accumulate instructions. Disabled by default. +.IP "\fB\-mpush\-args\fR" 4 +.IX Item "-mpush-args" +Push instructions will be used to pass outgoing arguments when functions +are called. Enabled by default. +.PP +\fIDarwin Options\fR +.IX Subsection "Darwin Options" +.PP +These options are defined for all architectures running the Darwin operating +system. +.PP +\&\s-1FSF\s0 \s-1GCC\s0 on Darwin does not create \*(L"fat\*(R" object files; it will create +an object file for the single architecture that it was built to +target. Apple's \s-1GCC\s0 on Darwin does create \*(L"fat\*(R" files if multiple +\&\fB\-arch\fR options are used; it does so by running the compiler or +linker multiple times and joining the results together with +\&\fIlipo\fR. +.PP +The subtype of the file created (like \fBppc7400\fR or \fBppc970\fR or +\&\fBi686\fR) is determined by the flags that specify the \s-1ISA\s0 +that \s-1GCC\s0 is targetting, like \fB\-mcpu\fR or \fB\-march\fR. The +\&\fB\-force_cpusubtype_ALL\fR option can be used to override this. +.PP +The Darwin tools vary in their behavior when presented with an \s-1ISA\s0 +mismatch. The assembler, \fIas\fR, will only permit instructions to +be used that are valid for the subtype of the file it is generating, +so you cannot put 64\-bit instructions in a \fBppc750\fR object file. +The linker for shared libraries, \fI/usr/bin/libtool\fR, will fail +and print an error if asked to create a shared library with a less +restrictive subtype than its input files (for instance, trying to put +a \fBppc970\fR object file in a \fBppc7400\fR library). The linker +for executables, \fIld\fR, will quietly give the executable the most +restrictive subtype of any of its input files. +.IP "\fB\-F\fR\fIdir\fR" 4 +.IX Item "-Fdir" +Add the framework directory \fIdir\fR to the head of the list of +directories to be searched for header files. These directories are +interleaved with those specified by \fB\-I\fR options and are +scanned in a left-to-right order. +.Sp +A framework directory is a directory with frameworks in it. A +framework is a directory with a \fB\*(L"Headers\*(R"\fR and/or +\&\fB\*(L"PrivateHeaders\*(R"\fR directory contained directly in it that ends +in \fB\*(L".framework\*(R"\fR. The name of a framework is the name of this +directory excluding the \fB\*(L".framework\*(R"\fR. Headers associated with +the framework are found in one of those two directories, with +\&\fB\*(L"Headers\*(R"\fR being searched first. A subframework is a framework +directory that is in a framework's \fB\*(L"Frameworks\*(R"\fR directory. +Includes of subframework headers can only appear in a header of a +framework that contains the subframework, or in a sibling subframework +header. Two subframeworks are siblings if they occur in the same +framework. A subframework should not have the same name as a +framework, a warning will be issued if this is violated. Currently a +subframework cannot have subframeworks, in the future, the mechanism +may be extended to support this. The standard frameworks can be found +in \fB\*(L"/System/Library/Frameworks\*(R"\fR and +\&\fB\*(L"/Library/Frameworks\*(R"\fR. An example include looks like +\&\f(CW\*(C`#include <Framework/header.h>\*(C'\fR, where \fBFramework\fR denotes +the name of the framework and header.h is found in the +\&\fB\*(L"PrivateHeaders\*(R"\fR or \fB\*(L"Headers\*(R"\fR directory. +.IP "\fB\-iframework\fR\fIdir\fR" 4 +.IX Item "-iframeworkdir" +Like \fB\-F\fR except the directory is a treated as a system +directory. The main difference between this \fB\-iframework\fR and +\&\fB\-F\fR is that with \fB\-iframework\fR the compiler does not +warn about constructs contained within header files found via +\&\fIdir\fR. This option is valid only for the C family of languages. +.IP "\fB\-gused\fR" 4 +.IX Item "-gused" +Emit debugging information for symbols that are used. For \s-1STABS\s0 +debugging format, this enables \fB\-feliminate\-unused\-debug\-symbols\fR. +This is by default \s-1ON\s0. +.IP "\fB\-gfull\fR" 4 +.IX Item "-gfull" +Emit debugging information for all symbols and types. +.IP "\fB\-mmacosx\-version\-min=\fR\fIversion\fR" 4 +.IX Item "-mmacosx-version-min=version" +The earliest version of MacOS X that this executable will run on +is \fIversion\fR. Typical values of \fIversion\fR include \f(CW10.1\fR, +\&\f(CW10.2\fR, and \f(CW10.3.9\fR. +.Sp +If the compiler was built to use the system's headers by default, +then the default for this option is the system version on which the +compiler is running, otherwise the default is to make choices which +are compatible with as many systems and code bases as possible. +.IP "\fB\-mkernel\fR" 4 +.IX Item "-mkernel" +Enable kernel development mode. The \fB\-mkernel\fR option sets +\&\fB\-static\fR, \fB\-fno\-common\fR, \fB\-fno\-cxa\-atexit\fR, +\&\fB\-fno\-exceptions\fR, \fB\-fno\-non\-call\-exceptions\fR, +\&\fB\-fapple\-kext\fR, \fB\-fno\-weak\fR and \fB\-fno\-rtti\fR where +applicable. This mode also sets \fB\-mno\-altivec\fR, +\&\fB\-msoft\-float\fR, \fB\-fno\-builtin\fR and +\&\fB\-mlong\-branch\fR for PowerPC targets. +.IP "\fB\-mone\-byte\-bool\fR" 4 +.IX Item "-mone-byte-bool" +Override the defaults for \fBbool\fR so that \fBsizeof(bool)==1\fR. +By default \fBsizeof(bool)\fR is \fB4\fR when compiling for +Darwin/PowerPC and \fB1\fR when compiling for Darwin/x86, so this +option has no effect on x86. +.Sp +\&\fBWarning:\fR The \fB\-mone\-byte\-bool\fR switch causes \s-1GCC\s0 +to generate code that is not binary compatible with code generated +without that switch. Using this switch may require recompiling all +other modules in a program, including system libraries. Use this +switch to conform to a non-default data model. +.IP "\fB\-mfix\-and\-continue\fR" 4 +.IX Item "-mfix-and-continue" +.PD 0 +.IP "\fB\-ffix\-and\-continue\fR" 4 +.IX Item "-ffix-and-continue" +.IP "\fB\-findirect\-data\fR" 4 +.IX Item "-findirect-data" +.PD +Generate code suitable for fast turn around development. Needed to +enable gdb to dynamically load \f(CW\*(C`.o\*(C'\fR files into already running +programs. \fB\-findirect\-data\fR and \fB\-ffix\-and\-continue\fR +are provided for backwards compatibility. +.IP "\fB\-all_load\fR" 4 +.IX Item "-all_load" +Loads all members of static archive libraries. +See man \fIld\fR\|(1) for more information. +.IP "\fB\-arch_errors_fatal\fR" 4 +.IX Item "-arch_errors_fatal" +Cause the errors having to do with files that have the wrong architecture +to be fatal. +.IP "\fB\-bind_at_load\fR" 4 +.IX Item "-bind_at_load" +Causes the output file to be marked such that the dynamic linker will +bind all undefined references when the file is loaded or launched. +.IP "\fB\-bundle\fR" 4 +.IX Item "-bundle" +Produce a Mach-o bundle format file. +See man \fIld\fR\|(1) for more information. +.IP "\fB\-bundle_loader\fR \fIexecutable\fR" 4 +.IX Item "-bundle_loader executable" +This option specifies the \fIexecutable\fR that will be loading the build +output file being linked. See man \fIld\fR\|(1) for more information. +.IP "\fB\-dynamiclib\fR" 4 +.IX Item "-dynamiclib" +When passed this option, \s-1GCC\s0 will produce a dynamic library instead of +an executable when linking, using the Darwin \fIlibtool\fR command. +.IP "\fB\-force_cpusubtype_ALL\fR" 4 +.IX Item "-force_cpusubtype_ALL" +This causes \s-1GCC\s0's output file to have the \fI\s-1ALL\s0\fR subtype, instead of +one controlled by the \fB\-mcpu\fR or \fB\-march\fR option. +.IP "\fB\-allowable_client\fR \fIclient_name\fR" 4 +.IX Item "-allowable_client client_name" +.PD 0 +.IP "\fB\-client_name\fR" 4 +.IX Item "-client_name" +.IP "\fB\-compatibility_version\fR" 4 +.IX Item "-compatibility_version" +.IP "\fB\-current_version\fR" 4 +.IX Item "-current_version" +.IP "\fB\-dead_strip\fR" 4 +.IX Item "-dead_strip" +.IP "\fB\-dependency\-file\fR" 4 +.IX Item "-dependency-file" +.IP "\fB\-dylib_file\fR" 4 +.IX Item "-dylib_file" +.IP "\fB\-dylinker_install_name\fR" 4 +.IX Item "-dylinker_install_name" +.IP "\fB\-dynamic\fR" 4 +.IX Item "-dynamic" +.IP "\fB\-exported_symbols_list\fR" 4 +.IX Item "-exported_symbols_list" +.IP "\fB\-filelist\fR" 4 +.IX Item "-filelist" +.IP "\fB\-flat_namespace\fR" 4 +.IX Item "-flat_namespace" +.IP "\fB\-force_flat_namespace\fR" 4 +.IX Item "-force_flat_namespace" +.IP "\fB\-headerpad_max_install_names\fR" 4 +.IX Item "-headerpad_max_install_names" +.IP "\fB\-image_base\fR" 4 +.IX Item "-image_base" +.IP "\fB\-init\fR" 4 +.IX Item "-init" +.IP "\fB\-install_name\fR" 4 +.IX Item "-install_name" +.IP "\fB\-keep_private_externs\fR" 4 +.IX Item "-keep_private_externs" +.IP "\fB\-multi_module\fR" 4 +.IX Item "-multi_module" +.IP "\fB\-multiply_defined\fR" 4 +.IX Item "-multiply_defined" +.IP "\fB\-multiply_defined_unused\fR" 4 +.IX Item "-multiply_defined_unused" +.IP "\fB\-noall_load\fR" 4 +.IX Item "-noall_load" +.IP "\fB\-no_dead_strip_inits_and_terms\fR" 4 +.IX Item "-no_dead_strip_inits_and_terms" +.IP "\fB\-nofixprebinding\fR" 4 +.IX Item "-nofixprebinding" +.IP "\fB\-nomultidefs\fR" 4 +.IX Item "-nomultidefs" +.IP "\fB\-noprebind\fR" 4 +.IX Item "-noprebind" +.IP "\fB\-noseglinkedit\fR" 4 +.IX Item "-noseglinkedit" +.IP "\fB\-pagezero_size\fR" 4 +.IX Item "-pagezero_size" +.IP "\fB\-prebind\fR" 4 +.IX Item "-prebind" +.IP "\fB\-prebind_all_twolevel_modules\fR" 4 +.IX Item "-prebind_all_twolevel_modules" +.IP "\fB\-private_bundle\fR" 4 +.IX Item "-private_bundle" +.IP "\fB\-read_only_relocs\fR" 4 +.IX Item "-read_only_relocs" +.IP "\fB\-sectalign\fR" 4 +.IX Item "-sectalign" +.IP "\fB\-sectobjectsymbols\fR" 4 +.IX Item "-sectobjectsymbols" +.IP "\fB\-whyload\fR" 4 +.IX Item "-whyload" +.IP "\fB\-seg1addr\fR" 4 +.IX Item "-seg1addr" +.IP "\fB\-sectcreate\fR" 4 +.IX Item "-sectcreate" +.IP "\fB\-sectobjectsymbols\fR" 4 +.IX Item "-sectobjectsymbols" +.IP "\fB\-sectorder\fR" 4 +.IX Item "-sectorder" +.IP "\fB\-segaddr\fR" 4 +.IX Item "-segaddr" +.IP "\fB\-segs_read_only_addr\fR" 4 +.IX Item "-segs_read_only_addr" +.IP "\fB\-segs_read_write_addr\fR" 4 +.IX Item "-segs_read_write_addr" +.IP "\fB\-seg_addr_table\fR" 4 +.IX Item "-seg_addr_table" +.IP "\fB\-seg_addr_table_filename\fR" 4 +.IX Item "-seg_addr_table_filename" +.IP "\fB\-seglinkedit\fR" 4 +.IX Item "-seglinkedit" +.IP "\fB\-segprot\fR" 4 +.IX Item "-segprot" +.IP "\fB\-segs_read_only_addr\fR" 4 +.IX Item "-segs_read_only_addr" +.IP "\fB\-segs_read_write_addr\fR" 4 +.IX Item "-segs_read_write_addr" +.IP "\fB\-single_module\fR" 4 +.IX Item "-single_module" +.IP "\fB\-static\fR" 4 +.IX Item "-static" +.IP "\fB\-sub_library\fR" 4 +.IX Item "-sub_library" +.IP "\fB\-sub_umbrella\fR" 4 +.IX Item "-sub_umbrella" +.IP "\fB\-twolevel_namespace\fR" 4 +.IX Item "-twolevel_namespace" +.IP "\fB\-umbrella\fR" 4 +.IX Item "-umbrella" +.IP "\fB\-undefined\fR" 4 +.IX Item "-undefined" +.IP "\fB\-unexported_symbols_list\fR" 4 +.IX Item "-unexported_symbols_list" +.IP "\fB\-weak_reference_mismatches\fR" 4 +.IX Item "-weak_reference_mismatches" +.IP "\fB\-whatsloaded\fR" 4 +.IX Item "-whatsloaded" +.PD +These options are passed to the Darwin linker. The Darwin linker man page +describes them in detail. +.PP +\fI\s-1DEC\s0 Alpha Options\fR +.IX Subsection "DEC Alpha Options" +.PP +These \fB\-m\fR options are defined for the \s-1DEC\s0 Alpha implementations: +.IP "\fB\-mno\-soft\-float\fR" 4 +.IX Item "-mno-soft-float" +.PD 0 +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD +Use (do not use) the hardware floating-point instructions for +floating-point operations. When \fB\-msoft\-float\fR is specified, +functions in \fIlibgcc.a\fR will be used to perform floating-point +operations. Unless they are replaced by routines that emulate the +floating-point operations, or compiled in such a way as to call such +emulations routines, these routines will issue floating-point +operations. If you are compiling for an Alpha without floating-point +operations, you must ensure that the library is built so as not to call +them. +.Sp +Note that Alpha implementations without floating-point operations are +required to have floating-point registers. +.IP "\fB\-mfp\-reg\fR" 4 +.IX Item "-mfp-reg" +.PD 0 +.IP "\fB\-mno\-fp\-regs\fR" 4 +.IX Item "-mno-fp-regs" +.PD +Generate code that uses (does not use) the floating-point register set. +\&\fB\-mno\-fp\-regs\fR implies \fB\-msoft\-float\fR. If the floating-point +register set is not used, floating point operands are passed in integer +registers as if they were integers and floating-point results are passed +in \f(CW$0\fR instead of \f(CW$f0\fR. This is a non-standard calling sequence, +so any function with a floating-point argument or return value called by code +compiled with \fB\-mno\-fp\-regs\fR must also be compiled with that +option. +.Sp +A typical use of this option is building a kernel that does not use, +and hence need not save and restore, any floating-point registers. +.IP "\fB\-mieee\fR" 4 +.IX Item "-mieee" +The Alpha architecture implements floating-point hardware optimized for +maximum performance. It is mostly compliant with the \s-1IEEE\s0 floating +point standard. However, for full compliance, software assistance is +required. This option generates code fully \s-1IEEE\s0 compliant code +\&\fIexcept\fR that the \fIinexact-flag\fR is not maintained (see below). +If this option is turned on, the preprocessor macro \f(CW\*(C`_IEEE_FP\*(C'\fR is +defined during compilation. The resulting code is less efficient but is +able to correctly support denormalized numbers and exceptional \s-1IEEE\s0 +values such as not-a-number and plus/minus infinity. Other Alpha +compilers call this option \fB\-ieee_with_no_inexact\fR. +.IP "\fB\-mieee\-with\-inexact\fR" 4 +.IX Item "-mieee-with-inexact" +This is like \fB\-mieee\fR except the generated code also maintains +the \s-1IEEE\s0 \fIinexact-flag\fR. Turning on this option causes the +generated code to implement fully-compliant \s-1IEEE\s0 math. In addition to +\&\f(CW\*(C`_IEEE_FP\*(C'\fR, \f(CW\*(C`_IEEE_FP_EXACT\*(C'\fR is defined as a preprocessor +macro. On some Alpha implementations the resulting code may execute +significantly slower than the code generated by default. Since there is +very little code that depends on the \fIinexact-flag\fR, you should +normally not specify this option. Other Alpha compilers call this +option \fB\-ieee_with_inexact\fR. +.IP "\fB\-mfp\-trap\-mode=\fR\fItrap-mode\fR" 4 +.IX Item "-mfp-trap-mode=trap-mode" +This option controls what floating-point related traps are enabled. +Other Alpha compilers call this option \fB\-fptm\fR \fItrap-mode\fR. +The trap mode can be set to one of four values: +.RS 4 +.IP "\fBn\fR" 4 +.IX Item "n" +This is the default (normal) setting. The only traps that are enabled +are the ones that cannot be disabled in software (e.g., division by zero +trap). +.IP "\fBu\fR" 4 +.IX Item "u" +In addition to the traps enabled by \fBn\fR, underflow traps are enabled +as well. +.IP "\fBsu\fR" 4 +.IX Item "su" +Like \fBu\fR, but the instructions are marked to be safe for software +completion (see Alpha architecture manual for details). +.IP "\fBsui\fR" 4 +.IX Item "sui" +Like \fBsu\fR, but inexact traps are enabled as well. +.RE +.RS 4 +.RE +.IP "\fB\-mfp\-rounding\-mode=\fR\fIrounding-mode\fR" 4 +.IX Item "-mfp-rounding-mode=rounding-mode" +Selects the \s-1IEEE\s0 rounding mode. Other Alpha compilers call this option +\&\fB\-fprm\fR \fIrounding-mode\fR. The \fIrounding-mode\fR can be one +of: +.RS 4 +.IP "\fBn\fR" 4 +.IX Item "n" +Normal \s-1IEEE\s0 rounding mode. Floating point numbers are rounded towards +the nearest machine number or towards the even machine number in case +of a tie. +.IP "\fBm\fR" 4 +.IX Item "m" +Round towards minus infinity. +.IP "\fBc\fR" 4 +.IX Item "c" +Chopped rounding mode. Floating point numbers are rounded towards zero. +.IP "\fBd\fR" 4 +.IX Item "d" +Dynamic rounding mode. A field in the floating point control register +(\fIfpcr\fR, see Alpha architecture reference manual) controls the +rounding mode in effect. The C library initializes this register for +rounding towards plus infinity. Thus, unless your program modifies the +\&\fIfpcr\fR, \fBd\fR corresponds to round towards plus infinity. +.RE +.RS 4 +.RE +.IP "\fB\-mtrap\-precision=\fR\fItrap-precision\fR" 4 +.IX Item "-mtrap-precision=trap-precision" +In the Alpha architecture, floating point traps are imprecise. This +means without software assistance it is impossible to recover from a +floating trap and program execution normally needs to be terminated. +\&\s-1GCC\s0 can generate code that can assist operating system trap handlers +in determining the exact location that caused a floating point trap. +Depending on the requirements of an application, different levels of +precisions can be selected: +.RS 4 +.IP "\fBp\fR" 4 +.IX Item "p" +Program precision. This option is the default and means a trap handler +can only identify which program caused a floating point exception. +.IP "\fBf\fR" 4 +.IX Item "f" +Function precision. The trap handler can determine the function that +caused a floating point exception. +.IP "\fBi\fR" 4 +.IX Item "i" +Instruction precision. The trap handler can determine the exact +instruction that caused a floating point exception. +.RE +.RS 4 +.Sp +Other Alpha compilers provide the equivalent options called +\&\fB\-scope_safe\fR and \fB\-resumption_safe\fR. +.RE +.IP "\fB\-mieee\-conformant\fR" 4 +.IX Item "-mieee-conformant" +This option marks the generated code as \s-1IEEE\s0 conformant. You must not +use this option unless you also specify \fB\-mtrap\-precision=i\fR and either +\&\fB\-mfp\-trap\-mode=su\fR or \fB\-mfp\-trap\-mode=sui\fR. Its only effect +is to emit the line \fB.eflag 48\fR in the function prologue of the +generated assembly file. Under \s-1DEC\s0 Unix, this has the effect that +IEEE-conformant math library routines will be linked in. +.IP "\fB\-mbuild\-constants\fR" 4 +.IX Item "-mbuild-constants" +Normally \s-1GCC\s0 examines a 32\- or 64\-bit integer constant to +see if it can construct it from smaller constants in two or three +instructions. If it cannot, it will output the constant as a literal and +generate code to load it from the data segment at runtime. +.Sp +Use this option to require \s-1GCC\s0 to construct \fIall\fR integer constants +using code, even if it takes more instructions (the maximum is six). +.Sp +You would typically use this option to build a shared library dynamic +loader. Itself a shared library, it must relocate itself in memory +before it can find the variables and constants in its own data segment. +.IP "\fB\-malpha\-as\fR" 4 +.IX Item "-malpha-as" +.PD 0 +.IP "\fB\-mgas\fR" 4 +.IX Item "-mgas" +.PD +Select whether to generate code to be assembled by the vendor-supplied +assembler (\fB\-malpha\-as\fR) or by the \s-1GNU\s0 assembler \fB\-mgas\fR. +.IP "\fB\-mbwx\fR" 4 +.IX Item "-mbwx" +.PD 0 +.IP "\fB\-mno\-bwx\fR" 4 +.IX Item "-mno-bwx" +.IP "\fB\-mcix\fR" 4 +.IX Item "-mcix" +.IP "\fB\-mno\-cix\fR" 4 +.IX Item "-mno-cix" +.IP "\fB\-mfix\fR" 4 +.IX Item "-mfix" +.IP "\fB\-mno\-fix\fR" 4 +.IX Item "-mno-fix" +.IP "\fB\-mmax\fR" 4 +.IX Item "-mmax" +.IP "\fB\-mno\-max\fR" 4 +.IX Item "-mno-max" +.PD +Indicate whether \s-1GCC\s0 should generate code to use the optional \s-1BWX\s0, +\&\s-1CIX\s0, \s-1FIX\s0 and \s-1MAX\s0 instruction sets. The default is to use the instruction +sets supported by the \s-1CPU\s0 type specified via \fB\-mcpu=\fR option or that +of the \s-1CPU\s0 on which \s-1GCC\s0 was built if none was specified. +.IP "\fB\-mfloat\-vax\fR" 4 +.IX Item "-mfloat-vax" +.PD 0 +.IP "\fB\-mfloat\-ieee\fR" 4 +.IX Item "-mfloat-ieee" +.PD +Generate code that uses (does not use) \s-1VAX\s0 F and G floating point +arithmetic instead of \s-1IEEE\s0 single and double precision. +.IP "\fB\-mexplicit\-relocs\fR" 4 +.IX Item "-mexplicit-relocs" +.PD 0 +.IP "\fB\-mno\-explicit\-relocs\fR" 4 +.IX Item "-mno-explicit-relocs" +.PD +Older Alpha assemblers provided no way to generate symbol relocations +except via assembler macros. Use of these macros does not allow +optimal instruction scheduling. \s-1GNU\s0 binutils as of version 2.12 +supports a new syntax that allows the compiler to explicitly mark +which relocations should apply to which instructions. This option +is mostly useful for debugging, as \s-1GCC\s0 detects the capabilities of +the assembler when it is built and sets the default accordingly. +.IP "\fB\-msmall\-data\fR" 4 +.IX Item "-msmall-data" +.PD 0 +.IP "\fB\-mlarge\-data\fR" 4 +.IX Item "-mlarge-data" +.PD +When \fB\-mexplicit\-relocs\fR is in effect, static data is +accessed via \fIgp-relative\fR relocations. When \fB\-msmall\-data\fR +is used, objects 8 bytes long or smaller are placed in a \fIsmall data area\fR +(the \f(CW\*(C`.sdata\*(C'\fR and \f(CW\*(C`.sbss\*(C'\fR sections) and are accessed via +16\-bit relocations off of the \f(CW$gp\fR register. This limits the +size of the small data area to 64KB, but allows the variables to be +directly accessed via a single instruction. +.Sp +The default is \fB\-mlarge\-data\fR. With this option the data area +is limited to just below 2GB. Programs that require more than 2GB of +data must use \f(CW\*(C`malloc\*(C'\fR or \f(CW\*(C`mmap\*(C'\fR to allocate the data in the +heap instead of in the program's data segment. +.Sp +When generating code for shared libraries, \fB\-fpic\fR implies +\&\fB\-msmall\-data\fR and \fB\-fPIC\fR implies \fB\-mlarge\-data\fR. +.IP "\fB\-msmall\-text\fR" 4 +.IX Item "-msmall-text" +.PD 0 +.IP "\fB\-mlarge\-text\fR" 4 +.IX Item "-mlarge-text" +.PD +When \fB\-msmall\-text\fR is used, the compiler assumes that the +code of the entire program (or shared library) fits in 4MB, and is +thus reachable with a branch instruction. When \fB\-msmall\-data\fR +is used, the compiler can assume that all local symbols share the +same \f(CW$gp\fR value, and thus reduce the number of instructions +required for a function call from 4 to 1. +.Sp +The default is \fB\-mlarge\-text\fR. +.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 +.IX Item "-mcpu=cpu_type" +Set the instruction set and instruction scheduling parameters for +machine type \fIcpu_type\fR. You can specify either the \fB\s-1EV\s0\fR +style name or the corresponding chip number. \s-1GCC\s0 supports scheduling +parameters for the \s-1EV4\s0, \s-1EV5\s0 and \s-1EV6\s0 family of processors and will +choose the default values for the instruction set from the processor +you specify. If you do not specify a processor type, \s-1GCC\s0 will default +to the processor on which the compiler was built. +.Sp +Supported values for \fIcpu_type\fR are +.RS 4 +.IP "\fBev4\fR" 4 +.IX Item "ev4" +.PD 0 +.IP "\fBev45\fR" 4 +.IX Item "ev45" +.IP "\fB21064\fR" 4 +.IX Item "21064" +.PD +Schedules as an \s-1EV4\s0 and has no instruction set extensions. +.IP "\fBev5\fR" 4 +.IX Item "ev5" +.PD 0 +.IP "\fB21164\fR" 4 +.IX Item "21164" +.PD +Schedules as an \s-1EV5\s0 and has no instruction set extensions. +.IP "\fBev56\fR" 4 +.IX Item "ev56" +.PD 0 +.IP "\fB21164a\fR" 4 +.IX Item "21164a" +.PD +Schedules as an \s-1EV5\s0 and supports the \s-1BWX\s0 extension. +.IP "\fBpca56\fR" 4 +.IX Item "pca56" +.PD 0 +.IP "\fB21164pc\fR" 4 +.IX Item "21164pc" +.IP "\fB21164PC\fR" 4 +.IX Item "21164PC" +.PD +Schedules as an \s-1EV5\s0 and supports the \s-1BWX\s0 and \s-1MAX\s0 extensions. +.IP "\fBev6\fR" 4 +.IX Item "ev6" +.PD 0 +.IP "\fB21264\fR" 4 +.IX Item "21264" +.PD +Schedules as an \s-1EV6\s0 and supports the \s-1BWX\s0, \s-1FIX\s0, and \s-1MAX\s0 extensions. +.IP "\fBev67\fR" 4 +.IX Item "ev67" +.PD 0 +.IP "\fB21264a\fR" 4 +.IX Item "21264a" +.PD +Schedules as an \s-1EV6\s0 and supports the \s-1BWX\s0, \s-1CIX\s0, \s-1FIX\s0, and \s-1MAX\s0 extensions. +.RE +.RS 4 +.Sp +Native Linux/GNU toolchains also support the value \fBnative\fR, +which selects the best architecture option for the host processor. +\&\fB\-mcpu=native\fR has no effect if \s-1GCC\s0 does not recognize +the processor. +.RE +.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4 +.IX Item "-mtune=cpu_type" +Set only the instruction scheduling parameters for machine type +\&\fIcpu_type\fR. The instruction set is not changed. +.Sp +Native Linux/GNU toolchains also support the value \fBnative\fR, +which selects the best architecture option for the host processor. +\&\fB\-mtune=native\fR has no effect if \s-1GCC\s0 does not recognize +the processor. +.IP "\fB\-mmemory\-latency=\fR\fItime\fR" 4 +.IX Item "-mmemory-latency=time" +Sets the latency the scheduler should assume for typical memory +references as seen by the application. This number is highly +dependent on the memory access patterns used by the application +and the size of the external cache on the machine. +.Sp +Valid options for \fItime\fR are +.RS 4 +.IP "\fInumber\fR" 4 +.IX Item "number" +A decimal number representing clock cycles. +.IP "\fBL1\fR" 4 +.IX Item "L1" +.PD 0 +.IP "\fBL2\fR" 4 +.IX Item "L2" +.IP "\fBL3\fR" 4 +.IX Item "L3" +.IP "\fBmain\fR" 4 +.IX Item "main" +.PD +The compiler contains estimates of the number of clock cycles for +\&\*(L"typical\*(R" \s-1EV4\s0 & \s-1EV5\s0 hardware for the Level 1, 2 & 3 caches +(also called Dcache, Scache, and Bcache), as well as to main memory. +Note that L3 is only valid for \s-1EV5\s0. +.RE +.RS 4 +.RE +.PP +\fI\s-1DEC\s0 Alpha/VMS Options\fR +.IX Subsection "DEC Alpha/VMS Options" +.PP +These \fB\-m\fR options are defined for the \s-1DEC\s0 Alpha/VMS implementations: +.IP "\fB\-mvms\-return\-codes\fR" 4 +.IX Item "-mvms-return-codes" +Return \s-1VMS\s0 condition codes from main. The default is to return \s-1POSIX\s0 +style condition (e.g. error) codes. +.IP "\fB\-mdebug\-main=\fR\fIprefix\fR" 4 +.IX Item "-mdebug-main=prefix" +Flag the first routine whose name starts with \fIprefix\fR as the main +routine for the debugger. +.IP "\fB\-mmalloc64\fR" 4 +.IX Item "-mmalloc64" +Default to 64bit memory allocation routines. +.PP +\fI\s-1FR30\s0 Options\fR +.IX Subsection "FR30 Options" +.PP +These options are defined specifically for the \s-1FR30\s0 port. +.IP "\fB\-msmall\-model\fR" 4 +.IX Item "-msmall-model" +Use the small address space model. This can produce smaller code, but +it does assume that all symbolic values and addresses will fit into a +20\-bit range. +.IP "\fB\-mno\-lsim\fR" 4 +.IX Item "-mno-lsim" +Assume that run-time support has been provided and so there is no need +to include the simulator library (\fIlibsim.a\fR) on the linker +command line. +.PP +\fI\s-1FRV\s0 Options\fR +.IX Subsection "FRV Options" +.IP "\fB\-mgpr\-32\fR" 4 +.IX Item "-mgpr-32" +Only use the first 32 general purpose registers. +.IP "\fB\-mgpr\-64\fR" 4 +.IX Item "-mgpr-64" +Use all 64 general purpose registers. +.IP "\fB\-mfpr\-32\fR" 4 +.IX Item "-mfpr-32" +Use only the first 32 floating point registers. +.IP "\fB\-mfpr\-64\fR" 4 +.IX Item "-mfpr-64" +Use all 64 floating point registers +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +Use hardware instructions for floating point operations. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Use library routines for floating point operations. +.IP "\fB\-malloc\-cc\fR" 4 +.IX Item "-malloc-cc" +Dynamically allocate condition code registers. +.IP "\fB\-mfixed\-cc\fR" 4 +.IX Item "-mfixed-cc" +Do not try to dynamically allocate condition code registers, only +use \f(CW\*(C`icc0\*(C'\fR and \f(CW\*(C`fcc0\*(C'\fR. +.IP "\fB\-mdword\fR" 4 +.IX Item "-mdword" +Change \s-1ABI\s0 to use double word insns. +.IP "\fB\-mno\-dword\fR" 4 +.IX Item "-mno-dword" +Do not use double word instructions. +.IP "\fB\-mdouble\fR" 4 +.IX Item "-mdouble" +Use floating point double instructions. +.IP "\fB\-mno\-double\fR" 4 +.IX Item "-mno-double" +Do not use floating point double instructions. +.IP "\fB\-mmedia\fR" 4 +.IX Item "-mmedia" +Use media instructions. +.IP "\fB\-mno\-media\fR" 4 +.IX Item "-mno-media" +Do not use media instructions. +.IP "\fB\-mmuladd\fR" 4 +.IX Item "-mmuladd" +Use multiply and add/subtract instructions. +.IP "\fB\-mno\-muladd\fR" 4 +.IX Item "-mno-muladd" +Do not use multiply and add/subtract instructions. +.IP "\fB\-mfdpic\fR" 4 +.IX Item "-mfdpic" +Select the \s-1FDPIC\s0 \s-1ABI\s0, that uses function descriptors to represent +pointers to functions. Without any PIC/PIE\-related options, it +implies \fB\-fPIE\fR. With \fB\-fpic\fR or \fB\-fpie\fR, it +assumes \s-1GOT\s0 entries and small data are within a 12\-bit range from the +\&\s-1GOT\s0 base address; with \fB\-fPIC\fR or \fB\-fPIE\fR, \s-1GOT\s0 offsets +are computed with 32 bits. +With a \fBbfin-elf\fR target, this option implies \fB\-msim\fR. +.IP "\fB\-minline\-plt\fR" 4 +.IX Item "-minline-plt" +Enable inlining of \s-1PLT\s0 entries in function calls to functions that are +not known to bind locally. It has no effect without \fB\-mfdpic\fR. +It's enabled by default if optimizing for speed and compiling for +shared libraries (i.e., \fB\-fPIC\fR or \fB\-fpic\fR), or when an +optimization option such as \fB\-O3\fR or above is present in the +command line. +.IP "\fB\-mTLS\fR" 4 +.IX Item "-mTLS" +Assume a large \s-1TLS\s0 segment when generating thread-local code. +.IP "\fB\-mtls\fR" 4 +.IX Item "-mtls" +Do not assume a large \s-1TLS\s0 segment when generating thread-local code. +.IP "\fB\-mgprel\-ro\fR" 4 +.IX Item "-mgprel-ro" +Enable the use of \f(CW\*(C`GPREL\*(C'\fR relocations in the \s-1FDPIC\s0 \s-1ABI\s0 for data +that is known to be in read-only sections. It's enabled by default, +except for \fB\-fpic\fR or \fB\-fpie\fR: even though it may help +make the global offset table smaller, it trades 1 instruction for 4. +With \fB\-fPIC\fR or \fB\-fPIE\fR, it trades 3 instructions for 4, +one of which may be shared by multiple symbols, and it avoids the need +for a \s-1GOT\s0 entry for the referenced symbol, so it's more likely to be a +win. If it is not, \fB\-mno\-gprel\-ro\fR can be used to disable it. +.IP "\fB\-multilib\-library\-pic\fR" 4 +.IX Item "-multilib-library-pic" +Link with the (library, not \s-1FD\s0) pic libraries. It's implied by +\&\fB\-mlibrary\-pic\fR, as well as by \fB\-fPIC\fR and +\&\fB\-fpic\fR without \fB\-mfdpic\fR. You should never have to use +it explicitly. +.IP "\fB\-mlinked\-fp\fR" 4 +.IX Item "-mlinked-fp" +Follow the \s-1EABI\s0 requirement of always creating a frame pointer whenever +a stack frame is allocated. This option is enabled by default and can +be disabled with \fB\-mno\-linked\-fp\fR. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +Use indirect addressing to call functions outside the current +compilation unit. This allows the functions to be placed anywhere +within the 32\-bit address space. +.IP "\fB\-malign\-labels\fR" 4 +.IX Item "-malign-labels" +Try to align labels to an 8\-byte boundary by inserting nops into the +previous packet. This option only has an effect when \s-1VLIW\s0 packing +is enabled. It doesn't create new packets; it merely adds nops to +existing ones. +.IP "\fB\-mlibrary\-pic\fR" 4 +.IX Item "-mlibrary-pic" +Generate position-independent \s-1EABI\s0 code. +.IP "\fB\-macc\-4\fR" 4 +.IX Item "-macc-4" +Use only the first four media accumulator registers. +.IP "\fB\-macc\-8\fR" 4 +.IX Item "-macc-8" +Use all eight media accumulator registers. +.IP "\fB\-mpack\fR" 4 +.IX Item "-mpack" +Pack \s-1VLIW\s0 instructions. +.IP "\fB\-mno\-pack\fR" 4 +.IX Item "-mno-pack" +Do not pack \s-1VLIW\s0 instructions. +.IP "\fB\-mno\-eflags\fR" 4 +.IX Item "-mno-eflags" +Do not mark \s-1ABI\s0 switches in e_flags. +.IP "\fB\-mcond\-move\fR" 4 +.IX Item "-mcond-move" +Enable the use of conditional-move instructions (default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-cond\-move\fR" 4 +.IX Item "-mno-cond-move" +Disable the use of conditional-move instructions. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mscc\fR" 4 +.IX Item "-mscc" +Enable the use of conditional set instructions (default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-scc\fR" 4 +.IX Item "-mno-scc" +Disable the use of conditional set instructions. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mcond\-exec\fR" 4 +.IX Item "-mcond-exec" +Enable the use of conditional execution (default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-cond\-exec\fR" 4 +.IX Item "-mno-cond-exec" +Disable the use of conditional execution. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mvliw\-branch\fR" 4 +.IX Item "-mvliw-branch" +Run a pass to pack branches into \s-1VLIW\s0 instructions (default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-vliw\-branch\fR" 4 +.IX Item "-mno-vliw-branch" +Do not run a pass to pack branches into \s-1VLIW\s0 instructions. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mmulti\-cond\-exec\fR" 4 +.IX Item "-mmulti-cond-exec" +Enable optimization of \f(CW\*(C`&&\*(C'\fR and \f(CW\*(C`||\*(C'\fR in conditional execution +(default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-multi\-cond\-exec\fR" 4 +.IX Item "-mno-multi-cond-exec" +Disable optimization of \f(CW\*(C`&&\*(C'\fR and \f(CW\*(C`||\*(C'\fR in conditional execution. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mnested\-cond\-exec\fR" 4 +.IX Item "-mnested-cond-exec" +Enable nested conditional execution optimizations (default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-nested\-cond\-exec\fR" 4 +.IX Item "-mno-nested-cond-exec" +Disable nested conditional execution optimizations. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-moptimize\-membar\fR" 4 +.IX Item "-moptimize-membar" +This switch removes redundant \f(CW\*(C`membar\*(C'\fR instructions from the +compiler generated code. It is enabled by default. +.IP "\fB\-mno\-optimize\-membar\fR" 4 +.IX Item "-mno-optimize-membar" +This switch disables the automatic removal of redundant \f(CW\*(C`membar\*(C'\fR +instructions from the generated code. +.IP "\fB\-mtomcat\-stats\fR" 4 +.IX Item "-mtomcat-stats" +Cause gas to print out tomcat statistics. +.IP "\fB\-mcpu=\fR\fIcpu\fR" 4 +.IX Item "-mcpu=cpu" +Select the processor type for which to generate code. Possible values are +\&\fBfrv\fR, \fBfr550\fR, \fBtomcat\fR, \fBfr500\fR, \fBfr450\fR, +\&\fBfr405\fR, \fBfr400\fR, \fBfr300\fR and \fBsimple\fR. +.PP +\fIGNU/Linux Options\fR +.IX Subsection "GNU/Linux Options" +.PP +These \fB\-m\fR options are defined for GNU/Linux targets: +.IP "\fB\-mglibc\fR" 4 +.IX Item "-mglibc" +Use the \s-1GNU\s0 C library. This is the default except +on \fB*\-*\-linux\-*uclibc*\fR and \fB*\-*\-linux\-*android*\fR targets. +.IP "\fB\-muclibc\fR" 4 +.IX Item "-muclibc" +Use uClibc C library. This is the default on +\&\fB*\-*\-linux\-*uclibc*\fR targets. +.IP "\fB\-mbionic\fR" 4 +.IX Item "-mbionic" +Use Bionic C library. This is the default on +\&\fB*\-*\-linux\-*android*\fR targets. +.IP "\fB\-mandroid\fR" 4 +.IX Item "-mandroid" +Compile code compatible with Android platform. This is the default on +\&\fB*\-*\-linux\-*android*\fR targets. +.Sp +When compiling, this option enables \fB\-mbionic\fR, \fB\-fPIC\fR, +\&\fB\-fno\-exceptions\fR and \fB\-fno\-rtti\fR by default. When linking, +this option makes the \s-1GCC\s0 driver pass Android-specific options to the linker. +Finally, this option causes the preprocessor macro \f(CW\*(C`_\|_ANDROID_\|_\*(C'\fR +to be defined. +.IP "\fB\-tno\-android\-cc\fR" 4 +.IX Item "-tno-android-cc" +Disable compilation effects of \fB\-mandroid\fR, i.e., do not enable +\&\fB\-mbionic\fR, \fB\-fPIC\fR, \fB\-fno\-exceptions\fR and +\&\fB\-fno\-rtti\fR by default. +.IP "\fB\-tno\-android\-ld\fR" 4 +.IX Item "-tno-android-ld" +Disable linking effects of \fB\-mandroid\fR, i.e., pass standard Linux +linking options to the linker. +.PP +\fIH8/300 Options\fR +.IX Subsection "H8/300 Options" +.PP +These \fB\-m\fR options are defined for the H8/300 implementations: +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +Shorten some address references at link time, when possible; uses the +linker option \fB\-relax\fR. +.IP "\fB\-mh\fR" 4 +.IX Item "-mh" +Generate code for the H8/300H. +.IP "\fB\-ms\fR" 4 +.IX Item "-ms" +Generate code for the H8S. +.IP "\fB\-mn\fR" 4 +.IX Item "-mn" +Generate code for the H8S and H8/300H in the normal mode. This switch +must be used either with \fB\-mh\fR or \fB\-ms\fR. +.IP "\fB\-ms2600\fR" 4 +.IX Item "-ms2600" +Generate code for the H8S/2600. This switch must be used with \fB\-ms\fR. +.IP "\fB\-mint32\fR" 4 +.IX Item "-mint32" +Make \f(CW\*(C`int\*(C'\fR data 32 bits by default. +.IP "\fB\-malign\-300\fR" 4 +.IX Item "-malign-300" +On the H8/300H and H8S, use the same alignment rules as for the H8/300. +The default for the H8/300H and H8S is to align longs and floats on 4 +byte boundaries. +\&\fB\-malign\-300\fR causes them to be aligned on 2 byte boundaries. +This option has no effect on the H8/300. +.PP +\fI\s-1HPPA\s0 Options\fR +.IX Subsection "HPPA Options" +.PP +These \fB\-m\fR options are defined for the \s-1HPPA\s0 family of computers: +.IP "\fB\-march=\fR\fIarchitecture-type\fR" 4 +.IX Item "-march=architecture-type" +Generate code for the specified architecture. The choices for +\&\fIarchitecture-type\fR are \fB1.0\fR for \s-1PA\s0 1.0, \fB1.1\fR for \s-1PA\s0 +1.1, and \fB2.0\fR for \s-1PA\s0 2.0 processors. Refer to +\&\fI/usr/lib/sched.models\fR on an HP-UX system to determine the proper +architecture option for your machine. Code compiled for lower numbered +architectures will run on higher numbered architectures, but not the +other way around. +.IP "\fB\-mpa\-risc\-1\-0\fR" 4 +.IX Item "-mpa-risc-1-0" +.PD 0 +.IP "\fB\-mpa\-risc\-1\-1\fR" 4 +.IX Item "-mpa-risc-1-1" +.IP "\fB\-mpa\-risc\-2\-0\fR" 4 +.IX Item "-mpa-risc-2-0" +.PD +Synonyms for \fB\-march=1.0\fR, \fB\-march=1.1\fR, and \fB\-march=2.0\fR respectively. +.IP "\fB\-mbig\-switch\fR" 4 +.IX Item "-mbig-switch" +Generate code suitable for big switch tables. Use this option only if +the assembler/linker complain about out of range branches within a switch +table. +.IP "\fB\-mjump\-in\-delay\fR" 4 +.IX Item "-mjump-in-delay" +Fill delay slots of function calls with unconditional jump instructions +by modifying the return pointer for the function call to be the target +of the conditional jump. +.IP "\fB\-mdisable\-fpregs\fR" 4 +.IX Item "-mdisable-fpregs" +Prevent floating point registers from being used in any manner. This is +necessary for compiling kernels which perform lazy context switching of +floating point registers. If you use this option and attempt to perform +floating point operations, the compiler will abort. +.IP "\fB\-mdisable\-indexing\fR" 4 +.IX Item "-mdisable-indexing" +Prevent the compiler from using indexing address modes. This avoids some +rather obscure problems when compiling \s-1MIG\s0 generated code under \s-1MACH\s0. +.IP "\fB\-mno\-space\-regs\fR" 4 +.IX Item "-mno-space-regs" +Generate code that assumes the target has no space registers. This allows +\&\s-1GCC\s0 to generate faster indirect calls and use unscaled index address modes. +.Sp +Such code is suitable for level 0 \s-1PA\s0 systems and kernels. +.IP "\fB\-mfast\-indirect\-calls\fR" 4 +.IX Item "-mfast-indirect-calls" +Generate code that assumes calls never cross space boundaries. This +allows \s-1GCC\s0 to emit code which performs faster indirect calls. +.Sp +This option will not work in the presence of shared libraries or nested +functions. +.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 +.IX Item "-mfixed-range=register-range" +Generate code treating the given register range as fixed registers. +A fixed register is one that the register allocator can not use. This is +useful when compiling kernel code. A register range is specified as +two registers separated by a dash. Multiple register ranges can be +specified separated by a comma. +.IP "\fB\-mlong\-load\-store\fR" 4 +.IX Item "-mlong-load-store" +Generate 3\-instruction load and store sequences as sometimes required by +the HP-UX 10 linker. This is equivalent to the \fB+k\fR option to +the \s-1HP\s0 compilers. +.IP "\fB\-mportable\-runtime\fR" 4 +.IX Item "-mportable-runtime" +Use the portable calling conventions proposed by \s-1HP\s0 for \s-1ELF\s0 systems. +.IP "\fB\-mgas\fR" 4 +.IX Item "-mgas" +Enable the use of assembler directives only \s-1GAS\s0 understands. +.IP "\fB\-mschedule=\fR\fIcpu-type\fR" 4 +.IX Item "-mschedule=cpu-type" +Schedule code according to the constraints for the machine type +\&\fIcpu-type\fR. The choices for \fIcpu-type\fR are \fB700\fR +\&\fB7100\fR, \fB7100LC\fR, \fB7200\fR, \fB7300\fR and \fB8000\fR. Refer +to \fI/usr/lib/sched.models\fR on an HP-UX system to determine the +proper scheduling option for your machine. The default scheduling is +\&\fB8000\fR. +.IP "\fB\-mlinker\-opt\fR" 4 +.IX Item "-mlinker-opt" +Enable the optimization pass in the HP-UX linker. Note this makes symbolic +debugging impossible. It also triggers a bug in the HP-UX 8 and HP-UX 9 +linkers in which they give bogus error messages when linking some programs. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Generate output containing library calls for floating point. +\&\fBWarning:\fR the requisite libraries are not available for all \s-1HPPA\s0 +targets. Normally the facilities of the machine's usual C compiler are +used, but this cannot be done directly in cross-compilation. You must make +your own arrangements to provide suitable library functions for +cross-compilation. +.Sp +\&\fB\-msoft\-float\fR changes the calling convention in the output file; +therefore, it is only useful if you compile \fIall\fR of a program with +this option. In particular, you need to compile \fIlibgcc.a\fR, the +library that comes with \s-1GCC\s0, with \fB\-msoft\-float\fR in order for +this to work. +.IP "\fB\-msio\fR" 4 +.IX Item "-msio" +Generate the predefine, \f(CW\*(C`_SIO\*(C'\fR, for server \s-1IO\s0. The default is +\&\fB\-mwsio\fR. This generates the predefines, \f(CW\*(C`_\|_hp9000s700\*(C'\fR, +\&\f(CW\*(C`_\|_hp9000s700_\|_\*(C'\fR and \f(CW\*(C`_WSIO\*(C'\fR, for workstation \s-1IO\s0. These +options are available under HP-UX and HI-UX. +.IP "\fB\-mgnu\-ld\fR" 4 +.IX Item "-mgnu-ld" +Use \s-1GNU\s0 ld specific options. This passes \fB\-shared\fR to ld when +building a shared library. It is the default when \s-1GCC\s0 is configured, +explicitly or implicitly, with the \s-1GNU\s0 linker. This option does not +have any affect on which ld is called, it only changes what parameters +are passed to that ld. The ld that is called is determined by the +\&\fB\-\-with\-ld\fR configure option, \s-1GCC\s0's program search path, and +finally by the user's \fB\s-1PATH\s0\fR. The linker used by \s-1GCC\s0 can be printed +using \fBwhich `gcc \-print\-prog\-name=ld`\fR. This option is only available +on the 64 bit HP-UX \s-1GCC\s0, i.e. configured with \fBhppa*64*\-*\-hpux*\fR. +.IP "\fB\-mhp\-ld\fR" 4 +.IX Item "-mhp-ld" +Use \s-1HP\s0 ld specific options. This passes \fB\-b\fR to ld when building +a shared library and passes \fB+Accept TypeMismatch\fR to ld on all +links. It is the default when \s-1GCC\s0 is configured, explicitly or +implicitly, with the \s-1HP\s0 linker. This option does not have any affect on +which ld is called, it only changes what parameters are passed to that +ld. The ld that is called is determined by the \fB\-\-with\-ld\fR +configure option, \s-1GCC\s0's program search path, and finally by the user's +\&\fB\s-1PATH\s0\fR. The linker used by \s-1GCC\s0 can be printed using \fBwhich +`gcc \-print\-prog\-name=ld`\fR. This option is only available on the 64 bit +HP-UX \s-1GCC\s0, i.e. configured with \fBhppa*64*\-*\-hpux*\fR. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +Generate code that uses long call sequences. This ensures that a call +is always able to reach linker generated stubs. The default is to generate +long calls only when the distance from the call site to the beginning +of the function or translation unit, as the case may be, exceeds a +predefined limit set by the branch type being used. The limits for +normal calls are 7,600,000 and 240,000 bytes, respectively for the +\&\s-1PA\s0 2.0 and \s-1PA\s0 1.X architectures. Sibcalls are always limited at +240,000 bytes. +.Sp +Distances are measured from the beginning of functions when using the +\&\fB\-ffunction\-sections\fR option, or when using the \fB\-mgas\fR +and \fB\-mno\-portable\-runtime\fR options together under HP-UX with +the \s-1SOM\s0 linker. +.Sp +It is normally not desirable to use this option as it will degrade +performance. However, it may be useful in large applications, +particularly when partial linking is used to build the application. +.Sp +The types of long calls used depends on the capabilities of the +assembler and linker, and the type of code being generated. The +impact on systems that support long absolute calls, and long pic +symbol-difference or pc-relative calls should be relatively small. +However, an indirect call is used on 32\-bit \s-1ELF\s0 systems in pic code +and it is quite long. +.IP "\fB\-munix=\fR\fIunix-std\fR" 4 +.IX Item "-munix=unix-std" +Generate compiler predefines and select a startfile for the specified +\&\s-1UNIX\s0 standard. The choices for \fIunix-std\fR are \fB93\fR, \fB95\fR +and \fB98\fR. \fB93\fR is supported on all HP-UX versions. \fB95\fR +is available on HP-UX 10.10 and later. \fB98\fR is available on HP-UX +11.11 and later. The default values are \fB93\fR for HP-UX 10.00, +\&\fB95\fR for HP-UX 10.10 though to 11.00, and \fB98\fR for HP-UX 11.11 +and later. +.Sp +\&\fB\-munix=93\fR provides the same predefines as \s-1GCC\s0 3.3 and 3.4. +\&\fB\-munix=95\fR provides additional predefines for \f(CW\*(C`XOPEN_UNIX\*(C'\fR +and \f(CW\*(C`_XOPEN_SOURCE_EXTENDED\*(C'\fR, and the startfile \fIunix95.o\fR. +\&\fB\-munix=98\fR provides additional predefines for \f(CW\*(C`_XOPEN_UNIX\*(C'\fR, +\&\f(CW\*(C`_XOPEN_SOURCE_EXTENDED\*(C'\fR, \f(CW\*(C`_INCLUDE_\|_STDC_A1_SOURCE\*(C'\fR and +\&\f(CW\*(C`_INCLUDE_XOPEN_SOURCE_500\*(C'\fR, and the startfile \fIunix98.o\fR. +.Sp +It is \fIimportant\fR to note that this option changes the interfaces +for various library routines. It also affects the operational behavior +of the C library. Thus, \fIextreme\fR care is needed in using this +option. +.Sp +Library code that is intended to operate with more than one \s-1UNIX\s0 +standard must test, set and restore the variable \fI_\|_xpg4_extended_mask\fR +as appropriate. Most \s-1GNU\s0 software doesn't provide this capability. +.IP "\fB\-nolibdld\fR" 4 +.IX Item "-nolibdld" +Suppress the generation of link options to search libdld.sl when the +\&\fB\-static\fR option is specified on HP-UX 10 and later. +.IP "\fB\-static\fR" 4 +.IX Item "-static" +The HP-UX implementation of setlocale in libc has a dependency on +libdld.sl. There isn't an archive version of libdld.sl. Thus, +when the \fB\-static\fR option is specified, special link options +are needed to resolve this dependency. +.Sp +On HP-UX 10 and later, the \s-1GCC\s0 driver adds the necessary options to +link with libdld.sl when the \fB\-static\fR option is specified. +This causes the resulting binary to be dynamic. On the 64\-bit port, +the linkers generate dynamic binaries by default in any case. The +\&\fB\-nolibdld\fR option can be used to prevent the \s-1GCC\s0 driver from +adding these link options. +.IP "\fB\-threads\fR" 4 +.IX Item "-threads" +Add support for multithreading with the \fIdce thread\fR library +under HP-UX. This option sets flags for both the preprocessor and +linker. +.PP +\fIIntel 386 and \s-1AMD\s0 x86\-64 Options\fR +.IX Subsection "Intel 386 and AMD x86-64 Options" +.PP +These \fB\-m\fR options are defined for the i386 and x86\-64 family of +computers: +.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 +.IX Item "-mtune=cpu-type" +Tune to \fIcpu-type\fR everything applicable about the generated code, except +for the \s-1ABI\s0 and the set of available instructions. The choices for +\&\fIcpu-type\fR are: +.RS 4 +.IP "\fIgeneric\fR" 4 +.IX Item "generic" +Produce code optimized for the most common \s-1IA32/AMD64/EM64T\s0 processors. +If you know the \s-1CPU\s0 on which your code will run, then you should use +the corresponding \fB\-mtune\fR option instead of +\&\fB\-mtune=generic\fR. But, if you do not know exactly what \s-1CPU\s0 users +of your application will have, then you should use this option. +.Sp +As new processors are deployed in the marketplace, the behavior of this +option will change. Therefore, if you upgrade to a newer version of +\&\s-1GCC\s0, the code generated option will change to reflect the processors +that were most common when that version of \s-1GCC\s0 was released. +.Sp +There is no \fB\-march=generic\fR option because \fB\-march\fR +indicates the instruction set the compiler can use, and there is no +generic instruction set applicable to all processors. In contrast, +\&\fB\-mtune\fR indicates the processor (or, in this case, collection of +processors) for which the code is optimized. +.IP "\fInative\fR" 4 +.IX Item "native" +This selects the \s-1CPU\s0 to tune for at compilation time by determining +the processor type of the compiling machine. Using \fB\-mtune=native\fR +will produce code optimized for the local machine under the constraints +of the selected instruction set. Using \fB\-march=native\fR will +enable all instruction subsets supported by the local machine (hence +the result might not run on different machines). +.IP "\fIi386\fR" 4 +.IX Item "i386" +Original Intel's i386 \s-1CPU\s0. +.IP "\fIi486\fR" 4 +.IX Item "i486" +Intel's i486 \s-1CPU\s0. (No scheduling is implemented for this chip.) +.IP "\fIi586, pentium\fR" 4 +.IX Item "i586, pentium" +Intel Pentium \s-1CPU\s0 with no \s-1MMX\s0 support. +.IP "\fIpentium-mmx\fR" 4 +.IX Item "pentium-mmx" +Intel PentiumMMX \s-1CPU\s0 based on Pentium core with \s-1MMX\s0 instruction set support. +.IP "\fIpentiumpro\fR" 4 +.IX Item "pentiumpro" +Intel PentiumPro \s-1CPU\s0. +.IP "\fIi686\fR" 4 +.IX Item "i686" +Same as \f(CW\*(C`generic\*(C'\fR, but when used as \f(CW\*(C`march\*(C'\fR option, PentiumPro +instruction set will be used, so the code will run on all i686 family chips. +.IP "\fIpentium2\fR" 4 +.IX Item "pentium2" +Intel Pentium2 \s-1CPU\s0 based on PentiumPro core with \s-1MMX\s0 instruction set support. +.IP "\fIpentium3, pentium3m\fR" 4 +.IX Item "pentium3, pentium3m" +Intel Pentium3 \s-1CPU\s0 based on PentiumPro core with \s-1MMX\s0 and \s-1SSE\s0 instruction set +support. +.IP "\fIpentium-m\fR" 4 +.IX Item "pentium-m" +Low power version of Intel Pentium3 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0 and \s-1SSE2\s0 instruction set +support. Used by Centrino notebooks. +.IP "\fIpentium4, pentium4m\fR" 4 +.IX Item "pentium4, pentium4m" +Intel Pentium4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0 and \s-1SSE2\s0 instruction set support. +.IP "\fIprescott\fR" 4 +.IX Item "prescott" +Improved version of Intel Pentium4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0 and \s-1SSE3\s0 instruction +set support. +.IP "\fInocona\fR" 4 +.IX Item "nocona" +Improved version of Intel Pentium4 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, +\&\s-1SSE2\s0 and \s-1SSE3\s0 instruction set support. +.IP "\fIcore2\fR" 4 +.IX Item "core2" +Intel Core2 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0 +instruction set support. +.IP "\fIcorei7\fR" 4 +.IX Item "corei7" +Intel Core i7 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, \s-1SSE4\s0.1 +and \s-1SSE4\s0.2 instruction set support. +.IP "\fIcorei7\-avx\fR" 4 +.IX Item "corei7-avx" +Intel Core i7 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, +\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1AVX\s0, \s-1AES\s0 and \s-1PCLMUL\s0 instruction set support. +.IP "\fIcore-avx-i\fR" 4 +.IX Item "core-avx-i" +Intel Core \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, +\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1AVX\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0 and F16C instruction +set support. +.IP "\fIatom\fR" 4 +.IX Item "atom" +Intel Atom \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0 +instruction set support. +.IP "\fIk6\fR" 4 +.IX Item "k6" +\&\s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 instruction set support. +.IP "\fIk6\-2, k6\-3\fR" 4 +.IX Item "k6-2, k6-3" +Improved versions of \s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. +.IP "\fIathlon, athlon-tbird\fR" 4 +.IX Item "athlon, athlon-tbird" +\&\s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX\s0, 3dNOW!, enhanced 3DNow! and \s-1SSE\s0 prefetch instructions +support. +.IP "\fIathlon\-4, athlon-xp, athlon-mp\fR" 4 +.IX Item "athlon-4, athlon-xp, athlon-mp" +Improved \s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX\s0, 3DNow!, enhanced 3DNow! and full \s-1SSE\s0 +instruction set support. +.IP "\fIk8, opteron, athlon64, athlon-fx\fR" 4 +.IX Item "k8, opteron, athlon64, athlon-fx" +\&\s-1AMD\s0 K8 core based CPUs with x86\-64 instruction set support. (This supersets +\&\s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, 3DNow!, enhanced 3DNow! and 64\-bit instruction set extensions.) +.IP "\fIk8\-sse3, opteron\-sse3, athlon64\-sse3\fR" 4 +.IX Item "k8-sse3, opteron-sse3, athlon64-sse3" +Improved versions of k8, opteron and athlon64 with \s-1SSE3\s0 instruction set support. +.IP "\fIamdfam10, barcelona\fR" 4 +.IX Item "amdfam10, barcelona" +\&\s-1AMD\s0 Family 10h core based CPUs with x86\-64 instruction set support. (This +supersets \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSE4A\s0, 3DNow!, enhanced 3DNow!, \s-1ABM\s0 and 64\-bit +instruction set extensions.) +.IP "\fIwinchip\-c6\fR" 4 +.IX Item "winchip-c6" +\&\s-1IDT\s0 Winchip C6 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 instruction +set support. +.IP "\fIwinchip2\fR" 4 +.IX Item "winchip2" +\&\s-1IDT\s0 Winchip2 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 and 3DNow! +instruction set support. +.IP "\fIc3\fR" 4 +.IX Item "c3" +Via C3 \s-1CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. (No scheduling is +implemented for this chip.) +.IP "\fIc3\-2\fR" 4 +.IX Item "c3-2" +Via C3\-2 \s-1CPU\s0 with \s-1MMX\s0 and \s-1SSE\s0 instruction set support. (No scheduling is +implemented for this chip.) +.IP "\fIgeode\fR" 4 +.IX Item "geode" +Embedded \s-1AMD\s0 \s-1CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. +.RE +.RS 4 +.Sp +While picking a specific \fIcpu-type\fR will schedule things appropriately +for that particular chip, the compiler will not generate any code that +does not run on the i386 without the \fB\-march=\fR\fIcpu-type\fR option +being used. +.RE +.IP "\fB\-march=\fR\fIcpu-type\fR" 4 +.IX Item "-march=cpu-type" +Generate instructions for the machine type \fIcpu-type\fR. The choices +for \fIcpu-type\fR are the same as for \fB\-mtune\fR. Moreover, +specifying \fB\-march=\fR\fIcpu-type\fR implies \fB\-mtune=\fR\fIcpu-type\fR. +.IP "\fB\-mcpu=\fR\fIcpu-type\fR" 4 +.IX Item "-mcpu=cpu-type" +A deprecated synonym for \fB\-mtune\fR. +.IP "\fB\-mfpmath=\fR\fIunit\fR" 4 +.IX Item "-mfpmath=unit" +Generate floating point arithmetics for selected unit \fIunit\fR. The choices +for \fIunit\fR are: +.RS 4 +.IP "\fB387\fR" 4 +.IX Item "387" +Use the standard 387 floating point coprocessor present majority of chips and +emulated otherwise. Code compiled with this option will run almost everywhere. +The temporary results are computed in 80bit precision instead of precision +specified by the type resulting in slightly different results compared to most +of other chips. See \fB\-ffloat\-store\fR for more detailed description. +.Sp +This is the default choice for i386 compiler. +.IP "\fBsse\fR" 4 +.IX Item "sse" +Use scalar floating point instructions present in the \s-1SSE\s0 instruction set. +This instruction set is supported by Pentium3 and newer chips, in the \s-1AMD\s0 line +by Athlon\-4, Athlon-xp and Athlon-mp chips. The earlier version of \s-1SSE\s0 +instruction set supports only single precision arithmetics, thus the double and +extended precision arithmetics is still done using 387. Later version, present +only in Pentium4 and the future \s-1AMD\s0 x86\-64 chips supports double precision +arithmetics too. +.Sp +For the i386 compiler, you need to use \fB\-march=\fR\fIcpu-type\fR, \fB\-msse\fR +or \fB\-msse2\fR switches to enable \s-1SSE\s0 extensions and make this option +effective. For the x86\-64 compiler, these extensions are enabled by default. +.Sp +The resulting code should be considerably faster in the majority of cases and avoid +the numerical instability problems of 387 code, but may break some existing +code that expects temporaries to be 80bit. +.Sp +This is the default choice for the x86\-64 compiler. +.IP "\fBsse,387\fR" 4 +.IX Item "sse,387" +.PD 0 +.IP "\fBsse+387\fR" 4 +.IX Item "sse+387" +.IP "\fBboth\fR" 4 +.IX Item "both" +.PD +Attempt to utilize both instruction sets at once. This effectively double the +amount of available registers and on chips with separate execution units for +387 and \s-1SSE\s0 the execution resources too. Use this option with care, as it is +still experimental, because the \s-1GCC\s0 register allocator does not model separate +functional units well resulting in instable performance. +.RE +.RS 4 +.RE +.IP "\fB\-masm=\fR\fIdialect\fR" 4 +.IX Item "-masm=dialect" +Output asm instructions using selected \fIdialect\fR. Supported +choices are \fBintel\fR or \fBatt\fR (the default one). Darwin does +not support \fBintel\fR. +.IP "\fB\-mieee\-fp\fR" 4 +.IX Item "-mieee-fp" +.PD 0 +.IP "\fB\-mno\-ieee\-fp\fR" 4 +.IX Item "-mno-ieee-fp" +.PD +Control whether or not the compiler uses \s-1IEEE\s0 floating point +comparisons. These handle correctly the case where the result of a +comparison is unordered. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Generate output containing library calls for floating point. +\&\fBWarning:\fR the requisite libraries are not part of \s-1GCC\s0. +Normally the facilities of the machine's usual C compiler are used, but +this can't be done directly in cross-compilation. You must make your +own arrangements to provide suitable library functions for +cross-compilation. +.Sp +On machines where a function returns floating point results in the 80387 +register stack, some floating point opcodes may be emitted even if +\&\fB\-msoft\-float\fR is used. +.IP "\fB\-mno\-fp\-ret\-in\-387\fR" 4 +.IX Item "-mno-fp-ret-in-387" +Do not use the \s-1FPU\s0 registers for return values of functions. +.Sp +The usual calling convention has functions return values of types +\&\f(CW\*(C`float\*(C'\fR and \f(CW\*(C`double\*(C'\fR in an \s-1FPU\s0 register, even if there +is no \s-1FPU\s0. The idea is that the operating system should emulate +an \s-1FPU\s0. +.Sp +The option \fB\-mno\-fp\-ret\-in\-387\fR causes such values to be returned +in ordinary \s-1CPU\s0 registers instead. +.IP "\fB\-mno\-fancy\-math\-387\fR" 4 +.IX Item "-mno-fancy-math-387" +Some 387 emulators do not support the \f(CW\*(C`sin\*(C'\fR, \f(CW\*(C`cos\*(C'\fR and +\&\f(CW\*(C`sqrt\*(C'\fR instructions for the 387. Specify this option to avoid +generating those instructions. This option is the default on FreeBSD, +OpenBSD and NetBSD. This option is overridden when \fB\-march\fR +indicates that the target \s-1CPU\s0 will always have an \s-1FPU\s0 and so the +instruction will not need emulation. As of revision 2.6.1, these +instructions are not generated unless you also use the +\&\fB\-funsafe\-math\-optimizations\fR switch. +.IP "\fB\-malign\-double\fR" 4 +.IX Item "-malign-double" +.PD 0 +.IP "\fB\-mno\-align\-double\fR" 4 +.IX Item "-mno-align-double" +.PD +Control whether \s-1GCC\s0 aligns \f(CW\*(C`double\*(C'\fR, \f(CW\*(C`long double\*(C'\fR, and +\&\f(CW\*(C`long long\*(C'\fR variables on a two word boundary or a one word +boundary. Aligning \f(CW\*(C`double\*(C'\fR variables on a two word boundary will +produce code that runs somewhat faster on a \fBPentium\fR at the +expense of more memory. +.Sp +On x86\-64, \fB\-malign\-double\fR is enabled by default. +.Sp +\&\fBWarning:\fR if you use the \fB\-malign\-double\fR switch, +structures containing the above types will be aligned differently than +the published application binary interface specifications for the 386 +and will not be binary compatible with structures in code compiled +without that switch. +.IP "\fB\-m96bit\-long\-double\fR" 4 +.IX Item "-m96bit-long-double" +.PD 0 +.IP "\fB\-m128bit\-long\-double\fR" 4 +.IX Item "-m128bit-long-double" +.PD +These switches control the size of \f(CW\*(C`long double\*(C'\fR type. The i386 +application binary interface specifies the size to be 96 bits, +so \fB\-m96bit\-long\-double\fR is the default in 32 bit mode. +.Sp +Modern architectures (Pentium and newer) would prefer \f(CW\*(C`long double\*(C'\fR +to be aligned to an 8 or 16 byte boundary. In arrays or structures +conforming to the \s-1ABI\s0, this would not be possible. So specifying a +\&\fB\-m128bit\-long\-double\fR will align \f(CW\*(C`long double\*(C'\fR +to a 16 byte boundary by padding the \f(CW\*(C`long double\*(C'\fR with an additional +32 bit zero. +.Sp +In the x86\-64 compiler, \fB\-m128bit\-long\-double\fR is the default choice as +its \s-1ABI\s0 specifies that \f(CW\*(C`long double\*(C'\fR is to be aligned on 16 byte boundary. +.Sp +Notice that neither of these options enable any extra precision over the x87 +standard of 80 bits for a \f(CW\*(C`long double\*(C'\fR. +.Sp +\&\fBWarning:\fR if you override the default value for your target \s-1ABI\s0, the +structures and arrays containing \f(CW\*(C`long double\*(C'\fR variables will change +their size as well as function calling convention for function taking +\&\f(CW\*(C`long double\*(C'\fR will be modified. Hence they will not be binary +compatible with arrays or structures in code compiled without that switch. +.IP "\fB\-mlarge\-data\-threshold=\fR\fInumber\fR" 4 +.IX Item "-mlarge-data-threshold=number" +When \fB\-mcmodel=medium\fR is specified, the data greater than +\&\fIthreshold\fR are placed in large data section. This value must be the +same across all object linked into the binary and defaults to 65535. +.IP "\fB\-mrtd\fR" 4 +.IX Item "-mrtd" +Use a different function-calling convention, in which functions that +take a fixed number of arguments return with the \f(CW\*(C`ret\*(C'\fR \fInum\fR +instruction, which pops their arguments while returning. This saves one +instruction in the caller since there is no need to pop the arguments +there. +.Sp +You can specify that an individual function is called with this calling +sequence with the function attribute \fBstdcall\fR. You can also +override the \fB\-mrtd\fR option by using the function attribute +\&\fBcdecl\fR. +.Sp +\&\fBWarning:\fR this calling convention is incompatible with the one +normally used on Unix, so you cannot use it if you need to call +libraries compiled with the Unix compiler. +.Sp +Also, you must provide function prototypes for all functions that +take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR); +otherwise incorrect code will be generated for calls to those +functions. +.Sp +In addition, seriously incorrect code will result if you call a +function with too many arguments. (Normally, extra arguments are +harmlessly ignored.) +.IP "\fB\-mregparm=\fR\fInum\fR" 4 +.IX Item "-mregparm=num" +Control how many registers are used to pass integer arguments. By +default, no registers are used to pass arguments, and at most 3 +registers can be used. You can control this behavior for a specific +function by using the function attribute \fBregparm\fR. +.Sp +\&\fBWarning:\fR if you use this switch, and +\&\fInum\fR is nonzero, then you must build all modules with the same +value, including any libraries. This includes the system libraries and +startup modules. +.IP "\fB\-msseregparm\fR" 4 +.IX Item "-msseregparm" +Use \s-1SSE\s0 register passing conventions for float and double arguments +and return values. You can control this behavior for a specific +function by using the function attribute \fBsseregparm\fR. +.Sp +\&\fBWarning:\fR if you use this switch then you must build all +modules with the same value, including any libraries. This includes +the system libraries and startup modules. +.IP "\fB\-mvect8\-ret\-in\-mem\fR" 4 +.IX Item "-mvect8-ret-in-mem" +Return 8\-byte vectors in memory instead of \s-1MMX\s0 registers. This is the +default on Solaris@tie{}8 and 9 and VxWorks to match the \s-1ABI\s0 of the Sun +Studio compilers until version 12. Later compiler versions (starting +with Studio 12 Update@tie{}1) follow the \s-1ABI\s0 used by other x86 targets, which +is the default on Solaris@tie{}10 and later. \fIOnly\fR use this option if +you need to remain compatible with existing code produced by those +previous compiler versions or older versions of \s-1GCC\s0. +.IP "\fB\-mpc32\fR" 4 +.IX Item "-mpc32" +.PD 0 +.IP "\fB\-mpc64\fR" 4 +.IX Item "-mpc64" +.IP "\fB\-mpc80\fR" 4 +.IX Item "-mpc80" +.PD +Set 80387 floating-point precision to 32, 64 or 80 bits. When \fB\-mpc32\fR +is specified, the significands of results of floating-point operations are +rounded to 24 bits (single precision); \fB\-mpc64\fR rounds the +significands of results of floating-point operations to 53 bits (double +precision) and \fB\-mpc80\fR rounds the significands of results of +floating-point operations to 64 bits (extended double precision), which is +the default. When this option is used, floating-point operations in higher +precisions are not available to the programmer without setting the \s-1FPU\s0 +control word explicitly. +.Sp +Setting the rounding of floating-point operations to less than the default +80 bits can speed some programs by 2% or more. Note that some mathematical +libraries assume that extended precision (80 bit) floating-point operations +are enabled by default; routines in such libraries could suffer significant +loss of accuracy, typically through so-called \*(L"catastrophic cancellation\*(R", +when this option is used to set the precision to less than extended precision. +.IP "\fB\-mstackrealign\fR" 4 +.IX Item "-mstackrealign" +Realign the stack at entry. On the Intel x86, the \fB\-mstackrealign\fR +option will generate an alternate prologue and epilogue that realigns the +runtime stack if necessary. This supports mixing legacy codes that keep +a 4\-byte aligned stack with modern codes that keep a 16\-byte stack for +\&\s-1SSE\s0 compatibility. See also the attribute \f(CW\*(C`force_align_arg_pointer\*(C'\fR, +applicable to individual functions. +.IP "\fB\-mpreferred\-stack\-boundary=\fR\fInum\fR" 4 +.IX Item "-mpreferred-stack-boundary=num" +Attempt to keep the stack boundary aligned to a 2 raised to \fInum\fR +byte boundary. If \fB\-mpreferred\-stack\-boundary\fR is not specified, +the default is 4 (16 bytes or 128 bits). +.IP "\fB\-mincoming\-stack\-boundary=\fR\fInum\fR" 4 +.IX Item "-mincoming-stack-boundary=num" +Assume the incoming stack is aligned to a 2 raised to \fInum\fR byte +boundary. If \fB\-mincoming\-stack\-boundary\fR is not specified, +the one specified by \fB\-mpreferred\-stack\-boundary\fR will be used. +.Sp +On Pentium and PentiumPro, \f(CW\*(C`double\*(C'\fR and \f(CW\*(C`long double\*(C'\fR values +should be aligned to an 8 byte boundary (see \fB\-malign\-double\fR) or +suffer significant run time performance penalties. On Pentium \s-1III\s0, the +Streaming \s-1SIMD\s0 Extension (\s-1SSE\s0) data type \f(CW\*(C`_\|_m128\*(C'\fR may not work +properly if it is not 16 byte aligned. +.Sp +To ensure proper alignment of this values on the stack, the stack boundary +must be as aligned as that required by any value stored on the stack. +Further, every function must be generated such that it keeps the stack +aligned. Thus calling a function compiled with a higher preferred +stack boundary from a function compiled with a lower preferred stack +boundary will most likely misalign the stack. It is recommended that +libraries that use callbacks always use the default setting. +.Sp +This extra alignment does consume extra stack space, and generally +increases code size. Code that is sensitive to stack space usage, such +as embedded systems and operating system kernels, may want to reduce the +preferred alignment to \fB\-mpreferred\-stack\-boundary=2\fR. +.IP "\fB\-mmmx\fR" 4 +.IX Item "-mmmx" +.PD 0 +.IP "\fB\-mno\-mmx\fR" 4 +.IX Item "-mno-mmx" +.IP "\fB\-msse\fR" 4 +.IX Item "-msse" +.IP "\fB\-mno\-sse\fR" 4 +.IX Item "-mno-sse" +.IP "\fB\-msse2\fR" 4 +.IX Item "-msse2" +.IP "\fB\-mno\-sse2\fR" 4 +.IX Item "-mno-sse2" +.IP "\fB\-msse3\fR" 4 +.IX Item "-msse3" +.IP "\fB\-mno\-sse3\fR" 4 +.IX Item "-mno-sse3" +.IP "\fB\-mssse3\fR" 4 +.IX Item "-mssse3" +.IP "\fB\-mno\-ssse3\fR" 4 +.IX Item "-mno-ssse3" +.IP "\fB\-msse4.1\fR" 4 +.IX Item "-msse4.1" +.IP "\fB\-mno\-sse4.1\fR" 4 +.IX Item "-mno-sse4.1" +.IP "\fB\-msse4.2\fR" 4 +.IX Item "-msse4.2" +.IP "\fB\-mno\-sse4.2\fR" 4 +.IX Item "-mno-sse4.2" +.IP "\fB\-msse4\fR" 4 +.IX Item "-msse4" +.IP "\fB\-mno\-sse4\fR" 4 +.IX Item "-mno-sse4" +.IP "\fB\-mavx\fR" 4 +.IX Item "-mavx" +.IP "\fB\-mno\-avx\fR" 4 +.IX Item "-mno-avx" +.IP "\fB\-maes\fR" 4 +.IX Item "-maes" +.IP "\fB\-mno\-aes\fR" 4 +.IX Item "-mno-aes" +.IP "\fB\-mpclmul\fR" 4 +.IX Item "-mpclmul" +.IP "\fB\-mno\-pclmul\fR" 4 +.IX Item "-mno-pclmul" +.IP "\fB\-mfsgsbase\fR" 4 +.IX Item "-mfsgsbase" +.IP "\fB\-mno\-fsgsbase\fR" 4 +.IX Item "-mno-fsgsbase" +.IP "\fB\-mrdrnd\fR" 4 +.IX Item "-mrdrnd" +.IP "\fB\-mno\-rdrnd\fR" 4 +.IX Item "-mno-rdrnd" +.IP "\fB\-mf16c\fR" 4 +.IX Item "-mf16c" +.IP "\fB\-mno\-f16c\fR" 4 +.IX Item "-mno-f16c" +.IP "\fB\-msse4a\fR" 4 +.IX Item "-msse4a" +.IP "\fB\-mno\-sse4a\fR" 4 +.IX Item "-mno-sse4a" +.IP "\fB\-mfma4\fR" 4 +.IX Item "-mfma4" +.IP "\fB\-mno\-fma4\fR" 4 +.IX Item "-mno-fma4" +.IP "\fB\-mxop\fR" 4 +.IX Item "-mxop" +.IP "\fB\-mno\-xop\fR" 4 +.IX Item "-mno-xop" +.IP "\fB\-mlwp\fR" 4 +.IX Item "-mlwp" +.IP "\fB\-mno\-lwp\fR" 4 +.IX Item "-mno-lwp" +.IP "\fB\-m3dnow\fR" 4 +.IX Item "-m3dnow" +.IP "\fB\-mno\-3dnow\fR" 4 +.IX Item "-mno-3dnow" +.IP "\fB\-mpopcnt\fR" 4 +.IX Item "-mpopcnt" +.IP "\fB\-mno\-popcnt\fR" 4 +.IX Item "-mno-popcnt" +.IP "\fB\-mabm\fR" 4 +.IX Item "-mabm" +.IP "\fB\-mno\-abm\fR" 4 +.IX Item "-mno-abm" +.IP "\fB\-mbmi\fR" 4 +.IX Item "-mbmi" +.IP "\fB\-mno\-bmi\fR" 4 +.IX Item "-mno-bmi" +.IP "\fB\-mtbm\fR" 4 +.IX Item "-mtbm" +.IP "\fB\-mno\-tbm\fR" 4 +.IX Item "-mno-tbm" +.PD +These switches enable or disable the use of instructions in the \s-1MMX\s0, +\&\s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, \s-1SSE4\s0.1, \s-1AVX\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0, +F16C, \s-1SSE4A\s0, \s-1FMA4\s0, \s-1XOP\s0, \s-1LWP\s0, \s-1ABM\s0, \s-1BMI\s0, or 3DNow! extended instruction sets. +These extensions are also available as built-in functions: see +\&\fBX86 Built-in Functions\fR, for details of the functions enabled and +disabled by these switches. +.Sp +To have \s-1SSE/SSE2\s0 instructions generated automatically from floating-point +code (as opposed to 387 instructions), see \fB\-mfpmath=sse\fR. +.Sp +\&\s-1GCC\s0 depresses SSEx instructions when \fB\-mavx\fR is used. Instead, it +generates new \s-1AVX\s0 instructions or \s-1AVX\s0 equivalence for all SSEx instructions +when needed. +.Sp +These options will enable \s-1GCC\s0 to use these extended instructions in +generated code, even without \fB\-mfpmath=sse\fR. Applications which +perform runtime \s-1CPU\s0 detection must compile separate files for each +supported architecture, using the appropriate flags. In particular, +the file containing the \s-1CPU\s0 detection code should be compiled without +these options. +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Do (don't) generate code that uses the fused multiply/add or multiply/subtract +instructions. The default is to use these instructions. +.IP "\fB\-mcld\fR" 4 +.IX Item "-mcld" +This option instructs \s-1GCC\s0 to emit a \f(CW\*(C`cld\*(C'\fR instruction in the prologue +of functions that use string instructions. String instructions depend on +the \s-1DF\s0 flag to select between autoincrement or autodecrement mode. While the +\&\s-1ABI\s0 specifies the \s-1DF\s0 flag to be cleared on function entry, some operating +systems violate this specification by not clearing the \s-1DF\s0 flag in their +exception dispatchers. The exception handler can be invoked with the \s-1DF\s0 flag +set which leads to wrong direction mode, when string instructions are used. +This option can be enabled by default on 32\-bit x86 targets by configuring +\&\s-1GCC\s0 with the \fB\-\-enable\-cld\fR configure option. Generation of \f(CW\*(C`cld\*(C'\fR +instructions can be suppressed with the \fB\-mno\-cld\fR compiler option +in this case. +.IP "\fB\-mvzeroupper\fR" 4 +.IX Item "-mvzeroupper" +This option instructs \s-1GCC\s0 to emit a \f(CW\*(C`vzeroupper\*(C'\fR instruction +before a transfer of control flow out of the function to minimize +\&\s-1AVX\s0 to \s-1SSE\s0 transition penalty as well as remove unnecessary zeroupper +intrinsics. +.IP "\fB\-mcx16\fR" 4 +.IX Item "-mcx16" +This option will enable \s-1GCC\s0 to use \s-1CMPXCHG16B\s0 instruction in generated code. +\&\s-1CMPXCHG16B\s0 allows for atomic operations on 128\-bit double quadword (or oword) +data types. This is useful for high resolution counters that could be updated +by multiple processors (or cores). This instruction is generated as part of +atomic built-in functions: see \fBAtomic Builtins\fR for details. +.IP "\fB\-msahf\fR" 4 +.IX Item "-msahf" +This option will enable \s-1GCC\s0 to use \s-1SAHF\s0 instruction in generated 64\-bit code. +Early Intel CPUs with Intel 64 lacked \s-1LAHF\s0 and \s-1SAHF\s0 instructions supported +by \s-1AMD64\s0 until introduction of Pentium 4 G1 step in December 2005. \s-1LAHF\s0 and +\&\s-1SAHF\s0 are load and store instructions, respectively, for certain status flags. +In 64\-bit mode, \s-1SAHF\s0 instruction is used to optimize \f(CW\*(C`fmod\*(C'\fR, \f(CW\*(C`drem\*(C'\fR +or \f(CW\*(C`remainder\*(C'\fR built-in functions: see \fBOther Builtins\fR for details. +.IP "\fB\-mmovbe\fR" 4 +.IX Item "-mmovbe" +This option will enable \s-1GCC\s0 to use movbe instruction to implement +\&\f(CW\*(C`_\|_builtin_bswap32\*(C'\fR and \f(CW\*(C`_\|_builtin_bswap64\*(C'\fR. +.IP "\fB\-mcrc32\fR" 4 +.IX Item "-mcrc32" +This option will enable built-in functions, \f(CW\*(C`_\|_builtin_ia32_crc32qi\*(C'\fR, +\&\f(CW\*(C`_\|_builtin_ia32_crc32hi\*(C'\fR. \f(CW\*(C`_\|_builtin_ia32_crc32si\*(C'\fR and +\&\f(CW\*(C`_\|_builtin_ia32_crc32di\*(C'\fR to generate the crc32 machine instruction. +.IP "\fB\-mrecip\fR" 4 +.IX Item "-mrecip" +This option will enable \s-1GCC\s0 to use \s-1RCPSS\s0 and \s-1RSQRTSS\s0 instructions (and their +vectorized variants \s-1RCPPS\s0 and \s-1RSQRTPS\s0) with an additional Newton-Raphson step +to increase precision instead of \s-1DIVSS\s0 and \s-1SQRTSS\s0 (and their vectorized +variants) for single precision floating point arguments. These instructions +are generated only when \fB\-funsafe\-math\-optimizations\fR is enabled +together with \fB\-finite\-math\-only\fR and \fB\-fno\-trapping\-math\fR. +Note that while the throughput of the sequence is higher than the throughput +of the non-reciprocal instruction, the precision of the sequence can be +decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994). +.Sp +Note that \s-1GCC\s0 implements 1.0f/sqrtf(x) in terms of \s-1RSQRTSS\s0 (or \s-1RSQRTPS\s0) +already with \fB\-ffast\-math\fR (or the above option combination), and +doesn't need \fB\-mrecip\fR. +.IP "\fB\-mveclibabi=\fR\fItype\fR" 4 +.IX Item "-mveclibabi=type" +Specifies the \s-1ABI\s0 type to use for vectorizing intrinsics using an +external library. Supported types are \f(CW\*(C`svml\*(C'\fR for the Intel short +vector math library and \f(CW\*(C`acml\*(C'\fR for the \s-1AMD\s0 math core library style +of interfacing. \s-1GCC\s0 will currently emit calls to \f(CW\*(C`vmldExp2\*(C'\fR, +\&\f(CW\*(C`vmldLn2\*(C'\fR, \f(CW\*(C`vmldLog102\*(C'\fR, \f(CW\*(C`vmldLog102\*(C'\fR, \f(CW\*(C`vmldPow2\*(C'\fR, +\&\f(CW\*(C`vmldTanh2\*(C'\fR, \f(CW\*(C`vmldTan2\*(C'\fR, \f(CW\*(C`vmldAtan2\*(C'\fR, \f(CW\*(C`vmldAtanh2\*(C'\fR, +\&\f(CW\*(C`vmldCbrt2\*(C'\fR, \f(CW\*(C`vmldSinh2\*(C'\fR, \f(CW\*(C`vmldSin2\*(C'\fR, \f(CW\*(C`vmldAsinh2\*(C'\fR, +\&\f(CW\*(C`vmldAsin2\*(C'\fR, \f(CW\*(C`vmldCosh2\*(C'\fR, \f(CW\*(C`vmldCos2\*(C'\fR, \f(CW\*(C`vmldAcosh2\*(C'\fR, +\&\f(CW\*(C`vmldAcos2\*(C'\fR, \f(CW\*(C`vmlsExp4\*(C'\fR, \f(CW\*(C`vmlsLn4\*(C'\fR, \f(CW\*(C`vmlsLog104\*(C'\fR, +\&\f(CW\*(C`vmlsLog104\*(C'\fR, \f(CW\*(C`vmlsPow4\*(C'\fR, \f(CW\*(C`vmlsTanh4\*(C'\fR, \f(CW\*(C`vmlsTan4\*(C'\fR, +\&\f(CW\*(C`vmlsAtan4\*(C'\fR, \f(CW\*(C`vmlsAtanh4\*(C'\fR, \f(CW\*(C`vmlsCbrt4\*(C'\fR, \f(CW\*(C`vmlsSinh4\*(C'\fR, +\&\f(CW\*(C`vmlsSin4\*(C'\fR, \f(CW\*(C`vmlsAsinh4\*(C'\fR, \f(CW\*(C`vmlsAsin4\*(C'\fR, \f(CW\*(C`vmlsCosh4\*(C'\fR, +\&\f(CW\*(C`vmlsCos4\*(C'\fR, \f(CW\*(C`vmlsAcosh4\*(C'\fR and \f(CW\*(C`vmlsAcos4\*(C'\fR for corresponding +function type when \fB\-mveclibabi=svml\fR is used and \f(CW\*(C`_\|_vrd2_sin\*(C'\fR, +\&\f(CW\*(C`_\|_vrd2_cos\*(C'\fR, \f(CW\*(C`_\|_vrd2_exp\*(C'\fR, \f(CW\*(C`_\|_vrd2_log\*(C'\fR, \f(CW\*(C`_\|_vrd2_log2\*(C'\fR, +\&\f(CW\*(C`_\|_vrd2_log10\*(C'\fR, \f(CW\*(C`_\|_vrs4_sinf\*(C'\fR, \f(CW\*(C`_\|_vrs4_cosf\*(C'\fR, +\&\f(CW\*(C`_\|_vrs4_expf\*(C'\fR, \f(CW\*(C`_\|_vrs4_logf\*(C'\fR, \f(CW\*(C`_\|_vrs4_log2f\*(C'\fR, +\&\f(CW\*(C`_\|_vrs4_log10f\*(C'\fR and \f(CW\*(C`_\|_vrs4_powf\*(C'\fR for corresponding function type +when \fB\-mveclibabi=acml\fR is used. Both \fB\-ftree\-vectorize\fR and +\&\fB\-funsafe\-math\-optimizations\fR have to be enabled. A \s-1SVML\s0 or \s-1ACML\s0 \s-1ABI\s0 +compatible library will have to be specified at link time. +.IP "\fB\-mabi=\fR\fIname\fR" 4 +.IX Item "-mabi=name" +Generate code for the specified calling convention. Permissible values +are: \fBsysv\fR for the \s-1ABI\s0 used on GNU/Linux and other systems and +\&\fBms\fR for the Microsoft \s-1ABI\s0. The default is to use the Microsoft +\&\s-1ABI\s0 when targeting Windows. On all other systems, the default is the +\&\s-1SYSV\s0 \s-1ABI\s0. You can control this behavior for a specific function by +using the function attribute \fBms_abi\fR/\fBsysv_abi\fR. +.IP "\fB\-mpush\-args\fR" 4 +.IX Item "-mpush-args" +.PD 0 +.IP "\fB\-mno\-push\-args\fR" 4 +.IX Item "-mno-push-args" +.PD +Use \s-1PUSH\s0 operations to store outgoing parameters. This method is shorter +and usually equally fast as method using \s-1SUB/MOV\s0 operations and is enabled +by default. In some cases disabling it may improve performance because of +improved scheduling and reduced dependencies. +.IP "\fB\-maccumulate\-outgoing\-args\fR" 4 +.IX Item "-maccumulate-outgoing-args" +If enabled, the maximum amount of space required for outgoing arguments will be +computed in the function prologue. This is faster on most modern CPUs +because of reduced dependencies, improved scheduling and reduced stack usage +when preferred stack boundary is not equal to 2. The drawback is a notable +increase in code size. This switch implies \fB\-mno\-push\-args\fR. +.IP "\fB\-mthreads\fR" 4 +.IX Item "-mthreads" +Support thread-safe exception handling on \fBMingw32\fR. Code that relies +on thread-safe exception handling must compile and link all code with the +\&\fB\-mthreads\fR option. When compiling, \fB\-mthreads\fR defines +\&\fB\-D_MT\fR; when linking, it links in a special thread helper library +\&\fB\-lmingwthrd\fR which cleans up per thread exception handling data. +.IP "\fB\-mno\-align\-stringops\fR" 4 +.IX Item "-mno-align-stringops" +Do not align destination of inlined string operations. This switch reduces +code size and improves performance in case the destination is already aligned, +but \s-1GCC\s0 doesn't know about it. +.IP "\fB\-minline\-all\-stringops\fR" 4 +.IX Item "-minline-all-stringops" +By default \s-1GCC\s0 inlines string operations only when destination is known to be +aligned at least to 4 byte boundary. This enables more inlining, increase code +size, but may improve performance of code that depends on fast memcpy, strlen +and memset for short lengths. +.IP "\fB\-minline\-stringops\-dynamically\fR" 4 +.IX Item "-minline-stringops-dynamically" +For string operation of unknown size, inline runtime checks so for small +blocks inline code is used, while for large blocks library call is used. +.IP "\fB\-mstringop\-strategy=\fR\fIalg\fR" 4 +.IX Item "-mstringop-strategy=alg" +Overwrite internal decision heuristic about particular algorithm to inline +string operation with. The allowed values are \f(CW\*(C`rep_byte\*(C'\fR, +\&\f(CW\*(C`rep_4byte\*(C'\fR, \f(CW\*(C`rep_8byte\*(C'\fR for expanding using i386 \f(CW\*(C`rep\*(C'\fR prefix +of specified size, \f(CW\*(C`byte_loop\*(C'\fR, \f(CW\*(C`loop\*(C'\fR, \f(CW\*(C`unrolled_loop\*(C'\fR for +expanding inline loop, \f(CW\*(C`libcall\*(C'\fR for always expanding library call. +.IP "\fB\-momit\-leaf\-frame\-pointer\fR" 4 +.IX Item "-momit-leaf-frame-pointer" +Don't keep the frame pointer in a register for leaf functions. This +avoids the instructions to save, set up and restore frame pointers and +makes an extra register available in leaf functions. The option +\&\fB\-fomit\-frame\-pointer\fR removes the frame pointer for all functions +which might make debugging harder. +.IP "\fB\-mtls\-direct\-seg\-refs\fR" 4 +.IX Item "-mtls-direct-seg-refs" +.PD 0 +.IP "\fB\-mno\-tls\-direct\-seg\-refs\fR" 4 +.IX Item "-mno-tls-direct-seg-refs" +.PD +Controls whether \s-1TLS\s0 variables may be accessed with offsets from the +\&\s-1TLS\s0 segment register (\f(CW%gs\fR for 32\-bit, \f(CW%fs\fR for 64\-bit), +or whether the thread base pointer must be added. Whether or not this +is legal depends on the operating system, and whether it maps the +segment to cover the entire \s-1TLS\s0 area. +.Sp +For systems that use \s-1GNU\s0 libc, the default is on. +.IP "\fB\-msse2avx\fR" 4 +.IX Item "-msse2avx" +.PD 0 +.IP "\fB\-mno\-sse2avx\fR" 4 +.IX Item "-mno-sse2avx" +.PD +Specify that the assembler should encode \s-1SSE\s0 instructions with \s-1VEX\s0 +prefix. The option \fB\-mavx\fR turns this on by default. +.IP "\fB\-mfentry\fR" 4 +.IX Item "-mfentry" +.PD 0 +.IP "\fB\-mno\-fentry\fR" 4 +.IX Item "-mno-fentry" +.PD +If profiling is active \fB\-pg\fR put the profiling +counter call before prologue. +Note: On x86 architectures the attribute \f(CW\*(C`ms_hook_prologue\*(C'\fR +isn't possible at the moment for \fB\-mfentry\fR and \fB\-pg\fR. +.IP "\fB\-m8bit\-idiv\fR" 4 +.IX Item "-m8bit-idiv" +.PD 0 +.IP "\fB\-mno\-8bit\-idiv\fR" 4 +.IX Item "-mno-8bit-idiv" +.PD +On some processors, like Intel Atom, 8bit unsigned integer divide is +much faster than 32bit/64bit integer divide. This option will generate a +runt-time check. If both dividend and divisor are within range of 0 +to 255, 8bit unsigned integer divide will be used instead of +32bit/64bit integer divide. +.IP "\fB\-mavx256\-split\-unaligned\-load\fR" 4 +.IX Item "-mavx256-split-unaligned-load" +.PD 0 +.IP "\fB\-mavx256\-split\-unaligned\-store\fR" 4 +.IX Item "-mavx256-split-unaligned-store" +.PD +Split 32\-byte \s-1AVX\s0 unaligned load and store. +.PP +These \fB\-m\fR switches are supported in addition to the above +on \s-1AMD\s0 x86\-64 processors in 64\-bit environments. +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" +.PD 0 +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.PD +Generate code for a 32\-bit or 64\-bit environment. +The 32\-bit environment sets int, long and pointer to 32 bits and +generates code that runs on any i386 system. +The 64\-bit environment sets int to 32 bits and long and pointer +to 64 bits and generates code for \s-1AMD\s0's x86\-64 architecture. For +darwin only the \-m64 option turns off the \fB\-fno\-pic\fR and +\&\fB\-mdynamic\-no\-pic\fR options. +.IP "\fB\-mno\-red\-zone\fR" 4 +.IX Item "-mno-red-zone" +Do not use a so called red zone for x86\-64 code. The red zone is mandated +by the x86\-64 \s-1ABI\s0, it is a 128\-byte area beyond the location of the +stack pointer that will not be modified by signal or interrupt handlers +and therefore can be used for temporary data without adjusting the stack +pointer. The flag \fB\-mno\-red\-zone\fR disables this red zone. +.IP "\fB\-mcmodel=small\fR" 4 +.IX Item "-mcmodel=small" +Generate code for the small code model: the program and its symbols must +be linked in the lower 2 \s-1GB\s0 of the address space. Pointers are 64 bits. +Programs can be statically or dynamically linked. This is the default +code model. +.IP "\fB\-mcmodel=kernel\fR" 4 +.IX Item "-mcmodel=kernel" +Generate code for the kernel code model. The kernel runs in the +negative 2 \s-1GB\s0 of the address space. +This model has to be used for Linux kernel code. +.IP "\fB\-mcmodel=medium\fR" 4 +.IX Item "-mcmodel=medium" +Generate code for the medium model: The program is linked in the lower 2 +\&\s-1GB\s0 of the address space. Small symbols are also placed there. Symbols +with sizes larger than \fB\-mlarge\-data\-threshold\fR are put into +large data or bss sections and can be located above 2GB. Programs can +be statically or dynamically linked. +.IP "\fB\-mcmodel=large\fR" 4 +.IX Item "-mcmodel=large" +Generate code for the large model: This model makes no assumptions +about addresses and sizes of sections. +.PP +\fIi386 and x86\-64 Windows Options\fR +.IX Subsection "i386 and x86-64 Windows Options" +.PP +These additional options are available for Windows targets: +.IP "\fB\-mconsole\fR" 4 +.IX Item "-mconsole" +This option is available for Cygwin and MinGW targets. It +specifies that a console application is to be generated, by +instructing the linker to set the \s-1PE\s0 header subsystem type +required for console applications. +This is the default behavior for Cygwin and MinGW targets. +.IP "\fB\-mdll\fR" 4 +.IX Item "-mdll" +This option is available for Cygwin and MinGW targets. It +specifies that a \s-1DLL\s0 \- a dynamic link library \- is to be +generated, enabling the selection of the required runtime +startup object and entry point. +.IP "\fB\-mnop\-fun\-dllimport\fR" 4 +.IX Item "-mnop-fun-dllimport" +This option is available for Cygwin and MinGW targets. It +specifies that the dllimport attribute should be ignored. +.IP "\fB\-mthread\fR" 4 +.IX Item "-mthread" +This option is available for MinGW targets. It specifies +that MinGW-specific thread support is to be used. +.IP "\fB\-municode\fR" 4 +.IX Item "-municode" +This option is available for mingw\-w64 targets. It specifies +that the \s-1UNICODE\s0 macro is getting pre-defined and that the +unicode capable runtime startup code is chosen. +.IP "\fB\-mwin32\fR" 4 +.IX Item "-mwin32" +This option is available for Cygwin and MinGW targets. It +specifies that the typical Windows pre-defined macros are to +be set in the pre-processor, but does not influence the choice +of runtime library/startup code. +.IP "\fB\-mwindows\fR" 4 +.IX Item "-mwindows" +This option is available for Cygwin and MinGW targets. It +specifies that a \s-1GUI\s0 application is to be generated by +instructing the linker to set the \s-1PE\s0 header subsystem type +appropriately. +.IP "\fB\-fno\-set\-stack\-executable\fR" 4 +.IX Item "-fno-set-stack-executable" +This option is available for MinGW targets. It specifies that +the executable flag for stack used by nested functions isn't +set. This is necessary for binaries running in kernel mode of +Windows, as there the user32 \s-1API\s0, which is used to set executable +privileges, isn't available. +.IP "\fB\-mpe\-aligned\-commons\fR" 4 +.IX Item "-mpe-aligned-commons" +This option is available for Cygwin and MinGW targets. It +specifies that the \s-1GNU\s0 extension to the \s-1PE\s0 file format that +permits the correct alignment of \s-1COMMON\s0 variables should be +used when generating code. It will be enabled by default if +\&\s-1GCC\s0 detects that the target assembler found during configuration +supports the feature. +.PP +See also under \fBi386 and x86\-64 Options\fR for standard options. +.PP +\fI\s-1IA\-64\s0 Options\fR +.IX Subsection "IA-64 Options" +.PP +These are the \fB\-m\fR options defined for the Intel \s-1IA\-64\s0 architecture. +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +Generate code for a big endian target. This is the default for HP-UX. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +Generate code for a little endian target. This is the default for \s-1AIX5\s0 +and GNU/Linux. +.IP "\fB\-mgnu\-as\fR" 4 +.IX Item "-mgnu-as" +.PD 0 +.IP "\fB\-mno\-gnu\-as\fR" 4 +.IX Item "-mno-gnu-as" +.PD +Generate (or don't) code for the \s-1GNU\s0 assembler. This is the default. +.IP "\fB\-mgnu\-ld\fR" 4 +.IX Item "-mgnu-ld" +.PD 0 +.IP "\fB\-mno\-gnu\-ld\fR" 4 +.IX Item "-mno-gnu-ld" +.PD +Generate (or don't) code for the \s-1GNU\s0 linker. This is the default. +.IP "\fB\-mno\-pic\fR" 4 +.IX Item "-mno-pic" +Generate code that does not use a global pointer register. The result +is not position independent code, and violates the \s-1IA\-64\s0 \s-1ABI\s0. +.IP "\fB\-mvolatile\-asm\-stop\fR" 4 +.IX Item "-mvolatile-asm-stop" +.PD 0 +.IP "\fB\-mno\-volatile\-asm\-stop\fR" 4 +.IX Item "-mno-volatile-asm-stop" +.PD +Generate (or don't) a stop bit immediately before and after volatile asm +statements. +.IP "\fB\-mregister\-names\fR" 4 +.IX Item "-mregister-names" +.PD 0 +.IP "\fB\-mno\-register\-names\fR" 4 +.IX Item "-mno-register-names" +.PD +Generate (or don't) \fBin\fR, \fBloc\fR, and \fBout\fR register names for +the stacked registers. This may make assembler output more readable. +.IP "\fB\-mno\-sdata\fR" 4 +.IX Item "-mno-sdata" +.PD 0 +.IP "\fB\-msdata\fR" 4 +.IX Item "-msdata" +.PD +Disable (or enable) optimizations that use the small data section. This may +be useful for working around optimizer bugs. +.IP "\fB\-mconstant\-gp\fR" 4 +.IX Item "-mconstant-gp" +Generate code that uses a single constant global pointer value. This is +useful when compiling kernel code. +.IP "\fB\-mauto\-pic\fR" 4 +.IX Item "-mauto-pic" +Generate code that is self-relocatable. This implies \fB\-mconstant\-gp\fR. +This is useful when compiling firmware code. +.IP "\fB\-minline\-float\-divide\-min\-latency\fR" 4 +.IX Item "-minline-float-divide-min-latency" +Generate code for inline divides of floating point values +using the minimum latency algorithm. +.IP "\fB\-minline\-float\-divide\-max\-throughput\fR" 4 +.IX Item "-minline-float-divide-max-throughput" +Generate code for inline divides of floating point values +using the maximum throughput algorithm. +.IP "\fB\-mno\-inline\-float\-divide\fR" 4 +.IX Item "-mno-inline-float-divide" +Do not generate inline code for divides of floating point values. +.IP "\fB\-minline\-int\-divide\-min\-latency\fR" 4 +.IX Item "-minline-int-divide-min-latency" +Generate code for inline divides of integer values +using the minimum latency algorithm. +.IP "\fB\-minline\-int\-divide\-max\-throughput\fR" 4 +.IX Item "-minline-int-divide-max-throughput" +Generate code for inline divides of integer values +using the maximum throughput algorithm. +.IP "\fB\-mno\-inline\-int\-divide\fR" 4 +.IX Item "-mno-inline-int-divide" +Do not generate inline code for divides of integer values. +.IP "\fB\-minline\-sqrt\-min\-latency\fR" 4 +.IX Item "-minline-sqrt-min-latency" +Generate code for inline square roots +using the minimum latency algorithm. +.IP "\fB\-minline\-sqrt\-max\-throughput\fR" 4 +.IX Item "-minline-sqrt-max-throughput" +Generate code for inline square roots +using the maximum throughput algorithm. +.IP "\fB\-mno\-inline\-sqrt\fR" 4 +.IX Item "-mno-inline-sqrt" +Do not generate inline code for sqrt. +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Do (don't) generate code that uses the fused multiply/add or multiply/subtract +instructions. The default is to use these instructions. +.IP "\fB\-mno\-dwarf2\-asm\fR" 4 +.IX Item "-mno-dwarf2-asm" +.PD 0 +.IP "\fB\-mdwarf2\-asm\fR" 4 +.IX Item "-mdwarf2-asm" +.PD +Don't (or do) generate assembler code for the \s-1DWARF2\s0 line number debugging +info. This may be useful when not using the \s-1GNU\s0 assembler. +.IP "\fB\-mearly\-stop\-bits\fR" 4 +.IX Item "-mearly-stop-bits" +.PD 0 +.IP "\fB\-mno\-early\-stop\-bits\fR" 4 +.IX Item "-mno-early-stop-bits" +.PD +Allow stop bits to be placed earlier than immediately preceding the +instruction that triggered the stop bit. This can improve instruction +scheduling, but does not always do so. +.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 +.IX Item "-mfixed-range=register-range" +Generate code treating the given register range as fixed registers. +A fixed register is one that the register allocator can not use. This is +useful when compiling kernel code. A register range is specified as +two registers separated by a dash. Multiple register ranges can be +specified separated by a comma. +.IP "\fB\-mtls\-size=\fR\fItls-size\fR" 4 +.IX Item "-mtls-size=tls-size" +Specify bit size of immediate \s-1TLS\s0 offsets. Valid values are 14, 22, and +64. +.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 +.IX Item "-mtune=cpu-type" +Tune the instruction scheduling for a particular \s-1CPU\s0, Valid values are +itanium, itanium1, merced, itanium2, and mckinley. +.IP "\fB\-milp32\fR" 4 +.IX Item "-milp32" +.PD 0 +.IP "\fB\-mlp64\fR" 4 +.IX Item "-mlp64" +.PD +Generate code for a 32\-bit or 64\-bit environment. +The 32\-bit environment sets int, long and pointer to 32 bits. +The 64\-bit environment sets int to 32 bits and long and pointer +to 64 bits. These are HP-UX specific flags. +.IP "\fB\-mno\-sched\-br\-data\-spec\fR" 4 +.IX Item "-mno-sched-br-data-spec" +.PD 0 +.IP "\fB\-msched\-br\-data\-spec\fR" 4 +.IX Item "-msched-br-data-spec" +.PD +(Dis/En)able data speculative scheduling before reload. +This will result in generation of the ld.a instructions and +the corresponding check instructions (ld.c / chk.a). +The default is 'disable'. +.IP "\fB\-msched\-ar\-data\-spec\fR" 4 +.IX Item "-msched-ar-data-spec" +.PD 0 +.IP "\fB\-mno\-sched\-ar\-data\-spec\fR" 4 +.IX Item "-mno-sched-ar-data-spec" +.PD +(En/Dis)able data speculative scheduling after reload. +This will result in generation of the ld.a instructions and +the corresponding check instructions (ld.c / chk.a). +The default is 'enable'. +.IP "\fB\-mno\-sched\-control\-spec\fR" 4 +.IX Item "-mno-sched-control-spec" +.PD 0 +.IP "\fB\-msched\-control\-spec\fR" 4 +.IX Item "-msched-control-spec" +.PD +(Dis/En)able control speculative scheduling. This feature is +available only during region scheduling (i.e. before reload). +This will result in generation of the ld.s instructions and +the corresponding check instructions chk.s . +The default is 'disable'. +.IP "\fB\-msched\-br\-in\-data\-spec\fR" 4 +.IX Item "-msched-br-in-data-spec" +.PD 0 +.IP "\fB\-mno\-sched\-br\-in\-data\-spec\fR" 4 +.IX Item "-mno-sched-br-in-data-spec" +.PD +(En/Dis)able speculative scheduling of the instructions that +are dependent on the data speculative loads before reload. +This is effective only with \fB\-msched\-br\-data\-spec\fR enabled. +The default is 'enable'. +.IP "\fB\-msched\-ar\-in\-data\-spec\fR" 4 +.IX Item "-msched-ar-in-data-spec" +.PD 0 +.IP "\fB\-mno\-sched\-ar\-in\-data\-spec\fR" 4 +.IX Item "-mno-sched-ar-in-data-spec" +.PD +(En/Dis)able speculative scheduling of the instructions that +are dependent on the data speculative loads after reload. +This is effective only with \fB\-msched\-ar\-data\-spec\fR enabled. +The default is 'enable'. +.IP "\fB\-msched\-in\-control\-spec\fR" 4 +.IX Item "-msched-in-control-spec" +.PD 0 +.IP "\fB\-mno\-sched\-in\-control\-spec\fR" 4 +.IX Item "-mno-sched-in-control-spec" +.PD +(En/Dis)able speculative scheduling of the instructions that +are dependent on the control speculative loads. +This is effective only with \fB\-msched\-control\-spec\fR enabled. +The default is 'enable'. +.IP "\fB\-mno\-sched\-prefer\-non\-data\-spec\-insns\fR" 4 +.IX Item "-mno-sched-prefer-non-data-spec-insns" +.PD 0 +.IP "\fB\-msched\-prefer\-non\-data\-spec\-insns\fR" 4 +.IX Item "-msched-prefer-non-data-spec-insns" +.PD +If enabled, data speculative instructions will be chosen for schedule +only if there are no other choices at the moment. This will make +the use of the data speculation much more conservative. +The default is 'disable'. +.IP "\fB\-mno\-sched\-prefer\-non\-control\-spec\-insns\fR" 4 +.IX Item "-mno-sched-prefer-non-control-spec-insns" +.PD 0 +.IP "\fB\-msched\-prefer\-non\-control\-spec\-insns\fR" 4 +.IX Item "-msched-prefer-non-control-spec-insns" +.PD +If enabled, control speculative instructions will be chosen for schedule +only if there are no other choices at the moment. This will make +the use of the control speculation much more conservative. +The default is 'disable'. +.IP "\fB\-mno\-sched\-count\-spec\-in\-critical\-path\fR" 4 +.IX Item "-mno-sched-count-spec-in-critical-path" +.PD 0 +.IP "\fB\-msched\-count\-spec\-in\-critical\-path\fR" 4 +.IX Item "-msched-count-spec-in-critical-path" +.PD +If enabled, speculative dependencies will be considered during +computation of the instructions priorities. This will make the use of the +speculation a bit more conservative. +The default is 'disable'. +.IP "\fB\-msched\-spec\-ldc\fR" 4 +.IX Item "-msched-spec-ldc" +Use a simple data speculation check. This option is on by default. +.IP "\fB\-msched\-control\-spec\-ldc\fR" 4 +.IX Item "-msched-control-spec-ldc" +Use a simple check for control speculation. This option is on by default. +.IP "\fB\-msched\-stop\-bits\-after\-every\-cycle\fR" 4 +.IX Item "-msched-stop-bits-after-every-cycle" +Place a stop bit after every cycle when scheduling. This option is on +by default. +.IP "\fB\-msched\-fp\-mem\-deps\-zero\-cost\fR" 4 +.IX Item "-msched-fp-mem-deps-zero-cost" +Assume that floating-point stores and loads are not likely to cause a conflict +when placed into the same instruction group. This option is disabled by +default. +.IP "\fB\-msel\-sched\-dont\-check\-control\-spec\fR" 4 +.IX Item "-msel-sched-dont-check-control-spec" +Generate checks for control speculation in selective scheduling. +This flag is disabled by default. +.IP "\fB\-msched\-max\-memory\-insns=\fR\fImax-insns\fR" 4 +.IX Item "-msched-max-memory-insns=max-insns" +Limit on the number of memory insns per instruction group, giving lower +priority to subsequent memory insns attempting to schedule in the same +instruction group. Frequently useful to prevent cache bank conflicts. +The default value is 1. +.IP "\fB\-msched\-max\-memory\-insns\-hard\-limit\fR" 4 +.IX Item "-msched-max-memory-insns-hard-limit" +Disallow more than `msched\-max\-memory\-insns' in instruction group. +Otherwise, limit is `soft' meaning that we would prefer non-memory operations +when limit is reached but may still schedule memory operations. +.PP +\fI\s-1IA\-64/VMS\s0 Options\fR +.IX Subsection "IA-64/VMS Options" +.PP +These \fB\-m\fR options are defined for the \s-1IA\-64/VMS\s0 implementations: +.IP "\fB\-mvms\-return\-codes\fR" 4 +.IX Item "-mvms-return-codes" +Return \s-1VMS\s0 condition codes from main. The default is to return \s-1POSIX\s0 +style condition (e.g. error) codes. +.IP "\fB\-mdebug\-main=\fR\fIprefix\fR" 4 +.IX Item "-mdebug-main=prefix" +Flag the first routine whose name starts with \fIprefix\fR as the main +routine for the debugger. +.IP "\fB\-mmalloc64\fR" 4 +.IX Item "-mmalloc64" +Default to 64bit memory allocation routines. +.PP +\fI\s-1LM32\s0 Options\fR +.IX Subsection "LM32 Options" +.PP +These \fB\-m\fR options are defined for the Lattice Mico32 architecture: +.IP "\fB\-mbarrel\-shift\-enabled\fR" 4 +.IX Item "-mbarrel-shift-enabled" +Enable barrel-shift instructions. +.IP "\fB\-mdivide\-enabled\fR" 4 +.IX Item "-mdivide-enabled" +Enable divide and modulus instructions. +.IP "\fB\-mmultiply\-enabled\fR" 4 +.IX Item "-mmultiply-enabled" +Enable multiply instructions. +.IP "\fB\-msign\-extend\-enabled\fR" 4 +.IX Item "-msign-extend-enabled" +Enable sign extend instructions. +.IP "\fB\-muser\-enabled\fR" 4 +.IX Item "-muser-enabled" +Enable user-defined instructions. +.PP +\fIM32C Options\fR +.IX Subsection "M32C Options" +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +Select the \s-1CPU\s0 for which code is generated. \fIname\fR may be one of +\&\fBr8c\fR for the R8C/Tiny series, \fBm16c\fR for the M16C (up to +/60) series, \fBm32cm\fR for the M16C/80 series, or \fBm32c\fR for +the M32C/80 series. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Specifies that the program will be run on the simulator. This causes +an alternate runtime library to be linked in which supports, for +example, file I/O. You must not use this option when generating +programs that will run on real hardware; you must provide your own +runtime library for whatever I/O functions are needed. +.IP "\fB\-memregs=\fR\fInumber\fR" 4 +.IX Item "-memregs=number" +Specifies the number of memory-based pseudo-registers \s-1GCC\s0 will use +during code generation. These pseudo-registers will be used like real +registers, so there is a tradeoff between \s-1GCC\s0's ability to fit the +code into available registers, and the performance penalty of using +memory instead of registers. Note that all modules in a program must +be compiled with the same value for this option. Because of that, you +must not use this option with the default runtime libraries gcc +builds. +.PP +\fIM32R/D Options\fR +.IX Subsection "M32R/D Options" +.PP +These \fB\-m\fR options are defined for Renesas M32R/D architectures: +.IP "\fB\-m32r2\fR" 4 +.IX Item "-m32r2" +Generate code for the M32R/2. +.IP "\fB\-m32rx\fR" 4 +.IX Item "-m32rx" +Generate code for the M32R/X. +.IP "\fB\-m32r\fR" 4 +.IX Item "-m32r" +Generate code for the M32R. This is the default. +.IP "\fB\-mmodel=small\fR" 4 +.IX Item "-mmodel=small" +Assume all objects live in the lower 16MB of memory (so that their addresses +can be loaded with the \f(CW\*(C`ld24\*(C'\fR instruction), and assume all subroutines +are reachable with the \f(CW\*(C`bl\*(C'\fR instruction. +This is the default. +.Sp +The addressability of a particular object can be set with the +\&\f(CW\*(C`model\*(C'\fR attribute. +.IP "\fB\-mmodel=medium\fR" 4 +.IX Item "-mmodel=medium" +Assume objects may be anywhere in the 32\-bit address space (the compiler +will generate \f(CW\*(C`seth/add3\*(C'\fR instructions to load their addresses), and +assume all subroutines are reachable with the \f(CW\*(C`bl\*(C'\fR instruction. +.IP "\fB\-mmodel=large\fR" 4 +.IX Item "-mmodel=large" +Assume objects may be anywhere in the 32\-bit address space (the compiler +will generate \f(CW\*(C`seth/add3\*(C'\fR instructions to load their addresses), and +assume subroutines may not be reachable with the \f(CW\*(C`bl\*(C'\fR instruction +(the compiler will generate the much slower \f(CW\*(C`seth/add3/jl\*(C'\fR +instruction sequence). +.IP "\fB\-msdata=none\fR" 4 +.IX Item "-msdata=none" +Disable use of the small data area. Variables will be put into +one of \fB.data\fR, \fBbss\fR, or \fB.rodata\fR (unless the +\&\f(CW\*(C`section\*(C'\fR attribute has been specified). +This is the default. +.Sp +The small data area consists of sections \fB.sdata\fR and \fB.sbss\fR. +Objects may be explicitly put in the small data area with the +\&\f(CW\*(C`section\*(C'\fR attribute using one of these sections. +.IP "\fB\-msdata=sdata\fR" 4 +.IX Item "-msdata=sdata" +Put small global and static data in the small data area, but do not +generate special code to reference them. +.IP "\fB\-msdata=use\fR" 4 +.IX Item "-msdata=use" +Put small global and static data in the small data area, and generate +special instructions to reference them. +.IP "\fB\-G\fR \fInum\fR" 4 +.IX Item "-G num" +Put global and static objects less than or equal to \fInum\fR bytes +into the small data or bss sections instead of the normal data or bss +sections. The default value of \fInum\fR is 8. +The \fB\-msdata\fR option must be set to one of \fBsdata\fR or \fBuse\fR +for this option to have any effect. +.Sp +All modules should be compiled with the same \fB\-G\fR \fInum\fR value. +Compiling with different values of \fInum\fR may or may not work; if it +doesn't the linker will give an error message\-\-\-incorrect code will not be +generated. +.IP "\fB\-mdebug\fR" 4 +.IX Item "-mdebug" +Makes the M32R specific code in the compiler display some statistics +that might help in debugging programs. +.IP "\fB\-malign\-loops\fR" 4 +.IX Item "-malign-loops" +Align all loops to a 32\-byte boundary. +.IP "\fB\-mno\-align\-loops\fR" 4 +.IX Item "-mno-align-loops" +Do not enforce a 32\-byte alignment for loops. This is the default. +.IP "\fB\-missue\-rate=\fR\fInumber\fR" 4 +.IX Item "-missue-rate=number" +Issue \fInumber\fR instructions per cycle. \fInumber\fR can only be 1 +or 2. +.IP "\fB\-mbranch\-cost=\fR\fInumber\fR" 4 +.IX Item "-mbranch-cost=number" +\&\fInumber\fR can only be 1 or 2. If it is 1 then branches will be +preferred over conditional code, if it is 2, then the opposite will +apply. +.IP "\fB\-mflush\-trap=\fR\fInumber\fR" 4 +.IX Item "-mflush-trap=number" +Specifies the trap number to use to flush the cache. The default is +12. Valid numbers are between 0 and 15 inclusive. +.IP "\fB\-mno\-flush\-trap\fR" 4 +.IX Item "-mno-flush-trap" +Specifies that the cache cannot be flushed by using a trap. +.IP "\fB\-mflush\-func=\fR\fIname\fR" 4 +.IX Item "-mflush-func=name" +Specifies the name of the operating system function to call to flush +the cache. The default is \fI_flush_cache\fR, but a function call +will only be used if a trap is not available. +.IP "\fB\-mno\-flush\-func\fR" 4 +.IX Item "-mno-flush-func" +Indicates that there is no \s-1OS\s0 function for flushing the cache. +.PP +\fIM680x0 Options\fR +.IX Subsection "M680x0 Options" +.PP +These are the \fB\-m\fR options defined for M680x0 and ColdFire processors. +The default settings depend on which architecture was selected when +the compiler was configured; the defaults for the most common choices +are given below. +.IP "\fB\-march=\fR\fIarch\fR" 4 +.IX Item "-march=arch" +Generate code for a specific M680x0 or ColdFire instruction set +architecture. Permissible values of \fIarch\fR for M680x0 +architectures are: \fB68000\fR, \fB68010\fR, \fB68020\fR, +\&\fB68030\fR, \fB68040\fR, \fB68060\fR and \fBcpu32\fR. ColdFire +architectures are selected according to Freescale's \s-1ISA\s0 classification +and the permissible values are: \fBisaa\fR, \fBisaaplus\fR, +\&\fBisab\fR and \fBisac\fR. +.Sp +gcc defines a macro \fB_\|_mcf\fR\fIarch\fR\fB_\|_\fR whenever it is generating +code for a ColdFire target. The \fIarch\fR in this macro is one of the +\&\fB\-march\fR arguments given above. +.Sp +When used together, \fB\-march\fR and \fB\-mtune\fR select code +that runs on a family of similar processors but that is optimized +for a particular microarchitecture. +.IP "\fB\-mcpu=\fR\fIcpu\fR" 4 +.IX Item "-mcpu=cpu" +Generate code for a specific M680x0 or ColdFire processor. +The M680x0 \fIcpu\fRs are: \fB68000\fR, \fB68010\fR, \fB68020\fR, +\&\fB68030\fR, \fB68040\fR, \fB68060\fR, \fB68302\fR, \fB68332\fR +and \fBcpu32\fR. The ColdFire \fIcpu\fRs are given by the table +below, which also classifies the CPUs into families: +.RS 4 +.IP "Family : \fB\-mcpu\fR arguments" 4 +.IX Item "Family : -mcpu arguments" +.PD 0 +.IP "\fB51\fR : \fB51\fR \fB51ac\fR \fB51cn\fR \fB51em\fR \fB51qe\fR" 4 +.IX Item "51 : 51 51ac 51cn 51em 51qe" +.IP "\fB5206\fR : \fB5202\fR \fB5204\fR \fB5206\fR" 4 +.IX Item "5206 : 5202 5204 5206" +.IP "\fB5206e\fR : \fB5206e\fR" 4 +.IX Item "5206e : 5206e" +.IP "\fB5208\fR : \fB5207\fR \fB5208\fR" 4 +.IX Item "5208 : 5207 5208" +.IP "\fB5211a\fR : \fB5210a\fR \fB5211a\fR" 4 +.IX Item "5211a : 5210a 5211a" +.IP "\fB5213\fR : \fB5211\fR \fB5212\fR \fB5213\fR" 4 +.IX Item "5213 : 5211 5212 5213" +.IP "\fB5216\fR : \fB5214\fR \fB5216\fR" 4 +.IX Item "5216 : 5214 5216" +.IP "\fB52235\fR : \fB52230\fR \fB52231\fR \fB52232\fR \fB52233\fR \fB52234\fR \fB52235\fR" 4 +.IX Item "52235 : 52230 52231 52232 52233 52234 52235" +.IP "\fB5225\fR : \fB5224\fR \fB5225\fR" 4 +.IX Item "5225 : 5224 5225" +.IP "\fB52259\fR : \fB52252\fR \fB52254\fR \fB52255\fR \fB52256\fR \fB52258\fR \fB52259\fR" 4 +.IX Item "52259 : 52252 52254 52255 52256 52258 52259" +.IP "\fB5235\fR : \fB5232\fR \fB5233\fR \fB5234\fR \fB5235\fR \fB523x\fR" 4 +.IX Item "5235 : 5232 5233 5234 5235 523x" +.IP "\fB5249\fR : \fB5249\fR" 4 +.IX Item "5249 : 5249" +.IP "\fB5250\fR : \fB5250\fR" 4 +.IX Item "5250 : 5250" +.IP "\fB5271\fR : \fB5270\fR \fB5271\fR" 4 +.IX Item "5271 : 5270 5271" +.IP "\fB5272\fR : \fB5272\fR" 4 +.IX Item "5272 : 5272" +.IP "\fB5275\fR : \fB5274\fR \fB5275\fR" 4 +.IX Item "5275 : 5274 5275" +.IP "\fB5282\fR : \fB5280\fR \fB5281\fR \fB5282\fR \fB528x\fR" 4 +.IX Item "5282 : 5280 5281 5282 528x" +.IP "\fB53017\fR : \fB53011\fR \fB53012\fR \fB53013\fR \fB53014\fR \fB53015\fR \fB53016\fR \fB53017\fR" 4 +.IX Item "53017 : 53011 53012 53013 53014 53015 53016 53017" +.IP "\fB5307\fR : \fB5307\fR" 4 +.IX Item "5307 : 5307" +.IP "\fB5329\fR : \fB5327\fR \fB5328\fR \fB5329\fR \fB532x\fR" 4 +.IX Item "5329 : 5327 5328 5329 532x" +.IP "\fB5373\fR : \fB5372\fR \fB5373\fR \fB537x\fR" 4 +.IX Item "5373 : 5372 5373 537x" +.IP "\fB5407\fR : \fB5407\fR" 4 +.IX Item "5407 : 5407" +.IP "\fB5475\fR : \fB5470\fR \fB5471\fR \fB5472\fR \fB5473\fR \fB5474\fR \fB5475\fR \fB547x\fR \fB5480\fR \fB5481\fR \fB5482\fR \fB5483\fR \fB5484\fR \fB5485\fR" 4 +.IX Item "5475 : 5470 5471 5472 5473 5474 5475 547x 5480 5481 5482 5483 5484 5485" +.RE +.RS 4 +.PD +.Sp +\&\fB\-mcpu=\fR\fIcpu\fR overrides \fB\-march=\fR\fIarch\fR if +\&\fIarch\fR is compatible with \fIcpu\fR. Other combinations of +\&\fB\-mcpu\fR and \fB\-march\fR are rejected. +.Sp +gcc defines the macro \fB_\|_mcf_cpu_\fR\fIcpu\fR when ColdFire target +\&\fIcpu\fR is selected. It also defines \fB_\|_mcf_family_\fR\fIfamily\fR, +where the value of \fIfamily\fR is given by the table above. +.RE +.IP "\fB\-mtune=\fR\fItune\fR" 4 +.IX Item "-mtune=tune" +Tune the code for a particular microarchitecture, within the +constraints set by \fB\-march\fR and \fB\-mcpu\fR. +The M680x0 microarchitectures are: \fB68000\fR, \fB68010\fR, +\&\fB68020\fR, \fB68030\fR, \fB68040\fR, \fB68060\fR +and \fBcpu32\fR. The ColdFire microarchitectures +are: \fBcfv1\fR, \fBcfv2\fR, \fBcfv3\fR, \fBcfv4\fR and \fBcfv4e\fR. +.Sp +You can also use \fB\-mtune=68020\-40\fR for code that needs +to run relatively well on 68020, 68030 and 68040 targets. +\&\fB\-mtune=68020\-60\fR is similar but includes 68060 targets +as well. These two options select the same tuning decisions as +\&\fB\-m68020\-40\fR and \fB\-m68020\-60\fR respectively. +.Sp +gcc defines the macros \fB_\|_mc\fR\fIarch\fR and \fB_\|_mc\fR\fIarch\fR\fB_\|_\fR +when tuning for 680x0 architecture \fIarch\fR. It also defines +\&\fBmc\fR\fIarch\fR unless either \fB\-ansi\fR or a non-GNU \fB\-std\fR +option is used. If gcc is tuning for a range of architectures, +as selected by \fB\-mtune=68020\-40\fR or \fB\-mtune=68020\-60\fR, +it defines the macros for every architecture in the range. +.Sp +gcc also defines the macro \fB_\|_m\fR\fIuarch\fR\fB_\|_\fR when tuning for +ColdFire microarchitecture \fIuarch\fR, where \fIuarch\fR is one +of the arguments given above. +.IP "\fB\-m68000\fR" 4 +.IX Item "-m68000" +.PD 0 +.IP "\fB\-mc68000\fR" 4 +.IX Item "-mc68000" +.PD +Generate output for a 68000. This is the default +when the compiler is configured for 68000\-based systems. +It is equivalent to \fB\-march=68000\fR. +.Sp +Use this option for microcontrollers with a 68000 or \s-1EC000\s0 core, +including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356. +.IP "\fB\-m68010\fR" 4 +.IX Item "-m68010" +Generate output for a 68010. This is the default +when the compiler is configured for 68010\-based systems. +It is equivalent to \fB\-march=68010\fR. +.IP "\fB\-m68020\fR" 4 +.IX Item "-m68020" +.PD 0 +.IP "\fB\-mc68020\fR" 4 +.IX Item "-mc68020" +.PD +Generate output for a 68020. This is the default +when the compiler is configured for 68020\-based systems. +It is equivalent to \fB\-march=68020\fR. +.IP "\fB\-m68030\fR" 4 +.IX Item "-m68030" +Generate output for a 68030. This is the default when the compiler is +configured for 68030\-based systems. It is equivalent to +\&\fB\-march=68030\fR. +.IP "\fB\-m68040\fR" 4 +.IX Item "-m68040" +Generate output for a 68040. This is the default when the compiler is +configured for 68040\-based systems. It is equivalent to +\&\fB\-march=68040\fR. +.Sp +This option inhibits the use of 68881/68882 instructions that have to be +emulated by software on the 68040. Use this option if your 68040 does not +have code to emulate those instructions. +.IP "\fB\-m68060\fR" 4 +.IX Item "-m68060" +Generate output for a 68060. This is the default when the compiler is +configured for 68060\-based systems. It is equivalent to +\&\fB\-march=68060\fR. +.Sp +This option inhibits the use of 68020 and 68881/68882 instructions that +have to be emulated by software on the 68060. Use this option if your 68060 +does not have code to emulate those instructions. +.IP "\fB\-mcpu32\fR" 4 +.IX Item "-mcpu32" +Generate output for a \s-1CPU32\s0. This is the default +when the compiler is configured for CPU32\-based systems. +It is equivalent to \fB\-march=cpu32\fR. +.Sp +Use this option for microcontrollers with a +\&\s-1CPU32\s0 or \s-1CPU32+\s0 core, including the 68330, 68331, 68332, 68333, 68334, +68336, 68340, 68341, 68349 and 68360. +.IP "\fB\-m5200\fR" 4 +.IX Item "-m5200" +Generate output for a 520X ColdFire \s-1CPU\s0. This is the default +when the compiler is configured for 520X\-based systems. +It is equivalent to \fB\-mcpu=5206\fR, and is now deprecated +in favor of that option. +.Sp +Use this option for microcontroller with a 5200 core, including +the \s-1MCF5202\s0, \s-1MCF5203\s0, \s-1MCF5204\s0 and \s-1MCF5206\s0. +.IP "\fB\-m5206e\fR" 4 +.IX Item "-m5206e" +Generate output for a 5206e ColdFire \s-1CPU\s0. The option is now +deprecated in favor of the equivalent \fB\-mcpu=5206e\fR. +.IP "\fB\-m528x\fR" 4 +.IX Item "-m528x" +Generate output for a member of the ColdFire 528X family. +The option is now deprecated in favor of the equivalent +\&\fB\-mcpu=528x\fR. +.IP "\fB\-m5307\fR" 4 +.IX Item "-m5307" +Generate output for a ColdFire 5307 \s-1CPU\s0. The option is now deprecated +in favor of the equivalent \fB\-mcpu=5307\fR. +.IP "\fB\-m5407\fR" 4 +.IX Item "-m5407" +Generate output for a ColdFire 5407 \s-1CPU\s0. The option is now deprecated +in favor of the equivalent \fB\-mcpu=5407\fR. +.IP "\fB\-mcfv4e\fR" 4 +.IX Item "-mcfv4e" +Generate output for a ColdFire V4e family \s-1CPU\s0 (e.g. 547x/548x). +This includes use of hardware floating point instructions. +The option is equivalent to \fB\-mcpu=547x\fR, and is now +deprecated in favor of that option. +.IP "\fB\-m68020\-40\fR" 4 +.IX Item "-m68020-40" +Generate output for a 68040, without using any of the new instructions. +This results in code which can run relatively efficiently on either a +68020/68881 or a 68030 or a 68040. The generated code does use the +68881 instructions that are emulated on the 68040. +.Sp +The option is equivalent to \fB\-march=68020\fR \fB\-mtune=68020\-40\fR. +.IP "\fB\-m68020\-60\fR" 4 +.IX Item "-m68020-60" +Generate output for a 68060, without using any of the new instructions. +This results in code which can run relatively efficiently on either a +68020/68881 or a 68030 or a 68040. The generated code does use the +68881 instructions that are emulated on the 68060. +.Sp +The option is equivalent to \fB\-march=68020\fR \fB\-mtune=68020\-60\fR. +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD 0 +.IP "\fB\-m68881\fR" 4 +.IX Item "-m68881" +.PD +Generate floating-point instructions. This is the default for 68020 +and above, and for ColdFire devices that have an \s-1FPU\s0. It defines the +macro \fB_\|_HAVE_68881_\|_\fR on M680x0 targets and \fB_\|_mcffpu_\|_\fR +on ColdFire targets. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Do not generate floating-point instructions; use library calls instead. +This is the default for 68000, 68010, and 68832 targets. It is also +the default for ColdFire devices that have no \s-1FPU\s0. +.IP "\fB\-mdiv\fR" 4 +.IX Item "-mdiv" +.PD 0 +.IP "\fB\-mno\-div\fR" 4 +.IX Item "-mno-div" +.PD +Generate (do not generate) ColdFire hardware divide and remainder +instructions. If \fB\-march\fR is used without \fB\-mcpu\fR, +the default is \*(L"on\*(R" for ColdFire architectures and \*(L"off\*(R" for M680x0 +architectures. Otherwise, the default is taken from the target \s-1CPU\s0 +(either the default \s-1CPU\s0, or the one specified by \fB\-mcpu\fR). For +example, the default is \*(L"off\*(R" for \fB\-mcpu=5206\fR and \*(L"on\*(R" for +\&\fB\-mcpu=5206e\fR. +.Sp +gcc defines the macro \fB_\|_mcfhwdiv_\|_\fR when this option is enabled. +.IP "\fB\-mshort\fR" 4 +.IX Item "-mshort" +Consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide, like \f(CW\*(C`short int\*(C'\fR. +Additionally, parameters passed on the stack are also aligned to a +16\-bit boundary even on targets whose \s-1API\s0 mandates promotion to 32\-bit. +.IP "\fB\-mno\-short\fR" 4 +.IX Item "-mno-short" +Do not consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide. This is the default. +.IP "\fB\-mnobitfield\fR" 4 +.IX Item "-mnobitfield" +.PD 0 +.IP "\fB\-mno\-bitfield\fR" 4 +.IX Item "-mno-bitfield" +.PD +Do not use the bit-field instructions. The \fB\-m68000\fR, \fB\-mcpu32\fR +and \fB\-m5200\fR options imply \fB\-mnobitfield\fR. +.IP "\fB\-mbitfield\fR" 4 +.IX Item "-mbitfield" +Do use the bit-field instructions. The \fB\-m68020\fR option implies +\&\fB\-mbitfield\fR. This is the default if you use a configuration +designed for a 68020. +.IP "\fB\-mrtd\fR" 4 +.IX Item "-mrtd" +Use a different function-calling convention, in which functions +that take a fixed number of arguments return with the \f(CW\*(C`rtd\*(C'\fR +instruction, which pops their arguments while returning. This +saves one instruction in the caller since there is no need to pop +the arguments there. +.Sp +This calling convention is incompatible with the one normally +used on Unix, so you cannot use it if you need to call libraries +compiled with the Unix compiler. +.Sp +Also, you must provide function prototypes for all functions that +take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR); +otherwise incorrect code will be generated for calls to those +functions. +.Sp +In addition, seriously incorrect code will result if you call a +function with too many arguments. (Normally, extra arguments are +harmlessly ignored.) +.Sp +The \f(CW\*(C`rtd\*(C'\fR instruction is supported by the 68010, 68020, 68030, +68040, 68060 and \s-1CPU32\s0 processors, but not by the 68000 or 5200. +.IP "\fB\-mno\-rtd\fR" 4 +.IX Item "-mno-rtd" +Do not use the calling conventions selected by \fB\-mrtd\fR. +This is the default. +.IP "\fB\-malign\-int\fR" 4 +.IX Item "-malign-int" +.PD 0 +.IP "\fB\-mno\-align\-int\fR" 4 +.IX Item "-mno-align-int" +.PD +Control whether \s-1GCC\s0 aligns \f(CW\*(C`int\*(C'\fR, \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`long long\*(C'\fR, +\&\f(CW\*(C`float\*(C'\fR, \f(CW\*(C`double\*(C'\fR, and \f(CW\*(C`long double\*(C'\fR variables on a 32\-bit +boundary (\fB\-malign\-int\fR) or a 16\-bit boundary (\fB\-mno\-align\-int\fR). +Aligning variables on 32\-bit boundaries produces code that runs somewhat +faster on processors with 32\-bit busses at the expense of more memory. +.Sp +\&\fBWarning:\fR if you use the \fB\-malign\-int\fR switch, \s-1GCC\s0 will +align structures containing the above types differently than +most published application binary interface specifications for the m68k. +.IP "\fB\-mpcrel\fR" 4 +.IX Item "-mpcrel" +Use the pc-relative addressing mode of the 68000 directly, instead of +using a global offset table. At present, this option implies \fB\-fpic\fR, +allowing at most a 16\-bit offset for pc-relative addressing. \fB\-fPIC\fR is +not presently supported with \fB\-mpcrel\fR, though this could be supported for +68020 and higher processors. +.IP "\fB\-mno\-strict\-align\fR" 4 +.IX Item "-mno-strict-align" +.PD 0 +.IP "\fB\-mstrict\-align\fR" 4 +.IX Item "-mstrict-align" +.PD +Do not (do) assume that unaligned memory references will be handled by +the system. +.IP "\fB\-msep\-data\fR" 4 +.IX Item "-msep-data" +Generate code that allows the data segment to be located in a different +area of memory from the text segment. This allows for execute in place in +an environment without virtual memory management. This option implies +\&\fB\-fPIC\fR. +.IP "\fB\-mno\-sep\-data\fR" 4 +.IX Item "-mno-sep-data" +Generate code that assumes that the data segment follows the text segment. +This is the default. +.IP "\fB\-mid\-shared\-library\fR" 4 +.IX Item "-mid-shared-library" +Generate code that supports shared libraries via the library \s-1ID\s0 method. +This allows for execute in place and shared libraries in an environment +without virtual memory management. This option implies \fB\-fPIC\fR. +.IP "\fB\-mno\-id\-shared\-library\fR" 4 +.IX Item "-mno-id-shared-library" +Generate code that doesn't assume \s-1ID\s0 based shared libraries are being used. +This is the default. +.IP "\fB\-mshared\-library\-id=n\fR" 4 +.IX Item "-mshared-library-id=n" +Specified the identification number of the \s-1ID\s0 based shared library being +compiled. Specifying a value of 0 will generate more compact code, specifying +other values will force the allocation of that number to the current +library but is no more space or time efficient than omitting this option. +.IP "\fB\-mxgot\fR" 4 +.IX Item "-mxgot" +.PD 0 +.IP "\fB\-mno\-xgot\fR" 4 +.IX Item "-mno-xgot" +.PD +When generating position-independent code for ColdFire, generate code +that works if the \s-1GOT\s0 has more than 8192 entries. This code is +larger and slower than code generated without this option. On M680x0 +processors, this option is not needed; \fB\-fPIC\fR suffices. +.Sp +\&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT\s0. +While this is relatively efficient, it only works if the \s-1GOT\s0 +is smaller than about 64k. Anything larger causes the linker +to report an error such as: +.Sp +.Vb 1 +\& relocation truncated to fit: R_68K_GOT16O foobar +.Ve +.Sp +If this happens, you should recompile your code with \fB\-mxgot\fR. +It should then work with very large GOTs. However, code generated with +\&\fB\-mxgot\fR is less efficient, since it takes 4 instructions to fetch +the value of a global symbol. +.Sp +Note that some linkers, including newer versions of the \s-1GNU\s0 linker, +can create multiple GOTs and sort \s-1GOT\s0 entries. If you have such a linker, +you should only need to use \fB\-mxgot\fR when compiling a single +object file that accesses more than 8192 \s-1GOT\s0 entries. Very few do. +.Sp +These options have no effect unless \s-1GCC\s0 is generating +position-independent code. +.PP +\fIM68hc1x Options\fR +.IX Subsection "M68hc1x Options" +.PP +These are the \fB\-m\fR options defined for the 68hc11 and 68hc12 +microcontrollers. The default values for these options depends on +which style of microcontroller was selected when the compiler was configured; +the defaults for the most common choices are given below. +.IP "\fB\-m6811\fR" 4 +.IX Item "-m6811" +.PD 0 +.IP "\fB\-m68hc11\fR" 4 +.IX Item "-m68hc11" +.PD +Generate output for a 68HC11. This is the default +when the compiler is configured for 68HC11\-based systems. +.IP "\fB\-m6812\fR" 4 +.IX Item "-m6812" +.PD 0 +.IP "\fB\-m68hc12\fR" 4 +.IX Item "-m68hc12" +.PD +Generate output for a 68HC12. This is the default +when the compiler is configured for 68HC12\-based systems. +.IP "\fB\-m68S12\fR" 4 +.IX Item "-m68S12" +.PD 0 +.IP "\fB\-m68hcs12\fR" 4 +.IX Item "-m68hcs12" +.PD +Generate output for a 68HCS12. +.IP "\fB\-mauto\-incdec\fR" 4 +.IX Item "-mauto-incdec" +Enable the use of 68HC12 pre and post auto-increment and auto-decrement +addressing modes. +.IP "\fB\-minmax\fR" 4 +.IX Item "-minmax" +.PD 0 +.IP "\fB\-mnominmax\fR" 4 +.IX Item "-mnominmax" +.PD +Enable the use of 68HC12 min and max instructions. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +.PD 0 +.IP "\fB\-mno\-long\-calls\fR" 4 +.IX Item "-mno-long-calls" +.PD +Treat all calls as being far away (near). If calls are assumed to be +far away, the compiler will use the \f(CW\*(C`call\*(C'\fR instruction to +call a function and the \f(CW\*(C`rtc\*(C'\fR instruction for returning. +.IP "\fB\-mshort\fR" 4 +.IX Item "-mshort" +Consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide, like \f(CW\*(C`short int\*(C'\fR. +.IP "\fB\-msoft\-reg\-count=\fR\fIcount\fR" 4 +.IX Item "-msoft-reg-count=count" +Specify the number of pseudo-soft registers which are used for the +code generation. The maximum number is 32. Using more pseudo-soft +register may or may not result in better code depending on the program. +The default is 4 for 68HC11 and 2 for 68HC12. +.PP +\fIMCore Options\fR +.IX Subsection "MCore Options" +.PP +These are the \fB\-m\fR options defined for the Motorola M*Core +processors. +.IP "\fB\-mhardlit\fR" 4 +.IX Item "-mhardlit" +.PD 0 +.IP "\fB\-mno\-hardlit\fR" 4 +.IX Item "-mno-hardlit" +.PD +Inline constants into the code stream if it can be done in two +instructions or less. +.IP "\fB\-mdiv\fR" 4 +.IX Item "-mdiv" +.PD 0 +.IP "\fB\-mno\-div\fR" 4 +.IX Item "-mno-div" +.PD +Use the divide instruction. (Enabled by default). +.IP "\fB\-mrelax\-immediate\fR" 4 +.IX Item "-mrelax-immediate" +.PD 0 +.IP "\fB\-mno\-relax\-immediate\fR" 4 +.IX Item "-mno-relax-immediate" +.PD +Allow arbitrary sized immediates in bit operations. +.IP "\fB\-mwide\-bitfields\fR" 4 +.IX Item "-mwide-bitfields" +.PD 0 +.IP "\fB\-mno\-wide\-bitfields\fR" 4 +.IX Item "-mno-wide-bitfields" +.PD +Always treat bit-fields as int-sized. +.IP "\fB\-m4byte\-functions\fR" 4 +.IX Item "-m4byte-functions" +.PD 0 +.IP "\fB\-mno\-4byte\-functions\fR" 4 +.IX Item "-mno-4byte-functions" +.PD +Force all functions to be aligned to a four byte boundary. +.IP "\fB\-mcallgraph\-data\fR" 4 +.IX Item "-mcallgraph-data" +.PD 0 +.IP "\fB\-mno\-callgraph\-data\fR" 4 +.IX Item "-mno-callgraph-data" +.PD +Emit callgraph information. +.IP "\fB\-mslow\-bytes\fR" 4 +.IX Item "-mslow-bytes" +.PD 0 +.IP "\fB\-mno\-slow\-bytes\fR" 4 +.IX Item "-mno-slow-bytes" +.PD +Prefer word access when reading byte quantities. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +.PD 0 +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +.PD +Generate code for a little endian target. +.IP "\fB\-m210\fR" 4 +.IX Item "-m210" +.PD 0 +.IP "\fB\-m340\fR" 4 +.IX Item "-m340" +.PD +Generate code for the 210 processor. +.IP "\fB\-mno\-lsim\fR" 4 +.IX Item "-mno-lsim" +Assume that run-time support has been provided and so omit the +simulator library (\fIlibsim.a)\fR from the linker command line. +.IP "\fB\-mstack\-increment=\fR\fIsize\fR" 4 +.IX Item "-mstack-increment=size" +Set the maximum amount for a single stack increment operation. Large +values can increase the speed of programs which contain functions +that need a large amount of stack space, but they can also trigger a +segmentation fault if the stack is extended too much. The default +value is 0x1000. +.PP +\fIMeP Options\fR +.IX Subsection "MeP Options" +.IP "\fB\-mabsdiff\fR" 4 +.IX Item "-mabsdiff" +Enables the \f(CW\*(C`abs\*(C'\fR instruction, which is the absolute difference +between two registers. +.IP "\fB\-mall\-opts\fR" 4 +.IX Item "-mall-opts" +Enables all the optional instructions \- average, multiply, divide, bit +operations, leading zero, absolute difference, min/max, clip, and +saturation. +.IP "\fB\-maverage\fR" 4 +.IX Item "-maverage" +Enables the \f(CW\*(C`ave\*(C'\fR instruction, which computes the average of two +registers. +.IP "\fB\-mbased=\fR\fIn\fR" 4 +.IX Item "-mbased=n" +Variables of size \fIn\fR bytes or smaller will be placed in the +\&\f(CW\*(C`.based\*(C'\fR section by default. Based variables use the \f(CW$tp\fR +register as a base register, and there is a 128 byte limit to the +\&\f(CW\*(C`.based\*(C'\fR section. +.IP "\fB\-mbitops\fR" 4 +.IX Item "-mbitops" +Enables the bit operation instructions \- bit test (\f(CW\*(C`btstm\*(C'\fR), set +(\f(CW\*(C`bsetm\*(C'\fR), clear (\f(CW\*(C`bclrm\*(C'\fR), invert (\f(CW\*(C`bnotm\*(C'\fR), and +test-and-set (\f(CW\*(C`tas\*(C'\fR). +.IP "\fB\-mc=\fR\fIname\fR" 4 +.IX Item "-mc=name" +Selects which section constant data will be placed in. \fIname\fR may +be \f(CW\*(C`tiny\*(C'\fR, \f(CW\*(C`near\*(C'\fR, or \f(CW\*(C`far\*(C'\fR. +.IP "\fB\-mclip\fR" 4 +.IX Item "-mclip" +Enables the \f(CW\*(C`clip\*(C'\fR instruction. Note that \f(CW\*(C`\-mclip\*(C'\fR is not +useful unless you also provide \f(CW\*(C`\-mminmax\*(C'\fR. +.IP "\fB\-mconfig=\fR\fIname\fR" 4 +.IX Item "-mconfig=name" +Selects one of the build-in core configurations. Each MeP chip has +one or more modules in it; each module has a core \s-1CPU\s0 and a variety of +coprocessors, optional instructions, and peripherals. The +\&\f(CW\*(C`MeP\-Integrator\*(C'\fR tool, not part of \s-1GCC\s0, provides these +configurations through this option; using this option is the same as +using all the corresponding command line options. The default +configuration is \f(CW\*(C`default\*(C'\fR. +.IP "\fB\-mcop\fR" 4 +.IX Item "-mcop" +Enables the coprocessor instructions. By default, this is a 32\-bit +coprocessor. Note that the coprocessor is normally enabled via the +\&\f(CW\*(C`\-mconfig=\*(C'\fR option. +.IP "\fB\-mcop32\fR" 4 +.IX Item "-mcop32" +Enables the 32\-bit coprocessor's instructions. +.IP "\fB\-mcop64\fR" 4 +.IX Item "-mcop64" +Enables the 64\-bit coprocessor's instructions. +.IP "\fB\-mivc2\fR" 4 +.IX Item "-mivc2" +Enables \s-1IVC2\s0 scheduling. \s-1IVC2\s0 is a 64\-bit \s-1VLIW\s0 coprocessor. +.IP "\fB\-mdc\fR" 4 +.IX Item "-mdc" +Causes constant variables to be placed in the \f(CW\*(C`.near\*(C'\fR section. +.IP "\fB\-mdiv\fR" 4 +.IX Item "-mdiv" +Enables the \f(CW\*(C`div\*(C'\fR and \f(CW\*(C`divu\*(C'\fR instructions. +.IP "\fB\-meb\fR" 4 +.IX Item "-meb" +Generate big-endian code. +.IP "\fB\-mel\fR" 4 +.IX Item "-mel" +Generate little-endian code. +.IP "\fB\-mio\-volatile\fR" 4 +.IX Item "-mio-volatile" +Tells the compiler that any variable marked with the \f(CW\*(C`io\*(C'\fR +attribute is to be considered volatile. +.IP "\fB\-ml\fR" 4 +.IX Item "-ml" +Causes variables to be assigned to the \f(CW\*(C`.far\*(C'\fR section by default. +.IP "\fB\-mleadz\fR" 4 +.IX Item "-mleadz" +Enables the \f(CW\*(C`leadz\*(C'\fR (leading zero) instruction. +.IP "\fB\-mm\fR" 4 +.IX Item "-mm" +Causes variables to be assigned to the \f(CW\*(C`.near\*(C'\fR section by default. +.IP "\fB\-mminmax\fR" 4 +.IX Item "-mminmax" +Enables the \f(CW\*(C`min\*(C'\fR and \f(CW\*(C`max\*(C'\fR instructions. +.IP "\fB\-mmult\fR" 4 +.IX Item "-mmult" +Enables the multiplication and multiply-accumulate instructions. +.IP "\fB\-mno\-opts\fR" 4 +.IX Item "-mno-opts" +Disables all the optional instructions enabled by \f(CW\*(C`\-mall\-opts\*(C'\fR. +.IP "\fB\-mrepeat\fR" 4 +.IX Item "-mrepeat" +Enables the \f(CW\*(C`repeat\*(C'\fR and \f(CW\*(C`erepeat\*(C'\fR instructions, used for +low-overhead looping. +.IP "\fB\-ms\fR" 4 +.IX Item "-ms" +Causes all variables to default to the \f(CW\*(C`.tiny\*(C'\fR section. Note +that there is a 65536 byte limit to this section. Accesses to these +variables use the \f(CW%gp\fR base register. +.IP "\fB\-msatur\fR" 4 +.IX Item "-msatur" +Enables the saturation instructions. Note that the compiler does not +currently generate these itself, but this option is included for +compatibility with other tools, like \f(CW\*(C`as\*(C'\fR. +.IP "\fB\-msdram\fR" 4 +.IX Item "-msdram" +Link the SDRAM-based runtime instead of the default ROM-based runtime. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Link the simulator runtime libraries. +.IP "\fB\-msimnovec\fR" 4 +.IX Item "-msimnovec" +Link the simulator runtime libraries, excluding built-in support +for reset and exception vectors and tables. +.IP "\fB\-mtf\fR" 4 +.IX Item "-mtf" +Causes all functions to default to the \f(CW\*(C`.far\*(C'\fR section. Without +this option, functions default to the \f(CW\*(C`.near\*(C'\fR section. +.IP "\fB\-mtiny=\fR\fIn\fR" 4 +.IX Item "-mtiny=n" +Variables that are \fIn\fR bytes or smaller will be allocated to the +\&\f(CW\*(C`.tiny\*(C'\fR section. These variables use the \f(CW$gp\fR base +register. The default for this option is 4, but note that there's a +65536 byte limit to the \f(CW\*(C`.tiny\*(C'\fR section. +.PP +\fIMicroBlaze Options\fR +.IX Subsection "MicroBlaze Options" +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Use software emulation for floating point (default). +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +Use hardware floating point instructions. +.IP "\fB\-mmemcpy\fR" 4 +.IX Item "-mmemcpy" +Do not optimize block moves, use \f(CW\*(C`memcpy\*(C'\fR. +.IP "\fB\-mno\-clearbss\fR" 4 +.IX Item "-mno-clearbss" +This option is deprecated. Use \fB\-fno\-zero\-initialized\-in\-bss\fR instead. +.IP "\fB\-mcpu=\fR\fIcpu-type\fR" 4 +.IX Item "-mcpu=cpu-type" +Use features of and schedule code for given \s-1CPU\s0. +Supported values are in the format \fBv\fR\fIX\fR\fB.\fR\fI\s-1YY\s0\fR\fB.\fR\fIZ\fR, +where \fIX\fR is a major version, \fI\s-1YY\s0\fR is the minor version, and +\&\fIZ\fR is compatibility code. Example values are \fBv3.00.a\fR, +\&\fBv4.00.b\fR, \fBv5.00.a\fR, \fBv5.00.b\fR, \fBv5.00.b\fR, \fBv6.00.a\fR. +.IP "\fB\-mxl\-soft\-mul\fR" 4 +.IX Item "-mxl-soft-mul" +Use software multiply emulation (default). +.IP "\fB\-mxl\-soft\-div\fR" 4 +.IX Item "-mxl-soft-div" +Use software emulation for divides (default). +.IP "\fB\-mxl\-barrel\-shift\fR" 4 +.IX Item "-mxl-barrel-shift" +Use the hardware barrel shifter. +.IP "\fB\-mxl\-pattern\-compare\fR" 4 +.IX Item "-mxl-pattern-compare" +Use pattern compare instructions. +.IP "\fB\-msmall\-divides\fR" 4 +.IX Item "-msmall-divides" +Use table lookup optimization for small signed integer divisions. +.IP "\fB\-mxl\-stack\-check\fR" 4 +.IX Item "-mxl-stack-check" +This option is deprecated. Use \-fstack\-check instead. +.IP "\fB\-mxl\-gp\-opt\fR" 4 +.IX Item "-mxl-gp-opt" +Use \s-1GP\s0 relative sdata/sbss sections. +.IP "\fB\-mxl\-multiply\-high\fR" 4 +.IX Item "-mxl-multiply-high" +Use multiply high instructions for high part of 32x32 multiply. +.IP "\fB\-mxl\-float\-convert\fR" 4 +.IX Item "-mxl-float-convert" +Use hardware floating point conversion instructions. +.IP "\fB\-mxl\-float\-sqrt\fR" 4 +.IX Item "-mxl-float-sqrt" +Use hardware floating point square root instruction. +.IP "\fB\-mxl\-mode\-\fR\fIapp-model\fR" 4 +.IX Item "-mxl-mode-app-model" +Select application model \fIapp-model\fR. Valid models are +.RS 4 +.IP "\fBexecutable\fR" 4 +.IX Item "executable" +normal executable (default), uses startup code \fIcrt0.o\fR. +.IP "\fBxmdstub\fR" 4 +.IX Item "xmdstub" +for use with Xilinx Microprocessor Debugger (\s-1XMD\s0) based +software intrusive debug agent called xmdstub. This uses startup file +\&\fIcrt1.o\fR and sets the start address of the program to be 0x800. +.IP "\fBbootstrap\fR" 4 +.IX Item "bootstrap" +for applications that are loaded using a bootloader. +This model uses startup file \fIcrt2.o\fR which does not contain a processor +reset vector handler. This is suitable for transferring control on a +processor reset to the bootloader rather than the application. +.IP "\fBnovectors\fR" 4 +.IX Item "novectors" +for applications that do not require any of the +MicroBlaze vectors. This option may be useful for applications running +within a monitoring application. This model uses \fIcrt3.o\fR as a startup file. +.RE +.RS 4 +.Sp +Option \fB\-xl\-mode\-\fR\fIapp-model\fR is a deprecated alias for +\&\fB\-mxl\-mode\-\fR\fIapp-model\fR. +.RE +.PP +\fI\s-1MIPS\s0 Options\fR +.IX Subsection "MIPS Options" +.IP "\fB\-EB\fR" 4 +.IX Item "-EB" +Generate big-endian code. +.IP "\fB\-EL\fR" 4 +.IX Item "-EL" +Generate little-endian code. This is the default for \fBmips*el\-*\-*\fR +configurations. +.IP "\fB\-march=\fR\fIarch\fR" 4 +.IX Item "-march=arch" +Generate code that will run on \fIarch\fR, which can be the name of a +generic \s-1MIPS\s0 \s-1ISA\s0, or the name of a particular processor. +The \s-1ISA\s0 names are: +\&\fBmips1\fR, \fBmips2\fR, \fBmips3\fR, \fBmips4\fR, +\&\fBmips32\fR, \fBmips32r2\fR, \fBmips64\fR and \fBmips64r2\fR. +The processor names are: +\&\fB4kc\fR, \fB4km\fR, \fB4kp\fR, \fB4ksc\fR, +\&\fB4kec\fR, \fB4kem\fR, \fB4kep\fR, \fB4ksd\fR, +\&\fB5kc\fR, \fB5kf\fR, +\&\fB20kc\fR, +\&\fB24kc\fR, \fB24kf2_1\fR, \fB24kf1_1\fR, +\&\fB24kec\fR, \fB24kef2_1\fR, \fB24kef1_1\fR, +\&\fB34kc\fR, \fB34kf2_1\fR, \fB34kf1_1\fR, +\&\fB74kc\fR, \fB74kf2_1\fR, \fB74kf1_1\fR, \fB74kf3_2\fR, +\&\fB1004kc\fR, \fB1004kf2_1\fR, \fB1004kf1_1\fR, +\&\fBloongson2e\fR, \fBloongson2f\fR, \fBloongson3a\fR, +\&\fBm4k\fR, +\&\fBocteon\fR, +\&\fBorion\fR, +\&\fBr2000\fR, \fBr3000\fR, \fBr3900\fR, \fBr4000\fR, \fBr4400\fR, +\&\fBr4600\fR, \fBr4650\fR, \fBr6000\fR, \fBr8000\fR, +\&\fBrm7000\fR, \fBrm9000\fR, +\&\fBr10000\fR, \fBr12000\fR, \fBr14000\fR, \fBr16000\fR, +\&\fBsb1\fR, +\&\fBsr71000\fR, +\&\fBvr4100\fR, \fBvr4111\fR, \fBvr4120\fR, \fBvr4130\fR, \fBvr4300\fR, +\&\fBvr5000\fR, \fBvr5400\fR, \fBvr5500\fR +and \fBxlr\fR. +The special value \fBfrom-abi\fR selects the +most compatible architecture for the selected \s-1ABI\s0 (that is, +\&\fBmips1\fR for 32\-bit ABIs and \fBmips3\fR for 64\-bit ABIs). +.Sp +Native Linux/GNU toolchains also support the value \fBnative\fR, +which selects the best architecture option for the host processor. +\&\fB\-march=native\fR has no effect if \s-1GCC\s0 does not recognize +the processor. +.Sp +In processor names, a final \fB000\fR can be abbreviated as \fBk\fR +(for example, \fB\-march=r2k\fR). Prefixes are optional, and +\&\fBvr\fR may be written \fBr\fR. +.Sp +Names of the form \fIn\fR\fBf2_1\fR refer to processors with +FPUs clocked at half the rate of the core, names of the form +\&\fIn\fR\fBf1_1\fR refer to processors with FPUs clocked at the same +rate as the core, and names of the form \fIn\fR\fBf3_2\fR refer to +processors with FPUs clocked a ratio of 3:2 with respect to the core. +For compatibility reasons, \fIn\fR\fBf\fR is accepted as a synonym +for \fIn\fR\fBf2_1\fR while \fIn\fR\fBx\fR and \fIb\fR\fBfx\fR are +accepted as synonyms for \fIn\fR\fBf1_1\fR. +.Sp +\&\s-1GCC\s0 defines two macros based on the value of this option. The first +is \fB_MIPS_ARCH\fR, which gives the name of target architecture, as +a string. The second has the form \fB_MIPS_ARCH_\fR\fIfoo\fR, +where \fIfoo\fR is the capitalized value of \fB_MIPS_ARCH\fR. +For example, \fB\-march=r2000\fR will set \fB_MIPS_ARCH\fR +to \fB\*(L"r2000\*(R"\fR and define the macro \fB_MIPS_ARCH_R2000\fR. +.Sp +Note that the \fB_MIPS_ARCH\fR macro uses the processor names given +above. In other words, it will have the full prefix and will not +abbreviate \fB000\fR as \fBk\fR. In the case of \fBfrom-abi\fR, +the macro names the resolved architecture (either \fB\*(L"mips1\*(R"\fR or +\&\fB\*(L"mips3\*(R"\fR). It names the default architecture when no +\&\fB\-march\fR option is given. +.IP "\fB\-mtune=\fR\fIarch\fR" 4 +.IX Item "-mtune=arch" +Optimize for \fIarch\fR. Among other things, this option controls +the way instructions are scheduled, and the perceived cost of arithmetic +operations. The list of \fIarch\fR values is the same as for +\&\fB\-march\fR. +.Sp +When this option is not used, \s-1GCC\s0 will optimize for the processor +specified by \fB\-march\fR. By using \fB\-march\fR and +\&\fB\-mtune\fR together, it is possible to generate code that will +run on a family of processors, but optimize the code for one +particular member of that family. +.Sp +\&\fB\-mtune\fR defines the macros \fB_MIPS_TUNE\fR and +\&\fB_MIPS_TUNE_\fR\fIfoo\fR, which work in the same way as the +\&\fB\-march\fR ones described above. +.IP "\fB\-mips1\fR" 4 +.IX Item "-mips1" +Equivalent to \fB\-march=mips1\fR. +.IP "\fB\-mips2\fR" 4 +.IX Item "-mips2" +Equivalent to \fB\-march=mips2\fR. +.IP "\fB\-mips3\fR" 4 +.IX Item "-mips3" +Equivalent to \fB\-march=mips3\fR. +.IP "\fB\-mips4\fR" 4 +.IX Item "-mips4" +Equivalent to \fB\-march=mips4\fR. +.IP "\fB\-mips32\fR" 4 +.IX Item "-mips32" +Equivalent to \fB\-march=mips32\fR. +.IP "\fB\-mips32r2\fR" 4 +.IX Item "-mips32r2" +Equivalent to \fB\-march=mips32r2\fR. +.IP "\fB\-mips64\fR" 4 +.IX Item "-mips64" +Equivalent to \fB\-march=mips64\fR. +.IP "\fB\-mips64r2\fR" 4 +.IX Item "-mips64r2" +Equivalent to \fB\-march=mips64r2\fR. +.IP "\fB\-mips16\fR" 4 +.IX Item "-mips16" +.PD 0 +.IP "\fB\-mno\-mips16\fR" 4 +.IX Item "-mno-mips16" +.PD +Generate (do not generate) \s-1MIPS16\s0 code. If \s-1GCC\s0 is targetting a +\&\s-1MIPS32\s0 or \s-1MIPS64\s0 architecture, it will make use of the MIPS16e \s-1ASE\s0. +.Sp +\&\s-1MIPS16\s0 code generation can also be controlled on a per-function basis +by means of \f(CW\*(C`mips16\*(C'\fR and \f(CW\*(C`nomips16\*(C'\fR attributes. +.IP "\fB\-mflip\-mips16\fR" 4 +.IX Item "-mflip-mips16" +Generate \s-1MIPS16\s0 code on alternating functions. This option is provided +for regression testing of mixed MIPS16/non\-MIPS16 code generation, and is +not intended for ordinary use in compiling user code. +.IP "\fB\-minterlink\-mips16\fR" 4 +.IX Item "-minterlink-mips16" +.PD 0 +.IP "\fB\-mno\-interlink\-mips16\fR" 4 +.IX Item "-mno-interlink-mips16" +.PD +Require (do not require) that non\-MIPS16 code be link-compatible with +\&\s-1MIPS16\s0 code. +.Sp +For example, non\-MIPS16 code cannot jump directly to \s-1MIPS16\s0 code; +it must either use a call or an indirect jump. \fB\-minterlink\-mips16\fR +therefore disables direct jumps unless \s-1GCC\s0 knows that the target of the +jump is not \s-1MIPS16\s0. +.IP "\fB\-mabi=32\fR" 4 +.IX Item "-mabi=32" +.PD 0 +.IP "\fB\-mabi=o64\fR" 4 +.IX Item "-mabi=o64" +.IP "\fB\-mabi=n32\fR" 4 +.IX Item "-mabi=n32" +.IP "\fB\-mabi=64\fR" 4 +.IX Item "-mabi=64" +.IP "\fB\-mabi=eabi\fR" 4 +.IX Item "-mabi=eabi" +.PD +Generate code for the given \s-1ABI\s0. +.Sp +Note that the \s-1EABI\s0 has a 32\-bit and a 64\-bit variant. \s-1GCC\s0 normally +generates 64\-bit code when you select a 64\-bit architecture, but you +can use \fB\-mgp32\fR to get 32\-bit code instead. +.Sp +For information about the O64 \s-1ABI\s0, see +<\fBhttp://gcc.gnu.org/projects/mipso64\-abi.html\fR>. +.Sp +\&\s-1GCC\s0 supports a variant of the o32 \s-1ABI\s0 in which floating-point registers +are 64 rather than 32 bits wide. You can select this combination with +\&\fB\-mabi=32\fR \fB\-mfp64\fR. This \s-1ABI\s0 relies on the \fBmthc1\fR +and \fBmfhc1\fR instructions and is therefore only supported for +\&\s-1MIPS32R2\s0 processors. +.Sp +The register assignments for arguments and return values remain the +same, but each scalar value is passed in a single 64\-bit register +rather than a pair of 32\-bit registers. For example, scalar +floating-point values are returned in \fB\f(CB$f0\fB\fR only, not a +\&\fB\f(CB$f0\fB\fR/\fB\f(CB$f1\fB\fR pair. The set of call-saved registers also +remains the same, but all 64 bits are saved. +.IP "\fB\-mabicalls\fR" 4 +.IX Item "-mabicalls" +.PD 0 +.IP "\fB\-mno\-abicalls\fR" 4 +.IX Item "-mno-abicalls" +.PD +Generate (do not generate) code that is suitable for SVR4\-style +dynamic objects. \fB\-mabicalls\fR is the default for SVR4\-based +systems. +.IP "\fB\-mshared\fR" 4 +.IX Item "-mshared" +.PD 0 +.IP "\fB\-mno\-shared\fR" 4 +.IX Item "-mno-shared" +.PD +Generate (do not generate) code that is fully position-independent, +and that can therefore be linked into shared libraries. This option +only affects \fB\-mabicalls\fR. +.Sp +All \fB\-mabicalls\fR code has traditionally been position-independent, +regardless of options like \fB\-fPIC\fR and \fB\-fpic\fR. However, +as an extension, the \s-1GNU\s0 toolchain allows executables to use absolute +accesses for locally-binding symbols. It can also use shorter \s-1GP\s0 +initialization sequences and generate direct calls to locally-defined +functions. This mode is selected by \fB\-mno\-shared\fR. +.Sp +\&\fB\-mno\-shared\fR depends on binutils 2.16 or higher and generates +objects that can only be linked by the \s-1GNU\s0 linker. However, the option +does not affect the \s-1ABI\s0 of the final executable; it only affects the \s-1ABI\s0 +of relocatable objects. Using \fB\-mno\-shared\fR will generally make +executables both smaller and quicker. +.Sp +\&\fB\-mshared\fR is the default. +.IP "\fB\-mplt\fR" 4 +.IX Item "-mplt" +.PD 0 +.IP "\fB\-mno\-plt\fR" 4 +.IX Item "-mno-plt" +.PD +Assume (do not assume) that the static and dynamic linkers +support PLTs and copy relocations. This option only affects +\&\fB\-mno\-shared \-mabicalls\fR. For the n64 \s-1ABI\s0, this option +has no effect without \fB\-msym32\fR. +.Sp +You can make \fB\-mplt\fR the default by configuring +\&\s-1GCC\s0 with \fB\-\-with\-mips\-plt\fR. The default is +\&\fB\-mno\-plt\fR otherwise. +.IP "\fB\-mxgot\fR" 4 +.IX Item "-mxgot" +.PD 0 +.IP "\fB\-mno\-xgot\fR" 4 +.IX Item "-mno-xgot" +.PD +Lift (do not lift) the usual restrictions on the size of the global +offset table. +.Sp +\&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT\s0. +While this is relatively efficient, it will only work if the \s-1GOT\s0 +is smaller than about 64k. Anything larger will cause the linker +to report an error such as: +.Sp +.Vb 1 +\& relocation truncated to fit: R_MIPS_GOT16 foobar +.Ve +.Sp +If this happens, you should recompile your code with \fB\-mxgot\fR. +It should then work with very large GOTs, although it will also be +less efficient, since it will take three instructions to fetch the +value of a global symbol. +.Sp +Note that some linkers can create multiple GOTs. If you have such a +linker, you should only need to use \fB\-mxgot\fR when a single object +file accesses more than 64k's worth of \s-1GOT\s0 entries. Very few do. +.Sp +These options have no effect unless \s-1GCC\s0 is generating position +independent code. +.IP "\fB\-mgp32\fR" 4 +.IX Item "-mgp32" +Assume that general-purpose registers are 32 bits wide. +.IP "\fB\-mgp64\fR" 4 +.IX Item "-mgp64" +Assume that general-purpose registers are 64 bits wide. +.IP "\fB\-mfp32\fR" 4 +.IX Item "-mfp32" +Assume that floating-point registers are 32 bits wide. +.IP "\fB\-mfp64\fR" 4 +.IX Item "-mfp64" +Assume that floating-point registers are 64 bits wide. +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +Use floating-point coprocessor instructions. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Do not use floating-point coprocessor instructions. Implement +floating-point calculations using library calls instead. +.IP "\fB\-msingle\-float\fR" 4 +.IX Item "-msingle-float" +Assume that the floating-point coprocessor only supports single-precision +operations. +.IP "\fB\-mdouble\-float\fR" 4 +.IX Item "-mdouble-float" +Assume that the floating-point coprocessor supports double-precision +operations. This is the default. +.IP "\fB\-mllsc\fR" 4 +.IX Item "-mllsc" +.PD 0 +.IP "\fB\-mno\-llsc\fR" 4 +.IX Item "-mno-llsc" +.PD +Use (do not use) \fBll\fR, \fBsc\fR, and \fBsync\fR instructions to +implement atomic memory built-in functions. When neither option is +specified, \s-1GCC\s0 will use the instructions if the target architecture +supports them. +.Sp +\&\fB\-mllsc\fR is useful if the runtime environment can emulate the +instructions and \fB\-mno\-llsc\fR can be useful when compiling for +nonstandard ISAs. You can make either option the default by +configuring \s-1GCC\s0 with \fB\-\-with\-llsc\fR and \fB\-\-without\-llsc\fR +respectively. \fB\-\-with\-llsc\fR is the default for some +configurations; see the installation documentation for details. +.IP "\fB\-mdsp\fR" 4 +.IX Item "-mdsp" +.PD 0 +.IP "\fB\-mno\-dsp\fR" 4 +.IX Item "-mno-dsp" +.PD +Use (do not use) revision 1 of the \s-1MIPS\s0 \s-1DSP\s0 \s-1ASE\s0. + This option defines the +preprocessor macro \fB_\|_mips_dsp\fR. It also defines +\&\fB_\|_mips_dsp_rev\fR to 1. +.IP "\fB\-mdspr2\fR" 4 +.IX Item "-mdspr2" +.PD 0 +.IP "\fB\-mno\-dspr2\fR" 4 +.IX Item "-mno-dspr2" +.PD +Use (do not use) revision 2 of the \s-1MIPS\s0 \s-1DSP\s0 \s-1ASE\s0. + This option defines the +preprocessor macros \fB_\|_mips_dsp\fR and \fB_\|_mips_dspr2\fR. +It also defines \fB_\|_mips_dsp_rev\fR to 2. +.IP "\fB\-msmartmips\fR" 4 +.IX Item "-msmartmips" +.PD 0 +.IP "\fB\-mno\-smartmips\fR" 4 +.IX Item "-mno-smartmips" +.PD +Use (do not use) the \s-1MIPS\s0 SmartMIPS \s-1ASE\s0. +.IP "\fB\-mpaired\-single\fR" 4 +.IX Item "-mpaired-single" +.PD 0 +.IP "\fB\-mno\-paired\-single\fR" 4 +.IX Item "-mno-paired-single" +.PD +Use (do not use) paired-single floating-point instructions. + This option requires +hardware floating-point support to be enabled. +.IP "\fB\-mdmx\fR" 4 +.IX Item "-mdmx" +.PD 0 +.IP "\fB\-mno\-mdmx\fR" 4 +.IX Item "-mno-mdmx" +.PD +Use (do not use) \s-1MIPS\s0 Digital Media Extension instructions. +This option can only be used when generating 64\-bit code and requires +hardware floating-point support to be enabled. +.IP "\fB\-mips3d\fR" 4 +.IX Item "-mips3d" +.PD 0 +.IP "\fB\-mno\-mips3d\fR" 4 +.IX Item "-mno-mips3d" +.PD +Use (do not use) the \s-1MIPS\-3D\s0 \s-1ASE\s0. +The option \fB\-mips3d\fR implies \fB\-mpaired\-single\fR. +.IP "\fB\-mmt\fR" 4 +.IX Item "-mmt" +.PD 0 +.IP "\fB\-mno\-mt\fR" 4 +.IX Item "-mno-mt" +.PD +Use (do not use) \s-1MT\s0 Multithreading instructions. +.IP "\fB\-mlong64\fR" 4 +.IX Item "-mlong64" +Force \f(CW\*(C`long\*(C'\fR types to be 64 bits wide. See \fB\-mlong32\fR for +an explanation of the default and the way that the pointer size is +determined. +.IP "\fB\-mlong32\fR" 4 +.IX Item "-mlong32" +Force \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`int\*(C'\fR, and pointer types to be 32 bits wide. +.Sp +The default size of \f(CW\*(C`int\*(C'\fRs, \f(CW\*(C`long\*(C'\fRs and pointers depends on +the \s-1ABI\s0. All the supported ABIs use 32\-bit \f(CW\*(C`int\*(C'\fRs. The n64 \s-1ABI\s0 +uses 64\-bit \f(CW\*(C`long\*(C'\fRs, as does the 64\-bit \s-1EABI\s0; the others use +32\-bit \f(CW\*(C`long\*(C'\fRs. Pointers are the same size as \f(CW\*(C`long\*(C'\fRs, +or the same size as integer registers, whichever is smaller. +.IP "\fB\-msym32\fR" 4 +.IX Item "-msym32" +.PD 0 +.IP "\fB\-mno\-sym32\fR" 4 +.IX Item "-mno-sym32" +.PD +Assume (do not assume) that all symbols have 32\-bit values, regardless +of the selected \s-1ABI\s0. This option is useful in combination with +\&\fB\-mabi=64\fR and \fB\-mno\-abicalls\fR because it allows \s-1GCC\s0 +to generate shorter and faster references to symbolic addresses. +.IP "\fB\-G\fR \fInum\fR" 4 +.IX Item "-G num" +Put definitions of externally-visible data in a small data section +if that data is no bigger than \fInum\fR bytes. \s-1GCC\s0 can then access +the data more efficiently; see \fB\-mgpopt\fR for details. +.Sp +The default \fB\-G\fR option depends on the configuration. +.IP "\fB\-mlocal\-sdata\fR" 4 +.IX Item "-mlocal-sdata" +.PD 0 +.IP "\fB\-mno\-local\-sdata\fR" 4 +.IX Item "-mno-local-sdata" +.PD +Extend (do not extend) the \fB\-G\fR behavior to local data too, +such as to static variables in C. \fB\-mlocal\-sdata\fR is the +default for all configurations. +.Sp +If the linker complains that an application is using too much small data, +you might want to try rebuilding the less performance-critical parts with +\&\fB\-mno\-local\-sdata\fR. You might also want to build large +libraries with \fB\-mno\-local\-sdata\fR, so that the libraries leave +more room for the main program. +.IP "\fB\-mextern\-sdata\fR" 4 +.IX Item "-mextern-sdata" +.PD 0 +.IP "\fB\-mno\-extern\-sdata\fR" 4 +.IX Item "-mno-extern-sdata" +.PD +Assume (do not assume) that externally-defined data will be in +a small data section if that data is within the \fB\-G\fR limit. +\&\fB\-mextern\-sdata\fR is the default for all configurations. +.Sp +If you compile a module \fIMod\fR with \fB\-mextern\-sdata\fR \fB\-G\fR +\&\fInum\fR \fB\-mgpopt\fR, and \fIMod\fR references a variable \fIVar\fR +that is no bigger than \fInum\fR bytes, you must make sure that \fIVar\fR +is placed in a small data section. If \fIVar\fR is defined by another +module, you must either compile that module with a high-enough +\&\fB\-G\fR setting or attach a \f(CW\*(C`section\*(C'\fR attribute to \fIVar\fR's +definition. If \fIVar\fR is common, you must link the application +with a high-enough \fB\-G\fR setting. +.Sp +The easiest way of satisfying these restrictions is to compile +and link every module with the same \fB\-G\fR option. However, +you may wish to build a library that supports several different +small data limits. You can do this by compiling the library with +the highest supported \fB\-G\fR setting and additionally using +\&\fB\-mno\-extern\-sdata\fR to stop the library from making assumptions +about externally-defined data. +.IP "\fB\-mgpopt\fR" 4 +.IX Item "-mgpopt" +.PD 0 +.IP "\fB\-mno\-gpopt\fR" 4 +.IX Item "-mno-gpopt" +.PD +Use (do not use) GP-relative accesses for symbols that are known to be +in a small data section; see \fB\-G\fR, \fB\-mlocal\-sdata\fR and +\&\fB\-mextern\-sdata\fR. \fB\-mgpopt\fR is the default for all +configurations. +.Sp +\&\fB\-mno\-gpopt\fR is useful for cases where the \f(CW$gp\fR register +might not hold the value of \f(CW\*(C`_gp\*(C'\fR. For example, if the code is +part of a library that might be used in a boot monitor, programs that +call boot monitor routines will pass an unknown value in \f(CW$gp\fR. +(In such situations, the boot monitor itself would usually be compiled +with \fB\-G0\fR.) +.Sp +\&\fB\-mno\-gpopt\fR implies \fB\-mno\-local\-sdata\fR and +\&\fB\-mno\-extern\-sdata\fR. +.IP "\fB\-membedded\-data\fR" 4 +.IX Item "-membedded-data" +.PD 0 +.IP "\fB\-mno\-embedded\-data\fR" 4 +.IX Item "-mno-embedded-data" +.PD +Allocate variables to the read-only data section first if possible, then +next in the small data section if possible, otherwise in data. This gives +slightly slower code than the default, but reduces the amount of \s-1RAM\s0 required +when executing, and thus may be preferred for some embedded systems. +.IP "\fB\-muninit\-const\-in\-rodata\fR" 4 +.IX Item "-muninit-const-in-rodata" +.PD 0 +.IP "\fB\-mno\-uninit\-const\-in\-rodata\fR" 4 +.IX Item "-mno-uninit-const-in-rodata" +.PD +Put uninitialized \f(CW\*(C`const\*(C'\fR variables in the read-only data section. +This option is only meaningful in conjunction with \fB\-membedded\-data\fR. +.IP "\fB\-mcode\-readable=\fR\fIsetting\fR" 4 +.IX Item "-mcode-readable=setting" +Specify whether \s-1GCC\s0 may generate code that reads from executable sections. +There are three possible settings: +.RS 4 +.IP "\fB\-mcode\-readable=yes\fR" 4 +.IX Item "-mcode-readable=yes" +Instructions may freely access executable sections. This is the +default setting. +.IP "\fB\-mcode\-readable=pcrel\fR" 4 +.IX Item "-mcode-readable=pcrel" +\&\s-1MIPS16\s0 PC-relative load instructions can access executable sections, +but other instructions must not do so. This option is useful on 4KSc +and 4KSd processors when the code TLBs have the Read Inhibit bit set. +It is also useful on processors that can be configured to have a dual +instruction/data \s-1SRAM\s0 interface and that, like the M4K, automatically +redirect PC-relative loads to the instruction \s-1RAM\s0. +.IP "\fB\-mcode\-readable=no\fR" 4 +.IX Item "-mcode-readable=no" +Instructions must not access executable sections. This option can be +useful on targets that are configured to have a dual instruction/data +\&\s-1SRAM\s0 interface but that (unlike the M4K) do not automatically redirect +PC-relative loads to the instruction \s-1RAM\s0. +.RE +.RS 4 +.RE +.IP "\fB\-msplit\-addresses\fR" 4 +.IX Item "-msplit-addresses" +.PD 0 +.IP "\fB\-mno\-split\-addresses\fR" 4 +.IX Item "-mno-split-addresses" +.PD +Enable (disable) use of the \f(CW\*(C`%hi()\*(C'\fR and \f(CW\*(C`%lo()\*(C'\fR assembler +relocation operators. This option has been superseded by +\&\fB\-mexplicit\-relocs\fR but is retained for backwards compatibility. +.IP "\fB\-mexplicit\-relocs\fR" 4 +.IX Item "-mexplicit-relocs" +.PD 0 +.IP "\fB\-mno\-explicit\-relocs\fR" 4 +.IX Item "-mno-explicit-relocs" +.PD +Use (do not use) assembler relocation operators when dealing with symbolic +addresses. The alternative, selected by \fB\-mno\-explicit\-relocs\fR, +is to use assembler macros instead. +.Sp +\&\fB\-mexplicit\-relocs\fR is the default if \s-1GCC\s0 was configured +to use an assembler that supports relocation operators. +.IP "\fB\-mcheck\-zero\-division\fR" 4 +.IX Item "-mcheck-zero-division" +.PD 0 +.IP "\fB\-mno\-check\-zero\-division\fR" 4 +.IX Item "-mno-check-zero-division" +.PD +Trap (do not trap) on integer division by zero. +.Sp +The default is \fB\-mcheck\-zero\-division\fR. +.IP "\fB\-mdivide\-traps\fR" 4 +.IX Item "-mdivide-traps" +.PD 0 +.IP "\fB\-mdivide\-breaks\fR" 4 +.IX Item "-mdivide-breaks" +.PD +\&\s-1MIPS\s0 systems check for division by zero by generating either a +conditional trap or a break instruction. Using traps results in +smaller code, but is only supported on \s-1MIPS\s0 \s-1II\s0 and later. Also, some +versions of the Linux kernel have a bug that prevents trap from +generating the proper signal (\f(CW\*(C`SIGFPE\*(C'\fR). Use \fB\-mdivide\-traps\fR to +allow conditional traps on architectures that support them and +\&\fB\-mdivide\-breaks\fR to force the use of breaks. +.Sp +The default is usually \fB\-mdivide\-traps\fR, but this can be +overridden at configure time using \fB\-\-with\-divide=breaks\fR. +Divide-by-zero checks can be completely disabled using +\&\fB\-mno\-check\-zero\-division\fR. +.IP "\fB\-mmemcpy\fR" 4 +.IX Item "-mmemcpy" +.PD 0 +.IP "\fB\-mno\-memcpy\fR" 4 +.IX Item "-mno-memcpy" +.PD +Force (do not force) the use of \f(CW\*(C`memcpy()\*(C'\fR for non-trivial block +moves. The default is \fB\-mno\-memcpy\fR, which allows \s-1GCC\s0 to inline +most constant-sized copies. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +.PD 0 +.IP "\fB\-mno\-long\-calls\fR" 4 +.IX Item "-mno-long-calls" +.PD +Disable (do not disable) use of the \f(CW\*(C`jal\*(C'\fR instruction. Calling +functions using \f(CW\*(C`jal\*(C'\fR is more efficient but requires the caller +and callee to be in the same 256 megabyte segment. +.Sp +This option has no effect on abicalls code. The default is +\&\fB\-mno\-long\-calls\fR. +.IP "\fB\-mmad\fR" 4 +.IX Item "-mmad" +.PD 0 +.IP "\fB\-mno\-mad\fR" 4 +.IX Item "-mno-mad" +.PD +Enable (disable) use of the \f(CW\*(C`mad\*(C'\fR, \f(CW\*(C`madu\*(C'\fR and \f(CW\*(C`mul\*(C'\fR +instructions, as provided by the R4650 \s-1ISA\s0. +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Enable (disable) use of the floating point multiply-accumulate +instructions, when they are available. The default is +\&\fB\-mfused\-madd\fR. +.Sp +When multiply-accumulate instructions are used, the intermediate +product is calculated to infinite precision and is not subject to +the \s-1FCSR\s0 Flush to Zero bit. This may be undesirable in some +circumstances. +.IP "\fB\-nocpp\fR" 4 +.IX Item "-nocpp" +Tell the \s-1MIPS\s0 assembler to not run its preprocessor over user +assembler files (with a \fB.s\fR suffix) when assembling them. +.IP "\fB\-mfix\-r4000\fR" 4 +.IX Item "-mfix-r4000" +.PD 0 +.IP "\fB\-mno\-fix\-r4000\fR" 4 +.IX Item "-mno-fix-r4000" +.PD +Work around certain R4000 \s-1CPU\s0 errata: +.RS 4 +.IP "\-" 4 +A double-word or a variable shift may give an incorrect result if executed +immediately after starting an integer division. +.IP "\-" 4 +A double-word or a variable shift may give an incorrect result if executed +while an integer multiplication is in progress. +.IP "\-" 4 +An integer division may give an incorrect result if started in a delay slot +of a taken branch or a jump. +.RE +.RS 4 +.RE +.IP "\fB\-mfix\-r4400\fR" 4 +.IX Item "-mfix-r4400" +.PD 0 +.IP "\fB\-mno\-fix\-r4400\fR" 4 +.IX Item "-mno-fix-r4400" +.PD +Work around certain R4400 \s-1CPU\s0 errata: +.RS 4 +.IP "\-" 4 +A double-word or a variable shift may give an incorrect result if executed +immediately after starting an integer division. +.RE +.RS 4 +.RE +.IP "\fB\-mfix\-r10000\fR" 4 +.IX Item "-mfix-r10000" +.PD 0 +.IP "\fB\-mno\-fix\-r10000\fR" 4 +.IX Item "-mno-fix-r10000" +.PD +Work around certain R10000 errata: +.RS 4 +.IP "\-" 4 +\&\f(CW\*(C`ll\*(C'\fR/\f(CW\*(C`sc\*(C'\fR sequences may not behave atomically on revisions +prior to 3.0. They may deadlock on revisions 2.6 and earlier. +.RE +.RS 4 +.Sp +This option can only be used if the target architecture supports +branch-likely instructions. \fB\-mfix\-r10000\fR is the default when +\&\fB\-march=r10000\fR is used; \fB\-mno\-fix\-r10000\fR is the default +otherwise. +.RE +.IP "\fB\-mfix\-vr4120\fR" 4 +.IX Item "-mfix-vr4120" +.PD 0 +.IP "\fB\-mno\-fix\-vr4120\fR" 4 +.IX Item "-mno-fix-vr4120" +.PD +Work around certain \s-1VR4120\s0 errata: +.RS 4 +.IP "\-" 4 +\&\f(CW\*(C`dmultu\*(C'\fR does not always produce the correct result. +.IP "\-" 4 +\&\f(CW\*(C`div\*(C'\fR and \f(CW\*(C`ddiv\*(C'\fR do not always produce the correct result if one +of the operands is negative. +.RE +.RS 4 +.Sp +The workarounds for the division errata rely on special functions in +\&\fIlibgcc.a\fR. At present, these functions are only provided by +the \f(CW\*(C`mips64vr*\-elf\*(C'\fR configurations. +.Sp +Other \s-1VR4120\s0 errata require a nop to be inserted between certain pairs of +instructions. These errata are handled by the assembler, not by \s-1GCC\s0 itself. +.RE +.IP "\fB\-mfix\-vr4130\fR" 4 +.IX Item "-mfix-vr4130" +Work around the \s-1VR4130\s0 \f(CW\*(C`mflo\*(C'\fR/\f(CW\*(C`mfhi\*(C'\fR errata. The +workarounds are implemented by the assembler rather than by \s-1GCC\s0, +although \s-1GCC\s0 will avoid using \f(CW\*(C`mflo\*(C'\fR and \f(CW\*(C`mfhi\*(C'\fR if the +\&\s-1VR4130\s0 \f(CW\*(C`macc\*(C'\fR, \f(CW\*(C`macchi\*(C'\fR, \f(CW\*(C`dmacc\*(C'\fR and \f(CW\*(C`dmacchi\*(C'\fR +instructions are available instead. +.IP "\fB\-mfix\-sb1\fR" 4 +.IX Item "-mfix-sb1" +.PD 0 +.IP "\fB\-mno\-fix\-sb1\fR" 4 +.IX Item "-mno-fix-sb1" +.PD +Work around certain \s-1SB\-1\s0 \s-1CPU\s0 core errata. +(This flag currently works around the \s-1SB\-1\s0 revision 2 +\&\*(L"F1\*(R" and \*(L"F2\*(R" floating point errata.) +.IP "\fB\-mr10k\-cache\-barrier=\fR\fIsetting\fR" 4 +.IX Item "-mr10k-cache-barrier=setting" +Specify whether \s-1GCC\s0 should insert cache barriers to avoid the +side-effects of speculation on R10K processors. +.Sp +In common with many processors, the R10K tries to predict the outcome +of a conditional branch and speculatively executes instructions from +the \*(L"taken\*(R" branch. It later aborts these instructions if the +predicted outcome was wrong. However, on the R10K, even aborted +instructions can have side effects. +.Sp +This problem only affects kernel stores and, depending on the system, +kernel loads. As an example, a speculatively-executed store may load +the target memory into cache and mark the cache line as dirty, even if +the store itself is later aborted. If a \s-1DMA\s0 operation writes to the +same area of memory before the \*(L"dirty\*(R" line is flushed, the cached +data will overwrite the DMA-ed data. See the R10K processor manual +for a full description, including other potential problems. +.Sp +One workaround is to insert cache barrier instructions before every memory +access that might be speculatively executed and that might have side +effects even if aborted. \fB\-mr10k\-cache\-barrier=\fR\fIsetting\fR +controls \s-1GCC\s0's implementation of this workaround. It assumes that +aborted accesses to any byte in the following regions will not have +side effects: +.RS 4 +.IP "1." 4 +the memory occupied by the current function's stack frame; +.IP "2." 4 +the memory occupied by an incoming stack argument; +.IP "3." 4 +the memory occupied by an object with a link-time-constant address. +.RE +.RS 4 +.Sp +It is the kernel's responsibility to ensure that speculative +accesses to these regions are indeed safe. +.Sp +If the input program contains a function declaration such as: +.Sp +.Vb 1 +\& void foo (void); +.Ve +.Sp +then the implementation of \f(CW\*(C`foo\*(C'\fR must allow \f(CW\*(C`j foo\*(C'\fR and +\&\f(CW\*(C`jal foo\*(C'\fR to be executed speculatively. \s-1GCC\s0 honors this +restriction for functions it compiles itself. It expects non-GCC +functions (such as hand-written assembly code) to do the same. +.Sp +The option has three forms: +.IP "\fB\-mr10k\-cache\-barrier=load\-store\fR" 4 +.IX Item "-mr10k-cache-barrier=load-store" +Insert a cache barrier before a load or store that might be +speculatively executed and that might have side effects even +if aborted. +.IP "\fB\-mr10k\-cache\-barrier=store\fR" 4 +.IX Item "-mr10k-cache-barrier=store" +Insert a cache barrier before a store that might be speculatively +executed and that might have side effects even if aborted. +.IP "\fB\-mr10k\-cache\-barrier=none\fR" 4 +.IX Item "-mr10k-cache-barrier=none" +Disable the insertion of cache barriers. This is the default setting. +.RE +.RS 4 +.RE +.IP "\fB\-mflush\-func=\fR\fIfunc\fR" 4 +.IX Item "-mflush-func=func" +.PD 0 +.IP "\fB\-mno\-flush\-func\fR" 4 +.IX Item "-mno-flush-func" +.PD +Specifies the function to call to flush the I and D caches, or to not +call any such function. If called, the function must take the same +arguments as the common \f(CW\*(C`_flush_func()\*(C'\fR, that is, the address of the +memory range for which the cache is being flushed, the size of the +memory range, and the number 3 (to flush both caches). The default +depends on the target \s-1GCC\s0 was configured for, but commonly is either +\&\fB_flush_func\fR or \fB_\|_cpu_flush\fR. +.IP "\fBmbranch\-cost=\fR\fInum\fR" 4 +.IX Item "mbranch-cost=num" +Set the cost of branches to roughly \fInum\fR \*(L"simple\*(R" instructions. +This cost is only a heuristic and is not guaranteed to produce +consistent results across releases. A zero cost redundantly selects +the default, which is based on the \fB\-mtune\fR setting. +.IP "\fB\-mbranch\-likely\fR" 4 +.IX Item "-mbranch-likely" +.PD 0 +.IP "\fB\-mno\-branch\-likely\fR" 4 +.IX Item "-mno-branch-likely" +.PD +Enable or disable use of Branch Likely instructions, regardless of the +default for the selected architecture. By default, Branch Likely +instructions may be generated if they are supported by the selected +architecture. An exception is for the \s-1MIPS32\s0 and \s-1MIPS64\s0 architectures +and processors which implement those architectures; for those, Branch +Likely instructions will not be generated by default because the \s-1MIPS32\s0 +and \s-1MIPS64\s0 architectures specifically deprecate their use. +.IP "\fB\-mfp\-exceptions\fR" 4 +.IX Item "-mfp-exceptions" +.PD 0 +.IP "\fB\-mno\-fp\-exceptions\fR" 4 +.IX Item "-mno-fp-exceptions" +.PD +Specifies whether \s-1FP\s0 exceptions are enabled. This affects how we schedule +\&\s-1FP\s0 instructions for some processors. The default is that \s-1FP\s0 exceptions are +enabled. +.Sp +For instance, on the \s-1SB\-1\s0, if \s-1FP\s0 exceptions are disabled, and we are emitting +64\-bit code, then we can use both \s-1FP\s0 pipes. Otherwise, we can only use one +\&\s-1FP\s0 pipe. +.IP "\fB\-mvr4130\-align\fR" 4 +.IX Item "-mvr4130-align" +.PD 0 +.IP "\fB\-mno\-vr4130\-align\fR" 4 +.IX Item "-mno-vr4130-align" +.PD +The \s-1VR4130\s0 pipeline is two-way superscalar, but can only issue two +instructions together if the first one is 8\-byte aligned. When this +option is enabled, \s-1GCC\s0 will align pairs of instructions that it +thinks should execute in parallel. +.Sp +This option only has an effect when optimizing for the \s-1VR4130\s0. +It normally makes code faster, but at the expense of making it bigger. +It is enabled by default at optimization level \fB\-O3\fR. +.IP "\fB\-msynci\fR" 4 +.IX Item "-msynci" +.PD 0 +.IP "\fB\-mno\-synci\fR" 4 +.IX Item "-mno-synci" +.PD +Enable (disable) generation of \f(CW\*(C`synci\*(C'\fR instructions on +architectures that support it. The \f(CW\*(C`synci\*(C'\fR instructions (if +enabled) will be generated when \f(CW\*(C`_\|_builtin_\|_\|_clear_cache()\*(C'\fR is +compiled. +.Sp +This option defaults to \f(CW\*(C`\-mno\-synci\*(C'\fR, but the default can be +overridden by configuring with \f(CW\*(C`\-\-with\-synci\*(C'\fR. +.Sp +When compiling code for single processor systems, it is generally safe +to use \f(CW\*(C`synci\*(C'\fR. However, on many multi-core (\s-1SMP\s0) systems, it +will not invalidate the instruction caches on all cores and may lead +to undefined behavior. +.IP "\fB\-mrelax\-pic\-calls\fR" 4 +.IX Item "-mrelax-pic-calls" +.PD 0 +.IP "\fB\-mno\-relax\-pic\-calls\fR" 4 +.IX Item "-mno-relax-pic-calls" +.PD +Try to turn \s-1PIC\s0 calls that are normally dispatched via register +\&\f(CW$25\fR into direct calls. This is only possible if the linker can +resolve the destination at link-time and if the destination is within +range for a direct call. +.Sp +\&\fB\-mrelax\-pic\-calls\fR is the default if \s-1GCC\s0 was configured to use +an assembler and a linker that supports the \f(CW\*(C`.reloc\*(C'\fR assembly +directive and \f(CW\*(C`\-mexplicit\-relocs\*(C'\fR is in effect. With +\&\f(CW\*(C`\-mno\-explicit\-relocs\*(C'\fR, this optimization can be performed by the +assembler and the linker alone without help from the compiler. +.IP "\fB\-mmcount\-ra\-address\fR" 4 +.IX Item "-mmcount-ra-address" +.PD 0 +.IP "\fB\-mno\-mcount\-ra\-address\fR" 4 +.IX Item "-mno-mcount-ra-address" +.PD +Emit (do not emit) code that allows \f(CW\*(C`_mcount\*(C'\fR to modify the +calling function's return address. When enabled, this option extends +the usual \f(CW\*(C`_mcount\*(C'\fR interface with a new \fIra-address\fR +parameter, which has type \f(CW\*(C`intptr_t *\*(C'\fR and is passed in register +\&\f(CW$12\fR. \f(CW\*(C`_mcount\*(C'\fR can then modify the return address by +doing both of the following: +.RS 4 +.IP "\(bu" 4 +Returning the new address in register \f(CW$31\fR. +.IP "\(bu" 4 +Storing the new address in \f(CW\*(C`*\f(CIra\-address\f(CW\*(C'\fR, +if \fIra-address\fR is nonnull. +.RE +.RS 4 +.Sp +The default is \fB\-mno\-mcount\-ra\-address\fR. +.RE +.PP +\fI\s-1MMIX\s0 Options\fR +.IX Subsection "MMIX Options" +.PP +These options are defined for the \s-1MMIX:\s0 +.IP "\fB\-mlibfuncs\fR" 4 +.IX Item "-mlibfuncs" +.PD 0 +.IP "\fB\-mno\-libfuncs\fR" 4 +.IX Item "-mno-libfuncs" +.PD +Specify that intrinsic library functions are being compiled, passing all +values in registers, no matter the size. +.IP "\fB\-mepsilon\fR" 4 +.IX Item "-mepsilon" +.PD 0 +.IP "\fB\-mno\-epsilon\fR" 4 +.IX Item "-mno-epsilon" +.PD +Generate floating-point comparison instructions that compare with respect +to the \f(CW\*(C`rE\*(C'\fR epsilon register. +.IP "\fB\-mabi=mmixware\fR" 4 +.IX Item "-mabi=mmixware" +.PD 0 +.IP "\fB\-mabi=gnu\fR" 4 +.IX Item "-mabi=gnu" +.PD +Generate code that passes function parameters and return values that (in +the called function) are seen as registers \f(CW$0\fR and up, as opposed to +the \s-1GNU\s0 \s-1ABI\s0 which uses global registers \f(CW$231\fR and up. +.IP "\fB\-mzero\-extend\fR" 4 +.IX Item "-mzero-extend" +.PD 0 +.IP "\fB\-mno\-zero\-extend\fR" 4 +.IX Item "-mno-zero-extend" +.PD +When reading data from memory in sizes shorter than 64 bits, use (do not +use) zero-extending load instructions by default, rather than +sign-extending ones. +.IP "\fB\-mknuthdiv\fR" 4 +.IX Item "-mknuthdiv" +.PD 0 +.IP "\fB\-mno\-knuthdiv\fR" 4 +.IX Item "-mno-knuthdiv" +.PD +Make the result of a division yielding a remainder have the same sign as +the divisor. With the default, \fB\-mno\-knuthdiv\fR, the sign of the +remainder follows the sign of the dividend. Both methods are +arithmetically valid, the latter being almost exclusively used. +.IP "\fB\-mtoplevel\-symbols\fR" 4 +.IX Item "-mtoplevel-symbols" +.PD 0 +.IP "\fB\-mno\-toplevel\-symbols\fR" 4 +.IX Item "-mno-toplevel-symbols" +.PD +Prepend (do not prepend) a \fB:\fR to all global symbols, so the assembly +code can be used with the \f(CW\*(C`PREFIX\*(C'\fR assembly directive. +.IP "\fB\-melf\fR" 4 +.IX Item "-melf" +Generate an executable in the \s-1ELF\s0 format, rather than the default +\&\fBmmo\fR format used by the \fBmmix\fR simulator. +.IP "\fB\-mbranch\-predict\fR" 4 +.IX Item "-mbranch-predict" +.PD 0 +.IP "\fB\-mno\-branch\-predict\fR" 4 +.IX Item "-mno-branch-predict" +.PD +Use (do not use) the probable-branch instructions, when static branch +prediction indicates a probable branch. +.IP "\fB\-mbase\-addresses\fR" 4 +.IX Item "-mbase-addresses" +.PD 0 +.IP "\fB\-mno\-base\-addresses\fR" 4 +.IX Item "-mno-base-addresses" +.PD +Generate (do not generate) code that uses \fIbase addresses\fR. Using a +base address automatically generates a request (handled by the assembler +and the linker) for a constant to be set up in a global register. The +register is used for one or more base address requests within the range 0 +to 255 from the value held in the register. The generally leads to short +and fast code, but the number of different data items that can be +addressed is limited. This means that a program that uses lots of static +data may require \fB\-mno\-base\-addresses\fR. +.IP "\fB\-msingle\-exit\fR" 4 +.IX Item "-msingle-exit" +.PD 0 +.IP "\fB\-mno\-single\-exit\fR" 4 +.IX Item "-mno-single-exit" +.PD +Force (do not force) generated code to have a single exit point in each +function. +.PP +\fI\s-1MN10300\s0 Options\fR +.IX Subsection "MN10300 Options" +.PP +These \fB\-m\fR options are defined for Matsushita \s-1MN10300\s0 architectures: +.IP "\fB\-mmult\-bug\fR" 4 +.IX Item "-mmult-bug" +Generate code to avoid bugs in the multiply instructions for the \s-1MN10300\s0 +processors. This is the default. +.IP "\fB\-mno\-mult\-bug\fR" 4 +.IX Item "-mno-mult-bug" +Do not generate code to avoid bugs in the multiply instructions for the +\&\s-1MN10300\s0 processors. +.IP "\fB\-mam33\fR" 4 +.IX Item "-mam33" +Generate code which uses features specific to the \s-1AM33\s0 processor. +.IP "\fB\-mno\-am33\fR" 4 +.IX Item "-mno-am33" +Do not generate code which uses features specific to the \s-1AM33\s0 processor. This +is the default. +.IP "\fB\-mam33\-2\fR" 4 +.IX Item "-mam33-2" +Generate code which uses features specific to the \s-1AM33/2\s0.0 processor. +.IP "\fB\-mam34\fR" 4 +.IX Item "-mam34" +Generate code which uses features specific to the \s-1AM34\s0 processor. +.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 +.IX Item "-mtune=cpu-type" +Use the timing characteristics of the indicated \s-1CPU\s0 type when +scheduling instructions. This does not change the targeted processor +type. The \s-1CPU\s0 type must be one of \fBmn10300\fR, \fBam33\fR, +\&\fBam33\-2\fR or \fBam34\fR. +.IP "\fB\-mreturn\-pointer\-on\-d0\fR" 4 +.IX Item "-mreturn-pointer-on-d0" +When generating a function which returns a pointer, return the pointer +in both \f(CW\*(C`a0\*(C'\fR and \f(CW\*(C`d0\*(C'\fR. Otherwise, the pointer is returned +only in a0, and attempts to call such functions without a prototype +would result in errors. Note that this option is on by default; use +\&\fB\-mno\-return\-pointer\-on\-d0\fR to disable it. +.IP "\fB\-mno\-crt0\fR" 4 +.IX Item "-mno-crt0" +Do not link in the C run-time initialization object file. +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +Indicate to the linker that it should perform a relaxation optimization pass +to shorten branches, calls and absolute memory addresses. This option only +has an effect when used on the command line for the final link step. +.Sp +This option makes symbolic debugging impossible. +.IP "\fB\-mliw\fR" 4 +.IX Item "-mliw" +Allow the compiler to generate \fILong Instruction Word\fR +instructions if the target is the \fB\s-1AM33\s0\fR or later. This is the +default. This option defines the preprocessor macro \fB_\|_LIW_\|_\fR. +.IP "\fB\-mnoliw\fR" 4 +.IX Item "-mnoliw" +Do not allow the compiler to generate \fILong Instruction Word\fR +instructions. This option defines the preprocessor macro +\&\fB_\|_NO_LIW_\|_\fR. +.PP +\fI\s-1PDP\-11\s0 Options\fR +.IX Subsection "PDP-11 Options" +.PP +These options are defined for the \s-1PDP\-11:\s0 +.IP "\fB\-mfpu\fR" 4 +.IX Item "-mfpu" +Use hardware \s-1FPP\s0 floating point. This is the default. (\s-1FIS\s0 floating +point on the \s-1PDP\-11/40\s0 is not supported.) +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Do not use hardware floating point. +.IP "\fB\-mac0\fR" 4 +.IX Item "-mac0" +Return floating-point results in ac0 (fr0 in Unix assembler syntax). +.IP "\fB\-mno\-ac0\fR" 4 +.IX Item "-mno-ac0" +Return floating-point results in memory. This is the default. +.IP "\fB\-m40\fR" 4 +.IX Item "-m40" +Generate code for a \s-1PDP\-11/40\s0. +.IP "\fB\-m45\fR" 4 +.IX Item "-m45" +Generate code for a \s-1PDP\-11/45\s0. This is the default. +.IP "\fB\-m10\fR" 4 +.IX Item "-m10" +Generate code for a \s-1PDP\-11/10\s0. +.IP "\fB\-mbcopy\-builtin\fR" 4 +.IX Item "-mbcopy-builtin" +Use inline \f(CW\*(C`movmemhi\*(C'\fR patterns for copying memory. This is the +default. +.IP "\fB\-mbcopy\fR" 4 +.IX Item "-mbcopy" +Do not use inline \f(CW\*(C`movmemhi\*(C'\fR patterns for copying memory. +.IP "\fB\-mint16\fR" 4 +.IX Item "-mint16" +.PD 0 +.IP "\fB\-mno\-int32\fR" 4 +.IX Item "-mno-int32" +.PD +Use 16\-bit \f(CW\*(C`int\*(C'\fR. This is the default. +.IP "\fB\-mint32\fR" 4 +.IX Item "-mint32" +.PD 0 +.IP "\fB\-mno\-int16\fR" 4 +.IX Item "-mno-int16" +.PD +Use 32\-bit \f(CW\*(C`int\*(C'\fR. +.IP "\fB\-mfloat64\fR" 4 +.IX Item "-mfloat64" +.PD 0 +.IP "\fB\-mno\-float32\fR" 4 +.IX Item "-mno-float32" +.PD +Use 64\-bit \f(CW\*(C`float\*(C'\fR. This is the default. +.IP "\fB\-mfloat32\fR" 4 +.IX Item "-mfloat32" +.PD 0 +.IP "\fB\-mno\-float64\fR" 4 +.IX Item "-mno-float64" +.PD +Use 32\-bit \f(CW\*(C`float\*(C'\fR. +.IP "\fB\-mabshi\fR" 4 +.IX Item "-mabshi" +Use \f(CW\*(C`abshi2\*(C'\fR pattern. This is the default. +.IP "\fB\-mno\-abshi\fR" 4 +.IX Item "-mno-abshi" +Do not use \f(CW\*(C`abshi2\*(C'\fR pattern. +.IP "\fB\-mbranch\-expensive\fR" 4 +.IX Item "-mbranch-expensive" +Pretend that branches are expensive. This is for experimenting with +code generation only. +.IP "\fB\-mbranch\-cheap\fR" 4 +.IX Item "-mbranch-cheap" +Do not pretend that branches are expensive. This is the default. +.IP "\fB\-munix\-asm\fR" 4 +.IX Item "-munix-asm" +Use Unix assembler syntax. This is the default when configured for +\&\fBpdp11\-*\-bsd\fR. +.IP "\fB\-mdec\-asm\fR" 4 +.IX Item "-mdec-asm" +Use \s-1DEC\s0 assembler syntax. This is the default when configured for any +\&\s-1PDP\-11\s0 target other than \fBpdp11\-*\-bsd\fR. +.PP +\fIpicoChip Options\fR +.IX Subsection "picoChip Options" +.PP +These \fB\-m\fR options are defined for picoChip implementations: +.IP "\fB\-mae=\fR\fIae_type\fR" 4 +.IX Item "-mae=ae_type" +Set the instruction set, register set, and instruction scheduling +parameters for array element type \fIae_type\fR. Supported values +for \fIae_type\fR are \fB\s-1ANY\s0\fR, \fB\s-1MUL\s0\fR, and \fB\s-1MAC\s0\fR. +.Sp +\&\fB\-mae=ANY\fR selects a completely generic \s-1AE\s0 type. Code +generated with this option will run on any of the other \s-1AE\s0 types. The +code will not be as efficient as it would be if compiled for a specific +\&\s-1AE\s0 type, and some types of operation (e.g., multiplication) will not +work properly on all types of \s-1AE\s0. +.Sp +\&\fB\-mae=MUL\fR selects a \s-1MUL\s0 \s-1AE\s0 type. This is the most useful \s-1AE\s0 type +for compiled code, and is the default. +.Sp +\&\fB\-mae=MAC\fR selects a DSP-style \s-1MAC\s0 \s-1AE\s0. Code compiled with this +option may suffer from poor performance of byte (char) manipulation, +since the \s-1DSP\s0 \s-1AE\s0 does not provide hardware support for byte load/stores. +.IP "\fB\-msymbol\-as\-address\fR" 4 +.IX Item "-msymbol-as-address" +Enable the compiler to directly use a symbol name as an address in a +load/store instruction, without first loading it into a +register. Typically, the use of this option will generate larger +programs, which run faster than when the option isn't used. However, the +results vary from program to program, so it is left as a user option, +rather than being permanently enabled. +.IP "\fB\-mno\-inefficient\-warnings\fR" 4 +.IX Item "-mno-inefficient-warnings" +Disables warnings about the generation of inefficient code. These +warnings can be generated, for example, when compiling code which +performs byte-level memory operations on the \s-1MAC\s0 \s-1AE\s0 type. The \s-1MAC\s0 \s-1AE\s0 has +no hardware support for byte-level memory operations, so all byte +load/stores must be synthesized from word load/store operations. This is +inefficient and a warning will be generated indicating to the programmer +that they should rewrite the code to avoid byte operations, or to target +an \s-1AE\s0 type which has the necessary hardware support. This option enables +the warning to be turned off. +.PP +\fIPowerPC Options\fR +.IX Subsection "PowerPC Options" +.PP +These are listed under +.PP +\fI\s-1IBM\s0 \s-1RS/6000\s0 and PowerPC Options\fR +.IX Subsection "IBM RS/6000 and PowerPC Options" +.PP +These \fB\-m\fR options are defined for the \s-1IBM\s0 \s-1RS/6000\s0 and PowerPC: +.IP "\fB\-mpower\fR" 4 +.IX Item "-mpower" +.PD 0 +.IP "\fB\-mno\-power\fR" 4 +.IX Item "-mno-power" +.IP "\fB\-mpower2\fR" 4 +.IX Item "-mpower2" +.IP "\fB\-mno\-power2\fR" 4 +.IX Item "-mno-power2" +.IP "\fB\-mpowerpc\fR" 4 +.IX Item "-mpowerpc" +.IP "\fB\-mno\-powerpc\fR" 4 +.IX Item "-mno-powerpc" +.IP "\fB\-mpowerpc\-gpopt\fR" 4 +.IX Item "-mpowerpc-gpopt" +.IP "\fB\-mno\-powerpc\-gpopt\fR" 4 +.IX Item "-mno-powerpc-gpopt" +.IP "\fB\-mpowerpc\-gfxopt\fR" 4 +.IX Item "-mpowerpc-gfxopt" +.IP "\fB\-mno\-powerpc\-gfxopt\fR" 4 +.IX Item "-mno-powerpc-gfxopt" +.IP "\fB\-mpowerpc64\fR" 4 +.IX Item "-mpowerpc64" +.IP "\fB\-mno\-powerpc64\fR" 4 +.IX Item "-mno-powerpc64" +.IP "\fB\-mmfcrf\fR" 4 +.IX Item "-mmfcrf" +.IP "\fB\-mno\-mfcrf\fR" 4 +.IX Item "-mno-mfcrf" +.IP "\fB\-mpopcntb\fR" 4 +.IX Item "-mpopcntb" +.IP "\fB\-mno\-popcntb\fR" 4 +.IX Item "-mno-popcntb" +.IP "\fB\-mpopcntd\fR" 4 +.IX Item "-mpopcntd" +.IP "\fB\-mno\-popcntd\fR" 4 +.IX Item "-mno-popcntd" +.IP "\fB\-mfprnd\fR" 4 +.IX Item "-mfprnd" +.IP "\fB\-mno\-fprnd\fR" 4 +.IX Item "-mno-fprnd" +.IP "\fB\-mcmpb\fR" 4 +.IX Item "-mcmpb" +.IP "\fB\-mno\-cmpb\fR" 4 +.IX Item "-mno-cmpb" +.IP "\fB\-mmfpgpr\fR" 4 +.IX Item "-mmfpgpr" +.IP "\fB\-mno\-mfpgpr\fR" 4 +.IX Item "-mno-mfpgpr" +.IP "\fB\-mhard\-dfp\fR" 4 +.IX Item "-mhard-dfp" +.IP "\fB\-mno\-hard\-dfp\fR" 4 +.IX Item "-mno-hard-dfp" +.PD +\&\s-1GCC\s0 supports two related instruction set architectures for the +\&\s-1RS/6000\s0 and PowerPC. The \fI\s-1POWER\s0\fR instruction set are those +instructions supported by the \fBrios\fR chip set used in the original +\&\s-1RS/6000\s0 systems and the \fIPowerPC\fR instruction set is the +architecture of the Freescale MPC5xx, MPC6xx, MPC8xx microprocessors, and +the \s-1IBM\s0 4xx, 6xx, and follow-on microprocessors. +.Sp +Neither architecture is a subset of the other. However there is a +large common subset of instructions supported by both. An \s-1MQ\s0 +register is included in processors supporting the \s-1POWER\s0 architecture. +.Sp +You use these options to specify which instructions are available on the +processor you are using. The default value of these options is +determined when configuring \s-1GCC\s0. Specifying the +\&\fB\-mcpu=\fR\fIcpu_type\fR overrides the specification of these +options. We recommend you use the \fB\-mcpu=\fR\fIcpu_type\fR option +rather than the options listed above. +.Sp +The \fB\-mpower\fR option allows \s-1GCC\s0 to generate instructions that +are found only in the \s-1POWER\s0 architecture and to use the \s-1MQ\s0 register. +Specifying \fB\-mpower2\fR implies \fB\-power\fR and also allows \s-1GCC\s0 +to generate instructions that are present in the \s-1POWER2\s0 architecture but +not the original \s-1POWER\s0 architecture. +.Sp +The \fB\-mpowerpc\fR option allows \s-1GCC\s0 to generate instructions that +are found only in the 32\-bit subset of the PowerPC architecture. +Specifying \fB\-mpowerpc\-gpopt\fR implies \fB\-mpowerpc\fR and also allows +\&\s-1GCC\s0 to use the optional PowerPC architecture instructions in the +General Purpose group, including floating-point square root. Specifying +\&\fB\-mpowerpc\-gfxopt\fR implies \fB\-mpowerpc\fR and also allows \s-1GCC\s0 to +use the optional PowerPC architecture instructions in the Graphics +group, including floating-point select. +.Sp +The \fB\-mmfcrf\fR option allows \s-1GCC\s0 to generate the move from +condition register field instruction implemented on the \s-1POWER4\s0 +processor and other processors that support the PowerPC V2.01 +architecture. +The \fB\-mpopcntb\fR option allows \s-1GCC\s0 to generate the popcount and +double precision \s-1FP\s0 reciprocal estimate instruction implemented on the +\&\s-1POWER5\s0 processor and other processors that support the PowerPC V2.02 +architecture. +The \fB\-mpopcntd\fR option allows \s-1GCC\s0 to generate the popcount +instruction implemented on the \s-1POWER7\s0 processor and other processors +that support the PowerPC V2.06 architecture. +The \fB\-mfprnd\fR option allows \s-1GCC\s0 to generate the \s-1FP\s0 round to +integer instructions implemented on the \s-1POWER5+\s0 processor and other +processors that support the PowerPC V2.03 architecture. +The \fB\-mcmpb\fR option allows \s-1GCC\s0 to generate the compare bytes +instruction implemented on the \s-1POWER6\s0 processor and other processors +that support the PowerPC V2.05 architecture. +The \fB\-mmfpgpr\fR option allows \s-1GCC\s0 to generate the \s-1FP\s0 move to/from +general purpose register instructions implemented on the \s-1POWER6X\s0 +processor and other processors that support the extended PowerPC V2.05 +architecture. +The \fB\-mhard\-dfp\fR option allows \s-1GCC\s0 to generate the decimal floating +point instructions implemented on some \s-1POWER\s0 processors. +.Sp +The \fB\-mpowerpc64\fR option allows \s-1GCC\s0 to generate the additional +64\-bit instructions that are found in the full PowerPC64 architecture +and to treat GPRs as 64\-bit, doubleword quantities. \s-1GCC\s0 defaults to +\&\fB\-mno\-powerpc64\fR. +.Sp +If you specify both \fB\-mno\-power\fR and \fB\-mno\-powerpc\fR, \s-1GCC\s0 +will use only the instructions in the common subset of both +architectures plus some special \s-1AIX\s0 common-mode calls, and will not use +the \s-1MQ\s0 register. Specifying both \fB\-mpower\fR and \fB\-mpowerpc\fR +permits \s-1GCC\s0 to use any instruction from either architecture and to +allow use of the \s-1MQ\s0 register; specify this for the Motorola \s-1MPC601\s0. +.IP "\fB\-mnew\-mnemonics\fR" 4 +.IX Item "-mnew-mnemonics" +.PD 0 +.IP "\fB\-mold\-mnemonics\fR" 4 +.IX Item "-mold-mnemonics" +.PD +Select which mnemonics to use in the generated assembler code. With +\&\fB\-mnew\-mnemonics\fR, \s-1GCC\s0 uses the assembler mnemonics defined for +the PowerPC architecture. With \fB\-mold\-mnemonics\fR it uses the +assembler mnemonics defined for the \s-1POWER\s0 architecture. Instructions +defined in only one architecture have only one mnemonic; \s-1GCC\s0 uses that +mnemonic irrespective of which of these options is specified. +.Sp +\&\s-1GCC\s0 defaults to the mnemonics appropriate for the architecture in +use. Specifying \fB\-mcpu=\fR\fIcpu_type\fR sometimes overrides the +value of these option. Unless you are building a cross-compiler, you +should normally not specify either \fB\-mnew\-mnemonics\fR or +\&\fB\-mold\-mnemonics\fR, but should instead accept the default. +.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 +.IX Item "-mcpu=cpu_type" +Set architecture type, register usage, choice of mnemonics, and +instruction scheduling parameters for machine type \fIcpu_type\fR. +Supported values for \fIcpu_type\fR are \fB401\fR, \fB403\fR, +\&\fB405\fR, \fB405fp\fR, \fB440\fR, \fB440fp\fR, \fB464\fR, \fB464fp\fR, +\&\fB476\fR, \fB476fp\fR, \fB505\fR, \fB601\fR, \fB602\fR, \fB603\fR, +\&\fB603e\fR, \fB604\fR, \fB604e\fR, \fB620\fR, \fB630\fR, \fB740\fR, +\&\fB7400\fR, \fB7450\fR, \fB750\fR, \fB801\fR, \fB821\fR, \fB823\fR, +\&\fB860\fR, \fB970\fR, \fB8540\fR, \fBa2\fR, \fBe300c2\fR, +\&\fBe300c3\fR, \fBe500mc\fR, \fBe500mc64\fR, \fBec603e\fR, \fBG3\fR, +\&\fBG4\fR, \fBG5\fR, \fBtitan\fR, \fBpower\fR, \fBpower2\fR, \fBpower3\fR, +\&\fBpower4\fR, \fBpower5\fR, \fBpower5+\fR, \fBpower6\fR, \fBpower6x\fR, +\&\fBpower7\fR, \fBcommon\fR, \fBpowerpc\fR, \fBpowerpc64\fR, \fBrios\fR, +\&\fBrios1\fR, \fBrios2\fR, \fBrsc\fR, and \fBrs64\fR. +.Sp +\&\fB\-mcpu=common\fR selects a completely generic processor. Code +generated under this option will run on any \s-1POWER\s0 or PowerPC processor. +\&\s-1GCC\s0 will use only the instructions in the common subset of both +architectures, and will not use the \s-1MQ\s0 register. \s-1GCC\s0 assumes a generic +processor model for scheduling purposes. +.Sp +\&\fB\-mcpu=power\fR, \fB\-mcpu=power2\fR, \fB\-mcpu=powerpc\fR, and +\&\fB\-mcpu=powerpc64\fR specify generic \s-1POWER\s0, \s-1POWER2\s0, pure 32\-bit +PowerPC (i.e., not \s-1MPC601\s0), and 64\-bit PowerPC architecture machine +types, with an appropriate, generic processor model assumed for +scheduling purposes. +.Sp +The other options specify a specific processor. Code generated under +those options will run best on that processor, and may not run at all on +others. +.Sp +The \fB\-mcpu\fR options automatically enable or disable the +following options: +.Sp +\&\fB\-maltivec \-mfprnd \-mhard\-float \-mmfcrf \-mmultiple +\&\-mnew\-mnemonics \-mpopcntb \-mpopcntd \-mpower \-mpower2 \-mpowerpc64 +\&\-mpowerpc\-gpopt \-mpowerpc\-gfxopt \-msingle\-float \-mdouble\-float +\&\-msimple\-fpu \-mstring \-mmulhw \-mdlmzb \-mmfpgpr \-mvsx\fR +.Sp +The particular options set for any particular \s-1CPU\s0 will vary between +compiler versions, depending on what setting seems to produce optimal +code for that \s-1CPU\s0; it doesn't necessarily reflect the actual hardware's +capabilities. If you wish to set an individual option to a particular +value, you may specify it after the \fB\-mcpu\fR option, like +\&\fB\-mcpu=970 \-mno\-altivec\fR. +.Sp +On \s-1AIX\s0, the \fB\-maltivec\fR and \fB\-mpowerpc64\fR options are +not enabled or disabled by the \fB\-mcpu\fR option at present because +\&\s-1AIX\s0 does not have full support for these options. You may still +enable or disable them individually if you're sure it'll work in your +environment. +.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4 +.IX Item "-mtune=cpu_type" +Set the instruction scheduling parameters for machine type +\&\fIcpu_type\fR, but do not set the architecture type, register usage, or +choice of mnemonics, as \fB\-mcpu=\fR\fIcpu_type\fR would. The same +values for \fIcpu_type\fR are used for \fB\-mtune\fR as for +\&\fB\-mcpu\fR. If both are specified, the code generated will use the +architecture, registers, and mnemonics set by \fB\-mcpu\fR, but the +scheduling parameters set by \fB\-mtune\fR. +.IP "\fB\-mcmodel=small\fR" 4 +.IX Item "-mcmodel=small" +Generate PowerPC64 code for the small model: The \s-1TOC\s0 is limited to +64k. +.IP "\fB\-mcmodel=medium\fR" 4 +.IX Item "-mcmodel=medium" +Generate PowerPC64 code for the medium model: The \s-1TOC\s0 and other static +data may be up to a total of 4G in size. +.IP "\fB\-mcmodel=large\fR" 4 +.IX Item "-mcmodel=large" +Generate PowerPC64 code for the large model: The \s-1TOC\s0 may be up to 4G +in size. Other data and code is only limited by the 64\-bit address +space. +.IP "\fB\-maltivec\fR" 4 +.IX Item "-maltivec" +.PD 0 +.IP "\fB\-mno\-altivec\fR" 4 +.IX Item "-mno-altivec" +.PD +Generate code that uses (does not use) AltiVec instructions, and also +enable the use of built-in functions that allow more direct access to +the AltiVec instruction set. You may also need to set +\&\fB\-mabi=altivec\fR to adjust the current \s-1ABI\s0 with AltiVec \s-1ABI\s0 +enhancements. +.IP "\fB\-mvrsave\fR" 4 +.IX Item "-mvrsave" +.PD 0 +.IP "\fB\-mno\-vrsave\fR" 4 +.IX Item "-mno-vrsave" +.PD +Generate \s-1VRSAVE\s0 instructions when generating AltiVec code. +.IP "\fB\-mgen\-cell\-microcode\fR" 4 +.IX Item "-mgen-cell-microcode" +Generate Cell microcode instructions +.IP "\fB\-mwarn\-cell\-microcode\fR" 4 +.IX Item "-mwarn-cell-microcode" +Warning when a Cell microcode instruction is going to emitted. An example +of a Cell microcode instruction is a variable shift. +.IP "\fB\-msecure\-plt\fR" 4 +.IX Item "-msecure-plt" +Generate code that allows ld and ld.so to build executables and shared +libraries with non-exec .plt and .got sections. This is a PowerPC +32\-bit \s-1SYSV\s0 \s-1ABI\s0 option. +.IP "\fB\-mbss\-plt\fR" 4 +.IX Item "-mbss-plt" +Generate code that uses a \s-1BSS\s0 .plt section that ld.so fills in, and +requires .plt and .got sections that are both writable and executable. +This is a PowerPC 32\-bit \s-1SYSV\s0 \s-1ABI\s0 option. +.IP "\fB\-misel\fR" 4 +.IX Item "-misel" +.PD 0 +.IP "\fB\-mno\-isel\fR" 4 +.IX Item "-mno-isel" +.PD +This switch enables or disables the generation of \s-1ISEL\s0 instructions. +.IP "\fB\-misel=\fR\fIyes/no\fR" 4 +.IX Item "-misel=yes/no" +This switch has been deprecated. Use \fB\-misel\fR and +\&\fB\-mno\-isel\fR instead. +.IP "\fB\-mspe\fR" 4 +.IX Item "-mspe" +.PD 0 +.IP "\fB\-mno\-spe\fR" 4 +.IX Item "-mno-spe" +.PD +This switch enables or disables the generation of \s-1SPE\s0 simd +instructions. +.IP "\fB\-mpaired\fR" 4 +.IX Item "-mpaired" +.PD 0 +.IP "\fB\-mno\-paired\fR" 4 +.IX Item "-mno-paired" +.PD +This switch enables or disables the generation of \s-1PAIRED\s0 simd +instructions. +.IP "\fB\-mspe=\fR\fIyes/no\fR" 4 +.IX Item "-mspe=yes/no" +This option has been deprecated. Use \fB\-mspe\fR and +\&\fB\-mno\-spe\fR instead. +.IP "\fB\-mvsx\fR" 4 +.IX Item "-mvsx" +.PD 0 +.IP "\fB\-mno\-vsx\fR" 4 +.IX Item "-mno-vsx" +.PD +Generate code that uses (does not use) vector/scalar (\s-1VSX\s0) +instructions, and also enable the use of built-in functions that allow +more direct access to the \s-1VSX\s0 instruction set. +.IP "\fB\-mfloat\-gprs=\fR\fIyes/single/double/no\fR" 4 +.IX Item "-mfloat-gprs=yes/single/double/no" +.PD 0 +.IP "\fB\-mfloat\-gprs\fR" 4 +.IX Item "-mfloat-gprs" +.PD +This switch enables or disables the generation of floating point +operations on the general purpose registers for architectures that +support it. +.Sp +The argument \fIyes\fR or \fIsingle\fR enables the use of +single-precision floating point operations. +.Sp +The argument \fIdouble\fR enables the use of single and +double-precision floating point operations. +.Sp +The argument \fIno\fR disables floating point operations on the +general purpose registers. +.Sp +This option is currently only available on the MPC854x. +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" +.PD 0 +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.PD +Generate code for 32\-bit or 64\-bit environments of Darwin and \s-1SVR4\s0 +targets (including GNU/Linux). The 32\-bit environment sets int, long +and pointer to 32 bits and generates code that runs on any PowerPC +variant. The 64\-bit environment sets int to 32 bits and long and +pointer to 64 bits, and generates code for PowerPC64, as for +\&\fB\-mpowerpc64\fR. +.IP "\fB\-mfull\-toc\fR" 4 +.IX Item "-mfull-toc" +.PD 0 +.IP "\fB\-mno\-fp\-in\-toc\fR" 4 +.IX Item "-mno-fp-in-toc" +.IP "\fB\-mno\-sum\-in\-toc\fR" 4 +.IX Item "-mno-sum-in-toc" +.IP "\fB\-mminimal\-toc\fR" 4 +.IX Item "-mminimal-toc" +.PD +Modify generation of the \s-1TOC\s0 (Table Of Contents), which is created for +every executable file. The \fB\-mfull\-toc\fR option is selected by +default. In that case, \s-1GCC\s0 will allocate at least one \s-1TOC\s0 entry for +each unique non-automatic variable reference in your program. \s-1GCC\s0 +will also place floating-point constants in the \s-1TOC\s0. However, only +16,384 entries are available in the \s-1TOC\s0. +.Sp +If you receive a linker error message that saying you have overflowed +the available \s-1TOC\s0 space, you can reduce the amount of \s-1TOC\s0 space used +with the \fB\-mno\-fp\-in\-toc\fR and \fB\-mno\-sum\-in\-toc\fR options. +\&\fB\-mno\-fp\-in\-toc\fR prevents \s-1GCC\s0 from putting floating-point +constants in the \s-1TOC\s0 and \fB\-mno\-sum\-in\-toc\fR forces \s-1GCC\s0 to +generate code to calculate the sum of an address and a constant at +run-time instead of putting that sum into the \s-1TOC\s0. You may specify one +or both of these options. Each causes \s-1GCC\s0 to produce very slightly +slower and larger code at the expense of conserving \s-1TOC\s0 space. +.Sp +If you still run out of space in the \s-1TOC\s0 even when you specify both of +these options, specify \fB\-mminimal\-toc\fR instead. This option causes +\&\s-1GCC\s0 to make only one \s-1TOC\s0 entry for every file. When you specify this +option, \s-1GCC\s0 will produce code that is slower and larger but which +uses extremely little \s-1TOC\s0 space. You may wish to use this option +only on files that contain less frequently executed code. +.IP "\fB\-maix64\fR" 4 +.IX Item "-maix64" +.PD 0 +.IP "\fB\-maix32\fR" 4 +.IX Item "-maix32" +.PD +Enable 64\-bit \s-1AIX\s0 \s-1ABI\s0 and calling convention: 64\-bit pointers, 64\-bit +\&\f(CW\*(C`long\*(C'\fR type, and the infrastructure needed to support them. +Specifying \fB\-maix64\fR implies \fB\-mpowerpc64\fR and +\&\fB\-mpowerpc\fR, while \fB\-maix32\fR disables the 64\-bit \s-1ABI\s0 and +implies \fB\-mno\-powerpc64\fR. \s-1GCC\s0 defaults to \fB\-maix32\fR. +.IP "\fB\-mxl\-compat\fR" 4 +.IX Item "-mxl-compat" +.PD 0 +.IP "\fB\-mno\-xl\-compat\fR" 4 +.IX Item "-mno-xl-compat" +.PD +Produce code that conforms more closely to \s-1IBM\s0 \s-1XL\s0 compiler semantics +when using AIX-compatible \s-1ABI\s0. Pass floating-point arguments to +prototyped functions beyond the register save area (\s-1RSA\s0) on the stack +in addition to argument FPRs. Do not assume that most significant +double in 128\-bit long double value is properly rounded when comparing +values and converting to double. Use \s-1XL\s0 symbol names for long double +support routines. +.Sp +The \s-1AIX\s0 calling convention was extended but not initially documented to +handle an obscure K&R C case of calling a function that takes the +address of its arguments with fewer arguments than declared. \s-1IBM\s0 \s-1XL\s0 +compilers access floating point arguments which do not fit in the +\&\s-1RSA\s0 from the stack when a subroutine is compiled without +optimization. Because always storing floating-point arguments on the +stack is inefficient and rarely needed, this option is not enabled by +default and only is necessary when calling subroutines compiled by \s-1IBM\s0 +\&\s-1XL\s0 compilers without optimization. +.IP "\fB\-mpe\fR" 4 +.IX Item "-mpe" +Support \fI\s-1IBM\s0 \s-1RS/6000\s0 \s-1SP\s0\fR \fIParallel Environment\fR (\s-1PE\s0). Link an +application written to use message passing with special startup code to +enable the application to run. The system must have \s-1PE\s0 installed in the +standard location (\fI/usr/lpp/ppe.poe/\fR), or the \fIspecs\fR file +must be overridden with the \fB\-specs=\fR option to specify the +appropriate directory location. The Parallel Environment does not +support threads, so the \fB\-mpe\fR option and the \fB\-pthread\fR +option are incompatible. +.IP "\fB\-malign\-natural\fR" 4 +.IX Item "-malign-natural" +.PD 0 +.IP "\fB\-malign\-power\fR" 4 +.IX Item "-malign-power" +.PD +On \s-1AIX\s0, 32\-bit Darwin, and 64\-bit PowerPC GNU/Linux, the option +\&\fB\-malign\-natural\fR overrides the ABI-defined alignment of larger +types, such as floating-point doubles, on their natural size-based boundary. +The option \fB\-malign\-power\fR instructs \s-1GCC\s0 to follow the ABI-specified +alignment rules. \s-1GCC\s0 defaults to the standard alignment defined in the \s-1ABI\s0. +.Sp +On 64\-bit Darwin, natural alignment is the default, and \fB\-malign\-power\fR +is not supported. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD 0 +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD +Generate code that does not use (uses) the floating-point register set. +Software floating point emulation is provided if you use the +\&\fB\-msoft\-float\fR option, and pass the option to \s-1GCC\s0 when linking. +.IP "\fB\-msingle\-float\fR" 4 +.IX Item "-msingle-float" +.PD 0 +.IP "\fB\-mdouble\-float\fR" 4 +.IX Item "-mdouble-float" +.PD +Generate code for single or double-precision floating point operations. +\&\fB\-mdouble\-float\fR implies \fB\-msingle\-float\fR. +.IP "\fB\-msimple\-fpu\fR" 4 +.IX Item "-msimple-fpu" +Do not generate sqrt and div instructions for hardware floating point unit. +.IP "\fB\-mfpu\fR" 4 +.IX Item "-mfpu" +Specify type of floating point unit. Valid values are \fIsp_lite\fR +(equivalent to \-msingle\-float \-msimple\-fpu), \fIdp_lite\fR (equivalent +to \-mdouble\-float \-msimple\-fpu), \fIsp_full\fR (equivalent to \-msingle\-float), +and \fIdp_full\fR (equivalent to \-mdouble\-float). +.IP "\fB\-mxilinx\-fpu\fR" 4 +.IX Item "-mxilinx-fpu" +Perform optimizations for floating point unit on Xilinx \s-1PPC\s0 405/440. +.IP "\fB\-mmultiple\fR" 4 +.IX Item "-mmultiple" +.PD 0 +.IP "\fB\-mno\-multiple\fR" 4 +.IX Item "-mno-multiple" +.PD +Generate code that uses (does not use) the load multiple word +instructions and the store multiple word instructions. These +instructions are generated by default on \s-1POWER\s0 systems, and not +generated on PowerPC systems. Do not use \fB\-mmultiple\fR on little +endian PowerPC systems, since those instructions do not work when the +processor is in little endian mode. The exceptions are \s-1PPC740\s0 and +\&\s-1PPC750\s0 which permit the instructions usage in little endian mode. +.IP "\fB\-mstring\fR" 4 +.IX Item "-mstring" +.PD 0 +.IP "\fB\-mno\-string\fR" 4 +.IX Item "-mno-string" +.PD +Generate code that uses (does not use) the load string instructions +and the store string word instructions to save multiple registers and +do small block moves. These instructions are generated by default on +\&\s-1POWER\s0 systems, and not generated on PowerPC systems. Do not use +\&\fB\-mstring\fR on little endian PowerPC systems, since those +instructions do not work when the processor is in little endian mode. +The exceptions are \s-1PPC740\s0 and \s-1PPC750\s0 which permit the instructions +usage in little endian mode. +.IP "\fB\-mupdate\fR" 4 +.IX Item "-mupdate" +.PD 0 +.IP "\fB\-mno\-update\fR" 4 +.IX Item "-mno-update" +.PD +Generate code that uses (does not use) the load or store instructions +that update the base register to the address of the calculated memory +location. These instructions are generated by default. If you use +\&\fB\-mno\-update\fR, there is a small window between the time that the +stack pointer is updated and the address of the previous frame is +stored, which means code that walks the stack frame across interrupts or +signals may get corrupted data. +.IP "\fB\-mavoid\-indexed\-addresses\fR" 4 +.IX Item "-mavoid-indexed-addresses" +.PD 0 +.IP "\fB\-mno\-avoid\-indexed\-addresses\fR" 4 +.IX Item "-mno-avoid-indexed-addresses" +.PD +Generate code that tries to avoid (not avoid) the use of indexed load +or store instructions. These instructions can incur a performance +penalty on Power6 processors in certain situations, such as when +stepping through large arrays that cross a 16M boundary. This option +is enabled by default when targetting Power6 and disabled otherwise. +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Generate code that uses (does not use) the floating point multiply and +accumulate instructions. These instructions are generated by default +if hardware floating point is used. The machine dependent +\&\fB\-mfused\-madd\fR option is now mapped to the machine independent +\&\fB\-ffp\-contract=fast\fR option, and \fB\-mno\-fused\-madd\fR is +mapped to \fB\-ffp\-contract=off\fR. +.IP "\fB\-mmulhw\fR" 4 +.IX Item "-mmulhw" +.PD 0 +.IP "\fB\-mno\-mulhw\fR" 4 +.IX Item "-mno-mulhw" +.PD +Generate code that uses (does not use) the half-word multiply and +multiply-accumulate instructions on the \s-1IBM\s0 405, 440, 464 and 476 processors. +These instructions are generated by default when targetting those +processors. +.IP "\fB\-mdlmzb\fR" 4 +.IX Item "-mdlmzb" +.PD 0 +.IP "\fB\-mno\-dlmzb\fR" 4 +.IX Item "-mno-dlmzb" +.PD +Generate code that uses (does not use) the string-search \fBdlmzb\fR +instruction on the \s-1IBM\s0 405, 440, 464 and 476 processors. This instruction is +generated by default when targetting those processors. +.IP "\fB\-mno\-bit\-align\fR" 4 +.IX Item "-mno-bit-align" +.PD 0 +.IP "\fB\-mbit\-align\fR" 4 +.IX Item "-mbit-align" +.PD +On System V.4 and embedded PowerPC systems do not (do) force structures +and unions that contain bit-fields to be aligned to the base type of the +bit-field. +.Sp +For example, by default a structure containing nothing but 8 +\&\f(CW\*(C`unsigned\*(C'\fR bit-fields of length 1 would be aligned to a 4 byte +boundary and have a size of 4 bytes. By using \fB\-mno\-bit\-align\fR, +the structure would be aligned to a 1 byte boundary and be one byte in +size. +.IP "\fB\-mno\-strict\-align\fR" 4 +.IX Item "-mno-strict-align" +.PD 0 +.IP "\fB\-mstrict\-align\fR" 4 +.IX Item "-mstrict-align" +.PD +On System V.4 and embedded PowerPC systems do not (do) assume that +unaligned memory references will be handled by the system. +.IP "\fB\-mrelocatable\fR" 4 +.IX Item "-mrelocatable" +.PD 0 +.IP "\fB\-mno\-relocatable\fR" 4 +.IX Item "-mno-relocatable" +.PD +Generate code that allows (does not allow) a static executable to be +relocated to a different address at runtime. A simple embedded +PowerPC system loader should relocate the entire contents of +\&\f(CW\*(C`.got2\*(C'\fR and 4\-byte locations listed in the \f(CW\*(C`.fixup\*(C'\fR section, +a table of 32\-bit addresses generated by this option. For this to +work, all objects linked together must be compiled with +\&\fB\-mrelocatable\fR or \fB\-mrelocatable\-lib\fR. +\&\fB\-mrelocatable\fR code aligns the stack to an 8 byte boundary. +.IP "\fB\-mrelocatable\-lib\fR" 4 +.IX Item "-mrelocatable-lib" +.PD 0 +.IP "\fB\-mno\-relocatable\-lib\fR" 4 +.IX Item "-mno-relocatable-lib" +.PD +Like \fB\-mrelocatable\fR, \fB\-mrelocatable\-lib\fR generates a +\&\f(CW\*(C`.fixup\*(C'\fR section to allow static executables to be relocated at +runtime, but \fB\-mrelocatable\-lib\fR does not use the smaller stack +alignment of \fB\-mrelocatable\fR. Objects compiled with +\&\fB\-mrelocatable\-lib\fR may be linked with objects compiled with +any combination of the \fB\-mrelocatable\fR options. +.IP "\fB\-mno\-toc\fR" 4 +.IX Item "-mno-toc" +.PD 0 +.IP "\fB\-mtoc\fR" 4 +.IX Item "-mtoc" +.PD +On System V.4 and embedded PowerPC systems do not (do) assume that +register 2 contains a pointer to a global area pointing to the addresses +used in the program. +.IP "\fB\-mlittle\fR" 4 +.IX Item "-mlittle" +.PD 0 +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +.PD +On System V.4 and embedded PowerPC systems compile code for the +processor in little endian mode. The \fB\-mlittle\-endian\fR option is +the same as \fB\-mlittle\fR. +.IP "\fB\-mbig\fR" 4 +.IX Item "-mbig" +.PD 0 +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +.PD +On System V.4 and embedded PowerPC systems compile code for the +processor in big endian mode. The \fB\-mbig\-endian\fR option is +the same as \fB\-mbig\fR. +.IP "\fB\-mdynamic\-no\-pic\fR" 4 +.IX Item "-mdynamic-no-pic" +On Darwin and Mac \s-1OS\s0 X systems, compile code so that it is not +relocatable, but that its external references are relocatable. The +resulting code is suitable for applications, but not shared +libraries. +.IP "\fB\-msingle\-pic\-base\fR" 4 +.IX Item "-msingle-pic-base" +Treat the register used for \s-1PIC\s0 addressing as read-only, rather than +loading it in the prologue for each function. The run-time system is +responsible for initializing this register with an appropriate value +before execution begins. +.IP "\fB\-mprioritize\-restricted\-insns=\fR\fIpriority\fR" 4 +.IX Item "-mprioritize-restricted-insns=priority" +This option controls the priority that is assigned to +dispatch-slot restricted instructions during the second scheduling +pass. The argument \fIpriority\fR takes the value \fI0/1/2\fR to assign +\&\fIno/highest/second\-highest\fR priority to dispatch slot restricted +instructions. +.IP "\fB\-msched\-costly\-dep=\fR\fIdependence_type\fR" 4 +.IX Item "-msched-costly-dep=dependence_type" +This option controls which dependences are considered costly +by the target during instruction scheduling. The argument +\&\fIdependence_type\fR takes one of the following values: +\&\fIno\fR: no dependence is costly, +\&\fIall\fR: all dependences are costly, +\&\fItrue_store_to_load\fR: a true dependence from store to load is costly, +\&\fIstore_to_load\fR: any dependence from store to load is costly, +\&\fInumber\fR: any dependence which latency >= \fInumber\fR is costly. +.IP "\fB\-minsert\-sched\-nops=\fR\fIscheme\fR" 4 +.IX Item "-minsert-sched-nops=scheme" +This option controls which nop insertion scheme will be used during +the second scheduling pass. The argument \fIscheme\fR takes one of the +following values: +\&\fIno\fR: Don't insert nops. +\&\fIpad\fR: Pad with nops any dispatch group which has vacant issue slots, +according to the scheduler's grouping. +\&\fIregroup_exact\fR: Insert nops to force costly dependent insns into +separate groups. Insert exactly as many nops as needed to force an insn +to a new group, according to the estimated processor grouping. +\&\fInumber\fR: Insert nops to force costly dependent insns into +separate groups. Insert \fInumber\fR nops to force an insn to a new group. +.IP "\fB\-mcall\-sysv\fR" 4 +.IX Item "-mcall-sysv" +On System V.4 and embedded PowerPC systems compile code using calling +conventions that adheres to the March 1995 draft of the System V +Application Binary Interface, PowerPC processor supplement. This is the +default unless you configured \s-1GCC\s0 using \fBpowerpc\-*\-eabiaix\fR. +.IP "\fB\-mcall\-sysv\-eabi\fR" 4 +.IX Item "-mcall-sysv-eabi" +.PD 0 +.IP "\fB\-mcall\-eabi\fR" 4 +.IX Item "-mcall-eabi" +.PD +Specify both \fB\-mcall\-sysv\fR and \fB\-meabi\fR options. +.IP "\fB\-mcall\-sysv\-noeabi\fR" 4 +.IX Item "-mcall-sysv-noeabi" +Specify both \fB\-mcall\-sysv\fR and \fB\-mno\-eabi\fR options. +.IP "\fB\-mcall\-aixdesc\fR" 4 +.IX Item "-mcall-aixdesc" +On System V.4 and embedded PowerPC systems compile code for the \s-1AIX\s0 +operating system. +.IP "\fB\-mcall\-linux\fR" 4 +.IX Item "-mcall-linux" +On System V.4 and embedded PowerPC systems compile code for the +Linux-based \s-1GNU\s0 system. +.IP "\fB\-mcall\-gnu\fR" 4 +.IX Item "-mcall-gnu" +On System V.4 and embedded PowerPC systems compile code for the +Hurd-based \s-1GNU\s0 system. +.IP "\fB\-mcall\-freebsd\fR" 4 +.IX Item "-mcall-freebsd" +On System V.4 and embedded PowerPC systems compile code for the +FreeBSD operating system. +.IP "\fB\-mcall\-netbsd\fR" 4 +.IX Item "-mcall-netbsd" +On System V.4 and embedded PowerPC systems compile code for the +NetBSD operating system. +.IP "\fB\-mcall\-openbsd\fR" 4 +.IX Item "-mcall-openbsd" +On System V.4 and embedded PowerPC systems compile code for the +OpenBSD operating system. +.IP "\fB\-maix\-struct\-return\fR" 4 +.IX Item "-maix-struct-return" +Return all structures in memory (as specified by the \s-1AIX\s0 \s-1ABI\s0). +.IP "\fB\-msvr4\-struct\-return\fR" 4 +.IX Item "-msvr4-struct-return" +Return structures smaller than 8 bytes in registers (as specified by the +\&\s-1SVR4\s0 \s-1ABI\s0). +.IP "\fB\-mabi=\fR\fIabi-type\fR" 4 +.IX Item "-mabi=abi-type" +Extend the current \s-1ABI\s0 with a particular extension, or remove such extension. +Valid values are \fIaltivec\fR, \fIno-altivec\fR, \fIspe\fR, +\&\fIno-spe\fR, \fIibmlongdouble\fR, \fIieeelongdouble\fR. +.IP "\fB\-mabi=spe\fR" 4 +.IX Item "-mabi=spe" +Extend the current \s-1ABI\s0 with \s-1SPE\s0 \s-1ABI\s0 extensions. This does not change +the default \s-1ABI\s0, instead it adds the \s-1SPE\s0 \s-1ABI\s0 extensions to the current +\&\s-1ABI\s0. +.IP "\fB\-mabi=no\-spe\fR" 4 +.IX Item "-mabi=no-spe" +Disable Booke \s-1SPE\s0 \s-1ABI\s0 extensions for the current \s-1ABI\s0. +.IP "\fB\-mabi=ibmlongdouble\fR" 4 +.IX Item "-mabi=ibmlongdouble" +Change the current \s-1ABI\s0 to use \s-1IBM\s0 extended precision long double. +This is a PowerPC 32\-bit \s-1SYSV\s0 \s-1ABI\s0 option. +.IP "\fB\-mabi=ieeelongdouble\fR" 4 +.IX Item "-mabi=ieeelongdouble" +Change the current \s-1ABI\s0 to use \s-1IEEE\s0 extended precision long double. +This is a PowerPC 32\-bit Linux \s-1ABI\s0 option. +.IP "\fB\-mprototype\fR" 4 +.IX Item "-mprototype" +.PD 0 +.IP "\fB\-mno\-prototype\fR" 4 +.IX Item "-mno-prototype" +.PD +On System V.4 and embedded PowerPC systems assume that all calls to +variable argument functions are properly prototyped. Otherwise, the +compiler must insert an instruction before every non prototyped call to +set or clear bit 6 of the condition code register (\fI\s-1CR\s0\fR) to +indicate whether floating point values were passed in the floating point +registers in case the function takes a variable arguments. With +\&\fB\-mprototype\fR, only calls to prototyped variable argument functions +will set or clear the bit. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +On embedded PowerPC systems, assume that the startup module is called +\&\fIsim\-crt0.o\fR and that the standard C libraries are \fIlibsim.a\fR and +\&\fIlibc.a\fR. This is the default for \fBpowerpc\-*\-eabisim\fR +configurations. +.IP "\fB\-mmvme\fR" 4 +.IX Item "-mmvme" +On embedded PowerPC systems, assume that the startup module is called +\&\fIcrt0.o\fR and the standard C libraries are \fIlibmvme.a\fR and +\&\fIlibc.a\fR. +.IP "\fB\-mads\fR" 4 +.IX Item "-mads" +On embedded PowerPC systems, assume that the startup module is called +\&\fIcrt0.o\fR and the standard C libraries are \fIlibads.a\fR and +\&\fIlibc.a\fR. +.IP "\fB\-myellowknife\fR" 4 +.IX Item "-myellowknife" +On embedded PowerPC systems, assume that the startup module is called +\&\fIcrt0.o\fR and the standard C libraries are \fIlibyk.a\fR and +\&\fIlibc.a\fR. +.IP "\fB\-mvxworks\fR" 4 +.IX Item "-mvxworks" +On System V.4 and embedded PowerPC systems, specify that you are +compiling for a VxWorks system. +.IP "\fB\-memb\fR" 4 +.IX Item "-memb" +On embedded PowerPC systems, set the \fI\s-1PPC_EMB\s0\fR bit in the \s-1ELF\s0 flags +header to indicate that \fBeabi\fR extended relocations are used. +.IP "\fB\-meabi\fR" 4 +.IX Item "-meabi" +.PD 0 +.IP "\fB\-mno\-eabi\fR" 4 +.IX Item "-mno-eabi" +.PD +On System V.4 and embedded PowerPC systems do (do not) adhere to the +Embedded Applications Binary Interface (eabi) which is a set of +modifications to the System V.4 specifications. Selecting \fB\-meabi\fR +means that the stack is aligned to an 8 byte boundary, a function +\&\f(CW\*(C`_\|_eabi\*(C'\fR is called to from \f(CW\*(C`main\*(C'\fR to set up the eabi +environment, and the \fB\-msdata\fR option can use both \f(CW\*(C`r2\*(C'\fR and +\&\f(CW\*(C`r13\*(C'\fR to point to two separate small data areas. Selecting +\&\fB\-mno\-eabi\fR means that the stack is aligned to a 16 byte boundary, +do not call an initialization function from \f(CW\*(C`main\*(C'\fR, and the +\&\fB\-msdata\fR option will only use \f(CW\*(C`r13\*(C'\fR to point to a single +small data area. The \fB\-meabi\fR option is on by default if you +configured \s-1GCC\s0 using one of the \fBpowerpc*\-*\-eabi*\fR options. +.IP "\fB\-msdata=eabi\fR" 4 +.IX Item "-msdata=eabi" +On System V.4 and embedded PowerPC systems, put small initialized +\&\f(CW\*(C`const\*(C'\fR global and static data in the \fB.sdata2\fR section, which +is pointed to by register \f(CW\*(C`r2\*(C'\fR. Put small initialized +non\-\f(CW\*(C`const\*(C'\fR global and static data in the \fB.sdata\fR section, +which is pointed to by register \f(CW\*(C`r13\*(C'\fR. Put small uninitialized +global and static data in the \fB.sbss\fR section, which is adjacent to +the \fB.sdata\fR section. The \fB\-msdata=eabi\fR option is +incompatible with the \fB\-mrelocatable\fR option. The +\&\fB\-msdata=eabi\fR option also sets the \fB\-memb\fR option. +.IP "\fB\-msdata=sysv\fR" 4 +.IX Item "-msdata=sysv" +On System V.4 and embedded PowerPC systems, put small global and static +data in the \fB.sdata\fR section, which is pointed to by register +\&\f(CW\*(C`r13\*(C'\fR. Put small uninitialized global and static data in the +\&\fB.sbss\fR section, which is adjacent to the \fB.sdata\fR section. +The \fB\-msdata=sysv\fR option is incompatible with the +\&\fB\-mrelocatable\fR option. +.IP "\fB\-msdata=default\fR" 4 +.IX Item "-msdata=default" +.PD 0 +.IP "\fB\-msdata\fR" 4 +.IX Item "-msdata" +.PD +On System V.4 and embedded PowerPC systems, if \fB\-meabi\fR is used, +compile code the same as \fB\-msdata=eabi\fR, otherwise compile code the +same as \fB\-msdata=sysv\fR. +.IP "\fB\-msdata=data\fR" 4 +.IX Item "-msdata=data" +On System V.4 and embedded PowerPC systems, put small global +data in the \fB.sdata\fR section. Put small uninitialized global +data in the \fB.sbss\fR section. Do not use register \f(CW\*(C`r13\*(C'\fR +to address small data however. This is the default behavior unless +other \fB\-msdata\fR options are used. +.IP "\fB\-msdata=none\fR" 4 +.IX Item "-msdata=none" +.PD 0 +.IP "\fB\-mno\-sdata\fR" 4 +.IX Item "-mno-sdata" +.PD +On embedded PowerPC systems, put all initialized global and static data +in the \fB.data\fR section, and all uninitialized data in the +\&\fB.bss\fR section. +.IP "\fB\-mblock\-move\-inline\-limit=\fR\fInum\fR" 4 +.IX Item "-mblock-move-inline-limit=num" +Inline all block moves (such as calls to \f(CW\*(C`memcpy\*(C'\fR or structure +copies) less than or equal to \fInum\fR bytes. The minimum value for +\&\fInum\fR is 32 bytes on 32\-bit targets and 64 bytes on 64\-bit +targets. The default value is target-specific. +.IP "\fB\-G\fR \fInum\fR" 4 +.IX Item "-G num" +On embedded PowerPC systems, put global and static items less than or +equal to \fInum\fR bytes into the small data or bss sections instead of +the normal data or bss section. By default, \fInum\fR is 8. The +\&\fB\-G\fR \fInum\fR switch is also passed to the linker. +All modules should be compiled with the same \fB\-G\fR \fInum\fR value. +.IP "\fB\-mregnames\fR" 4 +.IX Item "-mregnames" +.PD 0 +.IP "\fB\-mno\-regnames\fR" 4 +.IX Item "-mno-regnames" +.PD +On System V.4 and embedded PowerPC systems do (do not) emit register +names in the assembly language output using symbolic forms. +.IP "\fB\-mlongcall\fR" 4 +.IX Item "-mlongcall" +.PD 0 +.IP "\fB\-mno\-longcall\fR" 4 +.IX Item "-mno-longcall" +.PD +By default assume that all calls are far away so that a longer more +expensive calling sequence is required. This is required for calls +further than 32 megabytes (33,554,432 bytes) from the current location. +A short call will be generated if the compiler knows +the call cannot be that far away. This setting can be overridden by +the \f(CW\*(C`shortcall\*(C'\fR function attribute, or by \f(CW\*(C`#pragma +longcall(0)\*(C'\fR. +.Sp +Some linkers are capable of detecting out-of-range calls and generating +glue code on the fly. On these systems, long calls are unnecessary and +generate slower code. As of this writing, the \s-1AIX\s0 linker can do this, +as can the \s-1GNU\s0 linker for PowerPC/64. It is planned to add this feature +to the \s-1GNU\s0 linker for 32\-bit PowerPC systems as well. +.Sp +On Darwin/PPC systems, \f(CW\*(C`#pragma longcall\*(C'\fR will generate \*(L"jbsr +callee, L42\*(R", plus a \*(L"branch island\*(R" (glue code). The two target +addresses represent the callee and the \*(L"branch island\*(R". The +Darwin/PPC linker will prefer the first address and generate a \*(L"bl +callee\*(R" if the \s-1PPC\s0 \*(L"bl\*(R" instruction will reach the callee directly; +otherwise, the linker will generate \*(L"bl L42\*(R" to call the \*(L"branch +island\*(R". The \*(L"branch island\*(R" is appended to the body of the +calling function; it computes the full 32\-bit address of the callee +and jumps to it. +.Sp +On Mach-O (Darwin) systems, this option directs the compiler emit to +the glue for every direct call, and the Darwin linker decides whether +to use or discard it. +.Sp +In the future, we may cause \s-1GCC\s0 to ignore all longcall specifications +when the linker is known to generate glue. +.IP "\fB\-mtls\-markers\fR" 4 +.IX Item "-mtls-markers" +.PD 0 +.IP "\fB\-mno\-tls\-markers\fR" 4 +.IX Item "-mno-tls-markers" +.PD +Mark (do not mark) calls to \f(CW\*(C`_\|_tls_get_addr\*(C'\fR with a relocation +specifying the function argument. The relocation allows ld to +reliably associate function call with argument setup instructions for +\&\s-1TLS\s0 optimization, which in turn allows gcc to better schedule the +sequence. +.IP "\fB\-pthread\fR" 4 +.IX Item "-pthread" +Adds support for multithreading with the \fIpthreads\fR library. +This option sets flags for both the preprocessor and linker. +.IP "\fB\-mrecip\fR" 4 +.IX Item "-mrecip" +.PD 0 +.IP "\fB\-mno\-recip\fR" 4 +.IX Item "-mno-recip" +.PD +This option will enable \s-1GCC\s0 to use the reciprocal estimate and +reciprocal square root estimate instructions with additional +Newton-Raphson steps to increase precision instead of doing a divide or +square root and divide for floating point arguments. You should use +the \fB\-ffast\-math\fR option when using \fB\-mrecip\fR (or at +least \fB\-funsafe\-math\-optimizations\fR, +\&\fB\-finite\-math\-only\fR, \fB\-freciprocal\-math\fR and +\&\fB\-fno\-trapping\-math\fR). Note that while the throughput of the +sequence is generally higher than the throughput of the non-reciprocal +instruction, the precision of the sequence can be decreased by up to 2 +ulp (i.e. the inverse of 1.0 equals 0.99999994) for reciprocal square +roots. +.IP "\fB\-mrecip=\fR\fIopt\fR" 4 +.IX Item "-mrecip=opt" +This option allows to control which reciprocal estimate instructions +may be used. \fIopt\fR is a comma separated list of options, that may +be preceded by a \f(CW\*(C`!\*(C'\fR to invert the option: +\&\f(CW\*(C`all\*(C'\fR: enable all estimate instructions, +\&\f(CW\*(C`default\*(C'\fR: enable the default instructions, equivalent to \fB\-mrecip\fR, +\&\f(CW\*(C`none\*(C'\fR: disable all estimate instructions, equivalent to \fB\-mno\-recip\fR; +\&\f(CW\*(C`div\*(C'\fR: enable the reciprocal approximation instructions for both single and double precision; +\&\f(CW\*(C`divf\*(C'\fR: enable the single precision reciprocal approximation instructions; +\&\f(CW\*(C`divd\*(C'\fR: enable the double precision reciprocal approximation instructions; +\&\f(CW\*(C`rsqrt\*(C'\fR: enable the reciprocal square root approximation instructions for both single and double precision; +\&\f(CW\*(C`rsqrtf\*(C'\fR: enable the single precision reciprocal square root approximation instructions; +\&\f(CW\*(C`rsqrtd\*(C'\fR: enable the double precision reciprocal square root approximation instructions; +.Sp +So for example, \fB\-mrecip=all,!rsqrtd\fR would enable the +all of the reciprocal estimate instructions, except for the +\&\f(CW\*(C`FRSQRTE\*(C'\fR, \f(CW\*(C`XSRSQRTEDP\*(C'\fR, and \f(CW\*(C`XVRSQRTEDP\*(C'\fR instructions +which handle the double precision reciprocal square root calculations. +.IP "\fB\-mrecip\-precision\fR" 4 +.IX Item "-mrecip-precision" +.PD 0 +.IP "\fB\-mno\-recip\-precision\fR" 4 +.IX Item "-mno-recip-precision" +.PD +Assume (do not assume) that the reciprocal estimate instructions +provide higher precision estimates than is mandated by the powerpc +\&\s-1ABI\s0. Selecting \fB\-mcpu=power6\fR or \fB\-mcpu=power7\fR +automatically selects \fB\-mrecip\-precision\fR. The double +precision square root estimate instructions are not generated by +default on low precision machines, since they do not provide an +estimate that converges after three steps. +.IP "\fB\-mveclibabi=\fR\fItype\fR" 4 +.IX Item "-mveclibabi=type" +Specifies the \s-1ABI\s0 type to use for vectorizing intrinsics using an +external library. The only type supported at present is \f(CW\*(C`mass\*(C'\fR, +which specifies to use \s-1IBM\s0's Mathematical Acceleration Subsystem +(\s-1MASS\s0) libraries for vectorizing intrinsics using external libraries. +\&\s-1GCC\s0 will currently emit calls to \f(CW\*(C`acosd2\*(C'\fR, \f(CW\*(C`acosf4\*(C'\fR, +\&\f(CW\*(C`acoshd2\*(C'\fR, \f(CW\*(C`acoshf4\*(C'\fR, \f(CW\*(C`asind2\*(C'\fR, \f(CW\*(C`asinf4\*(C'\fR, +\&\f(CW\*(C`asinhd2\*(C'\fR, \f(CW\*(C`asinhf4\*(C'\fR, \f(CW\*(C`atan2d2\*(C'\fR, \f(CW\*(C`atan2f4\*(C'\fR, +\&\f(CW\*(C`atand2\*(C'\fR, \f(CW\*(C`atanf4\*(C'\fR, \f(CW\*(C`atanhd2\*(C'\fR, \f(CW\*(C`atanhf4\*(C'\fR, +\&\f(CW\*(C`cbrtd2\*(C'\fR, \f(CW\*(C`cbrtf4\*(C'\fR, \f(CW\*(C`cosd2\*(C'\fR, \f(CW\*(C`cosf4\*(C'\fR, +\&\f(CW\*(C`coshd2\*(C'\fR, \f(CW\*(C`coshf4\*(C'\fR, \f(CW\*(C`erfcd2\*(C'\fR, \f(CW\*(C`erfcf4\*(C'\fR, +\&\f(CW\*(C`erfd2\*(C'\fR, \f(CW\*(C`erff4\*(C'\fR, \f(CW\*(C`exp2d2\*(C'\fR, \f(CW\*(C`exp2f4\*(C'\fR, +\&\f(CW\*(C`expd2\*(C'\fR, \f(CW\*(C`expf4\*(C'\fR, \f(CW\*(C`expm1d2\*(C'\fR, \f(CW\*(C`expm1f4\*(C'\fR, +\&\f(CW\*(C`hypotd2\*(C'\fR, \f(CW\*(C`hypotf4\*(C'\fR, \f(CW\*(C`lgammad2\*(C'\fR, \f(CW\*(C`lgammaf4\*(C'\fR, +\&\f(CW\*(C`log10d2\*(C'\fR, \f(CW\*(C`log10f4\*(C'\fR, \f(CW\*(C`log1pd2\*(C'\fR, \f(CW\*(C`log1pf4\*(C'\fR, +\&\f(CW\*(C`log2d2\*(C'\fR, \f(CW\*(C`log2f4\*(C'\fR, \f(CW\*(C`logd2\*(C'\fR, \f(CW\*(C`logf4\*(C'\fR, +\&\f(CW\*(C`powd2\*(C'\fR, \f(CW\*(C`powf4\*(C'\fR, \f(CW\*(C`sind2\*(C'\fR, \f(CW\*(C`sinf4\*(C'\fR, \f(CW\*(C`sinhd2\*(C'\fR, +\&\f(CW\*(C`sinhf4\*(C'\fR, \f(CW\*(C`sqrtd2\*(C'\fR, \f(CW\*(C`sqrtf4\*(C'\fR, \f(CW\*(C`tand2\*(C'\fR, +\&\f(CW\*(C`tanf4\*(C'\fR, \f(CW\*(C`tanhd2\*(C'\fR, and \f(CW\*(C`tanhf4\*(C'\fR when generating code +for power7. Both \fB\-ftree\-vectorize\fR and +\&\fB\-funsafe\-math\-optimizations\fR have to be enabled. The \s-1MASS\s0 +libraries will have to be specified at link time. +.IP "\fB\-mfriz\fR" 4 +.IX Item "-mfriz" +.PD 0 +.IP "\fB\-mno\-friz\fR" 4 +.IX Item "-mno-friz" +.PD +Generate (do not generate) the \f(CW\*(C`friz\*(C'\fR instruction when the +\&\fB\-funsafe\-math\-optimizations\fR option is used to optimize +rounding a floating point value to 64\-bit integer and back to floating +point. The \f(CW\*(C`friz\*(C'\fR instruction does not return the same value if +the floating point number is too large to fit in an integer. +.PP +\fI\s-1RX\s0 Options\fR +.IX Subsection "RX Options" +.PP +These command line options are defined for \s-1RX\s0 targets: +.IP "\fB\-m64bit\-doubles\fR" 4 +.IX Item "-m64bit-doubles" +.PD 0 +.IP "\fB\-m32bit\-doubles\fR" 4 +.IX Item "-m32bit-doubles" +.PD +Make the \f(CW\*(C`double\*(C'\fR data type be 64\-bits (\fB\-m64bit\-doubles\fR) +or 32\-bits (\fB\-m32bit\-doubles\fR) in size. The default is +\&\fB\-m32bit\-doubles\fR. \fINote\fR \s-1RX\s0 floating point hardware only +works on 32\-bit values, which is why the default is +\&\fB\-m32bit\-doubles\fR. +.IP "\fB\-fpu\fR" 4 +.IX Item "-fpu" +.PD 0 +.IP "\fB\-nofpu\fR" 4 +.IX Item "-nofpu" +.PD +Enables (\fB\-fpu\fR) or disables (\fB\-nofpu\fR) the use of \s-1RX\s0 +floating point hardware. The default is enabled for the \fI\s-1RX600\s0\fR +series and disabled for the \fI\s-1RX200\s0\fR series. +.Sp +Floating point instructions will only be generated for 32\-bit floating +point values however, so if the \fB\-m64bit\-doubles\fR option is in +use then the \s-1FPU\s0 hardware will not be used for doubles. +.Sp +\&\fINote\fR If the \fB\-fpu\fR option is enabled then +\&\fB\-funsafe\-math\-optimizations\fR is also enabled automatically. +This is because the \s-1RX\s0 \s-1FPU\s0 instructions are themselves unsafe. +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +Selects the type of \s-1RX\s0 \s-1CPU\s0 to be targeted. Currently three types are +supported, the generic \fI\s-1RX600\s0\fR and \fI\s-1RX200\s0\fR series hardware and +the specific \fI\s-1RX610\s0\fR \s-1CPU\s0. The default is \fI\s-1RX600\s0\fR. +.Sp +The only difference between \fI\s-1RX600\s0\fR and \fI\s-1RX610\s0\fR is that the +\&\fI\s-1RX610\s0\fR does not support the \f(CW\*(C`MVTIPL\*(C'\fR instruction. +.Sp +The \fI\s-1RX200\s0\fR series does not have a hardware floating point unit +and so \fB\-nofpu\fR is enabled by default when this type is +selected. +.IP "\fB\-mbig\-endian\-data\fR" 4 +.IX Item "-mbig-endian-data" +.PD 0 +.IP "\fB\-mlittle\-endian\-data\fR" 4 +.IX Item "-mlittle-endian-data" +.PD +Store data (but not code) in the big-endian format. The default is +\&\fB\-mlittle\-endian\-data\fR, i.e. to store data in the little endian +format. +.IP "\fB\-msmall\-data\-limit=\fR\fIN\fR" 4 +.IX Item "-msmall-data-limit=N" +Specifies the maximum size in bytes of global and static variables +which can be placed into the small data area. Using the small data +area can lead to smaller and faster code, but the size of area is +limited and it is up to the programmer to ensure that the area does +not overflow. Also when the small data area is used one of the \s-1RX\s0's +registers (\f(CW\*(C`r13\*(C'\fR) is reserved for use pointing to this area, so +it is no longer available for use by the compiler. This could result +in slower and/or larger code if variables which once could have been +held in \f(CW\*(C`r13\*(C'\fR are now pushed onto the stack. +.Sp +Note, common variables (variables which have not been initialised) and +constants are not placed into the small data area as they are assigned +to other sections in the output executable. +.Sp +The default value is zero, which disables this feature. Note, this +feature is not enabled by default with higher optimization levels +(\fB\-O2\fR etc) because of the potentially detrimental effects of +reserving register \f(CW\*(C`r13\*(C'\fR. It is up to the programmer to +experiment and discover whether this feature is of benefit to their +program. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +.PD 0 +.IP "\fB\-mno\-sim\fR" 4 +.IX Item "-mno-sim" +.PD +Use the simulator runtime. The default is to use the libgloss board +specific runtime. +.IP "\fB\-mas100\-syntax\fR" 4 +.IX Item "-mas100-syntax" +.PD 0 +.IP "\fB\-mno\-as100\-syntax\fR" 4 +.IX Item "-mno-as100-syntax" +.PD +When generating assembler output use a syntax that is compatible with +Renesas's \s-1AS100\s0 assembler. This syntax can also be handled by the \s-1GAS\s0 +assembler but it has some restrictions so generating it is not the +default option. +.IP "\fB\-mmax\-constant\-size=\fR\fIN\fR" 4 +.IX Item "-mmax-constant-size=N" +Specifies the maximum size, in bytes, of a constant that can be used as +an operand in a \s-1RX\s0 instruction. Although the \s-1RX\s0 instruction set does +allow constants of up to 4 bytes in length to be used in instructions, +a longer value equates to a longer instruction. Thus in some +circumstances it can be beneficial to restrict the size of constants +that are used in instructions. Constants that are too big are instead +placed into a constant pool and referenced via register indirection. +.Sp +The value \fIN\fR can be between 0 and 4. A value of 0 (the default) +or 4 means that constants of any size are allowed. +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +Enable linker relaxation. Linker relaxation is a process whereby the +linker will attempt to reduce the size of a program by finding shorter +versions of various instructions. Disabled by default. +.IP "\fB\-mint\-register=\fR\fIN\fR" 4 +.IX Item "-mint-register=N" +Specify the number of registers to reserve for fast interrupt handler +functions. The value \fIN\fR can be between 0 and 4. A value of 1 +means that register \f(CW\*(C`r13\*(C'\fR will be reserved for the exclusive use +of fast interrupt handlers. A value of 2 reserves \f(CW\*(C`r13\*(C'\fR and +\&\f(CW\*(C`r12\*(C'\fR. A value of 3 reserves \f(CW\*(C`r13\*(C'\fR, \f(CW\*(C`r12\*(C'\fR and +\&\f(CW\*(C`r11\*(C'\fR, and a value of 4 reserves \f(CW\*(C`r13\*(C'\fR through \f(CW\*(C`r10\*(C'\fR. +A value of 0, the default, does not reserve any registers. +.IP "\fB\-msave\-acc\-in\-interrupts\fR" 4 +.IX Item "-msave-acc-in-interrupts" +Specifies that interrupt handler functions should preserve the +accumulator register. This is only necessary if normal code might use +the accumulator register, for example because it performs 64\-bit +multiplications. The default is to ignore the accumulator as this +makes the interrupt handlers faster. +.PP +\&\fINote:\fR The generic \s-1GCC\s0 command line \fB\-ffixed\-\fR\fIreg\fR +has special significance to the \s-1RX\s0 port when used with the +\&\f(CW\*(C`interrupt\*(C'\fR function attribute. This attribute indicates a +function intended to process fast interrupts. \s-1GCC\s0 will will ensure +that it only uses the registers \f(CW\*(C`r10\*(C'\fR, \f(CW\*(C`r11\*(C'\fR, \f(CW\*(C`r12\*(C'\fR +and/or \f(CW\*(C`r13\*(C'\fR and only provided that the normal use of the +corresponding registers have been restricted via the +\&\fB\-ffixed\-\fR\fIreg\fR or \fB\-mint\-register\fR command line +options. +.PP +\fIS/390 and zSeries Options\fR +.IX Subsection "S/390 and zSeries Options" +.PP +These are the \fB\-m\fR options defined for the S/390 and zSeries architecture. +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD 0 +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD +Use (do not use) the hardware floating-point instructions and registers +for floating-point operations. When \fB\-msoft\-float\fR is specified, +functions in \fIlibgcc.a\fR will be used to perform floating-point +operations. When \fB\-mhard\-float\fR is specified, the compiler +generates \s-1IEEE\s0 floating-point instructions. This is the default. +.IP "\fB\-mhard\-dfp\fR" 4 +.IX Item "-mhard-dfp" +.PD 0 +.IP "\fB\-mno\-hard\-dfp\fR" 4 +.IX Item "-mno-hard-dfp" +.PD +Use (do not use) the hardware decimal-floating-point instructions for +decimal-floating-point operations. When \fB\-mno\-hard\-dfp\fR is +specified, functions in \fIlibgcc.a\fR will be used to perform +decimal-floating-point operations. When \fB\-mhard\-dfp\fR is +specified, the compiler generates decimal-floating-point hardware +instructions. This is the default for \fB\-march=z9\-ec\fR or higher. +.IP "\fB\-mlong\-double\-64\fR" 4 +.IX Item "-mlong-double-64" +.PD 0 +.IP "\fB\-mlong\-double\-128\fR" 4 +.IX Item "-mlong-double-128" +.PD +These switches control the size of \f(CW\*(C`long double\*(C'\fR type. A size +of 64bit makes the \f(CW\*(C`long double\*(C'\fR type equivalent to the \f(CW\*(C`double\*(C'\fR +type. This is the default. +.IP "\fB\-mbackchain\fR" 4 +.IX Item "-mbackchain" +.PD 0 +.IP "\fB\-mno\-backchain\fR" 4 +.IX Item "-mno-backchain" +.PD +Store (do not store) the address of the caller's frame as backchain pointer +into the callee's stack frame. +A backchain may be needed to allow debugging using tools that do not understand +\&\s-1DWARF\-2\s0 call frame information. +When \fB\-mno\-packed\-stack\fR is in effect, the backchain pointer is stored +at the bottom of the stack frame; when \fB\-mpacked\-stack\fR is in effect, +the backchain is placed into the topmost word of the 96/160 byte register +save area. +.Sp +In general, code compiled with \fB\-mbackchain\fR is call-compatible with +code compiled with \fB\-mmo\-backchain\fR; however, use of the backchain +for debugging purposes usually requires that the whole binary is built with +\&\fB\-mbackchain\fR. Note that the combination of \fB\-mbackchain\fR, +\&\fB\-mpacked\-stack\fR and \fB\-mhard\-float\fR is not supported. In order +to build a linux kernel use \fB\-msoft\-float\fR. +.Sp +The default is to not maintain the backchain. +.IP "\fB\-mpacked\-stack\fR" 4 +.IX Item "-mpacked-stack" +.PD 0 +.IP "\fB\-mno\-packed\-stack\fR" 4 +.IX Item "-mno-packed-stack" +.PD +Use (do not use) the packed stack layout. When \fB\-mno\-packed\-stack\fR is +specified, the compiler uses the all fields of the 96/160 byte register save +area only for their default purpose; unused fields still take up stack space. +When \fB\-mpacked\-stack\fR is specified, register save slots are densely +packed at the top of the register save area; unused space is reused for other +purposes, allowing for more efficient use of the available stack space. +However, when \fB\-mbackchain\fR is also in effect, the topmost word of +the save area is always used to store the backchain, and the return address +register is always saved two words below the backchain. +.Sp +As long as the stack frame backchain is not used, code generated with +\&\fB\-mpacked\-stack\fR is call-compatible with code generated with +\&\fB\-mno\-packed\-stack\fR. Note that some non-FSF releases of \s-1GCC\s0 2.95 for +S/390 or zSeries generated code that uses the stack frame backchain at run +time, not just for debugging purposes. Such code is not call-compatible +with code compiled with \fB\-mpacked\-stack\fR. Also, note that the +combination of \fB\-mbackchain\fR, +\&\fB\-mpacked\-stack\fR and \fB\-mhard\-float\fR is not supported. In order +to build a linux kernel use \fB\-msoft\-float\fR. +.Sp +The default is to not use the packed stack layout. +.IP "\fB\-msmall\-exec\fR" 4 +.IX Item "-msmall-exec" +.PD 0 +.IP "\fB\-mno\-small\-exec\fR" 4 +.IX Item "-mno-small-exec" +.PD +Generate (or do not generate) code using the \f(CW\*(C`bras\*(C'\fR instruction +to do subroutine calls. +This only works reliably if the total executable size does not +exceed 64k. The default is to use the \f(CW\*(C`basr\*(C'\fR instruction instead, +which does not have this limitation. +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.PD 0 +.IP "\fB\-m31\fR" 4 +.IX Item "-m31" +.PD +When \fB\-m31\fR is specified, generate code compliant to the +GNU/Linux for S/390 \s-1ABI\s0. When \fB\-m64\fR is specified, generate +code compliant to the GNU/Linux for zSeries \s-1ABI\s0. This allows \s-1GCC\s0 in +particular to generate 64\-bit instructions. For the \fBs390\fR +targets, the default is \fB\-m31\fR, while the \fBs390x\fR +targets default to \fB\-m64\fR. +.IP "\fB\-mzarch\fR" 4 +.IX Item "-mzarch" +.PD 0 +.IP "\fB\-mesa\fR" 4 +.IX Item "-mesa" +.PD +When \fB\-mzarch\fR is specified, generate code using the +instructions available on z/Architecture. +When \fB\-mesa\fR is specified, generate code using the +instructions available on \s-1ESA/390\s0. Note that \fB\-mesa\fR is +not possible with \fB\-m64\fR. +When generating code compliant to the GNU/Linux for S/390 \s-1ABI\s0, +the default is \fB\-mesa\fR. When generating code compliant +to the GNU/Linux for zSeries \s-1ABI\s0, the default is \fB\-mzarch\fR. +.IP "\fB\-mmvcle\fR" 4 +.IX Item "-mmvcle" +.PD 0 +.IP "\fB\-mno\-mvcle\fR" 4 +.IX Item "-mno-mvcle" +.PD +Generate (or do not generate) code using the \f(CW\*(C`mvcle\*(C'\fR instruction +to perform block moves. When \fB\-mno\-mvcle\fR is specified, +use a \f(CW\*(C`mvc\*(C'\fR loop instead. This is the default unless optimizing for +size. +.IP "\fB\-mdebug\fR" 4 +.IX Item "-mdebug" +.PD 0 +.IP "\fB\-mno\-debug\fR" 4 +.IX Item "-mno-debug" +.PD +Print (or do not print) additional debug information when compiling. +The default is to not print debug information. +.IP "\fB\-march=\fR\fIcpu-type\fR" 4 +.IX Item "-march=cpu-type" +Generate code that will run on \fIcpu-type\fR, which is the name of a system +representing a certain processor type. Possible values for +\&\fIcpu-type\fR are \fBg5\fR, \fBg6\fR, \fBz900\fR, \fBz990\fR, +\&\fBz9\-109\fR, \fBz9\-ec\fR and \fBz10\fR. +When generating code using the instructions available on z/Architecture, +the default is \fB\-march=z900\fR. Otherwise, the default is +\&\fB\-march=g5\fR. +.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 +.IX Item "-mtune=cpu-type" +Tune to \fIcpu-type\fR everything applicable about the generated code, +except for the \s-1ABI\s0 and the set of available instructions. +The list of \fIcpu-type\fR values is the same as for \fB\-march\fR. +The default is the value used for \fB\-march\fR. +.IP "\fB\-mtpf\-trace\fR" 4 +.IX Item "-mtpf-trace" +.PD 0 +.IP "\fB\-mno\-tpf\-trace\fR" 4 +.IX Item "-mno-tpf-trace" +.PD +Generate code that adds (does not add) in \s-1TPF\s0 \s-1OS\s0 specific branches to trace +routines in the operating system. This option is off by default, even +when compiling for the \s-1TPF\s0 \s-1OS\s0. +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Generate code that uses (does not use) the floating point multiply and +accumulate instructions. These instructions are generated by default if +hardware floating point is used. +.IP "\fB\-mwarn\-framesize=\fR\fIframesize\fR" 4 +.IX Item "-mwarn-framesize=framesize" +Emit a warning if the current function exceeds the given frame size. Because +this is a compile time check it doesn't need to be a real problem when the program +runs. It is intended to identify functions which most probably cause +a stack overflow. It is useful to be used in an environment with limited stack +size e.g. the linux kernel. +.IP "\fB\-mwarn\-dynamicstack\fR" 4 +.IX Item "-mwarn-dynamicstack" +Emit a warning if the function calls alloca or uses dynamically +sized arrays. This is generally a bad idea with a limited stack size. +.IP "\fB\-mstack\-guard=\fR\fIstack-guard\fR" 4 +.IX Item "-mstack-guard=stack-guard" +.PD 0 +.IP "\fB\-mstack\-size=\fR\fIstack-size\fR" 4 +.IX Item "-mstack-size=stack-size" +.PD +If these options are provided the s390 back end emits additional instructions in +the function prologue which trigger a trap if the stack size is \fIstack-guard\fR +bytes above the \fIstack-size\fR (remember that the stack on s390 grows downward). +If the \fIstack-guard\fR option is omitted the smallest power of 2 larger than +the frame size of the compiled function is chosen. +These options are intended to be used to help debugging stack overflow problems. +The additionally emitted code causes only little overhead and hence can also be +used in production like systems without greater performance degradation. The given +values have to be exact powers of 2 and \fIstack-size\fR has to be greater than +\&\fIstack-guard\fR without exceeding 64k. +In order to be efficient the extra code makes the assumption that the stack starts +at an address aligned to the value given by \fIstack-size\fR. +The \fIstack-guard\fR option can only be used in conjunction with \fIstack-size\fR. +.PP +\fIScore Options\fR +.IX Subsection "Score Options" +.PP +These options are defined for Score implementations: +.IP "\fB\-meb\fR" 4 +.IX Item "-meb" +Compile code for big endian mode. This is the default. +.IP "\fB\-mel\fR" 4 +.IX Item "-mel" +Compile code for little endian mode. +.IP "\fB\-mnhwloop\fR" 4 +.IX Item "-mnhwloop" +Disable generate bcnz instruction. +.IP "\fB\-muls\fR" 4 +.IX Item "-muls" +Enable generate unaligned load and store instruction. +.IP "\fB\-mmac\fR" 4 +.IX Item "-mmac" +Enable the use of multiply-accumulate instructions. Disabled by default. +.IP "\fB\-mscore5\fR" 4 +.IX Item "-mscore5" +Specify the \s-1SCORE5\s0 as the target architecture. +.IP "\fB\-mscore5u\fR" 4 +.IX Item "-mscore5u" +Specify the \s-1SCORE5U\s0 of the target architecture. +.IP "\fB\-mscore7\fR" 4 +.IX Item "-mscore7" +Specify the \s-1SCORE7\s0 as the target architecture. This is the default. +.IP "\fB\-mscore7d\fR" 4 +.IX Item "-mscore7d" +Specify the \s-1SCORE7D\s0 as the target architecture. +.PP +\fI\s-1SH\s0 Options\fR +.IX Subsection "SH Options" +.PP +These \fB\-m\fR options are defined for the \s-1SH\s0 implementations: +.IP "\fB\-m1\fR" 4 +.IX Item "-m1" +Generate code for the \s-1SH1\s0. +.IP "\fB\-m2\fR" 4 +.IX Item "-m2" +Generate code for the \s-1SH2\s0. +.IP "\fB\-m2e\fR" 4 +.IX Item "-m2e" +Generate code for the SH2e. +.IP "\fB\-m2a\-nofpu\fR" 4 +.IX Item "-m2a-nofpu" +Generate code for the SH2a without \s-1FPU\s0, or for a SH2a\-FPU in such a way +that the floating-point unit is not used. +.IP "\fB\-m2a\-single\-only\fR" 4 +.IX Item "-m2a-single-only" +Generate code for the SH2a\-FPU, in such a way that no double-precision +floating point operations are used. +.IP "\fB\-m2a\-single\fR" 4 +.IX Item "-m2a-single" +Generate code for the SH2a\-FPU assuming the floating-point unit is in +single-precision mode by default. +.IP "\fB\-m2a\fR" 4 +.IX Item "-m2a" +Generate code for the SH2a\-FPU assuming the floating-point unit is in +double-precision mode by default. +.IP "\fB\-m3\fR" 4 +.IX Item "-m3" +Generate code for the \s-1SH3\s0. +.IP "\fB\-m3e\fR" 4 +.IX Item "-m3e" +Generate code for the SH3e. +.IP "\fB\-m4\-nofpu\fR" 4 +.IX Item "-m4-nofpu" +Generate code for the \s-1SH4\s0 without a floating-point unit. +.IP "\fB\-m4\-single\-only\fR" 4 +.IX Item "-m4-single-only" +Generate code for the \s-1SH4\s0 with a floating-point unit that only +supports single-precision arithmetic. +.IP "\fB\-m4\-single\fR" 4 +.IX Item "-m4-single" +Generate code for the \s-1SH4\s0 assuming the floating-point unit is in +single-precision mode by default. +.IP "\fB\-m4\fR" 4 +.IX Item "-m4" +Generate code for the \s-1SH4\s0. +.IP "\fB\-m4a\-nofpu\fR" 4 +.IX Item "-m4a-nofpu" +Generate code for the SH4al\-dsp, or for a SH4a in such a way that the +floating-point unit is not used. +.IP "\fB\-m4a\-single\-only\fR" 4 +.IX Item "-m4a-single-only" +Generate code for the SH4a, in such a way that no double-precision +floating point operations are used. +.IP "\fB\-m4a\-single\fR" 4 +.IX Item "-m4a-single" +Generate code for the SH4a assuming the floating-point unit is in +single-precision mode by default. +.IP "\fB\-m4a\fR" 4 +.IX Item "-m4a" +Generate code for the SH4a. +.IP "\fB\-m4al\fR" 4 +.IX Item "-m4al" +Same as \fB\-m4a\-nofpu\fR, except that it implicitly passes +\&\fB\-dsp\fR to the assembler. \s-1GCC\s0 doesn't generate any \s-1DSP\s0 +instructions at the moment. +.IP "\fB\-mb\fR" 4 +.IX Item "-mb" +Compile code for the processor in big endian mode. +.IP "\fB\-ml\fR" 4 +.IX Item "-ml" +Compile code for the processor in little endian mode. +.IP "\fB\-mdalign\fR" 4 +.IX Item "-mdalign" +Align doubles at 64\-bit boundaries. Note that this changes the calling +conventions, and thus some functions from the standard C library will +not work unless you recompile it first with \fB\-mdalign\fR. +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +Shorten some address references at link time, when possible; uses the +linker option \fB\-relax\fR. +.IP "\fB\-mbigtable\fR" 4 +.IX Item "-mbigtable" +Use 32\-bit offsets in \f(CW\*(C`switch\*(C'\fR tables. The default is to use +16\-bit offsets. +.IP "\fB\-mbitops\fR" 4 +.IX Item "-mbitops" +Enable the use of bit manipulation instructions on \s-1SH2A\s0. +.IP "\fB\-mfmovd\fR" 4 +.IX Item "-mfmovd" +Enable the use of the instruction \f(CW\*(C`fmovd\*(C'\fR. Check \fB\-mdalign\fR for +alignment constraints. +.IP "\fB\-mhitachi\fR" 4 +.IX Item "-mhitachi" +Comply with the calling conventions defined by Renesas. +.IP "\fB\-mrenesas\fR" 4 +.IX Item "-mrenesas" +Comply with the calling conventions defined by Renesas. +.IP "\fB\-mno\-renesas\fR" 4 +.IX Item "-mno-renesas" +Comply with the calling conventions defined for \s-1GCC\s0 before the Renesas +conventions were available. This option is the default for all +targets of the \s-1SH\s0 toolchain except for \fBsh-symbianelf\fR. +.IP "\fB\-mnomacsave\fR" 4 +.IX Item "-mnomacsave" +Mark the \f(CW\*(C`MAC\*(C'\fR register as call-clobbered, even if +\&\fB\-mhitachi\fR is given. +.IP "\fB\-mieee\fR" 4 +.IX Item "-mieee" +Increase IEEE-compliance of floating-point code. +At the moment, this is equivalent to \fB\-fno\-finite\-math\-only\fR. +When generating 16 bit \s-1SH\s0 opcodes, getting IEEE-conforming results for +comparisons of NANs / infinities incurs extra overhead in every +floating point comparison, therefore the default is set to +\&\fB\-ffinite\-math\-only\fR. +.IP "\fB\-minline\-ic_invalidate\fR" 4 +.IX Item "-minline-ic_invalidate" +Inline code to invalidate instruction cache entries after setting up +nested function trampolines. +This option has no effect if \-musermode is in effect and the selected +code generation option (e.g. \-m4) does not allow the use of the icbi +instruction. +If the selected code generation option does not allow the use of the icbi +instruction, and \-musermode is not in effect, the inlined code will +manipulate the instruction cache address array directly with an associative +write. This not only requires privileged mode, but it will also +fail if the cache line had been mapped via the \s-1TLB\s0 and has become unmapped. +.IP "\fB\-misize\fR" 4 +.IX Item "-misize" +Dump instruction size and location in the assembly code. +.IP "\fB\-mpadstruct\fR" 4 +.IX Item "-mpadstruct" +This option is deprecated. It pads structures to multiple of 4 bytes, +which is incompatible with the \s-1SH\s0 \s-1ABI\s0. +.IP "\fB\-mspace\fR" 4 +.IX Item "-mspace" +Optimize for space instead of speed. Implied by \fB\-Os\fR. +.IP "\fB\-mprefergot\fR" 4 +.IX Item "-mprefergot" +When generating position-independent code, emit function calls using +the Global Offset Table instead of the Procedure Linkage Table. +.IP "\fB\-musermode\fR" 4 +.IX Item "-musermode" +Don't generate privileged mode only code; implies \-mno\-inline\-ic_invalidate +if the inlined code would not work in user mode. +This is the default when the target is \f(CW\*(C`sh\-*\-linux*\*(C'\fR. +.IP "\fB\-multcost=\fR\fInumber\fR" 4 +.IX Item "-multcost=number" +Set the cost to assume for a multiply insn. +.IP "\fB\-mdiv=\fR\fIstrategy\fR" 4 +.IX Item "-mdiv=strategy" +Set the division strategy to use for SHmedia code. \fIstrategy\fR must be +one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, +inv:call2, inv:fp . +\&\*(L"fp\*(R" performs the operation in floating point. This has a very high latency, +but needs only a few instructions, so it might be a good choice if +your code has enough easily exploitable \s-1ILP\s0 to allow the compiler to +schedule the floating point instructions together with other instructions. +Division by zero causes a floating point exception. +\&\*(L"inv\*(R" uses integer operations to calculate the inverse of the divisor, +and then multiplies the dividend with the inverse. This strategy allows +cse and hoisting of the inverse calculation. Division by zero calculates +an unspecified result, but does not trap. +\&\*(L"inv:minlat\*(R" is a variant of \*(L"inv\*(R" where if no cse / hoisting opportunities +have been found, or if the entire operation has been hoisted to the same +place, the last stages of the inverse calculation are intertwined with the +final multiply to reduce the overall latency, at the expense of using a few +more instructions, and thus offering fewer scheduling opportunities with +other code. +\&\*(L"call\*(R" calls a library function that usually implements the inv:minlat +strategy. +This gives high code density for m5\-*media\-nofpu compilations. +\&\*(L"call2\*(R" uses a different entry point of the same library function, where it +assumes that a pointer to a lookup table has already been set up, which +exposes the pointer load to cse / code hoisting optimizations. +\&\*(L"inv:call\*(R", \*(L"inv:call2\*(R" and \*(L"inv:fp\*(R" all use the \*(L"inv\*(R" algorithm for initial +code generation, but if the code stays unoptimized, revert to the \*(L"call\*(R", +\&\*(L"call2\*(R", or \*(L"fp\*(R" strategies, respectively. Note that the +potentially-trapping side effect of division by zero is carried by a +separate instruction, so it is possible that all the integer instructions +are hoisted out, but the marker for the side effect stays where it is. +A recombination to fp operations or a call is not possible in that case. +\&\*(L"inv20u\*(R" and \*(L"inv20l\*(R" are variants of the \*(L"inv:minlat\*(R" strategy. In the case +that the inverse calculation was nor separated from the multiply, they speed +up division where the dividend fits into 20 bits (plus sign where applicable), +by inserting a test to skip a number of operations in this case; this test +slows down the case of larger dividends. inv20u assumes the case of a such +a small dividend to be unlikely, and inv20l assumes it to be likely. +.IP "\fB\-maccumulate\-outgoing\-args\fR" 4 +.IX Item "-maccumulate-outgoing-args" +Reserve space once for outgoing arguments in the function prologue rather +than around each call. Generally beneficial for performance and size. Also +needed for unwinding to avoid changing the stack frame around conditional code. +.IP "\fB\-mdivsi3_libfunc=\fR\fIname\fR" 4 +.IX Item "-mdivsi3_libfunc=name" +Set the name of the library function used for 32 bit signed division to +\&\fIname\fR. This only affect the name used in the call and inv:call +division strategies, and the compiler will still expect the same +sets of input/output/clobbered registers as if this option was not present. +.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 +.IX Item "-mfixed-range=register-range" +Generate code treating the given register range as fixed registers. +A fixed register is one that the register allocator can not use. This is +useful when compiling kernel code. A register range is specified as +two registers separated by a dash. Multiple register ranges can be +specified separated by a comma. +.IP "\fB\-madjust\-unroll\fR" 4 +.IX Item "-madjust-unroll" +Throttle unrolling to avoid thrashing target registers. +This option only has an effect if the gcc code base supports the +\&\s-1TARGET_ADJUST_UNROLL_MAX\s0 target hook. +.IP "\fB\-mindexed\-addressing\fR" 4 +.IX Item "-mindexed-addressing" +Enable the use of the indexed addressing mode for SHmedia32/SHcompact. +This is only safe if the hardware and/or \s-1OS\s0 implement 32 bit wrap-around +semantics for the indexed addressing mode. The architecture allows the +implementation of processors with 64 bit \s-1MMU\s0, which the \s-1OS\s0 could use to +get 32 bit addressing, but since no current hardware implementation supports +this or any other way to make the indexed addressing mode safe to use in +the 32 bit \s-1ABI\s0, the default is \-mno\-indexed\-addressing. +.IP "\fB\-mgettrcost=\fR\fInumber\fR" 4 +.IX Item "-mgettrcost=number" +Set the cost assumed for the gettr instruction to \fInumber\fR. +The default is 2 if \fB\-mpt\-fixed\fR is in effect, 100 otherwise. +.IP "\fB\-mpt\-fixed\fR" 4 +.IX Item "-mpt-fixed" +Assume pt* instructions won't trap. This will generally generate better +scheduled code, but is unsafe on current hardware. The current architecture +definition says that ptabs and ptrel trap when the target anded with 3 is 3. +This has the unintentional effect of making it unsafe to schedule ptabs / +ptrel before a branch, or hoist it out of a loop. For example, +_\|_do_global_ctors, a part of libgcc that runs constructors at program +startup, calls functions in a list which is delimited by \-1. With the +\&\-mpt\-fixed option, the ptabs will be done before testing against \-1. +That means that all the constructors will be run a bit quicker, but when +the loop comes to the end of the list, the program crashes because ptabs +loads \-1 into a target register. Since this option is unsafe for any +hardware implementing the current architecture specification, the default +is \-mno\-pt\-fixed. Unless the user specifies a specific cost with +\&\fB\-mgettrcost\fR, \-mno\-pt\-fixed also implies \fB\-mgettrcost=100\fR; +this deters register allocation using target registers for storing +ordinary integers. +.IP "\fB\-minvalid\-symbols\fR" 4 +.IX Item "-minvalid-symbols" +Assume symbols might be invalid. Ordinary function symbols generated by +the compiler will always be valid to load with movi/shori/ptabs or +movi/shori/ptrel, but with assembler and/or linker tricks it is possible +to generate symbols that will cause ptabs / ptrel to trap. +This option is only meaningful when \fB\-mno\-pt\-fixed\fR is in effect. +It will then prevent cross-basic-block cse, hoisting and most scheduling +of symbol loads. The default is \fB\-mno\-invalid\-symbols\fR. +.PP +\fISolaris 2 Options\fR +.IX Subsection "Solaris 2 Options" +.PP +These \fB\-m\fR options are supported on Solaris 2: +.IP "\fB\-mimpure\-text\fR" 4 +.IX Item "-mimpure-text" +\&\fB\-mimpure\-text\fR, used in addition to \fB\-shared\fR, tells +the compiler to not pass \fB\-z text\fR to the linker when linking a +shared object. Using this option, you can link position-dependent +code into a shared object. +.Sp +\&\fB\-mimpure\-text\fR suppresses the \*(L"relocations remain against +allocatable but non-writable sections\*(R" linker error message. +However, the necessary relocations will trigger copy-on-write, and the +shared object is not actually shared across processes. Instead of +using \fB\-mimpure\-text\fR, you should compile all source code with +\&\fB\-fpic\fR or \fB\-fPIC\fR. +.PP +These switches are supported in addition to the above on Solaris 2: +.IP "\fB\-threads\fR" 4 +.IX Item "-threads" +Add support for multithreading using the Solaris threads library. This +option sets flags for both the preprocessor and linker. This option does +not affect the thread safety of object code produced by the compiler or +that of libraries supplied with it. +.IP "\fB\-pthreads\fR" 4 +.IX Item "-pthreads" +Add support for multithreading using the \s-1POSIX\s0 threads library. This +option sets flags for both the preprocessor and linker. This option does +not affect the thread safety of object code produced by the compiler or +that of libraries supplied with it. +.IP "\fB\-pthread\fR" 4 +.IX Item "-pthread" +This is a synonym for \fB\-pthreads\fR. +.PP +\fI\s-1SPARC\s0 Options\fR +.IX Subsection "SPARC Options" +.PP +These \fB\-m\fR options are supported on the \s-1SPARC:\s0 +.IP "\fB\-mno\-app\-regs\fR" 4 +.IX Item "-mno-app-regs" +.PD 0 +.IP "\fB\-mapp\-regs\fR" 4 +.IX Item "-mapp-regs" +.PD +Specify \fB\-mapp\-regs\fR to generate output using the global registers +2 through 4, which the \s-1SPARC\s0 \s-1SVR4\s0 \s-1ABI\s0 reserves for applications. This +is the default. +.Sp +To be fully \s-1SVR4\s0 \s-1ABI\s0 compliant at the cost of some performance loss, +specify \fB\-mno\-app\-regs\fR. You should compile libraries and system +software with this option. +.IP "\fB\-mfpu\fR" 4 +.IX Item "-mfpu" +.PD 0 +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD +Generate output containing floating point instructions. This is the +default. +.IP "\fB\-mno\-fpu\fR" 4 +.IX Item "-mno-fpu" +.PD 0 +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD +Generate output containing library calls for floating point. +\&\fBWarning:\fR the requisite libraries are not available for all \s-1SPARC\s0 +targets. Normally the facilities of the machine's usual C compiler are +used, but this cannot be done directly in cross-compilation. You must make +your own arrangements to provide suitable library functions for +cross-compilation. The embedded targets \fBsparc\-*\-aout\fR and +\&\fBsparclite\-*\-*\fR do provide software floating point support. +.Sp +\&\fB\-msoft\-float\fR changes the calling convention in the output file; +therefore, it is only useful if you compile \fIall\fR of a program with +this option. In particular, you need to compile \fIlibgcc.a\fR, the +library that comes with \s-1GCC\s0, with \fB\-msoft\-float\fR in order for +this to work. +.IP "\fB\-mhard\-quad\-float\fR" 4 +.IX Item "-mhard-quad-float" +Generate output containing quad-word (long double) floating point +instructions. +.IP "\fB\-msoft\-quad\-float\fR" 4 +.IX Item "-msoft-quad-float" +Generate output containing library calls for quad-word (long double) +floating point instructions. The functions called are those specified +in the \s-1SPARC\s0 \s-1ABI\s0. This is the default. +.Sp +As of this writing, there are no \s-1SPARC\s0 implementations that have hardware +support for the quad-word floating point instructions. They all invoke +a trap handler for one of these instructions, and then the trap handler +emulates the effect of the instruction. Because of the trap handler overhead, +this is much slower than calling the \s-1ABI\s0 library routines. Thus the +\&\fB\-msoft\-quad\-float\fR option is the default. +.IP "\fB\-mno\-unaligned\-doubles\fR" 4 +.IX Item "-mno-unaligned-doubles" +.PD 0 +.IP "\fB\-munaligned\-doubles\fR" 4 +.IX Item "-munaligned-doubles" +.PD +Assume that doubles have 8 byte alignment. This is the default. +.Sp +With \fB\-munaligned\-doubles\fR, \s-1GCC\s0 assumes that doubles have 8 byte +alignment only if they are contained in another type, or if they have an +absolute address. Otherwise, it assumes they have 4 byte alignment. +Specifying this option avoids some rare compatibility problems with code +generated by other compilers. It is not the default because it results +in a performance loss, especially for floating point code. +.IP "\fB\-mno\-faster\-structs\fR" 4 +.IX Item "-mno-faster-structs" +.PD 0 +.IP "\fB\-mfaster\-structs\fR" 4 +.IX Item "-mfaster-structs" +.PD +With \fB\-mfaster\-structs\fR, the compiler assumes that structures +should have 8 byte alignment. This enables the use of pairs of +\&\f(CW\*(C`ldd\*(C'\fR and \f(CW\*(C`std\*(C'\fR instructions for copies in structure +assignment, in place of twice as many \f(CW\*(C`ld\*(C'\fR and \f(CW\*(C`st\*(C'\fR pairs. +However, the use of this changed alignment directly violates the \s-1SPARC\s0 +\&\s-1ABI\s0. Thus, it's intended only for use on targets where the developer +acknowledges that their resulting code will not be directly in line with +the rules of the \s-1ABI\s0. +.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 +.IX Item "-mcpu=cpu_type" +Set the instruction set, register set, and instruction scheduling parameters +for machine type \fIcpu_type\fR. Supported values for \fIcpu_type\fR are +\&\fBv7\fR, \fBcypress\fR, \fBv8\fR, \fBsupersparc\fR, \fBhypersparc\fR, +\&\fBleon\fR, \fBsparclite\fR, \fBf930\fR, \fBf934\fR, \fBsparclite86x\fR, +\&\fBsparclet\fR, \fBtsc701\fR, \fBv9\fR, \fBultrasparc\fR, +\&\fBultrasparc3\fR, \fBniagara\fR and \fBniagara2\fR. +.Sp +Default instruction scheduling parameters are used for values that select +an architecture and not an implementation. These are \fBv7\fR, \fBv8\fR, +\&\fBsparclite\fR, \fBsparclet\fR, \fBv9\fR. +.Sp +Here is a list of each supported architecture and their supported +implementations. +.Sp +.Vb 5 +\& v7: cypress +\& v8: supersparc, hypersparc, leon +\& sparclite: f930, f934, sparclite86x +\& sparclet: tsc701 +\& v9: ultrasparc, ultrasparc3, niagara, niagara2 +.Ve +.Sp +By default (unless configured otherwise), \s-1GCC\s0 generates code for the V7 +variant of the \s-1SPARC\s0 architecture. With \fB\-mcpu=cypress\fR, the compiler +additionally optimizes it for the Cypress \s-1CY7C602\s0 chip, as used in the +SPARCStation/SPARCServer 3xx series. This is also appropriate for the older +SPARCStation 1, 2, \s-1IPX\s0 etc. +.Sp +With \fB\-mcpu=v8\fR, \s-1GCC\s0 generates code for the V8 variant of the \s-1SPARC\s0 +architecture. The only difference from V7 code is that the compiler emits +the integer multiply and integer divide instructions which exist in \s-1SPARC\-V8\s0 +but not in \s-1SPARC\-V7\s0. With \fB\-mcpu=supersparc\fR, the compiler additionally +optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and +2000 series. +.Sp +With \fB\-mcpu=sparclite\fR, \s-1GCC\s0 generates code for the SPARClite variant of +the \s-1SPARC\s0 architecture. This adds the integer multiply, integer divide step +and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClite but not in \s-1SPARC\-V7\s0. +With \fB\-mcpu=f930\fR, the compiler additionally optimizes it for the +Fujitsu \s-1MB86930\s0 chip, which is the original SPARClite, with no \s-1FPU\s0. With +\&\fB\-mcpu=f934\fR, the compiler additionally optimizes it for the Fujitsu +\&\s-1MB86934\s0 chip, which is the more recent SPARClite with \s-1FPU\s0. +.Sp +With \fB\-mcpu=sparclet\fR, \s-1GCC\s0 generates code for the SPARClet variant of +the \s-1SPARC\s0 architecture. This adds the integer multiply, multiply/accumulate, +integer divide step and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClet +but not in \s-1SPARC\-V7\s0. With \fB\-mcpu=tsc701\fR, the compiler additionally +optimizes it for the \s-1TEMIC\s0 SPARClet chip. +.Sp +With \fB\-mcpu=v9\fR, \s-1GCC\s0 generates code for the V9 variant of the \s-1SPARC\s0 +architecture. This adds 64\-bit integer and floating-point move instructions, +3 additional floating-point condition code registers and conditional move +instructions. With \fB\-mcpu=ultrasparc\fR, the compiler additionally +optimizes it for the Sun UltraSPARC I/II/IIi chips. With +\&\fB\-mcpu=ultrasparc3\fR, the compiler additionally optimizes it for the +Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips. With +\&\fB\-mcpu=niagara\fR, the compiler additionally optimizes it for +Sun UltraSPARC T1 chips. With \fB\-mcpu=niagara2\fR, the compiler +additionally optimizes it for Sun UltraSPARC T2 chips. +.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4 +.IX Item "-mtune=cpu_type" +Set the instruction scheduling parameters for machine type +\&\fIcpu_type\fR, but do not set the instruction set or register set that the +option \fB\-mcpu=\fR\fIcpu_type\fR would. +.Sp +The same values for \fB\-mcpu=\fR\fIcpu_type\fR can be used for +\&\fB\-mtune=\fR\fIcpu_type\fR, but the only useful values are those +that select a particular \s-1CPU\s0 implementation. Those are \fBcypress\fR, +\&\fBsupersparc\fR, \fBhypersparc\fR, \fBleon\fR, \fBf930\fR, \fBf934\fR, +\&\fBsparclite86x\fR, \fBtsc701\fR, \fBultrasparc\fR, \fBultrasparc3\fR, +\&\fBniagara\fR, and \fBniagara2\fR. +.IP "\fB\-mv8plus\fR" 4 +.IX Item "-mv8plus" +.PD 0 +.IP "\fB\-mno\-v8plus\fR" 4 +.IX Item "-mno-v8plus" +.PD +With \fB\-mv8plus\fR, \s-1GCC\s0 generates code for the \s-1SPARC\-V8+\s0 \s-1ABI\s0. The +difference from the V8 \s-1ABI\s0 is that the global and out registers are +considered 64\-bit wide. This is enabled by default on Solaris in 32\-bit +mode for all \s-1SPARC\-V9\s0 processors. +.IP "\fB\-mvis\fR" 4 +.IX Item "-mvis" +.PD 0 +.IP "\fB\-mno\-vis\fR" 4 +.IX Item "-mno-vis" +.PD +With \fB\-mvis\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC +Visual Instruction Set extensions. The default is \fB\-mno\-vis\fR. +.IP "\fB\-mfix\-at697f\fR" 4 +.IX Item "-mfix-at697f" +Enable the documented workaround for the single erratum of the Atmel \s-1AT697F\s0 +processor (which corresponds to erratum #13 of the \s-1AT697E\s0 processor). +.PP +These \fB\-m\fR options are supported in addition to the above +on \s-1SPARC\-V9\s0 processors in 64\-bit environments: +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +Generate code for a processor running in little-endian mode. It is only +available for a few configurations and most notably not on Solaris and Linux. +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" +.PD 0 +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.PD +Generate code for a 32\-bit or 64\-bit environment. +The 32\-bit environment sets int, long and pointer to 32 bits. +The 64\-bit environment sets int to 32 bits and long and pointer +to 64 bits. +.IP "\fB\-mcmodel=medlow\fR" 4 +.IX Item "-mcmodel=medlow" +Generate code for the Medium/Low code model: 64\-bit addresses, programs +must be linked in the low 32 bits of memory. Programs can be statically +or dynamically linked. +.IP "\fB\-mcmodel=medmid\fR" 4 +.IX Item "-mcmodel=medmid" +Generate code for the Medium/Middle code model: 64\-bit addresses, programs +must be linked in the low 44 bits of memory, the text and data segments must +be less than 2GB in size and the data segment must be located within 2GB of +the text segment. +.IP "\fB\-mcmodel=medany\fR" 4 +.IX Item "-mcmodel=medany" +Generate code for the Medium/Anywhere code model: 64\-bit addresses, programs +may be linked anywhere in memory, the text and data segments must be less +than 2GB in size and the data segment must be located within 2GB of the +text segment. +.IP "\fB\-mcmodel=embmedany\fR" 4 +.IX Item "-mcmodel=embmedany" +Generate code for the Medium/Anywhere code model for embedded systems: +64\-bit addresses, the text and data segments must be less than 2GB in +size, both starting anywhere in memory (determined at link time). The +global register \f(CW%g4\fR points to the base of the data segment. Programs +are statically linked and \s-1PIC\s0 is not supported. +.IP "\fB\-mstack\-bias\fR" 4 +.IX Item "-mstack-bias" +.PD 0 +.IP "\fB\-mno\-stack\-bias\fR" 4 +.IX Item "-mno-stack-bias" +.PD +With \fB\-mstack\-bias\fR, \s-1GCC\s0 assumes that the stack pointer, and +frame pointer if present, are offset by \-2047 which must be added back +when making stack frame references. This is the default in 64\-bit mode. +Otherwise, assume no such offset is present. +.PP +\fI\s-1SPU\s0 Options\fR +.IX Subsection "SPU Options" +.PP +These \fB\-m\fR options are supported on the \s-1SPU:\s0 +.IP "\fB\-mwarn\-reloc\fR" 4 +.IX Item "-mwarn-reloc" +.PD 0 +.IP "\fB\-merror\-reloc\fR" 4 +.IX Item "-merror-reloc" +.PD +The loader for \s-1SPU\s0 does not handle dynamic relocations. By default, \s-1GCC\s0 +will give an error when it generates code that requires a dynamic +relocation. \fB\-mno\-error\-reloc\fR disables the error, +\&\fB\-mwarn\-reloc\fR will generate a warning instead. +.IP "\fB\-msafe\-dma\fR" 4 +.IX Item "-msafe-dma" +.PD 0 +.IP "\fB\-munsafe\-dma\fR" 4 +.IX Item "-munsafe-dma" +.PD +Instructions which initiate or test completion of \s-1DMA\s0 must not be +reordered with respect to loads and stores of the memory which is being +accessed. Users typically address this problem using the volatile +keyword, but that can lead to inefficient code in places where the +memory is known to not change. Rather than mark the memory as volatile +we treat the \s-1DMA\s0 instructions as potentially effecting all memory. With +\&\fB\-munsafe\-dma\fR users must use the volatile keyword to protect +memory accesses. +.IP "\fB\-mbranch\-hints\fR" 4 +.IX Item "-mbranch-hints" +By default, \s-1GCC\s0 will generate a branch hint instruction to avoid +pipeline stalls for always taken or probably taken branches. A hint +will not be generated closer than 8 instructions away from its branch. +There is little reason to disable them, except for debugging purposes, +or to make an object a little bit smaller. +.IP "\fB\-msmall\-mem\fR" 4 +.IX Item "-msmall-mem" +.PD 0 +.IP "\fB\-mlarge\-mem\fR" 4 +.IX Item "-mlarge-mem" +.PD +By default, \s-1GCC\s0 generates code assuming that addresses are never larger +than 18 bits. With \fB\-mlarge\-mem\fR code is generated that assumes +a full 32 bit address. +.IP "\fB\-mstdmain\fR" 4 +.IX Item "-mstdmain" +By default, \s-1GCC\s0 links against startup code that assumes the SPU-style +main function interface (which has an unconventional parameter list). +With \fB\-mstdmain\fR, \s-1GCC\s0 will link your program against startup +code that assumes a C99\-style interface to \f(CW\*(C`main\*(C'\fR, including a +local copy of \f(CW\*(C`argv\*(C'\fR strings. +.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 +.IX Item "-mfixed-range=register-range" +Generate code treating the given register range as fixed registers. +A fixed register is one that the register allocator can not use. This is +useful when compiling kernel code. A register range is specified as +two registers separated by a dash. Multiple register ranges can be +specified separated by a comma. +.IP "\fB\-mea32\fR" 4 +.IX Item "-mea32" +.PD 0 +.IP "\fB\-mea64\fR" 4 +.IX Item "-mea64" +.PD +Compile code assuming that pointers to the \s-1PPU\s0 address space accessed +via the \f(CW\*(C`_\|_ea\*(C'\fR named address space qualifier are either 32 or 64 +bits wide. The default is 32 bits. As this is an \s-1ABI\s0 changing option, +all object code in an executable must be compiled with the same setting. +.IP "\fB\-maddress\-space\-conversion\fR" 4 +.IX Item "-maddress-space-conversion" +.PD 0 +.IP "\fB\-mno\-address\-space\-conversion\fR" 4 +.IX Item "-mno-address-space-conversion" +.PD +Allow/disallow treating the \f(CW\*(C`_\|_ea\*(C'\fR address space as superset +of the generic address space. This enables explicit type casts +between \f(CW\*(C`_\|_ea\*(C'\fR and generic pointer as well as implicit +conversions of generic pointers to \f(CW\*(C`_\|_ea\*(C'\fR pointers. The +default is to allow address space pointer conversions. +.IP "\fB\-mcache\-size=\fR\fIcache-size\fR" 4 +.IX Item "-mcache-size=cache-size" +This option controls the version of libgcc that the compiler links to an +executable and selects a software-managed cache for accessing variables +in the \f(CW\*(C`_\|_ea\*(C'\fR address space with a particular cache size. Possible +options for \fIcache-size\fR are \fB8\fR, \fB16\fR, \fB32\fR, \fB64\fR +and \fB128\fR. The default cache size is 64KB. +.IP "\fB\-matomic\-updates\fR" 4 +.IX Item "-matomic-updates" +.PD 0 +.IP "\fB\-mno\-atomic\-updates\fR" 4 +.IX Item "-mno-atomic-updates" +.PD +This option controls the version of libgcc that the compiler links to an +executable and selects whether atomic updates to the software-managed +cache of PPU-side variables are used. If you use atomic updates, changes +to a \s-1PPU\s0 variable from \s-1SPU\s0 code using the \f(CW\*(C`_\|_ea\*(C'\fR named address space +qualifier will not interfere with changes to other \s-1PPU\s0 variables residing +in the same cache line from \s-1PPU\s0 code. If you do not use atomic updates, +such interference may occur; however, writing back cache lines will be +more efficient. The default behavior is to use atomic updates. +.IP "\fB\-mdual\-nops\fR" 4 +.IX Item "-mdual-nops" +.PD 0 +.IP "\fB\-mdual\-nops=\fR\fIn\fR" 4 +.IX Item "-mdual-nops=n" +.PD +By default, \s-1GCC\s0 will insert nops to increase dual issue when it expects +it to increase performance. \fIn\fR can be a value from 0 to 10. A +smaller \fIn\fR will insert fewer nops. 10 is the default, 0 is the +same as \fB\-mno\-dual\-nops\fR. Disabled with \fB\-Os\fR. +.IP "\fB\-mhint\-max\-nops=\fR\fIn\fR" 4 +.IX Item "-mhint-max-nops=n" +Maximum number of nops to insert for a branch hint. A branch hint must +be at least 8 instructions away from the branch it is effecting. \s-1GCC\s0 +will insert up to \fIn\fR nops to enforce this, otherwise it will not +generate the branch hint. +.IP "\fB\-mhint\-max\-distance=\fR\fIn\fR" 4 +.IX Item "-mhint-max-distance=n" +The encoding of the branch hint instruction limits the hint to be within +256 instructions of the branch it is effecting. By default, \s-1GCC\s0 makes +sure it is within 125. +.IP "\fB\-msafe\-hints\fR" 4 +.IX Item "-msafe-hints" +Work around a hardware bug which causes the \s-1SPU\s0 to stall indefinitely. +By default, \s-1GCC\s0 will insert the \f(CW\*(C`hbrp\*(C'\fR instruction to make sure +this stall won't happen. +.PP +\fIOptions for System V\fR +.IX Subsection "Options for System V" +.PP +These additional options are available on System V Release 4 for +compatibility with other compilers on those systems: +.IP "\fB\-G\fR" 4 +.IX Item "-G" +Create a shared object. +It is recommended that \fB\-symbolic\fR or \fB\-shared\fR be used instead. +.IP "\fB\-Qy\fR" 4 +.IX Item "-Qy" +Identify the versions of each tool used by the compiler, in a +\&\f(CW\*(C`.ident\*(C'\fR assembler directive in the output. +.IP "\fB\-Qn\fR" 4 +.IX Item "-Qn" +Refrain from adding \f(CW\*(C`.ident\*(C'\fR directives to the output file (this is +the default). +.IP "\fB\-YP,\fR\fIdirs\fR" 4 +.IX Item "-YP,dirs" +Search the directories \fIdirs\fR, and no others, for libraries +specified with \fB\-l\fR. +.IP "\fB\-Ym,\fR\fIdir\fR" 4 +.IX Item "-Ym,dir" +Look in the directory \fIdir\fR to find the M4 preprocessor. +The assembler uses this option. +.PP +\fIV850 Options\fR +.IX Subsection "V850 Options" +.PP +These \fB\-m\fR options are defined for V850 implementations: +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +.PD 0 +.IP "\fB\-mno\-long\-calls\fR" 4 +.IX Item "-mno-long-calls" +.PD +Treat all calls as being far away (near). If calls are assumed to be +far away, the compiler will always load the functions address up into a +register, and call indirect through the pointer. +.IP "\fB\-mno\-ep\fR" 4 +.IX Item "-mno-ep" +.PD 0 +.IP "\fB\-mep\fR" 4 +.IX Item "-mep" +.PD +Do not optimize (do optimize) basic blocks that use the same index +pointer 4 or more times to copy pointer into the \f(CW\*(C`ep\*(C'\fR register, and +use the shorter \f(CW\*(C`sld\*(C'\fR and \f(CW\*(C`sst\*(C'\fR instructions. The \fB\-mep\fR +option is on by default if you optimize. +.IP "\fB\-mno\-prolog\-function\fR" 4 +.IX Item "-mno-prolog-function" +.PD 0 +.IP "\fB\-mprolog\-function\fR" 4 +.IX Item "-mprolog-function" +.PD +Do not use (do use) external functions to save and restore registers +at the prologue and epilogue of a function. The external functions +are slower, but use less code space if more than one function saves +the same number of registers. The \fB\-mprolog\-function\fR option +is on by default if you optimize. +.IP "\fB\-mspace\fR" 4 +.IX Item "-mspace" +Try to make the code as small as possible. At present, this just turns +on the \fB\-mep\fR and \fB\-mprolog\-function\fR options. +.IP "\fB\-mtda=\fR\fIn\fR" 4 +.IX Item "-mtda=n" +Put static or global variables whose size is \fIn\fR bytes or less into +the tiny data area that register \f(CW\*(C`ep\*(C'\fR points to. The tiny data +area can hold up to 256 bytes in total (128 bytes for byte references). +.IP "\fB\-msda=\fR\fIn\fR" 4 +.IX Item "-msda=n" +Put static or global variables whose size is \fIn\fR bytes or less into +the small data area that register \f(CW\*(C`gp\*(C'\fR points to. The small data +area can hold up to 64 kilobytes. +.IP "\fB\-mzda=\fR\fIn\fR" 4 +.IX Item "-mzda=n" +Put static or global variables whose size is \fIn\fR bytes or less into +the first 32 kilobytes of memory. +.IP "\fB\-mv850\fR" 4 +.IX Item "-mv850" +Specify that the target processor is the V850. +.IP "\fB\-mbig\-switch\fR" 4 +.IX Item "-mbig-switch" +Generate code suitable for big switch tables. Use this option only if +the assembler/linker complain about out of range branches within a switch +table. +.IP "\fB\-mapp\-regs\fR" 4 +.IX Item "-mapp-regs" +This option will cause r2 and r5 to be used in the code generated by +the compiler. This setting is the default. +.IP "\fB\-mno\-app\-regs\fR" 4 +.IX Item "-mno-app-regs" +This option will cause r2 and r5 to be treated as fixed registers. +.IP "\fB\-mv850e2v3\fR" 4 +.IX Item "-mv850e2v3" +Specify that the target processor is the V850E2V3. The preprocessor +constants \fB_\|_v850e2v3_\|_\fR will be defined if +this option is used. +.IP "\fB\-mv850e2\fR" 4 +.IX Item "-mv850e2" +Specify that the target processor is the V850E2. The preprocessor +constants \fB_\|_v850e2_\|_\fR will be defined if +.IP "\fB\-mv850e1\fR" 4 +.IX Item "-mv850e1" +Specify that the target processor is the V850E1. The preprocessor +constants \fB_\|_v850e1_\|_\fR and \fB_\|_v850e_\|_\fR will be defined if +.IP "\fB\-mv850es\fR" 4 +.IX Item "-mv850es" +Specify that the target processor is the V850ES. This is an alias for +the \fB\-mv850e1\fR option. +.IP "\fB\-mv850e\fR" 4 +.IX Item "-mv850e" +Specify that the target processor is the V850E. The preprocessor +constant \fB_\|_v850e_\|_\fR will be defined if this option is used. +.Sp +If neither \fB\-mv850\fR nor \fB\-mv850e\fR nor \fB\-mv850e1\fR +nor \fB\-mv850e2\fR nor \fB\-mv850e2v3\fR +are defined then a default target processor will be chosen and the +relevant \fB_\|_v850*_\|_\fR preprocessor constant will be defined. +.Sp +The preprocessor constants \fB_\|_v850\fR and \fB_\|_v851_\|_\fR are always +defined, regardless of which processor variant is the target. +.IP "\fB\-mdisable\-callt\fR" 4 +.IX Item "-mdisable-callt" +This option will suppress generation of the \s-1CALLT\s0 instruction for the +v850e, v850e1, v850e2 and v850e2v3 flavors of the v850 architecture. The default is +\&\fB\-mno\-disable\-callt\fR which allows the \s-1CALLT\s0 instruction to be used. +.PP +\fI\s-1VAX\s0 Options\fR +.IX Subsection "VAX Options" +.PP +These \fB\-m\fR options are defined for the \s-1VAX:\s0 +.IP "\fB\-munix\fR" 4 +.IX Item "-munix" +Do not output certain jump instructions (\f(CW\*(C`aobleq\*(C'\fR and so on) +that the Unix assembler for the \s-1VAX\s0 cannot handle across long +ranges. +.IP "\fB\-mgnu\fR" 4 +.IX Item "-mgnu" +Do output those jump instructions, on the assumption that you +will assemble with the \s-1GNU\s0 assembler. +.IP "\fB\-mg\fR" 4 +.IX Item "-mg" +Output code for g\-format floating point numbers instead of d\-format. +.PP +\fIVxWorks Options\fR +.IX Subsection "VxWorks Options" +.PP +The options in this section are defined for all VxWorks targets. +Options specific to the target hardware are listed with the other +options for that target. +.IP "\fB\-mrtp\fR" 4 +.IX Item "-mrtp" +\&\s-1GCC\s0 can generate code for both VxWorks kernels and real time processes +(RTPs). This option switches from the former to the latter. It also +defines the preprocessor macro \f(CW\*(C`_\|_RTP_\|_\*(C'\fR. +.IP "\fB\-non\-static\fR" 4 +.IX Item "-non-static" +Link an \s-1RTP\s0 executable against shared libraries rather than static +libraries. The options \fB\-static\fR and \fB\-shared\fR can +also be used for RTPs; \fB\-static\fR +is the default. +.IP "\fB\-Bstatic\fR" 4 +.IX Item "-Bstatic" +.PD 0 +.IP "\fB\-Bdynamic\fR" 4 +.IX Item "-Bdynamic" +.PD +These options are passed down to the linker. They are defined for +compatibility with Diab. +.IP "\fB\-Xbind\-lazy\fR" 4 +.IX Item "-Xbind-lazy" +Enable lazy binding of function calls. This option is equivalent to +\&\fB\-Wl,\-z,now\fR and is defined for compatibility with Diab. +.IP "\fB\-Xbind\-now\fR" 4 +.IX Item "-Xbind-now" +Disable lazy binding of function calls. This option is the default and +is defined for compatibility with Diab. +.PP +\fIx86\-64 Options\fR +.IX Subsection "x86-64 Options" +.PP +These are listed under +.PP +\fIXstormy16 Options\fR +.IX Subsection "Xstormy16 Options" +.PP +These options are defined for Xstormy16: +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Choose startup files and linker script suitable for the simulator. +.PP +\fIXtensa Options\fR +.IX Subsection "Xtensa Options" +.PP +These options are supported for Xtensa targets: +.IP "\fB\-mconst16\fR" 4 +.IX Item "-mconst16" +.PD 0 +.IP "\fB\-mno\-const16\fR" 4 +.IX Item "-mno-const16" +.PD +Enable or disable use of \f(CW\*(C`CONST16\*(C'\fR instructions for loading +constant values. The \f(CW\*(C`CONST16\*(C'\fR instruction is currently not a +standard option from Tensilica. When enabled, \f(CW\*(C`CONST16\*(C'\fR +instructions are always used in place of the standard \f(CW\*(C`L32R\*(C'\fR +instructions. The use of \f(CW\*(C`CONST16\*(C'\fR is enabled by default only if +the \f(CW\*(C`L32R\*(C'\fR instruction is not available. +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Enable or disable use of fused multiply/add and multiply/subtract +instructions in the floating-point option. This has no effect if the +floating-point option is not also enabled. Disabling fused multiply/add +and multiply/subtract instructions forces the compiler to use separate +instructions for the multiply and add/subtract operations. This may be +desirable in some cases where strict \s-1IEEE\s0 754\-compliant results are +required: the fused multiply add/subtract instructions do not round the +intermediate result, thereby producing results with \fImore\fR bits of +precision than specified by the \s-1IEEE\s0 standard. Disabling fused multiply +add/subtract instructions also ensures that the program output is not +sensitive to the compiler's ability to combine multiply and add/subtract +operations. +.IP "\fB\-mserialize\-volatile\fR" 4 +.IX Item "-mserialize-volatile" +.PD 0 +.IP "\fB\-mno\-serialize\-volatile\fR" 4 +.IX Item "-mno-serialize-volatile" +.PD +When this option is enabled, \s-1GCC\s0 inserts \f(CW\*(C`MEMW\*(C'\fR instructions before +\&\f(CW\*(C`volatile\*(C'\fR memory references to guarantee sequential consistency. +The default is \fB\-mserialize\-volatile\fR. Use +\&\fB\-mno\-serialize\-volatile\fR to omit the \f(CW\*(C`MEMW\*(C'\fR instructions. +.IP "\fB\-mforce\-no\-pic\fR" 4 +.IX Item "-mforce-no-pic" +For targets, like GNU/Linux, where all user-mode Xtensa code must be +position-independent code (\s-1PIC\s0), this option disables \s-1PIC\s0 for compiling +kernel code. +.IP "\fB\-mtext\-section\-literals\fR" 4 +.IX Item "-mtext-section-literals" +.PD 0 +.IP "\fB\-mno\-text\-section\-literals\fR" 4 +.IX Item "-mno-text-section-literals" +.PD +Control the treatment of literal pools. The default is +\&\fB\-mno\-text\-section\-literals\fR, which places literals in a separate +section in the output file. This allows the literal pool to be placed +in a data \s-1RAM/ROM\s0, and it also allows the linker to combine literal +pools from separate object files to remove redundant literals and +improve code size. With \fB\-mtext\-section\-literals\fR, the literals +are interspersed in the text section in order to keep them as close as +possible to their references. This may be necessary for large assembly +files. +.IP "\fB\-mtarget\-align\fR" 4 +.IX Item "-mtarget-align" +.PD 0 +.IP "\fB\-mno\-target\-align\fR" 4 +.IX Item "-mno-target-align" +.PD +When this option is enabled, \s-1GCC\s0 instructs the assembler to +automatically align instructions to reduce branch penalties at the +expense of some code density. The assembler attempts to widen density +instructions to align branch targets and the instructions following call +instructions. If there are not enough preceding safe density +instructions to align a target, no widening will be performed. The +default is \fB\-mtarget\-align\fR. These options do not affect the +treatment of auto-aligned instructions like \f(CW\*(C`LOOP\*(C'\fR, which the +assembler will always align, either by widening density instructions or +by inserting no-op instructions. +.IP "\fB\-mlongcalls\fR" 4 +.IX Item "-mlongcalls" +.PD 0 +.IP "\fB\-mno\-longcalls\fR" 4 +.IX Item "-mno-longcalls" +.PD +When this option is enabled, \s-1GCC\s0 instructs the assembler to translate +direct calls to indirect calls unless it can determine that the target +of a direct call is in the range allowed by the call instruction. This +translation typically occurs for calls to functions in other source +files. Specifically, the assembler translates a direct \f(CW\*(C`CALL\*(C'\fR +instruction into an \f(CW\*(C`L32R\*(C'\fR followed by a \f(CW\*(C`CALLX\*(C'\fR instruction. +The default is \fB\-mno\-longcalls\fR. This option should be used in +programs where the call target can potentially be out of range. This +option is implemented in the assembler, not the compiler, so the +assembly code generated by \s-1GCC\s0 will still show direct call +instructions\-\-\-look at the disassembled object code to see the actual +instructions. Note that the assembler will use an indirect call for +every cross-file call, not just those that really will be out of range. +.PP +\fIzSeries Options\fR +.IX Subsection "zSeries Options" +.PP +These are listed under +.SS "Options for Code Generation Conventions" +.IX Subsection "Options for Code Generation Conventions" +These machine-independent options control the interface conventions +used in code generation. +.PP +Most of them have both positive and negative forms; the negative form +of \fB\-ffoo\fR would be \fB\-fno\-foo\fR. In the table below, only +one of the forms is listed\-\-\-the one which is not the default. You +can figure out the other form by either removing \fBno\-\fR or adding +it. +.IP "\fB\-fbounds\-check\fR" 4 +.IX Item "-fbounds-check" +For front-ends that support it, generate additional code to check that +indices used to access arrays are within the declared range. This is +currently only supported by the Java and Fortran front-ends, where +this option defaults to true and false respectively. +.IP "\fB\-ftrapv\fR" 4 +.IX Item "-ftrapv" +This option generates traps for signed overflow on addition, subtraction, +multiplication operations. +.IP "\fB\-fwrapv\fR" 4 +.IX Item "-fwrapv" +This option instructs the compiler to assume that signed arithmetic +overflow of addition, subtraction and multiplication wraps around +using twos-complement representation. This flag enables some optimizations +and disables others. This option is enabled by default for the Java +front-end, as required by the Java language specification. +.IP "\fB\-fexceptions\fR" 4 +.IX Item "-fexceptions" +Enable exception handling. Generates extra code needed to propagate +exceptions. For some targets, this implies \s-1GCC\s0 will generate frame +unwind information for all functions, which can produce significant data +size overhead, although it does not affect execution. If you do not +specify this option, \s-1GCC\s0 will enable it by default for languages like +\&\*(C+ which normally require exception handling, and disable it for +languages like C that do not normally require it. However, you may need +to enable this option when compiling C code that needs to interoperate +properly with exception handlers written in \*(C+. You may also wish to +disable this option if you are compiling older \*(C+ programs that don't +use exception handling. +.IP "\fB\-fnon\-call\-exceptions\fR" 4 +.IX Item "-fnon-call-exceptions" +Generate code that allows trapping instructions to throw exceptions. +Note that this requires platform-specific runtime support that does +not exist everywhere. Moreover, it only allows \fItrapping\fR +instructions to throw exceptions, i.e. memory references or floating +point instructions. It does not allow exceptions to be thrown from +arbitrary signal handlers such as \f(CW\*(C`SIGALRM\*(C'\fR. +.IP "\fB\-funwind\-tables\fR" 4 +.IX Item "-funwind-tables" +Similar to \fB\-fexceptions\fR, except that it will just generate any needed +static data, but will not affect the generated code in any other way. +You will normally not enable this option; instead, a language processor +that needs this handling would enable it on your behalf. +.IP "\fB\-fasynchronous\-unwind\-tables\fR" 4 +.IX Item "-fasynchronous-unwind-tables" +Generate unwind table in dwarf2 format, if supported by target machine. The +table is exact at each instruction boundary, so it can be used for stack +unwinding from asynchronous events (such as debugger or garbage collector). +.IP "\fB\-fpcc\-struct\-return\fR" 4 +.IX Item "-fpcc-struct-return" +Return \*(L"short\*(R" \f(CW\*(C`struct\*(C'\fR and \f(CW\*(C`union\*(C'\fR values in memory like +longer ones, rather than in registers. This convention is less +efficient, but it has the advantage of allowing intercallability between +GCC-compiled files and files compiled with other compilers, particularly +the Portable C Compiler (pcc). +.Sp +The precise convention for returning structures in memory depends +on the target configuration macros. +.Sp +Short structures and unions are those whose size and alignment match +that of some integer type. +.Sp +\&\fBWarning:\fR code compiled with the \fB\-fpcc\-struct\-return\fR +switch is not binary compatible with code compiled with the +\&\fB\-freg\-struct\-return\fR switch. +Use it to conform to a non-default application binary interface. +.IP "\fB\-freg\-struct\-return\fR" 4 +.IX Item "-freg-struct-return" +Return \f(CW\*(C`struct\*(C'\fR and \f(CW\*(C`union\*(C'\fR values in registers when possible. +This is more efficient for small structures than +\&\fB\-fpcc\-struct\-return\fR. +.Sp +If you specify neither \fB\-fpcc\-struct\-return\fR nor +\&\fB\-freg\-struct\-return\fR, \s-1GCC\s0 defaults to whichever convention is +standard for the target. If there is no standard convention, \s-1GCC\s0 +defaults to \fB\-fpcc\-struct\-return\fR, except on targets where \s-1GCC\s0 is +the principal compiler. In those cases, we can choose the standard, and +we chose the more efficient register return alternative. +.Sp +\&\fBWarning:\fR code compiled with the \fB\-freg\-struct\-return\fR +switch is not binary compatible with code compiled with the +\&\fB\-fpcc\-struct\-return\fR switch. +Use it to conform to a non-default application binary interface. +.IP "\fB\-fshort\-enums\fR" 4 +.IX Item "-fshort-enums" +Allocate to an \f(CW\*(C`enum\*(C'\fR type only as many bytes as it needs for the +declared range of possible values. Specifically, the \f(CW\*(C`enum\*(C'\fR type +will be equivalent to the smallest integer type which has enough room. +.Sp +\&\fBWarning:\fR the \fB\-fshort\-enums\fR switch causes \s-1GCC\s0 to generate +code that is not binary compatible with code generated without that switch. +Use it to conform to a non-default application binary interface. +.IP "\fB\-fshort\-double\fR" 4 +.IX Item "-fshort-double" +Use the same size for \f(CW\*(C`double\*(C'\fR as for \f(CW\*(C`float\*(C'\fR. +.Sp +\&\fBWarning:\fR the \fB\-fshort\-double\fR switch causes \s-1GCC\s0 to generate +code that is not binary compatible with code generated without that switch. +Use it to conform to a non-default application binary interface. +.IP "\fB\-fshort\-wchar\fR" 4 +.IX Item "-fshort-wchar" +Override the underlying type for \fBwchar_t\fR to be \fBshort +unsigned int\fR instead of the default for the target. This option is +useful for building programs to run under \s-1WINE\s0. +.Sp +\&\fBWarning:\fR the \fB\-fshort\-wchar\fR switch causes \s-1GCC\s0 to generate +code that is not binary compatible with code generated without that switch. +Use it to conform to a non-default application binary interface. +.IP "\fB\-fno\-common\fR" 4 +.IX Item "-fno-common" +In C code, controls the placement of uninitialized global variables. +Unix C compilers have traditionally permitted multiple definitions of +such variables in different compilation units by placing the variables +in a common block. +This is the behavior specified by \fB\-fcommon\fR, and is the default +for \s-1GCC\s0 on most targets. +On the other hand, this behavior is not required by \s-1ISO\s0 C, and on some +targets may carry a speed or code size penalty on variable references. +The \fB\-fno\-common\fR option specifies that the compiler should place +uninitialized global variables in the data section of the object file, +rather than generating them as common blocks. +This has the effect that if the same variable is declared +(without \f(CW\*(C`extern\*(C'\fR) in two different compilations, +you will get a multiple-definition error when you link them. +In this case, you must compile with \fB\-fcommon\fR instead. +Compiling with \fB\-fno\-common\fR is useful on targets for which +it provides better performance, or if you wish to verify that the +program will work on other systems which always treat uninitialized +variable declarations this way. +.IP "\fB\-fno\-ident\fR" 4 +.IX Item "-fno-ident" +Ignore the \fB#ident\fR directive. +.IP "\fB\-finhibit\-size\-directive\fR" 4 +.IX Item "-finhibit-size-directive" +Don't output a \f(CW\*(C`.size\*(C'\fR assembler directive, or anything else that +would cause trouble if the function is split in the middle, and the +two halves are placed at locations far apart in memory. This option is +used when compiling \fIcrtstuff.c\fR; you should not need to use it +for anything else. +.IP "\fB\-fverbose\-asm\fR" 4 +.IX Item "-fverbose-asm" +Put extra commentary information in the generated assembly code to +make it more readable. This option is generally only of use to those +who actually need to read the generated assembly code (perhaps while +debugging the compiler itself). +.Sp +\&\fB\-fno\-verbose\-asm\fR, the default, causes the +extra information to be omitted and is useful when comparing two assembler +files. +.IP "\fB\-frecord\-gcc\-switches\fR" 4 +.IX Item "-frecord-gcc-switches" +This switch causes the command line that was used to invoke the +compiler to be recorded into the object file that is being created. +This switch is only implemented on some targets and the exact format +of the recording is target and binary file format dependent, but it +usually takes the form of a section containing \s-1ASCII\s0 text. This +switch is related to the \fB\-fverbose\-asm\fR switch, but that +switch only records information in the assembler output file as +comments, so it never reaches the object file. +.IP "\fB\-fpic\fR" 4 +.IX Item "-fpic" +Generate position-independent code (\s-1PIC\s0) suitable for use in a shared +library, if supported for the target machine. Such code accesses all +constant addresses through a global offset table (\s-1GOT\s0). The dynamic +loader resolves the \s-1GOT\s0 entries when the program starts (the dynamic +loader is not part of \s-1GCC\s0; it is part of the operating system). If +the \s-1GOT\s0 size for the linked executable exceeds a machine-specific +maximum size, you get an error message from the linker indicating that +\&\fB\-fpic\fR does not work; in that case, recompile with \fB\-fPIC\fR +instead. (These maximums are 8k on the \s-1SPARC\s0 and 32k +on the m68k and \s-1RS/6000\s0. The 386 has no such limit.) +.Sp +Position-independent code requires special support, and therefore works +only on certain machines. For the 386, \s-1GCC\s0 supports \s-1PIC\s0 for System V +but not for the Sun 386i. Code generated for the \s-1IBM\s0 \s-1RS/6000\s0 is always +position-independent. +.Sp +When this flag is set, the macros \f(CW\*(C`_\|_pic_\|_\*(C'\fR and \f(CW\*(C`_\|_PIC_\|_\*(C'\fR +are defined to 1. +.IP "\fB\-fPIC\fR" 4 +.IX Item "-fPIC" +If supported for the target machine, emit position-independent code, +suitable for dynamic linking and avoiding any limit on the size of the +global offset table. This option makes a difference on the m68k, +PowerPC and \s-1SPARC\s0. +.Sp +Position-independent code requires special support, and therefore works +only on certain machines. +.Sp +When this flag is set, the macros \f(CW\*(C`_\|_pic_\|_\*(C'\fR and \f(CW\*(C`_\|_PIC_\|_\*(C'\fR +are defined to 2. +.IP "\fB\-fpie\fR" 4 +.IX Item "-fpie" +.PD 0 +.IP "\fB\-fPIE\fR" 4 +.IX Item "-fPIE" +.PD +These options are similar to \fB\-fpic\fR and \fB\-fPIC\fR, but +generated position independent code can be only linked into executables. +Usually these options are used when \fB\-pie\fR \s-1GCC\s0 option will be +used during linking. +.Sp +\&\fB\-fpie\fR and \fB\-fPIE\fR both define the macros +\&\f(CW\*(C`_\|_pie_\|_\*(C'\fR and \f(CW\*(C`_\|_PIE_\|_\*(C'\fR. The macros have the value 1 +for \fB\-fpie\fR and 2 for \fB\-fPIE\fR. +.IP "\fB\-fno\-jump\-tables\fR" 4 +.IX Item "-fno-jump-tables" +Do not use jump tables for switch statements even where it would be +more efficient than other code generation strategies. This option is +of use in conjunction with \fB\-fpic\fR or \fB\-fPIC\fR for +building code which forms part of a dynamic linker and cannot +reference the address of a jump table. On some targets, jump tables +do not require a \s-1GOT\s0 and this option is not needed. +.IP "\fB\-ffixed\-\fR\fIreg\fR" 4 +.IX Item "-ffixed-reg" +Treat the register named \fIreg\fR as a fixed register; generated code +should never refer to it (except perhaps as a stack pointer, frame +pointer or in some other fixed role). +.Sp +\&\fIreg\fR must be the name of a register. The register names accepted +are machine-specific and are defined in the \f(CW\*(C`REGISTER_NAMES\*(C'\fR +macro in the machine description macro file. +.Sp +This flag does not have a negative form, because it specifies a +three-way choice. +.IP "\fB\-fcall\-used\-\fR\fIreg\fR" 4 +.IX Item "-fcall-used-reg" +Treat the register named \fIreg\fR as an allocable register that is +clobbered by function calls. It may be allocated for temporaries or +variables that do not live across a call. Functions compiled this way +will not save and restore the register \fIreg\fR. +.Sp +It is an error to used this flag with the frame pointer or stack pointer. +Use of this flag for other registers that have fixed pervasive roles in +the machine's execution model will produce disastrous results. +.Sp +This flag does not have a negative form, because it specifies a +three-way choice. +.IP "\fB\-fcall\-saved\-\fR\fIreg\fR" 4 +.IX Item "-fcall-saved-reg" +Treat the register named \fIreg\fR as an allocable register saved by +functions. It may be allocated even for temporaries or variables that +live across a call. Functions compiled this way will save and restore +the register \fIreg\fR if they use it. +.Sp +It is an error to used this flag with the frame pointer or stack pointer. +Use of this flag for other registers that have fixed pervasive roles in +the machine's execution model will produce disastrous results. +.Sp +A different sort of disaster will result from the use of this flag for +a register in which function values may be returned. +.Sp +This flag does not have a negative form, because it specifies a +three-way choice. +.IP "\fB\-fpack\-struct[=\fR\fIn\fR\fB]\fR" 4 +.IX Item "-fpack-struct[=n]" +Without a value specified, pack all structure members together without +holes. When a value is specified (which must be a small power of two), pack +structure members according to this value, representing the maximum +alignment (that is, objects with default alignment requirements larger than +this will be output potentially unaligned at the next fitting location. +.Sp +\&\fBWarning:\fR the \fB\-fpack\-struct\fR switch causes \s-1GCC\s0 to generate +code that is not binary compatible with code generated without that switch. +Additionally, it makes the code suboptimal. +Use it to conform to a non-default application binary interface. +.IP "\fB\-finstrument\-functions\fR" 4 +.IX Item "-finstrument-functions" +Generate instrumentation calls for entry and exit to functions. Just +after function entry and just before function exit, the following +profiling functions will be called with the address of the current +function and its call site. (On some platforms, +\&\f(CW\*(C`_\|_builtin_return_address\*(C'\fR does not work beyond the current +function, so the call site information may not be available to the +profiling functions otherwise.) +.Sp +.Vb 4 +\& void _\|_cyg_profile_func_enter (void *this_fn, +\& void *call_site); +\& void _\|_cyg_profile_func_exit (void *this_fn, +\& void *call_site); +.Ve +.Sp +The first argument is the address of the start of the current function, +which may be looked up exactly in the symbol table. +.Sp +This instrumentation is also done for functions expanded inline in other +functions. The profiling calls will indicate where, conceptually, the +inline function is entered and exited. This means that addressable +versions of such functions must be available. If all your uses of a +function are expanded inline, this may mean an additional expansion of +code size. If you use \fBextern inline\fR in your C code, an +addressable version of such functions must be provided. (This is +normally the case anyways, but if you get lucky and the optimizer always +expands the functions inline, you might have gotten away without +providing static copies.) +.Sp +A function may be given the attribute \f(CW\*(C`no_instrument_function\*(C'\fR, in +which case this instrumentation will not be done. This can be used, for +example, for the profiling functions listed above, high-priority +interrupt routines, and any functions from which the profiling functions +cannot safely be called (perhaps signal handlers, if the profiling +routines generate output or allocate memory). +.IP "\fB\-finstrument\-functions\-exclude\-file\-list=\fR\fIfile\fR\fB,\fR\fIfile\fR\fB,...\fR" 4 +.IX Item "-finstrument-functions-exclude-file-list=file,file,..." +Set the list of functions that are excluded from instrumentation (see +the description of \f(CW\*(C`\-finstrument\-functions\*(C'\fR). If the file that +contains a function definition matches with one of \fIfile\fR, then +that function is not instrumented. The match is done on substrings: +if the \fIfile\fR parameter is a substring of the file name, it is +considered to be a match. +.Sp +For example: +.Sp +.Vb 1 +\& \-finstrument\-functions\-exclude\-file\-list=/bits/stl,include/sys +.Ve +.Sp +will exclude any inline function defined in files whose pathnames +contain \f(CW\*(C`/bits/stl\*(C'\fR or \f(CW\*(C`include/sys\*(C'\fR. +.Sp +If, for some reason, you want to include letter \f(CW\*(Aq,\*(Aq\fR in one of +\&\fIsym\fR, write \f(CW\*(Aq,\*(Aq\fR. For example, +\&\f(CW\*(C`\-finstrument\-functions\-exclude\-file\-list=\*(Aq,,tmp\*(Aq\*(C'\fR +(note the single quote surrounding the option). +.IP "\fB\-finstrument\-functions\-exclude\-function\-list=\fR\fIsym\fR\fB,\fR\fIsym\fR\fB,...\fR" 4 +.IX Item "-finstrument-functions-exclude-function-list=sym,sym,..." +This is similar to \f(CW\*(C`\-finstrument\-functions\-exclude\-file\-list\*(C'\fR, +but this option sets the list of function names to be excluded from +instrumentation. The function name to be matched is its user-visible +name, such as \f(CW\*(C`vector<int> blah(const vector<int> &)\*(C'\fR, not the +internal mangled name (e.g., \f(CW\*(C`_Z4blahRSt6vectorIiSaIiEE\*(C'\fR). The +match is done on substrings: if the \fIsym\fR parameter is a substring +of the function name, it is considered to be a match. For C99 and \*(C+ +extended identifiers, the function name must be given in \s-1UTF\-8\s0, not +using universal character names. +.IP "\fB\-fstack\-check\fR" 4 +.IX Item "-fstack-check" +Generate code to verify that you do not go beyond the boundary of the +stack. You should specify this flag if you are running in an +environment with multiple threads, but only rarely need to specify it in +a single-threaded environment since stack overflow is automatically +detected on nearly all systems if there is only one stack. +.Sp +Note that this switch does not actually cause checking to be done; the +operating system or the language runtime must do that. The switch causes +generation of code to ensure that they see the stack being extended. +.Sp +You can additionally specify a string parameter: \f(CW\*(C`no\*(C'\fR means no +checking, \f(CW\*(C`generic\*(C'\fR means force the use of old-style checking, +\&\f(CW\*(C`specific\*(C'\fR means use the best checking method and is equivalent +to bare \fB\-fstack\-check\fR. +.Sp +Old-style checking is a generic mechanism that requires no specific +target support in the compiler but comes with the following drawbacks: +.RS 4 +.IP "1." 4 +Modified allocation strategy for large objects: they will always be +allocated dynamically if their size exceeds a fixed threshold. +.IP "2." 4 +Fixed limit on the size of the static frame of functions: when it is +topped by a particular function, stack checking is not reliable and +a warning is issued by the compiler. +.IP "3." 4 +Inefficiency: because of both the modified allocation strategy and the +generic implementation, the performances of the code are hampered. +.RE +.RS 4 +.Sp +Note that old-style stack checking is also the fallback method for +\&\f(CW\*(C`specific\*(C'\fR if no target support has been added in the compiler. +.RE +.IP "\fB\-fstack\-limit\-register=\fR\fIreg\fR" 4 +.IX Item "-fstack-limit-register=reg" +.PD 0 +.IP "\fB\-fstack\-limit\-symbol=\fR\fIsym\fR" 4 +.IX Item "-fstack-limit-symbol=sym" +.IP "\fB\-fno\-stack\-limit\fR" 4 +.IX Item "-fno-stack-limit" +.PD +Generate code to ensure that the stack does not grow beyond a certain value, +either the value of a register or the address of a symbol. If the stack +would grow beyond the value, a signal is raised. For most targets, +the signal is raised before the stack overruns the boundary, so +it is possible to catch the signal without taking special precautions. +.Sp +For instance, if the stack starts at absolute address \fB0x80000000\fR +and grows downwards, you can use the flags +\&\fB\-fstack\-limit\-symbol=_\|_stack_limit\fR and +\&\fB\-Wl,\-\-defsym,_\|_stack_limit=0x7ffe0000\fR to enforce a stack limit +of 128KB. Note that this may only work with the \s-1GNU\s0 linker. +.IP "\fB\-fsplit\-stack\fR" 4 +.IX Item "-fsplit-stack" +Generate code to automatically split the stack before it overflows. +The resulting program has a discontiguous stack which can only +overflow if the program is unable to allocate any more memory. This +is most useful when running threaded programs, as it is no longer +necessary to calculate a good stack size to use for each thread. This +is currently only implemented for the i386 and x86_64 backends running +GNU/Linux. +.Sp +When code compiled with \fB\-fsplit\-stack\fR calls code compiled +without \fB\-fsplit\-stack\fR, there may not be much stack space +available for the latter code to run. If compiling all code, +including library code, with \fB\-fsplit\-stack\fR is not an option, +then the linker can fix up these calls so that the code compiled +without \fB\-fsplit\-stack\fR always has a large stack. Support for +this is implemented in the gold linker in \s-1GNU\s0 binutils release 2.21 +and later. +.IP "\fB\-fleading\-underscore\fR" 4 +.IX Item "-fleading-underscore" +This option and its counterpart, \fB\-fno\-leading\-underscore\fR, forcibly +change the way C symbols are represented in the object file. One use +is to help link with legacy assembly code. +.Sp +\&\fBWarning:\fR the \fB\-fleading\-underscore\fR switch causes \s-1GCC\s0 to +generate code that is not binary compatible with code generated without that +switch. Use it to conform to a non-default application binary interface. +Not all targets provide complete support for this switch. +.IP "\fB\-ftls\-model=\fR\fImodel\fR" 4 +.IX Item "-ftls-model=model" +Alter the thread-local storage model to be used. +The \fImodel\fR argument should be one of \f(CW\*(C`global\-dynamic\*(C'\fR, +\&\f(CW\*(C`local\-dynamic\*(C'\fR, \f(CW\*(C`initial\-exec\*(C'\fR or \f(CW\*(C`local\-exec\*(C'\fR. +.Sp +The default without \fB\-fpic\fR is \f(CW\*(C`initial\-exec\*(C'\fR; with +\&\fB\-fpic\fR the default is \f(CW\*(C`global\-dynamic\*(C'\fR. +.IP "\fB\-fvisibility=\fR\fIdefault|internal|hidden|protected\fR" 4 +.IX Item "-fvisibility=default|internal|hidden|protected" +Set the default \s-1ELF\s0 image symbol visibility to the specified option\-\-\-all +symbols will be marked with this unless overridden within the code. +Using this feature can very substantially improve linking and +load times of shared object libraries, produce more optimized +code, provide near-perfect \s-1API\s0 export and prevent symbol clashes. +It is \fBstrongly\fR recommended that you use this in any shared objects +you distribute. +.Sp +Despite the nomenclature, \f(CW\*(C`default\*(C'\fR always means public; i.e., +available to be linked against from outside the shared object. +\&\f(CW\*(C`protected\*(C'\fR and \f(CW\*(C`internal\*(C'\fR are pretty useless in real-world +usage so the only other commonly used option will be \f(CW\*(C`hidden\*(C'\fR. +The default if \fB\-fvisibility\fR isn't specified is +\&\f(CW\*(C`default\*(C'\fR, i.e., make every +symbol public\-\-\-this causes the same behavior as previous versions of +\&\s-1GCC\s0. +.Sp +A good explanation of the benefits offered by ensuring \s-1ELF\s0 +symbols have the correct visibility is given by \*(L"How To Write +Shared Libraries\*(R" by Ulrich Drepper (which can be found at +<\fBhttp://people.redhat.com/~drepper/\fR>)\-\-\-however a superior +solution made possible by this option to marking things hidden when +the default is public is to make the default hidden and mark things +public. This is the norm with \s-1DLL\s0's on Windows and with \fB\-fvisibility=hidden\fR +and \f(CW\*(C`_\|_attribute_\|_ ((visibility("default")))\*(C'\fR instead of +\&\f(CW\*(C`_\|_declspec(dllexport)\*(C'\fR you get almost identical semantics with +identical syntax. This is a great boon to those working with +cross-platform projects. +.Sp +For those adding visibility support to existing code, you may find +\&\fB#pragma \s-1GCC\s0 visibility\fR of use. This works by you enclosing +the declarations you wish to set visibility for with (for example) +\&\fB#pragma \s-1GCC\s0 visibility push(hidden)\fR and +\&\fB#pragma \s-1GCC\s0 visibility pop\fR. +Bear in mind that symbol visibility should be viewed \fBas +part of the \s-1API\s0 interface contract\fR and thus all new code should +always specify visibility when it is not the default; i.e., declarations +only for use within the local \s-1DSO\s0 should \fBalways\fR be marked explicitly +as hidden as so to avoid \s-1PLT\s0 indirection overheads\-\-\-making this +abundantly clear also aids readability and self-documentation of the code. +Note that due to \s-1ISO\s0 \*(C+ specification requirements, operator new and +operator delete must always be of default visibility. +.Sp +Be aware that headers from outside your project, in particular system +headers and headers from any other library you use, may not be +expecting to be compiled with visibility other than the default. You +may need to explicitly say \fB#pragma \s-1GCC\s0 visibility push(default)\fR +before including any such headers. +.Sp +\&\fBextern\fR declarations are not affected by \fB\-fvisibility\fR, so +a lot of code can be recompiled with \fB\-fvisibility=hidden\fR with +no modifications. However, this means that calls to \fBextern\fR +functions with no explicit visibility will use the \s-1PLT\s0, so it is more +effective to use \fB_\|_attribute ((visibility))\fR and/or +\&\fB#pragma \s-1GCC\s0 visibility\fR to tell the compiler which \fBextern\fR +declarations should be treated as hidden. +.Sp +Note that \fB\-fvisibility\fR does affect \*(C+ vague linkage +entities. This means that, for instance, an exception class that will +be thrown between DSOs must be explicitly marked with default +visibility so that the \fBtype_info\fR nodes will be unified between +the DSOs. +.Sp +An overview of these techniques, their benefits and how to use them +is at <\fBhttp://gcc.gnu.org/wiki/Visibility\fR>. +.IP "\fB\-fstrict\-volatile\-bitfields\fR" 4 +.IX Item "-fstrict-volatile-bitfields" +This option should be used if accesses to volatile bitfields (or other +structure fields, although the compiler usually honors those types +anyway) should use a single access of the width of the +field's type, aligned to a natural alignment if possible. For +example, targets with memory-mapped peripheral registers might require +all such accesses to be 16 bits wide; with this flag the user could +declare all peripheral bitfields as \*(L"unsigned short\*(R" (assuming short +is 16 bits on these targets) to force \s-1GCC\s0 to use 16 bit accesses +instead of, perhaps, a more efficient 32 bit access. +.Sp +If this option is disabled, the compiler will use the most efficient +instruction. In the previous example, that might be a 32\-bit load +instruction, even though that will access bytes that do not contain +any portion of the bitfield, or memory-mapped registers unrelated to +the one being updated. +.Sp +If the target requires strict alignment, and honoring the field +type would require violating this alignment, a warning is issued. +If the field has \f(CW\*(C`packed\*(C'\fR attribute, the access is done without +honoring the field type. If the field doesn't have \f(CW\*(C`packed\*(C'\fR +attribute, the access is done honoring the field type. In both cases, +\&\s-1GCC\s0 assumes that the user knows something about the target hardware +that it is unaware of. +.Sp +The default value of this option is determined by the application binary +interface for the target processor. +.SH "ENVIRONMENT" +.IX Header "ENVIRONMENT" +This section describes several environment variables that affect how \s-1GCC\s0 +operates. Some of them work by specifying directories or prefixes to use +when searching for various kinds of files. Some are used to specify other +aspects of the compilation environment. +.PP +Note that you can also specify places to search using options such as +\&\fB\-B\fR, \fB\-I\fR and \fB\-L\fR. These +take precedence over places specified using environment variables, which +in turn take precedence over those specified by the configuration of \s-1GCC\s0. +.IP "\fB\s-1LANG\s0\fR" 4 +.IX Item "LANG" +.PD 0 +.IP "\fB\s-1LC_CTYPE\s0\fR" 4 +.IX Item "LC_CTYPE" +.IP "\fB\s-1LC_MESSAGES\s0\fR" 4 +.IX Item "LC_MESSAGES" +.IP "\fB\s-1LC_ALL\s0\fR" 4 +.IX Item "LC_ALL" +.PD +These environment variables control the way that \s-1GCC\s0 uses +localization information that allow \s-1GCC\s0 to work with different +national conventions. \s-1GCC\s0 inspects the locale categories +\&\fB\s-1LC_CTYPE\s0\fR and \fB\s-1LC_MESSAGES\s0\fR if it has been configured to do +so. These locale categories can be set to any value supported by your +installation. A typical value is \fBen_GB.UTF\-8\fR for English in the United +Kingdom encoded in \s-1UTF\-8\s0. +.Sp +The \fB\s-1LC_CTYPE\s0\fR environment variable specifies character +classification. \s-1GCC\s0 uses it to determine the character boundaries in +a string; this is needed for some multibyte encodings that contain quote +and escape characters that would otherwise be interpreted as a string +end or escape. +.Sp +The \fB\s-1LC_MESSAGES\s0\fR environment variable specifies the language to +use in diagnostic messages. +.Sp +If the \fB\s-1LC_ALL\s0\fR environment variable is set, it overrides the value +of \fB\s-1LC_CTYPE\s0\fR and \fB\s-1LC_MESSAGES\s0\fR; otherwise, \fB\s-1LC_CTYPE\s0\fR +and \fB\s-1LC_MESSAGES\s0\fR default to the value of the \fB\s-1LANG\s0\fR +environment variable. If none of these variables are set, \s-1GCC\s0 +defaults to traditional C English behavior. +.IP "\fB\s-1TMPDIR\s0\fR" 4 +.IX Item "TMPDIR" +If \fB\s-1TMPDIR\s0\fR is set, it specifies the directory to use for temporary +files. \s-1GCC\s0 uses temporary files to hold the output of one stage of +compilation which is to be used as input to the next stage: for example, +the output of the preprocessor, which is the input to the compiler +proper. +.IP "\fB\s-1GCC_EXEC_PREFIX\s0\fR" 4 +.IX Item "GCC_EXEC_PREFIX" +If \fB\s-1GCC_EXEC_PREFIX\s0\fR is set, it specifies a prefix to use in the +names of the subprograms executed by the compiler. No slash is added +when this prefix is combined with the name of a subprogram, but you can +specify a prefix that ends with a slash if you wish. +.Sp +If \fB\s-1GCC_EXEC_PREFIX\s0\fR is not set, \s-1GCC\s0 will attempt to figure out +an appropriate prefix to use based on the pathname it was invoked with. +.Sp +If \s-1GCC\s0 cannot find the subprogram using the specified prefix, it +tries looking in the usual places for the subprogram. +.Sp +The default value of \fB\s-1GCC_EXEC_PREFIX\s0\fR is +\&\fI\fIprefix\fI/lib/gcc/\fR where \fIprefix\fR is the prefix to +the installed compiler. In many cases \fIprefix\fR is the value +of \f(CW\*(C`prefix\*(C'\fR when you ran the \fIconfigure\fR script. +.Sp +Other prefixes specified with \fB\-B\fR take precedence over this prefix. +.Sp +This prefix is also used for finding files such as \fIcrt0.o\fR that are +used for linking. +.Sp +In addition, the prefix is used in an unusual way in finding the +directories to search for header files. For each of the standard +directories whose name normally begins with \fB/usr/local/lib/gcc\fR +(more precisely, with the value of \fB\s-1GCC_INCLUDE_DIR\s0\fR), \s-1GCC\s0 tries +replacing that beginning with the specified prefix to produce an +alternate directory name. Thus, with \fB\-Bfoo/\fR, \s-1GCC\s0 will search +\&\fIfoo/bar\fR where it would normally search \fI/usr/local/lib/bar\fR. +These alternate directories are searched first; the standard directories +come next. If a standard directory begins with the configured +\&\fIprefix\fR then the value of \fIprefix\fR is replaced by +\&\fB\s-1GCC_EXEC_PREFIX\s0\fR when looking for header files. +.IP "\fB\s-1COMPILER_PATH\s0\fR" 4 +.IX Item "COMPILER_PATH" +The value of \fB\s-1COMPILER_PATH\s0\fR is a colon-separated list of +directories, much like \fB\s-1PATH\s0\fR. \s-1GCC\s0 tries the directories thus +specified when searching for subprograms, if it can't find the +subprograms using \fB\s-1GCC_EXEC_PREFIX\s0\fR. +.IP "\fB\s-1LIBRARY_PATH\s0\fR" 4 +.IX Item "LIBRARY_PATH" +The value of \fB\s-1LIBRARY_PATH\s0\fR is a colon-separated list of +directories, much like \fB\s-1PATH\s0\fR. When configured as a native compiler, +\&\s-1GCC\s0 tries the directories thus specified when searching for special +linker files, if it can't find them using \fB\s-1GCC_EXEC_PREFIX\s0\fR. Linking +using \s-1GCC\s0 also uses these directories when searching for ordinary +libraries for the \fB\-l\fR option (but directories specified with +\&\fB\-L\fR come first). +.IP "\fB\s-1LANG\s0\fR" 4 +.IX Item "LANG" +This variable is used to pass locale information to the compiler. One way in +which this information is used is to determine the character set to be used +when character literals, string literals and comments are parsed in C and \*(C+. +When the compiler is configured to allow multibyte characters, +the following values for \fB\s-1LANG\s0\fR are recognized: +.RS 4 +.IP "\fBC\-JIS\fR" 4 +.IX Item "C-JIS" +Recognize \s-1JIS\s0 characters. +.IP "\fBC\-SJIS\fR" 4 +.IX Item "C-SJIS" +Recognize \s-1SJIS\s0 characters. +.IP "\fBC\-EUCJP\fR" 4 +.IX Item "C-EUCJP" +Recognize \s-1EUCJP\s0 characters. +.RE +.RS 4 +.Sp +If \fB\s-1LANG\s0\fR is not defined, or if it has some other value, then the +compiler will use mblen and mbtowc as defined by the default locale to +recognize and translate multibyte characters. +.RE +.PP +Some additional environments variables affect the behavior of the +preprocessor. +.IP "\fB\s-1CPATH\s0\fR" 4 +.IX Item "CPATH" +.PD 0 +.IP "\fBC_INCLUDE_PATH\fR" 4 +.IX Item "C_INCLUDE_PATH" +.IP "\fB\s-1CPLUS_INCLUDE_PATH\s0\fR" 4 +.IX Item "CPLUS_INCLUDE_PATH" +.IP "\fB\s-1OBJC_INCLUDE_PATH\s0\fR" 4 +.IX Item "OBJC_INCLUDE_PATH" +.PD +Each variable's value is a list of directories separated by a special +character, much like \fB\s-1PATH\s0\fR, in which to look for header files. +The special character, \f(CW\*(C`PATH_SEPARATOR\*(C'\fR, is target-dependent and +determined at \s-1GCC\s0 build time. For Microsoft Windows-based targets it is a +semicolon, and for almost all other targets it is a colon. +.Sp +\&\fB\s-1CPATH\s0\fR specifies a list of directories to be searched as if +specified with \fB\-I\fR, but after any paths given with \fB\-I\fR +options on the command line. This environment variable is used +regardless of which language is being preprocessed. +.Sp +The remaining environment variables apply only when preprocessing the +particular language indicated. Each specifies a list of directories +to be searched as if specified with \fB\-isystem\fR, but after any +paths given with \fB\-isystem\fR options on the command line. +.Sp +In all these variables, an empty element instructs the compiler to +search its current working directory. Empty elements can appear at the +beginning or end of a path. For instance, if the value of +\&\fB\s-1CPATH\s0\fR is \f(CW\*(C`:/special/include\*(C'\fR, that has the same +effect as \fB\-I.\ \-I/special/include\fR. +.IP "\fB\s-1DEPENDENCIES_OUTPUT\s0\fR" 4 +.IX Item "DEPENDENCIES_OUTPUT" +If this variable is set, its value specifies how to output +dependencies for Make based on the non-system header files processed +by the compiler. System header files are ignored in the dependency +output. +.Sp +The value of \fB\s-1DEPENDENCIES_OUTPUT\s0\fR can be just a file name, in +which case the Make rules are written to that file, guessing the target +name from the source file name. Or the value can have the form +\&\fIfile\fR\fB \fR\fItarget\fR, in which case the rules are written to +file \fIfile\fR using \fItarget\fR as the target name. +.Sp +In other words, this environment variable is equivalent to combining +the options \fB\-MM\fR and \fB\-MF\fR, +with an optional \fB\-MT\fR switch too. +.IP "\fB\s-1SUNPRO_DEPENDENCIES\s0\fR" 4 +.IX Item "SUNPRO_DEPENDENCIES" +This variable is the same as \fB\s-1DEPENDENCIES_OUTPUT\s0\fR (see above), +except that system header files are not ignored, so it implies +\&\fB\-M\fR rather than \fB\-MM\fR. However, the dependence on the +main input file is omitted. +.SH "BUGS" +.IX Header "BUGS" +For instructions on reporting bugs, see +<\fBhttp://gcc.gnu.org/bugs.html\fR>. +.SH "FOOTNOTES" +.IX Header "FOOTNOTES" +.IP "1." 4 +On some systems, \fBgcc \-shared\fR +needs to build supplementary stub code for constructors to work. On +multi-libbed systems, \fBgcc \-shared\fR must select the correct support +libraries to link against. Failing to supply the correct flags may lead +to subtle defects. Supplying them in cases where they are not necessary +is innocuous. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fIgpl\fR\|(7), \fIgfdl\fR\|(7), \fIfsf\-funding\fR\|(7), +\&\fIcpp\fR\|(1), \fIgcov\fR\|(1), \fIas\fR\|(1), \fIld\fR\|(1), \fIgdb\fR\|(1), \fIadb\fR\|(1), \fIdbx\fR\|(1), \fIsdb\fR\|(1) +and the Info entries for \fIgcc\fR, \fIcpp\fR, \fIas\fR, +\&\fIld\fR, \fIbinutils\fR and \fIgdb\fR. +.SH "AUTHOR" +.IX Header "AUTHOR" +See the Info entry for \fBgcc\fR, or +<\fBhttp://gcc.gnu.org/onlinedocs/gcc/Contributors.html\fR>, +for contributors to \s-1GCC\s0. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, +1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 or +any later version published by the Free Software Foundation; with the +Invariant Sections being \*(L"\s-1GNU\s0 General Public License\*(R" and \*(L"Funding +Free Software\*(R", the Front-Cover texts being (a) (see below), and with +the Back-Cover Texts being (b) (see below). A copy of the license is +included in the \fIgfdl\fR\|(7) man page. +.PP +(a) The \s-1FSF\s0's Front-Cover Text is: +.PP +.Vb 1 +\& A GNU Manual +.Ve +.PP +(b) The \s-1FSF\s0's Back-Cover Text is: +.PP +.Vb 3 +\& You have freedom to copy and modify this GNU Manual, like GNU +\& software. Copies published by the Free Software Foundation raise +\& funds for GNU development. +.Ve diff --git a/share/man/man1/arm-eabi-gcc.1 b/share/man/man1/arm-eabi-gcc.1 new file mode 100644 index 0000000..d08d4ac --- /dev/null +++ b/share/man/man1/arm-eabi-gcc.1 @@ -0,0 +1,17818 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "GCC 1" +.TH GCC 1 "2012-01-06" "gcc-4.6.x-google" "GNU" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +gcc \- GNU project C and C++ compiler +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +gcc [\fB\-c\fR|\fB\-S\fR|\fB\-E\fR] [\fB\-std=\fR\fIstandard\fR] + [\fB\-g\fR] [\fB\-pg\fR] [\fB\-O\fR\fIlevel\fR] + [\fB\-W\fR\fIwarn\fR...] [\fB\-pedantic\fR] + [\fB\-I\fR\fIdir\fR...] [\fB\-L\fR\fIdir\fR...] + [\fB\-D\fR\fImacro\fR[=\fIdefn\fR]...] [\fB\-U\fR\fImacro\fR] + [\fB\-f\fR\fIoption\fR...] [\fB\-m\fR\fImachine-option\fR...] + [\fB\-o\fR \fIoutfile\fR] [@\fIfile\fR] \fIinfile\fR... +.PP +Only the most useful options are listed here; see below for the +remainder. \fBg++\fR accepts mostly the same options as \fBgcc\fR. +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +When you invoke \s-1GCC\s0, it normally does preprocessing, compilation, +assembly and linking. The \*(L"overall options\*(R" allow you to stop this +process at an intermediate stage. For example, the \fB\-c\fR option +says not to run the linker. Then the output consists of object files +output by the assembler. +.PP +Other options are passed on to one stage of processing. Some options +control the preprocessor and others the compiler itself. Yet other +options control the assembler and linker; most of these are not +documented here, since you rarely need to use any of them. +.PP +Most of the command line options that you can use with \s-1GCC\s0 are useful +for C programs; when an option is only useful with another language +(usually \*(C+), the explanation says so explicitly. If the description +for a particular option does not mention a source language, you can use +that option with all supported languages. +.PP +The \fBgcc\fR program accepts options and file names as operands. Many +options have multi-letter names; therefore multiple single-letter options +may \fInot\fR be grouped: \fB\-dv\fR is very different from \fB\-d\ \-v\fR. +.PP +You can mix options and other arguments. For the most part, the order +you use doesn't matter. Order does matter when you use several +options of the same kind; for example, if you specify \fB\-L\fR more +than once, the directories are searched in the order specified. Also, +the placement of the \fB\-l\fR option is significant. +.PP +Many options have long names starting with \fB\-f\fR or with +\&\fB\-W\fR\-\-\-for example, +\&\fB\-fmove\-loop\-invariants\fR, \fB\-Wformat\fR and so on. Most of +these have both positive and negative forms; the negative form of +\&\fB\-ffoo\fR would be \fB\-fno\-foo\fR. This manual documents +only one of these two forms, whichever one is not the default. +.SH "OPTIONS" +.IX Header "OPTIONS" +.SS "Option Summary" +.IX Subsection "Option Summary" +Here is a summary of all the options, grouped by type. Explanations are +in the following sections. +.IP "\fIOverall Options\fR" 4 +.IX Item "Overall Options" +\&\fB\-c \-S \-E \-o\fR \fIfile\fR \fB\-no\-canonical\-prefixes +\&\-pipe \-pass\-exit\-codes +\&\-x\fR \fIlanguage\fR \fB\-v \-### \-\-help\fR[\fB=\fR\fIclass\fR[\fB,...\fR]] \fB\-\-target\-help +\&\-\-version \-wrapper @\fR\fIfile\fR \fB\-fplugin=\fR\fIfile\fR \fB\-fplugin\-arg\-\fR\fIname\fR\fB=\fR\fIarg\fR +\&\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] \-fdump\-go\-spec=\fIfile\fR +.IP "\fIC Language Options\fR" 4 +.IX Item "C Language Options" +\&\fB\-ansi \-std=\fR\fIstandard\fR \fB\-fgnu89\-inline +\&\-aux\-info\fR \fIfilename\fR +\&\fB\-fno\-asm \-fno\-builtin \-fno\-builtin\-\fR\fIfunction\fR +\&\fB\-fhosted \-ffreestanding \-fopenmp \-fms\-extensions \-fplan9\-extensions +\&\-trigraphs \-no\-integrated\-cpp \-traditional \-traditional\-cpp +\&\-fallow\-single\-precision \-fcond\-mismatch \-flax\-vector\-conversions +\&\-fsigned\-bitfields \-fsigned\-char +\&\-funsigned\-bitfields \-funsigned\-char\fR +.IP "\fI\*(C+ Language Options\fR" 4 +.IX Item " Language Options" +\&\fB\-fabi\-version=\fR\fIn\fR \fB\-fno\-access\-control \-fcheck\-new +\&\-fconserve\-space \-fconstexpr\-depth=\fR\fIn\fR \fB\-ffriend\-injection +\&\-fno\-elide\-constructors +\&\-fno\-enforce\-eh\-specs +\&\-ffor\-scope \-fno\-for\-scope \-fno\-gnu\-keywords +\&\-fno\-implicit\-templates +\&\-fno\-implicit\-inline\-templates +\&\-fno\-implement\-inlines \-fms\-extensions +\&\-fno\-nonansi\-builtins \-fnothrow\-opt \-fno\-operator\-names +\&\-fno\-optional\-diags \-fpermissive +\&\-fno\-pretty\-templates +\&\-frepo \-fno\-rtti \-fstats \-ftemplate\-depth=\fR\fIn\fR +\&\fB\-fno\-threadsafe\-statics \-fuse\-cxa\-atexit \-fno\-weak \-nostdinc++ +\&\-fno\-default\-inline \-fvisibility\-inlines\-hidden +\&\-fvisibility\-ms\-compat +\&\-Wabi \-Wconversion\-null \-Wctor\-dtor\-privacy +\&\-Wnoexcept \-Wnon\-virtual\-dtor \-Wreorder +\&\-Weffc++ \-Wstrict\-null\-sentinel +\&\-Wno\-non\-template\-friend \-Wold\-style\-cast +\&\-Woverloaded\-virtual \-Wno\-pmf\-conversions +\&\-Wsign\-promo\fR +.IP "\fIObjective-C and Objective\-\*(C+ Language Options\fR" 4 +.IX Item "Objective-C and Objective- Language Options" +\&\fB\-fconstant\-string\-class=\fR\fIclass-name\fR +\&\fB\-fgnu\-runtime \-fnext\-runtime +\&\-fno\-nil\-receivers +\&\-fobjc\-abi\-version=\fR\fIn\fR +\&\fB\-fobjc\-call\-cxx\-cdtors +\&\-fobjc\-direct\-dispatch +\&\-fobjc\-exceptions +\&\-fobjc\-gc +\&\-fobjc\-nilcheck +\&\-fobjc\-std=objc1 +\&\-freplace\-objc\-classes +\&\-fzero\-link +\&\-gen\-decls +\&\-Wassign\-intercept +\&\-Wno\-protocol \-Wselector +\&\-Wstrict\-selector\-match +\&\-Wundeclared\-selector\fR +.IP "\fILanguage Independent Options\fR" 4 +.IX Item "Language Independent Options" +\&\fB\-fmessage\-length=\fR\fIn\fR +\&\fB\-fdiagnostics\-show\-location=\fR[\fBonce\fR|\fBevery-line\fR] +\&\fB\-fno\-diagnostics\-show\-option\fR +.IP "\fIWarning Options\fR" 4 +.IX Item "Warning Options" +\&\fB\-fsyntax\-only \-fmax\-errors=\fR\fIn\fR \fB\-pedantic +\&\-pedantic\-errors +\&\-w \-Wextra \-Wall \-Waddress \-Waggregate\-return \-Warray\-bounds +\&\-Wno\-attributes \-Wno\-builtin\-macro\-redefined +\&\-Wc++\-compat \-Wc++0x\-compat \-Wcast\-align \-Wcast\-qual +\&\-Wchar\-subscripts \-Wclobbered \-Wcomment +\&\-Wconversion \-Wcoverage\-mismatch \-Wno\-cpp \-Wno\-deprecated +\&\-Wno\-deprecated\-declarations \-Wdisabled\-optimization +\&\-Wno\-div\-by\-zero \-Wdouble\-promotion \-Wempty\-body \-Wenum\-compare +\&\-Wno\-endif\-labels \-Werror \-Werror=* +\&\-Wfatal\-errors \-Wfloat\-equal \-Wformat \-Wformat=2 +\&\-Wno\-format\-contains\-nul \-Wno\-format\-extra\-args \-Wformat\-nonliteral +\&\-Wformat\-security \-Wformat\-y2k +\&\-Wframe\-larger\-than=\fR\fIlen\fR \fB\-Wjump\-misses\-init \-Wignored\-qualifiers +\&\-Wimplicit \-Wimplicit\-function\-declaration \-Wimplicit\-int +\&\-Winit\-self \-Winline \-Wmaybe\-uninitialized +\&\-Wno\-int\-to\-pointer\-cast \-Wno\-invalid\-offsetof +\&\-Winvalid\-pch \-Wlarger\-than=\fR\fIlen\fR \fB\-Wunsafe\-loop\-optimizations +\&\-Wlogical\-op \-Wlong\-long +\&\-Wmain \-Wmaybe\-uninitialized \-Wmissing\-braces \-Wmissing\-field\-initializers +\&\-Wmissing\-format\-attribute \-Wmissing\-include\-dirs +\&\-Wno\-mudflap +\&\-Wno\-multichar \-Wnonnull \-Wno\-overflow +\&\-Woverlength\-strings \-Wpacked \-Wpacked\-bitfield\-compat \-Wpadded +\&\-Wparentheses \-Wpedantic\-ms\-format \-Wno\-pedantic\-ms\-format +\&\-Wpointer\-arith \-Wno\-pointer\-to\-int\-cast +\&\-Wreal\-conversion \-Wredundant\-decls \-Wreturn\-type \-Wripa\-opt\-mismatch +\&\-Wself\-assign \-Wself\-assign\-non\-pod \-Wsequence\-point \-Wshadow +\&\-Wshadow\-compatible\-local \-Wshadow\-local +\&\-Wsign\-compare \-Wsign\-conversion \-Wstack\-protector +\&\-Wstrict\-aliasing \-Wstrict\-aliasing=n +\&\-Wstrict\-overflow \-Wstrict\-overflow=\fR\fIn\fR +\&\fB\-Wsuggest\-attribute=\fR[\fBpure\fR|\fBconst\fR|\fBnoreturn\fR] +\&\fB\-Wswitch \-Wswitch\-default \-Wswitch\-enum \-Wsync\-nand +\&\-Wsystem\-headers \-Wthread\-safety \-Wthread\-unguarded\-var +\&\-Wthread\-unguarded\-func \-Wthread\-mismatched\-lock\-order +\&\-Wthread\-mismatched\-lock\-acq\-rel \-Wthread\-reentrant\-lock +\&\-Wthread\-unsupported\-lock\-name \-Wthread\-attr\-bind\-param +\&\-Wtrampolines \-Wtrigraphs \-Wtype\-limits \-Wundef +\&\-Wuninitialized \-Wunknown\-pragmas \-Wno\-pragmas +\&\-Wunsuffixed\-float\-constants \-Wunused \-Wunused\-function +\&\-Wunused\-label \-Wunused\-parameter \-Wno\-unused\-result \-Wunused\-value +\&\-Wunused\-variable \-Wunused\-but\-set\-parameter \-Wunused\-but\-set\-variable +\&\-Wvariadic\-macros \-Wvla \-Wvolatile\-register\-var \-Wwrite\-strings\fR +.IP "\fIC and Objective-C-only Warning Options\fR" 4 +.IX Item "C and Objective-C-only Warning Options" +\&\fB\-Wbad\-function\-cast \-Wmissing\-declarations +\&\-Wmissing\-parameter\-type \-Wmissing\-prototypes \-Wnested\-externs +\&\-Wold\-style\-declaration \-Wold\-style\-definition +\&\-Wstrict\-prototypes \-Wtraditional \-Wtraditional\-conversion +\&\-Wdeclaration\-after\-statement \-Wpointer\-sign\fR +.IP "\fIDebugging Options\fR" 4 +.IX Item "Debugging Options" +\&\fB\-d\fR\fIletters\fR \fB\-dumpspecs \-dumpmachine \-dumpversion +\&\-fdbg\-cnt\-list \-fdbg\-cnt=\fR\fIcounter-value-list\fR +\&\fB\-fdisable\-ipa\-\fR\fIpass_name\fR +\&\fB\-fdisable\-rtl\-\fR\fIpass_name\fR +\&\fB\-fdisable\-rtl\-\fR\fIpass-name\fR\fB=\fR\fIrange-list\fR +\&\fB\-fdisable\-tree\-\fR\fIpass_name\fR +\&\fB\-fdisable\-tree\-\fR\fIpass-name\fR\fB=\fR\fIrange-list\fR +\&\fB\-fdump\-noaddr \-fdump\-unnumbered \-fdump\-unnumbered\-links +\&\-fdump\-translation\-unit\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-class\-hierarchy\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-ipa\-all \-fdump\-ipa\-cgraph \-fdump\-ipa\-inline +\&\-fdump\-passes +\&\-fdump\-statistics +\&\-fdump\-tree\-all +\&\-fdump\-tree\-original\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-optimized\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-cfg \-fdump\-tree\-vcg \-fdump\-tree\-alias +\&\-fdump\-tree\-ch +\&\-fdump\-tree\-ssa\fR[\fB\-\fR\fIn\fR] \fB\-fdump\-tree\-pre\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-ccp\fR[\fB\-\fR\fIn\fR] \fB\-fdump\-tree\-dce\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-gimple\fR[\fB\-raw\fR] \fB\-fdump\-tree\-mudflap\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-dom\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-dse\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-phiprop\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-phiopt\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-forwprop\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-copyrename\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-nrv \-fdump\-tree\-vect +\&\-fdump\-tree\-sink +\&\-fdump\-tree\-sra\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-forwprop\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-fre\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-tree\-vrp\fR[\fB\-\fR\fIn\fR] +\&\fB\-ftree\-vectorizer\-verbose=\fR\fIn\fR +\&\fB\-fdump\-tree\-storeccp\fR[\fB\-\fR\fIn\fR] +\&\fB\-fdump\-final\-insns=\fR\fIfile\fR +\&\fB\-fcompare\-debug\fR[\fB=\fR\fIopts\fR] \fB\-fcompare\-debug\-second +\&\-feliminate\-dwarf2\-dups \-feliminate\-unused\-debug\-types +\&\-feliminate\-unused\-debug\-symbols \-femit\-class\-debug\-always +\&\-fenable\-icf\-debug +\&\-fenable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR +\&\fB\-fenable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR +\&\fB\-fdebug\-types\-section +\&\-fmem\-report \-fpre\-ipa\-mem\-report \-fpost\-ipa\-mem\-report \-fprofile\-arcs +\&\-frandom\-seed=\fR\fIstring\fR \fB\-fsched\-verbose=\fR\fIn\fR +\&\fB\-fsel\-sched\-verbose \-fsel\-sched\-dump\-cfg \-fsel\-sched\-pipelining\-verbose +\&\-fstack\-usage \-ftest\-coverage \-ftime\-report \-fvar\-tracking +\&\-fvar\-tracking\-assignments \-fvar\-tracking\-assignments\-toggle +\&\-g \-g\fR\fIlevel\fR \fB\-gtoggle \-gcoff \-gdwarf\-\fR\fIversion\fR +\&\fB\-ggdb \-gmlt \-gstabs \-gstabs+ \-gstrict\-dwarf \-gno\-strict\-dwarf +\&\-gvms \-gxcoff \-gxcoff+ +\&\-fno\-merge\-debug\-strings \-fno\-dwarf2\-cfi\-asm +\&\-fdebug\-prefix\-map=\fR\fIold\fR\fB=\fR\fInew\fR +\&\fB\-femit\-struct\-debug\-baseonly \-femit\-struct\-debug\-reduced +\&\-femit\-struct\-debug\-detailed\fR[\fB=\fR\fIspec-list\fR] +\&\fB\-p \-pg \-print\-file\-name=\fR\fIlibrary\fR \fB\-print\-libgcc\-file\-name +\&\-print\-multi\-directory \-print\-multi\-lib \-print\-multi\-os\-directory +\&\-print\-prog\-name=\fR\fIprogram\fR \fB\-print\-search\-dirs \-Q +\&\-print\-sysroot \-print\-sysroot\-headers\-suffix +\&\-save\-temps \-save\-temps=cwd \-save\-temps=obj \-time\fR[\fB=\fR\fIfile\fR] +.IP "\fIOptimization Options\fR" 4 +.IX Item "Optimization Options" +\&\fB\-falign\-functions[=\fR\fIn\fR\fB] \-falign\-jumps[=\fR\fIn\fR\fB] +\&\-falign\-labels[=\fR\fIn\fR\fB] \-falign\-loops[=\fR\fIn\fR\fB] \-fassociative\-math +\&\-fauto\-inc\-dec \-fbranch\-probabilities \-fbranch\-target\-load\-optimize +\&\-fbranch\-target\-load\-optimize2 \-fbtr\-bb\-exclusive \-fcaller\-saves +\&\-fcallgraph\-profiles\-sections \-fcheck\-data\-deps \-fclone\-hot\-version\-paths +\&\-fcombine\-stack\-adjustments \-fconserve\-stack +\&\-fcompare\-elim \-fcprop\-registers \-fcrossjumping +\&\-fcse\-follow\-jumps \-fcse\-skip\-blocks \-fcx\-fortran\-rules +\&\-fcx\-limited\-range +\&\-fdata\-sections \-fdce \-fdce \-fdelayed\-branch +\&\-fdelete\-null\-pointer\-checks \-fdse \-fdevirtualize \-fdse +\&\-fearly\-inlining \-fipa\-sra \-fexpensive\-optimizations \-ffast\-math +\&\-ffinite\-math\-only \-ffloat\-store \-fexcess\-precision=\fR\fIstyle\fR +\&\fB\-fforward\-propagate \-ffp\-contract=\fR\fIstyle\fR \fB\-ffunction\-sections +\&\-fgcse \-fgcse\-after\-reload \-fgcse\-las \-fgcse\-lm \-fgraphite\-identity +\&\-fgcse\-sm \-fif\-conversion \-fif\-conversion2 \-findirect\-inlining +\&\-finline\-functions \-finline\-functions\-called\-once \-finline\-limit=\fR\fIn\fR +\&\fB\-finline\-small\-functions \-fipa\-cp \-fipa\-cp\-clone \-fipa\-matrix\-reorg +\&\-fipa\-pta \-fipa\-profile \-fipa\-pure\-const \-fipa\-reference +\&\-fipa\-struct\-reorg \-fira\-algorithm=\fR\fIalgorithm\fR +\&\fB\-fira\-region=\fR\fIregion\fR +\&\fB\-fira\-loop\-pressure \-fno\-ira\-share\-save\-slots +\&\-fno\-ira\-share\-spill\-slots \-fira\-verbose=\fR\fIn\fR +\&\fB\-fivopts \-fkeep\-inline\-functions \-fkeep\-static\-consts +\&\-floop\-block \-floop\-flatten \-floop\-interchange \-floop\-strip\-mine +\&\-floop\-parallelize\-all \-flto \-flto\-compression\-level +\&\-flto\-partition=\fR\fIalg\fR \fB\-flto\-report \-fmerge\-all\-constants +\&\-fmerge\-constants \-fmodulo\-sched \-fmodulo\-sched\-allow\-regmoves +\&\-fmove\-loop\-invariants fmudflap \-fmudflapir \-fmudflapth \-fno\-branch\-count\-reg +\&\-fno\-default\-inline +\&\-fno\-defer\-pop \-fno\-function\-cse \-fno\-guess\-branch\-probability +\&\-fno\-inline \-fno\-math\-errno \-fno\-peephole \-fno\-peephole2 +\&\-fno\-sched\-interblock \-fno\-sched\-spec \-fno\-signed\-zeros +\&\-fno\-toplevel\-reorder \-fno\-trapping\-math \-fno\-zero\-initialized\-in\-bss +\&\-fomit\-frame\-pointer \-foptimize\-register\-move \-foptimize\-sibling\-calls +\&\-fpartial\-inlining \-fpeel\-loops \-fpredictive\-commoning +\&\-fprefetch\-loop\-arrays +\&\-fprofile\-correction \-fprofile\-dir=\fR\fIpath\fR \fB\-fprofile\-generate +\&\-fprofile\-generate=\fR\fIpath\fR \fB\-fprofile\-generate\-sampling +\&\-fprofile\-use \-fprofile\-use=\fR\fIpath\fR \fB\-fprofile\-values +\&\-fpmu\-profile\-generate=\fR\fIpmuoption\fR +\&\fB\-fpmu\-profile\-use=\fR\fIpmuoption\fR +\&\fB\-freciprocal\-math \-fregmove \-frename\-registers \-freorder\-blocks +\&\-frecord\-gcc\-switches\-in\-elf +\&\-freorder\-blocks\-and\-partition \-freorder\-functions +\&\-frerun\-cse\-after\-loop \-freschedule\-modulo\-scheduled\-loops +\&\-fripa \-fripa\-disallow\-asm\-modules \-fripa\-disallow\-opt\-mismatch +\&\-fripa\-no\-promote\-always\-inline\-func \-fripa\-verbose +\&\-fripa\-peel\-size\-limit \-fripa\-unroll\-size\-limit \-frounding\-math +\&\-fsched2\-use\-superblocks \-fsched\-pressure +\&\-fsched\-spec\-load \-fsched\-spec\-load\-dangerous +\&\-fsched\-stalled\-insns\-dep[=\fR\fIn\fR\fB] \-fsched\-stalled\-insns[=\fR\fIn\fR\fB] +\&\-fsched\-group\-heuristic \-fsched\-critical\-path\-heuristic +\&\-fsched\-spec\-insn\-heuristic \-fsched\-rank\-heuristic +\&\-fsched\-last\-insn\-heuristic \-fsched\-dep\-count\-heuristic +\&\-fschedule\-insns \-fschedule\-insns2 \-fsection\-anchors +\&\-fselective\-scheduling \-fselective\-scheduling2 +\&\-fsel\-sched\-pipelining \-fsel\-sched\-pipelining\-outer\-loops +\&\-fsignaling\-nans \-fsingle\-precision\-constant \-fsplit\-ivs\-in\-unroller +\&\-fsplit\-wide\-types \-fstack\-protector \-fstack\-protector\-all +\&\-fstack\-protector\-strong \-fstrict\-aliasing \-fstrict\-overflow +\&\-fthread\-jumps \-ftracer \-ftree\-bit\-ccp +\&\-ftree\-builtin\-call\-dce \-ftree\-ccp \-ftree\-ch \-ftree\-copy\-prop +\&\-ftree\-copyrename \-ftree\-dce \-ftree\-dominator\-opts \-ftree\-dse +\&\-ftree\-forwprop \-ftree\-fre \-ftree\-loop\-if\-convert +\&\-ftree\-loop\-if\-convert\-stores \-ftree\-loop\-im +\&\-ftree\-phiprop \-ftree\-loop\-distribution \-ftree\-loop\-distribute\-patterns +\&\-ftree\-loop\-ivcanon \-ftree\-loop\-linear \-ftree\-loop\-optimize +\&\-ftree\-parallelize\-loops=\fR\fIn\fR \fB\-ftree\-pre \-ftree\-pta \-ftree\-reassoc +\&\-ftree\-sink \-ftree\-sra \-ftree\-switch\-conversion +\&\-ftree\-ter \-ftree\-vect\-loop\-version \-ftree\-vectorize \-ftree\-vrp +\&\-funit\-at\-a\-time \-funroll\-all\-loops \-funroll\-loops +\&\-funsafe\-loop\-optimizations \-funsafe\-math\-optimizations \-funswitch\-loops +\&\-fvariable\-expansion\-in\-unroller \-fvect\-cost\-model \-fvpt \-fweb +\&\-fwhole\-program \-fwpa \-fuse\-ld \-fuse\-linker\-plugin +\&\-\-param\fR \fIname\fR\fB=\fR\fIvalue\fR +\&\fB\-O \-O0 \-O1 \-O2 \-O3 \-Os \-Ofast\fR +.IP "\fIPreprocessor Options\fR" 4 +.IX Item "Preprocessor Options" +\&\fB\-A\fR\fIquestion\fR\fB=\fR\fIanswer\fR +\&\fB\-A\-\fR\fIquestion\fR[\fB=\fR\fIanswer\fR] +\&\fB\-C \-dD \-dI \-dM \-dN +\&\-D\fR\fImacro\fR[\fB=\fR\fIdefn\fR] \fB\-E \-H +\&\-idirafter\fR \fIdir\fR +\&\fB\-include\fR \fIfile\fR \fB\-imacros\fR \fIfile\fR +\&\fB\-iprefix\fR \fIfile\fR \fB\-iwithprefix\fR \fIdir\fR +\&\fB\-iwithprefixbefore\fR \fIdir\fR \fB\-isystem\fR \fIdir\fR +\&\fB\-imultilib\fR \fIdir\fR \fB\-isysroot\fR \fIdir\fR +\&\fB\-M \-MM \-MF \-MG \-MP \-MQ \-MT \-nostdinc +\&\-P \-fworking\-directory \-remap +\&\-trigraphs \-undef \-U\fR\fImacro\fR \fB\-Wp,\fR\fIoption\fR +\&\fB\-Xpreprocessor\fR \fIoption\fR +.IP "\fIAssembler Option\fR" 4 +.IX Item "Assembler Option" +\&\fB\-Wa,\fR\fIoption\fR \fB\-Xassembler\fR \fIoption\fR +.IP "\fILinker Options\fR" 4 +.IX Item "Linker Options" +\&\fIobject-file-name\fR \fB\-l\fR\fIlibrary\fR +\&\fB\-nostartfiles \-nodefaultlibs \-nostdlib \-pie \-rdynamic +\&\-s \-static \-static\-libgcc \-static\-libstdc++ \-shared +\&\-shared\-libgcc \-symbolic +\&\-T\fR \fIscript\fR \fB\-Wl,\fR\fIoption\fR \fB\-Xlinker\fR \fIoption\fR +\&\fB\-u\fR \fIsymbol\fR +.IP "\fIDirectory Options\fR" 4 +.IX Item "Directory Options" +\&\fB\-B\fR\fIprefix\fR \fB\-I\fR\fIdir\fR \fB\-iplugindir=\fR\fIdir\fR +\&\-iquote\fIdir\fR \-L\fIdir\fR \-specs=\fIfile\fR \-I\- +\&\-\-sysroot=\fIdir\fR +.IP "\fIMachine Dependent Options\fR" 4 +.IX Item "Machine Dependent Options" +\&\fI\s-1ARC\s0 Options\fR +\&\fB\-EB \-EL +\&\-mmangle\-cpu \-mcpu=\fR\fIcpu\fR \fB\-mtext=\fR\fItext-section\fR +\&\fB\-mdata=\fR\fIdata-section\fR \fB\-mrodata=\fR\fIreadonly-data-section\fR +.Sp +\&\fI\s-1ARM\s0 Options\fR +\&\fB\-mapcs\-frame \-mno\-apcs\-frame +\&\-mabi=\fR\fIname\fR +\&\fB\-mapcs\-stack\-check \-mno\-apcs\-stack\-check +\&\-mapcs\-float \-mno\-apcs\-float +\&\-mapcs\-reentrant \-mno\-apcs\-reentrant +\&\-msched\-prolog \-mno\-sched\-prolog +\&\-mlittle\-endian \-mbig\-endian \-mwords\-little\-endian +\&\-mfloat\-abi=\fR\fIname\fR \fB\-msoft\-float \-mhard\-float \-mfpe +\&\-mfp16\-format=\fR\fIname\fR +\&\fB\-mthumb\-interwork \-mno\-thumb\-interwork +\&\-mcpu=\fR\fIname\fR \fB\-march=\fR\fIname\fR \fB\-mfpu=\fR\fIname\fR +\&\fB\-mstructure\-size\-boundary=\fR\fIn\fR +\&\fB\-mabort\-on\-noreturn +\&\-mlong\-calls \-mno\-long\-calls +\&\-msingle\-pic\-base \-mno\-single\-pic\-base +\&\-mpic\-register=\fR\fIreg\fR +\&\fB\-mnop\-fun\-dllimport +\&\-mcirrus\-fix\-invalid\-insns \-mno\-cirrus\-fix\-invalid\-insns +\&\-mpoke\-function\-name +\&\-mthumb \-marm +\&\-mtpcs\-frame \-mtpcs\-leaf\-frame +\&\-mcaller\-super\-interworking \-mcallee\-super\-interworking +\&\-mtp=\fR\fIname\fR +\&\fB\-mword\-relocations +\&\-mfix\-cortex\-m3\-ldrd\fR +.Sp +\&\fI\s-1AVR\s0 Options\fR +\&\fB\-mmcu=\fR\fImcu\fR \fB\-mno\-interrupts +\&\-mcall\-prologues \-mtiny\-stack \-mint8\fR +.Sp +\&\fIBlackfin Options\fR +\&\fB\-mcpu=\fR\fIcpu\fR[\fB\-\fR\fIsirevision\fR] +\&\fB\-msim \-momit\-leaf\-frame\-pointer \-mno\-omit\-leaf\-frame\-pointer +\&\-mspecld\-anomaly \-mno\-specld\-anomaly \-mcsync\-anomaly \-mno\-csync\-anomaly +\&\-mlow\-64k \-mno\-low64k \-mstack\-check\-l1 \-mid\-shared\-library +\&\-mno\-id\-shared\-library \-mshared\-library\-id=\fR\fIn\fR +\&\fB\-mleaf\-id\-shared\-library \-mno\-leaf\-id\-shared\-library +\&\-msep\-data \-mno\-sep\-data \-mlong\-calls \-mno\-long\-calls +\&\-mfast\-fp \-minline\-plt \-mmulticore \-mcorea \-mcoreb \-msdram +\&\-micplb\fR +.Sp +\&\fI\s-1CRIS\s0 Options\fR +\&\fB\-mcpu=\fR\fIcpu\fR \fB\-march=\fR\fIcpu\fR \fB\-mtune=\fR\fIcpu\fR +\&\fB\-mmax\-stack\-frame=\fR\fIn\fR \fB\-melinux\-stacksize=\fR\fIn\fR +\&\fB\-metrax4 \-metrax100 \-mpdebug \-mcc\-init \-mno\-side\-effects +\&\-mstack\-align \-mdata\-align \-mconst\-align +\&\-m32\-bit \-m16\-bit \-m8\-bit \-mno\-prologue\-epilogue \-mno\-gotplt +\&\-melf \-maout \-melinux \-mlinux \-sim \-sim2 +\&\-mmul\-bug\-workaround \-mno\-mul\-bug\-workaround\fR +.Sp +\&\fI\s-1CRX\s0 Options\fR +\&\fB\-mmac \-mpush\-args\fR +.Sp +\&\fIDarwin Options\fR +\&\fB\-all_load \-allowable_client \-arch \-arch_errors_fatal +\&\-arch_only \-bind_at_load \-bundle \-bundle_loader +\&\-client_name \-compatibility_version \-current_version +\&\-dead_strip +\&\-dependency\-file \-dylib_file \-dylinker_install_name +\&\-dynamic \-dynamiclib \-exported_symbols_list +\&\-filelist \-flat_namespace \-force_cpusubtype_ALL +\&\-force_flat_namespace \-headerpad_max_install_names +\&\-iframework +\&\-image_base \-init \-install_name \-keep_private_externs +\&\-multi_module \-multiply_defined \-multiply_defined_unused +\&\-noall_load \-no_dead_strip_inits_and_terms +\&\-nofixprebinding \-nomultidefs \-noprebind \-noseglinkedit +\&\-pagezero_size \-prebind \-prebind_all_twolevel_modules +\&\-private_bundle \-read_only_relocs \-sectalign +\&\-sectobjectsymbols \-whyload \-seg1addr +\&\-sectcreate \-sectobjectsymbols \-sectorder +\&\-segaddr \-segs_read_only_addr \-segs_read_write_addr +\&\-seg_addr_table \-seg_addr_table_filename \-seglinkedit +\&\-segprot \-segs_read_only_addr \-segs_read_write_addr +\&\-single_module \-static \-sub_library \-sub_umbrella +\&\-twolevel_namespace \-umbrella \-undefined +\&\-unexported_symbols_list \-weak_reference_mismatches +\&\-whatsloaded \-F \-gused \-gfull \-mmacosx\-version\-min=\fR\fIversion\fR +\&\fB\-mkernel \-mone\-byte\-bool\fR +.Sp +\&\fI\s-1DEC\s0 Alpha Options\fR +\&\fB\-mno\-fp\-regs \-msoft\-float \-malpha\-as \-mgas +\&\-mieee \-mieee\-with\-inexact \-mieee\-conformant +\&\-mfp\-trap\-mode=\fR\fImode\fR \fB\-mfp\-rounding\-mode=\fR\fImode\fR +\&\fB\-mtrap\-precision=\fR\fImode\fR \fB\-mbuild\-constants +\&\-mcpu=\fR\fIcpu-type\fR \fB\-mtune=\fR\fIcpu-type\fR +\&\fB\-mbwx \-mmax \-mfix \-mcix +\&\-mfloat\-vax \-mfloat\-ieee +\&\-mexplicit\-relocs \-msmall\-data \-mlarge\-data +\&\-msmall\-text \-mlarge\-text +\&\-mmemory\-latency=\fR\fItime\fR +.Sp +\&\fI\s-1DEC\s0 Alpha/VMS Options\fR +\&\fB\-mvms\-return\-codes \-mdebug\-main=\fR\fIprefix\fR \fB\-mmalloc64\fR +.Sp +\&\fI\s-1FR30\s0 Options\fR +\&\fB\-msmall\-model \-mno\-lsim\fR +.Sp +\&\fI\s-1FRV\s0 Options\fR +\&\fB\-mgpr\-32 \-mgpr\-64 \-mfpr\-32 \-mfpr\-64 +\&\-mhard\-float \-msoft\-float +\&\-malloc\-cc \-mfixed\-cc \-mdword \-mno\-dword +\&\-mdouble \-mno\-double +\&\-mmedia \-mno\-media \-mmuladd \-mno\-muladd +\&\-mfdpic \-minline\-plt \-mgprel\-ro \-multilib\-library\-pic +\&\-mlinked\-fp \-mlong\-calls \-malign\-labels +\&\-mlibrary\-pic \-macc\-4 \-macc\-8 +\&\-mpack \-mno\-pack \-mno\-eflags \-mcond\-move \-mno\-cond\-move +\&\-moptimize\-membar \-mno\-optimize\-membar +\&\-mscc \-mno\-scc \-mcond\-exec \-mno\-cond\-exec +\&\-mvliw\-branch \-mno\-vliw\-branch +\&\-mmulti\-cond\-exec \-mno\-multi\-cond\-exec \-mnested\-cond\-exec +\&\-mno\-nested\-cond\-exec \-mtomcat\-stats +\&\-mTLS \-mtls +\&\-mcpu=\fR\fIcpu\fR +.Sp +\&\fIGNU/Linux Options\fR +\&\fB\-mglibc \-muclibc \-mbionic \-mandroid +\&\-tno\-android\-cc \-tno\-android\-ld\fR +.Sp +\&\fIH8/300 Options\fR +\&\fB\-mrelax \-mh \-ms \-mn \-mint32 \-malign\-300\fR +.Sp +\&\fI\s-1HPPA\s0 Options\fR +\&\fB\-march=\fR\fIarchitecture-type\fR +\&\fB\-mbig\-switch \-mdisable\-fpregs \-mdisable\-indexing +\&\-mfast\-indirect\-calls \-mgas \-mgnu\-ld \-mhp\-ld +\&\-mfixed\-range=\fR\fIregister-range\fR +\&\fB\-mjump\-in\-delay \-mlinker\-opt \-mlong\-calls +\&\-mlong\-load\-store \-mno\-big\-switch \-mno\-disable\-fpregs +\&\-mno\-disable\-indexing \-mno\-fast\-indirect\-calls \-mno\-gas +\&\-mno\-jump\-in\-delay \-mno\-long\-load\-store +\&\-mno\-portable\-runtime \-mno\-soft\-float +\&\-mno\-space\-regs \-msoft\-float \-mpa\-risc\-1\-0 +\&\-mpa\-risc\-1\-1 \-mpa\-risc\-2\-0 \-mportable\-runtime +\&\-mschedule=\fR\fIcpu-type\fR \fB\-mspace\-regs \-msio \-mwsio +\&\-munix=\fR\fIunix-std\fR \fB\-nolibdld \-static \-threads\fR +.Sp +\&\fIi386 and x86\-64 Options\fR +\&\fB\-mtune=\fR\fIcpu-type\fR \fB\-march=\fR\fIcpu-type\fR +\&\fB\-mfpmath=\fR\fIunit\fR +\&\fB\-masm=\fR\fIdialect\fR \fB\-mno\-fancy\-math\-387 +\&\-mno\-fp\-ret\-in\-387 \-msoft\-float +\&\-mno\-wide\-multiply \-mrtd \-malign\-double +\&\-mpreferred\-stack\-boundary=\fR\fInum\fR +\&\fB\-mincoming\-stack\-boundary=\fR\fInum\fR +\&\fB\-mcld \-mcx16 \-msahf \-mmovbe \-mcrc32 \-mrecip \-mvzeroupper +\&\-mmmx \-msse \-msse2 \-msse3 \-mssse3 \-msse4.1 \-msse4.2 \-msse4 \-mavx +\&\-maes \-mpclmul \-mfsgsbase \-mrdrnd \-mf16c \-mfused\-madd +\&\-msse4a \-m3dnow \-mpopcnt \-mabm \-mbmi \-mtbm \-mfma4 \-mxop \-mlwp +\&\-mthreads \-mno\-align\-stringops \-minline\-all\-stringops +\&\-minline\-stringops\-dynamically \-mstringop\-strategy=\fR\fIalg\fR +\&\fB\-mpush\-args \-maccumulate\-outgoing\-args \-m128bit\-long\-double +\&\-m96bit\-long\-double \-mregparm=\fR\fInum\fR \fB\-msseregparm +\&\-mveclibabi=\fR\fItype\fR \fB\-mvect8\-ret\-in\-mem +\&\-mpc32 \-mpc64 \-mpc80 \-mstackrealign +\&\-momit\-leaf\-frame\-pointer \-mno\-red\-zone \-mno\-tls\-direct\-seg\-refs +\&\-mcmodel=\fR\fIcode-model\fR \fB\-mabi=\fR\fIname\fR +\&\fB\-m32 \-m64 \-mlarge\-data\-threshold=\fR\fInum\fR +\&\fB\-msse2avx \-mfentry \-m8bit\-idiv +\&\-mavx256\-split\-unaligned\-load \-mavx256\-split\-unaligned\-store\fR +.Sp +\&\fIi386 and x86\-64 Windows Options\fR +\&\fB\-mconsole \-mcygwin \-mno\-cygwin \-mdll +\&\-mnop\-fun\-dllimport \-mthread +\&\-municode \-mwin32 \-mwindows \-fno\-set\-stack\-executable\fR +.Sp +\&\fI\s-1IA\-64\s0 Options\fR +\&\fB\-mbig\-endian \-mlittle\-endian \-mgnu\-as \-mgnu\-ld \-mno\-pic +\&\-mvolatile\-asm\-stop \-mregister\-names \-msdata \-mno\-sdata +\&\-mconstant\-gp \-mauto\-pic \-mfused\-madd +\&\-minline\-float\-divide\-min\-latency +\&\-minline\-float\-divide\-max\-throughput +\&\-mno\-inline\-float\-divide +\&\-minline\-int\-divide\-min\-latency +\&\-minline\-int\-divide\-max\-throughput +\&\-mno\-inline\-int\-divide +\&\-minline\-sqrt\-min\-latency \-minline\-sqrt\-max\-throughput +\&\-mno\-inline\-sqrt +\&\-mdwarf2\-asm \-mearly\-stop\-bits +\&\-mfixed\-range=\fR\fIregister-range\fR \fB\-mtls\-size=\fR\fItls-size\fR +\&\fB\-mtune=\fR\fIcpu-type\fR \fB\-milp32 \-mlp64 +\&\-msched\-br\-data\-spec \-msched\-ar\-data\-spec \-msched\-control\-spec +\&\-msched\-br\-in\-data\-spec \-msched\-ar\-in\-data\-spec \-msched\-in\-control\-spec +\&\-msched\-spec\-ldc \-msched\-spec\-control\-ldc +\&\-msched\-prefer\-non\-data\-spec\-insns \-msched\-prefer\-non\-control\-spec\-insns +\&\-msched\-stop\-bits\-after\-every\-cycle \-msched\-count\-spec\-in\-critical\-path +\&\-msel\-sched\-dont\-check\-control\-spec \-msched\-fp\-mem\-deps\-zero\-cost +\&\-msched\-max\-memory\-insns\-hard\-limit \-msched\-max\-memory\-insns=\fR\fImax-insns\fR +.Sp +\&\fI\s-1IA\-64/VMS\s0 Options\fR +\&\fB\-mvms\-return\-codes \-mdebug\-main=\fR\fIprefix\fR \fB\-mmalloc64\fR +.Sp +\&\fI\s-1LM32\s0 Options\fR +\&\fB\-mbarrel\-shift\-enabled \-mdivide\-enabled \-mmultiply\-enabled +\&\-msign\-extend\-enabled \-muser\-enabled\fR +.Sp +\&\fIM32R/D Options\fR +\&\fB\-m32r2 \-m32rx \-m32r +\&\-mdebug +\&\-malign\-loops \-mno\-align\-loops +\&\-missue\-rate=\fR\fInumber\fR +\&\fB\-mbranch\-cost=\fR\fInumber\fR +\&\fB\-mmodel=\fR\fIcode-size-model-type\fR +\&\fB\-msdata=\fR\fIsdata-type\fR +\&\fB\-mno\-flush\-func \-mflush\-func=\fR\fIname\fR +\&\fB\-mno\-flush\-trap \-mflush\-trap=\fR\fInumber\fR +\&\fB\-G\fR \fInum\fR +.Sp +\&\fIM32C Options\fR +\&\fB\-mcpu=\fR\fIcpu\fR \fB\-msim \-memregs=\fR\fInumber\fR +.Sp +\&\fIM680x0 Options\fR +\&\fB\-march=\fR\fIarch\fR \fB\-mcpu=\fR\fIcpu\fR \fB\-mtune=\fR\fItune\fR +\&\fB\-m68000 \-m68020 \-m68020\-40 \-m68020\-60 \-m68030 \-m68040 +\&\-m68060 \-mcpu32 \-m5200 \-m5206e \-m528x \-m5307 \-m5407 +\&\-mcfv4e \-mbitfield \-mno\-bitfield \-mc68000 \-mc68020 +\&\-mnobitfield \-mrtd \-mno\-rtd \-mdiv \-mno\-div \-mshort +\&\-mno\-short \-mhard\-float \-m68881 \-msoft\-float \-mpcrel +\&\-malign\-int \-mstrict\-align \-msep\-data \-mno\-sep\-data +\&\-mshared\-library\-id=n \-mid\-shared\-library \-mno\-id\-shared\-library +\&\-mxgot \-mno\-xgot\fR +.Sp +\&\fIM68hc1x Options\fR +\&\fB\-m6811 \-m6812 \-m68hc11 \-m68hc12 \-m68hcs12 +\&\-mauto\-incdec \-minmax \-mlong\-calls \-mshort +\&\-msoft\-reg\-count=\fR\fIcount\fR +.Sp +\&\fIMCore Options\fR +\&\fB\-mhardlit \-mno\-hardlit \-mdiv \-mno\-div \-mrelax\-immediates +\&\-mno\-relax\-immediates \-mwide\-bitfields \-mno\-wide\-bitfields +\&\-m4byte\-functions \-mno\-4byte\-functions \-mcallgraph\-data +\&\-mno\-callgraph\-data \-mslow\-bytes \-mno\-slow\-bytes \-mno\-lsim +\&\-mlittle\-endian \-mbig\-endian \-m210 \-m340 \-mstack\-increment\fR +.Sp +\&\fIMeP Options\fR +\&\fB\-mabsdiff \-mall\-opts \-maverage \-mbased=\fR\fIn\fR \fB\-mbitops +\&\-mc=\fR\fIn\fR \fB\-mclip \-mconfig=\fR\fIname\fR \fB\-mcop \-mcop32 \-mcop64 \-mivc2 +\&\-mdc \-mdiv \-meb \-mel \-mio\-volatile \-ml \-mleadz \-mm \-mminmax +\&\-mmult \-mno\-opts \-mrepeat \-ms \-msatur \-msdram \-msim \-msimnovec \-mtf +\&\-mtiny=\fR\fIn\fR +.Sp +\&\fIMicroBlaze Options\fR +\&\fB\-msoft\-float \-mhard\-float \-msmall\-divides \-mcpu=\fR\fIcpu\fR +\&\fB\-mmemcpy \-mxl\-soft\-mul \-mxl\-soft\-div \-mxl\-barrel\-shift +\&\-mxl\-pattern\-compare \-mxl\-stack\-check \-mxl\-gp\-opt \-mno\-clearbss +\&\-mxl\-multiply\-high \-mxl\-float\-convert \-mxl\-float\-sqrt +\&\-mxl\-mode\-\fR\fIapp-model\fR +.Sp +\&\fI\s-1MIPS\s0 Options\fR +\&\fB\-EL \-EB \-march=\fR\fIarch\fR \fB\-mtune=\fR\fIarch\fR +\&\fB\-mips1 \-mips2 \-mips3 \-mips4 \-mips32 \-mips32r2 +\&\-mips64 \-mips64r2 +\&\-mips16 \-mno\-mips16 \-mflip\-mips16 +\&\-minterlink\-mips16 \-mno\-interlink\-mips16 +\&\-mabi=\fR\fIabi\fR \fB\-mabicalls \-mno\-abicalls +\&\-mshared \-mno\-shared \-mplt \-mno\-plt \-mxgot \-mno\-xgot +\&\-mgp32 \-mgp64 \-mfp32 \-mfp64 \-mhard\-float \-msoft\-float +\&\-msingle\-float \-mdouble\-float \-mdsp \-mno\-dsp \-mdspr2 \-mno\-dspr2 +\&\-mfpu=\fR\fIfpu-type\fR +\&\fB\-msmartmips \-mno\-smartmips +\&\-mpaired\-single \-mno\-paired\-single \-mdmx \-mno\-mdmx +\&\-mips3d \-mno\-mips3d \-mmt \-mno\-mt \-mllsc \-mno\-llsc +\&\-mlong64 \-mlong32 \-msym32 \-mno\-sym32 +\&\-G\fR\fInum\fR \fB\-mlocal\-sdata \-mno\-local\-sdata +\&\-mextern\-sdata \-mno\-extern\-sdata \-mgpopt \-mno\-gopt +\&\-membedded\-data \-mno\-embedded\-data +\&\-muninit\-const\-in\-rodata \-mno\-uninit\-const\-in\-rodata +\&\-mcode\-readable=\fR\fIsetting\fR +\&\fB\-msplit\-addresses \-mno\-split\-addresses +\&\-mexplicit\-relocs \-mno\-explicit\-relocs +\&\-mcheck\-zero\-division \-mno\-check\-zero\-division +\&\-mdivide\-traps \-mdivide\-breaks +\&\-mmemcpy \-mno\-memcpy \-mlong\-calls \-mno\-long\-calls +\&\-mmad \-mno\-mad \-mfused\-madd \-mno\-fused\-madd \-nocpp +\&\-mfix\-r4000 \-mno\-fix\-r4000 \-mfix\-r4400 \-mno\-fix\-r4400 +\&\-mfix\-r10000 \-mno\-fix\-r10000 \-mfix\-vr4120 \-mno\-fix\-vr4120 +\&\-mfix\-vr4130 \-mno\-fix\-vr4130 \-mfix\-sb1 \-mno\-fix\-sb1 +\&\-mflush\-func=\fR\fIfunc\fR \fB\-mno\-flush\-func +\&\-mbranch\-cost=\fR\fInum\fR \fB\-mbranch\-likely \-mno\-branch\-likely +\&\-mfp\-exceptions \-mno\-fp\-exceptions +\&\-mvr4130\-align \-mno\-vr4130\-align \-msynci \-mno\-synci +\&\-mrelax\-pic\-calls \-mno\-relax\-pic\-calls \-mmcount\-ra\-address\fR +.Sp +\&\fI\s-1MMIX\s0 Options\fR +\&\fB\-mlibfuncs \-mno\-libfuncs \-mepsilon \-mno\-epsilon \-mabi=gnu +\&\-mabi=mmixware \-mzero\-extend \-mknuthdiv \-mtoplevel\-symbols +\&\-melf \-mbranch\-predict \-mno\-branch\-predict \-mbase\-addresses +\&\-mno\-base\-addresses \-msingle\-exit \-mno\-single\-exit\fR +.Sp +\&\fI\s-1MN10300\s0 Options\fR +\&\fB\-mmult\-bug \-mno\-mult\-bug +\&\-mno\-am33 \-mam33 \-mam33\-2 \-mam34 +\&\-mtune=\fR\fIcpu-type\fR +\&\fB\-mreturn\-pointer\-on\-d0 +\&\-mno\-crt0 \-mrelax \-mliw\fR +.Sp +\&\fI\s-1PDP\-11\s0 Options\fR +\&\fB\-mfpu \-msoft\-float \-mac0 \-mno\-ac0 \-m40 \-m45 \-m10 +\&\-mbcopy \-mbcopy\-builtin \-mint32 \-mno\-int16 +\&\-mint16 \-mno\-int32 \-mfloat32 \-mno\-float64 +\&\-mfloat64 \-mno\-float32 \-mabshi \-mno\-abshi +\&\-mbranch\-expensive \-mbranch\-cheap +\&\-munix\-asm \-mdec\-asm\fR +.Sp +\&\fIpicoChip Options\fR +\&\fB\-mae=\fR\fIae_type\fR \fB\-mvliw\-lookahead=\fR\fIN\fR +\&\fB\-msymbol\-as\-address \-mno\-inefficient\-warnings\fR +.Sp +\&\fIPowerPC Options\fR +See \s-1RS/6000\s0 and PowerPC Options. +.Sp +\&\fI\s-1RS/6000\s0 and PowerPC Options\fR +\&\fB\-mcpu=\fR\fIcpu-type\fR +\&\fB\-mtune=\fR\fIcpu-type\fR +\&\fB\-mcmodel=\fR\fIcode-model\fR +\&\fB\-mpower \-mno\-power \-mpower2 \-mno\-power2 +\&\-mpowerpc \-mpowerpc64 \-mno\-powerpc +\&\-maltivec \-mno\-altivec +\&\-mpowerpc\-gpopt \-mno\-powerpc\-gpopt +\&\-mpowerpc\-gfxopt \-mno\-powerpc\-gfxopt +\&\-mmfcrf \-mno\-mfcrf \-mpopcntb \-mno\-popcntb \-mpopcntd \-mno\-popcntd +\&\-mfprnd \-mno\-fprnd +\&\-mcmpb \-mno\-cmpb \-mmfpgpr \-mno\-mfpgpr \-mhard\-dfp \-mno\-hard\-dfp +\&\-mnew\-mnemonics \-mold\-mnemonics +\&\-mfull\-toc \-mminimal\-toc \-mno\-fp\-in\-toc \-mno\-sum\-in\-toc +\&\-m64 \-m32 \-mxl\-compat \-mno\-xl\-compat \-mpe +\&\-malign\-power \-malign\-natural +\&\-msoft\-float \-mhard\-float \-mmultiple \-mno\-multiple +\&\-msingle\-float \-mdouble\-float \-msimple\-fpu +\&\-mstring \-mno\-string \-mupdate \-mno\-update +\&\-mavoid\-indexed\-addresses \-mno\-avoid\-indexed\-addresses +\&\-mfused\-madd \-mno\-fused\-madd \-mbit\-align \-mno\-bit\-align +\&\-mstrict\-align \-mno\-strict\-align \-mrelocatable +\&\-mno\-relocatable \-mrelocatable\-lib \-mno\-relocatable\-lib +\&\-mtoc \-mno\-toc \-mlittle \-mlittle\-endian \-mbig \-mbig\-endian +\&\-mdynamic\-no\-pic \-maltivec \-mswdiv \-msingle\-pic\-base +\&\-mprioritize\-restricted\-insns=\fR\fIpriority\fR +\&\fB\-msched\-costly\-dep=\fR\fIdependence_type\fR +\&\fB\-minsert\-sched\-nops=\fR\fIscheme\fR +\&\fB\-mcall\-sysv \-mcall\-netbsd +\&\-maix\-struct\-return \-msvr4\-struct\-return +\&\-mabi=\fR\fIabi-type\fR \fB\-msecure\-plt \-mbss\-plt +\&\-mblock\-move\-inline\-limit=\fR\fInum\fR +\&\fB\-misel \-mno\-isel +\&\-misel=yes \-misel=no +\&\-mspe \-mno\-spe +\&\-mspe=yes \-mspe=no +\&\-mpaired +\&\-mgen\-cell\-microcode \-mwarn\-cell\-microcode +\&\-mvrsave \-mno\-vrsave +\&\-mmulhw \-mno\-mulhw +\&\-mdlmzb \-mno\-dlmzb +\&\-mfloat\-gprs=yes \-mfloat\-gprs=no \-mfloat\-gprs=single \-mfloat\-gprs=double +\&\-mprototype \-mno\-prototype +\&\-msim \-mmvme \-mads \-myellowknife \-memb \-msdata +\&\-msdata=\fR\fIopt\fR \fB\-mvxworks \-G\fR \fInum\fR \fB\-pthread +\&\-mrecip \-mrecip=\fR\fIopt\fR \fB\-mno\-recip \-mrecip\-precision +\&\-mno\-recip\-precision +\&\-mveclibabi=\fR\fItype\fR \fB\-mfriz \-mno\-friz\fR +.Sp +\&\fI\s-1RX\s0 Options\fR +\&\fB\-m64bit\-doubles \-m32bit\-doubles \-fpu \-nofpu +\&\-mcpu= +\&\-mbig\-endian\-data \-mlittle\-endian\-data +\&\-msmall\-data +\&\-msim \-mno\-sim +\&\-mas100\-syntax \-mno\-as100\-syntax +\&\-mrelax +\&\-mmax\-constant\-size= +\&\-mint\-register= +\&\-msave\-acc\-in\-interrupts\fR +.Sp +\&\fIS/390 and zSeries Options\fR +\&\fB\-mtune=\fR\fIcpu-type\fR \fB\-march=\fR\fIcpu-type\fR +\&\fB\-mhard\-float \-msoft\-float \-mhard\-dfp \-mno\-hard\-dfp +\&\-mlong\-double\-64 \-mlong\-double\-128 +\&\-mbackchain \-mno\-backchain \-mpacked\-stack \-mno\-packed\-stack +\&\-msmall\-exec \-mno\-small\-exec \-mmvcle \-mno\-mvcle +\&\-m64 \-m31 \-mdebug \-mno\-debug \-mesa \-mzarch +\&\-mtpf\-trace \-mno\-tpf\-trace \-mfused\-madd \-mno\-fused\-madd +\&\-mwarn\-framesize \-mwarn\-dynamicstack \-mstack\-size \-mstack\-guard\fR +.Sp +\&\fIScore Options\fR +\&\fB\-meb \-mel +\&\-mnhwloop +\&\-muls +\&\-mmac +\&\-mscore5 \-mscore5u \-mscore7 \-mscore7d\fR +.Sp +\&\fI\s-1SH\s0 Options\fR +\&\fB\-m1 \-m2 \-m2e +\&\-m2a\-nofpu \-m2a\-single\-only \-m2a\-single \-m2a +\&\-m3 \-m3e +\&\-m4\-nofpu \-m4\-single\-only \-m4\-single \-m4 +\&\-m4a\-nofpu \-m4a\-single\-only \-m4a\-single \-m4a \-m4al +\&\-m5\-64media \-m5\-64media\-nofpu +\&\-m5\-32media \-m5\-32media\-nofpu +\&\-m5\-compact \-m5\-compact\-nofpu +\&\-mb \-ml \-mdalign \-mrelax +\&\-mbigtable \-mfmovd \-mhitachi \-mrenesas \-mno\-renesas \-mnomacsave +\&\-mieee \-mbitops \-misize \-minline\-ic_invalidate \-mpadstruct \-mspace +\&\-mprefergot \-musermode \-multcost=\fR\fInumber\fR \fB\-mdiv=\fR\fIstrategy\fR +\&\fB\-mdivsi3_libfunc=\fR\fIname\fR \fB\-mfixed\-range=\fR\fIregister-range\fR +\&\fB\-madjust\-unroll \-mindexed\-addressing \-mgettrcost=\fR\fInumber\fR \fB\-mpt\-fixed +\&\-maccumulate\-outgoing\-args \-minvalid\-symbols\fR +.Sp +\&\fISolaris 2 Options\fR +\&\fB\-mimpure\-text \-mno\-impure\-text +\&\-threads \-pthreads \-pthread\fR +.Sp +\&\fI\s-1SPARC\s0 Options\fR +\&\fB\-mcpu=\fR\fIcpu-type\fR +\&\fB\-mtune=\fR\fIcpu-type\fR +\&\fB\-mcmodel=\fR\fIcode-model\fR +\&\fB\-m32 \-m64 \-mapp\-regs \-mno\-app\-regs +\&\-mfaster\-structs \-mno\-faster\-structs +\&\-mfpu \-mno\-fpu \-mhard\-float \-msoft\-float +\&\-mhard\-quad\-float \-msoft\-quad\-float +\&\-mlittle\-endian +\&\-mstack\-bias \-mno\-stack\-bias +\&\-munaligned\-doubles \-mno\-unaligned\-doubles +\&\-mv8plus \-mno\-v8plus \-mvis \-mno\-vis +\&\-mfix\-at697f\fR +.Sp +\&\fI\s-1SPU\s0 Options\fR +\&\fB\-mwarn\-reloc \-merror\-reloc +\&\-msafe\-dma \-munsafe\-dma +\&\-mbranch\-hints +\&\-msmall\-mem \-mlarge\-mem \-mstdmain +\&\-mfixed\-range=\fR\fIregister-range\fR +\&\fB\-mea32 \-mea64 +\&\-maddress\-space\-conversion \-mno\-address\-space\-conversion +\&\-mcache\-size=\fR\fIcache-size\fR +\&\fB\-matomic\-updates \-mno\-atomic\-updates\fR +.Sp +\&\fISystem V Options\fR +\&\fB\-Qy \-Qn \-YP,\fR\fIpaths\fR \fB\-Ym,\fR\fIdir\fR +.Sp +\&\fIV850 Options\fR +\&\fB\-mlong\-calls \-mno\-long\-calls \-mep \-mno\-ep +\&\-mprolog\-function \-mno\-prolog\-function \-mspace +\&\-mtda=\fR\fIn\fR \fB\-msda=\fR\fIn\fR \fB\-mzda=\fR\fIn\fR +\&\fB\-mapp\-regs \-mno\-app\-regs +\&\-mdisable\-callt \-mno\-disable\-callt +\&\-mv850e2v3 +\&\-mv850e2 +\&\-mv850e1 \-mv850es +\&\-mv850e +\&\-mv850 \-mbig\-switch\fR +.Sp +\&\fI\s-1VAX\s0 Options\fR +\&\fB\-mg \-mgnu \-munix\fR +.Sp +\&\fIVxWorks Options\fR +\&\fB\-mrtp \-non\-static \-Bstatic \-Bdynamic +\&\-Xbind\-lazy \-Xbind\-now\fR +.Sp +\&\fIx86\-64 Options\fR +See i386 and x86\-64 Options. +.Sp +\&\fIXstormy16 Options\fR +\&\fB\-msim\fR +.Sp +\&\fIXtensa Options\fR +\&\fB\-mconst16 \-mno\-const16 +\&\-mfused\-madd \-mno\-fused\-madd +\&\-mforce\-no\-pic +\&\-mserialize\-volatile \-mno\-serialize\-volatile +\&\-mtext\-section\-literals \-mno\-text\-section\-literals +\&\-mtarget\-align \-mno\-target\-align +\&\-mlongcalls \-mno\-longcalls\fR +.Sp +\&\fIzSeries Options\fR +See S/390 and zSeries Options. +.IP "\fICode Generation Options\fR" 4 +.IX Item "Code Generation Options" +\&\fB\-fcall\-saved\-\fR\fIreg\fR \fB\-fcall\-used\-\fR\fIreg\fR +\&\fB\-ffixed\-\fR\fIreg\fR \fB\-fexceptions +\&\-fnon\-call\-exceptions \-funwind\-tables +\&\-fasynchronous\-unwind\-tables +\&\-finhibit\-size\-directive \-finstrument\-functions +\&\-finstrument\-functions\-exclude\-function\-list=\fR\fIsym\fR\fB,\fR\fIsym\fR\fB,... +\&\-finstrument\-functions\-exclude\-file\-list=\fR\fIfile\fR\fB,\fR\fIfile\fR\fB,... +\&\-fno\-common \-fno\-ident +\&\-fpcc\-struct\-return \-fpic \-fPIC \-fpie \-fPIE +\&\-fno\-jump\-tables +\&\-frecord\-gcc\-switches +\&\-freg\-struct\-return \-fshort\-enums +\&\-fshort\-double \-fshort\-wchar +\&\-fverbose\-asm \-fpack\-struct[=\fR\fIn\fR\fB] \-fstack\-check +\&\-fstack\-limit\-register=\fR\fIreg\fR \fB\-fstack\-limit\-symbol=\fR\fIsym\fR +\&\fB\-fno\-stack\-limit \-fsplit\-stack +\&\-fleading\-underscore \-ftls\-model=\fR\fImodel\fR +\&\fB\-ftrapv \-fwrapv \-fbounds\-check +\&\-fvisibility \-fstrict\-volatile\-bitfields\fR +.SS "Options Controlling the Kind of Output" +.IX Subsection "Options Controlling the Kind of Output" +Compilation can involve up to four stages: preprocessing, compilation +proper, assembly and linking, always in that order. \s-1GCC\s0 is capable of +preprocessing and compiling several files either into several +assembler input files, or into one assembler input file; then each +assembler input file produces an object file, and linking combines all +the object files (those newly compiled, and those specified as input) +into an executable file. +.PP +For any given input file, the file name suffix determines what kind of +compilation is done: +.IP "\fIfile\fR\fB.c\fR" 4 +.IX Item "file.c" +C source code which must be preprocessed. +.IP "\fIfile\fR\fB.i\fR" 4 +.IX Item "file.i" +C source code which should not be preprocessed. +.IP "\fIfile\fR\fB.ii\fR" 4 +.IX Item "file.ii" +\&\*(C+ source code which should not be preprocessed. +.IP "\fIfile\fR\fB.m\fR" 4 +.IX Item "file.m" +Objective-C source code. Note that you must link with the \fIlibobjc\fR +library to make an Objective-C program work. +.IP "\fIfile\fR\fB.mi\fR" 4 +.IX Item "file.mi" +Objective-C source code which should not be preprocessed. +.IP "\fIfile\fR\fB.mm\fR" 4 +.IX Item "file.mm" +.PD 0 +.IP "\fIfile\fR\fB.M\fR" 4 +.IX Item "file.M" +.PD +Objective\-\*(C+ source code. Note that you must link with the \fIlibobjc\fR +library to make an Objective\-\*(C+ program work. Note that \fB.M\fR refers +to a literal capital M. +.IP "\fIfile\fR\fB.mii\fR" 4 +.IX Item "file.mii" +Objective\-\*(C+ source code which should not be preprocessed. +.IP "\fIfile\fR\fB.h\fR" 4 +.IX Item "file.h" +C, \*(C+, Objective-C or Objective\-\*(C+ header file to be turned into a +precompiled header (default), or C, \*(C+ header file to be turned into an +Ada spec (via the \fB\-fdump\-ada\-spec\fR switch). +.IP "\fIfile\fR\fB.cc\fR" 4 +.IX Item "file.cc" +.PD 0 +.IP "\fIfile\fR\fB.cp\fR" 4 +.IX Item "file.cp" +.IP "\fIfile\fR\fB.cxx\fR" 4 +.IX Item "file.cxx" +.IP "\fIfile\fR\fB.cpp\fR" 4 +.IX Item "file.cpp" +.IP "\fIfile\fR\fB.CPP\fR" 4 +.IX Item "file.CPP" +.IP "\fIfile\fR\fB.c++\fR" 4 +.IX Item "file.c++" +.IP "\fIfile\fR\fB.C\fR" 4 +.IX Item "file.C" +.PD +\&\*(C+ source code which must be preprocessed. Note that in \fB.cxx\fR, +the last two letters must both be literally \fBx\fR. Likewise, +\&\fB.C\fR refers to a literal capital C. +.IP "\fIfile\fR\fB.mm\fR" 4 +.IX Item "file.mm" +.PD 0 +.IP "\fIfile\fR\fB.M\fR" 4 +.IX Item "file.M" +.PD +Objective\-\*(C+ source code which must be preprocessed. +.IP "\fIfile\fR\fB.mii\fR" 4 +.IX Item "file.mii" +Objective\-\*(C+ source code which should not be preprocessed. +.IP "\fIfile\fR\fB.hh\fR" 4 +.IX Item "file.hh" +.PD 0 +.IP "\fIfile\fR\fB.H\fR" 4 +.IX Item "file.H" +.IP "\fIfile\fR\fB.hp\fR" 4 +.IX Item "file.hp" +.IP "\fIfile\fR\fB.hxx\fR" 4 +.IX Item "file.hxx" +.IP "\fIfile\fR\fB.hpp\fR" 4 +.IX Item "file.hpp" +.IP "\fIfile\fR\fB.HPP\fR" 4 +.IX Item "file.HPP" +.IP "\fIfile\fR\fB.h++\fR" 4 +.IX Item "file.h++" +.IP "\fIfile\fR\fB.tcc\fR" 4 +.IX Item "file.tcc" +.PD +\&\*(C+ header file to be turned into a precompiled header or Ada spec. +.IP "\fIfile\fR\fB.f\fR" 4 +.IX Item "file.f" +.PD 0 +.IP "\fIfile\fR\fB.for\fR" 4 +.IX Item "file.for" +.IP "\fIfile\fR\fB.ftn\fR" 4 +.IX Item "file.ftn" +.PD +Fixed form Fortran source code which should not be preprocessed. +.IP "\fIfile\fR\fB.F\fR" 4 +.IX Item "file.F" +.PD 0 +.IP "\fIfile\fR\fB.FOR\fR" 4 +.IX Item "file.FOR" +.IP "\fIfile\fR\fB.fpp\fR" 4 +.IX Item "file.fpp" +.IP "\fIfile\fR\fB.FPP\fR" 4 +.IX Item "file.FPP" +.IP "\fIfile\fR\fB.FTN\fR" 4 +.IX Item "file.FTN" +.PD +Fixed form Fortran source code which must be preprocessed (with the traditional +preprocessor). +.IP "\fIfile\fR\fB.f90\fR" 4 +.IX Item "file.f90" +.PD 0 +.IP "\fIfile\fR\fB.f95\fR" 4 +.IX Item "file.f95" +.IP "\fIfile\fR\fB.f03\fR" 4 +.IX Item "file.f03" +.IP "\fIfile\fR\fB.f08\fR" 4 +.IX Item "file.f08" +.PD +Free form Fortran source code which should not be preprocessed. +.IP "\fIfile\fR\fB.F90\fR" 4 +.IX Item "file.F90" +.PD 0 +.IP "\fIfile\fR\fB.F95\fR" 4 +.IX Item "file.F95" +.IP "\fIfile\fR\fB.F03\fR" 4 +.IX Item "file.F03" +.IP "\fIfile\fR\fB.F08\fR" 4 +.IX Item "file.F08" +.PD +Free form Fortran source code which must be preprocessed (with the +traditional preprocessor). +.IP "\fIfile\fR\fB.go\fR" 4 +.IX Item "file.go" +Go source code. +.IP "\fIfile\fR\fB.ads\fR" 4 +.IX Item "file.ads" +Ada source code file which contains a library unit declaration (a +declaration of a package, subprogram, or generic, or a generic +instantiation), or a library unit renaming declaration (a package, +generic, or subprogram renaming declaration). Such files are also +called \fIspecs\fR. +.IP "\fIfile\fR\fB.adb\fR" 4 +.IX Item "file.adb" +Ada source code file containing a library unit body (a subprogram or +package body). Such files are also called \fIbodies\fR. +.IP "\fIfile\fR\fB.s\fR" 4 +.IX Item "file.s" +Assembler code. +.IP "\fIfile\fR\fB.S\fR" 4 +.IX Item "file.S" +.PD 0 +.IP "\fIfile\fR\fB.sx\fR" 4 +.IX Item "file.sx" +.PD +Assembler code which must be preprocessed. +.IP "\fIother\fR" 4 +.IX Item "other" +An object file to be fed straight into linking. +Any file name with no recognized suffix is treated this way. +.PP +You can specify the input language explicitly with the \fB\-x\fR option: +.IP "\fB\-x\fR \fIlanguage\fR" 4 +.IX Item "-x language" +Specify explicitly the \fIlanguage\fR for the following input files +(rather than letting the compiler choose a default based on the file +name suffix). This option applies to all following input files until +the next \fB\-x\fR option. Possible values for \fIlanguage\fR are: +.Sp +.Vb 9 +\& c c\-header cpp\-output +\& c++ c++\-header c++\-cpp\-output +\& objective\-c objective\-c\-header objective\-c\-cpp\-output +\& objective\-c++ objective\-c++\-header objective\-c++\-cpp\-output +\& assembler assembler\-with\-cpp +\& ada +\& f77 f77\-cpp\-input f95 f95\-cpp\-input +\& go +\& java +.Ve +.IP "\fB\-x none\fR" 4 +.IX Item "-x none" +Turn off any specification of a language, so that subsequent files are +handled according to their file name suffixes (as they are if \fB\-x\fR +has not been used at all). +.IP "\fB\-pass\-exit\-codes\fR" 4 +.IX Item "-pass-exit-codes" +Normally the \fBgcc\fR program will exit with the code of 1 if any +phase of the compiler returns a non-success return code. If you specify +\&\fB\-pass\-exit\-codes\fR, the \fBgcc\fR program will instead return with +numerically highest error produced by any phase that returned an error +indication. The C, \*(C+, and Fortran frontends return 4, if an internal +compiler error is encountered. +.PP +If you only want some of the stages of compilation, you can use +\&\fB\-x\fR (or filename suffixes) to tell \fBgcc\fR where to start, and +one of the options \fB\-c\fR, \fB\-S\fR, or \fB\-E\fR to say where +\&\fBgcc\fR is to stop. Note that some combinations (for example, +\&\fB\-x cpp-output \-E\fR) instruct \fBgcc\fR to do nothing at all. +.IP "\fB\-c\fR" 4 +.IX Item "-c" +Compile or assemble the source files, but do not link. The linking +stage simply is not done. The ultimate output is in the form of an +object file for each source file. +.Sp +By default, the object file name for a source file is made by replacing +the suffix \fB.c\fR, \fB.i\fR, \fB.s\fR, etc., with \fB.o\fR. +.Sp +Unrecognized input files, not requiring compilation or assembly, are +ignored. +.IP "\fB\-S\fR" 4 +.IX Item "-S" +Stop after the stage of compilation proper; do not assemble. The output +is in the form of an assembler code file for each non-assembler input +file specified. +.Sp +By default, the assembler file name for a source file is made by +replacing the suffix \fB.c\fR, \fB.i\fR, etc., with \fB.s\fR. +.Sp +Input files that don't require compilation are ignored. +.IP "\fB\-E\fR" 4 +.IX Item "-E" +Stop after the preprocessing stage; do not run the compiler proper. The +output is in the form of preprocessed source code, which is sent to the +standard output. +.Sp +Input files which don't require preprocessing are ignored. +.IP "\fB\-o\fR \fIfile\fR" 4 +.IX Item "-o file" +Place output in file \fIfile\fR. This applies regardless to whatever +sort of output is being produced, whether it be an executable file, +an object file, an assembler file or preprocessed C code. +.Sp +If \fB\-o\fR is not specified, the default is to put an executable +file in \fIa.out\fR, the object file for +\&\fI\fIsource\fI.\fIsuffix\fI\fR in \fI\fIsource\fI.o\fR, its +assembler file in \fI\fIsource\fI.s\fR, a precompiled header file in +\&\fI\fIsource\fI.\fIsuffix\fI.gch\fR, and all preprocessed C source on +standard output. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +Print (on standard error output) the commands executed to run the stages +of compilation. Also print the version number of the compiler driver +program and of the preprocessor and the compiler proper. +.IP "\fB\-###\fR" 4 +.IX Item "-###" +Like \fB\-v\fR except the commands are not executed and arguments +are quoted unless they contain only alphanumeric characters or \f(CW\*(C`./\-_\*(C'\fR. +This is useful for shell scripts to capture the driver-generated command lines. +.IP "\fB\-pipe\fR" 4 +.IX Item "-pipe" +Use pipes rather than temporary files for communication between the +various stages of compilation. This fails to work on some systems where +the assembler is unable to read from a pipe; but the \s-1GNU\s0 assembler has +no trouble. +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +Print (on the standard output) a description of the command line options +understood by \fBgcc\fR. If the \fB\-v\fR option is also specified +then \fB\-\-help\fR will also be passed on to the various processes +invoked by \fBgcc\fR, so that they can display the command line options +they accept. If the \fB\-Wextra\fR option has also been specified +(prior to the \fB\-\-help\fR option), then command line options which +have no documentation associated with them will also be displayed. +.IP "\fB\-\-target\-help\fR" 4 +.IX Item "--target-help" +Print (on the standard output) a description of target-specific command +line options for each tool. For some targets extra target-specific +information may also be printed. +.IP "\fB\-\-help={\fR\fIclass\fR|[\fB^\fR]\fIqualifier\fR\fB}\fR[\fB,...\fR]" 4 +.IX Item "--help={class|[^]qualifier}[,...]" +Print (on the standard output) a description of the command line +options understood by the compiler that fit into all specified classes +and qualifiers. These are the supported classes: +.RS 4 +.IP "\fBoptimizers\fR" 4 +.IX Item "optimizers" +This will display all of the optimization options supported by the +compiler. +.IP "\fBwarnings\fR" 4 +.IX Item "warnings" +This will display all of the options controlling warning messages +produced by the compiler. +.IP "\fBtarget\fR" 4 +.IX Item "target" +This will display target-specific options. Unlike the +\&\fB\-\-target\-help\fR option however, target-specific options of the +linker and assembler will not be displayed. This is because those +tools do not currently support the extended \fB\-\-help=\fR syntax. +.IP "\fBparams\fR" 4 +.IX Item "params" +This will display the values recognized by the \fB\-\-param\fR +option. +.IP "\fIlanguage\fR" 4 +.IX Item "language" +This will display the options supported for \fIlanguage\fR, where +\&\fIlanguage\fR is the name of one of the languages supported in this +version of \s-1GCC\s0. +.IP "\fBcommon\fR" 4 +.IX Item "common" +This will display the options that are common to all languages. +.RE +.RS 4 +.Sp +These are the supported qualifiers: +.IP "\fBundocumented\fR" 4 +.IX Item "undocumented" +Display only those options which are undocumented. +.IP "\fBjoined\fR" 4 +.IX Item "joined" +Display options which take an argument that appears after an equal +sign in the same continuous piece of text, such as: +\&\fB\-\-help=target\fR. +.IP "\fBseparate\fR" 4 +.IX Item "separate" +Display options which take an argument that appears as a separate word +following the original option, such as: \fB\-o output-file\fR. +.RE +.RS 4 +.Sp +Thus for example to display all the undocumented target-specific +switches supported by the compiler the following can be used: +.Sp +.Vb 1 +\& \-\-help=target,undocumented +.Ve +.Sp +The sense of a qualifier can be inverted by prefixing it with the +\&\fB^\fR character, so for example to display all binary warning +options (i.e., ones that are either on or off and that do not take an +argument), which have a description the following can be used: +.Sp +.Vb 1 +\& \-\-help=warnings,^joined,^undocumented +.Ve +.Sp +The argument to \fB\-\-help=\fR should not consist solely of inverted +qualifiers. +.Sp +Combining several classes is possible, although this usually +restricts the output by so much that there is nothing to display. One +case where it does work however is when one of the classes is +\&\fItarget\fR. So for example to display all the target-specific +optimization options the following can be used: +.Sp +.Vb 1 +\& \-\-help=target,optimizers +.Ve +.Sp +The \fB\-\-help=\fR option can be repeated on the command line. Each +successive use will display its requested class of options, skipping +those that have already been displayed. +.Sp +If the \fB\-Q\fR option appears on the command line before the +\&\fB\-\-help=\fR option, then the descriptive text displayed by +\&\fB\-\-help=\fR is changed. Instead of describing the displayed +options, an indication is given as to whether the option is enabled, +disabled or set to a specific value (assuming that the compiler +knows this at the point where the \fB\-\-help=\fR option is used). +.Sp +Here is a truncated example from the \s-1ARM\s0 port of \fBgcc\fR: +.Sp +.Vb 5 +\& % gcc \-Q \-mabi=2 \-\-help=target \-c +\& The following options are target specific: +\& \-mabi= 2 +\& \-mabort\-on\-noreturn [disabled] +\& \-mapcs [disabled] +.Ve +.Sp +The output is sensitive to the effects of previous command line +options, so for example it is possible to find out which optimizations +are enabled at \fB\-O2\fR by using: +.Sp +.Vb 1 +\& \-Q \-O2 \-\-help=optimizers +.Ve +.Sp +Alternatively you can discover which binary optimizations are enabled +by \fB\-O3\fR by using: +.Sp +.Vb 3 +\& gcc \-c \-Q \-O3 \-\-help=optimizers > /tmp/O3\-opts +\& gcc \-c \-Q \-O2 \-\-help=optimizers > /tmp/O2\-opts +\& diff /tmp/O2\-opts /tmp/O3\-opts | grep enabled +.Ve +.RE +.IP "\fB\-canonical\-prefixes\fR" 4 +.IX Item "-canonical-prefixes" +Always expand any symbolic links, resolve references to \fB/../\fR +or \fB/./\fR, and make the path absolute when generating a relative +prefix. +.IP "\fB\-no\-canonical\-prefixes\fR" 4 +.IX Item "-no-canonical-prefixes" +Never expand any symbolic links, resolve references to \fB/../\fR +or \fB/./\fR, or make the path absolute when generating a relative +prefix. If neither \fB\-canonical\-prefixes\fR nor +\&\fB\-nocanonical\-prefixes\fR is given, \s-1GCC\s0 tries to set an appropriate +default by looking for a target-specific subdirectory alongside the +directory containing the compiler driver. +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +Display the version number and copyrights of the invoked \s-1GCC\s0. +.IP "\fB\-wrapper\fR" 4 +.IX Item "-wrapper" +Invoke all subcommands under a wrapper program. The name of the +wrapper program and its parameters are passed as a comma separated +list. +.Sp +.Vb 1 +\& gcc \-c t.c \-wrapper gdb,\-\-args +.Ve +.Sp +This will invoke all subprograms of \fBgcc\fR under +\&\fBgdb \-\-args\fR, thus the invocation of \fBcc1\fR will be +\&\fBgdb \-\-args cc1 ...\fR. +.IP "\fB\-fplugin=\fR\fIname\fR\fB.so\fR" 4 +.IX Item "-fplugin=name.so" +Load the plugin code in file \fIname\fR.so, assumed to be a +shared object to be dlopen'd by the compiler. The base name of +the shared object file is used to identify the plugin for the +purposes of argument parsing (See +\&\fB\-fplugin\-arg\-\fR\fIname\fR\fB\-\fR\fIkey\fR\fB=\fR\fIvalue\fR below). +Each plugin should define the callback functions specified in the +Plugins \s-1API\s0. +.IP "\fB\-fplugin\-arg\-\fR\fIname\fR\fB\-\fR\fIkey\fR\fB=\fR\fIvalue\fR" 4 +.IX Item "-fplugin-arg-name-key=value" +Define an argument called \fIkey\fR with a value of \fIvalue\fR +for the plugin called \fIname\fR. +.IP "\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR]" 4 +.IX Item "-fdump-ada-spec[-slim]" +For C and \*(C+ source and include files, generate corresponding Ada +specs. +.IP "\fB\-fdump\-go\-spec=\fR\fIfile\fR" 4 +.IX Item "-fdump-go-spec=file" +For input files in any language, generate corresponding Go +declarations in \fIfile\fR. This generates Go \f(CW\*(C`const\*(C'\fR, +\&\f(CW\*(C`type\*(C'\fR, \f(CW\*(C`var\*(C'\fR, and \f(CW\*(C`func\*(C'\fR declarations which may be a +useful way to start writing a Go interface to code written in some +other language. +.IP "\fB@\fR\fIfile\fR" 4 +.IX Item "@file" +Read command-line options from \fIfile\fR. The options read are +inserted in place of the original @\fIfile\fR option. If \fIfile\fR +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +.Sp +Options in \fIfile\fR are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The \fIfile\fR may itself contain additional +@\fIfile\fR options; any such options will be processed recursively. +.SS "Compiling \*(C+ Programs" +.IX Subsection "Compiling Programs" +\&\*(C+ source files conventionally use one of the suffixes \fB.C\fR, +\&\fB.cc\fR, \fB.cpp\fR, \fB.CPP\fR, \fB.c++\fR, \fB.cp\fR, or +\&\fB.cxx\fR; \*(C+ header files often use \fB.hh\fR, \fB.hpp\fR, +\&\fB.H\fR, or (for shared template code) \fB.tcc\fR; and +preprocessed \*(C+ files use the suffix \fB.ii\fR. \s-1GCC\s0 recognizes +files with these names and compiles them as \*(C+ programs even if you +call the compiler the same way as for compiling C programs (usually +with the name \fBgcc\fR). +.PP +However, the use of \fBgcc\fR does not add the \*(C+ library. +\&\fBg++\fR is a program that calls \s-1GCC\s0 and treats \fB.c\fR, +\&\fB.h\fR and \fB.i\fR files as \*(C+ source files instead of C source +files unless \fB\-x\fR is used, and automatically specifies linking +against the \*(C+ library. This program is also useful when +precompiling a C header file with a \fB.h\fR extension for use in \*(C+ +compilations. On many systems, \fBg++\fR is also installed with +the name \fBc++\fR. +.PP +When you compile \*(C+ programs, you may specify many of the same +command-line options that you use for compiling programs in any +language; or command-line options meaningful for C and related +languages; or options that are meaningful only for \*(C+ programs. +.SS "Options Controlling C Dialect" +.IX Subsection "Options Controlling C Dialect" +The following options control the dialect of C (or languages derived +from C, such as \*(C+, Objective-C and Objective\-\*(C+) that the compiler +accepts: +.IP "\fB\-ansi\fR" 4 +.IX Item "-ansi" +In C mode, this is equivalent to \fB\-std=c90\fR. In \*(C+ mode, it is +equivalent to \fB\-std=c++98\fR. +.Sp +This turns off certain features of \s-1GCC\s0 that are incompatible with \s-1ISO\s0 +C90 (when compiling C code), or of standard \*(C+ (when compiling \*(C+ code), +such as the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR keywords, and +predefined macros such as \f(CW\*(C`unix\*(C'\fR and \f(CW\*(C`vax\*(C'\fR that identify the +type of system you are using. It also enables the undesirable and +rarely used \s-1ISO\s0 trigraph feature. For the C compiler, +it disables recognition of \*(C+ style \fB//\fR comments as well as +the \f(CW\*(C`inline\*(C'\fR keyword. +.Sp +The alternate keywords \f(CW\*(C`_\|_asm_\|_\*(C'\fR, \f(CW\*(C`_\|_extension_\|_\*(C'\fR, +\&\f(CW\*(C`_\|_inline_\|_\*(C'\fR and \f(CW\*(C`_\|_typeof_\|_\*(C'\fR continue to work despite +\&\fB\-ansi\fR. You would not want to use them in an \s-1ISO\s0 C program, of +course, but it is useful to put them in header files that might be included +in compilations done with \fB\-ansi\fR. Alternate predefined macros +such as \f(CW\*(C`_\|_unix_\|_\*(C'\fR and \f(CW\*(C`_\|_vax_\|_\*(C'\fR are also available, with or +without \fB\-ansi\fR. +.Sp +The \fB\-ansi\fR option does not cause non-ISO programs to be +rejected gratuitously. For that, \fB\-pedantic\fR is required in +addition to \fB\-ansi\fR. +.Sp +The macro \f(CW\*(C`_\|_STRICT_ANSI_\|_\*(C'\fR is predefined when the \fB\-ansi\fR +option is used. Some header files may notice this macro and refrain +from declaring certain functions or defining certain macros that the +\&\s-1ISO\s0 standard doesn't call for; this is to avoid interfering with any +programs that might use these names for other things. +.Sp +Functions that would normally be built in but do not have semantics +defined by \s-1ISO\s0 C (such as \f(CW\*(C`alloca\*(C'\fR and \f(CW\*(C`ffs\*(C'\fR) are not built-in +functions when \fB\-ansi\fR is used. +.IP "\fB\-std=\fR" 4 +.IX Item "-std=" +Determine the language standard. This option +is currently only supported when compiling C or \*(C+. +.Sp +The compiler can accept several base standards, such as \fBc90\fR or +\&\fBc++98\fR, and \s-1GNU\s0 dialects of those standards, such as +\&\fBgnu90\fR or \fBgnu++98\fR. By specifying a base standard, the +compiler will accept all programs following that standard and those +using \s-1GNU\s0 extensions that do not contradict it. For example, +\&\fB\-std=c90\fR turns off certain features of \s-1GCC\s0 that are +incompatible with \s-1ISO\s0 C90, such as the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR +keywords, but not other \s-1GNU\s0 extensions that do not have a meaning in +\&\s-1ISO\s0 C90, such as omitting the middle term of a \f(CW\*(C`?:\*(C'\fR +expression. On the other hand, by specifying a \s-1GNU\s0 dialect of a +standard, all features the compiler support are enabled, even when +those features change the meaning of the base standard and some +strict-conforming programs may be rejected. The particular standard +is used by \fB\-pedantic\fR to identify which features are \s-1GNU\s0 +extensions given that version of the standard. For example +\&\fB\-std=gnu90 \-pedantic\fR would warn about \*(C+ style \fB//\fR +comments, while \fB\-std=gnu99 \-pedantic\fR would not. +.Sp +A value for this option must be provided; possible values are +.RS 4 +.IP "\fBc90\fR" 4 +.IX Item "c90" +.PD 0 +.IP "\fBc89\fR" 4 +.IX Item "c89" +.IP "\fBiso9899:1990\fR" 4 +.IX Item "iso9899:1990" +.PD +Support all \s-1ISO\s0 C90 programs (certain \s-1GNU\s0 extensions that conflict +with \s-1ISO\s0 C90 are disabled). Same as \fB\-ansi\fR for C code. +.IP "\fBiso9899:199409\fR" 4 +.IX Item "iso9899:199409" +\&\s-1ISO\s0 C90 as modified in amendment 1. +.IP "\fBc99\fR" 4 +.IX Item "c99" +.PD 0 +.IP "\fBc9x\fR" 4 +.IX Item "c9x" +.IP "\fBiso9899:1999\fR" 4 +.IX Item "iso9899:1999" +.IP "\fBiso9899:199x\fR" 4 +.IX Item "iso9899:199x" +.PD +\&\s-1ISO\s0 C99. Note that this standard is not yet fully supported; see +<\fBhttp://gcc.gnu.org/gcc\-4.6/c99status.html\fR> for more information. The +names \fBc9x\fR and \fBiso9899:199x\fR are deprecated. +.IP "\fBc1x\fR" 4 +.IX Item "c1x" +\&\s-1ISO\s0 C1X, the draft of the next revision of the \s-1ISO\s0 C standard. +Support is limited and experimental and features enabled by this +option may be changed or removed if changed in or removed from the +standard draft. +.IP "\fBgnu90\fR" 4 +.IX Item "gnu90" +.PD 0 +.IP "\fBgnu89\fR" 4 +.IX Item "gnu89" +.PD +\&\s-1GNU\s0 dialect of \s-1ISO\s0 C90 (including some C99 features). This +is the default for C code. +.IP "\fBgnu99\fR" 4 +.IX Item "gnu99" +.PD 0 +.IP "\fBgnu9x\fR" 4 +.IX Item "gnu9x" +.PD +\&\s-1GNU\s0 dialect of \s-1ISO\s0 C99. When \s-1ISO\s0 C99 is fully implemented in \s-1GCC\s0, +this will become the default. The name \fBgnu9x\fR is deprecated. +.IP "\fBgnu1x\fR" 4 +.IX Item "gnu1x" +\&\s-1GNU\s0 dialect of \s-1ISO\s0 C1X. Support is limited and experimental and +features enabled by this option may be changed or removed if changed +in or removed from the standard draft. +.IP "\fBc++98\fR" 4 +.IX Item "c++98" +The 1998 \s-1ISO\s0 \*(C+ standard plus amendments. Same as \fB\-ansi\fR for +\&\*(C+ code. +.IP "\fBgnu++98\fR" 4 +.IX Item "gnu++98" +\&\s-1GNU\s0 dialect of \fB\-std=c++98\fR. This is the default for +\&\*(C+ code. +.IP "\fBc++0x\fR" 4 +.IX Item "c++0x" +The working draft of the upcoming \s-1ISO\s0 \*(C+0x standard. This option +enables experimental features that are likely to be included in +\&\*(C+0x. The working draft is constantly changing, and any feature that is +enabled by this flag may be removed from future versions of \s-1GCC\s0 if it is +not part of the \*(C+0x standard. +.IP "\fBgnu++0x\fR" 4 +.IX Item "gnu++0x" +\&\s-1GNU\s0 dialect of \fB\-std=c++0x\fR. This option enables +experimental features that may be removed in future versions of \s-1GCC\s0. +.RE +.RS 4 +.RE +.IP "\fB\-fgnu89\-inline\fR" 4 +.IX Item "-fgnu89-inline" +The option \fB\-fgnu89\-inline\fR tells \s-1GCC\s0 to use the traditional +\&\s-1GNU\s0 semantics for \f(CW\*(C`inline\*(C'\fR functions when in C99 mode. + This option +is accepted and ignored by \s-1GCC\s0 versions 4.1.3 up to but not including +4.3. In \s-1GCC\s0 versions 4.3 and later it changes the behavior of \s-1GCC\s0 in +C99 mode. Using this option is roughly equivalent to adding the +\&\f(CW\*(C`gnu_inline\*(C'\fR function attribute to all inline functions. +.Sp +The option \fB\-fno\-gnu89\-inline\fR explicitly tells \s-1GCC\s0 to use the +C99 semantics for \f(CW\*(C`inline\*(C'\fR when in C99 or gnu99 mode (i.e., it +specifies the default behavior). This option was first supported in +\&\s-1GCC\s0 4.3. This option is not supported in \fB\-std=c90\fR or +\&\fB\-std=gnu90\fR mode. +.Sp +The preprocessor macros \f(CW\*(C`_\|_GNUC_GNU_INLINE_\|_\*(C'\fR and +\&\f(CW\*(C`_\|_GNUC_STDC_INLINE_\|_\*(C'\fR may be used to check which semantics are +in effect for \f(CW\*(C`inline\*(C'\fR functions. +.IP "\fB\-aux\-info\fR \fIfilename\fR" 4 +.IX Item "-aux-info filename" +Output to the given filename prototyped declarations for all functions +declared and/or defined in a translation unit, including those in header +files. This option is silently ignored in any language other than C. +.Sp +Besides declarations, the file indicates, in comments, the origin of +each declaration (source file and line), whether the declaration was +implicit, prototyped or unprototyped (\fBI\fR, \fBN\fR for new or +\&\fBO\fR for old, respectively, in the first character after the line +number and the colon), and whether it came from a declaration or a +definition (\fBC\fR or \fBF\fR, respectively, in the following +character). In the case of function definitions, a K&R\-style list of +arguments followed by their declarations is also provided, inside +comments, after the declaration. +.IP "\fB\-fno\-asm\fR" 4 +.IX Item "-fno-asm" +Do not recognize \f(CW\*(C`asm\*(C'\fR, \f(CW\*(C`inline\*(C'\fR or \f(CW\*(C`typeof\*(C'\fR as a +keyword, so that code can use these words as identifiers. You can use +the keywords \f(CW\*(C`_\|_asm_\|_\*(C'\fR, \f(CW\*(C`_\|_inline_\|_\*(C'\fR and \f(CW\*(C`_\|_typeof_\|_\*(C'\fR +instead. \fB\-ansi\fR implies \fB\-fno\-asm\fR. +.Sp +In \*(C+, this switch only affects the \f(CW\*(C`typeof\*(C'\fR keyword, since +\&\f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`inline\*(C'\fR are standard keywords. You may want to +use the \fB\-fno\-gnu\-keywords\fR flag instead, which has the same +effect. In C99 mode (\fB\-std=c99\fR or \fB\-std=gnu99\fR), this +switch only affects the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR keywords, since +\&\f(CW\*(C`inline\*(C'\fR is a standard keyword in \s-1ISO\s0 C99. +.IP "\fB\-fno\-builtin\fR" 4 +.IX Item "-fno-builtin" +.PD 0 +.IP "\fB\-fno\-builtin\-\fR\fIfunction\fR" 4 +.IX Item "-fno-builtin-function" +.PD +Don't recognize built-in functions that do not begin with +\&\fB_\|_builtin_\fR as prefix. +.Sp +\&\s-1GCC\s0 normally generates special code to handle certain built-in functions +more efficiently; for instance, calls to \f(CW\*(C`alloca\*(C'\fR may become single +instructions that adjust the stack directly, and calls to \f(CW\*(C`memcpy\*(C'\fR +may become inline copy loops. The resulting code is often both smaller +and faster, but since the function calls no longer appear as such, you +cannot set a breakpoint on those calls, nor can you change the behavior +of the functions by linking with a different library. In addition, +when a function is recognized as a built-in function, \s-1GCC\s0 may use +information about that function to warn about problems with calls to +that function, or to generate more efficient code, even if the +resulting code still contains calls to that function. For example, +warnings are given with \fB\-Wformat\fR for bad calls to +\&\f(CW\*(C`printf\*(C'\fR, when \f(CW\*(C`printf\*(C'\fR is built in, and \f(CW\*(C`strlen\*(C'\fR is +known not to modify global memory. +.Sp +With the \fB\-fno\-builtin\-\fR\fIfunction\fR option +only the built-in function \fIfunction\fR is +disabled. \fIfunction\fR must not begin with \fB_\|_builtin_\fR. If a +function is named that is not built-in in this version of \s-1GCC\s0, this +option is ignored. There is no corresponding +\&\fB\-fbuiltin\-\fR\fIfunction\fR option; if you wish to enable +built-in functions selectively when using \fB\-fno\-builtin\fR or +\&\fB\-ffreestanding\fR, you may define macros such as: +.Sp +.Vb 2 +\& #define abs(n) _\|_builtin_abs ((n)) +\& #define strcpy(d, s) _\|_builtin_strcpy ((d), (s)) +.Ve +.IP "\fB\-fhosted\fR" 4 +.IX Item "-fhosted" +Assert that compilation takes place in a hosted environment. This implies +\&\fB\-fbuiltin\fR. A hosted environment is one in which the +entire standard library is available, and in which \f(CW\*(C`main\*(C'\fR has a return +type of \f(CW\*(C`int\*(C'\fR. Examples are nearly everything except a kernel. +This is equivalent to \fB\-fno\-freestanding\fR. +.IP "\fB\-ffreestanding\fR" 4 +.IX Item "-ffreestanding" +Assert that compilation takes place in a freestanding environment. This +implies \fB\-fno\-builtin\fR. A freestanding environment +is one in which the standard library may not exist, and program startup may +not necessarily be at \f(CW\*(C`main\*(C'\fR. The most obvious example is an \s-1OS\s0 kernel. +This is equivalent to \fB\-fno\-hosted\fR. +.IP "\fB\-fopenmp\fR" 4 +.IX Item "-fopenmp" +Enable handling of OpenMP directives \f(CW\*(C`#pragma omp\*(C'\fR in C/\*(C+ and +\&\f(CW\*(C`!$omp\*(C'\fR in Fortran. When \fB\-fopenmp\fR is specified, the +compiler generates parallel code according to the OpenMP Application +Program Interface v3.0 <\fBhttp://www.openmp.org/\fR>. This option +implies \fB\-pthread\fR, and thus is only supported on targets that +have support for \fB\-pthread\fR. +.IP "\fB\-fms\-extensions\fR" 4 +.IX Item "-fms-extensions" +Accept some non-standard constructs used in Microsoft header files. +.Sp +In \*(C+ code, this allows member names in structures to be similar +to previous types declarations. +.Sp +.Vb 4 +\& typedef int UOW; +\& struct ABC { +\& UOW UOW; +\& }; +.Ve +.Sp +Some cases of unnamed fields in structures and unions are only +accepted with this option. +.IP "\fB\-fplan9\-extensions\fR" 4 +.IX Item "-fplan9-extensions" +Accept some non-standard constructs used in Plan 9 code. +.Sp +This enables \fB\-fms\-extensions\fR, permits passing pointers to +structures with anonymous fields to functions which expect pointers to +elements of the type of the field, and permits referring to anonymous +fields declared using a typedef. This is only +supported for C, not \*(C+. +.IP "\fB\-trigraphs\fR" 4 +.IX Item "-trigraphs" +Support \s-1ISO\s0 C trigraphs. The \fB\-ansi\fR option (and \fB\-std\fR +options for strict \s-1ISO\s0 C conformance) implies \fB\-trigraphs\fR. +.IP "\fB\-no\-integrated\-cpp\fR" 4 +.IX Item "-no-integrated-cpp" +Performs a compilation in two passes: preprocessing and compiling. This +option allows a user supplied \*(L"cc1\*(R", \*(L"cc1plus\*(R", or \*(L"cc1obj\*(R" via the +\&\fB\-B\fR option. The user supplied compilation step can then add in +an additional preprocessing step after normal preprocessing but before +compiling. The default is to use the integrated cpp (internal cpp) +.Sp +The semantics of this option will change if \*(L"cc1\*(R", \*(L"cc1plus\*(R", and +\&\*(L"cc1obj\*(R" are merged. +.IP "\fB\-traditional\fR" 4 +.IX Item "-traditional" +.PD 0 +.IP "\fB\-traditional\-cpp\fR" 4 +.IX Item "-traditional-cpp" +.PD +Formerly, these options caused \s-1GCC\s0 to attempt to emulate a pre-standard +C compiler. They are now only supported with the \fB\-E\fR switch. +The preprocessor continues to support a pre-standard mode. See the \s-1GNU\s0 +\&\s-1CPP\s0 manual for details. +.IP "\fB\-fcond\-mismatch\fR" 4 +.IX Item "-fcond-mismatch" +Allow conditional expressions with mismatched types in the second and +third arguments. The value of such an expression is void. This option +is not supported for \*(C+. +.IP "\fB\-flax\-vector\-conversions\fR" 4 +.IX Item "-flax-vector-conversions" +Allow implicit conversions between vectors with differing numbers of +elements and/or incompatible element types. This option should not be +used for new code. +.IP "\fB\-funsigned\-char\fR" 4 +.IX Item "-funsigned-char" +Let the type \f(CW\*(C`char\*(C'\fR be unsigned, like \f(CW\*(C`unsigned char\*(C'\fR. +.Sp +Each kind of machine has a default for what \f(CW\*(C`char\*(C'\fR should +be. It is either like \f(CW\*(C`unsigned char\*(C'\fR by default or like +\&\f(CW\*(C`signed char\*(C'\fR by default. +.Sp +Ideally, a portable program should always use \f(CW\*(C`signed char\*(C'\fR or +\&\f(CW\*(C`unsigned char\*(C'\fR when it depends on the signedness of an object. +But many programs have been written to use plain \f(CW\*(C`char\*(C'\fR and +expect it to be signed, or expect it to be unsigned, depending on the +machines they were written for. This option, and its inverse, let you +make such a program work with the opposite default. +.Sp +The type \f(CW\*(C`char\*(C'\fR is always a distinct type from each of +\&\f(CW\*(C`signed char\*(C'\fR or \f(CW\*(C`unsigned char\*(C'\fR, even though its behavior +is always just like one of those two. +.IP "\fB\-fsigned\-char\fR" 4 +.IX Item "-fsigned-char" +Let the type \f(CW\*(C`char\*(C'\fR be signed, like \f(CW\*(C`signed char\*(C'\fR. +.Sp +Note that this is equivalent to \fB\-fno\-unsigned\-char\fR, which is +the negative form of \fB\-funsigned\-char\fR. Likewise, the option +\&\fB\-fno\-signed\-char\fR is equivalent to \fB\-funsigned\-char\fR. +.IP "\fB\-fsigned\-bitfields\fR" 4 +.IX Item "-fsigned-bitfields" +.PD 0 +.IP "\fB\-funsigned\-bitfields\fR" 4 +.IX Item "-funsigned-bitfields" +.IP "\fB\-fno\-signed\-bitfields\fR" 4 +.IX Item "-fno-signed-bitfields" +.IP "\fB\-fno\-unsigned\-bitfields\fR" 4 +.IX Item "-fno-unsigned-bitfields" +.PD +These options control whether a bit-field is signed or unsigned, when the +declaration does not use either \f(CW\*(C`signed\*(C'\fR or \f(CW\*(C`unsigned\*(C'\fR. By +default, such a bit-field is signed, because this is consistent: the +basic integer types such as \f(CW\*(C`int\*(C'\fR are signed types. +.SS "Options Controlling \*(C+ Dialect" +.IX Subsection "Options Controlling Dialect" +This section describes the command-line options that are only meaningful +for \*(C+ programs; but you can also use most of the \s-1GNU\s0 compiler options +regardless of what language your program is in. For example, you +might compile a file \f(CW\*(C`firstClass.C\*(C'\fR like this: +.PP +.Vb 1 +\& g++ \-g \-frepo \-O \-c firstClass.C +.Ve +.PP +In this example, only \fB\-frepo\fR is an option meant +only for \*(C+ programs; you can use the other options with any +language supported by \s-1GCC\s0. +.PP +Here is a list of options that are \fIonly\fR for compiling \*(C+ programs: +.IP "\fB\-fabi\-version=\fR\fIn\fR" 4 +.IX Item "-fabi-version=n" +Use version \fIn\fR of the \*(C+ \s-1ABI\s0. Version 2 is the version of the +\&\*(C+ \s-1ABI\s0 that first appeared in G++ 3.4. Version 1 is the version of +the \*(C+ \s-1ABI\s0 that first appeared in G++ 3.2. Version 0 will always be +the version that conforms most closely to the \*(C+ \s-1ABI\s0 specification. +Therefore, the \s-1ABI\s0 obtained using version 0 will change as \s-1ABI\s0 bugs +are fixed. +.Sp +The default is version 2. +.Sp +Version 3 corrects an error in mangling a constant address as a +template argument. +.Sp +Version 4 implements a standard mangling for vector types. +.Sp +Version 5 corrects the mangling of attribute const/volatile on +function pointer types, decltype of a plain decl, and use of a +function parameter in the declaration of another parameter. +.Sp +See also \fB\-Wabi\fR. +.IP "\fB\-fno\-access\-control\fR" 4 +.IX Item "-fno-access-control" +Turn off all access checking. This switch is mainly useful for working +around bugs in the access control code. +.IP "\fB\-fcheck\-new\fR" 4 +.IX Item "-fcheck-new" +Check that the pointer returned by \f(CW\*(C`operator new\*(C'\fR is non-null +before attempting to modify the storage allocated. This check is +normally unnecessary because the \*(C+ standard specifies that +\&\f(CW\*(C`operator new\*(C'\fR will only return \f(CW0\fR if it is declared +\&\fB\f(BIthrow()\fB\fR, in which case the compiler will always check the +return value even without this option. In all other cases, when +\&\f(CW\*(C`operator new\*(C'\fR has a non-empty exception specification, memory +exhaustion is signalled by throwing \f(CW\*(C`std::bad_alloc\*(C'\fR. See also +\&\fBnew (nothrow)\fR. +.IP "\fB\-fconserve\-space\fR" 4 +.IX Item "-fconserve-space" +Put uninitialized or runtime-initialized global variables into the +common segment, as C does. This saves space in the executable at the +cost of not diagnosing duplicate definitions. If you compile with this +flag and your program mysteriously crashes after \f(CW\*(C`main()\*(C'\fR has +completed, you may have an object that is being destroyed twice because +two definitions were merged. +.Sp +This option is no longer useful on most targets, now that support has +been added for putting variables into \s-1BSS\s0 without making them common. +.IP "\fB\-fconstexpr\-depth=\fR\fIn\fR" 4 +.IX Item "-fconstexpr-depth=n" +Set the maximum nested evaluation depth for \*(C+0x constexpr functions +to \fIn\fR. A limit is needed to detect endless recursion during +constant expression evaluation. The minimum specified by the standard +is 512. +.IP "\fB\-fno\-deduce\-init\-list\fR" 4 +.IX Item "-fno-deduce-init-list" +Disable deduction of a template type parameter as +std::initializer_list from a brace-enclosed initializer list, i.e. +.Sp +.Vb 4 +\& template <class T> auto forward(T t) \-> decltype (realfn (t)) +\& { +\& return realfn (t); +\& } +\& +\& void f() +\& { +\& forward({1,2}); // call forward<std::initializer_list<int>> +\& } +.Ve +.Sp +This option is present because this deduction is an extension to the +current specification in the \*(C+0x working draft, and there was +some concern about potential overload resolution problems. +.IP "\fB\-ffriend\-injection\fR" 4 +.IX Item "-ffriend-injection" +Inject friend functions into the enclosing namespace, so that they are +visible outside the scope of the class in which they are declared. +Friend functions were documented to work this way in the old Annotated +\&\*(C+ Reference Manual, and versions of G++ before 4.1 always worked +that way. However, in \s-1ISO\s0 \*(C+ a friend function which is not declared +in an enclosing scope can only be found using argument dependent +lookup. This option causes friends to be injected as they were in +earlier releases. +.Sp +This option is for compatibility, and may be removed in a future +release of G++. +.IP "\fB\-fno\-elide\-constructors\fR" 4 +.IX Item "-fno-elide-constructors" +The \*(C+ standard allows an implementation to omit creating a temporary +which is only used to initialize another object of the same type. +Specifying this option disables that optimization, and forces G++ to +call the copy constructor in all cases. +.IP "\fB\-fno\-enforce\-eh\-specs\fR" 4 +.IX Item "-fno-enforce-eh-specs" +Don't generate code to check for violation of exception specifications +at runtime. This option violates the \*(C+ standard, but may be useful +for reducing code size in production builds, much like defining +\&\fB\s-1NDEBUG\s0\fR. This does not give user code permission to throw +exceptions in violation of the exception specifications; the compiler +will still optimize based on the specifications, so throwing an +unexpected exception will result in undefined behavior. +.IP "\fB\-ffor\-scope\fR" 4 +.IX Item "-ffor-scope" +.PD 0 +.IP "\fB\-fno\-for\-scope\fR" 4 +.IX Item "-fno-for-scope" +.PD +If \fB\-ffor\-scope\fR is specified, the scope of variables declared in +a \fIfor-init-statement\fR is limited to the \fBfor\fR loop itself, +as specified by the \*(C+ standard. +If \fB\-fno\-for\-scope\fR is specified, the scope of variables declared in +a \fIfor-init-statement\fR extends to the end of the enclosing scope, +as was the case in old versions of G++, and other (traditional) +implementations of \*(C+. +.Sp +The default if neither flag is given to follow the standard, +but to allow and give a warning for old-style code that would +otherwise be invalid, or have different behavior. +.IP "\fB\-fno\-gnu\-keywords\fR" 4 +.IX Item "-fno-gnu-keywords" +Do not recognize \f(CW\*(C`typeof\*(C'\fR as a keyword, so that code can use this +word as an identifier. You can use the keyword \f(CW\*(C`_\|_typeof_\|_\*(C'\fR instead. +\&\fB\-ansi\fR implies \fB\-fno\-gnu\-keywords\fR. +.IP "\fB\-fno\-implicit\-templates\fR" 4 +.IX Item "-fno-implicit-templates" +Never emit code for non-inline templates which are instantiated +implicitly (i.e. by use); only emit code for explicit instantiations. +.IP "\fB\-fno\-implicit\-inline\-templates\fR" 4 +.IX Item "-fno-implicit-inline-templates" +Don't emit code for implicit instantiations of inline templates, either. +The default is to handle inlines differently so that compiles with and +without optimization will need the same set of explicit instantiations. +.IP "\fB\-fno\-implement\-inlines\fR" 4 +.IX Item "-fno-implement-inlines" +To save space, do not emit out-of-line copies of inline functions +controlled by \fB#pragma implementation\fR. This will cause linker +errors if these functions are not inlined everywhere they are called. +.IP "\fB\-fms\-extensions\fR" 4 +.IX Item "-fms-extensions" +Disable pedantic warnings about constructs used in \s-1MFC\s0, such as implicit +int and getting a pointer to member function via non-standard syntax. +.IP "\fB\-fno\-nonansi\-builtins\fR" 4 +.IX Item "-fno-nonansi-builtins" +Disable built-in declarations of functions that are not mandated by +\&\s-1ANSI/ISO\s0 C. These include \f(CW\*(C`ffs\*(C'\fR, \f(CW\*(C`alloca\*(C'\fR, \f(CW\*(C`_exit\*(C'\fR, +\&\f(CW\*(C`index\*(C'\fR, \f(CW\*(C`bzero\*(C'\fR, \f(CW\*(C`conjf\*(C'\fR, and other related functions. +.IP "\fB\-fnothrow\-opt\fR" 4 +.IX Item "-fnothrow-opt" +Treat a \f(CW\*(C`throw()\*(C'\fR exception specification as though it were a +\&\f(CW\*(C`noexcept\*(C'\fR specification to reduce or eliminate the text size +overhead relative to a function with no exception specification. If +the function has local variables of types with non-trivial +destructors, the exception specification will actually make the +function smaller because the \s-1EH\s0 cleanups for those variables can be +optimized away. The semantic effect is that an exception thrown out of +a function with such an exception specification will result in a call +to \f(CW\*(C`terminate\*(C'\fR rather than \f(CW\*(C`unexpected\*(C'\fR. +.IP "\fB\-fno\-operator\-names\fR" 4 +.IX Item "-fno-operator-names" +Do not treat the operator name keywords \f(CW\*(C`and\*(C'\fR, \f(CW\*(C`bitand\*(C'\fR, +\&\f(CW\*(C`bitor\*(C'\fR, \f(CW\*(C`compl\*(C'\fR, \f(CW\*(C`not\*(C'\fR, \f(CW\*(C`or\*(C'\fR and \f(CW\*(C`xor\*(C'\fR as +synonyms as keywords. +.IP "\fB\-fno\-optional\-diags\fR" 4 +.IX Item "-fno-optional-diags" +Disable diagnostics that the standard says a compiler does not need to +issue. Currently, the only such diagnostic issued by G++ is the one for +a name having multiple meanings within a class. +.IP "\fB\-fpermissive\fR" 4 +.IX Item "-fpermissive" +Downgrade some diagnostics about nonconformant code from errors to +warnings. Thus, using \fB\-fpermissive\fR will allow some +nonconforming code to compile. +.IP "\fB\-fno\-pretty\-templates\fR" 4 +.IX Item "-fno-pretty-templates" +When an error message refers to a specialization of a function +template, the compiler will normally print the signature of the +template followed by the template arguments and any typedefs or +typenames in the signature (e.g. \f(CW\*(C`void f(T) [with T = int]\*(C'\fR +rather than \f(CW\*(C`void f(int)\*(C'\fR) so that it's clear which template is +involved. When an error message refers to a specialization of a class +template, the compiler will omit any template arguments which match +the default template arguments for that template. If either of these +behaviors make it harder to understand the error message rather than +easier, using \fB\-fno\-pretty\-templates\fR will disable them. +.IP "\fB\-frepo\fR" 4 +.IX Item "-frepo" +Enable automatic template instantiation at link time. This option also +implies \fB\-fno\-implicit\-templates\fR. +.IP "\fB\-fno\-rtti\fR" 4 +.IX Item "-fno-rtti" +Disable generation of information about every class with virtual +functions for use by the \*(C+ runtime type identification features +(\fBdynamic_cast\fR and \fBtypeid\fR). If you don't use those parts +of the language, you can save some space by using this flag. Note that +exception handling uses the same information, but it will generate it as +needed. The \fBdynamic_cast\fR operator can still be used for casts that +do not require runtime type information, i.e. casts to \f(CW\*(C`void *\*(C'\fR or to +unambiguous base classes. +.IP "\fB\-fstats\fR" 4 +.IX Item "-fstats" +Emit statistics about front-end processing at the end of the compilation. +This information is generally only useful to the G++ development team. +.IP "\fB\-fstrict\-enums\fR" 4 +.IX Item "-fstrict-enums" +Allow the compiler to optimize using the assumption that a value of +enumeration type can only be one of the values of the enumeration (as +defined in the \*(C+ standard; basically, a value which can be +represented in the minimum number of bits needed to represent all the +enumerators). This assumption may not be valid if the program uses a +cast to convert an arbitrary integer value to the enumeration type. +.IP "\fB\-ftemplate\-depth=\fR\fIn\fR" 4 +.IX Item "-ftemplate-depth=n" +Set the maximum instantiation depth for template classes to \fIn\fR. +A limit on the template instantiation depth is needed to detect +endless recursions during template class instantiation. \s-1ANSI/ISO\s0 \*(C+ +conforming programs must not rely on a maximum depth greater than 17 +(changed to 1024 in \*(C+0x). +.IP "\fB\-fno\-threadsafe\-statics\fR" 4 +.IX Item "-fno-threadsafe-statics" +Do not emit the extra code to use the routines specified in the \*(C+ +\&\s-1ABI\s0 for thread-safe initialization of local statics. You can use this +option to reduce code size slightly in code that doesn't need to be +thread-safe. +.IP "\fB\-fuse\-cxa\-atexit\fR" 4 +.IX Item "-fuse-cxa-atexit" +Register destructors for objects with static storage duration with the +\&\f(CW\*(C`_\|_cxa_atexit\*(C'\fR function rather than the \f(CW\*(C`atexit\*(C'\fR function. +This option is required for fully standards-compliant handling of static +destructors, but will only work if your C library supports +\&\f(CW\*(C`_\|_cxa_atexit\*(C'\fR. +.IP "\fB\-fno\-use\-cxa\-get\-exception\-ptr\fR" 4 +.IX Item "-fno-use-cxa-get-exception-ptr" +Don't use the \f(CW\*(C`_\|_cxa_get_exception_ptr\*(C'\fR runtime routine. This +will cause \f(CW\*(C`std::uncaught_exception\*(C'\fR to be incorrect, but is necessary +if the runtime routine is not available. +.IP "\fB\-fvisibility\-inlines\-hidden\fR" 4 +.IX Item "-fvisibility-inlines-hidden" +This switch declares that the user does not attempt to compare +pointers to inline methods where the addresses of the two functions +were taken in different shared objects. +.Sp +The effect of this is that \s-1GCC\s0 may, effectively, mark inline methods with +\&\f(CW\*(C`_\|_attribute_\|_ ((visibility ("hidden")))\*(C'\fR so that they do not +appear in the export table of a \s-1DSO\s0 and do not require a \s-1PLT\s0 indirection +when used within the \s-1DSO\s0. Enabling this option can have a dramatic effect +on load and link times of a \s-1DSO\s0 as it massively reduces the size of the +dynamic export table when the library makes heavy use of templates. +.Sp +The behavior of this switch is not quite the same as marking the +methods as hidden directly, because it does not affect static variables +local to the function or cause the compiler to deduce that +the function is defined in only one shared object. +.Sp +You may mark a method as having a visibility explicitly to negate the +effect of the switch for that method. For example, if you do want to +compare pointers to a particular inline method, you might mark it as +having default visibility. Marking the enclosing class with explicit +visibility will have no effect. +.Sp +Explicitly instantiated inline methods are unaffected by this option +as their linkage might otherwise cross a shared library boundary. +.IP "\fB\-fvisibility\-ms\-compat\fR" 4 +.IX Item "-fvisibility-ms-compat" +This flag attempts to use visibility settings to make \s-1GCC\s0's \*(C+ +linkage model compatible with that of Microsoft Visual Studio. +.Sp +The flag makes these changes to \s-1GCC\s0's linkage model: +.RS 4 +.IP "1." 4 +It sets the default visibility to \f(CW\*(C`hidden\*(C'\fR, like +\&\fB\-fvisibility=hidden\fR. +.IP "2." 4 +Types, but not their members, are not hidden by default. +.IP "3." 4 +The One Definition Rule is relaxed for types without explicit +visibility specifications which are defined in more than one different +shared object: those declarations are permitted if they would have +been permitted when this option was not used. +.RE +.RS 4 +.Sp +In new code it is better to use \fB\-fvisibility=hidden\fR and +export those classes which are intended to be externally visible. +Unfortunately it is possible for code to rely, perhaps accidentally, +on the Visual Studio behavior. +.Sp +Among the consequences of these changes are that static data members +of the same type with the same name but defined in different shared +objects will be different, so changing one will not change the other; +and that pointers to function members defined in different shared +objects may not compare equal. When this flag is given, it is a +violation of the \s-1ODR\s0 to define types with the same name differently. +.RE +.IP "\fB\-fno\-weak\fR" 4 +.IX Item "-fno-weak" +Do not use weak symbol support, even if it is provided by the linker. +By default, G++ will use weak symbols if they are available. This +option exists only for testing, and should not be used by end-users; +it will result in inferior code and has no benefits. This option may +be removed in a future release of G++. +.IP "\fB\-nostdinc++\fR" 4 +.IX Item "-nostdinc++" +Do not search for header files in the standard directories specific to +\&\*(C+, but do still search the other standard directories. (This option +is used when building the \*(C+ library.) +.PP +In addition, these optimization, warning, and code generation options +have meanings only for \*(C+ programs: +.IP "\fB\-fno\-default\-inline\fR" 4 +.IX Item "-fno-default-inline" +Do not assume \fBinline\fR for functions defined inside a class scope. + Note that these +functions will have linkage like inline functions; they just won't be +inlined by default. +.IP "\fB\-Wabi\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wabi (C, Objective-C, and Objective- only)" +Warn when G++ generates code that is probably not compatible with the +vendor-neutral \*(C+ \s-1ABI\s0. Although an effort has been made to warn about +all such cases, there are probably some cases that are not warned about, +even though G++ is generating incompatible code. There may also be +cases where warnings are emitted even though the code that is generated +will be compatible. +.Sp +You should rewrite your code to avoid these warnings if you are +concerned about the fact that code generated by G++ may not be binary +compatible with code generated by other compilers. +.Sp +The known incompatibilities in \fB\-fabi\-version=2\fR (the default) include: +.RS 4 +.IP "\(bu" 4 +A template with a non-type template parameter of reference type is +mangled incorrectly: +.Sp +.Vb 3 +\& extern int N; +\& template <int &> struct S {}; +\& void n (S<N>) {2} +.Ve +.Sp +This is fixed in \fB\-fabi\-version=3\fR. +.IP "\(bu" 4 +\&\s-1SIMD\s0 vector types declared using \f(CW\*(C`_\|_attribute ((vector_size))\*(C'\fR are +mangled in a non-standard way that does not allow for overloading of +functions taking vectors of different sizes. +.Sp +The mangling is changed in \fB\-fabi\-version=4\fR. +.RE +.RS 4 +.Sp +The known incompatibilities in \fB\-fabi\-version=1\fR include: +.IP "\(bu" 4 +Incorrect handling of tail-padding for bit-fields. G++ may attempt to +pack data into the same byte as a base class. For example: +.Sp +.Vb 2 +\& struct A { virtual void f(); int f1 : 1; }; +\& struct B : public A { int f2 : 1; }; +.Ve +.Sp +In this case, G++ will place \f(CW\*(C`B::f2\*(C'\fR into the same byte +as\f(CW\*(C`A::f1\*(C'\fR; other compilers will not. You can avoid this problem +by explicitly padding \f(CW\*(C`A\*(C'\fR so that its size is a multiple of the +byte size on your platform; that will cause G++ and other compilers to +layout \f(CW\*(C`B\*(C'\fR identically. +.IP "\(bu" 4 +Incorrect handling of tail-padding for virtual bases. G++ does not use +tail padding when laying out virtual bases. For example: +.Sp +.Vb 3 +\& struct A { virtual void f(); char c1; }; +\& struct B { B(); char c2; }; +\& struct C : public A, public virtual B {}; +.Ve +.Sp +In this case, G++ will not place \f(CW\*(C`B\*(C'\fR into the tail-padding for +\&\f(CW\*(C`A\*(C'\fR; other compilers will. You can avoid this problem by +explicitly padding \f(CW\*(C`A\*(C'\fR so that its size is a multiple of its +alignment (ignoring virtual base classes); that will cause G++ and other +compilers to layout \f(CW\*(C`C\*(C'\fR identically. +.IP "\(bu" 4 +Incorrect handling of bit-fields with declared widths greater than that +of their underlying types, when the bit-fields appear in a union. For +example: +.Sp +.Vb 1 +\& union U { int i : 4096; }; +.Ve +.Sp +Assuming that an \f(CW\*(C`int\*(C'\fR does not have 4096 bits, G++ will make the +union too small by the number of bits in an \f(CW\*(C`int\*(C'\fR. +.IP "\(bu" 4 +Empty classes can be placed at incorrect offsets. For example: +.Sp +.Vb 1 +\& struct A {}; +\& +\& struct B { +\& A a; +\& virtual void f (); +\& }; +\& +\& struct C : public B, public A {}; +.Ve +.Sp +G++ will place the \f(CW\*(C`A\*(C'\fR base class of \f(CW\*(C`C\*(C'\fR at a nonzero offset; +it should be placed at offset zero. G++ mistakenly believes that the +\&\f(CW\*(C`A\*(C'\fR data member of \f(CW\*(C`B\*(C'\fR is already at offset zero. +.IP "\(bu" 4 +Names of template functions whose types involve \f(CW\*(C`typename\*(C'\fR or +template template parameters can be mangled incorrectly. +.Sp +.Vb 2 +\& template <typename Q> +\& void f(typename Q::X) {} +\& +\& template <template <typename> class Q> +\& void f(typename Q<int>::X) {} +.Ve +.Sp +Instantiations of these templates may be mangled incorrectly. +.RE +.RS 4 +.Sp +It also warns psABI related changes. The known psABI changes at this +point include: +.IP "\(bu" 4 +For SYSV/x86\-64, when passing union with long double, it is changed to +pass in memory as specified in psABI. For example: +.Sp +.Vb 4 +\& union U { +\& long double ld; +\& int i; +\& }; +.Ve +.Sp +\&\f(CW\*(C`union U\*(C'\fR will always be passed in memory. +.RE +.RS 4 +.RE +.IP "\fB\-Wctor\-dtor\-privacy\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wctor-dtor-privacy ( and Objective- only)" +Warn when a class seems unusable because all the constructors or +destructors in that class are private, and it has neither friends nor +public static member functions. +.IP "\fB\-Wnoexcept\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wnoexcept ( and Objective- only)" +Warn when a noexcept-expression evaluates to false because of a call +to a function that does not have a non-throwing exception +specification (i.e. \fB\f(BIthrow()\fB\fR or \fBnoexcept\fR) but is known by +the compiler to never throw an exception. +.IP "\fB\-Wnon\-virtual\-dtor\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wnon-virtual-dtor ( and Objective- only)" +Warn when a class has virtual functions and accessible non-virtual +destructor, in which case it would be possible but unsafe to delete +an instance of a derived class through a pointer to the base class. +This warning is also enabled if \-Weffc++ is specified. +.IP "\fB\-Wreorder\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wreorder ( and Objective- only)" +Warn when the order of member initializers given in the code does not +match the order in which they must be executed. For instance: +.Sp +.Vb 5 +\& struct A { +\& int i; +\& int j; +\& A(): j (0), i (1) { } +\& }; +.Ve +.Sp +The compiler will rearrange the member initializers for \fBi\fR +and \fBj\fR to match the declaration order of the members, emitting +a warning to that effect. This warning is enabled by \fB\-Wall\fR. +.PP +The following \fB\-W...\fR options are not affected by \fB\-Wall\fR. +.IP "\fB\-Weffc++\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Weffc++ ( and Objective- only)" +Warn about violations of the following style guidelines from Scott Meyers' +\&\fIEffective \*(C+\fR book: +.RS 4 +.IP "\(bu" 4 +Item 11: Define a copy constructor and an assignment operator for classes +with dynamically allocated memory. +.IP "\(bu" 4 +Item 12: Prefer initialization to assignment in constructors. +.IP "\(bu" 4 +Item 14: Make destructors virtual in base classes. +.IP "\(bu" 4 +Item 15: Have \f(CW\*(C`operator=\*(C'\fR return a reference to \f(CW*this\fR. +.IP "\(bu" 4 +Item 23: Don't try to return a reference when you must return an object. +.RE +.RS 4 +.Sp +Also warn about violations of the following style guidelines from +Scott Meyers' \fIMore Effective \*(C+\fR book: +.IP "\(bu" 4 +Item 6: Distinguish between prefix and postfix forms of increment and +decrement operators. +.IP "\(bu" 4 +Item 7: Never overload \f(CW\*(C`&&\*(C'\fR, \f(CW\*(C`||\*(C'\fR, or \f(CW\*(C`,\*(C'\fR. +.RE +.RS 4 +.Sp +When selecting this option, be aware that the standard library +headers do not obey all of these guidelines; use \fBgrep \-v\fR +to filter out those warnings. +.RE +.IP "\fB\-Wstrict\-null\-sentinel\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wstrict-null-sentinel ( and Objective- only)" +Warn also about the use of an uncasted \f(CW\*(C`NULL\*(C'\fR as sentinel. When +compiling only with \s-1GCC\s0 this is a valid sentinel, as \f(CW\*(C`NULL\*(C'\fR is defined +to \f(CW\*(C`_\|_null\*(C'\fR. Although it is a null pointer constant not a null pointer, +it is guaranteed to be of the same size as a pointer. But this use is +not portable across different compilers. +.IP "\fB\-Wno\-non\-template\-friend\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-non-template-friend ( and Objective- only)" +Disable warnings when non-templatized friend functions are declared +within a template. Since the advent of explicit template specification +support in G++, if the name of the friend is an unqualified-id (i.e., +\&\fBfriend foo(int)\fR), the \*(C+ language specification demands that the +friend declare or define an ordinary, nontemplate function. (Section +14.5.3). Before G++ implemented explicit specification, unqualified-ids +could be interpreted as a particular specialization of a templatized +function. Because this non-conforming behavior is no longer the default +behavior for G++, \fB\-Wnon\-template\-friend\fR allows the compiler to +check existing code for potential trouble spots and is on by default. +This new compiler behavior can be turned off with +\&\fB\-Wno\-non\-template\-friend\fR which keeps the conformant compiler code +but disables the helpful warning. +.IP "\fB\-Wold\-style\-cast\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wold-style-cast ( and Objective- only)" +Warn if an old-style (C\-style) cast to a non-void type is used within +a \*(C+ program. The new-style casts (\fBdynamic_cast\fR, +\&\fBstatic_cast\fR, \fBreinterpret_cast\fR, and \fBconst_cast\fR) are +less vulnerable to unintended effects and much easier to search for. +.IP "\fB\-Woverloaded\-virtual\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Woverloaded-virtual ( and Objective- only)" +Warn when a function declaration hides virtual functions from a +base class. For example, in: +.Sp +.Vb 3 +\& struct A { +\& virtual void f(); +\& }; +\& +\& struct B: public A { +\& void f(int); +\& }; +.Ve +.Sp +the \f(CW\*(C`A\*(C'\fR class version of \f(CW\*(C`f\*(C'\fR is hidden in \f(CW\*(C`B\*(C'\fR, and code +like: +.Sp +.Vb 2 +\& B* b; +\& b\->f(); +.Ve +.Sp +will fail to compile. +.IP "\fB\-Wno\-pmf\-conversions\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-pmf-conversions ( and Objective- only)" +Disable the diagnostic for converting a bound pointer to member function +to a plain pointer. +.IP "\fB\-Wsign\-promo\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wsign-promo ( and Objective- only)" +Warn when overload resolution chooses a promotion from unsigned or +enumerated type to a signed type, over a conversion to an unsigned type of +the same size. Previous versions of G++ would try to preserve +unsignedness, but the standard mandates the current behavior. +.Sp +.Vb 4 +\& struct A { +\& operator int (); +\& A& operator = (int); +\& }; +\& +\& main () +\& { +\& A a,b; +\& a = b; +\& } +.Ve +.Sp +In this example, G++ will synthesize a default \fBA& operator = +(const A&);\fR, while cfront will use the user-defined \fBoperator =\fR. +.SS "Options Controlling Objective-C and Objective\-\*(C+ Dialects" +.IX Subsection "Options Controlling Objective-C and Objective- Dialects" +(\s-1NOTE:\s0 This manual does not describe the Objective-C and Objective\-\*(C+ +languages themselves. +.PP +This section describes the command-line options that are only meaningful +for Objective-C and Objective\-\*(C+ programs, but you can also use most of +the language-independent \s-1GNU\s0 compiler options. +For example, you might compile a file \f(CW\*(C`some_class.m\*(C'\fR like this: +.PP +.Vb 1 +\& gcc \-g \-fgnu\-runtime \-O \-c some_class.m +.Ve +.PP +In this example, \fB\-fgnu\-runtime\fR is an option meant only for +Objective-C and Objective\-\*(C+ programs; you can use the other options with +any language supported by \s-1GCC\s0. +.PP +Note that since Objective-C is an extension of the C language, Objective-C +compilations may also use options specific to the C front-end (e.g., +\&\fB\-Wtraditional\fR). Similarly, Objective\-\*(C+ compilations may use +\&\*(C+\-specific options (e.g., \fB\-Wabi\fR). +.PP +Here is a list of options that are \fIonly\fR for compiling Objective-C +and Objective\-\*(C+ programs: +.IP "\fB\-fconstant\-string\-class=\fR\fIclass-name\fR" 4 +.IX Item "-fconstant-string-class=class-name" +Use \fIclass-name\fR as the name of the class to instantiate for each +literal string specified with the syntax \f(CW\*(C`@"..."\*(C'\fR. The default +class name is \f(CW\*(C`NXConstantString\*(C'\fR if the \s-1GNU\s0 runtime is being used, and +\&\f(CW\*(C`NSConstantString\*(C'\fR if the NeXT runtime is being used (see below). The +\&\fB\-fconstant\-cfstrings\fR option, if also present, will override the +\&\fB\-fconstant\-string\-class\fR setting and cause \f(CW\*(C`@"..."\*(C'\fR literals +to be laid out as constant CoreFoundation strings. +.IP "\fB\-fgnu\-runtime\fR" 4 +.IX Item "-fgnu-runtime" +Generate object code compatible with the standard \s-1GNU\s0 Objective-C +runtime. This is the default for most types of systems. +.IP "\fB\-fnext\-runtime\fR" 4 +.IX Item "-fnext-runtime" +Generate output compatible with the NeXT runtime. This is the default +for NeXT-based systems, including Darwin and Mac \s-1OS\s0 X. The macro +\&\f(CW\*(C`_\|_NEXT_RUNTIME_\|_\*(C'\fR is predefined if (and only if) this option is +used. +.IP "\fB\-fno\-nil\-receivers\fR" 4 +.IX Item "-fno-nil-receivers" +Assume that all Objective-C message dispatches (\f(CW\*(C`[receiver +message:arg]\*(C'\fR) in this translation unit ensure that the receiver is +not \f(CW\*(C`nil\*(C'\fR. This allows for more efficient entry points in the +runtime to be used. This option is only available in conjunction with +the NeXT runtime and \s-1ABI\s0 version 0 or 1. +.IP "\fB\-fobjc\-abi\-version=\fR\fIn\fR" 4 +.IX Item "-fobjc-abi-version=n" +Use version \fIn\fR of the Objective-C \s-1ABI\s0 for the selected runtime. +This option is currently supported only for the NeXT runtime. In that +case, Version 0 is the traditional (32\-bit) \s-1ABI\s0 without support for +properties and other Objective-C 2.0 additions. Version 1 is the +traditional (32\-bit) \s-1ABI\s0 with support for properties and other +Objective-C 2.0 additions. Version 2 is the modern (64\-bit) \s-1ABI\s0. If +nothing is specified, the default is Version 0 on 32\-bit target +machines, and Version 2 on 64\-bit target machines. +.IP "\fB\-fobjc\-call\-cxx\-cdtors\fR" 4 +.IX Item "-fobjc-call-cxx-cdtors" +For each Objective-C class, check if any of its instance variables is a +\&\*(C+ object with a non-trivial default constructor. If so, synthesize a +special \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR instance method that will run +non-trivial default constructors on any such instance variables, in order, +and then return \f(CW\*(C`self\*(C'\fR. Similarly, check if any instance variable +is a \*(C+ object with a non-trivial destructor, and if so, synthesize a +special \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR method that will run +all such default destructors, in reverse order. +.Sp +The \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR and \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR +methods thusly generated will only operate on instance variables +declared in the current Objective-C class, and not those inherited +from superclasses. It is the responsibility of the Objective-C +runtime to invoke all such methods in an object's inheritance +hierarchy. The \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR methods will be invoked +by the runtime immediately after a new object instance is allocated; +the \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR methods will be invoked immediately +before the runtime deallocates an object instance. +.Sp +As of this writing, only the NeXT runtime on Mac \s-1OS\s0 X 10.4 and later has +support for invoking the \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR and +\&\f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR methods. +.IP "\fB\-fobjc\-direct\-dispatch\fR" 4 +.IX Item "-fobjc-direct-dispatch" +Allow fast jumps to the message dispatcher. On Darwin this is +accomplished via the comm page. +.IP "\fB\-fobjc\-exceptions\fR" 4 +.IX Item "-fobjc-exceptions" +Enable syntactic support for structured exception handling in +Objective-C, similar to what is offered by \*(C+ and Java. This option +is required to use the Objective-C keywords \f(CW@try\fR, +\&\f(CW@throw\fR, \f(CW@catch\fR, \f(CW@finally\fR and +\&\f(CW@synchronized\fR. This option is available with both the \s-1GNU\s0 +runtime and the NeXT runtime (but not available in conjunction with +the NeXT runtime on Mac \s-1OS\s0 X 10.2 and earlier). +.IP "\fB\-fobjc\-gc\fR" 4 +.IX Item "-fobjc-gc" +Enable garbage collection (\s-1GC\s0) in Objective-C and Objective\-\*(C+ +programs. This option is only available with the NeXT runtime; the +\&\s-1GNU\s0 runtime has a different garbage collection implementation that +does not require special compiler flags. +.IP "\fB\-fobjc\-nilcheck\fR" 4 +.IX Item "-fobjc-nilcheck" +For the NeXT runtime with version 2 of the \s-1ABI\s0, check for a nil +receiver in method invocations before doing the actual method call. +This is the default and can be disabled using +\&\fB\-fno\-objc\-nilcheck\fR. Class methods and super calls are never +checked for nil in this way no matter what this flag is set to. +Currently this flag does nothing when the \s-1GNU\s0 runtime, or an older +version of the NeXT runtime \s-1ABI\s0, is used. +.IP "\fB\-fobjc\-std=objc1\fR" 4 +.IX Item "-fobjc-std=objc1" +Conform to the language syntax of Objective-C 1.0, the language +recognized by \s-1GCC\s0 4.0. This only affects the Objective-C additions to +the C/\*(C+ language; it does not affect conformance to C/\*(C+ standards, +which is controlled by the separate C/\*(C+ dialect option flags. When +this option is used with the Objective-C or Objective\-\*(C+ compiler, +any Objective-C syntax that is not recognized by \s-1GCC\s0 4.0 is rejected. +This is useful if you need to make sure that your Objective-C code can +be compiled with older versions of \s-1GCC\s0. +.IP "\fB\-freplace\-objc\-classes\fR" 4 +.IX Item "-freplace-objc-classes" +Emit a special marker instructing \fB\f(BIld\fB\|(1)\fR not to statically link in +the resulting object file, and allow \fB\f(BIdyld\fB\|(1)\fR to load it in at +run time instead. This is used in conjunction with the Fix-and-Continue +debugging mode, where the object file in question may be recompiled and +dynamically reloaded in the course of program execution, without the need +to restart the program itself. Currently, Fix-and-Continue functionality +is only available in conjunction with the NeXT runtime on Mac \s-1OS\s0 X 10.3 +and later. +.IP "\fB\-fzero\-link\fR" 4 +.IX Item "-fzero-link" +When compiling for the NeXT runtime, the compiler ordinarily replaces calls +to \f(CW\*(C`objc_getClass("...")\*(C'\fR (when the name of the class is known at +compile time) with static class references that get initialized at load time, +which improves run-time performance. Specifying the \fB\-fzero\-link\fR flag +suppresses this behavior and causes calls to \f(CW\*(C`objc_getClass("...")\*(C'\fR +to be retained. This is useful in Zero-Link debugging mode, since it allows +for individual class implementations to be modified during program execution. +The \s-1GNU\s0 runtime currently always retains calls to \f(CW\*(C`objc_get_class("...")\*(C'\fR +regardless of command line options. +.IP "\fB\-gen\-decls\fR" 4 +.IX Item "-gen-decls" +Dump interface declarations for all classes seen in the source file to a +file named \fI\fIsourcename\fI.decl\fR. +.IP "\fB\-Wassign\-intercept\fR (Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wassign-intercept (Objective-C and Objective- only)" +Warn whenever an Objective-C assignment is being intercepted by the +garbage collector. +.IP "\fB\-Wno\-protocol\fR (Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-protocol (Objective-C and Objective- only)" +If a class is declared to implement a protocol, a warning is issued for +every method in the protocol that is not implemented by the class. The +default behavior is to issue a warning for every method not explicitly +implemented in the class, even if a method implementation is inherited +from the superclass. If you use the \fB\-Wno\-protocol\fR option, then +methods inherited from the superclass are considered to be implemented, +and no warning is issued for them. +.IP "\fB\-Wselector\fR (Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wselector (Objective-C and Objective- only)" +Warn if multiple methods of different types for the same selector are +found during compilation. The check is performed on the list of methods +in the final stage of compilation. Additionally, a check is performed +for each selector appearing in a \f(CW\*(C`@selector(...)\*(C'\fR +expression, and a corresponding method for that selector has been found +during compilation. Because these checks scan the method table only at +the end of compilation, these warnings are not produced if the final +stage of compilation is not reached, for example because an error is +found during compilation, or because the \fB\-fsyntax\-only\fR option is +being used. +.IP "\fB\-Wstrict\-selector\-match\fR (Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wstrict-selector-match (Objective-C and Objective- only)" +Warn if multiple methods with differing argument and/or return types are +found for a given selector when attempting to send a message using this +selector to a receiver of type \f(CW\*(C`id\*(C'\fR or \f(CW\*(C`Class\*(C'\fR. When this flag +is off (which is the default behavior), the compiler will omit such warnings +if any differences found are confined to types which share the same size +and alignment. +.IP "\fB\-Wundeclared\-selector\fR (Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wundeclared-selector (Objective-C and Objective- only)" +Warn if a \f(CW\*(C`@selector(...)\*(C'\fR expression referring to an +undeclared selector is found. A selector is considered undeclared if no +method with that name has been declared before the +\&\f(CW\*(C`@selector(...)\*(C'\fR expression, either explicitly in an +\&\f(CW@interface\fR or \f(CW@protocol\fR declaration, or implicitly in +an \f(CW@implementation\fR section. This option always performs its +checks as soon as a \f(CW\*(C`@selector(...)\*(C'\fR expression is found, +while \fB\-Wselector\fR only performs its checks in the final stage of +compilation. This also enforces the coding style convention +that methods and selectors must be declared before being used. +.IP "\fB\-print\-objc\-runtime\-info\fR" 4 +.IX Item "-print-objc-runtime-info" +Generate C header describing the largest structure that is passed by +value, if any. +.SS "Options to Control Diagnostic Messages Formatting" +.IX Subsection "Options to Control Diagnostic Messages Formatting" +Traditionally, diagnostic messages have been formatted irrespective of +the output device's aspect (e.g. its width, ...). The options described +below can be used to control the diagnostic messages formatting +algorithm, e.g. how many characters per line, how often source location +information should be reported. Right now, only the \*(C+ front end can +honor these options. However it is expected, in the near future, that +the remaining front ends would be able to digest them correctly. +.IP "\fB\-fmessage\-length=\fR\fIn\fR" 4 +.IX Item "-fmessage-length=n" +Try to format error messages so that they fit on lines of about \fIn\fR +characters. The default is 72 characters for \fBg++\fR and 0 for the rest of +the front ends supported by \s-1GCC\s0. If \fIn\fR is zero, then no +line-wrapping will be done; each error message will appear on a single +line. +.IP "\fB\-fdiagnostics\-show\-location=once\fR" 4 +.IX Item "-fdiagnostics-show-location=once" +Only meaningful in line-wrapping mode. Instructs the diagnostic messages +reporter to emit \fIonce\fR source location information; that is, in +case the message is too long to fit on a single physical line and has to +be wrapped, the source location won't be emitted (as prefix) again, +over and over, in subsequent continuation lines. This is the default +behavior. +.IP "\fB\-fdiagnostics\-show\-location=every\-line\fR" 4 +.IX Item "-fdiagnostics-show-location=every-line" +Only meaningful in line-wrapping mode. Instructs the diagnostic +messages reporter to emit the same source location information (as +prefix) for physical lines that result from the process of breaking +a message which is too long to fit on a single line. +.IP "\fB\-fno\-diagnostics\-show\-option\fR" 4 +.IX Item "-fno-diagnostics-show-option" +By default, each diagnostic emitted includes text which indicates the +command line option that directly controls the diagnostic (if such an +option is known to the diagnostic machinery). Specifying the +\&\fB\-fno\-diagnostics\-show\-option\fR flag suppresses that behavior. +.IP "\fB\-Wcoverage\-mismatch\fR" 4 +.IX Item "-Wcoverage-mismatch" +Warn if feedback profiles do not match when using the +\&\fB\-fprofile\-use\fR option. +If a source file was changed between \fB\-fprofile\-gen\fR and +\&\fB\-fprofile\-use\fR, the files with the profile feedback can fail +to match the source file and \s-1GCC\s0 can not use the profile feedback +information. By default, this warning is enabled and is treated as an +error. \fB\-Wno\-coverage\-mismatch\fR can be used to disable the +warning or \fB\-Wno\-error=coverage\-mismatch\fR can be used to +disable the error. Disable the error for this warning can result in +poorly optimized code, so disabling the error is useful only in the +case of very minor changes such as bug fixes to an existing code-base. +Completely disabling the warning is not recommended. +.SS "Options to Request or Suppress Warnings" +.IX Subsection "Options to Request or Suppress Warnings" +Warnings are diagnostic messages that report constructions which +are not inherently erroneous but which are risky or suggest there +may have been an error. +.PP +The following language-independent options do not enable specific +warnings but control the kinds of diagnostics produced by \s-1GCC\s0. +.IP "\fB\-fsyntax\-only\fR" 4 +.IX Item "-fsyntax-only" +Check the code for syntax errors, but don't do anything beyond that. +.IP "\fB\-fmax\-errors=\fR\fIn\fR" 4 +.IX Item "-fmax-errors=n" +Limits the maximum number of error messages to \fIn\fR, at which point +\&\s-1GCC\s0 bails out rather than attempting to continue processing the source +code. If \fIn\fR is 0 (the default), there is no limit on the number +of error messages produced. If \fB\-Wfatal\-errors\fR is also +specified, then \fB\-Wfatal\-errors\fR takes precedence over this +option. +.IP "\fB\-w\fR" 4 +.IX Item "-w" +Inhibit all warning messages. +.IP "\fB\-Werror\fR" 4 +.IX Item "-Werror" +Make all warnings into errors. +.IP "\fB\-Werror=\fR" 4 +.IX Item "-Werror=" +Make the specified warning into an error. The specifier for a warning +is appended, for example \fB\-Werror=switch\fR turns the warnings +controlled by \fB\-Wswitch\fR into errors. This switch takes a +negative form, to be used to negate \fB\-Werror\fR for specific +warnings, for example \fB\-Wno\-error=switch\fR makes +\&\fB\-Wswitch\fR warnings not be errors, even when \fB\-Werror\fR +is in effect. +.Sp +The warning message for each controllable warning includes the +option which controls the warning. That option can then be used with +\&\fB\-Werror=\fR and \fB\-Wno\-error=\fR as described above. +(Printing of the option in the warning message can be disabled using the +\&\fB\-fno\-diagnostics\-show\-option\fR flag.) +.Sp +Note that specifying \fB\-Werror=\fR\fIfoo\fR automatically implies +\&\fB\-W\fR\fIfoo\fR. However, \fB\-Wno\-error=\fR\fIfoo\fR does not +imply anything. +.IP "\fB\-Wfatal\-errors\fR" 4 +.IX Item "-Wfatal-errors" +This option causes the compiler to abort compilation on the first error +occurred rather than trying to keep going and printing further error +messages. +.PP +You can request many specific warnings with options beginning +\&\fB\-W\fR, for example \fB\-Wimplicit\fR to request warnings on +implicit declarations. Each of these specific warning options also +has a negative form beginning \fB\-Wno\-\fR to turn off warnings; for +example, \fB\-Wno\-implicit\fR. This manual lists only one of the +two forms, whichever is not the default. For further, +language-specific options also refer to \fB\*(C+ Dialect Options\fR and +\&\fBObjective-C and Objective\-\*(C+ Dialect Options\fR. +.PP +When an unrecognized warning option is requested (e.g., +\&\fB\-Wunknown\-warning\fR), \s-1GCC\s0 will emit a diagnostic stating +that the option is not recognized. However, if the \fB\-Wno\-\fR form +is used, the behavior is slightly different: No diagnostic will be +produced for \fB\-Wno\-unknown\-warning\fR unless other diagnostics +are being produced. This allows the use of new \fB\-Wno\-\fR options +with old compilers, but if something goes wrong, the compiler will +warn that an unrecognized option was used. +.IP "\fB\-pedantic\fR" 4 +.IX Item "-pedantic" +Issue all the warnings demanded by strict \s-1ISO\s0 C and \s-1ISO\s0 \*(C+; +reject all programs that use forbidden extensions, and some other +programs that do not follow \s-1ISO\s0 C and \s-1ISO\s0 \*(C+. For \s-1ISO\s0 C, follows the +version of the \s-1ISO\s0 C standard specified by any \fB\-std\fR option used. +.Sp +Valid \s-1ISO\s0 C and \s-1ISO\s0 \*(C+ programs should compile properly with or without +this option (though a rare few will require \fB\-ansi\fR or a +\&\fB\-std\fR option specifying the required version of \s-1ISO\s0 C). However, +without this option, certain \s-1GNU\s0 extensions and traditional C and \*(C+ +features are supported as well. With this option, they are rejected. +.Sp +\&\fB\-pedantic\fR does not cause warning messages for use of the +alternate keywords whose names begin and end with \fB_\|_\fR. Pedantic +warnings are also disabled in the expression that follows +\&\f(CW\*(C`_\|_extension_\|_\*(C'\fR. However, only system header files should use +these escape routes; application programs should avoid them. +.Sp +Some users try to use \fB\-pedantic\fR to check programs for strict \s-1ISO\s0 +C conformance. They soon find that it does not do quite what they want: +it finds some non-ISO practices, but not all\-\-\-only those for which +\&\s-1ISO\s0 C \fIrequires\fR a diagnostic, and some others for which +diagnostics have been added. +.Sp +A feature to report any failure to conform to \s-1ISO\s0 C might be useful in +some instances, but would require considerable additional work and would +be quite different from \fB\-pedantic\fR. We don't have plans to +support such a feature in the near future. +.Sp +Where the standard specified with \fB\-std\fR represents a \s-1GNU\s0 +extended dialect of C, such as \fBgnu90\fR or \fBgnu99\fR, there is a +corresponding \fIbase standard\fR, the version of \s-1ISO\s0 C on which the \s-1GNU\s0 +extended dialect is based. Warnings from \fB\-pedantic\fR are given +where they are required by the base standard. (It would not make sense +for such warnings to be given only for features not in the specified \s-1GNU\s0 +C dialect, since by definition the \s-1GNU\s0 dialects of C include all +features the compiler supports with the given option, and there would be +nothing to warn about.) +.IP "\fB\-pedantic\-errors\fR" 4 +.IX Item "-pedantic-errors" +Like \fB\-pedantic\fR, except that errors are produced rather than +warnings. +.IP "\fB\-Wall\fR" 4 +.IX Item "-Wall" +This enables all the warnings about constructions that some users +consider questionable, and that are easy to avoid (or modify to +prevent the warning), even in conjunction with macros. This also +enables some language-specific warnings described in \fB\*(C+ Dialect +Options\fR and \fBObjective-C and Objective\-\*(C+ Dialect Options\fR. +.Sp +\&\fB\-Wall\fR turns on the following warning flags: +.Sp +\&\fB\-Waddress +\&\-Warray\-bounds\fR (only with\fB \fR\fB\-O2\fR) +\&\fB\-Wc++0x\-compat +\&\-Wchar\-subscripts +\&\-Wenum\-compare\fR (in C/Objc; this is on by default in \*(C+) +\&\fB\-Wimplicit\-int\fR (C and Objective-C only) +\&\fB\-Wimplicit\-function\-declaration\fR (C and Objective-C only) +\&\fB\-Wcomment +\&\-Wformat +\&\-Wmain\fR (only for C/ObjC and unless\fB \fR\fB\-ffreestanding\fR) +\&\fB\-Wmaybe\-uninitialized +\&\-Wmissing\-braces +\&\-Wnonnull +\&\-Wparentheses +\&\-Wpointer\-sign +\&\-Wreorder +\&\-Wreturn\-type +\&\-Wripa\-opt\-mismatch +\&\-Wsequence\-point +\&\-Wsign\-compare\fR (only in \*(C+) +\&\fB\-Wstrict\-aliasing +\&\-Wstrict\-overflow=1 +\&\-Wswitch +\&\-Wtrigraphs +\&\-Wuninitialized +\&\-Wunknown\-pragmas +\&\-Wunused\-function +\&\-Wunused\-label +\&\-Wunused\-value +\&\-Wunused\-variable +\&\-Wvolatile\-register\-var\fR +.Sp +Note that some warning flags are not implied by \fB\-Wall\fR. Some of +them warn about constructions that users generally do not consider +questionable, but which occasionally you might wish to check for; +others warn about constructions that are necessary or hard to avoid in +some cases, and there is no simple way to modify the code to suppress +the warning. Some of them are enabled by \fB\-Wextra\fR but many of +them must be enabled individually. +.IP "\fB\-Wextra\fR" 4 +.IX Item "-Wextra" +This enables some extra warning flags that are not enabled by +\&\fB\-Wall\fR. (This option used to be called \fB\-W\fR. The older +name is still supported, but the newer name is more descriptive.) +.Sp +\&\fB\-Wclobbered +\&\-Wempty\-body +\&\-Wignored\-qualifiers +\&\-Wmissing\-field\-initializers +\&\-Wmissing\-parameter\-type\fR (C only) +\&\fB\-Wold\-style\-declaration\fR (C only) +\&\fB\-Woverride\-init +\&\-Wsign\-compare +\&\-Wtype\-limits +\&\-Wuninitialized +\&\-Wunused\-parameter\fR (only with\fB \fR\fB\-Wunused\fR\fB \fRor\fB \fR\fB\-Wall\fR) +\&\fB\-Wunused\-but\-set\-parameter\fR (only with\fB \fR\fB\-Wunused\fR\fB \fRor\fB \fR\fB\-Wall\fR) \fB \fR +.Sp +The option \fB\-Wextra\fR also prints warning messages for the +following cases: +.RS 4 +.IP "\(bu" 4 +A pointer is compared against integer zero with \fB<\fR, \fB<=\fR, +\&\fB>\fR, or \fB>=\fR. +.IP "\(bu" 4 +(\*(C+ only) An enumerator and a non-enumerator both appear in a +conditional expression. +.IP "\(bu" 4 +(\*(C+ only) Ambiguous virtual bases. +.IP "\(bu" 4 +(\*(C+ only) Subscripting an array which has been declared \fBregister\fR. +.IP "\(bu" 4 +(\*(C+ only) Taking the address of a variable which has been declared +\&\fBregister\fR. +.IP "\(bu" 4 +(\*(C+ only) A base class is not initialized in a derived class' copy +constructor. +.RE +.RS 4 +.RE +.IP "\fB\-Wchar\-subscripts\fR" 4 +.IX Item "-Wchar-subscripts" +Warn if an array subscript has type \f(CW\*(C`char\*(C'\fR. This is a common cause +of error, as programmers often forget that this type is signed on some +machines. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wcomment\fR" 4 +.IX Item "-Wcomment" +Warn whenever a comment-start sequence \fB/*\fR appears in a \fB/*\fR +comment, or whenever a Backslash-Newline appears in a \fB//\fR comment. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wno\-cpp\fR" 4 +.IX Item "-Wno-cpp" +(C, Objective-C, \*(C+, Objective\-\*(C+ and Fortran only) +.Sp +Suppress warning messages emitted by \f(CW\*(C`#warning\*(C'\fR directives. +.IP "\fB\-Wdouble\-promotion\fR (C, \*(C+, Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wdouble-promotion (C, , Objective-C and Objective- only)" +Give a warning when a value of type \f(CW\*(C`float\*(C'\fR is implicitly +promoted to \f(CW\*(C`double\*(C'\fR. CPUs with a 32\-bit \*(L"single-precision\*(R" +floating-point unit implement \f(CW\*(C`float\*(C'\fR in hardware, but emulate +\&\f(CW\*(C`double\*(C'\fR in software. On such a machine, doing computations +using \f(CW\*(C`double\*(C'\fR values is much more expensive because of the +overhead required for software emulation. +.Sp +It is easy to accidentally do computations with \f(CW\*(C`double\*(C'\fR because +floating-point literals are implicitly of type \f(CW\*(C`double\*(C'\fR. For +example, in: +.Sp +.Vb 4 +\& float area(float radius) +\& { +\& return 3.14159 * radius * radius; +\& } +.Ve +.Sp +the compiler will perform the entire computation with \f(CW\*(C`double\*(C'\fR +because the floating-point literal is a \f(CW\*(C`double\*(C'\fR. +.IP "\fB\-Wformat\fR" 4 +.IX Item "-Wformat" +Check calls to \f(CW\*(C`printf\*(C'\fR and \f(CW\*(C`scanf\*(C'\fR, etc., to make sure that +the arguments supplied have types appropriate to the format string +specified, and that the conversions specified in the format string make +sense. This includes standard functions, and others specified by format +attributes, in the \f(CW\*(C`printf\*(C'\fR, +\&\f(CW\*(C`scanf\*(C'\fR, \f(CW\*(C`strftime\*(C'\fR and \f(CW\*(C`strfmon\*(C'\fR (an X/Open extension, +not in the C standard) families (or other target-specific families). +Which functions are checked without format attributes having been +specified depends on the standard version selected, and such checks of +functions without the attribute specified are disabled by +\&\fB\-ffreestanding\fR or \fB\-fno\-builtin\fR. +.Sp +The formats are checked against the format features supported by \s-1GNU\s0 +libc version 2.2. These include all \s-1ISO\s0 C90 and C99 features, as well +as features from the Single Unix Specification and some \s-1BSD\s0 and \s-1GNU\s0 +extensions. Other library implementations may not support all these +features; \s-1GCC\s0 does not support warning about features that go beyond a +particular library's limitations. However, if \fB\-pedantic\fR is used +with \fB\-Wformat\fR, warnings will be given about format features not +in the selected standard version (but not for \f(CW\*(C`strfmon\*(C'\fR formats, +since those are not in any version of the C standard). +.Sp +Since \fB\-Wformat\fR also checks for null format arguments for +several functions, \fB\-Wformat\fR also implies \fB\-Wnonnull\fR. +.Sp +\&\fB\-Wformat\fR is included in \fB\-Wall\fR. For more control over some +aspects of format checking, the options \fB\-Wformat\-y2k\fR, +\&\fB\-Wno\-format\-extra\-args\fR, \fB\-Wno\-format\-zero\-length\fR, +\&\fB\-Wformat\-nonliteral\fR, \fB\-Wformat\-security\fR, and +\&\fB\-Wformat=2\fR are available, but are not included in \fB\-Wall\fR. +.IP "\fB\-Wformat\-y2k\fR" 4 +.IX Item "-Wformat-y2k" +If \fB\-Wformat\fR is specified, also warn about \f(CW\*(C`strftime\*(C'\fR +formats which may yield only a two-digit year. +.IP "\fB\-Wno\-format\-contains\-nul\fR" 4 +.IX Item "-Wno-format-contains-nul" +If \fB\-Wformat\fR is specified, do not warn about format strings that +contain \s-1NUL\s0 bytes. +.IP "\fB\-Wno\-format\-extra\-args\fR" 4 +.IX Item "-Wno-format-extra-args" +If \fB\-Wformat\fR is specified, do not warn about excess arguments to a +\&\f(CW\*(C`printf\*(C'\fR or \f(CW\*(C`scanf\*(C'\fR format function. The C standard specifies +that such arguments are ignored. +.Sp +Where the unused arguments lie between used arguments that are +specified with \fB$\fR operand number specifications, normally +warnings are still given, since the implementation could not know what +type to pass to \f(CW\*(C`va_arg\*(C'\fR to skip the unused arguments. However, +in the case of \f(CW\*(C`scanf\*(C'\fR formats, this option will suppress the +warning if the unused arguments are all pointers, since the Single +Unix Specification says that such unused arguments are allowed. +.IP "\fB\-Wno\-format\-zero\-length\fR (C and Objective-C only)" 4 +.IX Item "-Wno-format-zero-length (C and Objective-C only)" +If \fB\-Wformat\fR is specified, do not warn about zero-length formats. +The C standard specifies that zero-length formats are allowed. +.IP "\fB\-Wformat\-nonliteral\fR" 4 +.IX Item "-Wformat-nonliteral" +If \fB\-Wformat\fR is specified, also warn if the format string is not a +string literal and so cannot be checked, unless the format function +takes its format arguments as a \f(CW\*(C`va_list\*(C'\fR. +.IP "\fB\-Wformat\-security\fR" 4 +.IX Item "-Wformat-security" +If \fB\-Wformat\fR is specified, also warn about uses of format +functions that represent possible security problems. At present, this +warns about calls to \f(CW\*(C`printf\*(C'\fR and \f(CW\*(C`scanf\*(C'\fR functions where the +format string is not a string literal and there are no format arguments, +as in \f(CW\*(C`printf (foo);\*(C'\fR. This may be a security hole if the format +string came from untrusted input and contains \fB\f(CB%n\fB\fR. (This is +currently a subset of what \fB\-Wformat\-nonliteral\fR warns about, but +in future warnings may be added to \fB\-Wformat\-security\fR that are not +included in \fB\-Wformat\-nonliteral\fR.) +.IP "\fB\-Wformat=2\fR" 4 +.IX Item "-Wformat=2" +Enable \fB\-Wformat\fR plus format checks not included in +\&\fB\-Wformat\fR. Currently equivalent to \fB\-Wformat +\&\-Wformat\-nonliteral \-Wformat\-security \-Wformat\-y2k\fR. +.IP "\fB\-Wnonnull\fR (C, \*(C+, Objective-C, and Objective\-\*(C+ only)" 4 +.IX Item "-Wnonnull (C, , Objective-C, and Objective- only)" +Warn about passing a null pointer for arguments marked as +requiring a non-null value by the \f(CW\*(C`nonnull\*(C'\fR function attribute. +.Sp +\&\fB\-Wnonnull\fR is included in \fB\-Wall\fR and \fB\-Wformat\fR. It +can be disabled with the \fB\-Wno\-nonnull\fR option. +.IP "\fB\-Winit\-self\fR (C, \*(C+, Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Winit-self (C, , Objective-C and Objective- only)" +Warn about uninitialized variables which are initialized with themselves. +Note this option can only be used with the \fB\-Wuninitialized\fR option. +.Sp +For example, \s-1GCC\s0 will warn about \f(CW\*(C`i\*(C'\fR being uninitialized in the +following snippet only when \fB\-Winit\-self\fR has been specified: +.Sp +.Vb 5 +\& int f() +\& { +\& int i = i; +\& return i; +\& } +.Ve +.IP "\fB\-Wimplicit\-int\fR (C and Objective-C only)" 4 +.IX Item "-Wimplicit-int (C and Objective-C only)" +Warn when a declaration does not specify a type. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wimplicit\-function\-declaration\fR (C and Objective-C only)" 4 +.IX Item "-Wimplicit-function-declaration (C and Objective-C only)" +Give a warning whenever a function is used before being declared. In +C99 mode (\fB\-std=c99\fR or \fB\-std=gnu99\fR), this warning is +enabled by default and it is made into an error by +\&\fB\-pedantic\-errors\fR. This warning is also enabled by +\&\fB\-Wall\fR. +.IP "\fB\-Wimplicit\fR (C and Objective-C only)" 4 +.IX Item "-Wimplicit (C and Objective-C only)" +Same as \fB\-Wimplicit\-int\fR and \fB\-Wimplicit\-function\-declaration\fR. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wignored\-qualifiers\fR (C and \*(C+ only)" 4 +.IX Item "-Wignored-qualifiers (C and only)" +Warn if the return type of a function has a type qualifier +such as \f(CW\*(C`const\*(C'\fR. For \s-1ISO\s0 C such a type qualifier has no effect, +since the value returned by a function is not an lvalue. +For \*(C+, the warning is only emitted for scalar types or \f(CW\*(C`void\*(C'\fR. +\&\s-1ISO\s0 C prohibits qualified \f(CW\*(C`void\*(C'\fR return types on function +definitions, so such return types always receive a warning +even without this option. +.Sp +This warning is also enabled by \fB\-Wextra\fR. +.IP "\fB\-Wmain\fR" 4 +.IX Item "-Wmain" +Warn if the type of \fBmain\fR is suspicious. \fBmain\fR should be +a function with external linkage, returning int, taking either zero +arguments, two, or three arguments of appropriate types. This warning +is enabled by default in \*(C+ and is enabled by either \fB\-Wall\fR +or \fB\-pedantic\fR. +.IP "\fB\-Wmissing\-braces\fR" 4 +.IX Item "-Wmissing-braces" +Warn if an aggregate or union initializer is not fully bracketed. In +the following example, the initializer for \fBa\fR is not fully +bracketed, but that for \fBb\fR is fully bracketed. +.Sp +.Vb 2 +\& int a[2][2] = { 0, 1, 2, 3 }; +\& int b[2][2] = { { 0, 1 }, { 2, 3 } }; +.Ve +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wmissing\-include\-dirs\fR (C, \*(C+, Objective-C and Objective\-\*(C+ only)" 4 +.IX Item "-Wmissing-include-dirs (C, , Objective-C and Objective- only)" +Warn if a user-supplied include directory does not exist. +.IP "\fB\-Wparentheses\fR" 4 +.IX Item "-Wparentheses" +Warn if parentheses are omitted in certain contexts, such +as when there is an assignment in a context where a truth value +is expected, or when operators are nested whose precedence people +often get confused about. +.Sp +Also warn if a comparison like \fBx<=y<=z\fR appears; this is +equivalent to \fB(x<=y ? 1 : 0) <= z\fR, which is a different +interpretation from that of ordinary mathematical notation. +.Sp +Also warn about constructions where there may be confusion to which +\&\f(CW\*(C`if\*(C'\fR statement an \f(CW\*(C`else\*(C'\fR branch belongs. Here is an example of +such a case: +.Sp +.Vb 7 +\& { +\& if (a) +\& if (b) +\& foo (); +\& else +\& bar (); +\& } +.Ve +.Sp +In C/\*(C+, every \f(CW\*(C`else\*(C'\fR branch belongs to the innermost possible +\&\f(CW\*(C`if\*(C'\fR statement, which in this example is \f(CW\*(C`if (b)\*(C'\fR. This is +often not what the programmer expected, as illustrated in the above +example by indentation the programmer chose. When there is the +potential for this confusion, \s-1GCC\s0 will issue a warning when this flag +is specified. To eliminate the warning, add explicit braces around +the innermost \f(CW\*(C`if\*(C'\fR statement so there is no way the \f(CW\*(C`else\*(C'\fR +could belong to the enclosing \f(CW\*(C`if\*(C'\fR. The resulting code would +look like this: +.Sp +.Vb 9 +\& { +\& if (a) +\& { +\& if (b) +\& foo (); +\& else +\& bar (); +\& } +\& } +.Ve +.Sp +Also warn for dangerous uses of the +?: with omitted middle operand \s-1GNU\s0 extension. When the condition +in the ?: operator is a boolean expression the omitted value will +be always 1. Often the user expects it to be a value computed +inside the conditional expression instead. +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wsequence\-point\fR" 4 +.IX Item "-Wsequence-point" +Warn about code that may have undefined semantics because of violations +of sequence point rules in the C and \*(C+ standards. +.Sp +The C and \*(C+ standards defines the order in which expressions in a C/\*(C+ +program are evaluated in terms of \fIsequence points\fR, which represent +a partial ordering between the execution of parts of the program: those +executed before the sequence point, and those executed after it. These +occur after the evaluation of a full expression (one which is not part +of a larger expression), after the evaluation of the first operand of a +\&\f(CW\*(C`&&\*(C'\fR, \f(CW\*(C`||\*(C'\fR, \f(CW\*(C`? :\*(C'\fR or \f(CW\*(C`,\*(C'\fR (comma) operator, before a +function is called (but after the evaluation of its arguments and the +expression denoting the called function), and in certain other places. +Other than as expressed by the sequence point rules, the order of +evaluation of subexpressions of an expression is not specified. All +these rules describe only a partial order rather than a total order, +since, for example, if two functions are called within one expression +with no sequence point between them, the order in which the functions +are called is not specified. However, the standards committee have +ruled that function calls do not overlap. +.Sp +It is not specified when between sequence points modifications to the +values of objects take effect. Programs whose behavior depends on this +have undefined behavior; the C and \*(C+ standards specify that \*(L"Between +the previous and next sequence point an object shall have its stored +value modified at most once by the evaluation of an expression. +Furthermore, the prior value shall be read only to determine the value +to be stored.\*(R". If a program breaks these rules, the results on any +particular implementation are entirely unpredictable. +.Sp +Examples of code with undefined behavior are \f(CW\*(C`a = a++;\*(C'\fR, \f(CW\*(C`a[n] += b[n++]\*(C'\fR and \f(CW\*(C`a[i++] = i;\*(C'\fR. Some more complicated cases are not +diagnosed by this option, and it may give an occasional false positive +result, but in general it has been found fairly effective at detecting +this sort of problem in programs. +.Sp +The standard is worded confusingly, therefore there is some debate +over the precise meaning of the sequence point rules in subtle cases. +Links to discussions of the problem, including proposed formal +definitions, may be found on the \s-1GCC\s0 readings page, at +<\fBhttp://gcc.gnu.org/readings.html\fR>. +.Sp +This warning is enabled by \fB\-Wall\fR for C and \*(C+. +.IP "\fB\-Wself\-assign\fR" 4 +.IX Item "-Wself-assign" +Warn about self-assignment and self-initialization. This warning is intended +for detecting accidental self-assignment due to typos, and therefore does +not warn on a statement that is semantically a self-assignment after +constant folding. Here is an example of what will trigger a self-assign +warning and what will not: +.Sp +.Vb 6 +\& void func() +\& { +\& int i = 2; +\& int x = x; /* warn */ +\& float f = 5.0; +\& double a[3]; +\& +\& i = i + 0; /* not warn */ +\& f = f / 1; /* not warn */ +\& a[1] = a[1]; /* warn */ +\& i += 0; /* not warn */ +\& } +.Ve +.Sp +In \*(C+ it will not warn on self-assignment of non-POD variables unless +\&\fB\-Wself\-assign\-non\-pod\fR is also enabled. +.IP "\fB\-Wself\-assign\-non\-pod\fR" 4 +.IX Item "-Wself-assign-non-pod" +Warn about self-assignment of non-POD variables. This is a \*(C+\-specific +warning and only effective when \fB\-Wself\-assign\fR is enabled. +.Sp +There are cases where self-assignment might be intentional. For example, +a \*(C+ programmer might write code to test whether an overloaded +\&\f(CW\*(C`operator=\*(C'\fR works when the same object is assigned to itself. +One way to work around the self-assign warning in such cases when this flag +is enabled is using the functional form \f(CW\*(C`object.operator=(object)\*(C'\fR +instead of the assignment form \f(CW\*(C`object = object\*(C'\fR, as shown in the +following example. +.Sp +.Vb 3 +\& void test_func() +\& { +\& MyType t; +\& +\& t.operator=(t); // not warn +\& t = t; // warn +\& } +.Ve +.IP "\fB\-Wreturn\-type\fR" 4 +.IX Item "-Wreturn-type" +Warn whenever a function is defined with a return-type that defaults +to \f(CW\*(C`int\*(C'\fR. Also warn about any \f(CW\*(C`return\*(C'\fR statement with no +return-value in a function whose return-type is not \f(CW\*(C`void\*(C'\fR +(falling off the end of the function body is considered returning +without a value), and about a \f(CW\*(C`return\*(C'\fR statement with an +expression in a function whose return-type is \f(CW\*(C`void\*(C'\fR. +.Sp +For \*(C+, a function without return type always produces a diagnostic +message, even when \fB\-Wno\-return\-type\fR is specified. The only +exceptions are \fBmain\fR and functions defined in system headers. +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wripa\-opt\-mismatch\fR" 4 +.IX Item "-Wripa-opt-mismatch" +When doing an \s-1FDO\s0 build with \fB\-fprofile\-use\fR and \fB\-fripa\fR, +warn if importing an axuiliary module that was built with a different +\&\s-1GCC\s0 command line during the profile-generate phase than the primary +module. +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wswitch\fR" 4 +.IX Item "-Wswitch" +Warn whenever a \f(CW\*(C`switch\*(C'\fR statement has an index of enumerated type +and lacks a \f(CW\*(C`case\*(C'\fR for one or more of the named codes of that +enumeration. (The presence of a \f(CW\*(C`default\*(C'\fR label prevents this +warning.) \f(CW\*(C`case\*(C'\fR labels outside the enumeration range also +provoke warnings when this option is used (even if there is a +\&\f(CW\*(C`default\*(C'\fR label). +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wswitch\-default\fR" 4 +.IX Item "-Wswitch-default" +Warn whenever a \f(CW\*(C`switch\*(C'\fR statement does not have a \f(CW\*(C`default\*(C'\fR +case. +.IP "\fB\-Wswitch\-enum\fR" 4 +.IX Item "-Wswitch-enum" +Warn whenever a \f(CW\*(C`switch\*(C'\fR statement has an index of enumerated type +and lacks a \f(CW\*(C`case\*(C'\fR for one or more of the named codes of that +enumeration. \f(CW\*(C`case\*(C'\fR labels outside the enumeration range also +provoke warnings when this option is used. The only difference +between \fB\-Wswitch\fR and this option is that this option gives a +warning about an omitted enumeration code even if there is a +\&\f(CW\*(C`default\*(C'\fR label. +.IP "\fB\-Wsync\-nand\fR (C and \*(C+ only)" 4 +.IX Item "-Wsync-nand (C and only)" +Warn when \f(CW\*(C`_\|_sync_fetch_and_nand\*(C'\fR and \f(CW\*(C`_\|_sync_nand_and_fetch\*(C'\fR +built-in functions are used. These functions changed semantics in \s-1GCC\s0 4.4. +.IP "\fB\-Wthread\-safety\fR" 4 +.IX Item "-Wthread-safety" +Warn about potential thread safety issues when the code is annotated with +thread safety attributes. +.IP "\fBWthread-unguarded-var\fR" 4 +.IX Item "Wthread-unguarded-var" +Warn about shared variables not properly protected by locks specified in the +attributes. This flag is effective only with \fB\-Wthread\-safety\fR and +enabled by default. +.IP "\fBWthread-unguarded-func\fR" 4 +.IX Item "Wthread-unguarded-func" +Warn about function calls not properly protected by locks specified in the +attributes. This flag is effective only with \fB\-Wthread\-safety\fR and +enabled by default. +.IP "\fBWthread-mismatched-lock-order\fR" 4 +.IX Item "Wthread-mismatched-lock-order" +Warn about lock acquisition order inconsistent with what specified in the +attributes. This flag is effective only with \fB\-Wthread\-safety\fR and +enabled by default. +.IP "\fBWthread-mismatched-lock-acq-rel\fR" 4 +.IX Item "Wthread-mismatched-lock-acq-rel" +Warn about mismatched lock acquisition and release. This flag is effective only +with \fB\-Wthread\-safety\fR and enabled by default. +.IP "\fBWthread-reentrant-lock\fR" 4 +.IX Item "Wthread-reentrant-lock" +Warn about a lock being acquired recursively. This flag is effective only +with \fB\-Wthread\-safety\fR and enabled by default. +.IP "\fBWthread-unsupported-lock-name\fR" 4 +.IX Item "Wthread-unsupported-lock-name" +Warn about uses of unsupported lock names in attributes. This flag is effective +only with \fB\-Wthread\-safety\fR and disabled by default. +.IP "\fBWthread-attr-bind-param\fR" 4 +.IX Item "Wthread-attr-bind-param" +Make the thread safety analysis try to bind the function parameters used in +the attributes. This flag is effective only with \fB\-Wthread\-safety\fR +and enabled by default. +.IP "\fB\-Wtrigraphs\fR" 4 +.IX Item "-Wtrigraphs" +Warn if any trigraphs are encountered that might change the meaning of +the program (trigraphs within comments are not warned about). +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wunused\-but\-set\-parameter\fR" 4 +.IX Item "-Wunused-but-set-parameter" +Warn whenever a function parameter is assigned to, but otherwise unused +(aside from its declaration). +.Sp +To suppress this warning use the \fBunused\fR attribute. +.Sp +This warning is also enabled by \fB\-Wunused\fR together with +\&\fB\-Wextra\fR. +.IP "\fB\-Wunused\-but\-set\-variable\fR" 4 +.IX Item "-Wunused-but-set-variable" +Warn whenever a local variable is assigned to, but otherwise unused +(aside from its declaration). +This warning is enabled by \fB\-Wall\fR. +.Sp +To suppress this warning use the \fBunused\fR attribute. +.Sp +This warning is also enabled by \fB\-Wunused\fR, which is enabled +by \fB\-Wall\fR. +.IP "\fB\-Wunused\-function\fR" 4 +.IX Item "-Wunused-function" +Warn whenever a static function is declared but not defined or a +non-inline static function is unused. +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wunused\-label\fR" 4 +.IX Item "-Wunused-label" +Warn whenever a label is declared but not used. +This warning is enabled by \fB\-Wall\fR. +.Sp +To suppress this warning use the \fBunused\fR attribute. +.IP "\fB\-Wunused\-parameter\fR" 4 +.IX Item "-Wunused-parameter" +Warn whenever a function parameter is unused aside from its declaration. +.Sp +To suppress this warning use the \fBunused\fR attribute. +.IP "\fB\-Wno\-unused\-result\fR" 4 +.IX Item "-Wno-unused-result" +Do not warn if a caller of a function marked with attribute +\&\f(CW\*(C`warn_unused_result\*(C'\fR does not use +its return value. The default is \fB\-Wunused\-result\fR. +.IP "\fB\-Wunused\-variable\fR" 4 +.IX Item "-Wunused-variable" +Warn whenever a local variable or non-constant static variable is unused +aside from its declaration. +This warning is enabled by \fB\-Wall\fR. +.Sp +To suppress this warning use the \fBunused\fR attribute. +.Sp +Note that a classic way to avoid \fB\-Wunused\-variable\fR warning is +using \f(CW\*(C`x = x\*(C'\fR, but that does not work with \fB\-Wself\-assign\fR. +Use \f(CW\*(C`(void) x\*(C'\fR or \f(CW\*(C`static_cast<void>(x)\*(C'\fR instead. +.IP "\fB\-Wunused\-value\fR" 4 +.IX Item "-Wunused-value" +Warn whenever a statement computes a result that is explicitly not +used. To suppress this warning cast the unused expression to +\&\fBvoid\fR. This includes an expression-statement or the left-hand +side of a comma expression that contains no side effects. For example, +an expression such as \fBx[i,j]\fR will cause a warning, while +\&\fBx[(void)i,j]\fR will not. +.Sp +This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wunused\fR" 4 +.IX Item "-Wunused" +All the above \fB\-Wunused\fR options combined. +.Sp +In order to get a warning about an unused function parameter, you must +either specify \fB\-Wextra \-Wunused\fR (note that \fB\-Wall\fR implies +\&\fB\-Wunused\fR), or separately specify \fB\-Wunused\-parameter\fR. +.IP "\fB\-Wuninitialized\fR" 4 +.IX Item "-Wuninitialized" +Warn if an automatic variable is used without first being initialized +or if a variable may be clobbered by a \f(CW\*(C`setjmp\*(C'\fR call. In \*(C+, +warn if a non-static reference or non-static \fBconst\fR member +appears in a class without constructors. +.Sp +If you want to warn about code which uses the uninitialized value of the +variable in its own initializer, use the \fB\-Winit\-self\fR option. +.Sp +These warnings occur for individual uninitialized or clobbered +elements of structure, union or array variables as well as for +variables which are uninitialized or clobbered as a whole. They do +not occur for variables or elements declared \f(CW\*(C`volatile\*(C'\fR. Because +these warnings depend on optimization, the exact variables or elements +for which there are warnings will depend on the precise optimization +options and version of \s-1GCC\s0 used. +.Sp +Note that there may be no warning about a variable that is used only +to compute a value that itself is never used, because such +computations may be deleted by data flow analysis before the warnings +are printed. +.IP "\fB\-Wmaybe\-uninitialized\fR" 4 +.IX Item "-Wmaybe-uninitialized" +For an automatic variable, if there exists a path from the function +entry to a use of the variable that is initialized, but there exist +some other paths the variable is not initialized, the compiler will +emit a warning if it can not prove the uninitialized paths do not +happen at runtime. These warnings are made optional because \s-1GCC\s0 is +not smart enough to see all the reasons why the code might be correct +despite appearing to have an error. Here is one example of how +this can happen: +.Sp +.Vb 12 +\& { +\& int x; +\& switch (y) +\& { +\& case 1: x = 1; +\& break; +\& case 2: x = 4; +\& break; +\& case 3: x = 5; +\& } +\& foo (x); +\& } +.Ve +.Sp +If the value of \f(CW\*(C`y\*(C'\fR is always 1, 2 or 3, then \f(CW\*(C`x\*(C'\fR is +always initialized, but \s-1GCC\s0 doesn't know this. To suppress the +warning, the user needs to provide a default case with \fIassert\fR\|(0) or +similar code. +.Sp +This option also warns when a non-volatile automatic variable might be +changed by a call to \f(CW\*(C`longjmp\*(C'\fR. These warnings as well are possible +only in optimizing compilation. +.Sp +The compiler sees only the calls to \f(CW\*(C`setjmp\*(C'\fR. It cannot know +where \f(CW\*(C`longjmp\*(C'\fR will be called; in fact, a signal handler could +call it at any point in the code. As a result, you may get a warning +even when there is in fact no problem because \f(CW\*(C`longjmp\*(C'\fR cannot +in fact be called at the place which would cause a problem. +.Sp +Some spurious warnings can be avoided if you declare all the functions +you use that never return as \f(CW\*(C`noreturn\*(C'\fR. +.Sp +This warning is enabled by \fB\-Wall\fR or \fB\-Wextra\fR. +.IP "\fB\-Wunknown\-pragmas\fR" 4 +.IX Item "-Wunknown-pragmas" +Warn when a #pragma directive is encountered which is not understood by +\&\s-1GCC\s0. If this command line option is used, warnings will even be issued +for unknown pragmas in system header files. This is not the case if +the warnings were only enabled by the \fB\-Wall\fR command line option. +.IP "\fB\-Wno\-pragmas\fR" 4 +.IX Item "-Wno-pragmas" +Do not warn about misuses of pragmas, such as incorrect parameters, +invalid syntax, or conflicts between pragmas. See also +\&\fB\-Wunknown\-pragmas\fR. +.IP "\fB\-Wstrict\-aliasing\fR" 4 +.IX Item "-Wstrict-aliasing" +This option is only active when \fB\-fstrict\-aliasing\fR is active. +It warns about code which might break the strict aliasing rules that the +compiler is using for optimization. The warning does not catch all +cases, but does attempt to catch the more common pitfalls. It is +included in \fB\-Wall\fR. +It is equivalent to \fB\-Wstrict\-aliasing=3\fR +.IP "\fB\-Wstrict\-aliasing=n\fR" 4 +.IX Item "-Wstrict-aliasing=n" +This option is only active when \fB\-fstrict\-aliasing\fR is active. +It warns about code which might break the strict aliasing rules that the +compiler is using for optimization. +Higher levels correspond to higher accuracy (fewer false positives). +Higher levels also correspond to more effort, similar to the way \-O works. +\&\fB\-Wstrict\-aliasing\fR is equivalent to \fB\-Wstrict\-aliasing=n\fR, +with n=3. +.Sp +Level 1: Most aggressive, quick, least accurate. +Possibly useful when higher levels +do not warn but \-fstrict\-aliasing still breaks the code, as it has very few +false negatives. However, it has many false positives. +Warns for all pointer conversions between possibly incompatible types, +even if never dereferenced. Runs in the frontend only. +.Sp +Level 2: Aggressive, quick, not too precise. +May still have many false positives (not as many as level 1 though), +and few false negatives (but possibly more than level 1). +Unlike level 1, it only warns when an address is taken. Warns about +incomplete types. Runs in the frontend only. +.Sp +Level 3 (default for \fB\-Wstrict\-aliasing\fR): +Should have very few false positives and few false +negatives. Slightly slower than levels 1 or 2 when optimization is enabled. +Takes care of the common pun+dereference pattern in the frontend: +\&\f(CW\*(C`*(int*)&some_float\*(C'\fR. +If optimization is enabled, it also runs in the backend, where it deals +with multiple statement cases using flow-sensitive points-to information. +Only warns when the converted pointer is dereferenced. +Does not warn about incomplete types. +.IP "\fB\-Wstrict\-overflow\fR" 4 +.IX Item "-Wstrict-overflow" +.PD 0 +.IP "\fB\-Wstrict\-overflow=\fR\fIn\fR" 4 +.IX Item "-Wstrict-overflow=n" +.PD +This option is only active when \fB\-fstrict\-overflow\fR is active. +It warns about cases where the compiler optimizes based on the +assumption that signed overflow does not occur. Note that it does not +warn about all cases where the code might overflow: it only warns +about cases where the compiler implements some optimization. Thus +this warning depends on the optimization level. +.Sp +An optimization which assumes that signed overflow does not occur is +perfectly safe if the values of the variables involved are such that +overflow never does, in fact, occur. Therefore this warning can +easily give a false positive: a warning about code which is not +actually a problem. To help focus on important issues, several +warning levels are defined. No warnings are issued for the use of +undefined signed overflow when estimating how many iterations a loop +will require, in particular when determining whether a loop will be +executed at all. +.RS 4 +.IP "\fB\-Wstrict\-overflow=1\fR" 4 +.IX Item "-Wstrict-overflow=1" +Warn about cases which are both questionable and easy to avoid. For +example: \f(CW\*(C`x + 1 > x\*(C'\fR; with \fB\-fstrict\-overflow\fR, the +compiler will simplify this to \f(CW1\fR. This level of +\&\fB\-Wstrict\-overflow\fR is enabled by \fB\-Wall\fR; higher levels +are not, and must be explicitly requested. +.IP "\fB\-Wstrict\-overflow=2\fR" 4 +.IX Item "-Wstrict-overflow=2" +Also warn about other cases where a comparison is simplified to a +constant. For example: \f(CW\*(C`abs (x) >= 0\*(C'\fR. This can only be +simplified when \fB\-fstrict\-overflow\fR is in effect, because +\&\f(CW\*(C`abs (INT_MIN)\*(C'\fR overflows to \f(CW\*(C`INT_MIN\*(C'\fR, which is less than +zero. \fB\-Wstrict\-overflow\fR (with no level) is the same as +\&\fB\-Wstrict\-overflow=2\fR. +.IP "\fB\-Wstrict\-overflow=3\fR" 4 +.IX Item "-Wstrict-overflow=3" +Also warn about other cases where a comparison is simplified. For +example: \f(CW\*(C`x + 1 > 1\*(C'\fR will be simplified to \f(CW\*(C`x > 0\*(C'\fR. +.IP "\fB\-Wstrict\-overflow=4\fR" 4 +.IX Item "-Wstrict-overflow=4" +Also warn about other simplifications not covered by the above cases. +For example: \f(CW\*(C`(x * 10) / 5\*(C'\fR will be simplified to \f(CW\*(C`x * 2\*(C'\fR. +.IP "\fB\-Wstrict\-overflow=5\fR" 4 +.IX Item "-Wstrict-overflow=5" +Also warn about cases where the compiler reduces the magnitude of a +constant involved in a comparison. For example: \f(CW\*(C`x + 2 > y\*(C'\fR will +be simplified to \f(CW\*(C`x + 1 >= y\*(C'\fR. This is reported only at the +highest warning level because this simplification applies to many +comparisons, so this warning level will give a very large number of +false positives. +.RE +.RS 4 +.RE +.IP "\fB\-Wsuggest\-attribute=\fR[\fBpure\fR|\fBconst\fR|\fBnoreturn\fR]" 4 +.IX Item "-Wsuggest-attribute=[pure|const|noreturn]" +Warn for cases where adding an attribute may be beneficial. The +attributes currently supported are listed below. +.RS 4 +.IP "\fB\-Wsuggest\-attribute=pure\fR" 4 +.IX Item "-Wsuggest-attribute=pure" +.PD 0 +.IP "\fB\-Wsuggest\-attribute=const\fR" 4 +.IX Item "-Wsuggest-attribute=const" +.IP "\fB\-Wsuggest\-attribute=noreturn\fR" 4 +.IX Item "-Wsuggest-attribute=noreturn" +.PD +Warn about functions which might be candidates for attributes +\&\f(CW\*(C`pure\*(C'\fR, \f(CW\*(C`const\*(C'\fR or \f(CW\*(C`noreturn\*(C'\fR. The compiler only warns for +functions visible in other compilation units or (in the case of \f(CW\*(C`pure\*(C'\fR and +\&\f(CW\*(C`const\*(C'\fR) if it cannot prove that the function returns normally. A function +returns normally if it doesn't contain an infinite loop nor returns abnormally +by throwing, calling \f(CW\*(C`abort()\*(C'\fR or trapping. This analysis requires option +\&\fB\-fipa\-pure\-const\fR, which is enabled by default at \fB\-O\fR and +higher. Higher optimization levels improve the accuracy of the analysis. +.RE +.RS 4 +.RE +.IP "\fB\-Warray\-bounds\fR" 4 +.IX Item "-Warray-bounds" +This option is only active when \fB\-ftree\-vrp\fR is active +(default for \fB\-O2\fR and above). It warns about subscripts to arrays +that are always out of bounds. This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wno\-div\-by\-zero\fR" 4 +.IX Item "-Wno-div-by-zero" +Do not warn about compile-time integer division by zero. Floating point +division by zero is not warned about, as it can be a legitimate way of +obtaining infinities and NaNs. +.IP "\fB\-Wsystem\-headers\fR" 4 +.IX Item "-Wsystem-headers" +Print warning messages for constructs found in system header files. +Warnings from system headers are normally suppressed, on the assumption +that they usually do not indicate real problems and would only make the +compiler output harder to read. Using this command line option tells +\&\s-1GCC\s0 to emit warnings from system headers as if they occurred in user +code. However, note that using \fB\-Wall\fR in conjunction with this +option will \fInot\fR warn about unknown pragmas in system +headers\-\-\-for that, \fB\-Wunknown\-pragmas\fR must also be used. +.IP "\fB\-Wtrampolines\fR" 4 +.IX Item "-Wtrampolines" +.Vb 1 +\& Warn about trampolines generated for pointers to nested functions. +\& +\& A trampoline is a small piece of data or code that is created at run +\& time on the stack when the address of a nested function is taken, and +\& is used to call the nested function indirectly. For some targets, it +\& is made up of data only and thus requires no special treatment. But, +\& for most targets, it is made up of code and thus requires the stack +\& to be made executable in order for the program to work properly. +.Ve +.IP "\fB\-Wfloat\-equal\fR" 4 +.IX Item "-Wfloat-equal" +Warn if floating point values are used in equality comparisons. +.Sp +The idea behind this is that sometimes it is convenient (for the +programmer) to consider floating-point values as approximations to +infinitely precise real numbers. If you are doing this, then you need +to compute (by analyzing the code, or in some other way) the maximum or +likely maximum error that the computation introduces, and allow for it +when performing comparisons (and when producing output, but that's a +different problem). In particular, instead of testing for equality, you +would check to see whether the two values have ranges that overlap; and +this is done with the relational operators, so equality comparisons are +probably mistaken. +.IP "\fB\-Wtraditional\fR (C and Objective-C only)" 4 +.IX Item "-Wtraditional (C and Objective-C only)" +Warn about certain constructs that behave differently in traditional and +\&\s-1ISO\s0 C. Also warn about \s-1ISO\s0 C constructs that have no traditional C +equivalent, and/or problematic constructs which should be avoided. +.RS 4 +.IP "\(bu" 4 +Macro parameters that appear within string literals in the macro body. +In traditional C macro replacement takes place within string literals, +but does not in \s-1ISO\s0 C. +.IP "\(bu" 4 +In traditional C, some preprocessor directives did not exist. +Traditional preprocessors would only consider a line to be a directive +if the \fB#\fR appeared in column 1 on the line. Therefore +\&\fB\-Wtraditional\fR warns about directives that traditional C +understands but would ignore because the \fB#\fR does not appear as the +first character on the line. It also suggests you hide directives like +\&\fB#pragma\fR not understood by traditional C by indenting them. Some +traditional implementations would not recognize \fB#elif\fR, so it +suggests avoiding it altogether. +.IP "\(bu" 4 +A function-like macro that appears without arguments. +.IP "\(bu" 4 +The unary plus operator. +.IP "\(bu" 4 +The \fBU\fR integer constant suffix, or the \fBF\fR or \fBL\fR floating point +constant suffixes. (Traditional C does support the \fBL\fR suffix on integer +constants.) Note, these suffixes appear in macros defined in the system +headers of most modern systems, e.g. the \fB_MIN\fR/\fB_MAX\fR macros in \f(CW\*(C`<limits.h>\*(C'\fR. +Use of these macros in user code might normally lead to spurious +warnings, however \s-1GCC\s0's integrated preprocessor has enough context to +avoid warning in these cases. +.IP "\(bu" 4 +A function declared external in one block and then used after the end of +the block. +.IP "\(bu" 4 +A \f(CW\*(C`switch\*(C'\fR statement has an operand of type \f(CW\*(C`long\*(C'\fR. +.IP "\(bu" 4 +A non\-\f(CW\*(C`static\*(C'\fR function declaration follows a \f(CW\*(C`static\*(C'\fR one. +This construct is not accepted by some traditional C compilers. +.IP "\(bu" 4 +The \s-1ISO\s0 type of an integer constant has a different width or +signedness from its traditional type. This warning is only issued if +the base of the constant is ten. I.e. hexadecimal or octal values, which +typically represent bit patterns, are not warned about. +.IP "\(bu" 4 +Usage of \s-1ISO\s0 string concatenation is detected. +.IP "\(bu" 4 +Initialization of automatic aggregates. +.IP "\(bu" 4 +Identifier conflicts with labels. Traditional C lacks a separate +namespace for labels. +.IP "\(bu" 4 +Initialization of unions. If the initializer is zero, the warning is +omitted. This is done under the assumption that the zero initializer in +user code appears conditioned on e.g. \f(CW\*(C`_\|_STDC_\|_\*(C'\fR to avoid missing +initializer warnings and relies on default initialization to zero in the +traditional C case. +.IP "\(bu" 4 +Conversions by prototypes between fixed/floating point values and vice +versa. The absence of these prototypes when compiling with traditional +C would cause serious problems. This is a subset of the possible +conversion warnings, for the full set use \fB\-Wtraditional\-conversion\fR. +.IP "\(bu" 4 +Use of \s-1ISO\s0 C style function definitions. This warning intentionally is +\&\fInot\fR issued for prototype declarations or variadic functions +because these \s-1ISO\s0 C features will appear in your code when using +libiberty's traditional C compatibility macros, \f(CW\*(C`PARAMS\*(C'\fR and +\&\f(CW\*(C`VPARAMS\*(C'\fR. This warning is also bypassed for nested functions +because that feature is already a \s-1GCC\s0 extension and thus not relevant to +traditional C compatibility. +.RE +.RS 4 +.RE +.IP "\fB\-Wtraditional\-conversion\fR (C and Objective-C only)" 4 +.IX Item "-Wtraditional-conversion (C and Objective-C only)" +Warn if a prototype causes a type conversion that is different from what +would happen to the same argument in the absence of a prototype. This +includes conversions of fixed point to floating and vice versa, and +conversions changing the width or signedness of a fixed point argument +except when the same as the default promotion. +.IP "\fB\-Wdeclaration\-after\-statement\fR (C and Objective-C only)" 4 +.IX Item "-Wdeclaration-after-statement (C and Objective-C only)" +Warn when a declaration is found after a statement in a block. This +construct, known from \*(C+, was introduced with \s-1ISO\s0 C99 and is by default +allowed in \s-1GCC\s0. It is not supported by \s-1ISO\s0 C90 and was not supported by +\&\s-1GCC\s0 versions before \s-1GCC\s0 3.0. +.IP "\fB\-Wundef\fR" 4 +.IX Item "-Wundef" +Warn if an undefined identifier is evaluated in an \fB#if\fR directive. +.IP "\fB\-Wno\-endif\-labels\fR" 4 +.IX Item "-Wno-endif-labels" +Do not warn whenever an \fB#else\fR or an \fB#endif\fR are followed by text. +.IP "\fB\-Wshadow\fR" 4 +.IX Item "-Wshadow" +Warn whenever a local variable or type declaration shadows another variable, +parameter, type, or class member (in \*(C+), or whenever a built-in function +is shadowed. Note that in \*(C+, the compiler will not warn if a local variable +shadows a struct/class/enum, but will warn if it shadows an explicit typedef. +.IP "\fB\-Wshadow\-local\fR" 4 +.IX Item "-Wshadow-local" +Warn when a local variable shadows another local variable or parameter. +.IP "\fB\-Wshadow\-compatible\-local\fR" 4 +.IX Item "-Wshadow-compatible-local" +Warn when a local variable shadows another local variable or parameter +whose type is compatible with that of the shadowing variable. In \*(C+, +type compatibility here means the type of the shadowing variable can be +converted to that of the shadowed variable. The creation of this flag +(in addition to \fB\-Wshadow\-local\fR) is based on the idea that when +a local variable shadows another one of incompatible type, it is most +likely intentional, not a bug or typo, as shown in the following example: +.Sp +.Vb 8 +\& for (SomeIterator i = SomeObj.begin(); i != SomeObj.end(); ++i) +\& { +\& for (int i = 0; i < N; ++i) +\& { +\& ... +\& } +\& ... +\& } +.Ve +.Sp +Since the two variable \f(CW\*(C`i\*(C'\fR in the example above have incompatible types, +enabling only \fB\-Wshadow\-compatible\-local\fR will not emit a warning. +Because their types are incompatible, if a programmer accidentally uses one +in place of the other, type checking will catch that and emit an error or +warning. So not warning (about shadowing) in this case will not lead to +undetected bugs. Use of this flag instead of \fB\-Wshadow\-local\fR can +possibly reduce the number of warnings triggered by intentional shadowing. +.IP "\fB\-Wlarger\-than=\fR\fIlen\fR" 4 +.IX Item "-Wlarger-than=len" +Warn whenever an object of larger than \fIlen\fR bytes is defined. +.IP "\fB\-Wframe\-larger\-than=\fR\fIlen\fR" 4 +.IX Item "-Wframe-larger-than=len" +Warn if the size of a function frame is larger than \fIlen\fR bytes. +The computation done to determine the stack frame size is approximate +and not conservative. +The actual requirements may be somewhat greater than \fIlen\fR +even if you do not get a warning. In addition, any space allocated +via \f(CW\*(C`alloca\*(C'\fR, variable-length arrays, or related constructs +is not included by the compiler when determining +whether or not to issue a warning. +.IP "\fB\-Wunsafe\-loop\-optimizations\fR" 4 +.IX Item "-Wunsafe-loop-optimizations" +Warn if the loop cannot be optimized because the compiler could not +assume anything on the bounds of the loop indices. With +\&\fB\-funsafe\-loop\-optimizations\fR warn if the compiler made +such assumptions. +.IP "\fB\-Wno\-pedantic\-ms\-format\fR (MinGW targets only)" 4 +.IX Item "-Wno-pedantic-ms-format (MinGW targets only)" +Disables the warnings about non-ISO \f(CW\*(C`printf\*(C'\fR / \f(CW\*(C`scanf\*(C'\fR format +width specifiers \f(CW\*(C`I32\*(C'\fR, \f(CW\*(C`I64\*(C'\fR, and \f(CW\*(C`I\*(C'\fR used on Windows targets +depending on the \s-1MS\s0 runtime, when you are using the options \fB\-Wformat\fR +and \fB\-pedantic\fR without gnu-extensions. +.IP "\fB\-Wpointer\-arith\fR" 4 +.IX Item "-Wpointer-arith" +Warn about anything that depends on the \*(L"size of\*(R" a function type or +of \f(CW\*(C`void\*(C'\fR. \s-1GNU\s0 C assigns these types a size of 1, for +convenience in calculations with \f(CW\*(C`void *\*(C'\fR pointers and pointers +to functions. In \*(C+, warn also when an arithmetic operation involves +\&\f(CW\*(C`NULL\*(C'\fR. This warning is also enabled by \fB\-pedantic\fR. +.IP "\fB\-Wtype\-limits\fR" 4 +.IX Item "-Wtype-limits" +Warn if a comparison is always true or always false due to the limited +range of the data type, but do not warn for constant expressions. For +example, warn if an unsigned variable is compared against zero with +\&\fB<\fR or \fB>=\fR. This warning is also enabled by +\&\fB\-Wextra\fR. +.IP "\fB\-Wbad\-function\-cast\fR (C and Objective-C only)" 4 +.IX Item "-Wbad-function-cast (C and Objective-C only)" +Warn whenever a function call is cast to a non-matching type. +For example, warn if \f(CW\*(C`int malloc()\*(C'\fR is cast to \f(CW\*(C`anything *\*(C'\fR. +.IP "\fB\-Wc++\-compat\fR (C and Objective-C only)" 4 +.IX Item "-Wc++-compat (C and Objective-C only)" +Warn about \s-1ISO\s0 C constructs that are outside of the common subset of +\&\s-1ISO\s0 C and \s-1ISO\s0 \*(C+, e.g. request for implicit conversion from +\&\f(CW\*(C`void *\*(C'\fR to a pointer to non\-\f(CW\*(C`void\*(C'\fR type. +.IP "\fB\-Wc++0x\-compat\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wc++0x-compat ( and Objective- only)" +Warn about \*(C+ constructs whose meaning differs between \s-1ISO\s0 \*(C+ 1998 and +\&\s-1ISO\s0 \*(C+ 200x, e.g., identifiers in \s-1ISO\s0 \*(C+ 1998 that will become keywords +in \s-1ISO\s0 \*(C+ 200x. This warning is enabled by \fB\-Wall\fR. +.IP "\fB\-Wcast\-qual\fR" 4 +.IX Item "-Wcast-qual" +Warn whenever a pointer is cast so as to remove a type qualifier from +the target type. For example, warn if a \f(CW\*(C`const char *\*(C'\fR is cast +to an ordinary \f(CW\*(C`char *\*(C'\fR. +.Sp +Also warn when making a cast which introduces a type qualifier in an +unsafe way. For example, casting \f(CW\*(C`char **\*(C'\fR to \f(CW\*(C`const char **\*(C'\fR +is unsafe, as in this example: +.Sp +.Vb 6 +\& /* p is char ** value. */ +\& const char **q = (const char **) p; +\& /* Assignment of readonly string to const char * is OK. */ +\& *q = "string"; +\& /* Now char** pointer points to read\-only memory. */ +\& **p = \*(Aqb\*(Aq; +.Ve +.IP "\fB\-Wcast\-align\fR" 4 +.IX Item "-Wcast-align" +Warn whenever a pointer is cast such that the required alignment of the +target is increased. For example, warn if a \f(CW\*(C`char *\*(C'\fR is cast to +an \f(CW\*(C`int *\*(C'\fR on machines where integers can only be accessed at +two\- or four-byte boundaries. +.IP "\fB\-Wwrite\-strings\fR" 4 +.IX Item "-Wwrite-strings" +When compiling C, give string constants the type \f(CW\*(C`const +char[\f(CIlength\f(CW]\*(C'\fR so that copying the address of one into a +non\-\f(CW\*(C`const\*(C'\fR \f(CW\*(C`char *\*(C'\fR pointer will get a warning. These +warnings will help you find at compile time code that can try to write +into a string constant, but only if you have been very careful about +using \f(CW\*(C`const\*(C'\fR in declarations and prototypes. Otherwise, it will +just be a nuisance. This is why we did not make \fB\-Wall\fR request +these warnings. +.Sp +When compiling \*(C+, warn about the deprecated conversion from string +literals to \f(CW\*(C`char *\*(C'\fR. This warning is enabled by default for \*(C+ +programs. +.IP "\fB\-Wclobbered\fR" 4 +.IX Item "-Wclobbered" +Warn for variables that might be changed by \fBlongjmp\fR or +\&\fBvfork\fR. This warning is also enabled by \fB\-Wextra\fR. +.IP "\fB\-Wconversion\fR" 4 +.IX Item "-Wconversion" +Warn for implicit conversions that may alter a value. This includes +conversions between real and integer, like \f(CW\*(C`abs (x)\*(C'\fR when +\&\f(CW\*(C`x\*(C'\fR is \f(CW\*(C`double\*(C'\fR; conversions between signed and unsigned, +like \f(CW\*(C`unsigned ui = \-1\*(C'\fR; and conversions to smaller types, like +\&\f(CW\*(C`sqrtf (M_PI)\*(C'\fR. Do not warn for explicit casts like \f(CW\*(C`abs +((int) x)\*(C'\fR and \f(CW\*(C`ui = (unsigned) \-1\*(C'\fR, or if the value is not +changed by the conversion like in \f(CW\*(C`abs (2.0)\*(C'\fR. Warnings about +conversions between signed and unsigned integers can be disabled by +using \fB\-Wno\-sign\-conversion\fR. +.Sp +For \*(C+, also warn for confusing overload resolution for user-defined +conversions; and conversions that will never use a type conversion +operator: conversions to \f(CW\*(C`void\*(C'\fR, the same type, a base class or a +reference to them. Warnings about conversions between signed and +unsigned integers are disabled by default in \*(C+ unless +\&\fB\-Wsign\-conversion\fR is explicitly enabled. +.IP "\fB\-Wno\-conversion\-null\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-conversion-null ( and Objective- only)" +Do not warn for conversions between \f(CW\*(C`NULL\*(C'\fR and non-pointer +types. \fB\-Wconversion\-null\fR is enabled by default. +.IP "\fB\-Wreal\-conversion\fR" 4 +.IX Item "-Wreal-conversion" +Warn for implicit type conversions from real (\f(CW\*(C`double\*(C'\fR or \f(CW\*(C`float\*(C'\fR) +to integral values. +.IP "\fB\-Wempty\-body\fR" 4 +.IX Item "-Wempty-body" +Warn if an empty body occurs in an \fBif\fR, \fBelse\fR or \fBdo +while\fR statement. This warning is also enabled by \fB\-Wextra\fR. +.IP "\fB\-Wenum\-compare\fR" 4 +.IX Item "-Wenum-compare" +Warn about a comparison between values of different enum types. In \*(C+ +this warning is enabled by default. In C this warning is enabled by +\&\fB\-Wall\fR. +.IP "\fB\-Wjump\-misses\-init\fR (C, Objective-C only)" 4 +.IX Item "-Wjump-misses-init (C, Objective-C only)" +Warn if a \f(CW\*(C`goto\*(C'\fR statement or a \f(CW\*(C`switch\*(C'\fR statement jumps +forward across the initialization of a variable, or jumps backward to a +label after the variable has been initialized. This only warns about +variables which are initialized when they are declared. This warning is +only supported for C and Objective C; in \*(C+ this sort of branch is an +error in any case. +.Sp +\&\fB\-Wjump\-misses\-init\fR is included in \fB\-Wc++\-compat\fR. It +can be disabled with the \fB\-Wno\-jump\-misses\-init\fR option. +.IP "\fB\-Wsign\-compare\fR" 4 +.IX Item "-Wsign-compare" +Warn when a comparison between signed and unsigned values could produce +an incorrect result when the signed value is converted to unsigned. +This warning is also enabled by \fB\-Wextra\fR; to get the other warnings +of \fB\-Wextra\fR without this warning, use \fB\-Wextra \-Wno\-sign\-compare\fR. +.IP "\fB\-Wsign\-conversion\fR" 4 +.IX Item "-Wsign-conversion" +Warn for implicit conversions that may change the sign of an integer +value, like assigning a signed integer expression to an unsigned +integer variable. An explicit cast silences the warning. In C, this +option is enabled also by \fB\-Wconversion\fR. +.IP "\fB\-Waddress\fR" 4 +.IX Item "-Waddress" +Warn about suspicious uses of memory addresses. These include using +the address of a function in a conditional expression, such as +\&\f(CW\*(C`void func(void); if (func)\*(C'\fR, and comparisons against the memory +address of a string literal, such as \f(CW\*(C`if (x == "abc")\*(C'\fR. Such +uses typically indicate a programmer error: the address of a function +always evaluates to true, so their use in a conditional usually +indicate that the programmer forgot the parentheses in a function +call; and comparisons against string literals result in unspecified +behavior and are not portable in C, so they usually indicate that the +programmer intended to use \f(CW\*(C`strcmp\*(C'\fR. This warning is enabled by +\&\fB\-Wall\fR. +.IP "\fB\-Wlogical\-op\fR" 4 +.IX Item "-Wlogical-op" +Warn about suspicious uses of logical operators in expressions. +This includes using logical operators in contexts where a +bit-wise operator is likely to be expected. +.IP "\fB\-Waggregate\-return\fR" 4 +.IX Item "-Waggregate-return" +Warn if any functions that return structures or unions are defined or +called. (In languages where you can return an array, this also elicits +a warning.) +.IP "\fB\-Wno\-attributes\fR" 4 +.IX Item "-Wno-attributes" +Do not warn if an unexpected \f(CW\*(C`_\|_attribute_\|_\*(C'\fR is used, such as +unrecognized attributes, function attributes applied to variables, +etc. This will not stop errors for incorrect use of supported +attributes. +.IP "\fB\-Wno\-builtin\-macro\-redefined\fR" 4 +.IX Item "-Wno-builtin-macro-redefined" +Do not warn if certain built-in macros are redefined. This suppresses +warnings for redefinition of \f(CW\*(C`_\|_TIMESTAMP_\|_\*(C'\fR, \f(CW\*(C`_\|_TIME_\|_\*(C'\fR, +\&\f(CW\*(C`_\|_DATE_\|_\*(C'\fR, \f(CW\*(C`_\|_FILE_\|_\*(C'\fR, and \f(CW\*(C`_\|_BASE_FILE_\|_\*(C'\fR. +.IP "\fB\-Wstrict\-prototypes\fR (C and Objective-C only)" 4 +.IX Item "-Wstrict-prototypes (C and Objective-C only)" +Warn if a function is declared or defined without specifying the +argument types. (An old-style function definition is permitted without +a warning if preceded by a declaration which specifies the argument +types.) +.IP "\fB\-Wold\-style\-declaration\fR (C and Objective-C only)" 4 +.IX Item "-Wold-style-declaration (C and Objective-C only)" +Warn for obsolescent usages, according to the C Standard, in a +declaration. For example, warn if storage-class specifiers like +\&\f(CW\*(C`static\*(C'\fR are not the first things in a declaration. This warning +is also enabled by \fB\-Wextra\fR. +.IP "\fB\-Wold\-style\-definition\fR (C and Objective-C only)" 4 +.IX Item "-Wold-style-definition (C and Objective-C only)" +Warn if an old-style function definition is used. A warning is given +even if there is a previous prototype. +.IP "\fB\-Wmissing\-parameter\-type\fR (C and Objective-C only)" 4 +.IX Item "-Wmissing-parameter-type (C and Objective-C only)" +A function parameter is declared without a type specifier in K&R\-style +functions: +.Sp +.Vb 1 +\& void foo(bar) { } +.Ve +.Sp +This warning is also enabled by \fB\-Wextra\fR. +.IP "\fB\-Wmissing\-prototypes\fR (C and Objective-C only)" 4 +.IX Item "-Wmissing-prototypes (C and Objective-C only)" +Warn if a global function is defined without a previous prototype +declaration. This warning is issued even if the definition itself +provides a prototype. The aim is to detect global functions that fail +to be declared in header files. +.IP "\fB\-Wmissing\-declarations\fR" 4 +.IX Item "-Wmissing-declarations" +Warn if a global function is defined without a previous declaration. +Do so even if the definition itself provides a prototype. +Use this option to detect global functions that are not declared in +header files. In \*(C+, no warnings are issued for function templates, +or for inline functions, or for functions in anonymous namespaces. +.IP "\fB\-Wmissing\-field\-initializers\fR" 4 +.IX Item "-Wmissing-field-initializers" +Warn if a structure's initializer has some fields missing. For +example, the following code would cause such a warning, because +\&\f(CW\*(C`x.h\*(C'\fR is implicitly zero: +.Sp +.Vb 2 +\& struct s { int f, g, h; }; +\& struct s x = { 3, 4 }; +.Ve +.Sp +This option does not warn about designated initializers, so the following +modification would not trigger a warning: +.Sp +.Vb 2 +\& struct s { int f, g, h; }; +\& struct s x = { .f = 3, .g = 4 }; +.Ve +.Sp +This warning is included in \fB\-Wextra\fR. To get other \fB\-Wextra\fR +warnings without this one, use \fB\-Wextra \-Wno\-missing\-field\-initializers\fR. +.IP "\fB\-Wmissing\-format\-attribute\fR" 4 +.IX Item "-Wmissing-format-attribute" +Warn about function pointers which might be candidates for \f(CW\*(C`format\*(C'\fR +attributes. Note these are only possible candidates, not absolute ones. +\&\s-1GCC\s0 will guess that function pointers with \f(CW\*(C`format\*(C'\fR attributes that +are used in assignment, initialization, parameter passing or return +statements should have a corresponding \f(CW\*(C`format\*(C'\fR attribute in the +resulting type. I.e. the left-hand side of the assignment or +initialization, the type of the parameter variable, or the return type +of the containing function respectively should also have a \f(CW\*(C`format\*(C'\fR +attribute to avoid the warning. +.Sp +\&\s-1GCC\s0 will also warn about function definitions which might be +candidates for \f(CW\*(C`format\*(C'\fR attributes. Again, these are only +possible candidates. \s-1GCC\s0 will guess that \f(CW\*(C`format\*(C'\fR attributes +might be appropriate for any function that calls a function like +\&\f(CW\*(C`vprintf\*(C'\fR or \f(CW\*(C`vscanf\*(C'\fR, but this might not always be the +case, and some functions for which \f(CW\*(C`format\*(C'\fR attributes are +appropriate may not be detected. +.IP "\fB\-Wno\-multichar\fR" 4 +.IX Item "-Wno-multichar" +Do not warn if a multicharacter constant (\fB'\s-1FOOF\s0'\fR) is used. +Usually they indicate a typo in the user's code, as they have +implementation-defined values, and should not be used in portable code. +.IP "\fB\-Wnormalized=<none|id|nfc|nfkc>\fR" 4 +.IX Item "-Wnormalized=<none|id|nfc|nfkc>" +In \s-1ISO\s0 C and \s-1ISO\s0 \*(C+, two identifiers are different if they are +different sequences of characters. However, sometimes when characters +outside the basic \s-1ASCII\s0 character set are used, you can have two +different character sequences that look the same. To avoid confusion, +the \s-1ISO\s0 10646 standard sets out some \fInormalization rules\fR which +when applied ensure that two sequences that look the same are turned into +the same sequence. \s-1GCC\s0 can warn you if you are using identifiers which +have not been normalized; this option controls that warning. +.Sp +There are four levels of warning that \s-1GCC\s0 supports. The default is +\&\fB\-Wnormalized=nfc\fR, which warns about any identifier which is +not in the \s-1ISO\s0 10646 \*(L"C\*(R" normalized form, \fI\s-1NFC\s0\fR. \s-1NFC\s0 is the +recommended form for most uses. +.Sp +Unfortunately, there are some characters which \s-1ISO\s0 C and \s-1ISO\s0 \*(C+ allow +in identifiers that when turned into \s-1NFC\s0 aren't allowable as +identifiers. That is, there's no way to use these symbols in portable +\&\s-1ISO\s0 C or \*(C+ and have all your identifiers in \s-1NFC\s0. +\&\fB\-Wnormalized=id\fR suppresses the warning for these characters. +It is hoped that future versions of the standards involved will correct +this, which is why this option is not the default. +.Sp +You can switch the warning off for all characters by writing +\&\fB\-Wnormalized=none\fR. You would only want to do this if you +were using some other normalization scheme (like \*(L"D\*(R"), because +otherwise you can easily create bugs that are literally impossible to see. +.Sp +Some characters in \s-1ISO\s0 10646 have distinct meanings but look identical +in some fonts or display methodologies, especially once formatting has +been applied. For instance \f(CW\*(C`\eu207F\*(C'\fR, \*(L"\s-1SUPERSCRIPT\s0 \s-1LATIN\s0 \s-1SMALL\s0 +\&\s-1LETTER\s0 N\*(R", will display just like a regular \f(CW\*(C`n\*(C'\fR which has been +placed in a superscript. \s-1ISO\s0 10646 defines the \fI\s-1NFKC\s0\fR +normalization scheme to convert all these into a standard form as +well, and \s-1GCC\s0 will warn if your code is not in \s-1NFKC\s0 if you use +\&\fB\-Wnormalized=nfkc\fR. This warning is comparable to warning +about every identifier that contains the letter O because it might be +confused with the digit 0, and so is not the default, but may be +useful as a local coding convention if the programming environment is +unable to be fixed to display these characters distinctly. +.IP "\fB\-Wno\-deprecated\fR" 4 +.IX Item "-Wno-deprecated" +Do not warn about usage of deprecated features. +.IP "\fB\-Wno\-deprecated\-declarations\fR" 4 +.IX Item "-Wno-deprecated-declarations" +Do not warn about uses of functions, +variables, and types marked as deprecated by using the \f(CW\*(C`deprecated\*(C'\fR +attribute. +.IP "\fB\-Wno\-overflow\fR" 4 +.IX Item "-Wno-overflow" +Do not warn about compile-time overflow in constant expressions. +.IP "\fB\-Woverride\-init\fR (C and Objective-C only)" 4 +.IX Item "-Woverride-init (C and Objective-C only)" +Warn if an initialized field without side effects is overridden when +using designated initializers. +.Sp +This warning is included in \fB\-Wextra\fR. To get other +\&\fB\-Wextra\fR warnings without this one, use \fB\-Wextra +\&\-Wno\-override\-init\fR. +.IP "\fB\-Wpacked\fR" 4 +.IX Item "-Wpacked" +Warn if a structure is given the packed attribute, but the packed +attribute has no effect on the layout or size of the structure. +Such structures may be mis-aligned for little benefit. For +instance, in this code, the variable \f(CW\*(C`f.x\*(C'\fR in \f(CW\*(C`struct bar\*(C'\fR +will be misaligned even though \f(CW\*(C`struct bar\*(C'\fR does not itself +have the packed attribute: +.Sp +.Vb 8 +\& struct foo { +\& int x; +\& char a, b, c, d; +\& } _\|_attribute_\|_((packed)); +\& struct bar { +\& char z; +\& struct foo f; +\& }; +.Ve +.IP "\fB\-Wpacked\-bitfield\-compat\fR" 4 +.IX Item "-Wpacked-bitfield-compat" +The 4.1, 4.2 and 4.3 series of \s-1GCC\s0 ignore the \f(CW\*(C`packed\*(C'\fR attribute +on bit-fields of type \f(CW\*(C`char\*(C'\fR. This has been fixed in \s-1GCC\s0 4.4 but +the change can lead to differences in the structure layout. \s-1GCC\s0 +informs you when the offset of such a field has changed in \s-1GCC\s0 4.4. +For example there is no longer a 4\-bit padding between field \f(CW\*(C`a\*(C'\fR +and \f(CW\*(C`b\*(C'\fR in this structure: +.Sp +.Vb 5 +\& struct foo +\& { +\& char a:4; +\& char b:8; +\& } _\|_attribute_\|_ ((packed)); +.Ve +.Sp +This warning is enabled by default. Use +\&\fB\-Wno\-packed\-bitfield\-compat\fR to disable this warning. +.IP "\fB\-Wpadded\fR" 4 +.IX Item "-Wpadded" +Warn if padding is included in a structure, either to align an element +of the structure or to align the whole structure. Sometimes when this +happens it is possible to rearrange the fields of the structure to +reduce the padding and so make the structure smaller. +.IP "\fB\-Wredundant\-decls\fR" 4 +.IX Item "-Wredundant-decls" +Warn if anything is declared more than once in the same scope, even in +cases where multiple declaration is valid and changes nothing. +.IP "\fB\-Wnested\-externs\fR (C and Objective-C only)" 4 +.IX Item "-Wnested-externs (C and Objective-C only)" +Warn if an \f(CW\*(C`extern\*(C'\fR declaration is encountered within a function. +.IP "\fB\-Winline\fR" 4 +.IX Item "-Winline" +Warn if a function can not be inlined and it was declared as inline. +Even with this option, the compiler will not warn about failures to +inline functions declared in system headers. +.Sp +The compiler uses a variety of heuristics to determine whether or not +to inline a function. For example, the compiler takes into account +the size of the function being inlined and the amount of inlining +that has already been done in the current function. Therefore, +seemingly insignificant changes in the source program can cause the +warnings produced by \fB\-Winline\fR to appear or disappear. +.IP "\fB\-Wno\-invalid\-offsetof\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wno-invalid-offsetof ( and Objective- only)" +Suppress warnings from applying the \fBoffsetof\fR macro to a non-POD +type. According to the 1998 \s-1ISO\s0 \*(C+ standard, applying \fBoffsetof\fR +to a non-POD type is undefined. In existing \*(C+ implementations, +however, \fBoffsetof\fR typically gives meaningful results even when +applied to certain kinds of non-POD types. (Such as a simple +\&\fBstruct\fR that fails to be a \s-1POD\s0 type only by virtue of having a +constructor.) This flag is for users who are aware that they are +writing nonportable code and who have deliberately chosen to ignore the +warning about it. +.Sp +The restrictions on \fBoffsetof\fR may be relaxed in a future version +of the \*(C+ standard. +.IP "\fB\-Wno\-int\-to\-pointer\-cast\fR" 4 +.IX Item "-Wno-int-to-pointer-cast" +Suppress warnings from casts to pointer type of an integer of a +different size. In \*(C+, casting to a pointer type of smaller size is +an error. \fBWint-to-pointer-cast\fR is enabled by default. +.IP "\fBmax-lipo-mem\fR" 4 +.IX Item "max-lipo-mem" +When importing auxiliary modules during profile-use, check current +memory consumption after parsing each auxiliary module. If it exceeds +this limit (specified in kb), don't import any more auxiliary modules. +Specifying a value of 0 means don't enforce this limit. This parameter +is only useful when using \fB\-fprofile\-use\fR and \fB\-fripa\fR. +.IP "\fB\-Wno\-pointer\-to\-int\-cast\fR (C and Objective-C only)" 4 +.IX Item "-Wno-pointer-to-int-cast (C and Objective-C only)" +Suppress warnings from casts from a pointer to an integer type of a +different size. +.IP "\fB\-Winvalid\-pch\fR" 4 +.IX Item "-Winvalid-pch" +Warn if a precompiled header is found in +the search path but can't be used. +.IP "\fB\-Wlong\-long\fR" 4 +.IX Item "-Wlong-long" +Warn if \fBlong long\fR type is used. This is enabled by either +\&\fB\-pedantic\fR or \fB\-Wtraditional\fR in \s-1ISO\s0 C90 and \*(C+98 +modes. To inhibit the warning messages, use \fB\-Wno\-long\-long\fR. +.IP "\fB\-Wvariadic\-macros\fR" 4 +.IX Item "-Wvariadic-macros" +Warn if variadic macros are used in pedantic \s-1ISO\s0 C90 mode, or the \s-1GNU\s0 +alternate syntax when in pedantic \s-1ISO\s0 C99 mode. This is default. +To inhibit the warning messages, use \fB\-Wno\-variadic\-macros\fR. +.IP "\fB\-Wvla\fR" 4 +.IX Item "-Wvla" +Warn if variable length array is used in the code. +\&\fB\-Wno\-vla\fR will prevent the \fB\-pedantic\fR warning of +the variable length array. +.IP "\fB\-Wvolatile\-register\-var\fR" 4 +.IX Item "-Wvolatile-register-var" +Warn if a register variable is declared volatile. The volatile +modifier does not inhibit all optimizations that may eliminate reads +and/or writes to register variables. This warning is enabled by +\&\fB\-Wall\fR. +.IP "\fB\-Wdisabled\-optimization\fR" 4 +.IX Item "-Wdisabled-optimization" +Warn if a requested optimization pass is disabled. This warning does +not generally indicate that there is anything wrong with your code; it +merely indicates that \s-1GCC\s0's optimizers were unable to handle the code +effectively. Often, the problem is that your code is too big or too +complex; \s-1GCC\s0 will refuse to optimize programs when the optimization +itself is likely to take inordinate amounts of time. +.IP "\fB\-Wpointer\-sign\fR (C and Objective-C only)" 4 +.IX Item "-Wpointer-sign (C and Objective-C only)" +Warn for pointer argument passing or assignment with different signedness. +This option is only supported for C and Objective-C. It is implied by +\&\fB\-Wall\fR and by \fB\-pedantic\fR, which can be disabled with +\&\fB\-Wno\-pointer\-sign\fR. +.IP "\fB\-Wstack\-protector\fR" 4 +.IX Item "-Wstack-protector" +This option is only active when \fB\-fstack\-protector\fR is active. It +warns about functions that will not be protected against stack smashing. +.IP "\fB\-Wno\-mudflap\fR" 4 +.IX Item "-Wno-mudflap" +Suppress warnings about constructs that cannot be instrumented by +\&\fB\-fmudflap\fR. +.IP "\fB\-Woverlength\-strings\fR" 4 +.IX Item "-Woverlength-strings" +Warn about string constants which are longer than the \*(L"minimum +maximum\*(R" length specified in the C standard. Modern compilers +generally allow string constants which are much longer than the +standard's minimum limit, but very portable programs should avoid +using longer strings. +.Sp +The limit applies \fIafter\fR string constant concatenation, and does +not count the trailing \s-1NUL\s0. In C90, the limit was 509 characters; in +C99, it was raised to 4095. \*(C+98 does not specify a normative +minimum maximum, so we do not diagnose overlength strings in \*(C+. +.Sp +This option is implied by \fB\-pedantic\fR, and can be disabled with +\&\fB\-Wno\-overlength\-strings\fR. +.IP "\fB\-Wunsuffixed\-float\-constants\fR (C and Objective-C only)" 4 +.IX Item "-Wunsuffixed-float-constants (C and Objective-C only)" +\&\s-1GCC\s0 will issue a warning for any floating constant that does not have +a suffix. When used together with \fB\-Wsystem\-headers\fR it will +warn about such constants in system header files. This can be useful +when preparing code to use with the \f(CW\*(C`FLOAT_CONST_DECIMAL64\*(C'\fR pragma +from the decimal floating-point extension to C99. +.SS "Options for Debugging Your Program or \s-1GCC\s0" +.IX Subsection "Options for Debugging Your Program or GCC" +\&\s-1GCC\s0 has various special options that are used for debugging +either your program or \s-1GCC:\s0 +.IP "\fB\-g\fR" 4 +.IX Item "-g" +Produce debugging information in the operating system's native format +(stabs, \s-1COFF\s0, \s-1XCOFF\s0, or \s-1DWARF\s0 2). \s-1GDB\s0 can work with this debugging +information. +.Sp +On most systems that use stabs format, \fB\-g\fR enables use of extra +debugging information that only \s-1GDB\s0 can use; this extra information +makes debugging work better in \s-1GDB\s0 but will probably make other debuggers +crash or +refuse to read the program. If you want to control for certain whether +to generate the extra information, use \fB\-gstabs+\fR, \fB\-gstabs\fR, +\&\fB\-gxcoff+\fR, \fB\-gxcoff\fR, or \fB\-gvms\fR (see below). +.Sp +\&\s-1GCC\s0 allows you to use \fB\-g\fR with +\&\fB\-O\fR. The shortcuts taken by optimized code may occasionally +produce surprising results: some variables you declared may not exist +at all; flow of control may briefly move where you did not expect it; +some statements may not be executed because they compute constant +results or their values were already at hand; some statements may +execute in different places because they were moved out of loops. +.Sp +Nevertheless it proves possible to debug optimized output. This makes +it reasonable to use the optimizer for programs that might have bugs. +.Sp +The following options are useful when \s-1GCC\s0 is generated with the +capability for more than one debugging format. +.IP "\fB\-ggdb\fR" 4 +.IX Item "-ggdb" +Produce debugging information for use by \s-1GDB\s0. This means to use the +most expressive format available (\s-1DWARF\s0 2, stabs, or the native format +if neither of those are supported), including \s-1GDB\s0 extensions if at all +possible. +.IP "\fB\-gstabs\fR" 4 +.IX Item "-gstabs" +Produce debugging information in stabs format (if that is supported), +without \s-1GDB\s0 extensions. This is the format used by \s-1DBX\s0 on most \s-1BSD\s0 +systems. On \s-1MIPS\s0, Alpha and System V Release 4 systems this option +produces stabs debugging output which is not understood by \s-1DBX\s0 or \s-1SDB\s0. +On System V Release 4 systems this option requires the \s-1GNU\s0 assembler. +.IP "\fB\-feliminate\-unused\-debug\-symbols\fR" 4 +.IX Item "-feliminate-unused-debug-symbols" +Produce debugging information in stabs format (if that is supported), +for only symbols that are actually used. +.IP "\fB\-femit\-class\-debug\-always\fR" 4 +.IX Item "-femit-class-debug-always" +Instead of emitting debugging information for a \*(C+ class in only one +object file, emit it in all object files using the class. This option +should be used only with debuggers that are unable to handle the way \s-1GCC\s0 +normally emits debugging information for classes because using this +option will increase the size of debugging information by as much as a +factor of two. +.IP "\fB\-gstabs+\fR" 4 +.IX Item "-gstabs+" +Produce debugging information in stabs format (if that is supported), +using \s-1GNU\s0 extensions understood only by the \s-1GNU\s0 debugger (\s-1GDB\s0). The +use of these extensions is likely to make other debuggers crash or +refuse to read the program. +.IP "\fB\-gcoff\fR" 4 +.IX Item "-gcoff" +Produce debugging information in \s-1COFF\s0 format (if that is supported). +This is the format used by \s-1SDB\s0 on most System V systems prior to +System V Release 4. +.IP "\fB\-gxcoff\fR" 4 +.IX Item "-gxcoff" +Produce debugging information in \s-1XCOFF\s0 format (if that is supported). +This is the format used by the \s-1DBX\s0 debugger on \s-1IBM\s0 \s-1RS/6000\s0 systems. +.IP "\fB\-gxcoff+\fR" 4 +.IX Item "-gxcoff+" +Produce debugging information in \s-1XCOFF\s0 format (if that is supported), +using \s-1GNU\s0 extensions understood only by the \s-1GNU\s0 debugger (\s-1GDB\s0). The +use of these extensions is likely to make other debuggers crash or +refuse to read the program, and may cause assemblers other than the \s-1GNU\s0 +assembler (\s-1GAS\s0) to fail with an error. +.IP "\fB\-gdwarf\-\fR\fIversion\fR" 4 +.IX Item "-gdwarf-version" +Produce debugging information in \s-1DWARF\s0 format (if that is +supported). This is the format used by \s-1DBX\s0 on \s-1IRIX\s0 6. The value +of \fIversion\fR may be either 2, 3 or 4; the default version is 2. +.Sp +Note that with \s-1DWARF\s0 version 2 some ports require, and will always +use, some non-conflicting \s-1DWARF\s0 3 extensions in the unwind tables. +.Sp +Version 4 may require \s-1GDB\s0 7.0 and \fB\-fvar\-tracking\-assignments\fR +for maximum benefit. +.IP "\fB\-gstrict\-dwarf\fR" 4 +.IX Item "-gstrict-dwarf" +Disallow using extensions of later \s-1DWARF\s0 standard version than selected +with \fB\-gdwarf\-\fR\fIversion\fR. On most targets using non-conflicting +\&\s-1DWARF\s0 extensions from later standard versions is allowed. +.IP "\fB\-gno\-strict\-dwarf\fR" 4 +.IX Item "-gno-strict-dwarf" +Allow using extensions of later \s-1DWARF\s0 standard version than selected with +\&\fB\-gdwarf\-\fR\fIversion\fR. +.IP "\fB\-gvms\fR" 4 +.IX Item "-gvms" +Produce debugging information in \s-1VMS\s0 debug format (if that is +supported). This is the format used by \s-1DEBUG\s0 on \s-1VMS\s0 systems. +.IP "\fB\-g\fR\fIlevel\fR" 4 +.IX Item "-glevel" +.PD 0 +.IP "\fB\-ggdb\fR\fIlevel\fR" 4 +.IX Item "-ggdblevel" +.IP "\fB\-gstabs\fR\fIlevel\fR" 4 +.IX Item "-gstabslevel" +.IP "\fB\-gcoff\fR\fIlevel\fR" 4 +.IX Item "-gcofflevel" +.IP "\fB\-gxcoff\fR\fIlevel\fR" 4 +.IX Item "-gxcofflevel" +.IP "\fB\-gvms\fR\fIlevel\fR" 4 +.IX Item "-gvmslevel" +.PD +Request debugging information and also use \fIlevel\fR to specify how +much information. The default level is 2. +.Sp +Level 0 produces no debug information at all. Thus, \fB\-g0\fR negates +\&\fB\-g\fR. +.Sp +Level 1 produces minimal information, enough for making backtraces in +parts of the program that you don't plan to debug. This includes +descriptions of functions and external variables, but no information +about local variables and no line numbers. +.Sp +Level 3 includes extra information, such as all the macro definitions +present in the program. Some debuggers support macro expansion when +you use \fB\-g3\fR. +.Sp +\&\fB\-gdwarf\-2\fR does not accept a concatenated debug level, because +\&\s-1GCC\s0 used to support an option \fB\-gdwarf\fR that meant to generate +debug information in version 1 of the \s-1DWARF\s0 format (which is very +different from version 2), and it would have been too confusing. That +debug format is long obsolete, but the option cannot be changed now. +Instead use an additional \fB\-g\fR\fIlevel\fR option to change the +debug level for \s-1DWARF\s0. +.IP "\fB\-gmlt\fR" 4 +.IX Item "-gmlt" +Produce a minimal line table, with level 1 debugging information plus +information about inlined functions and line numbers. +.IP "\fB\-gtoggle\fR" 4 +.IX Item "-gtoggle" +Turn off generation of debug info, if leaving out this option would have +generated it, or turn it on at level 2 otherwise. The position of this +argument in the command line does not matter, it takes effect after all +other options are processed, and it does so only once, no matter how +many times it is given. This is mainly intended to be used with +\&\fB\-fcompare\-debug\fR. +.IP "\fB\-fdump\-final\-insns\fR[\fB=\fR\fIfile\fR]" 4 +.IX Item "-fdump-final-insns[=file]" +Dump the final internal representation (\s-1RTL\s0) to \fIfile\fR. If the +optional argument is omitted (or if \fIfile\fR is \f(CW\*(C`.\*(C'\fR), the name +of the dump file will be determined by appending \f(CW\*(C`.gkd\*(C'\fR to the +compilation output file name. +.IP "\fB\-fcompare\-debug\fR[\fB=\fR\fIopts\fR]" 4 +.IX Item "-fcompare-debug[=opts]" +If no error occurs during compilation, run the compiler a second time, +adding \fIopts\fR and \fB\-fcompare\-debug\-second\fR to the arguments +passed to the second compilation. Dump the final internal +representation in both compilations, and print an error if they differ. +.Sp +If the equal sign is omitted, the default \fB\-gtoggle\fR is used. +.Sp +The environment variable \fB\s-1GCC_COMPARE_DEBUG\s0\fR, if defined, non-empty +and nonzero, implicitly enables \fB\-fcompare\-debug\fR. If +\&\fB\s-1GCC_COMPARE_DEBUG\s0\fR is defined to a string starting with a dash, +then it is used for \fIopts\fR, otherwise the default \fB\-gtoggle\fR +is used. +.Sp +\&\fB\-fcompare\-debug=\fR, with the equal sign but without \fIopts\fR, +is equivalent to \fB\-fno\-compare\-debug\fR, which disables the dumping +of the final representation and the second compilation, preventing even +\&\fB\s-1GCC_COMPARE_DEBUG\s0\fR from taking effect. +.Sp +To verify full coverage during \fB\-fcompare\-debug\fR testing, set +\&\fB\s-1GCC_COMPARE_DEBUG\s0\fR to say \fB\-fcompare\-debug\-not\-overridden\fR, +which \s-1GCC\s0 will reject as an invalid option in any actual compilation +(rather than preprocessing, assembly or linking). To get just a +warning, setting \fB\s-1GCC_COMPARE_DEBUG\s0\fR to \fB\-w%n\-fcompare\-debug +not overridden\fR will do. +.IP "\fB\-fcompare\-debug\-second\fR" 4 +.IX Item "-fcompare-debug-second" +This option is implicitly passed to the compiler for the second +compilation requested by \fB\-fcompare\-debug\fR, along with options to +silence warnings, and omitting other options that would cause +side-effect compiler outputs to files or to the standard output. Dump +files and preserved temporary files are renamed so as to contain the +\&\f(CW\*(C`.gk\*(C'\fR additional extension during the second compilation, to avoid +overwriting those generated by the first. +.Sp +When this option is passed to the compiler driver, it causes the +\&\fIfirst\fR compilation to be skipped, which makes it useful for little +other than debugging the compiler proper. +.IP "\fB\-feliminate\-dwarf2\-dups\fR" 4 +.IX Item "-feliminate-dwarf2-dups" +Compress \s-1DWARF2\s0 debugging information by eliminating duplicated +information about each symbol. This option only makes sense when +generating \s-1DWARF2\s0 debugging information with \fB\-gdwarf\-2\fR. +.IP "\fB\-femit\-struct\-debug\-baseonly\fR" 4 +.IX Item "-femit-struct-debug-baseonly" +Emit debug information for struct-like types +only when the base name of the compilation source file +matches the base name of file in which the struct was defined. +.Sp +This option substantially reduces the size of debugging information, +but at significant potential loss in type information to the debugger. +See \fB\-femit\-struct\-debug\-reduced\fR for a less aggressive option. +See \fB\-femit\-struct\-debug\-detailed\fR for more detailed control. +.Sp +This option works only with \s-1DWARF\s0 2. +.IP "\fB\-femit\-struct\-debug\-reduced\fR" 4 +.IX Item "-femit-struct-debug-reduced" +Emit debug information for struct-like types +only when the base name of the compilation source file +matches the base name of file in which the type was defined, +unless the struct is a template or defined in a system header. +.Sp +This option significantly reduces the size of debugging information, +with some potential loss in type information to the debugger. +See \fB\-femit\-struct\-debug\-baseonly\fR for a more aggressive option. +See \fB\-femit\-struct\-debug\-detailed\fR for more detailed control. +.Sp +This option works only with \s-1DWARF\s0 2. +.IP "\fB\-femit\-struct\-debug\-detailed\fR[\fB=\fR\fIspec-list\fR]" 4 +.IX Item "-femit-struct-debug-detailed[=spec-list]" +Specify the struct-like types +for which the compiler will generate debug information. +The intent is to reduce duplicate struct debug information +between different object files within the same program. +.Sp +This option is a detailed version of +\&\fB\-femit\-struct\-debug\-reduced\fR and \fB\-femit\-struct\-debug\-baseonly\fR, +which will serve for most needs. +.Sp +A specification has the syntax[\fBdir:\fR|\fBind:\fR][\fBord:\fR|\fBgen:\fR](\fBany\fR|\fBsys\fR|\fBbase\fR|\fBnone\fR) +.Sp +The optional first word limits the specification to +structs that are used directly (\fBdir:\fR) or used indirectly (\fBind:\fR). +A struct type is used directly when it is the type of a variable, member. +Indirect uses arise through pointers to structs. +That is, when use of an incomplete struct would be legal, the use is indirect. +An example is +\&\fBstruct one direct; struct two * indirect;\fR. +.Sp +The optional second word limits the specification to +ordinary structs (\fBord:\fR) or generic structs (\fBgen:\fR). +Generic structs are a bit complicated to explain. +For \*(C+, these are non-explicit specializations of template classes, +or non-template classes within the above. +Other programming languages have generics, +but \fB\-femit\-struct\-debug\-detailed\fR does not yet implement them. +.Sp +The third word specifies the source files for those +structs for which the compiler will emit debug information. +The values \fBnone\fR and \fBany\fR have the normal meaning. +The value \fBbase\fR means that +the base of name of the file in which the type declaration appears +must match the base of the name of the main compilation file. +In practice, this means that +types declared in \fIfoo.c\fR and \fIfoo.h\fR will have debug information, +but types declared in other header will not. +The value \fBsys\fR means those types satisfying \fBbase\fR +or declared in system or compiler headers. +.Sp +You may need to experiment to determine the best settings for your application. +.Sp +The default is \fB\-femit\-struct\-debug\-detailed=all\fR. +.Sp +This option works only with \s-1DWARF\s0 2. +.IP "\fB\-fenable\-icf\-debug\fR" 4 +.IX Item "-fenable-icf-debug" +Generate additional debug information to support identical code folding (\s-1ICF\s0). +This option only works with \s-1DWARF\s0 version 2 or higher. +.IP "\fB\-fno\-merge\-debug\-strings\fR" 4 +.IX Item "-fno-merge-debug-strings" +Direct the linker to not merge together strings in the debugging +information which are identical in different object files. Merging is +not supported by all assemblers or linkers. Merging decreases the size +of the debug information in the output file at the cost of increasing +link processing time. Merging is enabled by default. +.IP "\fB\-fdebug\-prefix\-map=\fR\fIold\fR\fB=\fR\fInew\fR" 4 +.IX Item "-fdebug-prefix-map=old=new" +When compiling files in directory \fI\fIold\fI\fR, record debugging +information describing them as in \fI\fInew\fI\fR instead. +.IP "\fB\-fno\-dwarf2\-cfi\-asm\fR" 4 +.IX Item "-fno-dwarf2-cfi-asm" +Emit \s-1DWARF\s0 2 unwind info as compiler generated \f(CW\*(C`.eh_frame\*(C'\fR section +instead of using \s-1GAS\s0 \f(CW\*(C`.cfi_*\*(C'\fR directives. +.IP "\fB\-p\fR" 4 +.IX Item "-p" +Generate extra code to write profile information suitable for the +analysis program \fBprof\fR. You must use this option when compiling +the source files you want data about, and you must also use it when +linking. +.IP "\fB\-pg\fR" 4 +.IX Item "-pg" +Generate extra code to write profile information suitable for the +analysis program \fBgprof\fR. You must use this option when compiling +the source files you want data about, and you must also use it when +linking. +.IP "\fB\-Q\fR" 4 +.IX Item "-Q" +Makes the compiler print out each function name as it is compiled, and +print some statistics about each pass when it finishes. +.IP "\fB\-ftime\-report\fR" 4 +.IX Item "-ftime-report" +Makes the compiler print some statistics about the time consumed by each +pass when it finishes. +.IP "\fB\-fmem\-report\fR" 4 +.IX Item "-fmem-report" +Makes the compiler print some statistics about permanent memory +allocation when it finishes. +.IP "\fB\-fpre\-ipa\-mem\-report\fR" 4 +.IX Item "-fpre-ipa-mem-report" +.PD 0 +.IP "\fB\-fpost\-ipa\-mem\-report\fR" 4 +.IX Item "-fpost-ipa-mem-report" +.PD +Makes the compiler print some statistics about permanent memory +allocation before or after interprocedural optimization. +.IP "\fB\-fstack\-usage\fR" 4 +.IX Item "-fstack-usage" +Makes the compiler output stack usage information for the program, on a +per-function basis. The filename for the dump is made by appending +\&\fI.su\fR to the \fIauxname\fR. \fIauxname\fR is generated from the name of +the output file, if explicitly specified and it is not an executable, +otherwise it is the basename of the source file. An entry is made up +of three fields: +.RS 4 +.IP "\(bu" 4 +The name of the function. +.IP "\(bu" 4 +A number of bytes. +.IP "\(bu" 4 +One or more qualifiers: \f(CW\*(C`static\*(C'\fR, \f(CW\*(C`dynamic\*(C'\fR, \f(CW\*(C`bounded\*(C'\fR. +.RE +.RS 4 +.Sp +The qualifier \f(CW\*(C`static\*(C'\fR means that the function manipulates the stack +statically: a fixed number of bytes are allocated for the frame on function +entry and released on function exit; no stack adjustments are otherwise made +in the function. The second field is this fixed number of bytes. +.Sp +The qualifier \f(CW\*(C`dynamic\*(C'\fR means that the function manipulates the stack +dynamically: in addition to the static allocation described above, stack +adjustments are made in the body of the function, for example to push/pop +arguments around function calls. If the qualifier \f(CW\*(C`bounded\*(C'\fR is also +present, the amount of these adjustments is bounded at compile-time and +the second field is an upper bound of the total amount of stack used by +the function. If it is not present, the amount of these adjustments is +not bounded at compile-time and the second field only represents the +bounded part. +.RE +.IP "\fB\-fprofile\-arcs\fR" 4 +.IX Item "-fprofile-arcs" +Add code so that program flow \fIarcs\fR are instrumented. During +execution the program records how many times each branch and call is +executed and how many times it is taken or returns. When the compiled +program exits it saves this data to a file called +\&\fI\fIauxname\fI.gcda\fR for each source file. The data may be used for +profile-directed optimizations (\fB\-fbranch\-probabilities\fR), or for +test coverage analysis (\fB\-ftest\-coverage\fR). Each object file's +\&\fIauxname\fR is generated from the name of the output file, if +explicitly specified and it is not the final executable, otherwise it is +the basename of the source file. In both cases any suffix is removed +(e.g. \fIfoo.gcda\fR for input file \fIdir/foo.c\fR, or +\&\fIdir/foo.gcda\fR for output file specified as \fB\-o dir/foo.o\fR). +.IP "\fB\-\-coverage\fR" 4 +.IX Item "--coverage" +This option is used to compile and link code instrumented for coverage +analysis. The option is a synonym for \fB\-fprofile\-arcs\fR +\&\fB\-ftest\-coverage\fR (when compiling) and \fB\-lgcov\fR (when +linking). See the documentation for those options for more details. +.RS 4 +.IP "\(bu" 4 +Compile the source files with \fB\-fprofile\-arcs\fR plus optimization +and code generation options. For test coverage analysis, use the +additional \fB\-ftest\-coverage\fR option. You do not need to profile +every source file in a program. +.IP "\(bu" 4 +Link your object files with \fB\-lgcov\fR or \fB\-fprofile\-arcs\fR +(the latter implies the former). +.IP "\(bu" 4 +Run the program on a representative workload to generate the arc profile +information. This may be repeated any number of times. You can run +concurrent instances of your program, and provided that the file system +supports locking, the data files will be correctly updated. Also +\&\f(CW\*(C`fork\*(C'\fR calls are detected and correctly handled (double counting +will not happen). +.IP "\(bu" 4 +For profile-directed optimizations, compile the source files again with +the same optimization and code generation options plus +\&\fB\-fbranch\-probabilities\fR. +.IP "\(bu" 4 +For test coverage analysis, use \fBgcov\fR to produce human readable +information from the \fI.gcno\fR and \fI.gcda\fR files. Refer to the +\&\fBgcov\fR documentation for further information. +.RE +.RS 4 +.Sp +With \fB\-fprofile\-arcs\fR, for each function of your program \s-1GCC\s0 +creates a program flow graph, then finds a spanning tree for the graph. +Only arcs that are not on the spanning tree have to be instrumented: the +compiler adds code to count the number of times that these arcs are +executed. When an arc is the only exit or only entrance to a block, the +instrumentation code can be added to the block; otherwise, a new basic +block must be created to hold the instrumentation code. +.RE +.IP "\fB\-ftest\-coverage\fR" 4 +.IX Item "-ftest-coverage" +Produce a notes file that the \fBgcov\fR code-coverage utility can use to +show program coverage. Each source file's note file is called +\&\fI\fIauxname\fI.gcno\fR. Refer to the \fB\-fprofile\-arcs\fR option +above for a description of \fIauxname\fR and instructions on how to +generate test coverage data. Coverage data will match the source files +more closely, if you do not optimize. +.IP "\fB\-fdbg\-cnt\-list\fR" 4 +.IX Item "-fdbg-cnt-list" +Print the name and the counter upper bound for all debug counters. +.IP "\fB\-fdbg\-cnt=\fR\fIcounter-value-list\fR" 4 +.IX Item "-fdbg-cnt=counter-value-list" +Set the internal debug counter upper bound. \fIcounter-value-list\fR +is a comma-separated list of \fIname\fR:\fIvalue\fR pairs +which sets the upper bound of each debug counter \fIname\fR to \fIvalue\fR. +All debug counters have the initial upper bound of \fI\s-1UINT_MAX\s0\fR, +thus \fIdbg_cnt()\fR returns true always unless the upper bound is set by this option. +e.g. With \-fdbg\-cnt=dce:10,tail_call:0 +dbg_cnt(dce) will return true only for first 10 invocations +.IP "\fB\-fenable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR" 4 +.IX Item "-fenable-kind-pass" +.PD 0 +.IP "\fB\-fdisable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR" 4 +.IX Item "-fdisable-kind-pass=range-list" +.PD +This is a set of debugging options that are used to explicitly disable/enable +optimization passes. For compiler users, regular options for enabling/disabling +passes should be used instead. +.RS 4 +.IP "*<\-fdisable\-ipa\-\fIpass\fR>" 4 +.IX Item "*<-fdisable-ipa-pass>" +Disable ipa pass \fIpass\fR. \fIpass\fR is the pass name. If the same pass is +statically invoked in the compiler multiple times, the pass name should be +appended with a sequential number starting from 1. +.IP "*<\-fdisable\-rtl\-\fIpass\fR>" 4 +.IX Item "*<-fdisable-rtl-pass>" +.PD 0 +.IP "*<\-fdisable\-rtl\-\fIpass\fR=\fIrange-list\fR>" 4 +.IX Item "*<-fdisable-rtl-pass=range-list>" +.PD +Disable rtl pass \fIpass\fR. \fIpass\fR is the pass name. If the same pass is +statically invoked in the compiler multiple times, the pass name should be +appended with a sequential number starting from 1. \fIrange-list\fR is a comma +seperated list of function ranges or assembler names. Each range is a number +pair seperated by a colon. The range is inclusive in both ends. If the range +is trivial, the number pair can be simplified as a single number. If the +function's cgraph node's \fIuid\fR is falling within one of the specified ranges, +the \fIpass\fR is disabled for that function. The \fIuid\fR is shown in the +function header of a dump file, and the pass names can be dumped by using +option \fB\-fdump\-passes\fR. +.IP "*<\-fdisable\-tree\-\fIpass\fR>" 4 +.IX Item "*<-fdisable-tree-pass>" +.PD 0 +.IP "*<\-fdisable\-tree\-\fIpass\fR=\fIrange-list\fR>" 4 +.IX Item "*<-fdisable-tree-pass=range-list>" +.PD +Disable tree pass \fIpass\fR. See \fB\-fdisable\-rtl\fR for the description of +option arguments. +.IP "*<\-fenable\-ipa\-\fIpass\fR>" 4 +.IX Item "*<-fenable-ipa-pass>" +Enable ipa pass \fIpass\fR. \fIpass\fR is the pass name. If the same pass is +statically invoked in the compiler multiple times, the pass name should be +appended with a sequential number starting from 1. +.IP "*<\-fenable\-rtl\-\fIpass\fR>" 4 +.IX Item "*<-fenable-rtl-pass>" +.PD 0 +.IP "*<\-fenable\-rtl\-\fIpass\fR=\fIrange-list\fR>" 4 +.IX Item "*<-fenable-rtl-pass=range-list>" +.PD +Enable rtl pass \fIpass\fR. See \fB\-fdisable\-rtl\fR for option argument +description and examples. +.IP "*<\-fenable\-tree\-\fIpass\fR>" 4 +.IX Item "*<-fenable-tree-pass>" +.PD 0 +.IP "*<\-fenable\-tree\-\fIpass\fR=\fIrange-list\fR>" 4 +.IX Item "*<-fenable-tree-pass=range-list>" +.PD +Enable tree pass \fIpass\fR. See \fB\-fdisable\-rtl\fR for the description +of option arguments. +.Sp +.Vb 10 +\& # disable ccp1 for all functions +\& \-fdisable\-tree\-ccp1 +\& # disable complete unroll for function whose cgraph node uid is 1 +\& \-fenable\-tree\-cunroll=1 +\& # disable gcse2 for functions at the following ranges [1,1], +\& # [300,400], and [400,1000] +\& # disable gcse2 for functions foo and foo2 +\& \-fdisable\-rtl\-gcse2=foo,foo2 +\& # disable early inlining +\& \-fdisable\-tree\-einline +\& # disable ipa inlining +\& \-fdisable\-ipa\-inline +\& # enable tree full unroll +\& \-fenable\-tree\-unroll +.Ve +.RE +.RS 4 +.RE +.IP "\fB\-d\fR\fIletters\fR" 4 +.IX Item "-dletters" +.PD 0 +.IP "\fB\-fdump\-rtl\-\fR\fIpass\fR" 4 +.IX Item "-fdump-rtl-pass" +.PD +Says to make debugging dumps during compilation at times specified by +\&\fIletters\fR. This is used for debugging the RTL-based passes of the +compiler. The file names for most of the dumps are made by appending +a pass number and a word to the \fIdumpname\fR, and the files are +created in the directory of the output file. Note that the pass +number is computed statically as passes get registered into the pass +manager. Thus the numbering is not related to the dynamic order of +execution of passes. In particular, a pass installed by a plugin +could have a number over 200 even if it executed quite early. +\&\fIdumpname\fR is generated from the name of the output file, if +explicitly specified and it is not an executable, otherwise it is the +basename of the source file. These switches may have different effects +when \fB\-E\fR is used for preprocessing. +.Sp +Debug dumps can be enabled with a \fB\-fdump\-rtl\fR switch or some +\&\fB\-d\fR option \fIletters\fR. Here are the possible +letters for use in \fIpass\fR and \fIletters\fR, and their meanings: +.RS 4 +.IP "\fB\-fdump\-rtl\-alignments\fR" 4 +.IX Item "-fdump-rtl-alignments" +Dump after branch alignments have been computed. +.IP "\fB\-fdump\-rtl\-asmcons\fR" 4 +.IX Item "-fdump-rtl-asmcons" +Dump after fixing rtl statements that have unsatisfied in/out constraints. +.IP "\fB\-fdump\-rtl\-auto_inc_dec\fR" 4 +.IX Item "-fdump-rtl-auto_inc_dec" +Dump after auto-inc-dec discovery. This pass is only run on +architectures that have auto inc or auto dec instructions. +.IP "\fB\-fdump\-rtl\-barriers\fR" 4 +.IX Item "-fdump-rtl-barriers" +Dump after cleaning up the barrier instructions. +.IP "\fB\-fdump\-rtl\-bbpart\fR" 4 +.IX Item "-fdump-rtl-bbpart" +Dump after partitioning hot and cold basic blocks. +.IP "\fB\-fdump\-rtl\-bbro\fR" 4 +.IX Item "-fdump-rtl-bbro" +Dump after block reordering. +.IP "\fB\-fdump\-rtl\-btl1\fR" 4 +.IX Item "-fdump-rtl-btl1" +.PD 0 +.IP "\fB\-fdump\-rtl\-btl2\fR" 4 +.IX Item "-fdump-rtl-btl2" +.PD +\&\fB\-fdump\-rtl\-btl1\fR and \fB\-fdump\-rtl\-btl2\fR enable dumping +after the two branch +target load optimization passes. +.IP "\fB\-fdump\-rtl\-bypass\fR" 4 +.IX Item "-fdump-rtl-bypass" +Dump after jump bypassing and control flow optimizations. +.IP "\fB\-fdump\-rtl\-combine\fR" 4 +.IX Item "-fdump-rtl-combine" +Dump after the \s-1RTL\s0 instruction combination pass. +.IP "\fB\-fdump\-rtl\-compgotos\fR" 4 +.IX Item "-fdump-rtl-compgotos" +Dump after duplicating the computed gotos. +.IP "\fB\-fdump\-rtl\-ce1\fR" 4 +.IX Item "-fdump-rtl-ce1" +.PD 0 +.IP "\fB\-fdump\-rtl\-ce2\fR" 4 +.IX Item "-fdump-rtl-ce2" +.IP "\fB\-fdump\-rtl\-ce3\fR" 4 +.IX Item "-fdump-rtl-ce3" +.PD +\&\fB\-fdump\-rtl\-ce1\fR, \fB\-fdump\-rtl\-ce2\fR, and +\&\fB\-fdump\-rtl\-ce3\fR enable dumping after the three +if conversion passes. +.IP "\fB\-fdump\-rtl\-cprop_hardreg\fR" 4 +.IX Item "-fdump-rtl-cprop_hardreg" +Dump after hard register copy propagation. +.IP "\fB\-fdump\-rtl\-csa\fR" 4 +.IX Item "-fdump-rtl-csa" +Dump after combining stack adjustments. +.IP "\fB\-fdump\-rtl\-cse1\fR" 4 +.IX Item "-fdump-rtl-cse1" +.PD 0 +.IP "\fB\-fdump\-rtl\-cse2\fR" 4 +.IX Item "-fdump-rtl-cse2" +.PD +\&\fB\-fdump\-rtl\-cse1\fR and \fB\-fdump\-rtl\-cse2\fR enable dumping after +the two common sub-expression elimination passes. +.IP "\fB\-fdump\-rtl\-dce\fR" 4 +.IX Item "-fdump-rtl-dce" +Dump after the standalone dead code elimination passes. +.IP "\fB\-fdump\-rtl\-dbr\fR" 4 +.IX Item "-fdump-rtl-dbr" +Dump after delayed branch scheduling. +.IP "\fB\-fdump\-rtl\-dce1\fR" 4 +.IX Item "-fdump-rtl-dce1" +.PD 0 +.IP "\fB\-fdump\-rtl\-dce2\fR" 4 +.IX Item "-fdump-rtl-dce2" +.PD +\&\fB\-fdump\-rtl\-dce1\fR and \fB\-fdump\-rtl\-dce2\fR enable dumping after +the two dead store elimination passes. +.IP "\fB\-fdump\-rtl\-eh\fR" 4 +.IX Item "-fdump-rtl-eh" +Dump after finalization of \s-1EH\s0 handling code. +.IP "\fB\-fdump\-rtl\-eh_ranges\fR" 4 +.IX Item "-fdump-rtl-eh_ranges" +Dump after conversion of \s-1EH\s0 handling range regions. +.IP "\fB\-fdump\-rtl\-expand\fR" 4 +.IX Item "-fdump-rtl-expand" +Dump after \s-1RTL\s0 generation. +.IP "\fB\-fdump\-rtl\-fwprop1\fR" 4 +.IX Item "-fdump-rtl-fwprop1" +.PD 0 +.IP "\fB\-fdump\-rtl\-fwprop2\fR" 4 +.IX Item "-fdump-rtl-fwprop2" +.PD +\&\fB\-fdump\-rtl\-fwprop1\fR and \fB\-fdump\-rtl\-fwprop2\fR enable +dumping after the two forward propagation passes. +.IP "\fB\-fdump\-rtl\-gcse1\fR" 4 +.IX Item "-fdump-rtl-gcse1" +.PD 0 +.IP "\fB\-fdump\-rtl\-gcse2\fR" 4 +.IX Item "-fdump-rtl-gcse2" +.PD +\&\fB\-fdump\-rtl\-gcse1\fR and \fB\-fdump\-rtl\-gcse2\fR enable dumping +after global common subexpression elimination. +.IP "\fB\-fdump\-rtl\-init\-regs\fR" 4 +.IX Item "-fdump-rtl-init-regs" +Dump after the initialization of the registers. +.IP "\fB\-fdump\-rtl\-initvals\fR" 4 +.IX Item "-fdump-rtl-initvals" +Dump after the computation of the initial value sets. +.IP "\fB\-fdump\-rtl\-into_cfglayout\fR" 4 +.IX Item "-fdump-rtl-into_cfglayout" +Dump after converting to cfglayout mode. +.IP "\fB\-fdump\-rtl\-ira\fR" 4 +.IX Item "-fdump-rtl-ira" +Dump after iterated register allocation. +.IP "\fB\-fdump\-rtl\-jump\fR" 4 +.IX Item "-fdump-rtl-jump" +Dump after the second jump optimization. +.IP "\fB\-fdump\-rtl\-loop2\fR" 4 +.IX Item "-fdump-rtl-loop2" +\&\fB\-fdump\-rtl\-loop2\fR enables dumping after the rtl +loop optimization passes. +.IP "\fB\-fdump\-rtl\-mach\fR" 4 +.IX Item "-fdump-rtl-mach" +Dump after performing the machine dependent reorganization pass, if that +pass exists. +.IP "\fB\-fdump\-rtl\-mode_sw\fR" 4 +.IX Item "-fdump-rtl-mode_sw" +Dump after removing redundant mode switches. +.IP "\fB\-fdump\-rtl\-rnreg\fR" 4 +.IX Item "-fdump-rtl-rnreg" +Dump after register renumbering. +.IP "\fB\-fdump\-rtl\-outof_cfglayout\fR" 4 +.IX Item "-fdump-rtl-outof_cfglayout" +Dump after converting from cfglayout mode. +.IP "\fB\-fdump\-rtl\-peephole2\fR" 4 +.IX Item "-fdump-rtl-peephole2" +Dump after the peephole pass. +.IP "\fB\-fdump\-rtl\-postreload\fR" 4 +.IX Item "-fdump-rtl-postreload" +Dump after post-reload optimizations. +.IP "\fB\-fdump\-rtl\-pro_and_epilogue\fR" 4 +.IX Item "-fdump-rtl-pro_and_epilogue" +Dump after generating the function pro and epilogues. +.IP "\fB\-fdump\-rtl\-regmove\fR" 4 +.IX Item "-fdump-rtl-regmove" +Dump after the register move pass. +.IP "\fB\-fdump\-rtl\-sched1\fR" 4 +.IX Item "-fdump-rtl-sched1" +.PD 0 +.IP "\fB\-fdump\-rtl\-sched2\fR" 4 +.IX Item "-fdump-rtl-sched2" +.PD +\&\fB\-fdump\-rtl\-sched1\fR and \fB\-fdump\-rtl\-sched2\fR enable dumping +after the basic block scheduling passes. +.IP "\fB\-fdump\-rtl\-see\fR" 4 +.IX Item "-fdump-rtl-see" +Dump after sign extension elimination. +.IP "\fB\-fdump\-rtl\-seqabstr\fR" 4 +.IX Item "-fdump-rtl-seqabstr" +Dump after common sequence discovery. +.IP "\fB\-fdump\-rtl\-shorten\fR" 4 +.IX Item "-fdump-rtl-shorten" +Dump after shortening branches. +.IP "\fB\-fdump\-rtl\-sibling\fR" 4 +.IX Item "-fdump-rtl-sibling" +Dump after sibling call optimizations. +.IP "\fB\-fdump\-rtl\-split1\fR" 4 +.IX Item "-fdump-rtl-split1" +.PD 0 +.IP "\fB\-fdump\-rtl\-split2\fR" 4 +.IX Item "-fdump-rtl-split2" +.IP "\fB\-fdump\-rtl\-split3\fR" 4 +.IX Item "-fdump-rtl-split3" +.IP "\fB\-fdump\-rtl\-split4\fR" 4 +.IX Item "-fdump-rtl-split4" +.IP "\fB\-fdump\-rtl\-split5\fR" 4 +.IX Item "-fdump-rtl-split5" +.PD +\&\fB\-fdump\-rtl\-split1\fR, \fB\-fdump\-rtl\-split2\fR, +\&\fB\-fdump\-rtl\-split3\fR, \fB\-fdump\-rtl\-split4\fR and +\&\fB\-fdump\-rtl\-split5\fR enable dumping after five rounds of +instruction splitting. +.IP "\fB\-fdump\-rtl\-sms\fR" 4 +.IX Item "-fdump-rtl-sms" +Dump after modulo scheduling. This pass is only run on some +architectures. +.IP "\fB\-fdump\-rtl\-stack\fR" 4 +.IX Item "-fdump-rtl-stack" +Dump after conversion from \s-1GCC\s0's \*(L"flat register file\*(R" registers to the +x87's stack-like registers. This pass is only run on x86 variants. +.IP "\fB\-fdump\-rtl\-subreg1\fR" 4 +.IX Item "-fdump-rtl-subreg1" +.PD 0 +.IP "\fB\-fdump\-rtl\-subreg2\fR" 4 +.IX Item "-fdump-rtl-subreg2" +.PD +\&\fB\-fdump\-rtl\-subreg1\fR and \fB\-fdump\-rtl\-subreg2\fR enable dumping after +the two subreg expansion passes. +.IP "\fB\-fdump\-rtl\-unshare\fR" 4 +.IX Item "-fdump-rtl-unshare" +Dump after all rtl has been unshared. +.IP "\fB\-fdump\-rtl\-vartrack\fR" 4 +.IX Item "-fdump-rtl-vartrack" +Dump after variable tracking. +.IP "\fB\-fdump\-rtl\-vregs\fR" 4 +.IX Item "-fdump-rtl-vregs" +Dump after converting virtual registers to hard registers. +.IP "\fB\-fdump\-rtl\-web\fR" 4 +.IX Item "-fdump-rtl-web" +Dump after live range splitting. +.IP "\fB\-fdump\-rtl\-regclass\fR" 4 +.IX Item "-fdump-rtl-regclass" +.PD 0 +.IP "\fB\-fdump\-rtl\-subregs_of_mode_init\fR" 4 +.IX Item "-fdump-rtl-subregs_of_mode_init" +.IP "\fB\-fdump\-rtl\-subregs_of_mode_finish\fR" 4 +.IX Item "-fdump-rtl-subregs_of_mode_finish" +.IP "\fB\-fdump\-rtl\-dfinit\fR" 4 +.IX Item "-fdump-rtl-dfinit" +.IP "\fB\-fdump\-rtl\-dfinish\fR" 4 +.IX Item "-fdump-rtl-dfinish" +.PD +These dumps are defined but always produce empty files. +.IP "\fB\-fdump\-rtl\-all\fR" 4 +.IX Item "-fdump-rtl-all" +Produce all the dumps listed above. +.IP "\fB\-dA\fR" 4 +.IX Item "-dA" +Annotate the assembler output with miscellaneous debugging information. +.IP "\fB\-dD\fR" 4 +.IX Item "-dD" +Dump all macro definitions, at the end of preprocessing, in addition to +normal output. +.IP "\fB\-dH\fR" 4 +.IX Item "-dH" +Produce a core dump whenever an error occurs. +.IP "\fB\-dm\fR" 4 +.IX Item "-dm" +Print statistics on memory usage, at the end of the run, to +standard error. +.IP "\fB\-dp\fR" 4 +.IX Item "-dp" +Annotate the assembler output with a comment indicating which +pattern and alternative was used. The length of each instruction is +also printed. +.IP "\fB\-dP\fR" 4 +.IX Item "-dP" +Dump the \s-1RTL\s0 in the assembler output as a comment before each instruction. +Also turns on \fB\-dp\fR annotation. +.IP "\fB\-dv\fR" 4 +.IX Item "-dv" +For each of the other indicated dump files (\fB\-fdump\-rtl\-\fR\fIpass\fR), +dump a representation of the control flow graph suitable for viewing with \s-1VCG\s0 +to \fI\fIfile\fI.\fIpass\fI.vcg\fR. +.IP "\fB\-dx\fR" 4 +.IX Item "-dx" +Just generate \s-1RTL\s0 for a function instead of compiling it. Usually used +with \fB\-fdump\-rtl\-expand\fR. +.RE +.RS 4 +.RE +.IP "\fB\-fdump\-noaddr\fR" 4 +.IX Item "-fdump-noaddr" +When doing debugging dumps, suppress address output. This makes it more +feasible to use diff on debugging dumps for compiler invocations with +different compiler binaries and/or different +text / bss / data / heap / stack / dso start locations. +.IP "\fB\-fdump\-unnumbered\fR" 4 +.IX Item "-fdump-unnumbered" +When doing debugging dumps, suppress instruction numbers and address output. +This makes it more feasible to use diff on debugging dumps for compiler +invocations with different options, in particular with and without +\&\fB\-g\fR. +.IP "\fB\-fdump\-unnumbered\-links\fR" 4 +.IX Item "-fdump-unnumbered-links" +When doing debugging dumps (see \fB\-d\fR option above), suppress +instruction numbers for the links to the previous and next instructions +in a sequence. +.IP "\fB\-fdump\-translation\-unit\fR (\*(C+ only)" 4 +.IX Item "-fdump-translation-unit ( only)" +.PD 0 +.IP "\fB\-fdump\-translation\-unit\-\fR\fIoptions\fR\fB \fR(\*(C+ only)" 4 +.IX Item "-fdump-translation-unit-options ( only)" +.PD +Dump a representation of the tree structure for the entire translation +unit to a file. The file name is made by appending \fI.tu\fR to the +source file name, and the file is created in the same directory as the +output file. If the \fB\-\fR\fIoptions\fR form is used, \fIoptions\fR +controls the details of the dump as described for the +\&\fB\-fdump\-tree\fR options. +.IP "\fB\-fdump\-class\-hierarchy\fR (\*(C+ only)" 4 +.IX Item "-fdump-class-hierarchy ( only)" +.PD 0 +.IP "\fB\-fdump\-class\-hierarchy\-\fR\fIoptions\fR\fB \fR(\*(C+ only)" 4 +.IX Item "-fdump-class-hierarchy-options ( only)" +.PD +Dump a representation of each class's hierarchy and virtual function +table layout to a file. The file name is made by appending +\&\fI.class\fR to the source file name, and the file is created in the +same directory as the output file. If the \fB\-\fR\fIoptions\fR form +is used, \fIoptions\fR controls the details of the dump as described +for the \fB\-fdump\-tree\fR options. +.IP "\fB\-fdump\-ipa\-\fR\fIswitch\fR" 4 +.IX Item "-fdump-ipa-switch" +Control the dumping at various stages of inter-procedural analysis +language tree to a file. The file name is generated by appending a +switch specific suffix to the source file name, and the file is created +in the same directory as the output file. The following dumps are +possible: +.RS 4 +.IP "\fBall\fR" 4 +.IX Item "all" +Enables all inter-procedural analysis dumps. +.IP "\fBcgraph\fR" 4 +.IX Item "cgraph" +Dumps information about call-graph optimization, unused function removal, +and inlining decisions. +.IP "\fBinline\fR" 4 +.IX Item "inline" +Dump after function inlining. +.RE +.RS 4 +.RE +.IP "\fB\-fdump\-passes\fR" 4 +.IX Item "-fdump-passes" +Dump the list of optimization passes that are turned on and off by +the current command line options. +.IP "\fB\-fdump\-statistics\-\fR\fIoption\fR" 4 +.IX Item "-fdump-statistics-option" +Enable and control dumping of pass statistics in a separate file. The +file name is generated by appending a suffix ending in +\&\fB.statistics\fR to the source file name, and the file is created in +the same directory as the output file. If the \fB\-\fR\fIoption\fR +form is used, \fB\-stats\fR will cause counters to be summed over the +whole compilation unit while \fB\-details\fR will dump every event as +the passes generate them. The default with no option is to sum +counters for each function compiled. +.IP "\fB\-fdump\-tree\-\fR\fIswitch\fR" 4 +.IX Item "-fdump-tree-switch" +.PD 0 +.IP "\fB\-fdump\-tree\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR" 4 +.IX Item "-fdump-tree-switch-options" +.PD +Control the dumping at various stages of processing the intermediate +language tree to a file. The file name is generated by appending a +switch specific suffix to the source file name, and the file is +created in the same directory as the output file. If the +\&\fB\-\fR\fIoptions\fR form is used, \fIoptions\fR is a list of +\&\fB\-\fR separated options that control the details of the dump. Not +all options are applicable to all dumps, those which are not +meaningful will be ignored. The following options are available +.RS 4 +.IP "\fBaddress\fR" 4 +.IX Item "address" +Print the address of each node. Usually this is not meaningful as it +changes according to the environment and source file. Its primary use +is for tying up a dump file with a debug environment. +.IP "\fBasmname\fR" 4 +.IX Item "asmname" +If \f(CW\*(C`DECL_ASSEMBLER_NAME\*(C'\fR has been set for a given decl, use that +in the dump instead of \f(CW\*(C`DECL_NAME\*(C'\fR. Its primary use is ease of +use working backward from mangled names in the assembly file. +.IP "\fBslim\fR" 4 +.IX Item "slim" +Inhibit dumping of members of a scope or body of a function merely +because that scope has been reached. Only dump such items when they +are directly reachable by some other path. When dumping pretty-printed +trees, this option inhibits dumping the bodies of control structures. +.IP "\fBraw\fR" 4 +.IX Item "raw" +Print a raw representation of the tree. By default, trees are +pretty-printed into a C\-like representation. +.IP "\fBdetails\fR" 4 +.IX Item "details" +Enable more detailed dumps (not honored by every dump option). +.IP "\fBstats\fR" 4 +.IX Item "stats" +Enable dumping various statistics about the pass (not honored by every dump +option). +.IP "\fBblocks\fR" 4 +.IX Item "blocks" +Enable showing basic block boundaries (disabled in raw dumps). +.IP "\fBvops\fR" 4 +.IX Item "vops" +Enable showing virtual operands for every statement. +.IP "\fBlineno\fR" 4 +.IX Item "lineno" +Enable showing line numbers for statements. +.IP "\fBuid\fR" 4 +.IX Item "uid" +Enable showing the unique \s-1ID\s0 (\f(CW\*(C`DECL_UID\*(C'\fR) for each variable. +.IP "\fBverbose\fR" 4 +.IX Item "verbose" +Enable showing the tree dump for each statement. +.IP "\fBeh\fR" 4 +.IX Item "eh" +Enable showing the \s-1EH\s0 region number holding each statement. +.IP "\fBall\fR" 4 +.IX Item "all" +Turn on all options, except \fBraw\fR, \fBslim\fR, \fBverbose\fR +and \fBlineno\fR. +.RE +.RS 4 +.Sp +The following tree dumps are possible: +.IP "\fBoriginal\fR" 4 +.IX Item "original" +Dump before any tree based optimization, to \fI\fIfile\fI.original\fR. +.IP "\fBoptimized\fR" 4 +.IX Item "optimized" +Dump after all tree based optimization, to \fI\fIfile\fI.optimized\fR. +.IP "\fBgimple\fR" 4 +.IX Item "gimple" +Dump each function before and after the gimplification pass to a file. The +file name is made by appending \fI.gimple\fR to the source file name. +.IP "\fBcfg\fR" 4 +.IX Item "cfg" +Dump the control flow graph of each function to a file. The file name is +made by appending \fI.cfg\fR to the source file name. +.IP "\fBvcg\fR" 4 +.IX Item "vcg" +Dump the control flow graph of each function to a file in \s-1VCG\s0 format. The +file name is made by appending \fI.vcg\fR to the source file name. Note +that if the file contains more than one function, the generated file cannot +be used directly by \s-1VCG\s0. You will need to cut and paste each function's +graph into its own separate file first. +.IP "\fBch\fR" 4 +.IX Item "ch" +Dump each function after copying loop headers. The file name is made by +appending \fI.ch\fR to the source file name. +.IP "\fBssa\fR" 4 +.IX Item "ssa" +Dump \s-1SSA\s0 related information to a file. The file name is made by appending +\&\fI.ssa\fR to the source file name. +.IP "\fBalias\fR" 4 +.IX Item "alias" +Dump aliasing information for each function. The file name is made by +appending \fI.alias\fR to the source file name. +.IP "\fBccp\fR" 4 +.IX Item "ccp" +Dump each function after \s-1CCP\s0. The file name is made by appending +\&\fI.ccp\fR to the source file name. +.IP "\fBstoreccp\fR" 4 +.IX Item "storeccp" +Dump each function after STORE-CCP. The file name is made by appending +\&\fI.storeccp\fR to the source file name. +.IP "\fBpre\fR" 4 +.IX Item "pre" +Dump trees after partial redundancy elimination. The file name is made +by appending \fI.pre\fR to the source file name. +.IP "\fBfre\fR" 4 +.IX Item "fre" +Dump trees after full redundancy elimination. The file name is made +by appending \fI.fre\fR to the source file name. +.IP "\fBcopyprop\fR" 4 +.IX Item "copyprop" +Dump trees after copy propagation. The file name is made +by appending \fI.copyprop\fR to the source file name. +.IP "\fBstore_copyprop\fR" 4 +.IX Item "store_copyprop" +Dump trees after store copy-propagation. The file name is made +by appending \fI.store_copyprop\fR to the source file name. +.IP "\fBdce\fR" 4 +.IX Item "dce" +Dump each function after dead code elimination. The file name is made by +appending \fI.dce\fR to the source file name. +.IP "\fBmudflap\fR" 4 +.IX Item "mudflap" +Dump each function after adding mudflap instrumentation. The file name is +made by appending \fI.mudflap\fR to the source file name. +.IP "\fBsra\fR" 4 +.IX Item "sra" +Dump each function after performing scalar replacement of aggregates. The +file name is made by appending \fI.sra\fR to the source file name. +.IP "\fBsink\fR" 4 +.IX Item "sink" +Dump each function after performing code sinking. The file name is made +by appending \fI.sink\fR to the source file name. +.IP "\fBdom\fR" 4 +.IX Item "dom" +Dump each function after applying dominator tree optimizations. The file +name is made by appending \fI.dom\fR to the source file name. +.IP "\fBdse\fR" 4 +.IX Item "dse" +Dump each function after applying dead store elimination. The file +name is made by appending \fI.dse\fR to the source file name. +.IP "\fBphiopt\fR" 4 +.IX Item "phiopt" +Dump each function after optimizing \s-1PHI\s0 nodes into straightline code. The file +name is made by appending \fI.phiopt\fR to the source file name. +.IP "\fBforwprop\fR" 4 +.IX Item "forwprop" +Dump each function after forward propagating single use variables. The file +name is made by appending \fI.forwprop\fR to the source file name. +.IP "\fBcopyrename\fR" 4 +.IX Item "copyrename" +Dump each function after applying the copy rename optimization. The file +name is made by appending \fI.copyrename\fR to the source file name. +.IP "\fBnrv\fR" 4 +.IX Item "nrv" +Dump each function after applying the named return value optimization on +generic trees. The file name is made by appending \fI.nrv\fR to the source +file name. +.IP "\fBvect\fR" 4 +.IX Item "vect" +Dump each function after applying vectorization of loops. The file name is +made by appending \fI.vect\fR to the source file name. +.IP "\fBslp\fR" 4 +.IX Item "slp" +Dump each function after applying vectorization of basic blocks. The file name +is made by appending \fI.slp\fR to the source file name. +.IP "\fBvrp\fR" 4 +.IX Item "vrp" +Dump each function after Value Range Propagation (\s-1VRP\s0). The file name +is made by appending \fI.vrp\fR to the source file name. +.IP "\fBall\fR" 4 +.IX Item "all" +Enable all the available tree dumps with the flags provided in this option. +.RE +.RS 4 +.RE +.IP "\fB\-ftree\-vectorizer\-verbose=\fR\fIn\fR" 4 +.IX Item "-ftree-vectorizer-verbose=n" +This option controls the amount of debugging output the vectorizer prints. +This information is written to standard error, unless +\&\fB\-fdump\-tree\-all\fR or \fB\-fdump\-tree\-vect\fR is specified, +in which case it is output to the usual dump listing file, \fI.vect\fR. +For \fIn\fR=0 no diagnostic information is reported. +If \fIn\fR=1 the vectorizer reports each loop that got vectorized, +and the total number of loops that got vectorized. +If \fIn\fR=2 the vectorizer also reports non-vectorized loops that passed +the first analysis phase (vect_analyze_loop_form) \- i.e. countable, +inner-most, single-bb, single\-entry/exit loops. This is the same verbosity +level that \fB\-fdump\-tree\-vect\-stats\fR uses. +Higher verbosity levels mean either more information dumped for each +reported loop, or same amount of information reported for more loops: +if \fIn\fR=3, vectorizer cost model information is reported. +If \fIn\fR=4, alignment related information is added to the reports. +If \fIn\fR=5, data-references related information (e.g. memory dependences, +memory access-patterns) is added to the reports. +If \fIn\fR=6, the vectorizer reports also non-vectorized inner-most loops +that did not pass the first analysis phase (i.e., may not be countable, or +may have complicated control-flow). +If \fIn\fR=7, the vectorizer reports also non-vectorized nested loops. +If \fIn\fR=8, \s-1SLP\s0 related information is added to the reports. +For \fIn\fR=9, all the information the vectorizer generates during its +analysis and transformation is reported. This is the same verbosity level +that \fB\-fdump\-tree\-vect\-details\fR uses. +.IP "\fB\-frandom\-seed=\fR\fIstring\fR" 4 +.IX Item "-frandom-seed=string" +This option provides a seed that \s-1GCC\s0 uses when it would otherwise use +random numbers. It is used to generate certain symbol names +that have to be different in every compiled file. It is also used to +place unique stamps in coverage data files and the object files that +produce them. You can use the \fB\-frandom\-seed\fR option to produce +reproducibly identical object files. +.Sp +The \fIstring\fR should be different for every file you compile. +.IP "\fB\-fsched\-verbose=\fR\fIn\fR" 4 +.IX Item "-fsched-verbose=n" +On targets that use instruction scheduling, this option controls the +amount of debugging output the scheduler prints. This information is +written to standard error, unless \fB\-fdump\-rtl\-sched1\fR or +\&\fB\-fdump\-rtl\-sched2\fR is specified, in which case it is output +to the usual dump listing file, \fI.sched1\fR or \fI.sched2\fR +respectively. However for \fIn\fR greater than nine, the output is +always printed to standard error. +.Sp +For \fIn\fR greater than zero, \fB\-fsched\-verbose\fR outputs the +same information as \fB\-fdump\-rtl\-sched1\fR and \fB\-fdump\-rtl\-sched2\fR. +For \fIn\fR greater than one, it also output basic block probabilities, +detailed ready list information and unit/insn info. For \fIn\fR greater +than two, it includes \s-1RTL\s0 at abort point, control-flow and regions info. +And for \fIn\fR over four, \fB\-fsched\-verbose\fR also includes +dependence info. +.IP "\fB\-save\-temps\fR" 4 +.IX Item "-save-temps" +.PD 0 +.IP "\fB\-save\-temps=cwd\fR" 4 +.IX Item "-save-temps=cwd" +.PD +Store the usual \*(L"temporary\*(R" intermediate files permanently; place them +in the current directory and name them based on the source file. Thus, +compiling \fIfoo.c\fR with \fB\-c \-save\-temps\fR would produce files +\&\fIfoo.i\fR and \fIfoo.s\fR, as well as \fIfoo.o\fR. This creates a +preprocessed \fIfoo.i\fR output file even though the compiler now +normally uses an integrated preprocessor. +.Sp +When used in combination with the \fB\-x\fR command line option, +\&\fB\-save\-temps\fR is sensible enough to avoid over writing an +input source file with the same extension as an intermediate file. +The corresponding intermediate file may be obtained by renaming the +source file before using \fB\-save\-temps\fR. +.Sp +If you invoke \s-1GCC\s0 in parallel, compiling several different source +files that share a common base name in different subdirectories or the +same source file compiled for multiple output destinations, it is +likely that the different parallel compilers will interfere with each +other, and overwrite the temporary files. For instance: +.Sp +.Vb 2 +\& gcc \-save\-temps \-o outdir1/foo.o indir1/foo.c& +\& gcc \-save\-temps \-o outdir2/foo.o indir2/foo.c& +.Ve +.Sp +may result in \fIfoo.i\fR and \fIfoo.o\fR being written to +simultaneously by both compilers. +.IP "\fB\-save\-temps=obj\fR" 4 +.IX Item "-save-temps=obj" +Store the usual \*(L"temporary\*(R" intermediate files permanently. If the +\&\fB\-o\fR option is used, the temporary files are based on the +object file. If the \fB\-o\fR option is not used, the +\&\fB\-save\-temps=obj\fR switch behaves like \fB\-save\-temps\fR. +.Sp +For example: +.Sp +.Vb 3 +\& gcc \-save\-temps=obj \-c foo.c +\& gcc \-save\-temps=obj \-c bar.c \-o dir/xbar.o +\& gcc \-save\-temps=obj foobar.c \-o dir2/yfoobar +.Ve +.Sp +would create \fIfoo.i\fR, \fIfoo.s\fR, \fIdir/xbar.i\fR, +\&\fIdir/xbar.s\fR, \fIdir2/yfoobar.i\fR, \fIdir2/yfoobar.s\fR, and +\&\fIdir2/yfoobar.o\fR. +.IP "\fB\-time\fR[\fB=\fR\fIfile\fR]" 4 +.IX Item "-time[=file]" +Report the \s-1CPU\s0 time taken by each subprocess in the compilation +sequence. For C source files, this is the compiler proper and assembler +(plus the linker if linking is done). +.Sp +Without the specification of an output file, the output looks like this: +.Sp +.Vb 2 +\& # cc1 0.12 0.01 +\& # as 0.00 0.01 +.Ve +.Sp +The first number on each line is the \*(L"user time\*(R", that is time spent +executing the program itself. The second number is \*(L"system time\*(R", +time spent executing operating system routines on behalf of the program. +Both numbers are in seconds. +.Sp +With the specification of an output file, the output is appended to the +named file, and it looks like this: +.Sp +.Vb 2 +\& 0.12 0.01 cc1 <options> +\& 0.00 0.01 as <options> +.Ve +.Sp +The \*(L"user time\*(R" and the \*(L"system time\*(R" are moved before the program +name, and the options passed to the program are displayed, so that one +can later tell what file was being compiled, and with which options. +.IP "\fB\-fvar\-tracking\fR" 4 +.IX Item "-fvar-tracking" +Run variable tracking pass. It computes where variables are stored at each +position in code. Better debugging information is then generated +(if the debugging information format supports this information). +.Sp +It is enabled by default when compiling with optimization (\fB\-Os\fR, +\&\fB\-O\fR, \fB\-O2\fR, ...), debugging information (\fB\-g\fR) and +the debug info format supports it. +.IP "\fB\-fvar\-tracking\-assignments\fR" 4 +.IX Item "-fvar-tracking-assignments" +Annotate assignments to user variables early in the compilation and +attempt to carry the annotations over throughout the compilation all the +way to the end, in an attempt to improve debug information while +optimizing. Use of \fB\-gdwarf\-4\fR is recommended along with it. +.Sp +It can be enabled even if var-tracking is disabled, in which case +annotations will be created and maintained, but discarded at the end. +.IP "\fB\-fvar\-tracking\-assignments\-toggle\fR" 4 +.IX Item "-fvar-tracking-assignments-toggle" +Toggle \fB\-fvar\-tracking\-assignments\fR, in the same way that +\&\fB\-gtoggle\fR toggles \fB\-g\fR. +.IP "\fB\-print\-file\-name=\fR\fIlibrary\fR" 4 +.IX Item "-print-file-name=library" +Print the full absolute name of the library file \fIlibrary\fR that +would be used when linking\-\-\-and don't do anything else. With this +option, \s-1GCC\s0 does not compile or link anything; it just prints the +file name. +.IP "\fB\-print\-multi\-directory\fR" 4 +.IX Item "-print-multi-directory" +Print the directory name corresponding to the multilib selected by any +other switches present in the command line. This directory is supposed +to exist in \fB\s-1GCC_EXEC_PREFIX\s0\fR. +.IP "\fB\-print\-multi\-lib\fR" 4 +.IX Item "-print-multi-lib" +Print the mapping from multilib directory names to compiler switches +that enable them. The directory name is separated from the switches by +\&\fB;\fR, and each switch starts with an \fB@\fR instead of the +\&\fB\-\fR, without spaces between multiple switches. This is supposed to +ease shell-processing. +.IP "\fB\-print\-multi\-os\-directory\fR" 4 +.IX Item "-print-multi-os-directory" +Print the path to \s-1OS\s0 libraries for the selected +multilib, relative to some \fIlib\fR subdirectory. If \s-1OS\s0 libraries are +present in the \fIlib\fR subdirectory and no multilibs are used, this is +usually just \fI.\fR, if \s-1OS\s0 libraries are present in \fIlib\fIsuffix\fI\fR +sibling directories this prints e.g. \fI../lib64\fR, \fI../lib\fR or +\&\fI../lib32\fR, or if \s-1OS\s0 libraries are present in \fIlib/\fIsubdir\fI\fR +subdirectories it prints e.g. \fIamd64\fR, \fIsparcv9\fR or \fIev6\fR. +.IP "\fB\-print\-prog\-name=\fR\fIprogram\fR" 4 +.IX Item "-print-prog-name=program" +Like \fB\-print\-file\-name\fR, but searches for a program such as \fBcpp\fR. +.IP "\fB\-print\-libgcc\-file\-name\fR" 4 +.IX Item "-print-libgcc-file-name" +Same as \fB\-print\-file\-name=libgcc.a\fR. +.Sp +This is useful when you use \fB\-nostdlib\fR or \fB\-nodefaultlibs\fR +but you do want to link with \fIlibgcc.a\fR. You can do +.Sp +.Vb 1 +\& gcc \-nostdlib <files>... \`gcc \-print\-libgcc\-file\-name\` +.Ve +.IP "\fB\-print\-search\-dirs\fR" 4 +.IX Item "-print-search-dirs" +Print the name of the configured installation directory and a list of +program and library directories \fBgcc\fR will search\-\-\-and don't do anything else. +.Sp +This is useful when \fBgcc\fR prints the error message +\&\fBinstallation problem, cannot exec cpp0: No such file or directory\fR. +To resolve this you either need to put \fIcpp0\fR and the other compiler +components where \fBgcc\fR expects to find them, or you can set the environment +variable \fB\s-1GCC_EXEC_PREFIX\s0\fR to the directory where you installed them. +Don't forget the trailing \fB/\fR. +.IP "\fB\-print\-sysroot\fR" 4 +.IX Item "-print-sysroot" +Print the target sysroot directory that will be used during +compilation. This is the target sysroot specified either at configure +time or using the \fB\-\-sysroot\fR option, possibly with an extra +suffix that depends on compilation options. If no target sysroot is +specified, the option prints nothing. +.IP "\fB\-print\-sysroot\-headers\-suffix\fR" 4 +.IX Item "-print-sysroot-headers-suffix" +Print the suffix added to the target sysroot when searching for +headers, or give an error if the compiler is not configured with such +a suffix\-\-\-and don't do anything else. +.IP "\fB\-dumpmachine\fR" 4 +.IX Item "-dumpmachine" +Print the compiler's target machine (for example, +\&\fBi686\-pc\-linux\-gnu\fR)\-\-\-and don't do anything else. +.IP "\fB\-dumpversion\fR" 4 +.IX Item "-dumpversion" +Print the compiler version (for example, \fB3.0\fR)\-\-\-and don't do +anything else. +.IP "\fB\-dumpspecs\fR" 4 +.IX Item "-dumpspecs" +Print the compiler's built-in specs\-\-\-and don't do anything else. (This +is used when \s-1GCC\s0 itself is being built.) +.IP "\fB\-feliminate\-unused\-debug\-types\fR" 4 +.IX Item "-feliminate-unused-debug-types" +Normally, when producing \s-1DWARF2\s0 output, \s-1GCC\s0 will emit debugging +information for all types declared in a compilation +unit, regardless of whether or not they are actually used +in that compilation unit. Sometimes this is useful, such as +if, in the debugger, you want to cast a value to a type that is +not actually used in your program (but is declared). More often, +however, this results in a significant amount of wasted space. +With this option, \s-1GCC\s0 will avoid producing debug symbol output +for types that are nowhere used in the source file being compiled. +.SS "Options That Control Optimization" +.IX Subsection "Options That Control Optimization" +These options control various sorts of optimizations. +.PP +Without any optimization option, the compiler's goal is to reduce the +cost of compilation and to make debugging produce the expected +results. Statements are independent: if you stop the program with a +breakpoint between statements, you can then assign a new value to any +variable or change the program counter to any other statement in the +function and get exactly the results you would expect from the source +code. +.PP +Turning on optimization flags makes the compiler attempt to improve +the performance and/or code size at the expense of compilation time +and possibly the ability to debug the program. +.PP +The compiler performs optimization based on the knowledge it has of the +program. Compiling multiple files at once to a single output file mode allows +the compiler to use information gained from all of the files when compiling +each of them. +.PP +Not all optimizations are controlled directly by a flag. Only +optimizations that have a flag are listed in this section. +.PP +Most optimizations are only enabled if an \fB\-O\fR level is set on +the command line. Otherwise they are disabled, even if individual +optimization flags are specified. +.PP +Depending on the target and how \s-1GCC\s0 was configured, a slightly different +set of optimizations may be enabled at each \fB\-O\fR level than +those listed here. You can invoke \s-1GCC\s0 with \fB\-Q \-\-help=optimizers\fR +to find out the exact set of optimizations that are enabled at each level. +.IP "\fB\-O\fR" 4 +.IX Item "-O" +.PD 0 +.IP "\fB\-O1\fR" 4 +.IX Item "-O1" +.PD +Optimize. Optimizing compilation takes somewhat more time, and a lot +more memory for a large function. +.Sp +With \fB\-O\fR, the compiler tries to reduce code size and execution +time, without performing any optimizations that take a great deal of +compilation time. +.Sp +\&\fB\-O\fR turns on the following optimization flags: +.Sp +\&\fB\-fauto\-inc\-dec +\&\-fcompare\-elim +\&\-fcprop\-registers +\&\-fdce +\&\-fdefer\-pop +\&\-fdelayed\-branch +\&\-fdse +\&\-fguess\-branch\-probability +\&\-fif\-conversion2 +\&\-fif\-conversion +\&\-fipa\-pure\-const +\&\-fipa\-profile +\&\-fipa\-reference +\&\-fmerge\-constants +\&\-fsplit\-wide\-types +\&\-ftree\-bit\-ccp +\&\-ftree\-builtin\-call\-dce +\&\-ftree\-ccp +\&\-ftree\-ch +\&\-ftree\-copyrename +\&\-ftree\-dce +\&\-ftree\-dominator\-opts +\&\-ftree\-dse +\&\-ftree\-forwprop +\&\-ftree\-fre +\&\-ftree\-phiprop +\&\-ftree\-sra +\&\-ftree\-pta +\&\-ftree\-ter +\&\-funit\-at\-a\-time\fR +.Sp +\&\fB\-O\fR also turns on \fB\-fomit\-frame\-pointer\fR on machines +where doing so does not interfere with debugging. +.IP "\fB\-O2\fR" 4 +.IX Item "-O2" +Optimize even more. \s-1GCC\s0 performs nearly all supported optimizations +that do not involve a space-speed tradeoff. +As compared to \fB\-O\fR, this option increases both compilation time +and the performance of the generated code. +.Sp +\&\fB\-O2\fR turns on all optimization flags specified by \fB\-O\fR. It +also turns on the following optimization flags: +\&\fB\-fthread\-jumps +\&\-falign\-functions \-falign\-jumps +\&\-falign\-loops \-falign\-labels +\&\-fcaller\-saves +\&\-fcrossjumping +\&\-fcse\-follow\-jumps \-fcse\-skip\-blocks +\&\-fdelete\-null\-pointer\-checks +\&\-fdevirtualize +\&\-fexpensive\-optimizations +\&\-fgcse \-fgcse\-lm +\&\-finline\-small\-functions +\&\-findirect\-inlining +\&\-fipa\-sra +\&\-foptimize\-sibling\-calls +\&\-fpartial\-inlining +\&\-fpeephole2 +\&\-fregmove +\&\-freorder\-blocks \-freorder\-functions +\&\-frerun\-cse\-after\-loop +\&\-fsched\-interblock \-fsched\-spec +\&\-fschedule\-insns \-fschedule\-insns2 +\&\-fstrict\-aliasing \-fstrict\-overflow +\&\-ftree\-switch\-conversion +\&\-ftree\-pre +\&\-ftree\-vrp\fR +.Sp +Please note the warning under \fB\-fgcse\fR about +invoking \fB\-O2\fR on programs that use computed gotos. +.IP "\fB\-O3\fR" 4 +.IX Item "-O3" +Optimize yet more. \fB\-O3\fR turns on all optimizations specified +by \fB\-O2\fR and also turns on the \fB\-finline\-functions\fR, +\&\fB\-funswitch\-loops\fR, \fB\-fpredictive\-commoning\fR, +\&\fB\-fgcse\-after\-reload\fR, \fB\-ftree\-vectorize\fR and +\&\fB\-fipa\-cp\-clone\fR options. +.IP "\fB\-O0\fR" 4 +.IX Item "-O0" +Reduce compilation time and make debugging produce the expected +results. This is the default. +.IP "\fB\-Os\fR" 4 +.IX Item "-Os" +Optimize for size. \fB\-Os\fR enables all \fB\-O2\fR optimizations that +do not typically increase code size. It also performs further +optimizations designed to reduce code size. +.Sp +\&\fB\-Os\fR disables the following optimization flags: +\&\fB\-falign\-functions \-falign\-jumps \-falign\-loops +\&\-falign\-labels \-freorder\-blocks \-freorder\-blocks\-and\-partition +\&\-fprefetch\-loop\-arrays \-ftree\-vect\-loop\-version\fR +.IP "\fB\-Ofast\fR" 4 +.IX Item "-Ofast" +Disregard strict standards compliance. \fB\-Ofast\fR enables all +\&\fB\-O3\fR optimizations. It also enables optimizations that are not +valid for all standard compliant programs. +It turns on \fB\-ffast\-math\fR. +.Sp +If you use multiple \fB\-O\fR options, with or without level numbers, +the last such option is the one that is effective. +.PP +Options of the form \fB\-f\fR\fIflag\fR specify machine-independent +flags. Most flags have both positive and negative forms; the negative +form of \fB\-ffoo\fR would be \fB\-fno\-foo\fR. In the table +below, only one of the forms is listed\-\-\-the one you typically will +use. You can figure out the other form by either removing \fBno\-\fR +or adding it. +.PP +The following options control specific optimizations. They are either +activated by \fB\-O\fR options or are related to ones that are. You +can use the following flags in the rare cases when \*(L"fine-tuning\*(R" of +optimizations to be performed is desired. +.IP "\fB\-fno\-default\-inline\fR" 4 +.IX Item "-fno-default-inline" +Do not make member functions inline by default merely because they are +defined inside the class scope (\*(C+ only). Otherwise, when you specify +\&\fB\-O\fR, member functions defined inside class scope are compiled +inline by default; i.e., you don't need to add \fBinline\fR in front of +the member function name. +.IP "\fB\-fno\-defer\-pop\fR" 4 +.IX Item "-fno-defer-pop" +Always pop the arguments to each function call as soon as that function +returns. For machines which must pop arguments after a function call, +the compiler normally lets arguments accumulate on the stack for several +function calls and pops them all at once. +.Sp +Disabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fforward\-propagate\fR" 4 +.IX Item "-fforward-propagate" +Perform a forward propagation pass on \s-1RTL\s0. The pass tries to combine two +instructions and checks if the result can be simplified. If loop unrolling +is active, two passes are performed and the second is scheduled after +loop unrolling. +.Sp +This option is enabled by default at optimization levels \fB\-O\fR, +\&\fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-ffp\-contract=\fR\fIstyle\fR" 4 +.IX Item "-ffp-contract=style" +\&\fB\-ffp\-contract=off\fR disables floating-point expression contraction. +\&\fB\-ffp\-contract=fast\fR enables floating-point expression contraction +such as forming of fused multiply-add operations if the target has +native support for them. +\&\fB\-ffp\-contract=on\fR enables floating-point expression contraction +if allowed by the language standard. This is currently not implemented +and treated equal to \fB\-ffp\-contract=off\fR. +.Sp +The default is \fB\-ffp\-contract=fast\fR. +.IP "\fB\-fomit\-frame\-pointer\fR" 4 +.IX Item "-fomit-frame-pointer" +Don't keep the frame pointer in a register for functions that +don't need one. This avoids the instructions to save, set up and +restore frame pointers; it also makes an extra register available +in many functions. \fBIt also makes debugging impossible on +some machines.\fR +.Sp +On some machines, such as the \s-1VAX\s0, this flag has no effect, because +the standard calling sequence automatically handles the frame pointer +and nothing is saved by pretending it doesn't exist. The +machine-description macro \f(CW\*(C`FRAME_POINTER_REQUIRED\*(C'\fR controls +whether a target machine supports this flag. +.Sp +Starting with \s-1GCC\s0 version 4.6, the default setting (when not optimizing for +size) for 32\-bit Linux x86 and 32\-bit Darwin x86 targets has been changed to +\&\fB\-fomit\-frame\-pointer\fR. The default can be reverted to +\&\fB\-fno\-omit\-frame\-pointer\fR by configuring \s-1GCC\s0 with the +\&\fB\-\-enable\-frame\-pointer\fR configure option. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-foptimize\-sibling\-calls\fR" 4 +.IX Item "-foptimize-sibling-calls" +Optimize sibling and tail recursive calls. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fno\-inline\fR" 4 +.IX Item "-fno-inline" +Don't pay attention to the \f(CW\*(C`inline\*(C'\fR keyword. Normally this option +is used to keep the compiler from expanding any functions inline. +Note that if you are not optimizing, no functions can be expanded inline. +.IP "\fB\-finline\-small\-functions\fR" 4 +.IX Item "-finline-small-functions" +Integrate functions into their callers when their body is smaller than expected +function call code (so overall size of program gets smaller). The compiler +heuristically decides which functions are simple enough to be worth integrating +in this way. +.Sp +Enabled at level \fB\-O2\fR. +.IP "\fB\-findirect\-inlining\fR" 4 +.IX Item "-findirect-inlining" +Inline also indirect calls that are discovered to be known at compile +time thanks to previous inlining. This option has any effect only +when inlining itself is turned on by the \fB\-finline\-functions\fR +or \fB\-finline\-small\-functions\fR options. +.Sp +Enabled at level \fB\-O2\fR. +.IP "\fB\-finline\-functions\fR" 4 +.IX Item "-finline-functions" +Integrate all simple functions into their callers. The compiler +heuristically decides which functions are simple enough to be worth +integrating in this way. +.Sp +If all calls to a given function are integrated, and the function is +declared \f(CW\*(C`static\*(C'\fR, then the function is normally not output as +assembler code in its own right. +.Sp +Enabled at level \fB\-O3\fR. +.IP "\fB\-finline\-functions\-called\-once\fR" 4 +.IX Item "-finline-functions-called-once" +Consider all \f(CW\*(C`static\*(C'\fR functions called once for inlining into their +caller even if they are not marked \f(CW\*(C`inline\*(C'\fR. If a call to a given +function is integrated, then the function is not output as assembler code +in its own right. +.Sp +Enabled at levels \fB\-O1\fR, \fB\-O2\fR, \fB\-O3\fR and \fB\-Os\fR. +.IP "\fB\-fearly\-inlining\fR" 4 +.IX Item "-fearly-inlining" +Inline functions marked by \f(CW\*(C`always_inline\*(C'\fR and functions whose body seems +smaller than the function call overhead early before doing +\&\fB\-fprofile\-generate\fR instrumentation and real inlining pass. Doing so +makes profiling significantly cheaper and usually inlining faster on programs +having large chains of nested wrapper functions. +.Sp +Enabled by default. +.IP "\fB\-fipa\-sra\fR" 4 +.IX Item "-fipa-sra" +Perform interprocedural scalar replacement of aggregates, removal of +unused parameters and replacement of parameters passed by reference +by parameters passed by value. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR and \fB\-Os\fR. +.IP "\fB\-finline\-limit=\fR\fIn\fR" 4 +.IX Item "-finline-limit=n" +By default, \s-1GCC\s0 limits the size of functions that can be inlined. This flag +allows coarse control of this limit. \fIn\fR is the size of functions that +can be inlined in number of pseudo instructions. +.Sp +Inlining is actually controlled by a number of parameters, which may be +specified individually by using \fB\-\-param\fR \fIname\fR\fB=\fR\fIvalue\fR. +The \fB\-finline\-limit=\fR\fIn\fR option sets some of these parameters +as follows: +.RS 4 +.IP "\fBmax-inline-insns-single\fR" 4 +.IX Item "max-inline-insns-single" +is set to \fIn\fR/2. +.IP "\fBmax-inline-insns-auto\fR" 4 +.IX Item "max-inline-insns-auto" +is set to \fIn\fR/2. +.RE +.RS 4 +.Sp +See below for a documentation of the individual +parameters controlling inlining and for the defaults of these parameters. +.Sp +\&\fINote:\fR there may be no value to \fB\-finline\-limit\fR that results +in default behavior. +.Sp +\&\fINote:\fR pseudo instruction represents, in this particular context, an +abstract measurement of function's size. In no way does it represent a count +of assembly instructions and as such its exact meaning might change from one +release to an another. +.RE +.IP "\fB\-fno\-keep\-inline\-dllexport\fR" 4 +.IX Item "-fno-keep-inline-dllexport" +This is a more fine-grained version of \fB\-fkeep\-inline\-functions\fR, +which applies only to functions that are declared using the \f(CW\*(C`dllexport\*(C'\fR +attribute or declspec +.IP "\fB\-fkeep\-inline\-functions\fR" 4 +.IX Item "-fkeep-inline-functions" +In C, emit \f(CW\*(C`static\*(C'\fR functions that are declared \f(CW\*(C`inline\*(C'\fR +into the object file, even if the function has been inlined into all +of its callers. This switch does not affect functions using the +\&\f(CW\*(C`extern inline\*(C'\fR extension in \s-1GNU\s0 C90. In \*(C+, emit any and all +inline functions into the object file. +.IP "\fB\-fkeep\-static\-consts\fR" 4 +.IX Item "-fkeep-static-consts" +Emit variables declared \f(CW\*(C`static const\*(C'\fR when optimization isn't turned +on, even if the variables aren't referenced. +.Sp +\&\s-1GCC\s0 enables this option by default. If you want to force the compiler to +check if the variable was referenced, regardless of whether or not +optimization is turned on, use the \fB\-fno\-keep\-static\-consts\fR option. +.IP "\fB\-fmerge\-constants\fR" 4 +.IX Item "-fmerge-constants" +Attempt to merge identical constants (string constants and floating point +constants) across compilation units. +.Sp +This option is the default for optimized compilation if the assembler and +linker support it. Use \fB\-fno\-merge\-constants\fR to inhibit this +behavior. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fmerge\-all\-constants\fR" 4 +.IX Item "-fmerge-all-constants" +Attempt to merge identical constants and identical variables. +.Sp +This option implies \fB\-fmerge\-constants\fR. In addition to +\&\fB\-fmerge\-constants\fR this considers e.g. even constant initialized +arrays or initialized constant variables with integral or floating point +types. Languages like C or \*(C+ require each variable, including multiple +instances of the same variable in recursive calls, to have distinct locations, +so using this option will result in non-conforming +behavior. +.IP "\fB\-fmodulo\-sched\fR" 4 +.IX Item "-fmodulo-sched" +Perform swing modulo scheduling immediately before the first scheduling +pass. This pass looks at innermost loops and reorders their +instructions by overlapping different iterations. +.IP "\fB\-fmodulo\-sched\-allow\-regmoves\fR" 4 +.IX Item "-fmodulo-sched-allow-regmoves" +Perform more aggressive \s-1SMS\s0 based modulo scheduling with register moves +allowed. By setting this flag certain anti-dependences edges will be +deleted which will trigger the generation of reg-moves based on the +life-range analysis. This option is effective only with +\&\fB\-fmodulo\-sched\fR enabled. +.IP "\fB\-fno\-branch\-count\-reg\fR" 4 +.IX Item "-fno-branch-count-reg" +Do not use \*(L"decrement and branch\*(R" instructions on a count register, +but instead generate a sequence of instructions that decrement a +register, compare it against zero, then branch based upon the result. +This option is only meaningful on architectures that support such +instructions, which include x86, PowerPC, \s-1IA\-64\s0 and S/390. +.Sp +The default is \fB\-fbranch\-count\-reg\fR. +.IP "\fB\-fno\-function\-cse\fR" 4 +.IX Item "-fno-function-cse" +Do not put function addresses in registers; make each instruction that +calls a constant function contain the function's address explicitly. +.Sp +This option results in less efficient code, but some strange hacks +that alter the assembler output may be confused by the optimizations +performed when this option is not used. +.Sp +The default is \fB\-ffunction\-cse\fR +.IP "\fB\-fno\-zero\-initialized\-in\-bss\fR" 4 +.IX Item "-fno-zero-initialized-in-bss" +If the target supports a \s-1BSS\s0 section, \s-1GCC\s0 by default puts variables that +are initialized to zero into \s-1BSS\s0. This can save space in the resulting +code. +.Sp +This option turns off this behavior because some programs explicitly +rely on variables going to the data section. E.g., so that the +resulting executable can find the beginning of that section and/or make +assumptions based on that. +.Sp +The default is \fB\-fzero\-initialized\-in\-bss\fR. +.IP "\fB\-fmudflap \-fmudflapth \-fmudflapir\fR" 4 +.IX Item "-fmudflap -fmudflapth -fmudflapir" +For front-ends that support it (C and \*(C+), instrument all risky +pointer/array dereferencing operations, some standard library +string/heap functions, and some other associated constructs with +range/validity tests. Modules so instrumented should be immune to +buffer overflows, invalid heap use, and some other classes of C/\*(C+ +programming errors. The instrumentation relies on a separate runtime +library (\fIlibmudflap\fR), which will be linked into a program if +\&\fB\-fmudflap\fR is given at link time. Run-time behavior of the +instrumented program is controlled by the \fB\s-1MUDFLAP_OPTIONS\s0\fR +environment variable. See \f(CW\*(C`env MUDFLAP_OPTIONS=\-help a.out\*(C'\fR +for its options. +.Sp +Use \fB\-fmudflapth\fR instead of \fB\-fmudflap\fR to compile and to +link if your program is multi-threaded. Use \fB\-fmudflapir\fR, in +addition to \fB\-fmudflap\fR or \fB\-fmudflapth\fR, if +instrumentation should ignore pointer reads. This produces less +instrumentation (and therefore faster execution) and still provides +some protection against outright memory corrupting writes, but allows +erroneously read data to propagate within a program. +.IP "\fB\-fthread\-jumps\fR" 4 +.IX Item "-fthread-jumps" +Perform optimizations where we check to see if a jump branches to a +location where another comparison subsumed by the first is found. If +so, the first branch is redirected to either the destination of the +second branch or a point immediately following it, depending on whether +the condition is known to be true or false. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fsplit\-wide\-types\fR" 4 +.IX Item "-fsplit-wide-types" +When using a type that occupies multiple registers, such as \f(CW\*(C`long +long\*(C'\fR on a 32\-bit system, split the registers apart and allocate them +independently. This normally generates better code for those types, +but may make debugging more difficult. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, +\&\fB\-Os\fR. +.IP "\fB\-fcse\-follow\-jumps\fR" 4 +.IX Item "-fcse-follow-jumps" +In common subexpression elimination (\s-1CSE\s0), scan through jump instructions +when the target of the jump is not reached by any other path. For +example, when \s-1CSE\s0 encounters an \f(CW\*(C`if\*(C'\fR statement with an +\&\f(CW\*(C`else\*(C'\fR clause, \s-1CSE\s0 will follow the jump when the condition +tested is false. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fcse\-skip\-blocks\fR" 4 +.IX Item "-fcse-skip-blocks" +This is similar to \fB\-fcse\-follow\-jumps\fR, but causes \s-1CSE\s0 to +follow jumps which conditionally skip over blocks. When \s-1CSE\s0 +encounters a simple \f(CW\*(C`if\*(C'\fR statement with no else clause, +\&\fB\-fcse\-skip\-blocks\fR causes \s-1CSE\s0 to follow the jump around the +body of the \f(CW\*(C`if\*(C'\fR. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-frerun\-cse\-after\-loop\fR" 4 +.IX Item "-frerun-cse-after-loop" +Re-run common subexpression elimination after loop optimizations has been +performed. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fgcse\fR" 4 +.IX Item "-fgcse" +Perform a global common subexpression elimination pass. +This pass also performs global constant and copy propagation. +.Sp +\&\fINote:\fR When compiling a program using computed gotos, a \s-1GCC\s0 +extension, you may get better runtime performance if you disable +the global common subexpression elimination pass by adding +\&\fB\-fno\-gcse\fR to the command line. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fgcse\-lm\fR" 4 +.IX Item "-fgcse-lm" +When \fB\-fgcse\-lm\fR is enabled, global common subexpression elimination will +attempt to move loads which are only killed by stores into themselves. This +allows a loop containing a load/store sequence to be changed to a load outside +the loop, and a copy/store within the loop. +.Sp +Enabled by default when gcse is enabled. +.IP "\fB\-fgcse\-sm\fR" 4 +.IX Item "-fgcse-sm" +When \fB\-fgcse\-sm\fR is enabled, a store motion pass is run after +global common subexpression elimination. This pass will attempt to move +stores out of loops. When used in conjunction with \fB\-fgcse\-lm\fR, +loops containing a load/store sequence can be changed to a load before +the loop and a store after the loop. +.Sp +Not enabled at any optimization level. +.IP "\fB\-fgcse\-las\fR" 4 +.IX Item "-fgcse-las" +When \fB\-fgcse\-las\fR is enabled, the global common subexpression +elimination pass eliminates redundant loads that come after stores to the +same memory location (both partial and full redundancies). +.Sp +Not enabled at any optimization level. +.IP "\fB\-fgcse\-after\-reload\fR" 4 +.IX Item "-fgcse-after-reload" +When \fB\-fgcse\-after\-reload\fR is enabled, a redundant load elimination +pass is performed after reload. The purpose of this pass is to cleanup +redundant spilling. +.IP "\fB\-funsafe\-loop\-optimizations\fR" 4 +.IX Item "-funsafe-loop-optimizations" +If given, the loop optimizer will assume that loop indices do not +overflow, and that the loops with nontrivial exit condition are not +infinite. This enables a wider range of loop optimizations even if +the loop optimizer itself cannot prove that these assumptions are valid. +Using \fB\-Wunsafe\-loop\-optimizations\fR, the compiler will warn you +if it finds this kind of loop. +.IP "\fB\-fcrossjumping\fR" 4 +.IX Item "-fcrossjumping" +Perform cross-jumping transformation. This transformation unifies equivalent code and save code size. The +resulting code may or may not perform better than without cross-jumping. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fauto\-inc\-dec\fR" 4 +.IX Item "-fauto-inc-dec" +Combine increments or decrements of addresses with memory accesses. +This pass is always skipped on architectures that do not have +instructions to support this. Enabled by default at \fB\-O\fR and +higher on architectures that support this. +.IP "\fB\-fdce\fR" 4 +.IX Item "-fdce" +Perform dead code elimination (\s-1DCE\s0) on \s-1RTL\s0. +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fdse\fR" 4 +.IX Item "-fdse" +Perform dead store elimination (\s-1DSE\s0) on \s-1RTL\s0. +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fif\-conversion\fR" 4 +.IX Item "-fif-conversion" +Attempt to transform conditional jumps into branch-less equivalents. This +include use of conditional moves, min, max, set flags and abs instructions, and +some tricks doable by standard arithmetics. The use of conditional execution +on chips where it is available is controlled by \f(CW\*(C`if\-conversion2\*(C'\fR. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fif\-conversion2\fR" 4 +.IX Item "-fif-conversion2" +Use conditional execution (where available) to transform conditional jumps into +branch-less equivalents. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fdelete\-null\-pointer\-checks\fR" 4 +.IX Item "-fdelete-null-pointer-checks" +Assume that programs cannot safely dereference null pointers, and that +no code or data element resides there. This enables simple constant +folding optimizations at all optimization levels. In addition, other +optimization passes in \s-1GCC\s0 use this flag to control global dataflow +analyses that eliminate useless checks for null pointers; these assume +that if a pointer is checked after it has already been dereferenced, +it cannot be null. +.Sp +Note however that in some environments this assumption is not true. +Use \fB\-fno\-delete\-null\-pointer\-checks\fR to disable this optimization +for programs which depend on that behavior. +.Sp +Some targets, especially embedded ones, disable this option at all levels. +Otherwise it is enabled at all levels: \fB\-O0\fR, \fB\-O1\fR, +\&\fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. Passes that use the information +are enabled independently at different optimization levels. +.IP "\fB\-fdevirtualize\fR" 4 +.IX Item "-fdevirtualize" +Attempt to convert calls to virtual functions to direct calls. This +is done both within a procedure and interprocedurally as part of +indirect inlining (\f(CW\*(C`\-findirect\-inlining\*(C'\fR) and interprocedural constant +propagation (\fB\-fipa\-cp\fR). +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fexpensive\-optimizations\fR" 4 +.IX Item "-fexpensive-optimizations" +Perform a number of minor optimizations that are relatively expensive. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-foptimize\-register\-move\fR" 4 +.IX Item "-foptimize-register-move" +.PD 0 +.IP "\fB\-fregmove\fR" 4 +.IX Item "-fregmove" +.PD +Attempt to reassign register numbers in move instructions and as +operands of other simple instructions in order to maximize the amount of +register tying. This is especially helpful on machines with two-operand +instructions. +.Sp +Note \fB\-fregmove\fR and \fB\-foptimize\-register\-move\fR are the same +optimization. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fira\-algorithm=\fR\fIalgorithm\fR" 4 +.IX Item "-fira-algorithm=algorithm" +Use specified coloring algorithm for the integrated register +allocator. The \fIalgorithm\fR argument should be \f(CW\*(C`priority\*(C'\fR or +\&\f(CW\*(C`CB\*(C'\fR. The first algorithm specifies Chow's priority coloring, +the second one specifies Chaitin-Briggs coloring. The second +algorithm can be unimplemented for some architectures. If it is +implemented, it is the default because Chaitin-Briggs coloring as a +rule generates a better code. +.IP "\fB\-fira\-region=\fR\fIregion\fR" 4 +.IX Item "-fira-region=region" +Use specified regions for the integrated register allocator. The +\&\fIregion\fR argument should be one of \f(CW\*(C`all\*(C'\fR, \f(CW\*(C`mixed\*(C'\fR, or +\&\f(CW\*(C`one\*(C'\fR. The first value means using all loops as register +allocation regions, the second value which is the default means using +all loops except for loops with small register pressure as the +regions, and third one means using all function as a single region. +The first value can give best result for machines with small size and +irregular register set, the third one results in faster and generates +decent code and the smallest size code, and the default value usually +give the best results in most cases and for most architectures. +.IP "\fB\-fira\-loop\-pressure\fR" 4 +.IX Item "-fira-loop-pressure" +Use \s-1IRA\s0 to evaluate register pressure in loops for decision to move +loop invariants. Usage of this option usually results in generation +of faster and smaller code on machines with big register files (>= 32 +registers) but it can slow compiler down. +.Sp +This option is enabled at level \fB\-O3\fR for some targets. +.IP "\fB\-fno\-ira\-share\-save\-slots\fR" 4 +.IX Item "-fno-ira-share-save-slots" +Switch off sharing stack slots used for saving call used hard +registers living through a call. Each hard register will get a +separate stack slot and as a result function stack frame will be +bigger. +.IP "\fB\-fno\-ira\-share\-spill\-slots\fR" 4 +.IX Item "-fno-ira-share-spill-slots" +Switch off sharing stack slots allocated for pseudo-registers. Each +pseudo-register which did not get a hard register will get a separate +stack slot and as a result function stack frame will be bigger. +.IP "\fB\-fira\-verbose=\fR\fIn\fR" 4 +.IX Item "-fira-verbose=n" +Set up how verbose dump file for the integrated register allocator +will be. Default value is 5. If the value is greater or equal to 10, +the dump file will be stderr as if the value were \fIn\fR minus 10. +.IP "\fB\-fdelayed\-branch\fR" 4 +.IX Item "-fdelayed-branch" +If supported for the target machine, attempt to reorder instructions +to exploit instruction slots available after delayed branch +instructions. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fschedule\-insns\fR" 4 +.IX Item "-fschedule-insns" +If supported for the target machine, attempt to reorder instructions to +eliminate execution stalls due to required data being unavailable. This +helps machines that have slow floating point or memory load instructions +by allowing other instructions to be issued until the result of the load +or floating point instruction is required. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-fschedule\-insns2\fR" 4 +.IX Item "-fschedule-insns2" +Similar to \fB\-fschedule\-insns\fR, but requests an additional pass of +instruction scheduling after register allocation has been done. This is +especially useful on machines with a relatively small number of +registers and where memory load instructions take more than one cycle. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fno\-sched\-interblock\fR" 4 +.IX Item "-fno-sched-interblock" +Don't schedule instructions across basic blocks. This is normally +enabled by default when scheduling before register allocation, i.e. +with \fB\-fschedule\-insns\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fno\-sched\-spec\fR" 4 +.IX Item "-fno-sched-spec" +Don't allow speculative motion of non-load instructions. This is normally +enabled by default when scheduling before register allocation, i.e. +with \fB\-fschedule\-insns\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-pressure\fR" 4 +.IX Item "-fsched-pressure" +Enable register pressure sensitive insn scheduling before the register +allocation. This only makes sense when scheduling before register +allocation is enabled, i.e. with \fB\-fschedule\-insns\fR or at +\&\fB\-O2\fR or higher. Usage of this option can improve the +generated code and decrease its size by preventing register pressure +increase above the number of available hard registers and as a +consequence register spills in the register allocation. +.IP "\fB\-fsched\-spec\-load\fR" 4 +.IX Item "-fsched-spec-load" +Allow speculative motion of some load instructions. This only makes +sense when scheduling before register allocation, i.e. with +\&\fB\-fschedule\-insns\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-spec\-load\-dangerous\fR" 4 +.IX Item "-fsched-spec-load-dangerous" +Allow speculative motion of more load instructions. This only makes +sense when scheduling before register allocation, i.e. with +\&\fB\-fschedule\-insns\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-stalled\-insns\fR" 4 +.IX Item "-fsched-stalled-insns" +.PD 0 +.IP "\fB\-fsched\-stalled\-insns=\fR\fIn\fR" 4 +.IX Item "-fsched-stalled-insns=n" +.PD +Define how many insns (if any) can be moved prematurely from the queue +of stalled insns into the ready list, during the second scheduling pass. +\&\fB\-fno\-sched\-stalled\-insns\fR means that no insns will be moved +prematurely, \fB\-fsched\-stalled\-insns=0\fR means there is no limit +on how many queued insns can be moved prematurely. +\&\fB\-fsched\-stalled\-insns\fR without a value is equivalent to +\&\fB\-fsched\-stalled\-insns=1\fR. +.IP "\fB\-fsched\-stalled\-insns\-dep\fR" 4 +.IX Item "-fsched-stalled-insns-dep" +.PD 0 +.IP "\fB\-fsched\-stalled\-insns\-dep=\fR\fIn\fR" 4 +.IX Item "-fsched-stalled-insns-dep=n" +.PD +Define how many insn groups (cycles) will be examined for a dependency +on a stalled insn that is candidate for premature removal from the queue +of stalled insns. This has an effect only during the second scheduling pass, +and only if \fB\-fsched\-stalled\-insns\fR is used. +\&\fB\-fno\-sched\-stalled\-insns\-dep\fR is equivalent to +\&\fB\-fsched\-stalled\-insns\-dep=0\fR. +\&\fB\-fsched\-stalled\-insns\-dep\fR without a value is equivalent to +\&\fB\-fsched\-stalled\-insns\-dep=1\fR. +.IP "\fB\-fsched2\-use\-superblocks\fR" 4 +.IX Item "-fsched2-use-superblocks" +When scheduling after register allocation, do use superblock scheduling +algorithm. Superblock scheduling allows motion across basic block boundaries +resulting on faster schedules. This option is experimental, as not all machine +descriptions used by \s-1GCC\s0 model the \s-1CPU\s0 closely enough to avoid unreliable +results from the algorithm. +.Sp +This only makes sense when scheduling after register allocation, i.e. with +\&\fB\-fschedule\-insns2\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-group\-heuristic\fR" 4 +.IX Item "-fsched-group-heuristic" +Enable the group heuristic in the scheduler. This heuristic favors +the instruction that belongs to a schedule group. This is enabled +by default when scheduling is enabled, i.e. with \fB\-fschedule\-insns\fR +or \fB\-fschedule\-insns2\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-critical\-path\-heuristic\fR" 4 +.IX Item "-fsched-critical-path-heuristic" +Enable the critical-path heuristic in the scheduler. This heuristic favors +instructions on the critical path. This is enabled by default when +scheduling is enabled, i.e. with \fB\-fschedule\-insns\fR +or \fB\-fschedule\-insns2\fR or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-spec\-insn\-heuristic\fR" 4 +.IX Item "-fsched-spec-insn-heuristic" +Enable the speculative instruction heuristic in the scheduler. This +heuristic favors speculative instructions with greater dependency weakness. +This is enabled by default when scheduling is enabled, i.e. +with \fB\-fschedule\-insns\fR or \fB\-fschedule\-insns2\fR +or at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-rank\-heuristic\fR" 4 +.IX Item "-fsched-rank-heuristic" +Enable the rank heuristic in the scheduler. This heuristic favors +the instruction belonging to a basic block with greater size or frequency. +This is enabled by default when scheduling is enabled, i.e. +with \fB\-fschedule\-insns\fR or \fB\-fschedule\-insns2\fR or +at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-last\-insn\-heuristic\fR" 4 +.IX Item "-fsched-last-insn-heuristic" +Enable the last-instruction heuristic in the scheduler. This heuristic +favors the instruction that is less dependent on the last instruction +scheduled. This is enabled by default when scheduling is enabled, +i.e. with \fB\-fschedule\-insns\fR or \fB\-fschedule\-insns2\fR or +at \fB\-O2\fR or higher. +.IP "\fB\-fsched\-dep\-count\-heuristic\fR" 4 +.IX Item "-fsched-dep-count-heuristic" +Enable the dependent-count heuristic in the scheduler. This heuristic +favors the instruction that has more instructions depending on it. +This is enabled by default when scheduling is enabled, i.e. +with \fB\-fschedule\-insns\fR or \fB\-fschedule\-insns2\fR or +at \fB\-O2\fR or higher. +.IP "\fB\-freschedule\-modulo\-scheduled\-loops\fR" 4 +.IX Item "-freschedule-modulo-scheduled-loops" +The modulo scheduling comes before the traditional scheduling, if a loop +was modulo scheduled we may want to prevent the later scheduling passes +from changing its schedule, we use this option to control that. +.IP "\fB\-fselective\-scheduling\fR" 4 +.IX Item "-fselective-scheduling" +Schedule instructions using selective scheduling algorithm. Selective +scheduling runs instead of the first scheduler pass. +.IP "\fB\-fselective\-scheduling2\fR" 4 +.IX Item "-fselective-scheduling2" +Schedule instructions using selective scheduling algorithm. Selective +scheduling runs instead of the second scheduler pass. +.IP "\fB\-fsel\-sched\-pipelining\fR" 4 +.IX Item "-fsel-sched-pipelining" +Enable software pipelining of innermost loops during selective scheduling. +This option has no effect until one of \fB\-fselective\-scheduling\fR or +\&\fB\-fselective\-scheduling2\fR is turned on. +.IP "\fB\-fsel\-sched\-pipelining\-outer\-loops\fR" 4 +.IX Item "-fsel-sched-pipelining-outer-loops" +When pipelining loops during selective scheduling, also pipeline outer loops. +This option has no effect until \fB\-fsel\-sched\-pipelining\fR is turned on. +.IP "\fB\-fcaller\-saves\fR" 4 +.IX Item "-fcaller-saves" +Enable values to be allocated in registers that will be clobbered by +function calls, by emitting extra instructions to save and restore the +registers around such calls. Such allocation is done only when it +seems to result in better code than would otherwise be produced. +.Sp +This option is always enabled by default on certain machines, usually +those which have no call-preserved registers to use instead. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fcombine\-stack\-adjustments\fR" 4 +.IX Item "-fcombine-stack-adjustments" +Tracks stack adjustments (pushes and pops) and stack memory references +and then tries to find ways to combine them. +.Sp +Enabled by default at \fB\-O1\fR and higher. +.IP "\fB\-fconserve\-stack\fR" 4 +.IX Item "-fconserve-stack" +Attempt to minimize stack usage. The compiler will attempt to use less +stack space, even if that makes the program slower. This option +implies setting the \fBlarge-stack-frame\fR parameter to 100 +and the \fBlarge-stack-frame-growth\fR parameter to 400. +.IP "\fB\-ftree\-reassoc\fR" 4 +.IX Item "-ftree-reassoc" +Perform reassociation on trees. This flag is enabled by default +at \fB\-O\fR and higher. +.IP "\fB\-ftree\-pre\fR" 4 +.IX Item "-ftree-pre" +Perform partial redundancy elimination (\s-1PRE\s0) on trees. This flag is +enabled by default at \fB\-O2\fR and \fB\-O3\fR. +.IP "\fB\-ftree\-forwprop\fR" 4 +.IX Item "-ftree-forwprop" +Perform forward propagation on trees. This flag is enabled by default +at \fB\-O\fR and higher. +.IP "\fB\-ftree\-fre\fR" 4 +.IX Item "-ftree-fre" +Perform full redundancy elimination (\s-1FRE\s0) on trees. The difference +between \s-1FRE\s0 and \s-1PRE\s0 is that \s-1FRE\s0 only considers expressions +that are computed on all paths leading to the redundant computation. +This analysis is faster than \s-1PRE\s0, though it exposes fewer redundancies. +This flag is enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-phiprop\fR" 4 +.IX Item "-ftree-phiprop" +Perform hoisting of loads from conditional pointers on trees. This +pass is enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-copy\-prop\fR" 4 +.IX Item "-ftree-copy-prop" +Perform copy propagation on trees. This pass eliminates unnecessary +copy operations. This flag is enabled by default at \fB\-O\fR and +higher. +.IP "\fB\-fipa\-pure\-const\fR" 4 +.IX Item "-fipa-pure-const" +Discover which functions are pure or constant. +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fipa\-reference\fR" 4 +.IX Item "-fipa-reference" +Discover which static variables do not escape cannot escape the +compilation unit. +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fipa\-struct\-reorg\fR" 4 +.IX Item "-fipa-struct-reorg" +Perform structure reorganization optimization, that change C\-like structures +layout in order to better utilize spatial locality. This transformation is +affective for programs containing arrays of structures. Available in two +compilation modes: profile-based (enabled with \fB\-fprofile\-generate\fR) +or static (which uses built-in heuristics). It works only in whole program +mode, so it requires \fB\-fwhole\-program\fR to be +enabled. Structures considered \fBcold\fR by this transformation are not +affected (see \fB\-\-param struct\-reorg\-cold\-struct\-ratio=\fR\fIvalue\fR). +.Sp +With this flag, the program debug info reflects a new structure layout. +.IP "\fB\-fipa\-pta\fR" 4 +.IX Item "-fipa-pta" +Perform interprocedural pointer analysis and interprocedural modification +and reference analysis. This option can cause excessive memory and +compile-time usage on large compilation units. It is not enabled by +default at any optimization level. +.IP "\fB\-fipa\-profile\fR" 4 +.IX Item "-fipa-profile" +Perform interprocedural profile propagation. The functions called only from +cold functions are marked as cold. Also functions executed once (such as +\&\f(CW\*(C`cold\*(C'\fR, \f(CW\*(C`noreturn\*(C'\fR, static constructors or destructors) are identified. Cold +functions and loop less parts of functions executed once are then optimized for +size. +Enabled by default at \fB\-O\fR and higher. +.IP "\fB\-fipa\-cp\fR" 4 +.IX Item "-fipa-cp" +Perform interprocedural constant propagation. +This optimization analyzes the program to determine when values passed +to functions are constants and then optimizes accordingly. +This optimization can substantially increase performance +if the application has constants passed to functions. +This flag is enabled by default at \fB\-O2\fR, \fB\-Os\fR and \fB\-O3\fR. +.IP "\fB\-fipa\-cp\-clone\fR" 4 +.IX Item "-fipa-cp-clone" +Perform function cloning to make interprocedural constant propagation stronger. +When enabled, interprocedural constant propagation will perform function cloning +when externally visible function can be called with constant arguments. +Because this optimization can create multiple copies of functions, +it may significantly increase code size +(see \fB\-\-param ipcp\-unit\-growth=\fR\fIvalue\fR). +This flag is enabled by default at \fB\-O3\fR. +.IP "\fB\-fipa\-matrix\-reorg\fR" 4 +.IX Item "-fipa-matrix-reorg" +Perform matrix flattening and transposing. +Matrix flattening tries to replace an m\-dimensional matrix +with its equivalent n\-dimensional matrix, where n < m. +This reduces the level of indirection needed for accessing the elements +of the matrix. The second optimization is matrix transposing that +attempts to change the order of the matrix's dimensions in order to +improve cache locality. +Both optimizations need the \fB\-fwhole\-program\fR flag. +Transposing is enabled only if profiling information is available. +.IP "\fB\-ftree\-sink\fR" 4 +.IX Item "-ftree-sink" +Perform forward store motion on trees. This flag is +enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-bit\-ccp\fR" 4 +.IX Item "-ftree-bit-ccp" +Perform sparse conditional bit constant propagation on trees and propagate +pointer alignment information. +This pass only operates on local scalar variables and is enabled by default +at \fB\-O\fR and higher. It requires that \fB\-ftree\-ccp\fR is enabled. +.IP "\fB\-ftree\-ccp\fR" 4 +.IX Item "-ftree-ccp" +Perform sparse conditional constant propagation (\s-1CCP\s0) on trees. This +pass only operates on local scalar variables and is enabled by default +at \fB\-O\fR and higher. +.IP "\fB\-ftree\-switch\-conversion\fR" 4 +.IX Item "-ftree-switch-conversion" +Perform conversion of simple initializations in a switch to +initializations from a scalar array. This flag is enabled by default +at \fB\-O2\fR and higher. +.IP "\fB\-ftree\-dce\fR" 4 +.IX Item "-ftree-dce" +Perform dead code elimination (\s-1DCE\s0) on trees. This flag is enabled by +default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-builtin\-call\-dce\fR" 4 +.IX Item "-ftree-builtin-call-dce" +Perform conditional dead code elimination (\s-1DCE\s0) for calls to builtin functions +that may set \f(CW\*(C`errno\*(C'\fR but are otherwise side-effect free. This flag is +enabled by default at \fB\-O2\fR and higher if \fB\-Os\fR is not also +specified. +.IP "\fB\-ftree\-dominator\-opts\fR" 4 +.IX Item "-ftree-dominator-opts" +Perform a variety of simple scalar cleanups (constant/copy +propagation, redundancy elimination, range propagation and expression +simplification) based on a dominator tree traversal. This also +performs jump threading (to reduce jumps to jumps). This flag is +enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-dse\fR" 4 +.IX Item "-ftree-dse" +Perform dead store elimination (\s-1DSE\s0) on trees. A dead store is a store into +a memory location which will later be overwritten by another store without +any intervening loads. In this case the earlier store can be deleted. This +flag is enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-ch\fR" 4 +.IX Item "-ftree-ch" +Perform loop header copying on trees. This is beneficial since it increases +effectiveness of code motion optimizations. It also saves one jump. This flag +is enabled by default at \fB\-O\fR and higher. It is not enabled +for \fB\-Os\fR, since it usually increases code size. +.IP "\fB\-ftree\-loop\-optimize\fR" 4 +.IX Item "-ftree-loop-optimize" +Perform loop optimizations on trees. This flag is enabled by default +at \fB\-O\fR and higher. +.IP "\fB\-ftree\-loop\-linear\fR" 4 +.IX Item "-ftree-loop-linear" +Perform loop interchange transformations on tree. Same as +\&\fB\-floop\-interchange\fR. To use this code transformation, \s-1GCC\s0 has +to be configured with \fB\-\-with\-ppl\fR and \fB\-\-with\-cloog\fR to +enable the Graphite loop transformation infrastructure. +.IP "\fB\-floop\-interchange\fR" 4 +.IX Item "-floop-interchange" +Perform loop interchange transformations on loops. Interchanging two +nested loops switches the inner and outer loops. For example, given a +loop like: +.Sp +.Vb 5 +\& DO J = 1, M +\& DO I = 1, N +\& A(J, I) = A(J, I) * C +\& ENDDO +\& ENDDO +.Ve +.Sp +loop interchange will transform the loop as if the user had written: +.Sp +.Vb 5 +\& DO I = 1, N +\& DO J = 1, M +\& A(J, I) = A(J, I) * C +\& ENDDO +\& ENDDO +.Ve +.Sp +which can be beneficial when \f(CW\*(C`N\*(C'\fR is larger than the caches, +because in Fortran, the elements of an array are stored in memory +contiguously by column, and the original loop iterates over rows, +potentially creating at each access a cache miss. This optimization +applies to all the languages supported by \s-1GCC\s0 and is not limited to +Fortran. To use this code transformation, \s-1GCC\s0 has to be configured +with \fB\-\-with\-ppl\fR and \fB\-\-with\-cloog\fR to enable the +Graphite loop transformation infrastructure. +.IP "\fB\-floop\-strip\-mine\fR" 4 +.IX Item "-floop-strip-mine" +Perform loop strip mining transformations on loops. Strip mining +splits a loop into two nested loops. The outer loop has strides +equal to the strip size and the inner loop has strides of the +original loop within a strip. The strip length can be changed +using the \fBloop-block-tile-size\fR parameter. For example, +given a loop like: +.Sp +.Vb 3 +\& DO I = 1, N +\& A(I) = A(I) + C +\& ENDDO +.Ve +.Sp +loop strip mining will transform the loop as if the user had written: +.Sp +.Vb 5 +\& DO II = 1, N, 51 +\& DO I = II, min (II + 50, N) +\& A(I) = A(I) + C +\& ENDDO +\& ENDDO +.Ve +.Sp +This optimization applies to all the languages supported by \s-1GCC\s0 and is +not limited to Fortran. To use this code transformation, \s-1GCC\s0 has to +be configured with \fB\-\-with\-ppl\fR and \fB\-\-with\-cloog\fR to +enable the Graphite loop transformation infrastructure. +.IP "\fB\-floop\-block\fR" 4 +.IX Item "-floop-block" +Perform loop blocking transformations on loops. Blocking strip mines +each loop in the loop nest such that the memory accesses of the +element loops fit inside caches. The strip length can be changed +using the \fBloop-block-tile-size\fR parameter. For example, given +a loop like: +.Sp +.Vb 5 +\& DO I = 1, N +\& DO J = 1, M +\& A(J, I) = B(I) + C(J) +\& ENDDO +\& ENDDO +.Ve +.Sp +loop blocking will transform the loop as if the user had written: +.Sp +.Vb 9 +\& DO II = 1, N, 51 +\& DO JJ = 1, M, 51 +\& DO I = II, min (II + 50, N) +\& DO J = JJ, min (JJ + 50, M) +\& A(J, I) = B(I) + C(J) +\& ENDDO +\& ENDDO +\& ENDDO +\& ENDDO +.Ve +.Sp +which can be beneficial when \f(CW\*(C`M\*(C'\fR is larger than the caches, +because the innermost loop will iterate over a smaller amount of data +that can be kept in the caches. This optimization applies to all the +languages supported by \s-1GCC\s0 and is not limited to Fortran. To use this +code transformation, \s-1GCC\s0 has to be configured with \fB\-\-with\-ppl\fR +and \fB\-\-with\-cloog\fR to enable the Graphite loop transformation +infrastructure. +.IP "\fB\-fgraphite\-identity\fR" 4 +.IX Item "-fgraphite-identity" +Enable the identity transformation for graphite. For every SCoP we generate +the polyhedral representation and transform it back to gimple. Using +\&\fB\-fgraphite\-identity\fR we can check the costs or benefits of the +\&\s-1GIMPLE\s0 \-> \s-1GRAPHITE\s0 \-> \s-1GIMPLE\s0 transformation. Some minimal optimizations +are also performed by the code generator CLooG, like index splitting and +dead code elimination in loops. +.IP "\fB\-floop\-flatten\fR" 4 +.IX Item "-floop-flatten" +Removes the loop nesting structure: transforms the loop nest into a +single loop. This transformation can be useful to vectorize all the +levels of the loop nest. +.IP "\fB\-floop\-parallelize\-all\fR" 4 +.IX Item "-floop-parallelize-all" +Use the Graphite data dependence analysis to identify loops that can +be parallelized. Parallelize all the loops that can be analyzed to +not contain loop carried dependences without checking that it is +profitable to parallelize the loops. +.IP "\fB\-fcheck\-data\-deps\fR" 4 +.IX Item "-fcheck-data-deps" +Compare the results of several data dependence analyzers. This option +is used for debugging the data dependence analyzers. +.IP "\fB\-ftree\-loop\-if\-convert\fR" 4 +.IX Item "-ftree-loop-if-convert" +Attempt to transform conditional jumps in the innermost loops to +branch-less equivalents. The intent is to remove control-flow from +the innermost loops in order to improve the ability of the +vectorization pass to handle these loops. This is enabled by default +if vectorization is enabled. +.IP "\fB\-ftree\-loop\-if\-convert\-stores\fR" 4 +.IX Item "-ftree-loop-if-convert-stores" +Attempt to also if-convert conditional jumps containing memory writes. +This transformation can be unsafe for multi-threaded programs as it +transforms conditional memory writes into unconditional memory writes. +For example, +.Sp +.Vb 3 +\& for (i = 0; i < N; i++) +\& if (cond) +\& A[i] = expr; +.Ve +.Sp +would be transformed to +.Sp +.Vb 2 +\& for (i = 0; i < N; i++) +\& A[i] = cond ? expr : A[i]; +.Ve +.Sp +potentially producing data races. +.IP "\fB\-ftree\-loop\-distribution\fR" 4 +.IX Item "-ftree-loop-distribution" +Perform loop distribution. This flag can improve cache performance on +big loop bodies and allow further loop optimizations, like +parallelization or vectorization, to take place. For example, the loop +.Sp +.Vb 4 +\& DO I = 1, N +\& A(I) = B(I) + C +\& D(I) = E(I) * F +\& ENDDO +.Ve +.Sp +is transformed to +.Sp +.Vb 6 +\& DO I = 1, N +\& A(I) = B(I) + C +\& ENDDO +\& DO I = 1, N +\& D(I) = E(I) * F +\& ENDDO +.Ve +.IP "\fB\-ftree\-loop\-distribute\-patterns\fR" 4 +.IX Item "-ftree-loop-distribute-patterns" +Perform loop distribution of patterns that can be code generated with +calls to a library. This flag is enabled by default at \fB\-O3\fR. +.Sp +This pass distributes the initialization loops and generates a call to +memset zero. For example, the loop +.Sp +.Vb 4 +\& DO I = 1, N +\& A(I) = 0 +\& B(I) = A(I) + I +\& ENDDO +.Ve +.Sp +is transformed to +.Sp +.Vb 6 +\& DO I = 1, N +\& A(I) = 0 +\& ENDDO +\& DO I = 1, N +\& B(I) = A(I) + I +\& ENDDO +.Ve +.Sp +and the initialization loop is transformed into a call to memset zero. +.IP "\fB\-ftree\-loop\-im\fR" 4 +.IX Item "-ftree-loop-im" +Perform loop invariant motion on trees. This pass moves only invariants that +would be hard to handle at \s-1RTL\s0 level (function calls, operations that expand to +nontrivial sequences of insns). With \fB\-funswitch\-loops\fR it also moves +operands of conditions that are invariant out of the loop, so that we can use +just trivial invariantness analysis in loop unswitching. The pass also includes +store motion. +.IP "\fB\-ftree\-loop\-ivcanon\fR" 4 +.IX Item "-ftree-loop-ivcanon" +Create a canonical counter for number of iterations in the loop for that +determining number of iterations requires complicated analysis. Later +optimizations then may determine the number easily. Useful especially +in connection with unrolling. +.IP "\fB\-fivopts\fR" 4 +.IX Item "-fivopts" +Perform induction variable optimizations (strength reduction, induction +variable merging and induction variable elimination) on trees. +.IP "\fB\-ftree\-parallelize\-loops=n\fR" 4 +.IX Item "-ftree-parallelize-loops=n" +Parallelize loops, i.e., split their iteration space to run in n threads. +This is only possible for loops whose iterations are independent +and can be arbitrarily reordered. The optimization is only +profitable on multiprocessor machines, for loops that are CPU-intensive, +rather than constrained e.g. by memory bandwidth. This option +implies \fB\-pthread\fR, and thus is only supported on targets +that have support for \fB\-pthread\fR. +.IP "\fB\-ftree\-pta\fR" 4 +.IX Item "-ftree-pta" +Perform function-local points-to analysis on trees. This flag is +enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-sra\fR" 4 +.IX Item "-ftree-sra" +Perform scalar replacement of aggregates. This pass replaces structure +references with scalars to prevent committing structures to memory too +early. This flag is enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-copyrename\fR" 4 +.IX Item "-ftree-copyrename" +Perform copy renaming on trees. This pass attempts to rename compiler +temporaries to other variables at copy locations, usually resulting in +variable names which more closely resemble the original variables. This flag +is enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-ter\fR" 4 +.IX Item "-ftree-ter" +Perform temporary expression replacement during the \s-1SSA\-\s0>normal phase. Single +use/single def temporaries are replaced at their use location with their +defining expression. This results in non-GIMPLE code, but gives the expanders +much more complex trees to work on resulting in better \s-1RTL\s0 generation. This is +enabled by default at \fB\-O\fR and higher. +.IP "\fB\-ftree\-vectorize\fR" 4 +.IX Item "-ftree-vectorize" +Perform loop vectorization on trees. This flag is enabled by default at +\&\fB\-O3\fR. +.IP "\fB\-ftree\-slp\-vectorize\fR" 4 +.IX Item "-ftree-slp-vectorize" +Perform basic block vectorization on trees. This flag is enabled by default at +\&\fB\-O3\fR and when \fB\-ftree\-vectorize\fR is enabled. +.IP "\fB\-ftree\-vect\-loop\-version\fR" 4 +.IX Item "-ftree-vect-loop-version" +Perform loop versioning when doing loop vectorization on trees. When a loop +appears to be vectorizable except that data alignment or data dependence cannot +be determined at compile time then vectorized and non-vectorized versions of +the loop are generated along with runtime checks for alignment or dependence +to control which version is executed. This option is enabled by default +except at level \fB\-Os\fR where it is disabled. +.IP "\fB\-fvect\-cost\-model\fR" 4 +.IX Item "-fvect-cost-model" +Enable cost model for vectorization. +.IP "\fB\-ftree\-vrp\fR" 4 +.IX Item "-ftree-vrp" +Perform Value Range Propagation on trees. This is similar to the +constant propagation pass, but instead of values, ranges of values are +propagated. This allows the optimizers to remove unnecessary range +checks like array bound checks and null pointer checks. This is +enabled by default at \fB\-O2\fR and higher. Null pointer check +elimination is only done if \fB\-fdelete\-null\-pointer\-checks\fR is +enabled. +.IP "\fB\-ftracer\fR" 4 +.IX Item "-ftracer" +Perform tail duplication to enlarge superblock size. This transformation +simplifies the control flow of the function allowing other optimizations to do +better job. +.IP "\fB\-funroll\-loops\fR" 4 +.IX Item "-funroll-loops" +Unroll loops whose number of iterations can be determined at compile +time or upon entry to the loop. \fB\-funroll\-loops\fR implies +\&\fB\-frerun\-cse\-after\-loop\fR. This option makes code larger, +and may or may not make it run faster. +.IP "\fB\-funroll\-all\-loops\fR" 4 +.IX Item "-funroll-all-loops" +Unroll all loops, even if their number of iterations is uncertain when +the loop is entered. This usually makes programs run more slowly. +\&\fB\-funroll\-all\-loops\fR implies the same options as +\&\fB\-funroll\-loops\fR, +.IP "\fB\-fsplit\-ivs\-in\-unroller\fR" 4 +.IX Item "-fsplit-ivs-in-unroller" +Enables expressing of values of induction variables in later iterations +of the unrolled loop using the value in the first iteration. This breaks +long dependency chains, thus improving efficiency of the scheduling passes. +.Sp +Combination of \fB\-fweb\fR and \s-1CSE\s0 is often sufficient to obtain the +same effect. However in cases the loop body is more complicated than +a single basic block, this is not reliable. It also does not work at all +on some of the architectures due to restrictions in the \s-1CSE\s0 pass. +.Sp +This optimization is enabled by default. +.IP "\fB\-fvariable\-expansion\-in\-unroller\fR" 4 +.IX Item "-fvariable-expansion-in-unroller" +With this option, the compiler will create multiple copies of some +local variables when unrolling a loop which can result in superior code. +.IP "\fB\-fpartial\-inlining\fR" 4 +.IX Item "-fpartial-inlining" +Inline parts of functions. This option has any effect only +when inlining itself is turned on by the \fB\-finline\-functions\fR +or \fB\-finline\-small\-functions\fR options. +.Sp +Enabled at level \fB\-O2\fR. +.IP "\fB\-fpredictive\-commoning\fR" 4 +.IX Item "-fpredictive-commoning" +Perform predictive commoning optimization, i.e., reusing computations +(especially memory loads and stores) performed in previous +iterations of loops. +.Sp +This option is enabled at level \fB\-O3\fR. +.IP "\fB\-fprefetch\-loop\-arrays\fR" 4 +.IX Item "-fprefetch-loop-arrays" +If supported by the target machine, generate instructions to prefetch +memory to improve the performance of loops that access large arrays. +.Sp +This option may generate better or worse code; results are highly +dependent on the structure of loops within the source code. +.Sp +Disabled at level \fB\-Os\fR. +.IP "\fB\-fno\-peephole\fR" 4 +.IX Item "-fno-peephole" +.PD 0 +.IP "\fB\-fno\-peephole2\fR" 4 +.IX Item "-fno-peephole2" +.PD +Disable any machine-specific peephole optimizations. The difference +between \fB\-fno\-peephole\fR and \fB\-fno\-peephole2\fR is in how they +are implemented in the compiler; some targets use one, some use the +other, a few use both. +.Sp +\&\fB\-fpeephole\fR is enabled by default. +\&\fB\-fpeephole2\fR enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fno\-guess\-branch\-probability\fR" 4 +.IX Item "-fno-guess-branch-probability" +Do not guess branch probabilities using heuristics. +.Sp +\&\s-1GCC\s0 will use heuristics to guess branch probabilities if they are +not provided by profiling feedback (\fB\-fprofile\-arcs\fR). These +heuristics are based on the control flow graph. If some branch probabilities +are specified by \fB_\|_builtin_expect\fR, then the heuristics will be +used to guess branch probabilities for the rest of the control flow graph, +taking the \fB_\|_builtin_expect\fR info into account. The interactions +between the heuristics and \fB_\|_builtin_expect\fR can be complex, and in +some cases, it may be useful to disable the heuristics so that the effects +of \fB_\|_builtin_expect\fR are easier to understand. +.Sp +The default is \fB\-fguess\-branch\-probability\fR at levels +\&\fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-freorder\-blocks\fR" 4 +.IX Item "-freorder-blocks" +Reorder basic blocks in the compiled function in order to reduce number of +taken branches and improve code locality. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-freorder\-blocks\-and\-partition\fR" 4 +.IX Item "-freorder-blocks-and-partition" +In addition to reordering basic blocks in the compiled function, in order +to reduce number of taken branches, partitions hot and cold basic blocks +into separate sections of the assembly and .o files, to improve +paging and cache locality performance. +.Sp +This optimization is automatically turned off in the presence of +exception handling, for linkonce sections, for functions with a user-defined +section attribute and on any architecture that does not support named +sections. +.IP "\fB\-freorder\-functions\fR" 4 +.IX Item "-freorder-functions" +Reorder functions in the object file in order to +improve code locality. This is implemented by using special +subsections \f(CW\*(C`.text.hot\*(C'\fR for most frequently executed functions and +\&\f(CW\*(C`.text.unlikely\*(C'\fR for unlikely executed functions. Reordering is done by +the linker so object file format must support named sections and linker must +place them in a reasonable way. +.Sp +Also profile feedback must be available in to make this option effective. See +\&\fB\-fprofile\-arcs\fR for details. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fstrict\-aliasing\fR" 4 +.IX Item "-fstrict-aliasing" +Allow the compiler to assume the strictest aliasing rules applicable to +the language being compiled. For C (and \*(C+), this activates +optimizations based on the type of expressions. In particular, an +object of one type is assumed never to reside at the same address as an +object of a different type, unless the types are almost the same. For +example, an \f(CW\*(C`unsigned int\*(C'\fR can alias an \f(CW\*(C`int\*(C'\fR, but not a +\&\f(CW\*(C`void*\*(C'\fR or a \f(CW\*(C`double\*(C'\fR. A character type may alias any other +type. +.Sp +Pay special attention to code like this: +.Sp +.Vb 4 +\& union a_union { +\& int i; +\& double d; +\& }; +\& +\& int f() { +\& union a_union t; +\& t.d = 3.0; +\& return t.i; +\& } +.Ve +.Sp +The practice of reading from a different union member than the one most +recently written to (called \*(L"type-punning\*(R") is common. Even with +\&\fB\-fstrict\-aliasing\fR, type-punning is allowed, provided the memory +is accessed through the union type. So, the code above will work as +expected. However, this code might not: +.Sp +.Vb 7 +\& int f() { +\& union a_union t; +\& int* ip; +\& t.d = 3.0; +\& ip = &t.i; +\& return *ip; +\& } +.Ve +.Sp +Similarly, access by taking the address, casting the resulting pointer +and dereferencing the result has undefined behavior, even if the cast +uses a union type, e.g.: +.Sp +.Vb 4 +\& int f() { +\& double d = 3.0; +\& return ((union a_union *) &d)\->i; +\& } +.Ve +.Sp +The \fB\-fstrict\-aliasing\fR option is enabled at levels +\&\fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fstrict\-overflow\fR" 4 +.IX Item "-fstrict-overflow" +Allow the compiler to assume strict signed overflow rules, depending +on the language being compiled. For C (and \*(C+) this means that +overflow when doing arithmetic with signed numbers is undefined, which +means that the compiler may assume that it will not happen. This +permits various optimizations. For example, the compiler will assume +that an expression like \f(CW\*(C`i + 10 > i\*(C'\fR will always be true for +signed \f(CW\*(C`i\*(C'\fR. This assumption is only valid if signed overflow is +undefined, as the expression is false if \f(CW\*(C`i + 10\*(C'\fR overflows when +using twos complement arithmetic. When this option is in effect any +attempt to determine whether an operation on signed numbers will +overflow must be written carefully to not actually involve overflow. +.Sp +This option also allows the compiler to assume strict pointer +semantics: given a pointer to an object, if adding an offset to that +pointer does not produce a pointer to the same object, the addition is +undefined. This permits the compiler to conclude that \f(CW\*(C`p + u > +p\*(C'\fR is always true for a pointer \f(CW\*(C`p\*(C'\fR and unsigned integer +\&\f(CW\*(C`u\*(C'\fR. This assumption is only valid because pointer wraparound is +undefined, as the expression is false if \f(CW\*(C`p + u\*(C'\fR overflows using +twos complement arithmetic. +.Sp +See also the \fB\-fwrapv\fR option. Using \fB\-fwrapv\fR means +that integer signed overflow is fully defined: it wraps. When +\&\fB\-fwrapv\fR is used, there is no difference between +\&\fB\-fstrict\-overflow\fR and \fB\-fno\-strict\-overflow\fR for +integers. With \fB\-fwrapv\fR certain types of overflow are +permitted. For example, if the compiler gets an overflow when doing +arithmetic on constants, the overflowed value can still be used with +\&\fB\-fwrapv\fR, but not otherwise. +.Sp +The \fB\-fstrict\-overflow\fR option is enabled at levels +\&\fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-falign\-functions\fR" 4 +.IX Item "-falign-functions" +.PD 0 +.IP "\fB\-falign\-functions=\fR\fIn\fR" 4 +.IX Item "-falign-functions=n" +.PD +Align the start of functions to the next power-of-two greater than +\&\fIn\fR, skipping up to \fIn\fR bytes. For instance, +\&\fB\-falign\-functions=32\fR aligns functions to the next 32\-byte +boundary, but \fB\-falign\-functions=24\fR would align to the next +32\-byte boundary only if this can be done by skipping 23 bytes or less. +.Sp +\&\fB\-fno\-align\-functions\fR and \fB\-falign\-functions=1\fR are +equivalent and mean that functions will not be aligned. +.Sp +Some assemblers only support this flag when \fIn\fR is a power of two; +in that case, it is rounded up. +.Sp +If \fIn\fR is not specified or is zero, use a machine-dependent default. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-falign\-labels\fR" 4 +.IX Item "-falign-labels" +.PD 0 +.IP "\fB\-falign\-labels=\fR\fIn\fR" 4 +.IX Item "-falign-labels=n" +.PD +Align all branch targets to a power-of-two boundary, skipping up to +\&\fIn\fR bytes like \fB\-falign\-functions\fR. This option can easily +make code slower, because it must insert dummy operations for when the +branch target is reached in the usual flow of the code. +.Sp +\&\fB\-fno\-align\-labels\fR and \fB\-falign\-labels=1\fR are +equivalent and mean that labels will not be aligned. +.Sp +If \fB\-falign\-loops\fR or \fB\-falign\-jumps\fR are applicable and +are greater than this value, then their values are used instead. +.Sp +If \fIn\fR is not specified or is zero, use a machine-dependent default +which is very likely to be \fB1\fR, meaning no alignment. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-falign\-loops\fR" 4 +.IX Item "-falign-loops" +.PD 0 +.IP "\fB\-falign\-loops=\fR\fIn\fR" 4 +.IX Item "-falign-loops=n" +.PD +Align loops to a power-of-two boundary, skipping up to \fIn\fR bytes +like \fB\-falign\-functions\fR. The hope is that the loop will be +executed many times, which will make up for any execution of the dummy +operations. +.Sp +\&\fB\-fno\-align\-loops\fR and \fB\-falign\-loops=1\fR are +equivalent and mean that loops will not be aligned. +.Sp +If \fIn\fR is not specified or is zero, use a machine-dependent default. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-falign\-jumps\fR" 4 +.IX Item "-falign-jumps" +.PD 0 +.IP "\fB\-falign\-jumps=\fR\fIn\fR" 4 +.IX Item "-falign-jumps=n" +.PD +Align branch targets to a power-of-two boundary, for branch targets +where the targets can only be reached by jumping, skipping up to \fIn\fR +bytes like \fB\-falign\-functions\fR. In this case, no dummy operations +need be executed. +.Sp +\&\fB\-fno\-align\-jumps\fR and \fB\-falign\-jumps=1\fR are +equivalent and mean that loops will not be aligned. +.Sp +If \fIn\fR is not specified or is zero, use a machine-dependent default. +.Sp +Enabled at levels \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-funit\-at\-a\-time\fR" 4 +.IX Item "-funit-at-a-time" +This option is left for compatibility reasons. \fB\-funit\-at\-a\-time\fR +has no effect, while \fB\-fno\-unit\-at\-a\-time\fR implies +\&\fB\-fno\-toplevel\-reorder\fR and \fB\-fno\-section\-anchors\fR. +.Sp +Enabled by default. +.IP "\fB\-fno\-toplevel\-reorder\fR" 4 +.IX Item "-fno-toplevel-reorder" +Do not reorder top-level functions, variables, and \f(CW\*(C`asm\*(C'\fR +statements. Output them in the same order that they appear in the +input file. When this option is used, unreferenced static variables +will not be removed. This option is intended to support existing code +which relies on a particular ordering. For new code, it is better to +use attributes. +.Sp +Enabled at level \fB\-O0\fR. When disabled explicitly, it also imply +\&\fB\-fno\-section\-anchors\fR that is otherwise enabled at \fB\-O0\fR on some +targets. +.IP "\fB\-fweb\fR" 4 +.IX Item "-fweb" +Constructs webs as commonly used for register allocation purposes and assign +each web individual pseudo register. This allows the register allocation pass +to operate on pseudos directly, but also strengthens several other optimization +passes, such as \s-1CSE\s0, loop optimizer and trivial dead code remover. It can, +however, make debugging impossible, since variables will no longer stay in a +\&\*(L"home register\*(R". +.Sp +Enabled by default with \fB\-funroll\-loops\fR. +.IP "\fB\-fwhole\-program\fR" 4 +.IX Item "-fwhole-program" +Assume that the current compilation unit represents the whole program being +compiled. All public functions and variables with the exception of \f(CW\*(C`main\*(C'\fR +and those merged by attribute \f(CW\*(C`externally_visible\*(C'\fR become static functions +and in effect are optimized more aggressively by interprocedural optimizers. If \fBgold\fR is used as the linker plugin, \f(CW\*(C`externally_visible\*(C'\fR attributes are automatically added to functions (not variable yet due to a current \fBgold\fR issue) that are accessed outside of \s-1LTO\s0 objects according to resolution file produced by \fBgold\fR. For other linkers that cannot generate resolution file, explicit \f(CW\*(C`externally_visible\*(C'\fR attributes are still necessary. +While this option is equivalent to proper use of the \f(CW\*(C`static\*(C'\fR keyword for +programs consisting of a single file, in combination with option +\&\fB\-flto\fR this flag can be used to +compile many smaller scale programs since the functions and variables become +local for the whole combined compilation unit, not for the single source file +itself. +.Sp +This option implies \fB\-fwhole\-file\fR for Fortran programs. +.IP "\fB\-flto[=\fR\fIn\fR\fB]\fR" 4 +.IX Item "-flto[=n]" +This option runs the standard link-time optimizer. When invoked +with source code, it generates \s-1GIMPLE\s0 (one of \s-1GCC\s0's internal +representations) and writes it to special \s-1ELF\s0 sections in the object +file. When the object files are linked together, all the function +bodies are read from these \s-1ELF\s0 sections and instantiated as if they +had been part of the same translation unit. +.Sp +To use the link-time optimizer, \fB\-flto\fR needs to be specified at +compile time and during the final link. For example: +.Sp +.Vb 3 +\& gcc \-c \-O2 \-flto foo.c +\& gcc \-c \-O2 \-flto bar.c +\& gcc \-o myprog \-flto \-O2 foo.o bar.o +.Ve +.Sp +The first two invocations to \s-1GCC\s0 save a bytecode representation +of \s-1GIMPLE\s0 into special \s-1ELF\s0 sections inside \fIfoo.o\fR and +\&\fIbar.o\fR. The final invocation reads the \s-1GIMPLE\s0 bytecode from +\&\fIfoo.o\fR and \fIbar.o\fR, merges the two files into a single +internal image, and compiles the result as usual. Since both +\&\fIfoo.o\fR and \fIbar.o\fR are merged into a single image, this +causes all the interprocedural analyses and optimizations in \s-1GCC\s0 to +work across the two files as if they were a single one. This means, +for example, that the inliner is able to inline functions in +\&\fIbar.o\fR into functions in \fIfoo.o\fR and vice-versa. +.Sp +Another (simpler) way to enable link-time optimization is: +.Sp +.Vb 1 +\& gcc \-o myprog \-flto \-O2 foo.c bar.c +.Ve +.Sp +The above generates bytecode for \fIfoo.c\fR and \fIbar.c\fR, +merges them together into a single \s-1GIMPLE\s0 representation and optimizes +them as usual to produce \fImyprog\fR. +.Sp +The only important thing to keep in mind is that to enable link-time +optimizations the \fB\-flto\fR flag needs to be passed to both the +compile and the link commands. +.Sp +To make whole program optimization effective, it is necessary to make +certain whole program assumptions. The compiler needs to know +what functions and variables can be accessed by libraries and runtime +outside of the link-time optimized unit. When supported by the linker, +the linker plugin (see \fB\-fuse\-linker\-plugin\fR) passes information +to the compiler about used and externally visible symbols. When +the linker plugin is not available, \fB\-fwhole\-program\fR should be +used to allow the compiler to make these assumptions, which leads +to more aggressive optimization decisions. +.Sp +Note that when a file is compiled with \fB\-flto\fR, the generated +object file is larger than a regular object file because it +contains \s-1GIMPLE\s0 bytecodes and the usual final code. This means that +object files with \s-1LTO\s0 information can be linked as normal object +files; if \fB\-flto\fR is not passed to the linker, no +interprocedural optimizations are applied. +.Sp +Additionally, the optimization flags used to compile individual files +are not necessarily related to those used at link time. For instance, +.Sp +.Vb 3 +\& gcc \-c \-O0 \-flto foo.c +\& gcc \-c \-O0 \-flto bar.c +\& gcc \-o myprog \-flto \-O3 foo.o bar.o +.Ve +.Sp +This produces individual object files with unoptimized assembler +code, but the resulting binary \fImyprog\fR is optimized at +\&\fB\-O3\fR. If, instead, the final binary is generated without +\&\fB\-flto\fR, then \fImyprog\fR is not optimized. +.Sp +When producing the final binary with \fB\-flto\fR, \s-1GCC\s0 only +applies link-time optimizations to those files that contain bytecode. +Therefore, you can mix and match object files and libraries with +\&\s-1GIMPLE\s0 bytecodes and final object code. \s-1GCC\s0 automatically selects +which files to optimize in \s-1LTO\s0 mode and which files to link without +further processing. +.Sp +There are some code generation flags that \s-1GCC\s0 preserves when +generating bytecodes, as they need to be used during the final link +stage. Currently, the following options are saved into the \s-1GIMPLE\s0 +bytecode files: \fB\-fPIC\fR, \fB\-fcommon\fR and all the +\&\fB\-m\fR target flags. +.Sp +At link time, these options are read in and reapplied. Note that the +current implementation makes no attempt to recognize conflicting +values for these options. If different files have conflicting option +values (e.g., one file is compiled with \fB\-fPIC\fR and another +isn't), the compiler simply uses the last value read from the +bytecode files. It is recommended, then, that you compile all the files +participating in the same link with the same options. +.Sp +If \s-1LTO\s0 encounters objects with C linkage declared with incompatible +types in separate translation units to be linked together (undefined +behavior according to \s-1ISO\s0 C99 6.2.7), a non-fatal diagnostic may be +issued. The behavior is still undefined at runtime. +.Sp +Another feature of \s-1LTO\s0 is that it is possible to apply interprocedural +optimizations on files written in different languages. This requires +support in the language front end. Currently, the C, \*(C+ and +Fortran front ends are capable of emitting \s-1GIMPLE\s0 bytecodes, so +something like this should work: +.Sp +.Vb 4 +\& gcc \-c \-flto foo.c +\& g++ \-c \-flto bar.cc +\& gfortran \-c \-flto baz.f90 +\& g++ \-o myprog \-flto \-O3 foo.o bar.o baz.o \-lgfortran +.Ve +.Sp +Notice that the final link is done with \fBg++\fR to get the \*(C+ +runtime libraries and \fB\-lgfortran\fR is added to get the Fortran +runtime libraries. In general, when mixing languages in \s-1LTO\s0 mode, you +should use the same link command options as when mixing languages in a +regular (non-LTO) compilation; all you need to add is \fB\-flto\fR to +all the compile and link commands. +.Sp +If object files containing \s-1GIMPLE\s0 bytecode are stored in a library archive, say +\&\fIlibfoo.a\fR, it is possible to extract and use them in an \s-1LTO\s0 link if you +are using a linker with plugin support. To enable this feature, use +the flag \fB\-fuse\-linker\-plugin\fR at link time: +.Sp +.Vb 1 +\& gcc \-o myprog \-O2 \-flto \-fuse\-linker\-plugin a.o b.o \-lfoo +.Ve +.Sp +With the linker plugin enabled, the linker extracts the needed +\&\s-1GIMPLE\s0 files from \fIlibfoo.a\fR and passes them on to the running \s-1GCC\s0 +to make them part of the aggregated \s-1GIMPLE\s0 image to be optimized. +.Sp +If you are not using a linker with plugin support and/or do not +enable the linker plugin, then the objects inside \fIlibfoo.a\fR +are extracted and linked as usual, but they do not participate +in the \s-1LTO\s0 optimization process. +.Sp +Link-time optimizations do not require the presence of the whole program to +operate. If the program does not require any symbols to be exported, it is +possible to combine \fB\-flto\fR and \fB\-fwhole\-program\fR to allow +the interprocedural optimizers to use more aggressive assumptions which may +lead to improved optimization opportunities. +Use of \fB\-fwhole\-program\fR is not needed when linker plugin is +active (see \fB\-fuse\-linker\-plugin\fR). +.Sp +The current implementation of \s-1LTO\s0 makes no +attempt to generate bytecode that is portable between different +types of hosts. The bytecode files are versioned and there is a +strict version check, so bytecode files generated in one version of +\&\s-1GCC\s0 will not work with an older/newer version of \s-1GCC\s0. +.Sp +Link-time optimization does not work well with generation of debugging +information. Combining \fB\-flto\fR with +\&\fB\-g\fR is currently experimental and expected to produce wrong +results. +.Sp +If you specify the optional \fIn\fR, the optimization and code +generation done at link time is executed in parallel using \fIn\fR +parallel jobs by utilizing an installed \fBmake\fR program. The +environment variable \fB\s-1MAKE\s0\fR may be used to override the program +used. The default value for \fIn\fR is 1. +.Sp +You can also specify \fB\-flto=jobserver\fR to use \s-1GNU\s0 make's +job server mode to determine the number of parallel jobs. This +is useful when the Makefile calling \s-1GCC\s0 is already executing in parallel. +You must prepend a \fB+\fR to the command recipe in the parent Makefile +for this to work. This option likely only works if \fB\s-1MAKE\s0\fR is +\&\s-1GNU\s0 make. +.Sp +This option is disabled by default. +.IP "\fB\-flto\-partition=\fR\fIalg\fR" 4 +.IX Item "-flto-partition=alg" +Specify the partitioning algorithm used by the link-time optimizer. +The value is either \f(CW\*(C`1to1\*(C'\fR to specify a partitioning mirroring +the original source files or \f(CW\*(C`balanced\*(C'\fR to specify partitioning +into equally sized chunks (whenever possible). Specifying \f(CW\*(C`none\*(C'\fR +as an algorithm disables partitioning and streaming completely. The +default value is \f(CW\*(C`balanced\*(C'\fR. +.IP "\fB\-flto\-compression\-level=\fR\fIn\fR" 4 +.IX Item "-flto-compression-level=n" +This option specifies the level of compression used for intermediate +language written to \s-1LTO\s0 object files, and is only meaningful in +conjunction with \s-1LTO\s0 mode (\fB\-flto\fR). Valid +values are 0 (no compression) to 9 (maximum compression). Values +outside this range are clamped to either 0 or 9. If the option is not +given, a default balanced compression setting is used. +.IP "\fB\-flto\-report\fR" 4 +.IX Item "-flto-report" +Prints a report with internal details on the workings of the link-time +optimizer. The contents of this report vary from version to version. +It is meant to be useful to \s-1GCC\s0 developers when processing object +files in \s-1LTO\s0 mode (via \fB\-flto\fR). +.Sp +Disabled by default. +.IP "\fB\-fuse\-linker\-plugin\fR" 4 +.IX Item "-fuse-linker-plugin" +Enables the use of a linker plugin during link-time optimization. This +option relies on the linker plugin support in linker that is available in gold +or in \s-1GNU\s0 ld 2.21 or newer. +.Sp +This option enables the extraction of object files with \s-1GIMPLE\s0 bytecode out +of library archives. This improves the quality of optimization by exposing +more code to the link-time optimizer. This information specifies what +symbols can be accessed externally (by non-LTO object or during dynamic +linking). Resulting code quality improvements on binaries (and shared +libraries that use hidden visibility) are similar to \f(CW\*(C`\-fwhole\-program\*(C'\fR. +See \fB\-flto\fR for a description of the effect of this flag and how to +use it. +.Sp +This option is enabled by default when \s-1LTO\s0 support in \s-1GCC\s0 is enabled +and \s-1GCC\s0 was configured for use with +a linker supporting plugins (\s-1GNU\s0 ld 2.21 or newer or gold). +.IP "\fB\-fcompare\-elim\fR" 4 +.IX Item "-fcompare-elim" +After register allocation and post-register allocation instruction splitting, +identify arithmetic instructions that compute processor flags similar to a +comparison operation based on that arithmetic. If possible, eliminate the +explicit comparison operation. +.Sp +This pass only applies to certain targets that cannot explicitly represent +the comparison operation before register allocation is complete. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fuse\-ld=gold\fR" 4 +.IX Item "-fuse-ld=gold" +Use the \fBgold\fR linker instead of the default linker. +This option is only necessary if \s-1GCC\s0 has been configured with +\&\fB\-\-enable\-gold\fR and \fB\-\-enable\-ld=default\fR. +.IP "\fB\-fuse\-ld=bfd\fR" 4 +.IX Item "-fuse-ld=bfd" +Use the \fBld.bfd\fR linker instead of the default linker. +This option is only necessary if \s-1GCC\s0 has been configured with +\&\fB\-\-enable\-gold\fR and \fB\-\-enable\-ld\fR. +.IP "\fB\-fcprop\-registers\fR" 4 +.IX Item "-fcprop-registers" +After register allocation and post-register allocation instruction splitting, +we perform a copy-propagation pass to try to reduce scheduling dependencies +and occasionally eliminate the copy. +.Sp +Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fprofile\-correction\fR" 4 +.IX Item "-fprofile-correction" +Profiles collected using an instrumented binary for multi-threaded programs may +be inconsistent due to missed counter updates. When this option is specified, +\&\s-1GCC\s0 will use heuristics to correct or smooth out such inconsistencies. By +default, \s-1GCC\s0 will emit an error message when an inconsistent profile is detected. +.IP "\fB\-fprofile\-dir=\fR\fIpath\fR" 4 +.IX Item "-fprofile-dir=path" +Set the directory to search for the profile data files in to \fIpath\fR. +This option affects only the profile data generated by +\&\fB\-fprofile\-generate\fR, \fB\-ftest\-coverage\fR, \fB\-fprofile\-arcs\fR +and used by \fB\-fprofile\-use\fR and \fB\-fbranch\-probabilities\fR +and its related options. Both absolute and relative paths can be used. +By default, \s-1GCC\s0 will use the current directory as \fIpath\fR, thus the +profile data file will appear in the same directory as the object file. +.IP "\fB\-fprofile\-generate\fR" 4 +.IX Item "-fprofile-generate" +.PD 0 +.IP "\fB\-fprofile\-generate=\fR\fIpath\fR" 4 +.IX Item "-fprofile-generate=path" +.PD +Enable options usually used for instrumenting application to produce +profile useful for later recompilation with profile feedback based +optimization. You must use \fB\-fprofile\-generate\fR both when +compiling and when linking your program. +.Sp +The following options are enabled: \f(CW\*(C`\-fprofile\-arcs\*(C'\fR, \f(CW\*(C`\-fprofile\-values\*(C'\fR, \f(CW\*(C`\-fvpt\*(C'\fR. +.Sp +If \fIpath\fR is specified, \s-1GCC\s0 will look at the \fIpath\fR to find +the profile feedback data files. See \fB\-fprofile\-dir\fR. +.IP "\fB\-fprofile\-generate\-sampling\fR" 4 +.IX Item "-fprofile-generate-sampling" +Enable sampling for instrumented binaries. Instead of recording every event, +record only every N\-th event, where N (the sampling rate) can be set either +at compile time using +\&\fB\-\-param profile\-generate\-sampling\-rate=\fR\fIvalue\fR, or +at execution start time through environment variable \fB\s-1GCOV_SAMPLING_RATE\s0\fR. +.Sp +At this time sampling applies only to branch counters. A sampling rate of 100 +decreases instrumentated binary slowdown from up to 20x for heavily threaded +applications down to around 2x. \fB\-fprofile\-correction\fR is always +needed with sampling. +.IP "\fB\-fprofile\-use\fR" 4 +.IX Item "-fprofile-use" +.PD 0 +.IP "\fB\-fprofile\-use=\fR\fIpath\fR" 4 +.IX Item "-fprofile-use=path" +.PD +Enable profile feedback directed optimizations, and optimizations +generally profitable only with profile feedback available. +.Sp +The following options are enabled: \f(CW\*(C`\-fbranch\-probabilities\*(C'\fR, \f(CW\*(C`\-fvpt\*(C'\fR, +\&\f(CW\*(C`\-funroll\-loops\*(C'\fR, \f(CW\*(C`\-fpeel\-loops\*(C'\fR. +.Sp +By default, \s-1GCC\s0 emits an error message if the feedback profiles do not +match the source code. This error can be turned into a warning by using +\&\fB\-Wcoverage\-mismatch\fR. Note this may result in poorly optimized +code. +.Sp +If \fIpath\fR is specified, \s-1GCC\s0 will look at the \fIpath\fR to find +the profile feedback data files. See \fB\-fprofile\-dir\fR. +.IP "\fB\-fpmu\-profile\-generate=\fR\fIpmuoption\fR" 4 +.IX Item "-fpmu-profile-generate=pmuoption" +Enable performance monitoring unit (\s-1PMU\s0) profiling. This collects +hardware counter data corresponding to \fIpmuoption\fR. Currently +only \fIload-latency\fR and \fIbranch-mispredict\fR are supported +using pfmon tool. You must use \fB\-fpmu\-profile\-generate\fR both +when compiling and when linking your program. This \s-1PMU\s0 profile data +may later be used by the compiler during optimizations as well can be +displayed using coverage tool gcov. The params variable +\&\*(L"pmu_profile_n_addresses\*(R" can be used to restrict \s-1PMU\s0 data collection +to only this many addresses. +.IP "\fB\-fpmu\-profile\-use=\fR\fIpmuoption\fR" 4 +.IX Item "-fpmu-profile-use=pmuoption" +Enable performance monitoring unit (\s-1PMU\s0) profiling based +optimizations. Currently only \fIload-latency\fR and +\&\fIbranch-mispredict\fR are supported. +.IP "\fB\-fripa\fR" 4 +.IX Item "-fripa" +Perform dynamic inter-procedural analysis. This is used in conjunction with +the \fB\-fprofile\-generate\fR and \fB\-fprofile\-use\fR options. +During the \fB\-fprofile\-generate\fR phase, this flag turns on some additional +instrumentation code that enables dynamic call-graph analysis. +During the \fB\-fprofile\-use\fR phase, this flag enables cross-module +optimizations such as inlining. +.IP "\fB\-fripa\-disallow\-asm\-modules\fR" 4 +.IX Item "-fripa-disallow-asm-modules" +During profile-gen, if this flag is enabled, and the module has asm statements, +arrange so that a bit recording this information will be set in the profile +feedback data file. +During profile-use, if this flag is enabled, and the same bit in auxiliary +module's profile feedback data is set, don't import this auxiliary module. +If this is the primary module, don't export it. +.IP "\fB\-fripa\-disallow\-opt\-mismatch\fR" 4 +.IX Item "-fripa-disallow-opt-mismatch" +Don't import an auxiliary module, if the \s-1GCC\s0 command line options used for this +auxiliary module during the profile-generate stage were different from those used +for the primary module. Note that any mismatches in warning-related options are +ignored for this comparison. +.IP "\fB\-fripa\-no\-promote\-always\-inline\-func\fR" 4 +.IX Item "-fripa-no-promote-always-inline-func" +Do not promote static functions with always inline attribute in \s-1LIPO\s0 compilation. +.IP "\fB\-fripa\-verbose\fR" 4 +.IX Item "-fripa-verbose" +Enable printing of verbose information about dynamic inter-procedural optimizations. +This is used in conjunction with the \fB\-fripa\fR. +.IP "\fB\-fripa\-peel\-size\-limit\fR" 4 +.IX Item "-fripa-peel-size-limit" +Limit loop peeling of non-const non-FP loops in a \s-1LIPO\s0 compilation under estimates +of a large code footprint. Enabled by default under \fB\-fripa\fR. Code size +estimation and thresholds are controlled by the \fBcodesize-hotness-threshold\fR +and \fBunrollpeel-codesize-threshold\fR parameters. +.IP "\fB\-fripa\-unroll\-size\-limit\fR" 4 +.IX Item "-fripa-unroll-size-limit" +Limit loop unrolling of non-const non-FP loops in a \s-1LIPO\s0 compilation under estimates +of a large code footprint. Enabled by default under \fB\-fripa\fR. Code size +estimation and thresholds are controlled by the \fBcodesize-hotness-threshold\fR +and \fBunrollpeel-codesize-threshold\fR parameters. +.IP "\fB\-fcallgraph\-profiles\-sections\fR" 4 +.IX Item "-fcallgraph-profiles-sections" +Emit call graph edge profile counts in .note.callgraph.text sections. This is +used in conjunction with \fB\-fprofile\-use\fR. A new .note.callgraph.text +section is created for each function. This section lists every callee and the +number of times it is called. The params variable +\&\*(L"note-cgraph-section-edge-threshold\*(R" can be used to only list edges above a +certain threshold. +.IP "\fB\-frecord\-gcc\-switches\-in\-elf\fR" 4 +.IX Item "-frecord-gcc-switches-in-elf" +Record the command line options in the .gnu.switches.text elf section for sample +based \s-1LIPO\s0 to do module grouping. +.PP +The following options control compiler behavior regarding floating +point arithmetic. These options trade off between speed and +correctness. All must be specifically enabled. +.IP "\fB\-ffloat\-store\fR" 4 +.IX Item "-ffloat-store" +Do not store floating point variables in registers, and inhibit other +options that might change whether a floating point value is taken from a +register or memory. +.Sp +This option prevents undesirable excess precision on machines such as +the 68000 where the floating registers (of the 68881) keep more +precision than a \f(CW\*(C`double\*(C'\fR is supposed to have. Similarly for the +x86 architecture. For most programs, the excess precision does only +good, but a few programs rely on the precise definition of \s-1IEEE\s0 floating +point. Use \fB\-ffloat\-store\fR for such programs, after modifying +them to store all pertinent intermediate computations into variables. +.IP "\fB\-fexcess\-precision=\fR\fIstyle\fR" 4 +.IX Item "-fexcess-precision=style" +This option allows further control over excess precision on machines +where floating-point registers have more precision than the \s-1IEEE\s0 +\&\f(CW\*(C`float\*(C'\fR and \f(CW\*(C`double\*(C'\fR types and the processor does not +support operations rounding to those types. By default, +\&\fB\-fexcess\-precision=fast\fR is in effect; this means that +operations are carried out in the precision of the registers and that +it is unpredictable when rounding to the types specified in the source +code takes place. When compiling C, if +\&\fB\-fexcess\-precision=standard\fR is specified then excess +precision will follow the rules specified in \s-1ISO\s0 C99; in particular, +both casts and assignments cause values to be rounded to their +semantic types (whereas \fB\-ffloat\-store\fR only affects +assignments). This option is enabled by default for C if a strict +conformance option such as \fB\-std=c99\fR is used. +.Sp +\&\fB\-fexcess\-precision=standard\fR is not implemented for languages +other than C, and has no effect if +\&\fB\-funsafe\-math\-optimizations\fR or \fB\-ffast\-math\fR is +specified. On the x86, it also has no effect if \fB\-mfpmath=sse\fR +or \fB\-mfpmath=sse+387\fR is specified; in the former case, \s-1IEEE\s0 +semantics apply without excess precision, and in the latter, rounding +is unpredictable. +.IP "\fB\-ffast\-math\fR" 4 +.IX Item "-ffast-math" +Sets \fB\-fno\-math\-errno\fR, \fB\-funsafe\-math\-optimizations\fR, +\&\fB\-ffinite\-math\-only\fR, \fB\-fno\-rounding\-math\fR, +\&\fB\-fno\-signaling\-nans\fR and \fB\-fcx\-limited\-range\fR. +.Sp +This option causes the preprocessor macro \f(CW\*(C`_\|_FAST_MATH_\|_\*(C'\fR to be defined. +.Sp +This option is not turned on by any \fB\-O\fR option besides +\&\fB\-Ofast\fR since it can result in incorrect output for programs +which depend on an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications +for math functions. It may, however, yield faster code for programs +that do not require the guarantees of these specifications. +.IP "\fB\-fno\-math\-errno\fR" 4 +.IX Item "-fno-math-errno" +Do not set \s-1ERRNO\s0 after calling math functions that are executed +with a single instruction, e.g., sqrt. A program that relies on +\&\s-1IEEE\s0 exceptions for math error handling may want to use this flag +for speed while maintaining \s-1IEEE\s0 arithmetic compatibility. +.Sp +This option is not turned on by any \fB\-O\fR option since +it can result in incorrect output for programs which depend on +an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for +math functions. It may, however, yield faster code for programs +that do not require the guarantees of these specifications. +.Sp +The default is \fB\-fmath\-errno\fR. +.Sp +On Darwin systems, the math library never sets \f(CW\*(C`errno\*(C'\fR. There is +therefore no reason for the compiler to consider the possibility that +it might, and \fB\-fno\-math\-errno\fR is the default. +.IP "\fB\-funsafe\-math\-optimizations\fR" 4 +.IX Item "-funsafe-math-optimizations" +Allow optimizations for floating-point arithmetic that (a) assume +that arguments and results are valid and (b) may violate \s-1IEEE\s0 or +\&\s-1ANSI\s0 standards. When used at link-time, it may include libraries +or startup files that change the default \s-1FPU\s0 control word or other +similar optimizations. +.Sp +This option is not turned on by any \fB\-O\fR option since +it can result in incorrect output for programs which depend on +an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for +math functions. It may, however, yield faster code for programs +that do not require the guarantees of these specifications. +Enables \fB\-fno\-signed\-zeros\fR, \fB\-fno\-trapping\-math\fR, +\&\fB\-fassociative\-math\fR and \fB\-freciprocal\-math\fR. +.Sp +The default is \fB\-fno\-unsafe\-math\-optimizations\fR. +.IP "\fB\-fassociative\-math\fR" 4 +.IX Item "-fassociative-math" +Allow re-association of operands in series of floating-point operations. +This violates the \s-1ISO\s0 C and \*(C+ language standard by possibly changing +computation result. \s-1NOTE:\s0 re-ordering may change the sign of zero as +well as ignore NaNs and inhibit or create underflow or overflow (and +thus cannot be used on a code which relies on rounding behavior like +\&\f(CW\*(C`(x + 2**52) \- 2**52)\*(C'\fR. May also reorder floating-point comparisons +and thus may not be used when ordered comparisons are required. +This option requires that both \fB\-fno\-signed\-zeros\fR and +\&\fB\-fno\-trapping\-math\fR be in effect. Moreover, it doesn't make +much sense with \fB\-frounding\-math\fR. For Fortran the option +is automatically enabled when both \fB\-fno\-signed\-zeros\fR and +\&\fB\-fno\-trapping\-math\fR are in effect. +.Sp +The default is \fB\-fno\-associative\-math\fR. +.IP "\fB\-freciprocal\-math\fR" 4 +.IX Item "-freciprocal-math" +Allow the reciprocal of a value to be used instead of dividing by +the value if this enables optimizations. For example \f(CW\*(C`x / y\*(C'\fR +can be replaced with \f(CW\*(C`x * (1/y)\*(C'\fR which is useful if \f(CW\*(C`(1/y)\*(C'\fR +is subject to common subexpression elimination. Note that this loses +precision and increases the number of flops operating on the value. +.Sp +The default is \fB\-fno\-reciprocal\-math\fR. +.IP "\fB\-ffinite\-math\-only\fR" 4 +.IX Item "-ffinite-math-only" +Allow optimizations for floating-point arithmetic that assume +that arguments and results are not NaNs or +\-Infs. +.Sp +This option is not turned on by any \fB\-O\fR option since +it can result in incorrect output for programs which depend on +an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for +math functions. It may, however, yield faster code for programs +that do not require the guarantees of these specifications. +.Sp +The default is \fB\-fno\-finite\-math\-only\fR. +.IP "\fB\-fno\-signed\-zeros\fR" 4 +.IX Item "-fno-signed-zeros" +Allow optimizations for floating point arithmetic that ignore the +signedness of zero. \s-1IEEE\s0 arithmetic specifies the behavior of +distinct +0.0 and \-0.0 values, which then prohibits simplification +of expressions such as x+0.0 or 0.0*x (even with \fB\-ffinite\-math\-only\fR). +This option implies that the sign of a zero result isn't significant. +.Sp +The default is \fB\-fsigned\-zeros\fR. +.IP "\fB\-fno\-trapping\-math\fR" 4 +.IX Item "-fno-trapping-math" +Compile code assuming that floating-point operations cannot generate +user-visible traps. These traps include division by zero, overflow, +underflow, inexact result and invalid operation. This option requires +that \fB\-fno\-signaling\-nans\fR be in effect. Setting this option may +allow faster code if one relies on \*(L"non-stop\*(R" \s-1IEEE\s0 arithmetic, for example. +.Sp +This option should never be turned on by any \fB\-O\fR option since +it can result in incorrect output for programs which depend on +an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for +math functions. +.Sp +The default is \fB\-ftrapping\-math\fR. +.IP "\fB\-frounding\-math\fR" 4 +.IX Item "-frounding-math" +Disable transformations and optimizations that assume default floating +point rounding behavior. This is round-to-zero for all floating point +to integer conversions, and round-to-nearest for all other arithmetic +truncations. This option should be specified for programs that change +the \s-1FP\s0 rounding mode dynamically, or that may be executed with a +non-default rounding mode. This option disables constant folding of +floating point expressions at compile-time (which may be affected by +rounding mode) and arithmetic transformations that are unsafe in the +presence of sign-dependent rounding modes. +.Sp +The default is \fB\-fno\-rounding\-math\fR. +.Sp +This option is experimental and does not currently guarantee to +disable all \s-1GCC\s0 optimizations that are affected by rounding mode. +Future versions of \s-1GCC\s0 may provide finer control of this setting +using C99's \f(CW\*(C`FENV_ACCESS\*(C'\fR pragma. This command line option +will be used to specify the default state for \f(CW\*(C`FENV_ACCESS\*(C'\fR. +.IP "\fB\-fsignaling\-nans\fR" 4 +.IX Item "-fsignaling-nans" +Compile code assuming that \s-1IEEE\s0 signaling NaNs may generate user-visible +traps during floating-point operations. Setting this option disables +optimizations that may change the number of exceptions visible with +signaling NaNs. This option implies \fB\-ftrapping\-math\fR. +.Sp +This option causes the preprocessor macro \f(CW\*(C`_\|_SUPPORT_SNAN_\|_\*(C'\fR to +be defined. +.Sp +The default is \fB\-fno\-signaling\-nans\fR. +.Sp +This option is experimental and does not currently guarantee to +disable all \s-1GCC\s0 optimizations that affect signaling NaN behavior. +.IP "\fB\-fsingle\-precision\-constant\fR" 4 +.IX Item "-fsingle-precision-constant" +Treat floating point constant as single precision constant instead of +implicitly converting it to double precision constant. +.IP "\fB\-fcx\-limited\-range\fR" 4 +.IX Item "-fcx-limited-range" +When enabled, this option states that a range reduction step is not +needed when performing complex division. Also, there is no checking +whether the result of a complex multiplication or division is \f(CW\*(C`NaN ++ I*NaN\*(C'\fR, with an attempt to rescue the situation in that case. The +default is \fB\-fno\-cx\-limited\-range\fR, but is enabled by +\&\fB\-ffast\-math\fR. +.Sp +This option controls the default setting of the \s-1ISO\s0 C99 +\&\f(CW\*(C`CX_LIMITED_RANGE\*(C'\fR pragma. Nevertheless, the option applies to +all languages. +.IP "\fB\-fcx\-fortran\-rules\fR" 4 +.IX Item "-fcx-fortran-rules" +Complex multiplication and division follow Fortran rules. Range +reduction is done as part of complex division, but there is no checking +whether the result of a complex multiplication or division is \f(CW\*(C`NaN ++ I*NaN\*(C'\fR, with an attempt to rescue the situation in that case. +.Sp +The default is \fB\-fno\-cx\-fortran\-rules\fR. +.IP "\fBmin-mcf-cancel-iters\fR" 4 +.IX Item "min-mcf-cancel-iters" +The minimum number of iterations of negative cycle cancellation during +\&\s-1MCF\s0 profile correction before early termination. This parameter is +only useful when using \fB\-fprofile\-correction\fR. +.PP +The following options control optimizations that may improve +performance, but are not enabled by any \fB\-O\fR options. This +section includes experimental options that may produce broken code. +.IP "\fB\-fbranch\-probabilities\fR" 4 +.IX Item "-fbranch-probabilities" +After running a program compiled with \fB\-fprofile\-arcs\fR, you can compile it a second time using +\&\fB\-fbranch\-probabilities\fR, to improve optimizations based on +the number of times each branch was taken. When the program +compiled with \fB\-fprofile\-arcs\fR exits it saves arc execution +counts to a file called \fI\fIsourcename\fI.gcda\fR for each source +file. The information in this data file is very dependent on the +structure of the generated code, so you must use the same source code +and the same optimization options for both compilations. +.Sp +With \fB\-fbranch\-probabilities\fR, \s-1GCC\s0 puts a +\&\fB\s-1REG_BR_PROB\s0\fR note on each \fB\s-1JUMP_INSN\s0\fR and \fB\s-1CALL_INSN\s0\fR. +These can be used to improve optimization. Currently, they are only +used in one place: in \fIreorg.c\fR, instead of guessing which path a +branch is most likely to take, the \fB\s-1REG_BR_PROB\s0\fR values are used to +exactly determine which path is taken more often. +.IP "\fB\-fclone\-hot\-version\-paths\fR" 4 +.IX Item "-fclone-hot-version-paths" +When multi-version calls are made using \fB_\|_builtin_dispatch\fR, this flag +enables cloning and hoisting of hot multiversioned paths. +.IP "\fB\-fprofile\-values\fR" 4 +.IX Item "-fprofile-values" +If combined with \fB\-fprofile\-arcs\fR, it adds code so that some +data about values of expressions in the program is gathered. +.Sp +With \fB\-fbranch\-probabilities\fR, it reads back the data gathered +from profiling values of expressions for usage in optimizations. +.Sp +Enabled with \fB\-fprofile\-generate\fR and \fB\-fprofile\-use\fR. +.IP "\fB\-fvpt\fR" 4 +.IX Item "-fvpt" +If combined with \fB\-fprofile\-arcs\fR, it instructs the compiler to add +a code to gather information about values of expressions. +.Sp +With \fB\-fbranch\-probabilities\fR, it reads back the data gathered +and actually performs the optimizations based on them. +Currently the optimizations include specialization of division operation +using the knowledge about the value of the denominator. +.IP "\fB\-frename\-registers\fR" 4 +.IX Item "-frename-registers" +Attempt to avoid false dependencies in scheduled code by making use +of registers left over after register allocation. This optimization +will most benefit processors with lots of registers. Depending on the +debug information format adopted by the target, however, it can +make debugging impossible, since variables will no longer stay in +a \*(L"home register\*(R". +.Sp +Enabled by default with \fB\-funroll\-loops\fR and \fB\-fpeel\-loops\fR. +.IP "\fB\-ftracer\fR" 4 +.IX Item "-ftracer" +Perform tail duplication to enlarge superblock size. This transformation +simplifies the control flow of the function allowing other optimizations to do +better job. +.Sp +Enabled with \fB\-fprofile\-use\fR. +.IP "\fB\-funroll\-loops\fR" 4 +.IX Item "-funroll-loops" +Unroll loops whose number of iterations can be determined at compile time or +upon entry to the loop. \fB\-funroll\-loops\fR implies +\&\fB\-frerun\-cse\-after\-loop\fR, \fB\-fweb\fR and \fB\-frename\-registers\fR. +It also turns on complete loop peeling (i.e. complete removal of loops with +small constant number of iterations). This option makes code larger, and may +or may not make it run faster. +.Sp +Enabled with \fB\-fprofile\-use\fR. +.IP "\fB\-funroll\-all\-loops\fR" 4 +.IX Item "-funroll-all-loops" +Unroll all loops, even if their number of iterations is uncertain when +the loop is entered. This usually makes programs run more slowly. +\&\fB\-funroll\-all\-loops\fR implies the same options as +\&\fB\-funroll\-loops\fR. +.IP "\fB\-fpeel\-loops\fR" 4 +.IX Item "-fpeel-loops" +Peels the loops for that there is enough information that they do not +roll much (from profile feedback). It also turns on complete loop peeling +(i.e. complete removal of loops with small constant number of iterations). +.Sp +Enabled with \fB\-fprofile\-use\fR. +.IP "\fB\-fmove\-loop\-invariants\fR" 4 +.IX Item "-fmove-loop-invariants" +Enables the loop invariant motion pass in the \s-1RTL\s0 loop optimizer. Enabled +at level \fB\-O1\fR +.IP "\fB\-funswitch\-loops\fR" 4 +.IX Item "-funswitch-loops" +Move branches with loop invariant conditions out of the loop, with duplicates +of the loop on both branches (modified according to result of the condition). +.IP "\fB\-ffunction\-sections\fR" 4 +.IX Item "-ffunction-sections" +.PD 0 +.IP "\fB\-fdata\-sections\fR" 4 +.IX Item "-fdata-sections" +.PD +Place each function or data item into its own section in the output +file if the target supports arbitrary sections. The name of the +function or the name of the data item determines the section's name +in the output file. +.Sp +Use these options on systems where the linker can perform optimizations +to improve locality of reference in the instruction space. Most systems +using the \s-1ELF\s0 object format and \s-1SPARC\s0 processors running Solaris 2 have +linkers with such optimizations. \s-1AIX\s0 may have these optimizations in +the future. +.Sp +Only use these options when there are significant benefits from doing +so. When you specify these options, the assembler and linker will +create larger object and executable files and will also be slower. +You will not be able to use \f(CW\*(C`gprof\*(C'\fR on all systems if you +specify this option and you may have problems with debugging if +you specify both this option and \fB\-g\fR. +.IP "\fB\-fbranch\-target\-load\-optimize\fR" 4 +.IX Item "-fbranch-target-load-optimize" +Perform branch target register load optimization before prologue / epilogue +threading. +The use of target registers can typically be exposed only during reload, +thus hoisting loads out of loops and doing inter-block scheduling needs +a separate optimization pass. +.IP "\fB\-fbranch\-target\-load\-optimize2\fR" 4 +.IX Item "-fbranch-target-load-optimize2" +Perform branch target register load optimization after prologue / epilogue +threading. +.IP "\fB\-fbtr\-bb\-exclusive\fR" 4 +.IX Item "-fbtr-bb-exclusive" +When performing branch target register load optimization, don't reuse +branch target registers in within any basic block. +.IP "\fB\-fstack\-protector\fR" 4 +.IX Item "-fstack-protector" +Emit extra code to check for buffer overflows, such as stack smashing +attacks. This is done by adding a guard variable to functions with +vulnerable objects. This includes functions that call alloca, and +functions with buffers larger than 8 bytes. The guards are initialized +when a function is entered and then checked when the function exits. +If a guard check fails, an error message is printed and the program exits. +.IP "\fB\-fstack\-protector\-all\fR" 4 +.IX Item "-fstack-protector-all" +Like \fB\-fstack\-protector\fR except that all functions are protected. +.IP "\fB\-fstack\-protector\-strong\fR" 4 +.IX Item "-fstack-protector-strong" +Like \fB\-fstack\-protector\fR but includes additional functions to be +protected \- those that have local array definitions, or have references to +local frame addresses. +.IP "\fB\-fsection\-anchors\fR" 4 +.IX Item "-fsection-anchors" +Try to reduce the number of symbolic address calculations by using +shared \*(L"anchor\*(R" symbols to address nearby objects. This transformation +can help to reduce the number of \s-1GOT\s0 entries and \s-1GOT\s0 accesses on some +targets. +.Sp +For example, the implementation of the following function \f(CW\*(C`foo\*(C'\fR: +.Sp +.Vb 2 +\& static int a, b, c; +\& int foo (void) { return a + b + c; } +.Ve +.Sp +would usually calculate the addresses of all three variables, but if you +compile it with \fB\-fsection\-anchors\fR, it will access the variables +from a common anchor point instead. The effect is similar to the +following pseudocode (which isn't valid C): +.Sp +.Vb 5 +\& int foo (void) +\& { +\& register int *xr = &x; +\& return xr[&a \- &x] + xr[&b \- &x] + xr[&c \- &x]; +\& } +.Ve +.Sp +Not all targets support this option. +.IP "\fB\-\-param\fR \fIname\fR\fB=\fR\fIvalue\fR" 4 +.IX Item "--param name=value" +In some places, \s-1GCC\s0 uses various constants to control the amount of +optimization that is done. For example, \s-1GCC\s0 will not inline functions +that contain more that a certain number of instructions. You can +control some of these constants on the command-line using the +\&\fB\-\-param\fR option. +.Sp +The names of specific parameters, and the meaning of the values, are +tied to the internals of the compiler, and are subject to change +without notice in future releases. +.Sp +In each case, the \fIvalue\fR is an integer. The allowable choices for +\&\fIname\fR are given in the following table: +.RS 4 +.IP "\fBstruct-reorg-cold-struct-ratio\fR" 4 +.IX Item "struct-reorg-cold-struct-ratio" +The threshold ratio (as a percentage) between a structure frequency +and the frequency of the hottest structure in the program. This parameter +is used by struct-reorg optimization enabled by \fB\-fipa\-struct\-reorg\fR. +We say that if the ratio of a structure frequency, calculated by profiling, +to the hottest structure frequency in the program is less than this +parameter, then structure reorganization is not applied to this structure. +The default is 10. +.IP "\fBpredictable-branch-outcome\fR" 4 +.IX Item "predictable-branch-outcome" +When branch is predicted to be taken with probability lower than this threshold +(in percent), then it is considered well predictable. The default is 10. +.IP "\fBmax-crossjump-edges\fR" 4 +.IX Item "max-crossjump-edges" +The maximum number of incoming edges to consider for crossjumping. +The algorithm used by \fB\-fcrossjumping\fR is O(N^2) in +the number of edges incoming to each block. Increasing values mean +more aggressive optimization, making the compile time increase with +probably small improvement in executable size. +.IP "\fBmin-crossjump-insns\fR" 4 +.IX Item "min-crossjump-insns" +The minimum number of instructions which must be matched at the end +of two blocks before crossjumping will be performed on them. This +value is ignored in the case where all instructions in the block being +crossjumped from are matched. The default value is 5. +.IP "\fBmax-grow-copy-bb-insns\fR" 4 +.IX Item "max-grow-copy-bb-insns" +The maximum code size expansion factor when copying basic blocks +instead of jumping. The expansion is relative to a jump instruction. +The default value is 8. +.IP "\fBmax-goto-duplication-insns\fR" 4 +.IX Item "max-goto-duplication-insns" +The maximum number of instructions to duplicate to a block that jumps +to a computed goto. To avoid O(N^2) behavior in a number of +passes, \s-1GCC\s0 factors computed gotos early in the compilation process, +and unfactors them as late as possible. Only computed jumps at the +end of a basic blocks with no more than max-goto-duplication-insns are +unfactored. The default value is 8. +.IP "\fBmax-delay-slot-insn-search\fR" 4 +.IX Item "max-delay-slot-insn-search" +The maximum number of instructions to consider when looking for an +instruction to fill a delay slot. If more than this arbitrary number of +instructions is searched, the time savings from filling the delay slot +will be minimal so stop searching. Increasing values mean more +aggressive optimization, making the compile time increase with probably +small improvement in executable run time. +.IP "\fBmax-delay-slot-live-search\fR" 4 +.IX Item "max-delay-slot-live-search" +When trying to fill delay slots, the maximum number of instructions to +consider when searching for a block with valid live register +information. Increasing this arbitrarily chosen value means more +aggressive optimization, increasing the compile time. This parameter +should be removed when the delay slot code is rewritten to maintain the +control-flow graph. +.IP "\fBmax-gcse-memory\fR" 4 +.IX Item "max-gcse-memory" +The approximate maximum amount of memory that will be allocated in +order to perform the global common subexpression elimination +optimization. If more memory than specified is required, the +optimization will not be done. +.IP "\fBmax-gcse-insertion-ratio\fR" 4 +.IX Item "max-gcse-insertion-ratio" +If the ratio of expression insertions to deletions is larger than this value +for any expression, then \s-1RTL\s0 \s-1PRE\s0 will insert or remove the expression and thus +leave partially redundant computations in the instruction stream. The default value is 20. +.IP "\fBmax-pending-list-length\fR" 4 +.IX Item "max-pending-list-length" +The maximum number of pending dependencies scheduling will allow +before flushing the current state and starting over. Large functions +with few branches or calls can create excessively large lists which +needlessly consume memory and resources. +.IP "\fBmax-inline-insns-single\fR" 4 +.IX Item "max-inline-insns-single" +Several parameters control the tree inliner used in gcc. +This number sets the maximum number of instructions (counted in \s-1GCC\s0's +internal representation) in a single function that the tree inliner +will consider for inlining. This only affects functions declared +inline and methods implemented in a class declaration (\*(C+). +The default value is 400. +.IP "\fBmax-inline-insns-auto\fR" 4 +.IX Item "max-inline-insns-auto" +When you use \fB\-finline\-functions\fR (included in \fB\-O3\fR), +a lot of functions that would otherwise not be considered for inlining +by the compiler will be investigated. To those functions, a different +(more restrictive) limit compared to functions declared inline can +be applied. +The default value is 40. +.IP "\fBmversn-clone-depth\fR" 4 +.IX Item "mversn-clone-depth" +When using \fB\-fclone\-hot\-version\-paths\fR, hot function paths are multi\- +versioned via cloning. This parameter specifies the maximum length of the +call graph path that can be cloned. The default value is 2. +.IP "\fBnum-mversn-clones\fR" 4 +.IX Item "num-mversn-clones" +When using \fB\-fclone\-hot\-version\-paths\fR, hot function paths are multi\- +versioned via cloning. This parameter specifies the maximum number of +functions that can be cloned. The default value is 10. +.IP "\fBlarge-function-insns\fR" 4 +.IX Item "large-function-insns" +The limit specifying really large functions. For functions larger than this +limit after inlining, inlining is constrained by +\&\fB\-\-param large-function-growth\fR. This parameter is useful primarily +to avoid extreme compilation time caused by non-linear algorithms used by the +backend. +The default value is 2700. +.IP "\fBlarge-function-growth\fR" 4 +.IX Item "large-function-growth" +Specifies maximal growth of large function caused by inlining in percents. +The default value is 100 which limits large function growth to 2.0 times +the original size. +.IP "\fBlarge-unit-insns\fR" 4 +.IX Item "large-unit-insns" +The limit specifying large translation unit. Growth caused by inlining of +units larger than this limit is limited by \fB\-\-param inline-unit-growth\fR. +For small units this might be too tight (consider unit consisting of function A +that is inline and B that just calls A three time. If B is small relative to +A, the growth of unit is 300\e% and yet such inlining is very sane. For very +large units consisting of small inlineable functions however the overall unit +growth limit is needed to avoid exponential explosion of code size. Thus for +smaller units, the size is increased to \fB\-\-param large-unit-insns\fR +before applying \fB\-\-param inline-unit-growth\fR. The default is 10000 +.IP "\fBinline-unit-growth\fR" 4 +.IX Item "inline-unit-growth" +Specifies maximal overall growth of the compilation unit caused by inlining. +The default value is 30 which limits unit growth to 1.3 times the original +size. +.IP "\fBipcp-unit-growth\fR" 4 +.IX Item "ipcp-unit-growth" +Specifies maximal overall growth of the compilation unit caused by +interprocedural constant propagation. The default value is 10 which limits +unit growth to 1.1 times the original size. +.IP "\fBlarge-stack-frame\fR" 4 +.IX Item "large-stack-frame" +The limit specifying large stack frames. While inlining the algorithm is trying +to not grow past this limit too much. Default value is 256 bytes. +.IP "\fBlarge-stack-frame-growth\fR" 4 +.IX Item "large-stack-frame-growth" +Specifies maximal growth of large stack frames caused by inlining in percents. +The default value is 1000 which limits large stack frame growth to 11 times +the original size. +.IP "\fBmax-inline-insns-recursive\fR" 4 +.IX Item "max-inline-insns-recursive" +.PD 0 +.IP "\fBmax-inline-insns-recursive-auto\fR" 4 +.IX Item "max-inline-insns-recursive-auto" +.PD +Specifies maximum number of instructions out-of-line copy of self recursive inline +function can grow into by performing recursive inlining. +.Sp +For functions declared inline \fB\-\-param max-inline-insns-recursive\fR is +taken into account. For function not declared inline, recursive inlining +happens only when \fB\-finline\-functions\fR (included in \fB\-O3\fR) is +enabled and \fB\-\-param max-inline-insns-recursive-auto\fR is used. The +default value is 450. +.IP "\fBmax-inline-recursive-depth\fR" 4 +.IX Item "max-inline-recursive-depth" +.PD 0 +.IP "\fBmax-inline-recursive-depth-auto\fR" 4 +.IX Item "max-inline-recursive-depth-auto" +.PD +Specifies maximum recursion depth used by the recursive inlining. +.Sp +For functions declared inline \fB\-\-param max-inline-recursive-depth\fR is +taken into account. For function not declared inline, recursive inlining +happens only when \fB\-finline\-functions\fR (included in \fB\-O3\fR) is +enabled and \fB\-\-param max-inline-recursive-depth-auto\fR is used. The +default value is 8. +.IP "\fBmin-inline-recursive-probability\fR" 4 +.IX Item "min-inline-recursive-probability" +Recursive inlining is profitable only for function having deep recursion +in average and can hurt for function having little recursion depth by +increasing the prologue size or complexity of function body to other +optimizers. +.Sp +When profile feedback is available (see \fB\-fprofile\-generate\fR) the actual +recursion depth can be guessed from probability that function will recurse via +given call expression. This parameter limits inlining only to call expression +whose probability exceeds given threshold (in percents). The default value is +10. +.IP "\fBearly-inlining-insns\fR" 4 +.IX Item "early-inlining-insns" +Specify growth that early inliner can make. In effect it increases amount of +inlining for code having large abstraction penalty. The default value is 10. +.IP "\fBmax-early-inliner-iterations\fR" 4 +.IX Item "max-early-inliner-iterations" +.PD 0 +.IP "\fBmax-early-inliner-iterations\fR" 4 +.IX Item "max-early-inliner-iterations" +.PD +Limit of iterations of early inliner. This basically bounds number of nested +indirect calls early inliner can resolve. Deeper chains are still handled by +late inlining. +.IP "\fBcomdat-sharing-probability\fR" 4 +.IX Item "comdat-sharing-probability" +.PD 0 +.IP "\fBcomdat-sharing-probability\fR" 4 +.IX Item "comdat-sharing-probability" +.PD +Probability (in percent) that \*(C+ inline function with comdat visibility +will be shared across multiple compilation units. The default value is 20. +.IP "\fBmin-vect-loop-bound\fR" 4 +.IX Item "min-vect-loop-bound" +The minimum number of iterations under which a loop will not get vectorized +when \fB\-ftree\-vectorize\fR is used. The number of iterations after +vectorization needs to be greater than the value specified by this option +to allow vectorization. The default value is 0. +.IP "\fBgcse-cost-distance-ratio\fR" 4 +.IX Item "gcse-cost-distance-ratio" +Scaling factor in calculation of maximum distance an expression +can be moved by \s-1GCSE\s0 optimizations. This is currently supported only in the +code hoisting pass. The bigger the ratio, the more aggressive code hoisting +will be with simple expressions, i.e., the expressions which have cost +less than \fBgcse-unrestricted-cost\fR. Specifying 0 will disable +hoisting of simple expressions. The default value is 10. +.IP "\fBgcse-unrestricted-cost\fR" 4 +.IX Item "gcse-unrestricted-cost" +Cost, roughly measured as the cost of a single typical machine +instruction, at which \s-1GCSE\s0 optimizations will not constrain +the distance an expression can travel. This is currently +supported only in the code hoisting pass. The lesser the cost, +the more aggressive code hoisting will be. Specifying 0 will +allow all expressions to travel unrestricted distances. +The default value is 3. +.IP "\fBmax-hoist-depth\fR" 4 +.IX Item "max-hoist-depth" +The depth of search in the dominator tree for expressions to hoist. +This is used to avoid quadratic behavior in hoisting algorithm. +The value of 0 will avoid limiting the search, but may slow down compilation +of huge functions. The default value is 30. +.IP "\fBmax-unrolled-insns\fR" 4 +.IX Item "max-unrolled-insns" +The maximum number of instructions that a loop should have if that loop +is unrolled, and if the loop is unrolled, it determines how many times +the loop code is unrolled. +.IP "\fBmax-average-unrolled-insns\fR" 4 +.IX Item "max-average-unrolled-insns" +The maximum number of instructions biased by probabilities of their execution +that a loop should have if that loop is unrolled, and if the loop is unrolled, +it determines how many times the loop code is unrolled. +.IP "\fBmax-unroll-times\fR" 4 +.IX Item "max-unroll-times" +The maximum number of unrollings of a single loop. +.IP "\fBmax-peeled-insns\fR" 4 +.IX Item "max-peeled-insns" +The maximum number of instructions that a loop should have if that loop +is peeled, and if the loop is peeled, it determines how many times +the loop code is peeled. +.IP "\fBmax-peel-times\fR" 4 +.IX Item "max-peel-times" +The maximum number of peelings of a single loop. +.IP "\fBmax-completely-peeled-insns\fR" 4 +.IX Item "max-completely-peeled-insns" +The maximum number of insns of a completely peeled loop. +.IP "\fBmax-completely-peeled-insns-feedback\fR" 4 +.IX Item "max-completely-peeled-insns-feedback" +The maximum number of insns of a completely peeled loop when profile +feedback is available and the loop is hot. Because of the real +profiles, this value may set to be larger for hot loops. Its default +value is 600. +.IP "\fBmax-once-peeled-insns\fR" 4 +.IX Item "max-once-peeled-insns" +The maximum number of insns of a peeled loop that rolls only once. +.IP "\fBmax-once-peeled-insns-feedback\fR" 4 +.IX Item "max-once-peeled-insns-feedback" +The maximum number of insns of a peeled loop when profile feedback is +available and the loop is hot. Because of the real profiles, this +value may set to be larger for hot loops. The default value is 600. +.IP "\fBmax-completely-peel-times\fR" 4 +.IX Item "max-completely-peel-times" +The maximum number of iterations of a loop to be suitable for complete peeling. +.IP "\fBmax-completely-peel-times-feedback\fR" 4 +.IX Item "max-completely-peel-times-feedback" +The maximum number of iterations of a loop to be suitable for complete +peeling when profile feedback is available and the loop is +hot. Because of the real profiles, this value may set to be larger for +hot loops. Its default value is 16. +.IP "\fBmax-completely-peel-loop-nest-depth\fR" 4 +.IX Item "max-completely-peel-loop-nest-depth" +The maximum depth of a loop nest suitable for complete peeling. +.IP "\fBcodesize-hotness-threshold\fR" 4 +.IX Item "codesize-hotness-threshold" +The minimum profile count of basic blocks to look at when estimating +the code size footprint of the call graph in a \s-1LIPO\s0 compile. +.IP "\fBunrollpeel-codesize-threshold\fR" 4 +.IX Item "unrollpeel-codesize-threshold" +Maximum \s-1LIPO\s0 code size footprint estimate for loop unrolling and peeling. +.IP "\fBmax-unswitch-insns\fR" 4 +.IX Item "max-unswitch-insns" +The maximum number of insns of an unswitched loop. +.IP "\fBmax-unswitch-level\fR" 4 +.IX Item "max-unswitch-level" +The maximum number of branches unswitched in a single loop. +.IP "\fBlim-expensive\fR" 4 +.IX Item "lim-expensive" +The minimum cost of an expensive expression in the loop invariant motion. +.IP "\fBiv-consider-all-candidates-bound\fR" 4 +.IX Item "iv-consider-all-candidates-bound" +Bound on number of candidates for induction variables below that +all candidates are considered for each use in induction variable +optimizations. Only the most relevant candidates are considered +if there are more candidates, to avoid quadratic time complexity. +.IP "\fBiv-max-considered-uses\fR" 4 +.IX Item "iv-max-considered-uses" +The induction variable optimizations give up on loops that contain more +induction variable uses. +.IP "\fBiv-always-prune-cand-set-bound\fR" 4 +.IX Item "iv-always-prune-cand-set-bound" +If number of candidates in the set is smaller than this value, +we always try to remove unnecessary ivs from the set during its +optimization when a new iv is added to the set. +.IP "\fBscev-max-expr-size\fR" 4 +.IX Item "scev-max-expr-size" +Bound on size of expressions used in the scalar evolutions analyzer. +Large expressions slow the analyzer. +.IP "\fBscev-max-expr-complexity\fR" 4 +.IX Item "scev-max-expr-complexity" +Bound on the complexity of the expressions in the scalar evolutions analyzer. +Complex expressions slow the analyzer. +.IP "\fBomega-max-vars\fR" 4 +.IX Item "omega-max-vars" +The maximum number of variables in an Omega constraint system. +The default value is 128. +.IP "\fBomega-max-geqs\fR" 4 +.IX Item "omega-max-geqs" +The maximum number of inequalities in an Omega constraint system. +The default value is 256. +.IP "\fBomega-max-eqs\fR" 4 +.IX Item "omega-max-eqs" +The maximum number of equalities in an Omega constraint system. +The default value is 128. +.IP "\fBomega-max-wild-cards\fR" 4 +.IX Item "omega-max-wild-cards" +The maximum number of wildcard variables that the Omega solver will +be able to insert. The default value is 18. +.IP "\fBomega-hash-table-size\fR" 4 +.IX Item "omega-hash-table-size" +The size of the hash table in the Omega solver. The default value is +550. +.IP "\fBomega-max-keys\fR" 4 +.IX Item "omega-max-keys" +The maximal number of keys used by the Omega solver. The default +value is 500. +.IP "\fBomega-eliminate-redundant-constraints\fR" 4 +.IX Item "omega-eliminate-redundant-constraints" +When set to 1, use expensive methods to eliminate all redundant +constraints. The default value is 0. +.IP "\fBvect-max-version-for-alignment-checks\fR" 4 +.IX Item "vect-max-version-for-alignment-checks" +The maximum number of runtime checks that can be performed when +doing loop versioning for alignment in the vectorizer. See option +ftree-vect-loop-version for more information. +.IP "\fBvect-max-version-for-alias-checks\fR" 4 +.IX Item "vect-max-version-for-alias-checks" +The maximum number of runtime checks that can be performed when +doing loop versioning for alias in the vectorizer. See option +ftree-vect-loop-version for more information. +.IP "\fBmax-iterations-to-track\fR" 4 +.IX Item "max-iterations-to-track" +The maximum number of iterations of a loop the brute force algorithm +for analysis of # of iterations of the loop tries to evaluate. +.IP "\fBhot-bb-count-fraction\fR" 4 +.IX Item "hot-bb-count-fraction" +Select fraction of the maximal count of repetitions of basic block in program +given basic block needs to have to be considered hot. +.IP "\fBhot-bb-frequency-fraction\fR" 4 +.IX Item "hot-bb-frequency-fraction" +Select fraction of the entry block frequency of executions of basic block in +function given basic block needs to have to be considered hot +.IP "\fBmax-predicted-iterations\fR" 4 +.IX Item "max-predicted-iterations" +The maximum number of loop iterations we predict statically. This is useful +in cases where function contain single loop with known bound and other loop +with unknown. We predict the known number of iterations correctly, while +the unknown number of iterations average to roughly 10. This means that the +loop without bounds would appear artificially cold relative to the other one. +.IP "\fBalign-threshold\fR" 4 +.IX Item "align-threshold" +Select fraction of the maximal frequency of executions of basic block in +function given basic block will get aligned. +.IP "\fBalign-loop-iterations\fR" 4 +.IX Item "align-loop-iterations" +A loop expected to iterate at lest the selected number of iterations will get +aligned. +.IP "\fBtracer-dynamic-coverage\fR" 4 +.IX Item "tracer-dynamic-coverage" +.PD 0 +.IP "\fBtracer-dynamic-coverage-feedback\fR" 4 +.IX Item "tracer-dynamic-coverage-feedback" +.PD +This value is used to limit superblock formation once the given percentage of +executed instructions is covered. This limits unnecessary code size +expansion. +.Sp +The \fBtracer-dynamic-coverage-feedback\fR is used only when profile +feedback is available. The real profiles (as opposed to statically estimated +ones) are much less balanced allowing the threshold to be larger value. +.IP "\fBtracer-max-code-growth\fR" 4 +.IX Item "tracer-max-code-growth" +Stop tail duplication once code growth has reached given percentage. This is +rather hokey argument, as most of the duplicates will be eliminated later in +cross jumping, so it may be set to much higher values than is the desired code +growth. +.IP "\fBtracer-min-branch-ratio\fR" 4 +.IX Item "tracer-min-branch-ratio" +Stop reverse growth when the reverse probability of best edge is less than this +threshold (in percent). +.IP "\fBtracer-min-branch-ratio\fR" 4 +.IX Item "tracer-min-branch-ratio" +.PD 0 +.IP "\fBtracer-min-branch-ratio-feedback\fR" 4 +.IX Item "tracer-min-branch-ratio-feedback" +.PD +Stop forward growth if the best edge do have probability lower than this +threshold. +.Sp +Similarly to \fBtracer-dynamic-coverage\fR two values are present, one for +compilation for profile feedback and one for compilation without. The value +for compilation with profile feedback needs to be more conservative (higher) in +order to make tracer effective. +.IP "\fBmax-cse-path-length\fR" 4 +.IX Item "max-cse-path-length" +Maximum number of basic blocks on path that cse considers. The default is 10. +.IP "\fBmax-cse-insns\fR" 4 +.IX Item "max-cse-insns" +The maximum instructions \s-1CSE\s0 process before flushing. The default is 1000. +.IP "\fBggc-min-expand\fR" 4 +.IX Item "ggc-min-expand" +\&\s-1GCC\s0 uses a garbage collector to manage its own memory allocation. This +parameter specifies the minimum percentage by which the garbage +collector's heap should be allowed to expand between collections. +Tuning this may improve compilation speed; it has no effect on code +generation. +.Sp +The default is 30% + 70% * (\s-1RAM/1GB\s0) with an upper bound of 100% when +\&\s-1RAM\s0 >= 1GB. If \f(CW\*(C`getrlimit\*(C'\fR is available, the notion of \*(L"\s-1RAM\s0\*(R" is +the smallest of actual \s-1RAM\s0 and \f(CW\*(C`RLIMIT_DATA\*(C'\fR or \f(CW\*(C`RLIMIT_AS\*(C'\fR. If +\&\s-1GCC\s0 is not able to calculate \s-1RAM\s0 on a particular platform, the lower +bound of 30% is used. Setting this parameter and +\&\fBggc-min-heapsize\fR to zero causes a full collection to occur at +every opportunity. This is extremely slow, but can be useful for +debugging. +.IP "\fBggc-min-heapsize\fR" 4 +.IX Item "ggc-min-heapsize" +Minimum size of the garbage collector's heap before it begins bothering +to collect garbage. The first collection occurs after the heap expands +by \fBggc-min-expand\fR% beyond \fBggc-min-heapsize\fR. Again, +tuning this may improve compilation speed, and has no effect on code +generation. +.Sp +The default is the smaller of \s-1RAM/8\s0, \s-1RLIMIT_RSS\s0, or a limit which +tries to ensure that \s-1RLIMIT_DATA\s0 or \s-1RLIMIT_AS\s0 are not exceeded, but +with a lower bound of 4096 (four megabytes) and an upper bound of +131072 (128 megabytes). If \s-1GCC\s0 is not able to calculate \s-1RAM\s0 on a +particular platform, the lower bound is used. Setting this parameter +very large effectively disables garbage collection. Setting this +parameter and \fBggc-min-expand\fR to zero causes a full collection +to occur at every opportunity. +.IP "\fBmax-reload-search-insns\fR" 4 +.IX Item "max-reload-search-insns" +The maximum number of instruction reload should look backward for equivalent +register. Increasing values mean more aggressive optimization, making the +compile time increase with probably slightly better performance. The default +value is 100. +.IP "\fBmax-cselib-memory-locations\fR" 4 +.IX Item "max-cselib-memory-locations" +The maximum number of memory locations cselib should take into account. +Increasing values mean more aggressive optimization, making the compile time +increase with probably slightly better performance. The default value is 500. +.IP "\fBreorder-blocks-duplicate\fR" 4 +.IX Item "reorder-blocks-duplicate" +.PD 0 +.IP "\fBreorder-blocks-duplicate-feedback\fR" 4 +.IX Item "reorder-blocks-duplicate-feedback" +.PD +Used by basic block reordering pass to decide whether to use unconditional +branch or duplicate the code on its destination. Code is duplicated when its +estimated size is smaller than this value multiplied by the estimated size of +unconditional jump in the hot spots of the program. +.Sp +The \fBreorder-block-duplicate-feedback\fR is used only when profile +feedback is available and may be set to higher values than +\&\fBreorder-block-duplicate\fR since information about the hot spots is more +accurate. +.IP "\fBmax-sched-ready-insns\fR" 4 +.IX Item "max-sched-ready-insns" +The maximum number of instructions ready to be issued the scheduler should +consider at any given time during the first scheduling pass. Increasing +values mean more thorough searches, making the compilation time increase +with probably little benefit. The default value is 100. +.IP "\fBmax-sched-region-blocks\fR" 4 +.IX Item "max-sched-region-blocks" +The maximum number of blocks in a region to be considered for +interblock scheduling. The default value is 10. +.IP "\fBmax-pipeline-region-blocks\fR" 4 +.IX Item "max-pipeline-region-blocks" +The maximum number of blocks in a region to be considered for +pipelining in the selective scheduler. The default value is 15. +.IP "\fBmax-sched-region-insns\fR" 4 +.IX Item "max-sched-region-insns" +The maximum number of insns in a region to be considered for +interblock scheduling. The default value is 100. +.IP "\fBmax-pipeline-region-insns\fR" 4 +.IX Item "max-pipeline-region-insns" +The maximum number of insns in a region to be considered for +pipelining in the selective scheduler. The default value is 200. +.IP "\fBmin-spec-prob\fR" 4 +.IX Item "min-spec-prob" +The minimum probability (in percents) of reaching a source block +for interblock speculative scheduling. The default value is 40. +.IP "\fBmax-sched-extend-regions-iters\fR" 4 +.IX Item "max-sched-extend-regions-iters" +The maximum number of iterations through \s-1CFG\s0 to extend regions. +0 \- disable region extension, +N \- do at most N iterations. +The default value is 0. +.IP "\fBmax-sched-insn-conflict-delay\fR" 4 +.IX Item "max-sched-insn-conflict-delay" +The maximum conflict delay for an insn to be considered for speculative motion. +The default value is 3. +.IP "\fBsched-spec-prob-cutoff\fR" 4 +.IX Item "sched-spec-prob-cutoff" +The minimal probability of speculation success (in percents), so that +speculative insn will be scheduled. +The default value is 40. +.IP "\fBsched-mem-true-dep-cost\fR" 4 +.IX Item "sched-mem-true-dep-cost" +Minimal distance (in \s-1CPU\s0 cycles) between store and load targeting same +memory locations. The default value is 1. +.IP "\fBselsched-max-lookahead\fR" 4 +.IX Item "selsched-max-lookahead" +The maximum size of the lookahead window of selective scheduling. It is a +depth of search for available instructions. +The default value is 50. +.IP "\fBselsched-max-sched-times\fR" 4 +.IX Item "selsched-max-sched-times" +The maximum number of times that an instruction will be scheduled during +selective scheduling. This is the limit on the number of iterations +through which the instruction may be pipelined. The default value is 2. +.IP "\fBselsched-max-insns-to-rename\fR" 4 +.IX Item "selsched-max-insns-to-rename" +The maximum number of best instructions in the ready list that are considered +for renaming in the selective scheduler. The default value is 2. +.IP "\fBmax-last-value-rtl\fR" 4 +.IX Item "max-last-value-rtl" +The maximum size measured as number of RTLs that can be recorded in an expression +in combiner for a pseudo register as last known value of that register. The default +is 10000. +.IP "\fBinteger-share-limit\fR" 4 +.IX Item "integer-share-limit" +Small integer constants can use a shared data structure, reducing the +compiler's memory usage and increasing its speed. This sets the maximum +value of a shared integer constant. The default value is 256. +.IP "\fBmin-virtual-mappings\fR" 4 +.IX Item "min-virtual-mappings" +Specifies the minimum number of virtual mappings in the incremental +\&\s-1SSA\s0 updater that should be registered to trigger the virtual mappings +heuristic defined by virtual-mappings-ratio. The default value is +100. +.IP "\fBvirtual-mappings-ratio\fR" 4 +.IX Item "virtual-mappings-ratio" +If the number of virtual mappings is virtual-mappings-ratio bigger +than the number of virtual symbols to be updated, then the incremental +\&\s-1SSA\s0 updater switches to a full update for those symbols. The default +ratio is 3. +.IP "\fBssp-buffer-size\fR" 4 +.IX Item "ssp-buffer-size" +The minimum size of buffers (i.e. arrays) that will receive stack smashing +protection when \fB\-fstack\-protection\fR is used. +.IP "\fBmax-jump-thread-duplication-stmts\fR" 4 +.IX Item "max-jump-thread-duplication-stmts" +Maximum number of statements allowed in a block that needs to be +duplicated when threading jumps. +.IP "\fBmax-fields-for-field-sensitive\fR" 4 +.IX Item "max-fields-for-field-sensitive" +Maximum number of fields in a structure we will treat in +a field sensitive manner during pointer analysis. The default is zero +for \-O0, and \-O1 and 100 for \-Os, \-O2, and \-O3. +.IP "\fBprefetch-latency\fR" 4 +.IX Item "prefetch-latency" +Estimate on average number of instructions that are executed before +prefetch finishes. The distance we prefetch ahead is proportional +to this constant. Increasing this number may also lead to less +streams being prefetched (see \fBsimultaneous-prefetches\fR). +.IP "\fBsimultaneous-prefetches\fR" 4 +.IX Item "simultaneous-prefetches" +Maximum number of prefetches that can run at the same time. +.IP "\fBl1\-cache\-line\-size\fR" 4 +.IX Item "l1-cache-line-size" +The size of cache line in L1 cache, in bytes. +.IP "\fBl1\-cache\-size\fR" 4 +.IX Item "l1-cache-size" +The size of L1 cache, in kilobytes. +.IP "\fBl2\-cache\-size\fR" 4 +.IX Item "l2-cache-size" +The size of L2 cache, in kilobytes. +.IP "\fBmin-insn-to-prefetch-ratio\fR" 4 +.IX Item "min-insn-to-prefetch-ratio" +The minimum ratio between the number of instructions and the +number of prefetches to enable prefetching in a loop. +.IP "\fBprefetch-min-insn-to-mem-ratio\fR" 4 +.IX Item "prefetch-min-insn-to-mem-ratio" +The minimum ratio between the number of instructions and the +number of memory references to enable prefetching in a loop. +.IP "\fBuse-canonical-types\fR" 4 +.IX Item "use-canonical-types" +Whether the compiler should use the \*(L"canonical\*(R" type system. By +default, this should always be 1, which uses a more efficient internal +mechanism for comparing types in \*(C+ and Objective\-\*(C+. However, if +bugs in the canonical type system are causing compilation failures, +set this value to 0 to disable canonical types. +.IP "\fBswitch-conversion-max-branch-ratio\fR" 4 +.IX Item "switch-conversion-max-branch-ratio" +Switch initialization conversion will refuse to create arrays that are +bigger than \fBswitch-conversion-max-branch-ratio\fR times the number of +branches in the switch. +.IP "\fBmax-partial-antic-length\fR" 4 +.IX Item "max-partial-antic-length" +Maximum length of the partial antic set computed during the tree +partial redundancy elimination optimization (\fB\-ftree\-pre\fR) when +optimizing at \fB\-O3\fR and above. For some sorts of source code +the enhanced partial redundancy elimination optimization can run away, +consuming all of the memory available on the host machine. This +parameter sets a limit on the length of the sets that are computed, +which prevents the runaway behavior. Setting a value of 0 for +this parameter will allow an unlimited set length. +.IP "\fBsccvn-max-scc-size\fR" 4 +.IX Item "sccvn-max-scc-size" +Maximum size of a strongly connected component (\s-1SCC\s0) during \s-1SCCVN\s0 +processing. If this limit is hit, \s-1SCCVN\s0 processing for the whole +function will not be done and optimizations depending on it will +be disabled. The default maximum \s-1SCC\s0 size is 10000. +.IP "\fBira-max-loops-num\fR" 4 +.IX Item "ira-max-loops-num" +\&\s-1IRA\s0 uses a regional register allocation by default. If a function +contains loops more than number given by the parameter, only at most +given number of the most frequently executed loops will form regions +for the regional register allocation. The default value of the +parameter is 100. +.IP "\fBira-max-conflict-table-size\fR" 4 +.IX Item "ira-max-conflict-table-size" +Although \s-1IRA\s0 uses a sophisticated algorithm of compression conflict +table, the table can be still big for huge functions. If the conflict +table for a function could be more than size in \s-1MB\s0 given by the +parameter, the conflict table is not built and faster, simpler, and +lower quality register allocation algorithm will be used. The +algorithm do not use pseudo-register conflicts. The default value of +the parameter is 2000. +.IP "\fBira-loop-reserved-regs\fR" 4 +.IX Item "ira-loop-reserved-regs" +\&\s-1IRA\s0 can be used to evaluate more accurate register pressure in loops +for decision to move loop invariants (see \fB\-O3\fR). The number +of available registers reserved for some other purposes is described +by this parameter. The default value of the parameter is 2 which is +minimal number of registers needed for execution of typical +instruction. This value is the best found from numerous experiments. +.IP "\fBloop-invariant-max-bbs-in-loop\fR" 4 +.IX Item "loop-invariant-max-bbs-in-loop" +Loop invariant motion can be very expensive, both in compile time and +in amount of needed compile time memory, with very large loops. Loops +with more basic blocks than this parameter won't have loop invariant +motion optimization performed on them. The default value of the +parameter is 1000 for \-O1 and 10000 for \-O2 and above. +.IP "\fBmax-vartrack-size\fR" 4 +.IX Item "max-vartrack-size" +Sets a maximum number of hash table slots to use during variable +tracking dataflow analysis of any function. If this limit is exceeded +with variable tracking at assignments enabled, analysis for that +function is retried without it, after removing all debug insns from +the function. If the limit is exceeded even without debug insns, var +tracking analysis is completely disabled for the function. Setting +the parameter to zero makes it unlimited. +.IP "\fBmin-nondebug-insn-uid\fR" 4 +.IX Item "min-nondebug-insn-uid" +Use uids starting at this parameter for nondebug insns. The range below +the parameter is reserved exclusively for debug insns created by +\&\fB\-fvar\-tracking\-assignments\fR, but debug insns may get +(non-overlapping) uids above it if the reserved range is exhausted. +.IP "\fBipa-sra-ptr-growth-factor\fR" 4 +.IX Item "ipa-sra-ptr-growth-factor" +IPA-SRA will replace a pointer to an aggregate with one or more new +parameters only when their cumulative size is less or equal to +\&\fBipa-sra-ptr-growth-factor\fR times the size of the original +pointer parameter. +.IP "\fBgraphite-max-nb-scop-params\fR" 4 +.IX Item "graphite-max-nb-scop-params" +To avoid exponential effects in the Graphite loop transforms, the +number of parameters in a Static Control Part (SCoP) is bounded. The +default value is 10 parameters. A variable whose value is unknown at +compile time and defined outside a SCoP is a parameter of the SCoP. +.IP "\fBgraphite-max-bbs-per-function\fR" 4 +.IX Item "graphite-max-bbs-per-function" +To avoid exponential effects in the detection of SCoPs, the size of +the functions analyzed by Graphite is bounded. The default value is +100 basic blocks. +.IP "\fBloop-block-tile-size\fR" 4 +.IX Item "loop-block-tile-size" +Loop blocking or strip mining transforms, enabled with +\&\fB\-floop\-block\fR or \fB\-floop\-strip\-mine\fR, strip mine each +loop in the loop nest by a given number of iterations. The strip +length can be changed using the \fBloop-block-tile-size\fR +parameter. The default value is 51 iterations. +.IP "\fBdevirt-type-list-size\fR" 4 +.IX Item "devirt-type-list-size" +IPA-CP attempts to track all possible types passed to a function's +parameter in order to perform devirtualization. +\&\fBdevirt-type-list-size\fR is the maximum number of types it +stores per a single formal parameter of a function. +.IP "\fBlto-partitions\fR" 4 +.IX Item "lto-partitions" +Specify desired number of partitions produced during \s-1WHOPR\s0 compilation. +The number of partitions should exceed the number of CPUs used for compilation. +The default value is 32. +.IP "\fBlto-minpartition\fR" 4 +.IX Item "lto-minpartition" +Size of minimal partition for \s-1WHOPR\s0 (in estimated instructions). +This prevents expenses of splitting very small programs into too many +partitions. +.IP "\fBcxx-max-namespaces-for-diagnostic-help\fR" 4 +.IX Item "cxx-max-namespaces-for-diagnostic-help" +The maximum number of namespaces to consult for suggestions when \*(C+ +name lookup fails for an identifier. The default is 1000. +.RE +.RS 4 +.RE +.SS "Options Controlling the Preprocessor" +.IX Subsection "Options Controlling the Preprocessor" +These options control the C preprocessor, which is run on each C source +file before actual compilation. +.PP +If you use the \fB\-E\fR option, nothing is done except preprocessing. +Some of these options make sense only together with \fB\-E\fR because +they cause the preprocessor output to be unsuitable for actual +compilation. +.IP "\fB\-Wp,\fR\fIoption\fR" 4 +.IX Item "-Wp,option" +You can use \fB\-Wp,\fR\fIoption\fR to bypass the compiler driver +and pass \fIoption\fR directly through to the preprocessor. If +\&\fIoption\fR contains commas, it is split into multiple options at the +commas. However, many options are modified, translated or interpreted +by the compiler driver before being passed to the preprocessor, and +\&\fB\-Wp\fR forcibly bypasses this phase. The preprocessor's direct +interface is undocumented and subject to change, so whenever possible +you should avoid using \fB\-Wp\fR and let the driver handle the +options instead. +.IP "\fB\-Xpreprocessor\fR \fIoption\fR" 4 +.IX Item "-Xpreprocessor option" +Pass \fIoption\fR as an option to the preprocessor. You can use this to +supply system-specific preprocessor options which \s-1GCC\s0 does not know how to +recognize. +.Sp +If you want to pass an option that takes an argument, you must use +\&\fB\-Xpreprocessor\fR twice, once for the option and once for the argument. +.IP "\fB\-D\fR \fIname\fR" 4 +.IX Item "-D name" +Predefine \fIname\fR as a macro, with definition \f(CW1\fR. +.IP "\fB\-D\fR \fIname\fR\fB=\fR\fIdefinition\fR" 4 +.IX Item "-D name=definition" +The contents of \fIdefinition\fR are tokenized and processed as if +they appeared during translation phase three in a \fB#define\fR +directive. In particular, the definition will be truncated by +embedded newline characters. +.Sp +If you are invoking the preprocessor from a shell or shell-like +program you may need to use the shell's quoting syntax to protect +characters such as spaces that have a meaning in the shell syntax. +.Sp +If you wish to define a function-like macro on the command line, write +its argument list with surrounding parentheses before the equals sign +(if any). Parentheses are meaningful to most shells, so you will need +to quote the option. With \fBsh\fR and \fBcsh\fR, +\&\fB\-D'\fR\fIname\fR\fB(\fR\fIargs...\fR\fB)=\fR\fIdefinition\fR\fB'\fR works. +.Sp +\&\fB\-D\fR and \fB\-U\fR options are processed in the order they +are given on the command line. All \fB\-imacros\fR \fIfile\fR and +\&\fB\-include\fR \fIfile\fR options are processed after all +\&\fB\-D\fR and \fB\-U\fR options. +.IP "\fB\-U\fR \fIname\fR" 4 +.IX Item "-U name" +Cancel any previous definition of \fIname\fR, either built in or +provided with a \fB\-D\fR option. +.IP "\fB\-undef\fR" 4 +.IX Item "-undef" +Do not predefine any system-specific or GCC-specific macros. The +standard predefined macros remain defined. +.IP "\fB\-I\fR \fIdir\fR" 4 +.IX Item "-I dir" +Add the directory \fIdir\fR to the list of directories to be searched +for header files. +Directories named by \fB\-I\fR are searched before the standard +system include directories. If the directory \fIdir\fR is a standard +system include directory, the option is ignored to ensure that the +default search order for system directories and the special treatment +of system headers are not defeated +\&. +If \fIdir\fR begins with \f(CW\*(C`=\*(C'\fR, then the \f(CW\*(C`=\*(C'\fR will be replaced +by the sysroot prefix; see \fB\-\-sysroot\fR and \fB\-isysroot\fR. +.IP "\fB\-o\fR \fIfile\fR" 4 +.IX Item "-o file" +Write output to \fIfile\fR. This is the same as specifying \fIfile\fR +as the second non-option argument to \fBcpp\fR. \fBgcc\fR has a +different interpretation of a second non-option argument, so you must +use \fB\-o\fR to specify the output file. +.IP "\fB\-Wall\fR" 4 +.IX Item "-Wall" +Turns on all optional warnings which are desirable for normal code. +At present this is \fB\-Wcomment\fR, \fB\-Wtrigraphs\fR, +\&\fB\-Wmultichar\fR and a warning about integer promotion causing a +change of sign in \f(CW\*(C`#if\*(C'\fR expressions. Note that many of the +preprocessor's warnings are on by default and have no options to +control them. +.IP "\fB\-Wcomment\fR" 4 +.IX Item "-Wcomment" +.PD 0 +.IP "\fB\-Wcomments\fR" 4 +.IX Item "-Wcomments" +.PD +Warn whenever a comment-start sequence \fB/*\fR appears in a \fB/*\fR +comment, or whenever a backslash-newline appears in a \fB//\fR comment. +(Both forms have the same effect.) +.IP "\fB\-Wtrigraphs\fR" 4 +.IX Item "-Wtrigraphs" +Most trigraphs in comments cannot affect the meaning of the program. +However, a trigraph that would form an escaped newline (\fB??/\fR at +the end of a line) can, by changing where the comment begins or ends. +Therefore, only trigraphs that would form escaped newlines produce +warnings inside a comment. +.Sp +This option is implied by \fB\-Wall\fR. If \fB\-Wall\fR is not +given, this option is still enabled unless trigraphs are enabled. To +get trigraph conversion without warnings, but get the other +\&\fB\-Wall\fR warnings, use \fB\-trigraphs \-Wall \-Wno\-trigraphs\fR. +.IP "\fB\-Wtraditional\fR" 4 +.IX Item "-Wtraditional" +Warn about certain constructs that behave differently in traditional and +\&\s-1ISO\s0 C. Also warn about \s-1ISO\s0 C constructs that have no traditional C +equivalent, and problematic constructs which should be avoided. +.IP "\fB\-Wundef\fR" 4 +.IX Item "-Wundef" +Warn whenever an identifier which is not a macro is encountered in an +\&\fB#if\fR directive, outside of \fBdefined\fR. Such identifiers are +replaced with zero. +.IP "\fB\-Wunused\-macros\fR" 4 +.IX Item "-Wunused-macros" +Warn about macros defined in the main file that are unused. A macro +is \fIused\fR if it is expanded or tested for existence at least once. +The preprocessor will also warn if the macro has not been used at the +time it is redefined or undefined. +.Sp +Built-in macros, macros defined on the command line, and macros +defined in include files are not warned about. +.Sp +\&\fINote:\fR If a macro is actually used, but only used in skipped +conditional blocks, then \s-1CPP\s0 will report it as unused. To avoid the +warning in such a case, you might improve the scope of the macro's +definition by, for example, moving it into the first skipped block. +Alternatively, you could provide a dummy use with something like: +.Sp +.Vb 2 +\& #if defined the_macro_causing_the_warning +\& #endif +.Ve +.IP "\fB\-Wendif\-labels\fR" 4 +.IX Item "-Wendif-labels" +Warn whenever an \fB#else\fR or an \fB#endif\fR are followed by text. +This usually happens in code of the form +.Sp +.Vb 5 +\& #if FOO +\& ... +\& #else FOO +\& ... +\& #endif FOO +.Ve +.Sp +The second and third \f(CW\*(C`FOO\*(C'\fR should be in comments, but often are not +in older programs. This warning is on by default. +.IP "\fB\-Werror\fR" 4 +.IX Item "-Werror" +Make all warnings into hard errors. Source code which triggers warnings +will be rejected. +.IP "\fB\-Wsystem\-headers\fR" 4 +.IX Item "-Wsystem-headers" +Issue warnings for code in system headers. These are normally unhelpful +in finding bugs in your own code, therefore suppressed. If you are +responsible for the system library, you may want to see them. +.IP "\fB\-w\fR" 4 +.IX Item "-w" +Suppress all warnings, including those which \s-1GNU\s0 \s-1CPP\s0 issues by default. +.IP "\fB\-pedantic\fR" 4 +.IX Item "-pedantic" +Issue all the mandatory diagnostics listed in the C standard. Some of +them are left out by default, since they trigger frequently on harmless +code. +.IP "\fB\-pedantic\-errors\fR" 4 +.IX Item "-pedantic-errors" +Issue all the mandatory diagnostics, and make all mandatory diagnostics +into errors. This includes mandatory diagnostics that \s-1GCC\s0 issues +without \fB\-pedantic\fR but treats as warnings. +.IP "\fB\-M\fR" 4 +.IX Item "-M" +Instead of outputting the result of preprocessing, output a rule +suitable for \fBmake\fR describing the dependencies of the main +source file. The preprocessor outputs one \fBmake\fR rule containing +the object file name for that source file, a colon, and the names of all +the included files, including those coming from \fB\-include\fR or +\&\fB\-imacros\fR command line options. +.Sp +Unless specified explicitly (with \fB\-MT\fR or \fB\-MQ\fR), the +object file name consists of the name of the source file with any +suffix replaced with object file suffix and with any leading directory +parts removed. If there are many included files then the rule is +split into several lines using \fB\e\fR\-newline. The rule has no +commands. +.Sp +This option does not suppress the preprocessor's debug output, such as +\&\fB\-dM\fR. To avoid mixing such debug output with the dependency +rules you should explicitly specify the dependency output file with +\&\fB\-MF\fR, or use an environment variable like +\&\fB\s-1DEPENDENCIES_OUTPUT\s0\fR. Debug output +will still be sent to the regular output stream as normal. +.Sp +Passing \fB\-M\fR to the driver implies \fB\-E\fR, and suppresses +warnings with an implicit \fB\-w\fR. +.IP "\fB\-MM\fR" 4 +.IX Item "-MM" +Like \fB\-M\fR but do not mention header files that are found in +system header directories, nor header files that are included, +directly or indirectly, from such a header. +.Sp +This implies that the choice of angle brackets or double quotes in an +\&\fB#include\fR directive does not in itself determine whether that +header will appear in \fB\-MM\fR dependency output. This is a +slight change in semantics from \s-1GCC\s0 versions 3.0 and earlier. +.IP "\fB\-MF\fR \fIfile\fR" 4 +.IX Item "-MF file" +When used with \fB\-M\fR or \fB\-MM\fR, specifies a +file to write the dependencies to. If no \fB\-MF\fR switch is given +the preprocessor sends the rules to the same place it would have sent +preprocessed output. +.Sp +When used with the driver options \fB\-MD\fR or \fB\-MMD\fR, +\&\fB\-MF\fR overrides the default dependency output file. +.IP "\fB\-MG\fR" 4 +.IX Item "-MG" +In conjunction with an option such as \fB\-M\fR requesting +dependency generation, \fB\-MG\fR assumes missing header files are +generated files and adds them to the dependency list without raising +an error. The dependency filename is taken directly from the +\&\f(CW\*(C`#include\*(C'\fR directive without prepending any path. \fB\-MG\fR +also suppresses preprocessed output, as a missing header file renders +this useless. +.Sp +This feature is used in automatic updating of makefiles. +.IP "\fB\-MP\fR" 4 +.IX Item "-MP" +This option instructs \s-1CPP\s0 to add a phony target for each dependency +other than the main file, causing each to depend on nothing. These +dummy rules work around errors \fBmake\fR gives if you remove header +files without updating the \fIMakefile\fR to match. +.Sp +This is typical output: +.Sp +.Vb 1 +\& test.o: test.c test.h +\& +\& test.h: +.Ve +.IP "\fB\-MT\fR \fItarget\fR" 4 +.IX Item "-MT target" +Change the target of the rule emitted by dependency generation. By +default \s-1CPP\s0 takes the name of the main input file, deletes any +directory components and any file suffix such as \fB.c\fR, and +appends the platform's usual object suffix. The result is the target. +.Sp +An \fB\-MT\fR option will set the target to be exactly the string you +specify. If you want multiple targets, you can specify them as a single +argument to \fB\-MT\fR, or use multiple \fB\-MT\fR options. +.Sp +For example, \fB\-MT\ '$(objpfx)foo.o'\fR might give +.Sp +.Vb 1 +\& $(objpfx)foo.o: foo.c +.Ve +.IP "\fB\-MQ\fR \fItarget\fR" 4 +.IX Item "-MQ target" +Same as \fB\-MT\fR, but it quotes any characters which are special to +Make. \fB\-MQ\ '$(objpfx)foo.o'\fR gives +.Sp +.Vb 1 +\& $$(objpfx)foo.o: foo.c +.Ve +.Sp +The default target is automatically quoted, as if it were given with +\&\fB\-MQ\fR. +.IP "\fB\-MD\fR" 4 +.IX Item "-MD" +\&\fB\-MD\fR is equivalent to \fB\-M \-MF\fR \fIfile\fR, except that +\&\fB\-E\fR is not implied. The driver determines \fIfile\fR based on +whether an \fB\-o\fR option is given. If it is, the driver uses its +argument but with a suffix of \fI.d\fR, otherwise it takes the name +of the input file, removes any directory components and suffix, and +applies a \fI.d\fR suffix. +.Sp +If \fB\-MD\fR is used in conjunction with \fB\-E\fR, any +\&\fB\-o\fR switch is understood to specify the dependency output file, but if used without \fB\-E\fR, each \fB\-o\fR +is understood to specify a target object file. +.Sp +Since \fB\-E\fR is not implied, \fB\-MD\fR can be used to generate +a dependency output file as a side-effect of the compilation process. +.IP "\fB\-MMD\fR" 4 +.IX Item "-MMD" +Like \fB\-MD\fR except mention only user header files, not system +header files. +.IP "\fB\-fpch\-deps\fR" 4 +.IX Item "-fpch-deps" +When using precompiled headers, this flag +will cause the dependency-output flags to also list the files from the +precompiled header's dependencies. If not specified only the +precompiled header would be listed and not the files that were used to +create it because those files are not consulted when a precompiled +header is used. +.IP "\fB\-fpch\-preprocess\fR" 4 +.IX Item "-fpch-preprocess" +This option allows use of a precompiled header together with \fB\-E\fR. It inserts a special \f(CW\*(C`#pragma\*(C'\fR, +\&\f(CW\*(C`#pragma GCC pch_preprocess "\f(CIfilename\f(CW"\*(C'\fR in the output to mark +the place where the precompiled header was found, and its \fIfilename\fR. +When \fB\-fpreprocessed\fR is in use, \s-1GCC\s0 recognizes this \f(CW\*(C`#pragma\*(C'\fR +and loads the \s-1PCH\s0. +.Sp +This option is off by default, because the resulting preprocessed output +is only really suitable as input to \s-1GCC\s0. It is switched on by +\&\fB\-save\-temps\fR. +.Sp +You should not write this \f(CW\*(C`#pragma\*(C'\fR in your own code, but it is +safe to edit the filename if the \s-1PCH\s0 file is available in a different +location. The filename may be absolute or it may be relative to \s-1GCC\s0's +current directory. +.IP "\fB\-x c\fR" 4 +.IX Item "-x c" +.PD 0 +.IP "\fB\-x c++\fR" 4 +.IX Item "-x c++" +.IP "\fB\-x objective-c\fR" 4 +.IX Item "-x objective-c" +.IP "\fB\-x assembler-with-cpp\fR" 4 +.IX Item "-x assembler-with-cpp" +.PD +Specify the source language: C, \*(C+, Objective-C, or assembly. This has +nothing to do with standards conformance or extensions; it merely +selects which base syntax to expect. If you give none of these options, +cpp will deduce the language from the extension of the source file: +\&\fB.c\fR, \fB.cc\fR, \fB.m\fR, or \fB.S\fR. Some other common +extensions for \*(C+ and assembly are also recognized. If cpp does not +recognize the extension, it will treat the file as C; this is the most +generic mode. +.Sp +\&\fINote:\fR Previous versions of cpp accepted a \fB\-lang\fR option +which selected both the language and the standards conformance level. +This option has been removed, because it conflicts with the \fB\-l\fR +option. +.IP "\fB\-std=\fR\fIstandard\fR" 4 +.IX Item "-std=standard" +.PD 0 +.IP "\fB\-ansi\fR" 4 +.IX Item "-ansi" +.PD +Specify the standard to which the code should conform. Currently \s-1CPP\s0 +knows about C and \*(C+ standards; others may be added in the future. +.Sp +\&\fIstandard\fR +may be one of: +.RS 4 +.ie n .IP """c90""" 4 +.el .IP "\f(CWc90\fR" 4 +.IX Item "c90" +.PD 0 +.ie n .IP """c89""" 4 +.el .IP "\f(CWc89\fR" 4 +.IX Item "c89" +.ie n .IP """iso9899:1990""" 4 +.el .IP "\f(CWiso9899:1990\fR" 4 +.IX Item "iso9899:1990" +.PD +The \s-1ISO\s0 C standard from 1990. \fBc90\fR is the customary shorthand for +this version of the standard. +.Sp +The \fB\-ansi\fR option is equivalent to \fB\-std=c90\fR. +.ie n .IP """iso9899:199409""" 4 +.el .IP "\f(CWiso9899:199409\fR" 4 +.IX Item "iso9899:199409" +The 1990 C standard, as amended in 1994. +.ie n .IP """iso9899:1999""" 4 +.el .IP "\f(CWiso9899:1999\fR" 4 +.IX Item "iso9899:1999" +.PD 0 +.ie n .IP """c99""" 4 +.el .IP "\f(CWc99\fR" 4 +.IX Item "c99" +.ie n .IP """iso9899:199x""" 4 +.el .IP "\f(CWiso9899:199x\fR" 4 +.IX Item "iso9899:199x" +.ie n .IP """c9x""" 4 +.el .IP "\f(CWc9x\fR" 4 +.IX Item "c9x" +.PD +The revised \s-1ISO\s0 C standard, published in December 1999. Before +publication, this was known as C9X. +.ie n .IP """c1x""" 4 +.el .IP "\f(CWc1x\fR" 4 +.IX Item "c1x" +The next version of the \s-1ISO\s0 C standard, still under development. +.ie n .IP """gnu90""" 4 +.el .IP "\f(CWgnu90\fR" 4 +.IX Item "gnu90" +.PD 0 +.ie n .IP """gnu89""" 4 +.el .IP "\f(CWgnu89\fR" 4 +.IX Item "gnu89" +.PD +The 1990 C standard plus \s-1GNU\s0 extensions. This is the default. +.ie n .IP """gnu99""" 4 +.el .IP "\f(CWgnu99\fR" 4 +.IX Item "gnu99" +.PD 0 +.ie n .IP """gnu9x""" 4 +.el .IP "\f(CWgnu9x\fR" 4 +.IX Item "gnu9x" +.PD +The 1999 C standard plus \s-1GNU\s0 extensions. +.ie n .IP """gnu1x""" 4 +.el .IP "\f(CWgnu1x\fR" 4 +.IX Item "gnu1x" +The next version of the \s-1ISO\s0 C standard, still under development, plus +\&\s-1GNU\s0 extensions. +.ie n .IP """c++98""" 4 +.el .IP "\f(CWc++98\fR" 4 +.IX Item "c++98" +The 1998 \s-1ISO\s0 \*(C+ standard plus amendments. +.ie n .IP """gnu++98""" 4 +.el .IP "\f(CWgnu++98\fR" 4 +.IX Item "gnu++98" +The same as \fB\-std=c++98\fR plus \s-1GNU\s0 extensions. This is the +default for \*(C+ code. +.RE +.RS 4 +.RE +.IP "\fB\-I\-\fR" 4 +.IX Item "-I-" +Split the include path. Any directories specified with \fB\-I\fR +options before \fB\-I\-\fR are searched only for headers requested with +\&\f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR; they are not searched for +\&\f(CW\*(C`#include\ <\f(CIfile\f(CW>\*(C'\fR. If additional directories are +specified with \fB\-I\fR options after the \fB\-I\-\fR, those +directories are searched for all \fB#include\fR directives. +.Sp +In addition, \fB\-I\-\fR inhibits the use of the directory of the current +file directory as the first search directory for \f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR. +This option has been deprecated. +.IP "\fB\-nostdinc\fR" 4 +.IX Item "-nostdinc" +Do not search the standard system directories for header files. +Only the directories you have specified with \fB\-I\fR options +(and the directory of the current file, if appropriate) are searched. +.IP "\fB\-nostdinc++\fR" 4 +.IX Item "-nostdinc++" +Do not search for header files in the \*(C+\-specific standard directories, +but do still search the other standard directories. (This option is +used when building the \*(C+ library.) +.IP "\fB\-include\fR \fIfile\fR" 4 +.IX Item "-include file" +Process \fIfile\fR as if \f(CW\*(C`#include "file"\*(C'\fR appeared as the first +line of the primary source file. However, the first directory searched +for \fIfile\fR is the preprocessor's working directory \fIinstead of\fR +the directory containing the main source file. If not found there, it +is searched for in the remainder of the \f(CW\*(C`#include "..."\*(C'\fR search +chain as normal. +.Sp +If multiple \fB\-include\fR options are given, the files are included +in the order they appear on the command line. +.IP "\fB\-imacros\fR \fIfile\fR" 4 +.IX Item "-imacros file" +Exactly like \fB\-include\fR, except that any output produced by +scanning \fIfile\fR is thrown away. Macros it defines remain defined. +This allows you to acquire all the macros from a header without also +processing its declarations. +.Sp +All files specified by \fB\-imacros\fR are processed before all files +specified by \fB\-include\fR. +.IP "\fB\-idirafter\fR \fIdir\fR" 4 +.IX Item "-idirafter dir" +Search \fIdir\fR for header files, but do it \fIafter\fR all +directories specified with \fB\-I\fR and the standard system directories +have been exhausted. \fIdir\fR is treated as a system include directory. +If \fIdir\fR begins with \f(CW\*(C`=\*(C'\fR, then the \f(CW\*(C`=\*(C'\fR will be replaced +by the sysroot prefix; see \fB\-\-sysroot\fR and \fB\-isysroot\fR. +.IP "\fB\-iprefix\fR \fIprefix\fR" 4 +.IX Item "-iprefix prefix" +Specify \fIprefix\fR as the prefix for subsequent \fB\-iwithprefix\fR +options. If the prefix represents a directory, you should include the +final \fB/\fR. +.IP "\fB\-iwithprefix\fR \fIdir\fR" 4 +.IX Item "-iwithprefix dir" +.PD 0 +.IP "\fB\-iwithprefixbefore\fR \fIdir\fR" 4 +.IX Item "-iwithprefixbefore dir" +.PD +Append \fIdir\fR to the prefix specified previously with +\&\fB\-iprefix\fR, and add the resulting directory to the include search +path. \fB\-iwithprefixbefore\fR puts it in the same place \fB\-I\fR +would; \fB\-iwithprefix\fR puts it where \fB\-idirafter\fR would. +.IP "\fB\-isysroot\fR \fIdir\fR" 4 +.IX Item "-isysroot dir" +This option is like the \fB\-\-sysroot\fR option, but applies only to +header files (except for Darwin targets, where it applies to both header +files and libraries). See the \fB\-\-sysroot\fR option for more +information. +.IP "\fB\-imultilib\fR \fIdir\fR" 4 +.IX Item "-imultilib dir" +Use \fIdir\fR as a subdirectory of the directory containing +target-specific \*(C+ headers. +.IP "\fB\-isystem\fR \fIdir\fR" 4 +.IX Item "-isystem dir" +Search \fIdir\fR for header files, after all directories specified by +\&\fB\-I\fR but before the standard system directories. Mark it +as a system directory, so that it gets the same special treatment as +is applied to the standard system directories. +If \fIdir\fR begins with \f(CW\*(C`=\*(C'\fR, then the \f(CW\*(C`=\*(C'\fR will be replaced +by the sysroot prefix; see \fB\-\-sysroot\fR and \fB\-isysroot\fR. +.IP "\fB\-iquote\fR \fIdir\fR" 4 +.IX Item "-iquote dir" +Search \fIdir\fR only for header files requested with +\&\f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR; they are not searched for +\&\f(CW\*(C`#include\ <\f(CIfile\f(CW>\*(C'\fR, before all directories specified by +\&\fB\-I\fR and before the standard system directories. +If \fIdir\fR begins with \f(CW\*(C`=\*(C'\fR, then the \f(CW\*(C`=\*(C'\fR will be replaced +by the sysroot prefix; see \fB\-\-sysroot\fR and \fB\-isysroot\fR. +.IP "\fB\-fdirectives\-only\fR" 4 +.IX Item "-fdirectives-only" +When preprocessing, handle directives, but do not expand macros. +.Sp +The option's behavior depends on the \fB\-E\fR and \fB\-fpreprocessed\fR +options. +.Sp +With \fB\-E\fR, preprocessing is limited to the handling of directives +such as \f(CW\*(C`#define\*(C'\fR, \f(CW\*(C`#ifdef\*(C'\fR, and \f(CW\*(C`#error\*(C'\fR. Other +preprocessor operations, such as macro expansion and trigraph +conversion are not performed. In addition, the \fB\-dD\fR option is +implicitly enabled. +.Sp +With \fB\-fpreprocessed\fR, predefinition of command line and most +builtin macros is disabled. Macros such as \f(CW\*(C`_\|_LINE_\|_\*(C'\fR, which are +contextually dependent, are handled normally. This enables compilation of +files previously preprocessed with \f(CW\*(C`\-E \-fdirectives\-only\*(C'\fR. +.Sp +With both \fB\-E\fR and \fB\-fpreprocessed\fR, the rules for +\&\fB\-fpreprocessed\fR take precedence. This enables full preprocessing of +files previously preprocessed with \f(CW\*(C`\-E \-fdirectives\-only\*(C'\fR. +.IP "\fB\-fdollars\-in\-identifiers\fR" 4 +.IX Item "-fdollars-in-identifiers" +Accept \fB$\fR in identifiers. +.IP "\fB\-fextended\-identifiers\fR" 4 +.IX Item "-fextended-identifiers" +Accept universal character names in identifiers. This option is +experimental; in a future version of \s-1GCC\s0, it will be enabled by +default for C99 and \*(C+. +.IP "\fB\-fpreprocessed\fR" 4 +.IX Item "-fpreprocessed" +Indicate to the preprocessor that the input file has already been +preprocessed. This suppresses things like macro expansion, trigraph +conversion, escaped newline splicing, and processing of most directives. +The preprocessor still recognizes and removes comments, so that you can +pass a file preprocessed with \fB\-C\fR to the compiler without +problems. In this mode the integrated preprocessor is little more than +a tokenizer for the front ends. +.Sp +\&\fB\-fpreprocessed\fR is implicit if the input file has one of the +extensions \fB.i\fR, \fB.ii\fR or \fB.mi\fR. These are the +extensions that \s-1GCC\s0 uses for preprocessed files created by +\&\fB\-save\-temps\fR. +.IP "\fB\-ftabstop=\fR\fIwidth\fR" 4 +.IX Item "-ftabstop=width" +Set the distance between tab stops. This helps the preprocessor report +correct column numbers in warnings or errors, even if tabs appear on the +line. If the value is less than 1 or greater than 100, the option is +ignored. The default is 8. +.IP "\fB\-fexec\-charset=\fR\fIcharset\fR" 4 +.IX Item "-fexec-charset=charset" +Set the execution character set, used for string and character +constants. The default is \s-1UTF\-8\s0. \fIcharset\fR can be any encoding +supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine. +.IP "\fB\-fwide\-exec\-charset=\fR\fIcharset\fR" 4 +.IX Item "-fwide-exec-charset=charset" +Set the wide execution character set, used for wide string and +character constants. The default is \s-1UTF\-32\s0 or \s-1UTF\-16\s0, whichever +corresponds to the width of \f(CW\*(C`wchar_t\*(C'\fR. As with +\&\fB\-fexec\-charset\fR, \fIcharset\fR can be any encoding supported +by the system's \f(CW\*(C`iconv\*(C'\fR library routine; however, you will have +problems with encodings that do not fit exactly in \f(CW\*(C`wchar_t\*(C'\fR. +.IP "\fB\-finput\-charset=\fR\fIcharset\fR" 4 +.IX Item "-finput-charset=charset" +Set the input character set, used for translation from the character +set of the input file to the source character set used by \s-1GCC\s0. If the +locale does not specify, or \s-1GCC\s0 cannot get this information from the +locale, the default is \s-1UTF\-8\s0. This can be overridden by either the locale +or this command line option. Currently the command line option takes +precedence if there's a conflict. \fIcharset\fR can be any encoding +supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine. +.IP "\fB\-fworking\-directory\fR" 4 +.IX Item "-fworking-directory" +Enable generation of linemarkers in the preprocessor output that will +let the compiler know the current working directory at the time of +preprocessing. When this option is enabled, the preprocessor will +emit, after the initial linemarker, a second linemarker with the +current working directory followed by two slashes. \s-1GCC\s0 will use this +directory, when it's present in the preprocessed input, as the +directory emitted as the current working directory in some debugging +information formats. This option is implicitly enabled if debugging +information is enabled, but this can be inhibited with the negated +form \fB\-fno\-working\-directory\fR. If the \fB\-P\fR flag is +present in the command line, this option has no effect, since no +\&\f(CW\*(C`#line\*(C'\fR directives are emitted whatsoever. +.IP "\fB\-fno\-show\-column\fR" 4 +.IX Item "-fno-show-column" +Do not print column numbers in diagnostics. This may be necessary if +diagnostics are being scanned by a program that does not understand the +column numbers, such as \fBdejagnu\fR. +.IP "\fB\-A\fR \fIpredicate\fR\fB=\fR\fIanswer\fR" 4 +.IX Item "-A predicate=answer" +Make an assertion with the predicate \fIpredicate\fR and answer +\&\fIanswer\fR. This form is preferred to the older form \fB\-A\fR +\&\fIpredicate\fR\fB(\fR\fIanswer\fR\fB)\fR, which is still supported, because +it does not use shell special characters. +.IP "\fB\-A \-\fR\fIpredicate\fR\fB=\fR\fIanswer\fR" 4 +.IX Item "-A -predicate=answer" +Cancel an assertion with the predicate \fIpredicate\fR and answer +\&\fIanswer\fR. +.IP "\fB\-dCHARS\fR" 4 +.IX Item "-dCHARS" +\&\fI\s-1CHARS\s0\fR is a sequence of one or more of the following characters, +and must not be preceded by a space. Other characters are interpreted +by the compiler proper, or reserved for future versions of \s-1GCC\s0, and so +are silently ignored. If you specify characters whose behavior +conflicts, the result is undefined. +.RS 4 +.IP "\fBM\fR" 4 +.IX Item "M" +Instead of the normal output, generate a list of \fB#define\fR +directives for all the macros defined during the execution of the +preprocessor, including predefined macros. This gives you a way of +finding out what is predefined in your version of the preprocessor. +Assuming you have no file \fIfoo.h\fR, the command +.Sp +.Vb 1 +\& touch foo.h; cpp \-dM foo.h +.Ve +.Sp +will show all the predefined macros. +.Sp +If you use \fB\-dM\fR without the \fB\-E\fR option, \fB\-dM\fR is +interpreted as a synonym for \fB\-fdump\-rtl\-mach\fR. +.IP "\fBD\fR" 4 +.IX Item "D" +Like \fBM\fR except in two respects: it does \fInot\fR include the +predefined macros, and it outputs \fIboth\fR the \fB#define\fR +directives and the result of preprocessing. Both kinds of output go to +the standard output file. +.IP "\fBN\fR" 4 +.IX Item "N" +Like \fBD\fR, but emit only the macro names, not their expansions. +.IP "\fBI\fR" 4 +.IX Item "I" +Output \fB#include\fR directives in addition to the result of +preprocessing. +.IP "\fBU\fR" 4 +.IX Item "U" +Like \fBD\fR except that only macros that are expanded, or whose +definedness is tested in preprocessor directives, are output; the +output is delayed until the use or test of the macro; and +\&\fB#undef\fR directives are also output for macros tested but +undefined at the time. +.RE +.RS 4 +.RE +.IP "\fB\-P\fR" 4 +.IX Item "-P" +Inhibit generation of linemarkers in the output from the preprocessor. +This might be useful when running the preprocessor on something that is +not C code, and will be sent to a program which might be confused by the +linemarkers. +.IP "\fB\-C\fR" 4 +.IX Item "-C" +Do not discard comments. All comments are passed through to the output +file, except for comments in processed directives, which are deleted +along with the directive. +.Sp +You should be prepared for side effects when using \fB\-C\fR; it +causes the preprocessor to treat comments as tokens in their own right. +For example, comments appearing at the start of what would be a +directive line have the effect of turning that line into an ordinary +source line, since the first token on the line is no longer a \fB#\fR. +.IP "\fB\-CC\fR" 4 +.IX Item "-CC" +Do not discard comments, including during macro expansion. This is +like \fB\-C\fR, except that comments contained within macros are +also passed through to the output file where the macro is expanded. +.Sp +In addition to the side-effects of the \fB\-C\fR option, the +\&\fB\-CC\fR option causes all \*(C+\-style comments inside a macro +to be converted to C\-style comments. This is to prevent later use +of that macro from inadvertently commenting out the remainder of +the source line. +.Sp +The \fB\-CC\fR option is generally used to support lint comments. +.IP "\fB\-traditional\-cpp\fR" 4 +.IX Item "-traditional-cpp" +Try to imitate the behavior of old-fashioned C preprocessors, as +opposed to \s-1ISO\s0 C preprocessors. +.IP "\fB\-trigraphs\fR" 4 +.IX Item "-trigraphs" +Process trigraph sequences. +These are three-character sequences, all starting with \fB??\fR, that +are defined by \s-1ISO\s0 C to stand for single characters. For example, +\&\fB??/\fR stands for \fB\e\fR, so \fB'??/n'\fR is a character +constant for a newline. By default, \s-1GCC\s0 ignores trigraphs, but in +standard-conforming modes it converts them. See the \fB\-std\fR and +\&\fB\-ansi\fR options. +.Sp +The nine trigraphs and their replacements are +.Sp +.Vb 2 +\& Trigraph: ??( ??) ??< ??> ??= ??/ ??\*(Aq ??! ??\- +\& Replacement: [ ] { } # \e ^ | ~ +.Ve +.IP "\fB\-remap\fR" 4 +.IX Item "-remap" +Enable special code to work around file systems which only permit very +short file names, such as MS-DOS. +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +.PD 0 +.IP "\fB\-\-target\-help\fR" 4 +.IX Item "--target-help" +.PD +Print text describing all the command line options instead of +preprocessing anything. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +Verbose mode. Print out \s-1GNU\s0 \s-1CPP\s0's version number at the beginning of +execution, and report the final form of the include path. +.IP "\fB\-H\fR" 4 +.IX Item "-H" +Print the name of each header file used, in addition to other normal +activities. Each name is indented to show how deep in the +\&\fB#include\fR stack it is. Precompiled header files are also +printed, even if they are found to be invalid; an invalid precompiled +header file is printed with \fB...x\fR and a valid one with \fB...!\fR . +.IP "\fB\-version\fR" 4 +.IX Item "-version" +.PD 0 +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +.PD +Print out \s-1GNU\s0 \s-1CPP\s0's version number. With one dash, proceed to +preprocess as normal. With two dashes, exit immediately. +.SS "Passing Options to the Assembler" +.IX Subsection "Passing Options to the Assembler" +You can pass options to the assembler. +.IP "\fB\-Wa,\fR\fIoption\fR" 4 +.IX Item "-Wa,option" +Pass \fIoption\fR as an option to the assembler. If \fIoption\fR +contains commas, it is split into multiple options at the commas. +.IP "\fB\-Xassembler\fR \fIoption\fR" 4 +.IX Item "-Xassembler option" +Pass \fIoption\fR as an option to the assembler. You can use this to +supply system-specific assembler options which \s-1GCC\s0 does not know how to +recognize. +.Sp +If you want to pass an option that takes an argument, you must use +\&\fB\-Xassembler\fR twice, once for the option and once for the argument. +.IP "\fBprofile-generate-sampling-rate\fR" 4 +.IX Item "profile-generate-sampling-rate" +Set the sampling rate with \fB\-fprofile\-generate\-sampling\fR. +.SS "Options for Linking" +.IX Subsection "Options for Linking" +These options come into play when the compiler links object files into +an executable output file. They are meaningless if the compiler is +not doing a link step. +.IP "\fIobject-file-name\fR" 4 +.IX Item "object-file-name" +A file name that does not end in a special recognized suffix is +considered to name an object file or library. (Object files are +distinguished from libraries by the linker according to the file +contents.) If linking is done, these object files are used as input +to the linker. +.IP "\fB\-c\fR" 4 +.IX Item "-c" +.PD 0 +.IP "\fB\-S\fR" 4 +.IX Item "-S" +.IP "\fB\-E\fR" 4 +.IX Item "-E" +.PD +If any of these options is used, then the linker is not run, and +object file names should not be used as arguments. +.IP "\fB\-l\fR\fIlibrary\fR" 4 +.IX Item "-llibrary" +.PD 0 +.IP "\fB\-l\fR \fIlibrary\fR" 4 +.IX Item "-l library" +.PD +Search the library named \fIlibrary\fR when linking. (The second +alternative with the library as a separate argument is only for +\&\s-1POSIX\s0 compliance and is not recommended.) +.Sp +It makes a difference where in the command you write this option; the +linker searches and processes libraries and object files in the order they +are specified. Thus, \fBfoo.o \-lz bar.o\fR searches library \fBz\fR +after file \fIfoo.o\fR but before \fIbar.o\fR. If \fIbar.o\fR refers +to functions in \fBz\fR, those functions may not be loaded. +.Sp +The linker searches a standard list of directories for the library, +which is actually a file named \fIlib\fIlibrary\fI.a\fR. The linker +then uses this file as if it had been specified precisely by name. +.Sp +The directories searched include several standard system directories +plus any that you specify with \fB\-L\fR. +.Sp +Normally the files found this way are library files\-\-\-archive files +whose members are object files. The linker handles an archive file by +scanning through it for members which define symbols that have so far +been referenced but not defined. But if the file that is found is an +ordinary object file, it is linked in the usual fashion. The only +difference between using an \fB\-l\fR option and specifying a file name +is that \fB\-l\fR surrounds \fIlibrary\fR with \fBlib\fR and \fB.a\fR +and searches several directories. +.IP "\fB\-lobjc\fR" 4 +.IX Item "-lobjc" +You need this special case of the \fB\-l\fR option in order to +link an Objective-C or Objective\-\*(C+ program. +.IP "\fB\-nostartfiles\fR" 4 +.IX Item "-nostartfiles" +Do not use the standard system startup files when linking. +The standard system libraries are used normally, unless \fB\-nostdlib\fR +or \fB\-nodefaultlibs\fR is used. +.IP "\fB\-nodefaultlibs\fR" 4 +.IX Item "-nodefaultlibs" +Do not use the standard system libraries when linking. +Only the libraries you specify will be passed to the linker, options +specifying linkage of the system libraries, such as \f(CW\*(C`\-static\-libgcc\*(C'\fR +or \f(CW\*(C`\-shared\-libgcc\*(C'\fR, will be ignored. +The standard startup files are used normally, unless \fB\-nostartfiles\fR +is used. The compiler may generate calls to \f(CW\*(C`memcmp\*(C'\fR, +\&\f(CW\*(C`memset\*(C'\fR, \f(CW\*(C`memcpy\*(C'\fR and \f(CW\*(C`memmove\*(C'\fR. +These entries are usually resolved by entries in +libc. These entry points should be supplied through some other +mechanism when this option is specified. +.IP "\fB\-nostdlib\fR" 4 +.IX Item "-nostdlib" +Do not use the standard system startup files or libraries when linking. +No startup files and only the libraries you specify will be passed to +the linker, options specifying linkage of the system libraries, such as +\&\f(CW\*(C`\-static\-libgcc\*(C'\fR or \f(CW\*(C`\-shared\-libgcc\*(C'\fR, will be ignored. +The compiler may generate calls to \f(CW\*(C`memcmp\*(C'\fR, \f(CW\*(C`memset\*(C'\fR, +\&\f(CW\*(C`memcpy\*(C'\fR and \f(CW\*(C`memmove\*(C'\fR. +These entries are usually resolved by entries in +libc. These entry points should be supplied through some other +mechanism when this option is specified. +.Sp +One of the standard libraries bypassed by \fB\-nostdlib\fR and +\&\fB\-nodefaultlibs\fR is \fIlibgcc.a\fR, a library of internal subroutines +that \s-1GCC\s0 uses to overcome shortcomings of particular machines, or special +needs for some languages. +.Sp +In most cases, you need \fIlibgcc.a\fR even when you want to avoid +other standard libraries. In other words, when you specify \fB\-nostdlib\fR +or \fB\-nodefaultlibs\fR you should usually specify \fB\-lgcc\fR as well. +This ensures that you have no unresolved references to internal \s-1GCC\s0 +library subroutines. (For example, \fB_\|_main\fR, used to ensure \*(C+ +constructors will be called.) +.IP "\fB\-pie\fR" 4 +.IX Item "-pie" +Produce a position independent executable on targets which support it. +For predictable results, you must also specify the same set of options +that were used to generate code (\fB\-fpie\fR, \fB\-fPIE\fR, +or model suboptions) when you specify this option. +.IP "\fB\-rdynamic\fR" 4 +.IX Item "-rdynamic" +Pass the flag \fB\-export\-dynamic\fR to the \s-1ELF\s0 linker, on targets +that support it. This instructs the linker to add all symbols, not +only used ones, to the dynamic symbol table. This option is needed +for some uses of \f(CW\*(C`dlopen\*(C'\fR or to allow obtaining backtraces +from within a program. +.IP "\fB\-s\fR" 4 +.IX Item "-s" +Remove all symbol table and relocation information from the executable. +.IP "\fB\-static\fR" 4 +.IX Item "-static" +On systems that support dynamic linking, this prevents linking with the shared +libraries. On other systems, this option has no effect. +.IP "\fB\-shared\fR" 4 +.IX Item "-shared" +Produce a shared object which can then be linked with other objects to +form an executable. Not all systems support this option. For predictable +results, you must also specify the same set of options that were used to +generate code (\fB\-fpic\fR, \fB\-fPIC\fR, or model suboptions) +when you specify this option.[1] +.IP "\fB\-shared\-libgcc\fR" 4 +.IX Item "-shared-libgcc" +.PD 0 +.IP "\fB\-static\-libgcc\fR" 4 +.IX Item "-static-libgcc" +.PD +On systems that provide \fIlibgcc\fR as a shared library, these options +force the use of either the shared or static version respectively. +If no shared version of \fIlibgcc\fR was built when the compiler was +configured, these options have no effect. +.Sp +There are several situations in which an application should use the +shared \fIlibgcc\fR instead of the static version. The most common +of these is when the application wishes to throw and catch exceptions +across different shared libraries. In that case, each of the libraries +as well as the application itself should use the shared \fIlibgcc\fR. +.Sp +Therefore, the G++ and \s-1GCJ\s0 drivers automatically add +\&\fB\-shared\-libgcc\fR whenever you build a shared library or a main +executable, because \*(C+ and Java programs typically use exceptions, so +this is the right thing to do. +.Sp +If, instead, you use the \s-1GCC\s0 driver to create shared libraries, you may +find that they will not always be linked with the shared \fIlibgcc\fR. +If \s-1GCC\s0 finds, at its configuration time, that you have a non-GNU linker +or a \s-1GNU\s0 linker that does not support option \fB\-\-eh\-frame\-hdr\fR, +it will link the shared version of \fIlibgcc\fR into shared libraries +by default. Otherwise, it will take advantage of the linker and optimize +away the linking with the shared version of \fIlibgcc\fR, linking with +the static version of libgcc by default. This allows exceptions to +propagate through such shared libraries, without incurring relocation +costs at library load time. +.Sp +However, if a library or main executable is supposed to throw or catch +exceptions, you must link it using the G++ or \s-1GCJ\s0 driver, as appropriate +for the languages used in the program, or using the option +\&\fB\-shared\-libgcc\fR, such that it is linked with the shared +\&\fIlibgcc\fR. +.IP "\fB\-static\-libstdc++\fR" 4 +.IX Item "-static-libstdc++" +When the \fBg++\fR program is used to link a \*(C+ program, it will +normally automatically link against \fBlibstdc++\fR. If +\&\fIlibstdc++\fR is available as a shared library, and the +\&\fB\-static\fR option is not used, then this will link against the +shared version of \fIlibstdc++\fR. That is normally fine. However, it +is sometimes useful to freeze the version of \fIlibstdc++\fR used by +the program without going all the way to a fully static link. The +\&\fB\-static\-libstdc++\fR option directs the \fBg++\fR driver to +link \fIlibstdc++\fR statically, without necessarily linking other +libraries statically. +.IP "\fB\-symbolic\fR" 4 +.IX Item "-symbolic" +Bind references to global symbols when building a shared object. Warn +about any unresolved references (unless overridden by the link editor +option \fB\-Xlinker \-z \-Xlinker defs\fR). Only a few systems support +this option. +.IP "\fB\-T\fR \fIscript\fR" 4 +.IX Item "-T script" +Use \fIscript\fR as the linker script. This option is supported by most +systems using the \s-1GNU\s0 linker. On some targets, such as bare-board +targets without an operating system, the \fB\-T\fR option may be required +when linking to avoid references to undefined symbols. +.IP "\fB\-Xlinker\fR \fIoption\fR" 4 +.IX Item "-Xlinker option" +Pass \fIoption\fR as an option to the linker. You can use this to +supply system-specific linker options which \s-1GCC\s0 does not know how to +recognize. +.Sp +If you want to pass an option that takes a separate argument, you must use +\&\fB\-Xlinker\fR twice, once for the option and once for the argument. +For example, to pass \fB\-assert definitions\fR, you must write +\&\fB\-Xlinker \-assert \-Xlinker definitions\fR. It does not work to write +\&\fB\-Xlinker \*(L"\-assert definitions\*(R"\fR, because this passes the entire +string as a single argument, which is not what the linker expects. +.Sp +When using the \s-1GNU\s0 linker, it is usually more convenient to pass +arguments to linker options using the \fIoption\fR\fB=\fR\fIvalue\fR +syntax than as separate arguments. For example, you can specify +\&\fB\-Xlinker \-Map=output.map\fR rather than +\&\fB\-Xlinker \-Map \-Xlinker output.map\fR. Other linkers may not support +this syntax for command-line options. +.IP "\fB\-Wl,\fR\fIoption\fR" 4 +.IX Item "-Wl,option" +Pass \fIoption\fR as an option to the linker. If \fIoption\fR contains +commas, it is split into multiple options at the commas. You can use this +syntax to pass an argument to the option. +For example, \fB\-Wl,\-Map,output.map\fR passes \fB\-Map output.map\fR to the +linker. When using the \s-1GNU\s0 linker, you can also get the same effect with +\&\fB\-Wl,\-Map=output.map\fR. +.IP "\fB\-u\fR \fIsymbol\fR" 4 +.IX Item "-u symbol" +Pretend the symbol \fIsymbol\fR is undefined, to force linking of +library modules to define it. You can use \fB\-u\fR multiple times with +different symbols to force loading of additional library modules. +.SS "Options for Directory Search" +.IX Subsection "Options for Directory Search" +These options specify directories to search for header files, for +libraries and for parts of the compiler: +.IP "\fB\-I\fR\fIdir\fR" 4 +.IX Item "-Idir" +Add the directory \fIdir\fR to the head of the list of directories to be +searched for header files. This can be used to override a system header +file, substituting your own version, since these directories are +searched before the system header file directories. However, you should +not use this option to add directories that contain vendor-supplied +system header files (use \fB\-isystem\fR for that). If you use more than +one \fB\-I\fR option, the directories are scanned in left-to-right +order; the standard system directories come after. +.Sp +If a standard system include directory, or a directory specified with +\&\fB\-isystem\fR, is also specified with \fB\-I\fR, the \fB\-I\fR +option will be ignored. The directory will still be searched but as a +system directory at its normal position in the system include chain. +This is to ensure that \s-1GCC\s0's procedure to fix buggy system headers and +the ordering for the include_next directive are not inadvertently changed. +If you really need to change the search order for system directories, +use the \fB\-nostdinc\fR and/or \fB\-isystem\fR options. +.IP "\fB\-iplugindir=\fR\fIdir\fR" 4 +.IX Item "-iplugindir=dir" +Set the directory to search for plugins which are passed +by \fB\-fplugin=\fR\fIname\fR instead of +\&\fB\-fplugin=\fR\fIpath\fR\fB/\fR\fIname\fR\fB.so\fR. This option is not meant +to be used by the user, but only passed by the driver. +.IP "\fB\-iquote\fR\fIdir\fR" 4 +.IX Item "-iquotedir" +Add the directory \fIdir\fR to the head of the list of directories to +be searched for header files only for the case of \fB#include +"\fR\fIfile\fR\fB"\fR; they are not searched for \fB#include <\fR\fIfile\fR\fB>\fR, +otherwise just like \fB\-I\fR. +.IP "\fB\-L\fR\fIdir\fR" 4 +.IX Item "-Ldir" +Add directory \fIdir\fR to the list of directories to be searched +for \fB\-l\fR. +.IP "\fB\-B\fR\fIprefix\fR" 4 +.IX Item "-Bprefix" +This option specifies where to find the executables, libraries, +include files, and data files of the compiler itself. +.Sp +The compiler driver program runs one or more of the subprograms +\&\fIcpp\fR, \fIcc1\fR, \fIas\fR and \fIld\fR. It tries +\&\fIprefix\fR as a prefix for each program it tries to run, both with and +without \fImachine\fR\fB/\fR\fIversion\fR\fB/\fR. +.Sp +For each subprogram to be run, the compiler driver first tries the +\&\fB\-B\fR prefix, if any. If that name is not found, or if \fB\-B\fR +was not specified, the driver tries two standard prefixes, which are +\&\fI/usr/lib/gcc/\fR and \fI/usr/local/lib/gcc/\fR. If neither of +those results in a file name that is found, the unmodified program +name is searched for using the directories specified in your +\&\fB\s-1PATH\s0\fR environment variable. +.Sp +The compiler will check to see if the path provided by the \fB\-B\fR +refers to a directory, and if necessary it will add a directory +separator character at the end of the path. +.Sp +\&\fB\-B\fR prefixes that effectively specify directory names also apply +to libraries in the linker, because the compiler translates these +options into \fB\-L\fR options for the linker. They also apply to +includes files in the preprocessor, because the compiler translates these +options into \fB\-isystem\fR options for the preprocessor. In this case, +the compiler appends \fBinclude\fR to the prefix. +.Sp +The run-time support file \fIlibgcc.a\fR can also be searched for using +the \fB\-B\fR prefix, if needed. If it is not found there, the two +standard prefixes above are tried, and that is all. The file is left +out of the link if it is not found by those means. +.Sp +Another way to specify a prefix much like the \fB\-B\fR prefix is to use +the environment variable \fB\s-1GCC_EXEC_PREFIX\s0\fR. +.Sp +As a special kludge, if the path provided by \fB\-B\fR is +\&\fI[dir/]stage\fIN\fI/\fR, where \fIN\fR is a number in the range 0 to +9, then it will be replaced by \fI[dir/]include\fR. This is to help +with boot-strapping the compiler. +.IP "\fB\-specs=\fR\fIfile\fR" 4 +.IX Item "-specs=file" +Process \fIfile\fR after the compiler reads in the standard \fIspecs\fR +file, in order to override the defaults that the \fIgcc\fR driver +program uses when determining what switches to pass to \fIcc1\fR, +\&\fIcc1plus\fR, \fIas\fR, \fIld\fR, etc. More than one +\&\fB\-specs=\fR\fIfile\fR can be specified on the command line, and they +are processed in order, from left to right. +.IP "\fB\-\-sysroot=\fR\fIdir\fR" 4 +.IX Item "--sysroot=dir" +Use \fIdir\fR as the logical root directory for headers and libraries. +For example, if the compiler would normally search for headers in +\&\fI/usr/include\fR and libraries in \fI/usr/lib\fR, it will instead +search \fI\fIdir\fI/usr/include\fR and \fI\fIdir\fI/usr/lib\fR. +.Sp +If you use both this option and the \fB\-isysroot\fR option, then +the \fB\-\-sysroot\fR option will apply to libraries, but the +\&\fB\-isysroot\fR option will apply to header files. +.Sp +The \s-1GNU\s0 linker (beginning with version 2.16) has the necessary support +for this option. If your linker does not support this option, the +header file aspect of \fB\-\-sysroot\fR will still work, but the +library aspect will not. +.IP "\fB\-I\-\fR" 4 +.IX Item "-I-" +This option has been deprecated. Please use \fB\-iquote\fR instead for +\&\fB\-I\fR directories before the \fB\-I\-\fR and remove the \fB\-I\-\fR. +Any directories you specify with \fB\-I\fR options before the \fB\-I\-\fR +option are searched only for the case of \fB#include "\fR\fIfile\fR\fB"\fR; +they are not searched for \fB#include <\fR\fIfile\fR\fB>\fR. +.Sp +If additional directories are specified with \fB\-I\fR options after +the \fB\-I\-\fR, these directories are searched for all \fB#include\fR +directives. (Ordinarily \fIall\fR \fB\-I\fR directories are used +this way.) +.Sp +In addition, the \fB\-I\-\fR option inhibits the use of the current +directory (where the current input file came from) as the first search +directory for \fB#include "\fR\fIfile\fR\fB"\fR. There is no way to +override this effect of \fB\-I\-\fR. With \fB\-I.\fR you can specify +searching the directory which was current when the compiler was +invoked. That is not exactly the same as what the preprocessor does +by default, but it is often satisfactory. +.Sp +\&\fB\-I\-\fR does not inhibit the use of the standard system directories +for header files. Thus, \fB\-I\-\fR and \fB\-nostdinc\fR are +independent. +.SS "Specifying Target Machine and Compiler Version" +.IX Subsection "Specifying Target Machine and Compiler Version" +The usual way to run \s-1GCC\s0 is to run the executable called \fBgcc\fR, or +\&\fImachine\fR\fB\-gcc\fR when cross-compiling, or +\&\fImachine\fR\fB\-gcc\-\fR\fIversion\fR to run a version other than the +one that was installed last. +.SS "Hardware Models and Configurations" +.IX Subsection "Hardware Models and Configurations" +Each target machine types can have its own +special options, starting with \fB\-m\fR, to choose among various +hardware models or configurations\-\-\-for example, 68010 vs 68020, +floating coprocessor or none. A single installed version of the +compiler can compile for any model or configuration, according to the +options specified. +.PP +Some configurations of the compiler also support additional special +options, usually for compatibility with other compilers on the same +platform. +.PP +\fI\s-1ARC\s0 Options\fR +.IX Subsection "ARC Options" +.PP +These options are defined for \s-1ARC\s0 implementations: +.IP "\fB\-EL\fR" 4 +.IX Item "-EL" +Compile code for little endian mode. This is the default. +.IP "\fB\-EB\fR" 4 +.IX Item "-EB" +Compile code for big endian mode. +.IP "\fB\-mmangle\-cpu\fR" 4 +.IX Item "-mmangle-cpu" +Prepend the name of the \s-1CPU\s0 to all public symbol names. +In multiple-processor systems, there are many \s-1ARC\s0 variants with different +instruction and register set characteristics. This flag prevents code +compiled for one \s-1CPU\s0 to be linked with code compiled for another. +No facility exists for handling variants that are \*(L"almost identical\*(R". +This is an all or nothing option. +.IP "\fB\-mcpu=\fR\fIcpu\fR" 4 +.IX Item "-mcpu=cpu" +Compile code for \s-1ARC\s0 variant \fIcpu\fR. +Which variants are supported depend on the configuration. +All variants support \fB\-mcpu=base\fR, this is the default. +.IP "\fB\-mtext=\fR\fItext-section\fR" 4 +.IX Item "-mtext=text-section" +.PD 0 +.IP "\fB\-mdata=\fR\fIdata-section\fR" 4 +.IX Item "-mdata=data-section" +.IP "\fB\-mrodata=\fR\fIreadonly-data-section\fR" 4 +.IX Item "-mrodata=readonly-data-section" +.PD +Put functions, data, and readonly data in \fItext-section\fR, +\&\fIdata-section\fR, and \fIreadonly-data-section\fR respectively +by default. This can be overridden with the \f(CW\*(C`section\*(C'\fR attribute. +.PP +\fI\s-1ARM\s0 Options\fR +.IX Subsection "ARM Options" +.PP +These \fB\-m\fR options are defined for Advanced \s-1RISC\s0 Machines (\s-1ARM\s0) +architectures: +.IP "\fB\-mabi=\fR\fIname\fR" 4 +.IX Item "-mabi=name" +Generate code for the specified \s-1ABI\s0. Permissible values are: \fBapcs-gnu\fR, +\&\fBatpcs\fR, \fBaapcs\fR, \fBaapcs-linux\fR and \fBiwmmxt\fR. +.IP "\fB\-mapcs\-frame\fR" 4 +.IX Item "-mapcs-frame" +Generate a stack frame that is compliant with the \s-1ARM\s0 Procedure Call +Standard for all functions, even if this is not strictly necessary for +correct execution of the code. Specifying \fB\-fomit\-frame\-pointer\fR +with this option will cause the stack frames not to be generated for +leaf functions. The default is \fB\-mno\-apcs\-frame\fR. +.IP "\fB\-mapcs\fR" 4 +.IX Item "-mapcs" +This is a synonym for \fB\-mapcs\-frame\fR. +.IP "\fB\-mthumb\-interwork\fR" 4 +.IX Item "-mthumb-interwork" +Generate code which supports calling between the \s-1ARM\s0 and Thumb +instruction sets. Without this option the two instruction sets cannot +be reliably used inside one program. The default is +\&\fB\-mno\-thumb\-interwork\fR, since slightly larger code is generated +when \fB\-mthumb\-interwork\fR is specified. +.IP "\fB\-mno\-sched\-prolog\fR" 4 +.IX Item "-mno-sched-prolog" +Prevent the reordering of instructions in the function prolog, or the +merging of those instruction with the instructions in the function's +body. This means that all functions will start with a recognizable set +of instructions (or in fact one of a choice from a small set of +different function prologues), and this information can be used to +locate the start if functions inside an executable piece of code. The +default is \fB\-msched\-prolog\fR. +.IP "\fB\-mfloat\-abi=\fR\fIname\fR" 4 +.IX Item "-mfloat-abi=name" +Specifies which floating-point \s-1ABI\s0 to use. Permissible values +are: \fBsoft\fR, \fBsoftfp\fR and \fBhard\fR. +.Sp +Specifying \fBsoft\fR causes \s-1GCC\s0 to generate output containing +library calls for floating-point operations. +\&\fBsoftfp\fR allows the generation of code using hardware floating-point +instructions, but still uses the soft-float calling conventions. +\&\fBhard\fR allows generation of floating-point instructions +and uses FPU-specific calling conventions. +.Sp +The default depends on the specific target configuration. Note that +the hard-float and soft-float ABIs are not link-compatible; you must +compile your entire program with the same \s-1ABI\s0, and link with a +compatible set of libraries. +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +Equivalent to \fB\-mfloat\-abi=hard\fR. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Equivalent to \fB\-mfloat\-abi=soft\fR. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +Generate code for a processor running in little-endian mode. This is +the default for all standard configurations. +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +Generate code for a processor running in big-endian mode; the default is +to compile code for a little-endian processor. +.IP "\fB\-mwords\-little\-endian\fR" 4 +.IX Item "-mwords-little-endian" +This option only applies when generating code for big-endian processors. +Generate code for a little-endian word order but a big-endian byte +order. That is, a byte order of the form \fB32107654\fR. Note: this +option should only be used if you require compatibility with code for +big-endian \s-1ARM\s0 processors generated by versions of the compiler prior to +2.8. +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +This specifies the name of the target \s-1ARM\s0 processor. \s-1GCC\s0 uses this name +to determine what kind of instructions it can emit when generating +assembly code. Permissible names are: \fBarm2\fR, \fBarm250\fR, +\&\fBarm3\fR, \fBarm6\fR, \fBarm60\fR, \fBarm600\fR, \fBarm610\fR, +\&\fBarm620\fR, \fBarm7\fR, \fBarm7m\fR, \fBarm7d\fR, \fBarm7dm\fR, +\&\fBarm7di\fR, \fBarm7dmi\fR, \fBarm70\fR, \fBarm700\fR, +\&\fBarm700i\fR, \fBarm710\fR, \fBarm710c\fR, \fBarm7100\fR, +\&\fBarm720\fR, +\&\fBarm7500\fR, \fBarm7500fe\fR, \fBarm7tdmi\fR, \fBarm7tdmi\-s\fR, +\&\fBarm710t\fR, \fBarm720t\fR, \fBarm740t\fR, +\&\fBstrongarm\fR, \fBstrongarm110\fR, \fBstrongarm1100\fR, +\&\fBstrongarm1110\fR, +\&\fBarm8\fR, \fBarm810\fR, \fBarm9\fR, \fBarm9e\fR, \fBarm920\fR, +\&\fBarm920t\fR, \fBarm922t\fR, \fBarm946e\-s\fR, \fBarm966e\-s\fR, +\&\fBarm968e\-s\fR, \fBarm926ej\-s\fR, \fBarm940t\fR, \fBarm9tdmi\fR, +\&\fBarm10tdmi\fR, \fBarm1020t\fR, \fBarm1026ej\-s\fR, +\&\fBarm10e\fR, \fBarm1020e\fR, \fBarm1022e\fR, +\&\fBarm1136j\-s\fR, \fBarm1136jf\-s\fR, \fBmpcore\fR, \fBmpcorenovfp\fR, +\&\fBarm1156t2\-s\fR, \fBarm1156t2f\-s\fR, \fBarm1176jz\-s\fR, \fBarm1176jzf\-s\fR, +\&\fBcortex\-a5\fR, \fBcortex\-a8\fR, \fBcortex\-a9\fR, \fBcortex\-a15\fR, +\&\fBcortex\-r4\fR, \fBcortex\-r4f\fR, \fBcortex\-m4\fR, \fBcortex\-m3\fR, +\&\fBcortex\-m1\fR, +\&\fBcortex\-m0\fR, +\&\fBxscale\fR, \fBiwmmxt\fR, \fBiwmmxt2\fR, \fBep9312\fR. +.IP "\fB\-mtune=\fR\fIname\fR" 4 +.IX Item "-mtune=name" +This option is very similar to the \fB\-mcpu=\fR option, except that +instead of specifying the actual target processor type, and hence +restricting which instructions can be used, it specifies that \s-1GCC\s0 should +tune the performance of the code as if the target were of the type +specified in this option, but still choosing the instructions that it +will generate based on the \s-1CPU\s0 specified by a \fB\-mcpu=\fR option. +For some \s-1ARM\s0 implementations better performance can be obtained by using +this option. +.IP "\fB\-march=\fR\fIname\fR" 4 +.IX Item "-march=name" +This specifies the name of the target \s-1ARM\s0 architecture. \s-1GCC\s0 uses this +name to determine what kind of instructions it can emit when generating +assembly code. This option can be used in conjunction with or instead +of the \fB\-mcpu=\fR option. Permissible names are: \fBarmv2\fR, +\&\fBarmv2a\fR, \fBarmv3\fR, \fBarmv3m\fR, \fBarmv4\fR, \fBarmv4t\fR, +\&\fBarmv5\fR, \fBarmv5t\fR, \fBarmv5e\fR, \fBarmv5te\fR, +\&\fBarmv6\fR, \fBarmv6j\fR, +\&\fBarmv6t2\fR, \fBarmv6z\fR, \fBarmv6zk\fR, \fBarmv6\-m\fR, +\&\fBarmv7\fR, \fBarmv7\-a\fR, \fBarmv7\-r\fR, \fBarmv7\-m\fR, +\&\fBiwmmxt\fR, \fBiwmmxt2\fR, \fBep9312\fR. +.IP "\fB\-mfpu=\fR\fIname\fR" 4 +.IX Item "-mfpu=name" +.PD 0 +.IP "\fB\-mfpe=\fR\fInumber\fR" 4 +.IX Item "-mfpe=number" +.IP "\fB\-mfp=\fR\fInumber\fR" 4 +.IX Item "-mfp=number" +.PD +This specifies what floating point hardware (or hardware emulation) is +available on the target. Permissible names are: \fBfpa\fR, \fBfpe2\fR, +\&\fBfpe3\fR, \fBmaverick\fR, \fBvfp\fR, \fBvfpv3\fR, \fBvfpv3\-fp16\fR, +\&\fBvfpv3\-d16\fR, \fBvfpv3\-d16\-fp16\fR, \fBvfpv3xd\fR, \fBvfpv3xd\-fp16\fR, +\&\fBneon\fR, \fBneon\-fp16\fR, \fBvfpv4\fR, \fBvfpv4\-d16\fR, +\&\fBfpv4\-sp\-d16\fR and \fBneon\-vfpv4\fR. +\&\fB\-mfp\fR and \fB\-mfpe\fR are synonyms for +\&\fB\-mfpu\fR=\fBfpe\fR\fInumber\fR, for compatibility with older versions +of \s-1GCC\s0. +.Sp +If \fB\-msoft\-float\fR is specified this specifies the format of +floating point values. +.Sp +If the selected floating-point hardware includes the \s-1NEON\s0 extension +(e.g. \fB\-mfpu\fR=\fBneon\fR), note that floating-point +operations will not be used by \s-1GCC\s0's auto-vectorization pass unless +\&\fB\-funsafe\-math\-optimizations\fR is also specified. This is +because \s-1NEON\s0 hardware does not fully implement the \s-1IEEE\s0 754 standard for +floating-point arithmetic (in particular denormal values are treated as +zero), so the use of \s-1NEON\s0 instructions may lead to a loss of precision. +.IP "\fB\-mfp16\-format=\fR\fIname\fR" 4 +.IX Item "-mfp16-format=name" +Specify the format of the \f(CW\*(C`_\|_fp16\*(C'\fR half-precision floating-point type. +Permissible names are \fBnone\fR, \fBieee\fR, and \fBalternative\fR; +the default is \fBnone\fR, in which case the \f(CW\*(C`_\|_fp16\*(C'\fR type is not +defined. +.IP "\fB\-mstructure\-size\-boundary=\fR\fIn\fR" 4 +.IX Item "-mstructure-size-boundary=n" +The size of all structures and unions will be rounded up to a multiple +of the number of bits set by this option. Permissible values are 8, 32 +and 64. The default value varies for different toolchains. For the \s-1COFF\s0 +targeted toolchain the default value is 8. A value of 64 is only allowed +if the underlying \s-1ABI\s0 supports it. +.Sp +Specifying the larger number can produce faster, more efficient code, but +can also increase the size of the program. Different values are potentially +incompatible. Code compiled with one value cannot necessarily expect to +work with code or libraries compiled with another value, if they exchange +information using structures or unions. +.IP "\fB\-mabort\-on\-noreturn\fR" 4 +.IX Item "-mabort-on-noreturn" +Generate a call to the function \f(CW\*(C`abort\*(C'\fR at the end of a +\&\f(CW\*(C`noreturn\*(C'\fR function. It will be executed if the function tries to +return. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +.PD 0 +.IP "\fB\-mno\-long\-calls\fR" 4 +.IX Item "-mno-long-calls" +.PD +Tells the compiler to perform function calls by first loading the +address of the function into a register and then performing a subroutine +call on this register. This switch is needed if the target function +will lie outside of the 64 megabyte addressing range of the offset based +version of subroutine call instruction. +.Sp +Even if this switch is enabled, not all function calls will be turned +into long calls. The heuristic is that static functions, functions +which have the \fBshort-call\fR attribute, functions that are inside +the scope of a \fB#pragma no_long_calls\fR directive and functions whose +definitions have already been compiled within the current compilation +unit, will not be turned into long calls. The exception to this rule is +that weak function definitions, functions with the \fBlong-call\fR +attribute or the \fBsection\fR attribute, and functions that are within +the scope of a \fB#pragma long_calls\fR directive, will always be +turned into long calls. +.Sp +This feature is not enabled by default. Specifying +\&\fB\-mno\-long\-calls\fR will restore the default behavior, as will +placing the function calls within the scope of a \fB#pragma +long_calls_off\fR directive. Note these switches have no effect on how +the compiler generates code to handle function calls via function +pointers. +.IP "\fB\-msingle\-pic\-base\fR" 4 +.IX Item "-msingle-pic-base" +Treat the register used for \s-1PIC\s0 addressing as read-only, rather than +loading it in the prologue for each function. The run-time system is +responsible for initializing this register with an appropriate value +before execution begins. +.IP "\fB\-mpic\-register=\fR\fIreg\fR" 4 +.IX Item "-mpic-register=reg" +Specify the register to be used for \s-1PIC\s0 addressing. The default is R10 +unless stack-checking is enabled, when R9 is used. +.IP "\fB\-mcirrus\-fix\-invalid\-insns\fR" 4 +.IX Item "-mcirrus-fix-invalid-insns" +Insert NOPs into the instruction stream to in order to work around +problems with invalid Maverick instruction combinations. This option +is only valid if the \fB\-mcpu=ep9312\fR option has been used to +enable generation of instructions for the Cirrus Maverick floating +point co-processor. This option is not enabled by default, since the +problem is only present in older Maverick implementations. The default +can be re-enabled by use of the \fB\-mno\-cirrus\-fix\-invalid\-insns\fR +switch. +.IP "\fB\-mpoke\-function\-name\fR" 4 +.IX Item "-mpoke-function-name" +Write the name of each function into the text section, directly +preceding the function prologue. The generated code is similar to this: +.Sp +.Vb 9 +\& t0 +\& .ascii "arm_poke_function_name", 0 +\& .align +\& t1 +\& .word 0xff000000 + (t1 \- t0) +\& arm_poke_function_name +\& mov ip, sp +\& stmfd sp!, {fp, ip, lr, pc} +\& sub fp, ip, #4 +.Ve +.Sp +When performing a stack backtrace, code can inspect the value of +\&\f(CW\*(C`pc\*(C'\fR stored at \f(CW\*(C`fp + 0\*(C'\fR. If the trace function then looks at +location \f(CW\*(C`pc \- 12\*(C'\fR and the top 8 bits are set, then we know that +there is a function name embedded immediately preceding this location +and has length \f(CW\*(C`((pc[\-3]) & 0xff000000)\*(C'\fR. +.IP "\fB\-mthumb\fR" 4 +.IX Item "-mthumb" +Generate code for the Thumb instruction set. The default is to +use the 32\-bit \s-1ARM\s0 instruction set. +This option automatically enables either 16\-bit Thumb\-1 or +mixed 16/32\-bit Thumb\-2 instructions based on the \fB\-mcpu=\fR\fIname\fR +and \fB\-march=\fR\fIname\fR options. This option is not passed to the +assembler. If you want to force assembler files to be interpreted as Thumb code, +either add a \fB.thumb\fR directive to the source or pass the \fB\-mthumb\fR +option directly to the assembler by prefixing it with \fB\-Wa\fR. +.IP "\fB\-mtpcs\-frame\fR" 4 +.IX Item "-mtpcs-frame" +Generate a stack frame that is compliant with the Thumb Procedure Call +Standard for all non-leaf functions. (A leaf function is one that does +not call any other functions.) The default is \fB\-mno\-tpcs\-frame\fR. +.IP "\fB\-mtpcs\-leaf\-frame\fR" 4 +.IX Item "-mtpcs-leaf-frame" +Generate a stack frame that is compliant with the Thumb Procedure Call +Standard for all leaf functions. (A leaf function is one that does +not call any other functions.) The default is \fB\-mno\-apcs\-leaf\-frame\fR. +.IP "\fB\-mcallee\-super\-interworking\fR" 4 +.IX Item "-mcallee-super-interworking" +Gives all externally visible functions in the file being compiled an \s-1ARM\s0 +instruction set header which switches to Thumb mode before executing the +rest of the function. This allows these functions to be called from +non-interworking code. This option is not valid in \s-1AAPCS\s0 configurations +because interworking is enabled by default. +.IP "\fB\-mcaller\-super\-interworking\fR" 4 +.IX Item "-mcaller-super-interworking" +Allows calls via function pointers (including virtual functions) to +execute correctly regardless of whether the target code has been +compiled for interworking or not. There is a small overhead in the cost +of executing a function pointer if this option is enabled. This option +is not valid in \s-1AAPCS\s0 configurations because interworking is enabled +by default. +.IP "\fB\-mtp=\fR\fIname\fR" 4 +.IX Item "-mtp=name" +Specify the access model for the thread local storage pointer. The valid +models are \fBsoft\fR, which generates calls to \f(CW\*(C`_\|_aeabi_read_tp\*(C'\fR, +\&\fBcp15\fR, which fetches the thread pointer from \f(CW\*(C`cp15\*(C'\fR directly +(supported in the arm6k architecture), and \fBauto\fR, which uses the +best available method for the selected processor. The default setting is +\&\fBauto\fR. +.IP "\fB\-mword\-relocations\fR" 4 +.IX Item "-mword-relocations" +Only generate absolute relocations on word sized values (i.e. R_ARM_ABS32). +This is enabled by default on targets (uClinux, SymbianOS) where the runtime +loader imposes this restriction, and when \fB\-fpic\fR or \fB\-fPIC\fR +is specified. +.IP "\fB\-mfix\-cortex\-m3\-ldrd\fR" 4 +.IX Item "-mfix-cortex-m3-ldrd" +Some Cortex\-M3 cores can cause data corruption when \f(CW\*(C`ldrd\*(C'\fR instructions +with overlapping destination and base registers are used. This option avoids +generating these instructions. This option is enabled by default when +\&\fB\-mcpu=cortex\-m3\fR is specified. +.PP +\fI\s-1AVR\s0 Options\fR +.IX Subsection "AVR Options" +.PP +These options are defined for \s-1AVR\s0 implementations: +.IP "\fB\-mmcu=\fR\fImcu\fR" 4 +.IX Item "-mmcu=mcu" +Specify \s-1ATMEL\s0 \s-1AVR\s0 instruction set or \s-1MCU\s0 type. +.Sp +Instruction set avr1 is for the minimal \s-1AVR\s0 core, not supported by the C +compiler, only for assembler programs (\s-1MCU\s0 types: at90s1200, attiny10, +attiny11, attiny12, attiny15, attiny28). +.Sp +Instruction set avr2 (default) is for the classic \s-1AVR\s0 core with up to +8K program memory space (\s-1MCU\s0 types: at90s2313, at90s2323, attiny22, +at90s2333, at90s2343, at90s4414, at90s4433, at90s4434, at90s8515, +at90c8534, at90s8535). +.Sp +Instruction set avr3 is for the classic \s-1AVR\s0 core with up to 128K program +memory space (\s-1MCU\s0 types: atmega103, atmega603, at43usb320, at76c711). +.Sp +Instruction set avr4 is for the enhanced \s-1AVR\s0 core with up to 8K program +memory space (\s-1MCU\s0 types: atmega8, atmega83, atmega85). +.Sp +Instruction set avr5 is for the enhanced \s-1AVR\s0 core with up to 128K program +memory space (\s-1MCU\s0 types: atmega16, atmega161, atmega163, atmega32, atmega323, +atmega64, atmega128, at43usb355, at94k). +.IP "\fB\-mno\-interrupts\fR" 4 +.IX Item "-mno-interrupts" +Generated code is not compatible with hardware interrupts. +Code size will be smaller. +.IP "\fB\-mcall\-prologues\fR" 4 +.IX Item "-mcall-prologues" +Functions prologues/epilogues expanded as call to appropriate +subroutines. Code size will be smaller. +.IP "\fB\-mtiny\-stack\fR" 4 +.IX Item "-mtiny-stack" +Change only the low 8 bits of the stack pointer. +.IP "\fB\-mint8\fR" 4 +.IX Item "-mint8" +Assume int to be 8 bit integer. This affects the sizes of all types: A +char will be 1 byte, an int will be 1 byte, a long will be 2 bytes +and long long will be 4 bytes. Please note that this option does not +comply to the C standards, but it will provide you with smaller code +size. +.PP +\f(CW\*(C`EIND\*(C'\fR and Devices with more than 128k Bytes of Flash +.IX Subsection "EIND and Devices with more than 128k Bytes of Flash" +.PP +Pointers in the implementation are 16 bits wide. +The address of a function or label is represented as word address so +that indirect jumps and calls can address any code address in the +range of 64k words. +.PP +In order to faciliate indirect jump on devices with more than 128k +bytes of program memory space, there is a special function register called +\&\f(CW\*(C`EIND\*(C'\fR that serves as most significant part of the target address +when \f(CW\*(C`EICALL\*(C'\fR or \f(CW\*(C`EIJMP\*(C'\fR instructions are used. +.PP +Indirect jumps and calls on these devices are handled as follows and +are subject to some limitations: +.IP "\(bu" 4 +The compiler never sets \f(CW\*(C`EIND\*(C'\fR. +.IP "\(bu" 4 +The startup code from libgcc never sets \f(CW\*(C`EIND\*(C'\fR. +Notice that startup code is a blend of code from libgcc and avr-libc. +For the impact of avr-libc on \f(CW\*(C`EIND\*(C'\fR, see the +avr-libc\ user\ manual (\f(CW\*(C`http://nongnu.org/avr\-libc/user\-manual\*(C'\fR). +.IP "\(bu" 4 +The compiler uses \f(CW\*(C`EIND\*(C'\fR implicitely in \f(CW\*(C`EICALL\*(C'\fR/\f(CW\*(C`EIJMP\*(C'\fR +instructions or might read \f(CW\*(C`EIND\*(C'\fR directly. +.IP "\(bu" 4 +The compiler assumes that \f(CW\*(C`EIND\*(C'\fR never changes during the startup +code or run of the application. In particular, \f(CW\*(C`EIND\*(C'\fR is not +saved/restored in function or interrupt service routine +prologue/epilogue. +.IP "\(bu" 4 +It is legitimate for user-specific startup code to set up \f(CW\*(C`EIND\*(C'\fR +early, for example by means of initialization code located in +section \f(CW\*(C`.init3\*(C'\fR, and thus prior to general startup code that +initializes \s-1RAM\s0 and calls constructors. +.IP "\(bu" 4 +For indirect calls to functions and computed goto, the linker will +generate \fIstubs\fR. Stubs are jump pads sometimes also called +\&\fItrampolines\fR. Thus, the indirect call/jump will jump to such a stub. +The stub contains a direct jump to the desired address. +.IP "\(bu" 4 +Stubs will be generated automatically by the linker if +the following two conditions are met: +.RS 4 +.ie n .IP "\-<The address of a label is taken by means of the ""gs"" modifier>" 4 +.el .IP "\-<The address of a label is taken by means of the \f(CWgs\fR modifier>" 4 +.IX Item "-<The address of a label is taken by means of the gs modifier>" +(short for \fIgenerate stubs\fR) like so: +.Sp +.Vb 2 +\& LDI r24, lo8(gs(<func>)) +\& LDI r25, hi8(gs(<func>)) +.Ve +.IP "\-<The final location of that label is in a code segment>" 4 +.IX Item "-<The final location of that label is in a code segment>" +\&\fIoutside\fR the segment where the stubs are located. +.RE +.RS 4 +.RE +.IP "\(bu" 4 +The compiler will emit such \f(CW\*(C`gs\*(C'\fR modifiers for code labels in the +following situations: +.RS 4 +.IP "\-<Taking address of a function or code label.>" 4 +.IX Item "-<Taking address of a function or code label.>" +.PD 0 +.IP "\-<Computed goto.>" 4 +.IX Item "-<Computed goto.>" +.IP "\-<If prologue-save function is used, see \fB\-mcall\-prologues\fR>" 4 +.IX Item "-<If prologue-save function is used, see -mcall-prologues>" +.PD +command line option. +.IP "\-<Switch/case dispatch tables. If you do not want such dispatch>" 4 +.IX Item "-<Switch/case dispatch tables. If you do not want such dispatch>" +tables you can specify the \fB\-fno\-jump\-tables\fR command line option. +.IP "\-<C and \*(C+ constructors/destructors called during startup/shutdown.>" 4 +.IX Item "-<C and constructors/destructors called during startup/shutdown.>" +.PD 0 +.ie n .IP "\-<If the tools hit a ""gs()"" modifier explained above.>" 4 +.el .IP "\-<If the tools hit a \f(CWgs()\fR modifier explained above.>" 4 +.IX Item "-<If the tools hit a gs() modifier explained above.>" +.RE +.RS 4 +.RE +.IP "\(bu" 4 +.PD +The default linker script is arranged for code with \f(CW\*(C`EIND = 0\*(C'\fR. +If code is supposed to work for a setup with \f(CW\*(C`EIND != 0\*(C'\fR, a custom +linker script has to be used in order to place the sections whose +name start with \f(CW\*(C`.trampolines\*(C'\fR into the segment where \f(CW\*(C`EIND\*(C'\fR +points to. +.IP "\(bu" 4 +Jumping to non-symbolic addresses like so is \fInot\fR supported: +.Sp +.Vb 5 +\& int main (void) +\& { +\& /* Call function at word address 0x2 */ +\& return ((int(*)(void)) 0x2)(); +\& } +.Ve +.Sp +Instead, a stub has to be set up: +.Sp +.Vb 3 +\& int main (void) +\& { +\& extern int func_4 (void); +\& +\& /* Call function at byte address 0x4 */ +\& return func_4(); +\& } +.Ve +.Sp +and the application be linked with \f(CW\*(C`\-Wl,\-\-defsym,func_4=0x4\*(C'\fR. +Alternatively, \f(CW\*(C`func_4\*(C'\fR can be defined in the linker script. +.PP +\fIBlackfin Options\fR +.IX Subsection "Blackfin Options" +.IP "\fB\-mcpu=\fR\fIcpu\fR[\fB\-\fR\fIsirevision\fR]" 4 +.IX Item "-mcpu=cpu[-sirevision]" +Specifies the name of the target Blackfin processor. Currently, \fIcpu\fR +can be one of \fBbf512\fR, \fBbf514\fR, \fBbf516\fR, \fBbf518\fR, +\&\fBbf522\fR, \fBbf523\fR, \fBbf524\fR, \fBbf525\fR, \fBbf526\fR, +\&\fBbf527\fR, \fBbf531\fR, \fBbf532\fR, \fBbf533\fR, +\&\fBbf534\fR, \fBbf536\fR, \fBbf537\fR, \fBbf538\fR, \fBbf539\fR, +\&\fBbf542\fR, \fBbf544\fR, \fBbf547\fR, \fBbf548\fR, \fBbf549\fR, +\&\fBbf542m\fR, \fBbf544m\fR, \fBbf547m\fR, \fBbf548m\fR, \fBbf549m\fR, +\&\fBbf561\fR. +The optional \fIsirevision\fR specifies the silicon revision of the target +Blackfin processor. Any workarounds available for the targeted silicon revision +will be enabled. If \fIsirevision\fR is \fBnone\fR, no workarounds are enabled. +If \fIsirevision\fR is \fBany\fR, all workarounds for the targeted processor +will be enabled. The \f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR macro is defined to two +hexadecimal digits representing the major and minor numbers in the silicon +revision. If \fIsirevision\fR is \fBnone\fR, the \f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR +is not defined. If \fIsirevision\fR is \fBany\fR, the +\&\f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR is defined to be \f(CW0xffff\fR. +If this optional \fIsirevision\fR is not used, \s-1GCC\s0 assumes the latest known +silicon revision of the targeted Blackfin processor. +.Sp +Support for \fBbf561\fR is incomplete. For \fBbf561\fR, +Only the processor macro is defined. +Without this option, \fBbf532\fR is used as the processor by default. +The corresponding predefined processor macros for \fIcpu\fR is to +be defined. And for \fBbfin-elf\fR toolchain, this causes the hardware \s-1BSP\s0 +provided by libgloss to be linked in if \fB\-msim\fR is not given. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Specifies that the program will be run on the simulator. This causes +the simulator \s-1BSP\s0 provided by libgloss to be linked in. This option +has effect only for \fBbfin-elf\fR toolchain. +Certain other options, such as \fB\-mid\-shared\-library\fR and +\&\fB\-mfdpic\fR, imply \fB\-msim\fR. +.IP "\fB\-momit\-leaf\-frame\-pointer\fR" 4 +.IX Item "-momit-leaf-frame-pointer" +Don't keep the frame pointer in a register for leaf functions. This +avoids the instructions to save, set up and restore frame pointers and +makes an extra register available in leaf functions. The option +\&\fB\-fomit\-frame\-pointer\fR removes the frame pointer for all functions +which might make debugging harder. +.IP "\fB\-mspecld\-anomaly\fR" 4 +.IX Item "-mspecld-anomaly" +When enabled, the compiler will ensure that the generated code does not +contain speculative loads after jump instructions. If this option is used, +\&\f(CW\*(C`_\|_WORKAROUND_SPECULATIVE_LOADS\*(C'\fR is defined. +.IP "\fB\-mno\-specld\-anomaly\fR" 4 +.IX Item "-mno-specld-anomaly" +Don't generate extra code to prevent speculative loads from occurring. +.IP "\fB\-mcsync\-anomaly\fR" 4 +.IX Item "-mcsync-anomaly" +When enabled, the compiler will ensure that the generated code does not +contain \s-1CSYNC\s0 or \s-1SSYNC\s0 instructions too soon after conditional branches. +If this option is used, \f(CW\*(C`_\|_WORKAROUND_SPECULATIVE_SYNCS\*(C'\fR is defined. +.IP "\fB\-mno\-csync\-anomaly\fR" 4 +.IX Item "-mno-csync-anomaly" +Don't generate extra code to prevent \s-1CSYNC\s0 or \s-1SSYNC\s0 instructions from +occurring too soon after a conditional branch. +.IP "\fB\-mlow\-64k\fR" 4 +.IX Item "-mlow-64k" +When enabled, the compiler is free to take advantage of the knowledge that +the entire program fits into the low 64k of memory. +.IP "\fB\-mno\-low\-64k\fR" 4 +.IX Item "-mno-low-64k" +Assume that the program is arbitrarily large. This is the default. +.IP "\fB\-mstack\-check\-l1\fR" 4 +.IX Item "-mstack-check-l1" +Do stack checking using information placed into L1 scratchpad memory by the +uClinux kernel. +.IP "\fB\-mid\-shared\-library\fR" 4 +.IX Item "-mid-shared-library" +Generate code that supports shared libraries via the library \s-1ID\s0 method. +This allows for execute in place and shared libraries in an environment +without virtual memory management. This option implies \fB\-fPIC\fR. +With a \fBbfin-elf\fR target, this option implies \fB\-msim\fR. +.IP "\fB\-mno\-id\-shared\-library\fR" 4 +.IX Item "-mno-id-shared-library" +Generate code that doesn't assume \s-1ID\s0 based shared libraries are being used. +This is the default. +.IP "\fB\-mleaf\-id\-shared\-library\fR" 4 +.IX Item "-mleaf-id-shared-library" +Generate code that supports shared libraries via the library \s-1ID\s0 method, +but assumes that this library or executable won't link against any other +\&\s-1ID\s0 shared libraries. That allows the compiler to use faster code for jumps +and calls. +.IP "\fB\-mno\-leaf\-id\-shared\-library\fR" 4 +.IX Item "-mno-leaf-id-shared-library" +Do not assume that the code being compiled won't link against any \s-1ID\s0 shared +libraries. Slower code will be generated for jump and call insns. +.IP "\fB\-mshared\-library\-id=n\fR" 4 +.IX Item "-mshared-library-id=n" +Specified the identification number of the \s-1ID\s0 based shared library being +compiled. Specifying a value of 0 will generate more compact code, specifying +other values will force the allocation of that number to the current +library but is no more space or time efficient than omitting this option. +.IP "\fB\-msep\-data\fR" 4 +.IX Item "-msep-data" +Generate code that allows the data segment to be located in a different +area of memory from the text segment. This allows for execute in place in +an environment without virtual memory management by eliminating relocations +against the text section. +.IP "\fB\-mno\-sep\-data\fR" 4 +.IX Item "-mno-sep-data" +Generate code that assumes that the data segment follows the text segment. +This is the default. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +.PD 0 +.IP "\fB\-mno\-long\-calls\fR" 4 +.IX Item "-mno-long-calls" +.PD +Tells the compiler to perform function calls by first loading the +address of the function into a register and then performing a subroutine +call on this register. This switch is needed if the target function +will lie outside of the 24 bit addressing range of the offset based +version of subroutine call instruction. +.Sp +This feature is not enabled by default. Specifying +\&\fB\-mno\-long\-calls\fR will restore the default behavior. Note these +switches have no effect on how the compiler generates code to handle +function calls via function pointers. +.IP "\fB\-mfast\-fp\fR" 4 +.IX Item "-mfast-fp" +Link with the fast floating-point library. This library relaxes some of +the \s-1IEEE\s0 floating-point standard's rules for checking inputs against +Not-a-Number (\s-1NAN\s0), in the interest of performance. +.IP "\fB\-minline\-plt\fR" 4 +.IX Item "-minline-plt" +Enable inlining of \s-1PLT\s0 entries in function calls to functions that are +not known to bind locally. It has no effect without \fB\-mfdpic\fR. +.IP "\fB\-mmulticore\fR" 4 +.IX Item "-mmulticore" +Build standalone application for multicore Blackfin processor. Proper +start files and link scripts will be used to support multicore. +This option defines \f(CW\*(C`_\|_BFIN_MULTICORE\*(C'\fR. It can only be used with +\&\fB\-mcpu=bf561\fR[\fB\-\fR\fIsirevision\fR]. It can be used with +\&\fB\-mcorea\fR or \fB\-mcoreb\fR. If it's used without +\&\fB\-mcorea\fR or \fB\-mcoreb\fR, single application/dual core +programming model is used. In this model, the main function of Core B +should be named as coreb_main. If it's used with \fB\-mcorea\fR or +\&\fB\-mcoreb\fR, one application per core programming model is used. +If this option is not used, single core application programming +model is used. +.IP "\fB\-mcorea\fR" 4 +.IX Item "-mcorea" +Build standalone application for Core A of \s-1BF561\s0 when using +one application per core programming model. Proper start files +and link scripts will be used to support Core A. This option +defines \f(CW\*(C`_\|_BFIN_COREA\*(C'\fR. It must be used with \fB\-mmulticore\fR. +.IP "\fB\-mcoreb\fR" 4 +.IX Item "-mcoreb" +Build standalone application for Core B of \s-1BF561\s0 when using +one application per core programming model. Proper start files +and link scripts will be used to support Core B. This option +defines \f(CW\*(C`_\|_BFIN_COREB\*(C'\fR. When this option is used, coreb_main +should be used instead of main. It must be used with +\&\fB\-mmulticore\fR. +.IP "\fB\-msdram\fR" 4 +.IX Item "-msdram" +Build standalone application for \s-1SDRAM\s0. Proper start files and +link scripts will be used to put the application into \s-1SDRAM\s0. +Loader should initialize \s-1SDRAM\s0 before loading the application +into \s-1SDRAM\s0. This option defines \f(CW\*(C`_\|_BFIN_SDRAM\*(C'\fR. +.IP "\fB\-micplb\fR" 4 +.IX Item "-micplb" +Assume that ICPLBs are enabled at runtime. This has an effect on certain +anomaly workarounds. For Linux targets, the default is to assume ICPLBs +are enabled; for standalone applications the default is off. +.PP +\fI\s-1CRIS\s0 Options\fR +.IX Subsection "CRIS Options" +.PP +These options are defined specifically for the \s-1CRIS\s0 ports. +.IP "\fB\-march=\fR\fIarchitecture-type\fR" 4 +.IX Item "-march=architecture-type" +.PD 0 +.IP "\fB\-mcpu=\fR\fIarchitecture-type\fR" 4 +.IX Item "-mcpu=architecture-type" +.PD +Generate code for the specified architecture. The choices for +\&\fIarchitecture-type\fR are \fBv3\fR, \fBv8\fR and \fBv10\fR for +respectively \s-1ETRAX\s0\ 4, \s-1ETRAX\s0\ 100, and \s-1ETRAX\s0\ 100\ \s-1LX\s0. +Default is \fBv0\fR except for cris-axis-linux-gnu, where the default is +\&\fBv10\fR. +.IP "\fB\-mtune=\fR\fIarchitecture-type\fR" 4 +.IX Item "-mtune=architecture-type" +Tune to \fIarchitecture-type\fR everything applicable about the generated +code, except for the \s-1ABI\s0 and the set of available instructions. The +choices for \fIarchitecture-type\fR are the same as for +\&\fB\-march=\fR\fIarchitecture-type\fR. +.IP "\fB\-mmax\-stack\-frame=\fR\fIn\fR" 4 +.IX Item "-mmax-stack-frame=n" +Warn when the stack frame of a function exceeds \fIn\fR bytes. +.IP "\fB\-metrax4\fR" 4 +.IX Item "-metrax4" +.PD 0 +.IP "\fB\-metrax100\fR" 4 +.IX Item "-metrax100" +.PD +The options \fB\-metrax4\fR and \fB\-metrax100\fR are synonyms for +\&\fB\-march=v3\fR and \fB\-march=v8\fR respectively. +.IP "\fB\-mmul\-bug\-workaround\fR" 4 +.IX Item "-mmul-bug-workaround" +.PD 0 +.IP "\fB\-mno\-mul\-bug\-workaround\fR" 4 +.IX Item "-mno-mul-bug-workaround" +.PD +Work around a bug in the \f(CW\*(C`muls\*(C'\fR and \f(CW\*(C`mulu\*(C'\fR instructions for \s-1CPU\s0 +models where it applies. This option is active by default. +.IP "\fB\-mpdebug\fR" 4 +.IX Item "-mpdebug" +Enable CRIS-specific verbose debug-related information in the assembly +code. This option also has the effect to turn off the \fB#NO_APP\fR +formatted-code indicator to the assembler at the beginning of the +assembly file. +.IP "\fB\-mcc\-init\fR" 4 +.IX Item "-mcc-init" +Do not use condition-code results from previous instruction; always emit +compare and test instructions before use of condition codes. +.IP "\fB\-mno\-side\-effects\fR" 4 +.IX Item "-mno-side-effects" +Do not emit instructions with side-effects in addressing modes other than +post-increment. +.IP "\fB\-mstack\-align\fR" 4 +.IX Item "-mstack-align" +.PD 0 +.IP "\fB\-mno\-stack\-align\fR" 4 +.IX Item "-mno-stack-align" +.IP "\fB\-mdata\-align\fR" 4 +.IX Item "-mdata-align" +.IP "\fB\-mno\-data\-align\fR" 4 +.IX Item "-mno-data-align" +.IP "\fB\-mconst\-align\fR" 4 +.IX Item "-mconst-align" +.IP "\fB\-mno\-const\-align\fR" 4 +.IX Item "-mno-const-align" +.PD +These options (no-options) arranges (eliminate arrangements) for the +stack-frame, individual data and constants to be aligned for the maximum +single data access size for the chosen \s-1CPU\s0 model. The default is to +arrange for 32\-bit alignment. \s-1ABI\s0 details such as structure layout are +not affected by these options. +.IP "\fB\-m32\-bit\fR" 4 +.IX Item "-m32-bit" +.PD 0 +.IP "\fB\-m16\-bit\fR" 4 +.IX Item "-m16-bit" +.IP "\fB\-m8\-bit\fR" 4 +.IX Item "-m8-bit" +.PD +Similar to the stack\- data\- and const-align options above, these options +arrange for stack-frame, writable data and constants to all be 32\-bit, +16\-bit or 8\-bit aligned. The default is 32\-bit alignment. +.IP "\fB\-mno\-prologue\-epilogue\fR" 4 +.IX Item "-mno-prologue-epilogue" +.PD 0 +.IP "\fB\-mprologue\-epilogue\fR" 4 +.IX Item "-mprologue-epilogue" +.PD +With \fB\-mno\-prologue\-epilogue\fR, the normal function prologue and +epilogue that sets up the stack-frame are omitted and no return +instructions or return sequences are generated in the code. Use this +option only together with visual inspection of the compiled code: no +warnings or errors are generated when call-saved registers must be saved, +or storage for local variable needs to be allocated. +.IP "\fB\-mno\-gotplt\fR" 4 +.IX Item "-mno-gotplt" +.PD 0 +.IP "\fB\-mgotplt\fR" 4 +.IX Item "-mgotplt" +.PD +With \fB\-fpic\fR and \fB\-fPIC\fR, don't generate (do generate) +instruction sequences that load addresses for functions from the \s-1PLT\s0 part +of the \s-1GOT\s0 rather than (traditional on other architectures) calls to the +\&\s-1PLT\s0. The default is \fB\-mgotplt\fR. +.IP "\fB\-melf\fR" 4 +.IX Item "-melf" +Legacy no-op option only recognized with the cris-axis-elf and +cris-axis-linux-gnu targets. +.IP "\fB\-mlinux\fR" 4 +.IX Item "-mlinux" +Legacy no-op option only recognized with the cris-axis-linux-gnu target. +.IP "\fB\-sim\fR" 4 +.IX Item "-sim" +This option, recognized for the cris-axis-elf arranges +to link with input-output functions from a simulator library. Code, +initialized data and zero-initialized data are allocated consecutively. +.IP "\fB\-sim2\fR" 4 +.IX Item "-sim2" +Like \fB\-sim\fR, but pass linker options to locate initialized data at +0x40000000 and zero-initialized data at 0x80000000. +.PP +\fI\s-1CRX\s0 Options\fR +.IX Subsection "CRX Options" +.PP +These options are defined specifically for the \s-1CRX\s0 ports. +.IP "\fB\-mmac\fR" 4 +.IX Item "-mmac" +Enable the use of multiply-accumulate instructions. Disabled by default. +.IP "\fB\-mpush\-args\fR" 4 +.IX Item "-mpush-args" +Push instructions will be used to pass outgoing arguments when functions +are called. Enabled by default. +.PP +\fIDarwin Options\fR +.IX Subsection "Darwin Options" +.PP +These options are defined for all architectures running the Darwin operating +system. +.PP +\&\s-1FSF\s0 \s-1GCC\s0 on Darwin does not create \*(L"fat\*(R" object files; it will create +an object file for the single architecture that it was built to +target. Apple's \s-1GCC\s0 on Darwin does create \*(L"fat\*(R" files if multiple +\&\fB\-arch\fR options are used; it does so by running the compiler or +linker multiple times and joining the results together with +\&\fIlipo\fR. +.PP +The subtype of the file created (like \fBppc7400\fR or \fBppc970\fR or +\&\fBi686\fR) is determined by the flags that specify the \s-1ISA\s0 +that \s-1GCC\s0 is targetting, like \fB\-mcpu\fR or \fB\-march\fR. The +\&\fB\-force_cpusubtype_ALL\fR option can be used to override this. +.PP +The Darwin tools vary in their behavior when presented with an \s-1ISA\s0 +mismatch. The assembler, \fIas\fR, will only permit instructions to +be used that are valid for the subtype of the file it is generating, +so you cannot put 64\-bit instructions in a \fBppc750\fR object file. +The linker for shared libraries, \fI/usr/bin/libtool\fR, will fail +and print an error if asked to create a shared library with a less +restrictive subtype than its input files (for instance, trying to put +a \fBppc970\fR object file in a \fBppc7400\fR library). The linker +for executables, \fIld\fR, will quietly give the executable the most +restrictive subtype of any of its input files. +.IP "\fB\-F\fR\fIdir\fR" 4 +.IX Item "-Fdir" +Add the framework directory \fIdir\fR to the head of the list of +directories to be searched for header files. These directories are +interleaved with those specified by \fB\-I\fR options and are +scanned in a left-to-right order. +.Sp +A framework directory is a directory with frameworks in it. A +framework is a directory with a \fB\*(L"Headers\*(R"\fR and/or +\&\fB\*(L"PrivateHeaders\*(R"\fR directory contained directly in it that ends +in \fB\*(L".framework\*(R"\fR. The name of a framework is the name of this +directory excluding the \fB\*(L".framework\*(R"\fR. Headers associated with +the framework are found in one of those two directories, with +\&\fB\*(L"Headers\*(R"\fR being searched first. A subframework is a framework +directory that is in a framework's \fB\*(L"Frameworks\*(R"\fR directory. +Includes of subframework headers can only appear in a header of a +framework that contains the subframework, or in a sibling subframework +header. Two subframeworks are siblings if they occur in the same +framework. A subframework should not have the same name as a +framework, a warning will be issued if this is violated. Currently a +subframework cannot have subframeworks, in the future, the mechanism +may be extended to support this. The standard frameworks can be found +in \fB\*(L"/System/Library/Frameworks\*(R"\fR and +\&\fB\*(L"/Library/Frameworks\*(R"\fR. An example include looks like +\&\f(CW\*(C`#include <Framework/header.h>\*(C'\fR, where \fBFramework\fR denotes +the name of the framework and header.h is found in the +\&\fB\*(L"PrivateHeaders\*(R"\fR or \fB\*(L"Headers\*(R"\fR directory. +.IP "\fB\-iframework\fR\fIdir\fR" 4 +.IX Item "-iframeworkdir" +Like \fB\-F\fR except the directory is a treated as a system +directory. The main difference between this \fB\-iframework\fR and +\&\fB\-F\fR is that with \fB\-iframework\fR the compiler does not +warn about constructs contained within header files found via +\&\fIdir\fR. This option is valid only for the C family of languages. +.IP "\fB\-gused\fR" 4 +.IX Item "-gused" +Emit debugging information for symbols that are used. For \s-1STABS\s0 +debugging format, this enables \fB\-feliminate\-unused\-debug\-symbols\fR. +This is by default \s-1ON\s0. +.IP "\fB\-gfull\fR" 4 +.IX Item "-gfull" +Emit debugging information for all symbols and types. +.IP "\fB\-mmacosx\-version\-min=\fR\fIversion\fR" 4 +.IX Item "-mmacosx-version-min=version" +The earliest version of MacOS X that this executable will run on +is \fIversion\fR. Typical values of \fIversion\fR include \f(CW10.1\fR, +\&\f(CW10.2\fR, and \f(CW10.3.9\fR. +.Sp +If the compiler was built to use the system's headers by default, +then the default for this option is the system version on which the +compiler is running, otherwise the default is to make choices which +are compatible with as many systems and code bases as possible. +.IP "\fB\-mkernel\fR" 4 +.IX Item "-mkernel" +Enable kernel development mode. The \fB\-mkernel\fR option sets +\&\fB\-static\fR, \fB\-fno\-common\fR, \fB\-fno\-cxa\-atexit\fR, +\&\fB\-fno\-exceptions\fR, \fB\-fno\-non\-call\-exceptions\fR, +\&\fB\-fapple\-kext\fR, \fB\-fno\-weak\fR and \fB\-fno\-rtti\fR where +applicable. This mode also sets \fB\-mno\-altivec\fR, +\&\fB\-msoft\-float\fR, \fB\-fno\-builtin\fR and +\&\fB\-mlong\-branch\fR for PowerPC targets. +.IP "\fB\-mone\-byte\-bool\fR" 4 +.IX Item "-mone-byte-bool" +Override the defaults for \fBbool\fR so that \fBsizeof(bool)==1\fR. +By default \fBsizeof(bool)\fR is \fB4\fR when compiling for +Darwin/PowerPC and \fB1\fR when compiling for Darwin/x86, so this +option has no effect on x86. +.Sp +\&\fBWarning:\fR The \fB\-mone\-byte\-bool\fR switch causes \s-1GCC\s0 +to generate code that is not binary compatible with code generated +without that switch. Using this switch may require recompiling all +other modules in a program, including system libraries. Use this +switch to conform to a non-default data model. +.IP "\fB\-mfix\-and\-continue\fR" 4 +.IX Item "-mfix-and-continue" +.PD 0 +.IP "\fB\-ffix\-and\-continue\fR" 4 +.IX Item "-ffix-and-continue" +.IP "\fB\-findirect\-data\fR" 4 +.IX Item "-findirect-data" +.PD +Generate code suitable for fast turn around development. Needed to +enable gdb to dynamically load \f(CW\*(C`.o\*(C'\fR files into already running +programs. \fB\-findirect\-data\fR and \fB\-ffix\-and\-continue\fR +are provided for backwards compatibility. +.IP "\fB\-all_load\fR" 4 +.IX Item "-all_load" +Loads all members of static archive libraries. +See man \fIld\fR\|(1) for more information. +.IP "\fB\-arch_errors_fatal\fR" 4 +.IX Item "-arch_errors_fatal" +Cause the errors having to do with files that have the wrong architecture +to be fatal. +.IP "\fB\-bind_at_load\fR" 4 +.IX Item "-bind_at_load" +Causes the output file to be marked such that the dynamic linker will +bind all undefined references when the file is loaded or launched. +.IP "\fB\-bundle\fR" 4 +.IX Item "-bundle" +Produce a Mach-o bundle format file. +See man \fIld\fR\|(1) for more information. +.IP "\fB\-bundle_loader\fR \fIexecutable\fR" 4 +.IX Item "-bundle_loader executable" +This option specifies the \fIexecutable\fR that will be loading the build +output file being linked. See man \fIld\fR\|(1) for more information. +.IP "\fB\-dynamiclib\fR" 4 +.IX Item "-dynamiclib" +When passed this option, \s-1GCC\s0 will produce a dynamic library instead of +an executable when linking, using the Darwin \fIlibtool\fR command. +.IP "\fB\-force_cpusubtype_ALL\fR" 4 +.IX Item "-force_cpusubtype_ALL" +This causes \s-1GCC\s0's output file to have the \fI\s-1ALL\s0\fR subtype, instead of +one controlled by the \fB\-mcpu\fR or \fB\-march\fR option. +.IP "\fB\-allowable_client\fR \fIclient_name\fR" 4 +.IX Item "-allowable_client client_name" +.PD 0 +.IP "\fB\-client_name\fR" 4 +.IX Item "-client_name" +.IP "\fB\-compatibility_version\fR" 4 +.IX Item "-compatibility_version" +.IP "\fB\-current_version\fR" 4 +.IX Item "-current_version" +.IP "\fB\-dead_strip\fR" 4 +.IX Item "-dead_strip" +.IP "\fB\-dependency\-file\fR" 4 +.IX Item "-dependency-file" +.IP "\fB\-dylib_file\fR" 4 +.IX Item "-dylib_file" +.IP "\fB\-dylinker_install_name\fR" 4 +.IX Item "-dylinker_install_name" +.IP "\fB\-dynamic\fR" 4 +.IX Item "-dynamic" +.IP "\fB\-exported_symbols_list\fR" 4 +.IX Item "-exported_symbols_list" +.IP "\fB\-filelist\fR" 4 +.IX Item "-filelist" +.IP "\fB\-flat_namespace\fR" 4 +.IX Item "-flat_namespace" +.IP "\fB\-force_flat_namespace\fR" 4 +.IX Item "-force_flat_namespace" +.IP "\fB\-headerpad_max_install_names\fR" 4 +.IX Item "-headerpad_max_install_names" +.IP "\fB\-image_base\fR" 4 +.IX Item "-image_base" +.IP "\fB\-init\fR" 4 +.IX Item "-init" +.IP "\fB\-install_name\fR" 4 +.IX Item "-install_name" +.IP "\fB\-keep_private_externs\fR" 4 +.IX Item "-keep_private_externs" +.IP "\fB\-multi_module\fR" 4 +.IX Item "-multi_module" +.IP "\fB\-multiply_defined\fR" 4 +.IX Item "-multiply_defined" +.IP "\fB\-multiply_defined_unused\fR" 4 +.IX Item "-multiply_defined_unused" +.IP "\fB\-noall_load\fR" 4 +.IX Item "-noall_load" +.IP "\fB\-no_dead_strip_inits_and_terms\fR" 4 +.IX Item "-no_dead_strip_inits_and_terms" +.IP "\fB\-nofixprebinding\fR" 4 +.IX Item "-nofixprebinding" +.IP "\fB\-nomultidefs\fR" 4 +.IX Item "-nomultidefs" +.IP "\fB\-noprebind\fR" 4 +.IX Item "-noprebind" +.IP "\fB\-noseglinkedit\fR" 4 +.IX Item "-noseglinkedit" +.IP "\fB\-pagezero_size\fR" 4 +.IX Item "-pagezero_size" +.IP "\fB\-prebind\fR" 4 +.IX Item "-prebind" +.IP "\fB\-prebind_all_twolevel_modules\fR" 4 +.IX Item "-prebind_all_twolevel_modules" +.IP "\fB\-private_bundle\fR" 4 +.IX Item "-private_bundle" +.IP "\fB\-read_only_relocs\fR" 4 +.IX Item "-read_only_relocs" +.IP "\fB\-sectalign\fR" 4 +.IX Item "-sectalign" +.IP "\fB\-sectobjectsymbols\fR" 4 +.IX Item "-sectobjectsymbols" +.IP "\fB\-whyload\fR" 4 +.IX Item "-whyload" +.IP "\fB\-seg1addr\fR" 4 +.IX Item "-seg1addr" +.IP "\fB\-sectcreate\fR" 4 +.IX Item "-sectcreate" +.IP "\fB\-sectobjectsymbols\fR" 4 +.IX Item "-sectobjectsymbols" +.IP "\fB\-sectorder\fR" 4 +.IX Item "-sectorder" +.IP "\fB\-segaddr\fR" 4 +.IX Item "-segaddr" +.IP "\fB\-segs_read_only_addr\fR" 4 +.IX Item "-segs_read_only_addr" +.IP "\fB\-segs_read_write_addr\fR" 4 +.IX Item "-segs_read_write_addr" +.IP "\fB\-seg_addr_table\fR" 4 +.IX Item "-seg_addr_table" +.IP "\fB\-seg_addr_table_filename\fR" 4 +.IX Item "-seg_addr_table_filename" +.IP "\fB\-seglinkedit\fR" 4 +.IX Item "-seglinkedit" +.IP "\fB\-segprot\fR" 4 +.IX Item "-segprot" +.IP "\fB\-segs_read_only_addr\fR" 4 +.IX Item "-segs_read_only_addr" +.IP "\fB\-segs_read_write_addr\fR" 4 +.IX Item "-segs_read_write_addr" +.IP "\fB\-single_module\fR" 4 +.IX Item "-single_module" +.IP "\fB\-static\fR" 4 +.IX Item "-static" +.IP "\fB\-sub_library\fR" 4 +.IX Item "-sub_library" +.IP "\fB\-sub_umbrella\fR" 4 +.IX Item "-sub_umbrella" +.IP "\fB\-twolevel_namespace\fR" 4 +.IX Item "-twolevel_namespace" +.IP "\fB\-umbrella\fR" 4 +.IX Item "-umbrella" +.IP "\fB\-undefined\fR" 4 +.IX Item "-undefined" +.IP "\fB\-unexported_symbols_list\fR" 4 +.IX Item "-unexported_symbols_list" +.IP "\fB\-weak_reference_mismatches\fR" 4 +.IX Item "-weak_reference_mismatches" +.IP "\fB\-whatsloaded\fR" 4 +.IX Item "-whatsloaded" +.PD +These options are passed to the Darwin linker. The Darwin linker man page +describes them in detail. +.PP +\fI\s-1DEC\s0 Alpha Options\fR +.IX Subsection "DEC Alpha Options" +.PP +These \fB\-m\fR options are defined for the \s-1DEC\s0 Alpha implementations: +.IP "\fB\-mno\-soft\-float\fR" 4 +.IX Item "-mno-soft-float" +.PD 0 +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD +Use (do not use) the hardware floating-point instructions for +floating-point operations. When \fB\-msoft\-float\fR is specified, +functions in \fIlibgcc.a\fR will be used to perform floating-point +operations. Unless they are replaced by routines that emulate the +floating-point operations, or compiled in such a way as to call such +emulations routines, these routines will issue floating-point +operations. If you are compiling for an Alpha without floating-point +operations, you must ensure that the library is built so as not to call +them. +.Sp +Note that Alpha implementations without floating-point operations are +required to have floating-point registers. +.IP "\fB\-mfp\-reg\fR" 4 +.IX Item "-mfp-reg" +.PD 0 +.IP "\fB\-mno\-fp\-regs\fR" 4 +.IX Item "-mno-fp-regs" +.PD +Generate code that uses (does not use) the floating-point register set. +\&\fB\-mno\-fp\-regs\fR implies \fB\-msoft\-float\fR. If the floating-point +register set is not used, floating point operands are passed in integer +registers as if they were integers and floating-point results are passed +in \f(CW$0\fR instead of \f(CW$f0\fR. This is a non-standard calling sequence, +so any function with a floating-point argument or return value called by code +compiled with \fB\-mno\-fp\-regs\fR must also be compiled with that +option. +.Sp +A typical use of this option is building a kernel that does not use, +and hence need not save and restore, any floating-point registers. +.IP "\fB\-mieee\fR" 4 +.IX Item "-mieee" +The Alpha architecture implements floating-point hardware optimized for +maximum performance. It is mostly compliant with the \s-1IEEE\s0 floating +point standard. However, for full compliance, software assistance is +required. This option generates code fully \s-1IEEE\s0 compliant code +\&\fIexcept\fR that the \fIinexact-flag\fR is not maintained (see below). +If this option is turned on, the preprocessor macro \f(CW\*(C`_IEEE_FP\*(C'\fR is +defined during compilation. The resulting code is less efficient but is +able to correctly support denormalized numbers and exceptional \s-1IEEE\s0 +values such as not-a-number and plus/minus infinity. Other Alpha +compilers call this option \fB\-ieee_with_no_inexact\fR. +.IP "\fB\-mieee\-with\-inexact\fR" 4 +.IX Item "-mieee-with-inexact" +This is like \fB\-mieee\fR except the generated code also maintains +the \s-1IEEE\s0 \fIinexact-flag\fR. Turning on this option causes the +generated code to implement fully-compliant \s-1IEEE\s0 math. In addition to +\&\f(CW\*(C`_IEEE_FP\*(C'\fR, \f(CW\*(C`_IEEE_FP_EXACT\*(C'\fR is defined as a preprocessor +macro. On some Alpha implementations the resulting code may execute +significantly slower than the code generated by default. Since there is +very little code that depends on the \fIinexact-flag\fR, you should +normally not specify this option. Other Alpha compilers call this +option \fB\-ieee_with_inexact\fR. +.IP "\fB\-mfp\-trap\-mode=\fR\fItrap-mode\fR" 4 +.IX Item "-mfp-trap-mode=trap-mode" +This option controls what floating-point related traps are enabled. +Other Alpha compilers call this option \fB\-fptm\fR \fItrap-mode\fR. +The trap mode can be set to one of four values: +.RS 4 +.IP "\fBn\fR" 4 +.IX Item "n" +This is the default (normal) setting. The only traps that are enabled +are the ones that cannot be disabled in software (e.g., division by zero +trap). +.IP "\fBu\fR" 4 +.IX Item "u" +In addition to the traps enabled by \fBn\fR, underflow traps are enabled +as well. +.IP "\fBsu\fR" 4 +.IX Item "su" +Like \fBu\fR, but the instructions are marked to be safe for software +completion (see Alpha architecture manual for details). +.IP "\fBsui\fR" 4 +.IX Item "sui" +Like \fBsu\fR, but inexact traps are enabled as well. +.RE +.RS 4 +.RE +.IP "\fB\-mfp\-rounding\-mode=\fR\fIrounding-mode\fR" 4 +.IX Item "-mfp-rounding-mode=rounding-mode" +Selects the \s-1IEEE\s0 rounding mode. Other Alpha compilers call this option +\&\fB\-fprm\fR \fIrounding-mode\fR. The \fIrounding-mode\fR can be one +of: +.RS 4 +.IP "\fBn\fR" 4 +.IX Item "n" +Normal \s-1IEEE\s0 rounding mode. Floating point numbers are rounded towards +the nearest machine number or towards the even machine number in case +of a tie. +.IP "\fBm\fR" 4 +.IX Item "m" +Round towards minus infinity. +.IP "\fBc\fR" 4 +.IX Item "c" +Chopped rounding mode. Floating point numbers are rounded towards zero. +.IP "\fBd\fR" 4 +.IX Item "d" +Dynamic rounding mode. A field in the floating point control register +(\fIfpcr\fR, see Alpha architecture reference manual) controls the +rounding mode in effect. The C library initializes this register for +rounding towards plus infinity. Thus, unless your program modifies the +\&\fIfpcr\fR, \fBd\fR corresponds to round towards plus infinity. +.RE +.RS 4 +.RE +.IP "\fB\-mtrap\-precision=\fR\fItrap-precision\fR" 4 +.IX Item "-mtrap-precision=trap-precision" +In the Alpha architecture, floating point traps are imprecise. This +means without software assistance it is impossible to recover from a +floating trap and program execution normally needs to be terminated. +\&\s-1GCC\s0 can generate code that can assist operating system trap handlers +in determining the exact location that caused a floating point trap. +Depending on the requirements of an application, different levels of +precisions can be selected: +.RS 4 +.IP "\fBp\fR" 4 +.IX Item "p" +Program precision. This option is the default and means a trap handler +can only identify which program caused a floating point exception. +.IP "\fBf\fR" 4 +.IX Item "f" +Function precision. The trap handler can determine the function that +caused a floating point exception. +.IP "\fBi\fR" 4 +.IX Item "i" +Instruction precision. The trap handler can determine the exact +instruction that caused a floating point exception. +.RE +.RS 4 +.Sp +Other Alpha compilers provide the equivalent options called +\&\fB\-scope_safe\fR and \fB\-resumption_safe\fR. +.RE +.IP "\fB\-mieee\-conformant\fR" 4 +.IX Item "-mieee-conformant" +This option marks the generated code as \s-1IEEE\s0 conformant. You must not +use this option unless you also specify \fB\-mtrap\-precision=i\fR and either +\&\fB\-mfp\-trap\-mode=su\fR or \fB\-mfp\-trap\-mode=sui\fR. Its only effect +is to emit the line \fB.eflag 48\fR in the function prologue of the +generated assembly file. Under \s-1DEC\s0 Unix, this has the effect that +IEEE-conformant math library routines will be linked in. +.IP "\fB\-mbuild\-constants\fR" 4 +.IX Item "-mbuild-constants" +Normally \s-1GCC\s0 examines a 32\- or 64\-bit integer constant to +see if it can construct it from smaller constants in two or three +instructions. If it cannot, it will output the constant as a literal and +generate code to load it from the data segment at runtime. +.Sp +Use this option to require \s-1GCC\s0 to construct \fIall\fR integer constants +using code, even if it takes more instructions (the maximum is six). +.Sp +You would typically use this option to build a shared library dynamic +loader. Itself a shared library, it must relocate itself in memory +before it can find the variables and constants in its own data segment. +.IP "\fB\-malpha\-as\fR" 4 +.IX Item "-malpha-as" +.PD 0 +.IP "\fB\-mgas\fR" 4 +.IX Item "-mgas" +.PD +Select whether to generate code to be assembled by the vendor-supplied +assembler (\fB\-malpha\-as\fR) or by the \s-1GNU\s0 assembler \fB\-mgas\fR. +.IP "\fB\-mbwx\fR" 4 +.IX Item "-mbwx" +.PD 0 +.IP "\fB\-mno\-bwx\fR" 4 +.IX Item "-mno-bwx" +.IP "\fB\-mcix\fR" 4 +.IX Item "-mcix" +.IP "\fB\-mno\-cix\fR" 4 +.IX Item "-mno-cix" +.IP "\fB\-mfix\fR" 4 +.IX Item "-mfix" +.IP "\fB\-mno\-fix\fR" 4 +.IX Item "-mno-fix" +.IP "\fB\-mmax\fR" 4 +.IX Item "-mmax" +.IP "\fB\-mno\-max\fR" 4 +.IX Item "-mno-max" +.PD +Indicate whether \s-1GCC\s0 should generate code to use the optional \s-1BWX\s0, +\&\s-1CIX\s0, \s-1FIX\s0 and \s-1MAX\s0 instruction sets. The default is to use the instruction +sets supported by the \s-1CPU\s0 type specified via \fB\-mcpu=\fR option or that +of the \s-1CPU\s0 on which \s-1GCC\s0 was built if none was specified. +.IP "\fB\-mfloat\-vax\fR" 4 +.IX Item "-mfloat-vax" +.PD 0 +.IP "\fB\-mfloat\-ieee\fR" 4 +.IX Item "-mfloat-ieee" +.PD +Generate code that uses (does not use) \s-1VAX\s0 F and G floating point +arithmetic instead of \s-1IEEE\s0 single and double precision. +.IP "\fB\-mexplicit\-relocs\fR" 4 +.IX Item "-mexplicit-relocs" +.PD 0 +.IP "\fB\-mno\-explicit\-relocs\fR" 4 +.IX Item "-mno-explicit-relocs" +.PD +Older Alpha assemblers provided no way to generate symbol relocations +except via assembler macros. Use of these macros does not allow +optimal instruction scheduling. \s-1GNU\s0 binutils as of version 2.12 +supports a new syntax that allows the compiler to explicitly mark +which relocations should apply to which instructions. This option +is mostly useful for debugging, as \s-1GCC\s0 detects the capabilities of +the assembler when it is built and sets the default accordingly. +.IP "\fB\-msmall\-data\fR" 4 +.IX Item "-msmall-data" +.PD 0 +.IP "\fB\-mlarge\-data\fR" 4 +.IX Item "-mlarge-data" +.PD +When \fB\-mexplicit\-relocs\fR is in effect, static data is +accessed via \fIgp-relative\fR relocations. When \fB\-msmall\-data\fR +is used, objects 8 bytes long or smaller are placed in a \fIsmall data area\fR +(the \f(CW\*(C`.sdata\*(C'\fR and \f(CW\*(C`.sbss\*(C'\fR sections) and are accessed via +16\-bit relocations off of the \f(CW$gp\fR register. This limits the +size of the small data area to 64KB, but allows the variables to be +directly accessed via a single instruction. +.Sp +The default is \fB\-mlarge\-data\fR. With this option the data area +is limited to just below 2GB. Programs that require more than 2GB of +data must use \f(CW\*(C`malloc\*(C'\fR or \f(CW\*(C`mmap\*(C'\fR to allocate the data in the +heap instead of in the program's data segment. +.Sp +When generating code for shared libraries, \fB\-fpic\fR implies +\&\fB\-msmall\-data\fR and \fB\-fPIC\fR implies \fB\-mlarge\-data\fR. +.IP "\fB\-msmall\-text\fR" 4 +.IX Item "-msmall-text" +.PD 0 +.IP "\fB\-mlarge\-text\fR" 4 +.IX Item "-mlarge-text" +.PD +When \fB\-msmall\-text\fR is used, the compiler assumes that the +code of the entire program (or shared library) fits in 4MB, and is +thus reachable with a branch instruction. When \fB\-msmall\-data\fR +is used, the compiler can assume that all local symbols share the +same \f(CW$gp\fR value, and thus reduce the number of instructions +required for a function call from 4 to 1. +.Sp +The default is \fB\-mlarge\-text\fR. +.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 +.IX Item "-mcpu=cpu_type" +Set the instruction set and instruction scheduling parameters for +machine type \fIcpu_type\fR. You can specify either the \fB\s-1EV\s0\fR +style name or the corresponding chip number. \s-1GCC\s0 supports scheduling +parameters for the \s-1EV4\s0, \s-1EV5\s0 and \s-1EV6\s0 family of processors and will +choose the default values for the instruction set from the processor +you specify. If you do not specify a processor type, \s-1GCC\s0 will default +to the processor on which the compiler was built. +.Sp +Supported values for \fIcpu_type\fR are +.RS 4 +.IP "\fBev4\fR" 4 +.IX Item "ev4" +.PD 0 +.IP "\fBev45\fR" 4 +.IX Item "ev45" +.IP "\fB21064\fR" 4 +.IX Item "21064" +.PD +Schedules as an \s-1EV4\s0 and has no instruction set extensions. +.IP "\fBev5\fR" 4 +.IX Item "ev5" +.PD 0 +.IP "\fB21164\fR" 4 +.IX Item "21164" +.PD +Schedules as an \s-1EV5\s0 and has no instruction set extensions. +.IP "\fBev56\fR" 4 +.IX Item "ev56" +.PD 0 +.IP "\fB21164a\fR" 4 +.IX Item "21164a" +.PD +Schedules as an \s-1EV5\s0 and supports the \s-1BWX\s0 extension. +.IP "\fBpca56\fR" 4 +.IX Item "pca56" +.PD 0 +.IP "\fB21164pc\fR" 4 +.IX Item "21164pc" +.IP "\fB21164PC\fR" 4 +.IX Item "21164PC" +.PD +Schedules as an \s-1EV5\s0 and supports the \s-1BWX\s0 and \s-1MAX\s0 extensions. +.IP "\fBev6\fR" 4 +.IX Item "ev6" +.PD 0 +.IP "\fB21264\fR" 4 +.IX Item "21264" +.PD +Schedules as an \s-1EV6\s0 and supports the \s-1BWX\s0, \s-1FIX\s0, and \s-1MAX\s0 extensions. +.IP "\fBev67\fR" 4 +.IX Item "ev67" +.PD 0 +.IP "\fB21264a\fR" 4 +.IX Item "21264a" +.PD +Schedules as an \s-1EV6\s0 and supports the \s-1BWX\s0, \s-1CIX\s0, \s-1FIX\s0, and \s-1MAX\s0 extensions. +.RE +.RS 4 +.Sp +Native Linux/GNU toolchains also support the value \fBnative\fR, +which selects the best architecture option for the host processor. +\&\fB\-mcpu=native\fR has no effect if \s-1GCC\s0 does not recognize +the processor. +.RE +.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4 +.IX Item "-mtune=cpu_type" +Set only the instruction scheduling parameters for machine type +\&\fIcpu_type\fR. The instruction set is not changed. +.Sp +Native Linux/GNU toolchains also support the value \fBnative\fR, +which selects the best architecture option for the host processor. +\&\fB\-mtune=native\fR has no effect if \s-1GCC\s0 does not recognize +the processor. +.IP "\fB\-mmemory\-latency=\fR\fItime\fR" 4 +.IX Item "-mmemory-latency=time" +Sets the latency the scheduler should assume for typical memory +references as seen by the application. This number is highly +dependent on the memory access patterns used by the application +and the size of the external cache on the machine. +.Sp +Valid options for \fItime\fR are +.RS 4 +.IP "\fInumber\fR" 4 +.IX Item "number" +A decimal number representing clock cycles. +.IP "\fBL1\fR" 4 +.IX Item "L1" +.PD 0 +.IP "\fBL2\fR" 4 +.IX Item "L2" +.IP "\fBL3\fR" 4 +.IX Item "L3" +.IP "\fBmain\fR" 4 +.IX Item "main" +.PD +The compiler contains estimates of the number of clock cycles for +\&\*(L"typical\*(R" \s-1EV4\s0 & \s-1EV5\s0 hardware for the Level 1, 2 & 3 caches +(also called Dcache, Scache, and Bcache), as well as to main memory. +Note that L3 is only valid for \s-1EV5\s0. +.RE +.RS 4 +.RE +.PP +\fI\s-1DEC\s0 Alpha/VMS Options\fR +.IX Subsection "DEC Alpha/VMS Options" +.PP +These \fB\-m\fR options are defined for the \s-1DEC\s0 Alpha/VMS implementations: +.IP "\fB\-mvms\-return\-codes\fR" 4 +.IX Item "-mvms-return-codes" +Return \s-1VMS\s0 condition codes from main. The default is to return \s-1POSIX\s0 +style condition (e.g. error) codes. +.IP "\fB\-mdebug\-main=\fR\fIprefix\fR" 4 +.IX Item "-mdebug-main=prefix" +Flag the first routine whose name starts with \fIprefix\fR as the main +routine for the debugger. +.IP "\fB\-mmalloc64\fR" 4 +.IX Item "-mmalloc64" +Default to 64bit memory allocation routines. +.PP +\fI\s-1FR30\s0 Options\fR +.IX Subsection "FR30 Options" +.PP +These options are defined specifically for the \s-1FR30\s0 port. +.IP "\fB\-msmall\-model\fR" 4 +.IX Item "-msmall-model" +Use the small address space model. This can produce smaller code, but +it does assume that all symbolic values and addresses will fit into a +20\-bit range. +.IP "\fB\-mno\-lsim\fR" 4 +.IX Item "-mno-lsim" +Assume that run-time support has been provided and so there is no need +to include the simulator library (\fIlibsim.a\fR) on the linker +command line. +.PP +\fI\s-1FRV\s0 Options\fR +.IX Subsection "FRV Options" +.IP "\fB\-mgpr\-32\fR" 4 +.IX Item "-mgpr-32" +Only use the first 32 general purpose registers. +.IP "\fB\-mgpr\-64\fR" 4 +.IX Item "-mgpr-64" +Use all 64 general purpose registers. +.IP "\fB\-mfpr\-32\fR" 4 +.IX Item "-mfpr-32" +Use only the first 32 floating point registers. +.IP "\fB\-mfpr\-64\fR" 4 +.IX Item "-mfpr-64" +Use all 64 floating point registers +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +Use hardware instructions for floating point operations. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Use library routines for floating point operations. +.IP "\fB\-malloc\-cc\fR" 4 +.IX Item "-malloc-cc" +Dynamically allocate condition code registers. +.IP "\fB\-mfixed\-cc\fR" 4 +.IX Item "-mfixed-cc" +Do not try to dynamically allocate condition code registers, only +use \f(CW\*(C`icc0\*(C'\fR and \f(CW\*(C`fcc0\*(C'\fR. +.IP "\fB\-mdword\fR" 4 +.IX Item "-mdword" +Change \s-1ABI\s0 to use double word insns. +.IP "\fB\-mno\-dword\fR" 4 +.IX Item "-mno-dword" +Do not use double word instructions. +.IP "\fB\-mdouble\fR" 4 +.IX Item "-mdouble" +Use floating point double instructions. +.IP "\fB\-mno\-double\fR" 4 +.IX Item "-mno-double" +Do not use floating point double instructions. +.IP "\fB\-mmedia\fR" 4 +.IX Item "-mmedia" +Use media instructions. +.IP "\fB\-mno\-media\fR" 4 +.IX Item "-mno-media" +Do not use media instructions. +.IP "\fB\-mmuladd\fR" 4 +.IX Item "-mmuladd" +Use multiply and add/subtract instructions. +.IP "\fB\-mno\-muladd\fR" 4 +.IX Item "-mno-muladd" +Do not use multiply and add/subtract instructions. +.IP "\fB\-mfdpic\fR" 4 +.IX Item "-mfdpic" +Select the \s-1FDPIC\s0 \s-1ABI\s0, that uses function descriptors to represent +pointers to functions. Without any PIC/PIE\-related options, it +implies \fB\-fPIE\fR. With \fB\-fpic\fR or \fB\-fpie\fR, it +assumes \s-1GOT\s0 entries and small data are within a 12\-bit range from the +\&\s-1GOT\s0 base address; with \fB\-fPIC\fR or \fB\-fPIE\fR, \s-1GOT\s0 offsets +are computed with 32 bits. +With a \fBbfin-elf\fR target, this option implies \fB\-msim\fR. +.IP "\fB\-minline\-plt\fR" 4 +.IX Item "-minline-plt" +Enable inlining of \s-1PLT\s0 entries in function calls to functions that are +not known to bind locally. It has no effect without \fB\-mfdpic\fR. +It's enabled by default if optimizing for speed and compiling for +shared libraries (i.e., \fB\-fPIC\fR or \fB\-fpic\fR), or when an +optimization option such as \fB\-O3\fR or above is present in the +command line. +.IP "\fB\-mTLS\fR" 4 +.IX Item "-mTLS" +Assume a large \s-1TLS\s0 segment when generating thread-local code. +.IP "\fB\-mtls\fR" 4 +.IX Item "-mtls" +Do not assume a large \s-1TLS\s0 segment when generating thread-local code. +.IP "\fB\-mgprel\-ro\fR" 4 +.IX Item "-mgprel-ro" +Enable the use of \f(CW\*(C`GPREL\*(C'\fR relocations in the \s-1FDPIC\s0 \s-1ABI\s0 for data +that is known to be in read-only sections. It's enabled by default, +except for \fB\-fpic\fR or \fB\-fpie\fR: even though it may help +make the global offset table smaller, it trades 1 instruction for 4. +With \fB\-fPIC\fR or \fB\-fPIE\fR, it trades 3 instructions for 4, +one of which may be shared by multiple symbols, and it avoids the need +for a \s-1GOT\s0 entry for the referenced symbol, so it's more likely to be a +win. If it is not, \fB\-mno\-gprel\-ro\fR can be used to disable it. +.IP "\fB\-multilib\-library\-pic\fR" 4 +.IX Item "-multilib-library-pic" +Link with the (library, not \s-1FD\s0) pic libraries. It's implied by +\&\fB\-mlibrary\-pic\fR, as well as by \fB\-fPIC\fR and +\&\fB\-fpic\fR without \fB\-mfdpic\fR. You should never have to use +it explicitly. +.IP "\fB\-mlinked\-fp\fR" 4 +.IX Item "-mlinked-fp" +Follow the \s-1EABI\s0 requirement of always creating a frame pointer whenever +a stack frame is allocated. This option is enabled by default and can +be disabled with \fB\-mno\-linked\-fp\fR. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +Use indirect addressing to call functions outside the current +compilation unit. This allows the functions to be placed anywhere +within the 32\-bit address space. +.IP "\fB\-malign\-labels\fR" 4 +.IX Item "-malign-labels" +Try to align labels to an 8\-byte boundary by inserting nops into the +previous packet. This option only has an effect when \s-1VLIW\s0 packing +is enabled. It doesn't create new packets; it merely adds nops to +existing ones. +.IP "\fB\-mlibrary\-pic\fR" 4 +.IX Item "-mlibrary-pic" +Generate position-independent \s-1EABI\s0 code. +.IP "\fB\-macc\-4\fR" 4 +.IX Item "-macc-4" +Use only the first four media accumulator registers. +.IP "\fB\-macc\-8\fR" 4 +.IX Item "-macc-8" +Use all eight media accumulator registers. +.IP "\fB\-mpack\fR" 4 +.IX Item "-mpack" +Pack \s-1VLIW\s0 instructions. +.IP "\fB\-mno\-pack\fR" 4 +.IX Item "-mno-pack" +Do not pack \s-1VLIW\s0 instructions. +.IP "\fB\-mno\-eflags\fR" 4 +.IX Item "-mno-eflags" +Do not mark \s-1ABI\s0 switches in e_flags. +.IP "\fB\-mcond\-move\fR" 4 +.IX Item "-mcond-move" +Enable the use of conditional-move instructions (default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-cond\-move\fR" 4 +.IX Item "-mno-cond-move" +Disable the use of conditional-move instructions. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mscc\fR" 4 +.IX Item "-mscc" +Enable the use of conditional set instructions (default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-scc\fR" 4 +.IX Item "-mno-scc" +Disable the use of conditional set instructions. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mcond\-exec\fR" 4 +.IX Item "-mcond-exec" +Enable the use of conditional execution (default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-cond\-exec\fR" 4 +.IX Item "-mno-cond-exec" +Disable the use of conditional execution. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mvliw\-branch\fR" 4 +.IX Item "-mvliw-branch" +Run a pass to pack branches into \s-1VLIW\s0 instructions (default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-vliw\-branch\fR" 4 +.IX Item "-mno-vliw-branch" +Do not run a pass to pack branches into \s-1VLIW\s0 instructions. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mmulti\-cond\-exec\fR" 4 +.IX Item "-mmulti-cond-exec" +Enable optimization of \f(CW\*(C`&&\*(C'\fR and \f(CW\*(C`||\*(C'\fR in conditional execution +(default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-multi\-cond\-exec\fR" 4 +.IX Item "-mno-multi-cond-exec" +Disable optimization of \f(CW\*(C`&&\*(C'\fR and \f(CW\*(C`||\*(C'\fR in conditional execution. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mnested\-cond\-exec\fR" 4 +.IX Item "-mnested-cond-exec" +Enable nested conditional execution optimizations (default). +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-mno\-nested\-cond\-exec\fR" 4 +.IX Item "-mno-nested-cond-exec" +Disable nested conditional execution optimizations. +.Sp +This switch is mainly for debugging the compiler and will likely be removed +in a future version. +.IP "\fB\-moptimize\-membar\fR" 4 +.IX Item "-moptimize-membar" +This switch removes redundant \f(CW\*(C`membar\*(C'\fR instructions from the +compiler generated code. It is enabled by default. +.IP "\fB\-mno\-optimize\-membar\fR" 4 +.IX Item "-mno-optimize-membar" +This switch disables the automatic removal of redundant \f(CW\*(C`membar\*(C'\fR +instructions from the generated code. +.IP "\fB\-mtomcat\-stats\fR" 4 +.IX Item "-mtomcat-stats" +Cause gas to print out tomcat statistics. +.IP "\fB\-mcpu=\fR\fIcpu\fR" 4 +.IX Item "-mcpu=cpu" +Select the processor type for which to generate code. Possible values are +\&\fBfrv\fR, \fBfr550\fR, \fBtomcat\fR, \fBfr500\fR, \fBfr450\fR, +\&\fBfr405\fR, \fBfr400\fR, \fBfr300\fR and \fBsimple\fR. +.PP +\fIGNU/Linux Options\fR +.IX Subsection "GNU/Linux Options" +.PP +These \fB\-m\fR options are defined for GNU/Linux targets: +.IP "\fB\-mglibc\fR" 4 +.IX Item "-mglibc" +Use the \s-1GNU\s0 C library. This is the default except +on \fB*\-*\-linux\-*uclibc*\fR and \fB*\-*\-linux\-*android*\fR targets. +.IP "\fB\-muclibc\fR" 4 +.IX Item "-muclibc" +Use uClibc C library. This is the default on +\&\fB*\-*\-linux\-*uclibc*\fR targets. +.IP "\fB\-mbionic\fR" 4 +.IX Item "-mbionic" +Use Bionic C library. This is the default on +\&\fB*\-*\-linux\-*android*\fR targets. +.IP "\fB\-mandroid\fR" 4 +.IX Item "-mandroid" +Compile code compatible with Android platform. This is the default on +\&\fB*\-*\-linux\-*android*\fR targets. +.Sp +When compiling, this option enables \fB\-mbionic\fR, \fB\-fPIC\fR, +\&\fB\-fno\-exceptions\fR and \fB\-fno\-rtti\fR by default. When linking, +this option makes the \s-1GCC\s0 driver pass Android-specific options to the linker. +Finally, this option causes the preprocessor macro \f(CW\*(C`_\|_ANDROID_\|_\*(C'\fR +to be defined. +.IP "\fB\-tno\-android\-cc\fR" 4 +.IX Item "-tno-android-cc" +Disable compilation effects of \fB\-mandroid\fR, i.e., do not enable +\&\fB\-mbionic\fR, \fB\-fPIC\fR, \fB\-fno\-exceptions\fR and +\&\fB\-fno\-rtti\fR by default. +.IP "\fB\-tno\-android\-ld\fR" 4 +.IX Item "-tno-android-ld" +Disable linking effects of \fB\-mandroid\fR, i.e., pass standard Linux +linking options to the linker. +.PP +\fIH8/300 Options\fR +.IX Subsection "H8/300 Options" +.PP +These \fB\-m\fR options are defined for the H8/300 implementations: +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +Shorten some address references at link time, when possible; uses the +linker option \fB\-relax\fR. +.IP "\fB\-mh\fR" 4 +.IX Item "-mh" +Generate code for the H8/300H. +.IP "\fB\-ms\fR" 4 +.IX Item "-ms" +Generate code for the H8S. +.IP "\fB\-mn\fR" 4 +.IX Item "-mn" +Generate code for the H8S and H8/300H in the normal mode. This switch +must be used either with \fB\-mh\fR or \fB\-ms\fR. +.IP "\fB\-ms2600\fR" 4 +.IX Item "-ms2600" +Generate code for the H8S/2600. This switch must be used with \fB\-ms\fR. +.IP "\fB\-mint32\fR" 4 +.IX Item "-mint32" +Make \f(CW\*(C`int\*(C'\fR data 32 bits by default. +.IP "\fB\-malign\-300\fR" 4 +.IX Item "-malign-300" +On the H8/300H and H8S, use the same alignment rules as for the H8/300. +The default for the H8/300H and H8S is to align longs and floats on 4 +byte boundaries. +\&\fB\-malign\-300\fR causes them to be aligned on 2 byte boundaries. +This option has no effect on the H8/300. +.PP +\fI\s-1HPPA\s0 Options\fR +.IX Subsection "HPPA Options" +.PP +These \fB\-m\fR options are defined for the \s-1HPPA\s0 family of computers: +.IP "\fB\-march=\fR\fIarchitecture-type\fR" 4 +.IX Item "-march=architecture-type" +Generate code for the specified architecture. The choices for +\&\fIarchitecture-type\fR are \fB1.0\fR for \s-1PA\s0 1.0, \fB1.1\fR for \s-1PA\s0 +1.1, and \fB2.0\fR for \s-1PA\s0 2.0 processors. Refer to +\&\fI/usr/lib/sched.models\fR on an HP-UX system to determine the proper +architecture option for your machine. Code compiled for lower numbered +architectures will run on higher numbered architectures, but not the +other way around. +.IP "\fB\-mpa\-risc\-1\-0\fR" 4 +.IX Item "-mpa-risc-1-0" +.PD 0 +.IP "\fB\-mpa\-risc\-1\-1\fR" 4 +.IX Item "-mpa-risc-1-1" +.IP "\fB\-mpa\-risc\-2\-0\fR" 4 +.IX Item "-mpa-risc-2-0" +.PD +Synonyms for \fB\-march=1.0\fR, \fB\-march=1.1\fR, and \fB\-march=2.0\fR respectively. +.IP "\fB\-mbig\-switch\fR" 4 +.IX Item "-mbig-switch" +Generate code suitable for big switch tables. Use this option only if +the assembler/linker complain about out of range branches within a switch +table. +.IP "\fB\-mjump\-in\-delay\fR" 4 +.IX Item "-mjump-in-delay" +Fill delay slots of function calls with unconditional jump instructions +by modifying the return pointer for the function call to be the target +of the conditional jump. +.IP "\fB\-mdisable\-fpregs\fR" 4 +.IX Item "-mdisable-fpregs" +Prevent floating point registers from being used in any manner. This is +necessary for compiling kernels which perform lazy context switching of +floating point registers. If you use this option and attempt to perform +floating point operations, the compiler will abort. +.IP "\fB\-mdisable\-indexing\fR" 4 +.IX Item "-mdisable-indexing" +Prevent the compiler from using indexing address modes. This avoids some +rather obscure problems when compiling \s-1MIG\s0 generated code under \s-1MACH\s0. +.IP "\fB\-mno\-space\-regs\fR" 4 +.IX Item "-mno-space-regs" +Generate code that assumes the target has no space registers. This allows +\&\s-1GCC\s0 to generate faster indirect calls and use unscaled index address modes. +.Sp +Such code is suitable for level 0 \s-1PA\s0 systems and kernels. +.IP "\fB\-mfast\-indirect\-calls\fR" 4 +.IX Item "-mfast-indirect-calls" +Generate code that assumes calls never cross space boundaries. This +allows \s-1GCC\s0 to emit code which performs faster indirect calls. +.Sp +This option will not work in the presence of shared libraries or nested +functions. +.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 +.IX Item "-mfixed-range=register-range" +Generate code treating the given register range as fixed registers. +A fixed register is one that the register allocator can not use. This is +useful when compiling kernel code. A register range is specified as +two registers separated by a dash. Multiple register ranges can be +specified separated by a comma. +.IP "\fB\-mlong\-load\-store\fR" 4 +.IX Item "-mlong-load-store" +Generate 3\-instruction load and store sequences as sometimes required by +the HP-UX 10 linker. This is equivalent to the \fB+k\fR option to +the \s-1HP\s0 compilers. +.IP "\fB\-mportable\-runtime\fR" 4 +.IX Item "-mportable-runtime" +Use the portable calling conventions proposed by \s-1HP\s0 for \s-1ELF\s0 systems. +.IP "\fB\-mgas\fR" 4 +.IX Item "-mgas" +Enable the use of assembler directives only \s-1GAS\s0 understands. +.IP "\fB\-mschedule=\fR\fIcpu-type\fR" 4 +.IX Item "-mschedule=cpu-type" +Schedule code according to the constraints for the machine type +\&\fIcpu-type\fR. The choices for \fIcpu-type\fR are \fB700\fR +\&\fB7100\fR, \fB7100LC\fR, \fB7200\fR, \fB7300\fR and \fB8000\fR. Refer +to \fI/usr/lib/sched.models\fR on an HP-UX system to determine the +proper scheduling option for your machine. The default scheduling is +\&\fB8000\fR. +.IP "\fB\-mlinker\-opt\fR" 4 +.IX Item "-mlinker-opt" +Enable the optimization pass in the HP-UX linker. Note this makes symbolic +debugging impossible. It also triggers a bug in the HP-UX 8 and HP-UX 9 +linkers in which they give bogus error messages when linking some programs. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Generate output containing library calls for floating point. +\&\fBWarning:\fR the requisite libraries are not available for all \s-1HPPA\s0 +targets. Normally the facilities of the machine's usual C compiler are +used, but this cannot be done directly in cross-compilation. You must make +your own arrangements to provide suitable library functions for +cross-compilation. +.Sp +\&\fB\-msoft\-float\fR changes the calling convention in the output file; +therefore, it is only useful if you compile \fIall\fR of a program with +this option. In particular, you need to compile \fIlibgcc.a\fR, the +library that comes with \s-1GCC\s0, with \fB\-msoft\-float\fR in order for +this to work. +.IP "\fB\-msio\fR" 4 +.IX Item "-msio" +Generate the predefine, \f(CW\*(C`_SIO\*(C'\fR, for server \s-1IO\s0. The default is +\&\fB\-mwsio\fR. This generates the predefines, \f(CW\*(C`_\|_hp9000s700\*(C'\fR, +\&\f(CW\*(C`_\|_hp9000s700_\|_\*(C'\fR and \f(CW\*(C`_WSIO\*(C'\fR, for workstation \s-1IO\s0. These +options are available under HP-UX and HI-UX. +.IP "\fB\-mgnu\-ld\fR" 4 +.IX Item "-mgnu-ld" +Use \s-1GNU\s0 ld specific options. This passes \fB\-shared\fR to ld when +building a shared library. It is the default when \s-1GCC\s0 is configured, +explicitly or implicitly, with the \s-1GNU\s0 linker. This option does not +have any affect on which ld is called, it only changes what parameters +are passed to that ld. The ld that is called is determined by the +\&\fB\-\-with\-ld\fR configure option, \s-1GCC\s0's program search path, and +finally by the user's \fB\s-1PATH\s0\fR. The linker used by \s-1GCC\s0 can be printed +using \fBwhich `gcc \-print\-prog\-name=ld`\fR. This option is only available +on the 64 bit HP-UX \s-1GCC\s0, i.e. configured with \fBhppa*64*\-*\-hpux*\fR. +.IP "\fB\-mhp\-ld\fR" 4 +.IX Item "-mhp-ld" +Use \s-1HP\s0 ld specific options. This passes \fB\-b\fR to ld when building +a shared library and passes \fB+Accept TypeMismatch\fR to ld on all +links. It is the default when \s-1GCC\s0 is configured, explicitly or +implicitly, with the \s-1HP\s0 linker. This option does not have any affect on +which ld is called, it only changes what parameters are passed to that +ld. The ld that is called is determined by the \fB\-\-with\-ld\fR +configure option, \s-1GCC\s0's program search path, and finally by the user's +\&\fB\s-1PATH\s0\fR. The linker used by \s-1GCC\s0 can be printed using \fBwhich +`gcc \-print\-prog\-name=ld`\fR. This option is only available on the 64 bit +HP-UX \s-1GCC\s0, i.e. configured with \fBhppa*64*\-*\-hpux*\fR. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +Generate code that uses long call sequences. This ensures that a call +is always able to reach linker generated stubs. The default is to generate +long calls only when the distance from the call site to the beginning +of the function or translation unit, as the case may be, exceeds a +predefined limit set by the branch type being used. The limits for +normal calls are 7,600,000 and 240,000 bytes, respectively for the +\&\s-1PA\s0 2.0 and \s-1PA\s0 1.X architectures. Sibcalls are always limited at +240,000 bytes. +.Sp +Distances are measured from the beginning of functions when using the +\&\fB\-ffunction\-sections\fR option, or when using the \fB\-mgas\fR +and \fB\-mno\-portable\-runtime\fR options together under HP-UX with +the \s-1SOM\s0 linker. +.Sp +It is normally not desirable to use this option as it will degrade +performance. However, it may be useful in large applications, +particularly when partial linking is used to build the application. +.Sp +The types of long calls used depends on the capabilities of the +assembler and linker, and the type of code being generated. The +impact on systems that support long absolute calls, and long pic +symbol-difference or pc-relative calls should be relatively small. +However, an indirect call is used on 32\-bit \s-1ELF\s0 systems in pic code +and it is quite long. +.IP "\fB\-munix=\fR\fIunix-std\fR" 4 +.IX Item "-munix=unix-std" +Generate compiler predefines and select a startfile for the specified +\&\s-1UNIX\s0 standard. The choices for \fIunix-std\fR are \fB93\fR, \fB95\fR +and \fB98\fR. \fB93\fR is supported on all HP-UX versions. \fB95\fR +is available on HP-UX 10.10 and later. \fB98\fR is available on HP-UX +11.11 and later. The default values are \fB93\fR for HP-UX 10.00, +\&\fB95\fR for HP-UX 10.10 though to 11.00, and \fB98\fR for HP-UX 11.11 +and later. +.Sp +\&\fB\-munix=93\fR provides the same predefines as \s-1GCC\s0 3.3 and 3.4. +\&\fB\-munix=95\fR provides additional predefines for \f(CW\*(C`XOPEN_UNIX\*(C'\fR +and \f(CW\*(C`_XOPEN_SOURCE_EXTENDED\*(C'\fR, and the startfile \fIunix95.o\fR. +\&\fB\-munix=98\fR provides additional predefines for \f(CW\*(C`_XOPEN_UNIX\*(C'\fR, +\&\f(CW\*(C`_XOPEN_SOURCE_EXTENDED\*(C'\fR, \f(CW\*(C`_INCLUDE_\|_STDC_A1_SOURCE\*(C'\fR and +\&\f(CW\*(C`_INCLUDE_XOPEN_SOURCE_500\*(C'\fR, and the startfile \fIunix98.o\fR. +.Sp +It is \fIimportant\fR to note that this option changes the interfaces +for various library routines. It also affects the operational behavior +of the C library. Thus, \fIextreme\fR care is needed in using this +option. +.Sp +Library code that is intended to operate with more than one \s-1UNIX\s0 +standard must test, set and restore the variable \fI_\|_xpg4_extended_mask\fR +as appropriate. Most \s-1GNU\s0 software doesn't provide this capability. +.IP "\fB\-nolibdld\fR" 4 +.IX Item "-nolibdld" +Suppress the generation of link options to search libdld.sl when the +\&\fB\-static\fR option is specified on HP-UX 10 and later. +.IP "\fB\-static\fR" 4 +.IX Item "-static" +The HP-UX implementation of setlocale in libc has a dependency on +libdld.sl. There isn't an archive version of libdld.sl. Thus, +when the \fB\-static\fR option is specified, special link options +are needed to resolve this dependency. +.Sp +On HP-UX 10 and later, the \s-1GCC\s0 driver adds the necessary options to +link with libdld.sl when the \fB\-static\fR option is specified. +This causes the resulting binary to be dynamic. On the 64\-bit port, +the linkers generate dynamic binaries by default in any case. The +\&\fB\-nolibdld\fR option can be used to prevent the \s-1GCC\s0 driver from +adding these link options. +.IP "\fB\-threads\fR" 4 +.IX Item "-threads" +Add support for multithreading with the \fIdce thread\fR library +under HP-UX. This option sets flags for both the preprocessor and +linker. +.PP +\fIIntel 386 and \s-1AMD\s0 x86\-64 Options\fR +.IX Subsection "Intel 386 and AMD x86-64 Options" +.PP +These \fB\-m\fR options are defined for the i386 and x86\-64 family of +computers: +.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 +.IX Item "-mtune=cpu-type" +Tune to \fIcpu-type\fR everything applicable about the generated code, except +for the \s-1ABI\s0 and the set of available instructions. The choices for +\&\fIcpu-type\fR are: +.RS 4 +.IP "\fIgeneric\fR" 4 +.IX Item "generic" +Produce code optimized for the most common \s-1IA32/AMD64/EM64T\s0 processors. +If you know the \s-1CPU\s0 on which your code will run, then you should use +the corresponding \fB\-mtune\fR option instead of +\&\fB\-mtune=generic\fR. But, if you do not know exactly what \s-1CPU\s0 users +of your application will have, then you should use this option. +.Sp +As new processors are deployed in the marketplace, the behavior of this +option will change. Therefore, if you upgrade to a newer version of +\&\s-1GCC\s0, the code generated option will change to reflect the processors +that were most common when that version of \s-1GCC\s0 was released. +.Sp +There is no \fB\-march=generic\fR option because \fB\-march\fR +indicates the instruction set the compiler can use, and there is no +generic instruction set applicable to all processors. In contrast, +\&\fB\-mtune\fR indicates the processor (or, in this case, collection of +processors) for which the code is optimized. +.IP "\fInative\fR" 4 +.IX Item "native" +This selects the \s-1CPU\s0 to tune for at compilation time by determining +the processor type of the compiling machine. Using \fB\-mtune=native\fR +will produce code optimized for the local machine under the constraints +of the selected instruction set. Using \fB\-march=native\fR will +enable all instruction subsets supported by the local machine (hence +the result might not run on different machines). +.IP "\fIi386\fR" 4 +.IX Item "i386" +Original Intel's i386 \s-1CPU\s0. +.IP "\fIi486\fR" 4 +.IX Item "i486" +Intel's i486 \s-1CPU\s0. (No scheduling is implemented for this chip.) +.IP "\fIi586, pentium\fR" 4 +.IX Item "i586, pentium" +Intel Pentium \s-1CPU\s0 with no \s-1MMX\s0 support. +.IP "\fIpentium-mmx\fR" 4 +.IX Item "pentium-mmx" +Intel PentiumMMX \s-1CPU\s0 based on Pentium core with \s-1MMX\s0 instruction set support. +.IP "\fIpentiumpro\fR" 4 +.IX Item "pentiumpro" +Intel PentiumPro \s-1CPU\s0. +.IP "\fIi686\fR" 4 +.IX Item "i686" +Same as \f(CW\*(C`generic\*(C'\fR, but when used as \f(CW\*(C`march\*(C'\fR option, PentiumPro +instruction set will be used, so the code will run on all i686 family chips. +.IP "\fIpentium2\fR" 4 +.IX Item "pentium2" +Intel Pentium2 \s-1CPU\s0 based on PentiumPro core with \s-1MMX\s0 instruction set support. +.IP "\fIpentium3, pentium3m\fR" 4 +.IX Item "pentium3, pentium3m" +Intel Pentium3 \s-1CPU\s0 based on PentiumPro core with \s-1MMX\s0 and \s-1SSE\s0 instruction set +support. +.IP "\fIpentium-m\fR" 4 +.IX Item "pentium-m" +Low power version of Intel Pentium3 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0 and \s-1SSE2\s0 instruction set +support. Used by Centrino notebooks. +.IP "\fIpentium4, pentium4m\fR" 4 +.IX Item "pentium4, pentium4m" +Intel Pentium4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0 and \s-1SSE2\s0 instruction set support. +.IP "\fIprescott\fR" 4 +.IX Item "prescott" +Improved version of Intel Pentium4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0 and \s-1SSE3\s0 instruction +set support. +.IP "\fInocona\fR" 4 +.IX Item "nocona" +Improved version of Intel Pentium4 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, +\&\s-1SSE2\s0 and \s-1SSE3\s0 instruction set support. +.IP "\fIcore2\fR" 4 +.IX Item "core2" +Intel Core2 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0 +instruction set support. +.IP "\fIcorei7\fR" 4 +.IX Item "corei7" +Intel Core i7 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, \s-1SSE4\s0.1 +and \s-1SSE4\s0.2 instruction set support. +.IP "\fIcorei7\-avx\fR" 4 +.IX Item "corei7-avx" +Intel Core i7 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, +\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1AVX\s0, \s-1AES\s0 and \s-1PCLMUL\s0 instruction set support. +.IP "\fIcore-avx-i\fR" 4 +.IX Item "core-avx-i" +Intel Core \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, +\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1AVX\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0 and F16C instruction +set support. +.IP "\fIatom\fR" 4 +.IX Item "atom" +Intel Atom \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0 +instruction set support. +.IP "\fIk6\fR" 4 +.IX Item "k6" +\&\s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 instruction set support. +.IP "\fIk6\-2, k6\-3\fR" 4 +.IX Item "k6-2, k6-3" +Improved versions of \s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. +.IP "\fIathlon, athlon-tbird\fR" 4 +.IX Item "athlon, athlon-tbird" +\&\s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX\s0, 3dNOW!, enhanced 3DNow! and \s-1SSE\s0 prefetch instructions +support. +.IP "\fIathlon\-4, athlon-xp, athlon-mp\fR" 4 +.IX Item "athlon-4, athlon-xp, athlon-mp" +Improved \s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX\s0, 3DNow!, enhanced 3DNow! and full \s-1SSE\s0 +instruction set support. +.IP "\fIk8, opteron, athlon64, athlon-fx\fR" 4 +.IX Item "k8, opteron, athlon64, athlon-fx" +\&\s-1AMD\s0 K8 core based CPUs with x86\-64 instruction set support. (This supersets +\&\s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, 3DNow!, enhanced 3DNow! and 64\-bit instruction set extensions.) +.IP "\fIk8\-sse3, opteron\-sse3, athlon64\-sse3\fR" 4 +.IX Item "k8-sse3, opteron-sse3, athlon64-sse3" +Improved versions of k8, opteron and athlon64 with \s-1SSE3\s0 instruction set support. +.IP "\fIamdfam10, barcelona\fR" 4 +.IX Item "amdfam10, barcelona" +\&\s-1AMD\s0 Family 10h core based CPUs with x86\-64 instruction set support. (This +supersets \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSE4A\s0, 3DNow!, enhanced 3DNow!, \s-1ABM\s0 and 64\-bit +instruction set extensions.) +.IP "\fIwinchip\-c6\fR" 4 +.IX Item "winchip-c6" +\&\s-1IDT\s0 Winchip C6 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 instruction +set support. +.IP "\fIwinchip2\fR" 4 +.IX Item "winchip2" +\&\s-1IDT\s0 Winchip2 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 and 3DNow! +instruction set support. +.IP "\fIc3\fR" 4 +.IX Item "c3" +Via C3 \s-1CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. (No scheduling is +implemented for this chip.) +.IP "\fIc3\-2\fR" 4 +.IX Item "c3-2" +Via C3\-2 \s-1CPU\s0 with \s-1MMX\s0 and \s-1SSE\s0 instruction set support. (No scheduling is +implemented for this chip.) +.IP "\fIgeode\fR" 4 +.IX Item "geode" +Embedded \s-1AMD\s0 \s-1CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. +.RE +.RS 4 +.Sp +While picking a specific \fIcpu-type\fR will schedule things appropriately +for that particular chip, the compiler will not generate any code that +does not run on the i386 without the \fB\-march=\fR\fIcpu-type\fR option +being used. +.RE +.IP "\fB\-march=\fR\fIcpu-type\fR" 4 +.IX Item "-march=cpu-type" +Generate instructions for the machine type \fIcpu-type\fR. The choices +for \fIcpu-type\fR are the same as for \fB\-mtune\fR. Moreover, +specifying \fB\-march=\fR\fIcpu-type\fR implies \fB\-mtune=\fR\fIcpu-type\fR. +.IP "\fB\-mcpu=\fR\fIcpu-type\fR" 4 +.IX Item "-mcpu=cpu-type" +A deprecated synonym for \fB\-mtune\fR. +.IP "\fB\-mfpmath=\fR\fIunit\fR" 4 +.IX Item "-mfpmath=unit" +Generate floating point arithmetics for selected unit \fIunit\fR. The choices +for \fIunit\fR are: +.RS 4 +.IP "\fB387\fR" 4 +.IX Item "387" +Use the standard 387 floating point coprocessor present majority of chips and +emulated otherwise. Code compiled with this option will run almost everywhere. +The temporary results are computed in 80bit precision instead of precision +specified by the type resulting in slightly different results compared to most +of other chips. See \fB\-ffloat\-store\fR for more detailed description. +.Sp +This is the default choice for i386 compiler. +.IP "\fBsse\fR" 4 +.IX Item "sse" +Use scalar floating point instructions present in the \s-1SSE\s0 instruction set. +This instruction set is supported by Pentium3 and newer chips, in the \s-1AMD\s0 line +by Athlon\-4, Athlon-xp and Athlon-mp chips. The earlier version of \s-1SSE\s0 +instruction set supports only single precision arithmetics, thus the double and +extended precision arithmetics is still done using 387. Later version, present +only in Pentium4 and the future \s-1AMD\s0 x86\-64 chips supports double precision +arithmetics too. +.Sp +For the i386 compiler, you need to use \fB\-march=\fR\fIcpu-type\fR, \fB\-msse\fR +or \fB\-msse2\fR switches to enable \s-1SSE\s0 extensions and make this option +effective. For the x86\-64 compiler, these extensions are enabled by default. +.Sp +The resulting code should be considerably faster in the majority of cases and avoid +the numerical instability problems of 387 code, but may break some existing +code that expects temporaries to be 80bit. +.Sp +This is the default choice for the x86\-64 compiler. +.IP "\fBsse,387\fR" 4 +.IX Item "sse,387" +.PD 0 +.IP "\fBsse+387\fR" 4 +.IX Item "sse+387" +.IP "\fBboth\fR" 4 +.IX Item "both" +.PD +Attempt to utilize both instruction sets at once. This effectively double the +amount of available registers and on chips with separate execution units for +387 and \s-1SSE\s0 the execution resources too. Use this option with care, as it is +still experimental, because the \s-1GCC\s0 register allocator does not model separate +functional units well resulting in instable performance. +.RE +.RS 4 +.RE +.IP "\fB\-masm=\fR\fIdialect\fR" 4 +.IX Item "-masm=dialect" +Output asm instructions using selected \fIdialect\fR. Supported +choices are \fBintel\fR or \fBatt\fR (the default one). Darwin does +not support \fBintel\fR. +.IP "\fB\-mieee\-fp\fR" 4 +.IX Item "-mieee-fp" +.PD 0 +.IP "\fB\-mno\-ieee\-fp\fR" 4 +.IX Item "-mno-ieee-fp" +.PD +Control whether or not the compiler uses \s-1IEEE\s0 floating point +comparisons. These handle correctly the case where the result of a +comparison is unordered. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Generate output containing library calls for floating point. +\&\fBWarning:\fR the requisite libraries are not part of \s-1GCC\s0. +Normally the facilities of the machine's usual C compiler are used, but +this can't be done directly in cross-compilation. You must make your +own arrangements to provide suitable library functions for +cross-compilation. +.Sp +On machines where a function returns floating point results in the 80387 +register stack, some floating point opcodes may be emitted even if +\&\fB\-msoft\-float\fR is used. +.IP "\fB\-mno\-fp\-ret\-in\-387\fR" 4 +.IX Item "-mno-fp-ret-in-387" +Do not use the \s-1FPU\s0 registers for return values of functions. +.Sp +The usual calling convention has functions return values of types +\&\f(CW\*(C`float\*(C'\fR and \f(CW\*(C`double\*(C'\fR in an \s-1FPU\s0 register, even if there +is no \s-1FPU\s0. The idea is that the operating system should emulate +an \s-1FPU\s0. +.Sp +The option \fB\-mno\-fp\-ret\-in\-387\fR causes such values to be returned +in ordinary \s-1CPU\s0 registers instead. +.IP "\fB\-mno\-fancy\-math\-387\fR" 4 +.IX Item "-mno-fancy-math-387" +Some 387 emulators do not support the \f(CW\*(C`sin\*(C'\fR, \f(CW\*(C`cos\*(C'\fR and +\&\f(CW\*(C`sqrt\*(C'\fR instructions for the 387. Specify this option to avoid +generating those instructions. This option is the default on FreeBSD, +OpenBSD and NetBSD. This option is overridden when \fB\-march\fR +indicates that the target \s-1CPU\s0 will always have an \s-1FPU\s0 and so the +instruction will not need emulation. As of revision 2.6.1, these +instructions are not generated unless you also use the +\&\fB\-funsafe\-math\-optimizations\fR switch. +.IP "\fB\-malign\-double\fR" 4 +.IX Item "-malign-double" +.PD 0 +.IP "\fB\-mno\-align\-double\fR" 4 +.IX Item "-mno-align-double" +.PD +Control whether \s-1GCC\s0 aligns \f(CW\*(C`double\*(C'\fR, \f(CW\*(C`long double\*(C'\fR, and +\&\f(CW\*(C`long long\*(C'\fR variables on a two word boundary or a one word +boundary. Aligning \f(CW\*(C`double\*(C'\fR variables on a two word boundary will +produce code that runs somewhat faster on a \fBPentium\fR at the +expense of more memory. +.Sp +On x86\-64, \fB\-malign\-double\fR is enabled by default. +.Sp +\&\fBWarning:\fR if you use the \fB\-malign\-double\fR switch, +structures containing the above types will be aligned differently than +the published application binary interface specifications for the 386 +and will not be binary compatible with structures in code compiled +without that switch. +.IP "\fB\-m96bit\-long\-double\fR" 4 +.IX Item "-m96bit-long-double" +.PD 0 +.IP "\fB\-m128bit\-long\-double\fR" 4 +.IX Item "-m128bit-long-double" +.PD +These switches control the size of \f(CW\*(C`long double\*(C'\fR type. The i386 +application binary interface specifies the size to be 96 bits, +so \fB\-m96bit\-long\-double\fR is the default in 32 bit mode. +.Sp +Modern architectures (Pentium and newer) would prefer \f(CW\*(C`long double\*(C'\fR +to be aligned to an 8 or 16 byte boundary. In arrays or structures +conforming to the \s-1ABI\s0, this would not be possible. So specifying a +\&\fB\-m128bit\-long\-double\fR will align \f(CW\*(C`long double\*(C'\fR +to a 16 byte boundary by padding the \f(CW\*(C`long double\*(C'\fR with an additional +32 bit zero. +.Sp +In the x86\-64 compiler, \fB\-m128bit\-long\-double\fR is the default choice as +its \s-1ABI\s0 specifies that \f(CW\*(C`long double\*(C'\fR is to be aligned on 16 byte boundary. +.Sp +Notice that neither of these options enable any extra precision over the x87 +standard of 80 bits for a \f(CW\*(C`long double\*(C'\fR. +.Sp +\&\fBWarning:\fR if you override the default value for your target \s-1ABI\s0, the +structures and arrays containing \f(CW\*(C`long double\*(C'\fR variables will change +their size as well as function calling convention for function taking +\&\f(CW\*(C`long double\*(C'\fR will be modified. Hence they will not be binary +compatible with arrays or structures in code compiled without that switch. +.IP "\fB\-mlarge\-data\-threshold=\fR\fInumber\fR" 4 +.IX Item "-mlarge-data-threshold=number" +When \fB\-mcmodel=medium\fR is specified, the data greater than +\&\fIthreshold\fR are placed in large data section. This value must be the +same across all object linked into the binary and defaults to 65535. +.IP "\fB\-mrtd\fR" 4 +.IX Item "-mrtd" +Use a different function-calling convention, in which functions that +take a fixed number of arguments return with the \f(CW\*(C`ret\*(C'\fR \fInum\fR +instruction, which pops their arguments while returning. This saves one +instruction in the caller since there is no need to pop the arguments +there. +.Sp +You can specify that an individual function is called with this calling +sequence with the function attribute \fBstdcall\fR. You can also +override the \fB\-mrtd\fR option by using the function attribute +\&\fBcdecl\fR. +.Sp +\&\fBWarning:\fR this calling convention is incompatible with the one +normally used on Unix, so you cannot use it if you need to call +libraries compiled with the Unix compiler. +.Sp +Also, you must provide function prototypes for all functions that +take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR); +otherwise incorrect code will be generated for calls to those +functions. +.Sp +In addition, seriously incorrect code will result if you call a +function with too many arguments. (Normally, extra arguments are +harmlessly ignored.) +.IP "\fB\-mregparm=\fR\fInum\fR" 4 +.IX Item "-mregparm=num" +Control how many registers are used to pass integer arguments. By +default, no registers are used to pass arguments, and at most 3 +registers can be used. You can control this behavior for a specific +function by using the function attribute \fBregparm\fR. +.Sp +\&\fBWarning:\fR if you use this switch, and +\&\fInum\fR is nonzero, then you must build all modules with the same +value, including any libraries. This includes the system libraries and +startup modules. +.IP "\fB\-msseregparm\fR" 4 +.IX Item "-msseregparm" +Use \s-1SSE\s0 register passing conventions for float and double arguments +and return values. You can control this behavior for a specific +function by using the function attribute \fBsseregparm\fR. +.Sp +\&\fBWarning:\fR if you use this switch then you must build all +modules with the same value, including any libraries. This includes +the system libraries and startup modules. +.IP "\fB\-mvect8\-ret\-in\-mem\fR" 4 +.IX Item "-mvect8-ret-in-mem" +Return 8\-byte vectors in memory instead of \s-1MMX\s0 registers. This is the +default on Solaris@tie{}8 and 9 and VxWorks to match the \s-1ABI\s0 of the Sun +Studio compilers until version 12. Later compiler versions (starting +with Studio 12 Update@tie{}1) follow the \s-1ABI\s0 used by other x86 targets, which +is the default on Solaris@tie{}10 and later. \fIOnly\fR use this option if +you need to remain compatible with existing code produced by those +previous compiler versions or older versions of \s-1GCC\s0. +.IP "\fB\-mpc32\fR" 4 +.IX Item "-mpc32" +.PD 0 +.IP "\fB\-mpc64\fR" 4 +.IX Item "-mpc64" +.IP "\fB\-mpc80\fR" 4 +.IX Item "-mpc80" +.PD +Set 80387 floating-point precision to 32, 64 or 80 bits. When \fB\-mpc32\fR +is specified, the significands of results of floating-point operations are +rounded to 24 bits (single precision); \fB\-mpc64\fR rounds the +significands of results of floating-point operations to 53 bits (double +precision) and \fB\-mpc80\fR rounds the significands of results of +floating-point operations to 64 bits (extended double precision), which is +the default. When this option is used, floating-point operations in higher +precisions are not available to the programmer without setting the \s-1FPU\s0 +control word explicitly. +.Sp +Setting the rounding of floating-point operations to less than the default +80 bits can speed some programs by 2% or more. Note that some mathematical +libraries assume that extended precision (80 bit) floating-point operations +are enabled by default; routines in such libraries could suffer significant +loss of accuracy, typically through so-called \*(L"catastrophic cancellation\*(R", +when this option is used to set the precision to less than extended precision. +.IP "\fB\-mstackrealign\fR" 4 +.IX Item "-mstackrealign" +Realign the stack at entry. On the Intel x86, the \fB\-mstackrealign\fR +option will generate an alternate prologue and epilogue that realigns the +runtime stack if necessary. This supports mixing legacy codes that keep +a 4\-byte aligned stack with modern codes that keep a 16\-byte stack for +\&\s-1SSE\s0 compatibility. See also the attribute \f(CW\*(C`force_align_arg_pointer\*(C'\fR, +applicable to individual functions. +.IP "\fB\-mpreferred\-stack\-boundary=\fR\fInum\fR" 4 +.IX Item "-mpreferred-stack-boundary=num" +Attempt to keep the stack boundary aligned to a 2 raised to \fInum\fR +byte boundary. If \fB\-mpreferred\-stack\-boundary\fR is not specified, +the default is 4 (16 bytes or 128 bits). +.IP "\fB\-mincoming\-stack\-boundary=\fR\fInum\fR" 4 +.IX Item "-mincoming-stack-boundary=num" +Assume the incoming stack is aligned to a 2 raised to \fInum\fR byte +boundary. If \fB\-mincoming\-stack\-boundary\fR is not specified, +the one specified by \fB\-mpreferred\-stack\-boundary\fR will be used. +.Sp +On Pentium and PentiumPro, \f(CW\*(C`double\*(C'\fR and \f(CW\*(C`long double\*(C'\fR values +should be aligned to an 8 byte boundary (see \fB\-malign\-double\fR) or +suffer significant run time performance penalties. On Pentium \s-1III\s0, the +Streaming \s-1SIMD\s0 Extension (\s-1SSE\s0) data type \f(CW\*(C`_\|_m128\*(C'\fR may not work +properly if it is not 16 byte aligned. +.Sp +To ensure proper alignment of this values on the stack, the stack boundary +must be as aligned as that required by any value stored on the stack. +Further, every function must be generated such that it keeps the stack +aligned. Thus calling a function compiled with a higher preferred +stack boundary from a function compiled with a lower preferred stack +boundary will most likely misalign the stack. It is recommended that +libraries that use callbacks always use the default setting. +.Sp +This extra alignment does consume extra stack space, and generally +increases code size. Code that is sensitive to stack space usage, such +as embedded systems and operating system kernels, may want to reduce the +preferred alignment to \fB\-mpreferred\-stack\-boundary=2\fR. +.IP "\fB\-mmmx\fR" 4 +.IX Item "-mmmx" +.PD 0 +.IP "\fB\-mno\-mmx\fR" 4 +.IX Item "-mno-mmx" +.IP "\fB\-msse\fR" 4 +.IX Item "-msse" +.IP "\fB\-mno\-sse\fR" 4 +.IX Item "-mno-sse" +.IP "\fB\-msse2\fR" 4 +.IX Item "-msse2" +.IP "\fB\-mno\-sse2\fR" 4 +.IX Item "-mno-sse2" +.IP "\fB\-msse3\fR" 4 +.IX Item "-msse3" +.IP "\fB\-mno\-sse3\fR" 4 +.IX Item "-mno-sse3" +.IP "\fB\-mssse3\fR" 4 +.IX Item "-mssse3" +.IP "\fB\-mno\-ssse3\fR" 4 +.IX Item "-mno-ssse3" +.IP "\fB\-msse4.1\fR" 4 +.IX Item "-msse4.1" +.IP "\fB\-mno\-sse4.1\fR" 4 +.IX Item "-mno-sse4.1" +.IP "\fB\-msse4.2\fR" 4 +.IX Item "-msse4.2" +.IP "\fB\-mno\-sse4.2\fR" 4 +.IX Item "-mno-sse4.2" +.IP "\fB\-msse4\fR" 4 +.IX Item "-msse4" +.IP "\fB\-mno\-sse4\fR" 4 +.IX Item "-mno-sse4" +.IP "\fB\-mavx\fR" 4 +.IX Item "-mavx" +.IP "\fB\-mno\-avx\fR" 4 +.IX Item "-mno-avx" +.IP "\fB\-maes\fR" 4 +.IX Item "-maes" +.IP "\fB\-mno\-aes\fR" 4 +.IX Item "-mno-aes" +.IP "\fB\-mpclmul\fR" 4 +.IX Item "-mpclmul" +.IP "\fB\-mno\-pclmul\fR" 4 +.IX Item "-mno-pclmul" +.IP "\fB\-mfsgsbase\fR" 4 +.IX Item "-mfsgsbase" +.IP "\fB\-mno\-fsgsbase\fR" 4 +.IX Item "-mno-fsgsbase" +.IP "\fB\-mrdrnd\fR" 4 +.IX Item "-mrdrnd" +.IP "\fB\-mno\-rdrnd\fR" 4 +.IX Item "-mno-rdrnd" +.IP "\fB\-mf16c\fR" 4 +.IX Item "-mf16c" +.IP "\fB\-mno\-f16c\fR" 4 +.IX Item "-mno-f16c" +.IP "\fB\-msse4a\fR" 4 +.IX Item "-msse4a" +.IP "\fB\-mno\-sse4a\fR" 4 +.IX Item "-mno-sse4a" +.IP "\fB\-mfma4\fR" 4 +.IX Item "-mfma4" +.IP "\fB\-mno\-fma4\fR" 4 +.IX Item "-mno-fma4" +.IP "\fB\-mxop\fR" 4 +.IX Item "-mxop" +.IP "\fB\-mno\-xop\fR" 4 +.IX Item "-mno-xop" +.IP "\fB\-mlwp\fR" 4 +.IX Item "-mlwp" +.IP "\fB\-mno\-lwp\fR" 4 +.IX Item "-mno-lwp" +.IP "\fB\-m3dnow\fR" 4 +.IX Item "-m3dnow" +.IP "\fB\-mno\-3dnow\fR" 4 +.IX Item "-mno-3dnow" +.IP "\fB\-mpopcnt\fR" 4 +.IX Item "-mpopcnt" +.IP "\fB\-mno\-popcnt\fR" 4 +.IX Item "-mno-popcnt" +.IP "\fB\-mabm\fR" 4 +.IX Item "-mabm" +.IP "\fB\-mno\-abm\fR" 4 +.IX Item "-mno-abm" +.IP "\fB\-mbmi\fR" 4 +.IX Item "-mbmi" +.IP "\fB\-mno\-bmi\fR" 4 +.IX Item "-mno-bmi" +.IP "\fB\-mtbm\fR" 4 +.IX Item "-mtbm" +.IP "\fB\-mno\-tbm\fR" 4 +.IX Item "-mno-tbm" +.PD +These switches enable or disable the use of instructions in the \s-1MMX\s0, +\&\s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, \s-1SSE4\s0.1, \s-1AVX\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0, +F16C, \s-1SSE4A\s0, \s-1FMA4\s0, \s-1XOP\s0, \s-1LWP\s0, \s-1ABM\s0, \s-1BMI\s0, or 3DNow! extended instruction sets. +These extensions are also available as built-in functions: see +\&\fBX86 Built-in Functions\fR, for details of the functions enabled and +disabled by these switches. +.Sp +To have \s-1SSE/SSE2\s0 instructions generated automatically from floating-point +code (as opposed to 387 instructions), see \fB\-mfpmath=sse\fR. +.Sp +\&\s-1GCC\s0 depresses SSEx instructions when \fB\-mavx\fR is used. Instead, it +generates new \s-1AVX\s0 instructions or \s-1AVX\s0 equivalence for all SSEx instructions +when needed. +.Sp +These options will enable \s-1GCC\s0 to use these extended instructions in +generated code, even without \fB\-mfpmath=sse\fR. Applications which +perform runtime \s-1CPU\s0 detection must compile separate files for each +supported architecture, using the appropriate flags. In particular, +the file containing the \s-1CPU\s0 detection code should be compiled without +these options. +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Do (don't) generate code that uses the fused multiply/add or multiply/subtract +instructions. The default is to use these instructions. +.IP "\fB\-mcld\fR" 4 +.IX Item "-mcld" +This option instructs \s-1GCC\s0 to emit a \f(CW\*(C`cld\*(C'\fR instruction in the prologue +of functions that use string instructions. String instructions depend on +the \s-1DF\s0 flag to select between autoincrement or autodecrement mode. While the +\&\s-1ABI\s0 specifies the \s-1DF\s0 flag to be cleared on function entry, some operating +systems violate this specification by not clearing the \s-1DF\s0 flag in their +exception dispatchers. The exception handler can be invoked with the \s-1DF\s0 flag +set which leads to wrong direction mode, when string instructions are used. +This option can be enabled by default on 32\-bit x86 targets by configuring +\&\s-1GCC\s0 with the \fB\-\-enable\-cld\fR configure option. Generation of \f(CW\*(C`cld\*(C'\fR +instructions can be suppressed with the \fB\-mno\-cld\fR compiler option +in this case. +.IP "\fB\-mvzeroupper\fR" 4 +.IX Item "-mvzeroupper" +This option instructs \s-1GCC\s0 to emit a \f(CW\*(C`vzeroupper\*(C'\fR instruction +before a transfer of control flow out of the function to minimize +\&\s-1AVX\s0 to \s-1SSE\s0 transition penalty as well as remove unnecessary zeroupper +intrinsics. +.IP "\fB\-mcx16\fR" 4 +.IX Item "-mcx16" +This option will enable \s-1GCC\s0 to use \s-1CMPXCHG16B\s0 instruction in generated code. +\&\s-1CMPXCHG16B\s0 allows for atomic operations on 128\-bit double quadword (or oword) +data types. This is useful for high resolution counters that could be updated +by multiple processors (or cores). This instruction is generated as part of +atomic built-in functions: see \fBAtomic Builtins\fR for details. +.IP "\fB\-msahf\fR" 4 +.IX Item "-msahf" +This option will enable \s-1GCC\s0 to use \s-1SAHF\s0 instruction in generated 64\-bit code. +Early Intel CPUs with Intel 64 lacked \s-1LAHF\s0 and \s-1SAHF\s0 instructions supported +by \s-1AMD64\s0 until introduction of Pentium 4 G1 step in December 2005. \s-1LAHF\s0 and +\&\s-1SAHF\s0 are load and store instructions, respectively, for certain status flags. +In 64\-bit mode, \s-1SAHF\s0 instruction is used to optimize \f(CW\*(C`fmod\*(C'\fR, \f(CW\*(C`drem\*(C'\fR +or \f(CW\*(C`remainder\*(C'\fR built-in functions: see \fBOther Builtins\fR for details. +.IP "\fB\-mmovbe\fR" 4 +.IX Item "-mmovbe" +This option will enable \s-1GCC\s0 to use movbe instruction to implement +\&\f(CW\*(C`_\|_builtin_bswap32\*(C'\fR and \f(CW\*(C`_\|_builtin_bswap64\*(C'\fR. +.IP "\fB\-mcrc32\fR" 4 +.IX Item "-mcrc32" +This option will enable built-in functions, \f(CW\*(C`_\|_builtin_ia32_crc32qi\*(C'\fR, +\&\f(CW\*(C`_\|_builtin_ia32_crc32hi\*(C'\fR. \f(CW\*(C`_\|_builtin_ia32_crc32si\*(C'\fR and +\&\f(CW\*(C`_\|_builtin_ia32_crc32di\*(C'\fR to generate the crc32 machine instruction. +.IP "\fB\-mrecip\fR" 4 +.IX Item "-mrecip" +This option will enable \s-1GCC\s0 to use \s-1RCPSS\s0 and \s-1RSQRTSS\s0 instructions (and their +vectorized variants \s-1RCPPS\s0 and \s-1RSQRTPS\s0) with an additional Newton-Raphson step +to increase precision instead of \s-1DIVSS\s0 and \s-1SQRTSS\s0 (and their vectorized +variants) for single precision floating point arguments. These instructions +are generated only when \fB\-funsafe\-math\-optimizations\fR is enabled +together with \fB\-finite\-math\-only\fR and \fB\-fno\-trapping\-math\fR. +Note that while the throughput of the sequence is higher than the throughput +of the non-reciprocal instruction, the precision of the sequence can be +decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994). +.Sp +Note that \s-1GCC\s0 implements 1.0f/sqrtf(x) in terms of \s-1RSQRTSS\s0 (or \s-1RSQRTPS\s0) +already with \fB\-ffast\-math\fR (or the above option combination), and +doesn't need \fB\-mrecip\fR. +.IP "\fB\-mveclibabi=\fR\fItype\fR" 4 +.IX Item "-mveclibabi=type" +Specifies the \s-1ABI\s0 type to use for vectorizing intrinsics using an +external library. Supported types are \f(CW\*(C`svml\*(C'\fR for the Intel short +vector math library and \f(CW\*(C`acml\*(C'\fR for the \s-1AMD\s0 math core library style +of interfacing. \s-1GCC\s0 will currently emit calls to \f(CW\*(C`vmldExp2\*(C'\fR, +\&\f(CW\*(C`vmldLn2\*(C'\fR, \f(CW\*(C`vmldLog102\*(C'\fR, \f(CW\*(C`vmldLog102\*(C'\fR, \f(CW\*(C`vmldPow2\*(C'\fR, +\&\f(CW\*(C`vmldTanh2\*(C'\fR, \f(CW\*(C`vmldTan2\*(C'\fR, \f(CW\*(C`vmldAtan2\*(C'\fR, \f(CW\*(C`vmldAtanh2\*(C'\fR, +\&\f(CW\*(C`vmldCbrt2\*(C'\fR, \f(CW\*(C`vmldSinh2\*(C'\fR, \f(CW\*(C`vmldSin2\*(C'\fR, \f(CW\*(C`vmldAsinh2\*(C'\fR, +\&\f(CW\*(C`vmldAsin2\*(C'\fR, \f(CW\*(C`vmldCosh2\*(C'\fR, \f(CW\*(C`vmldCos2\*(C'\fR, \f(CW\*(C`vmldAcosh2\*(C'\fR, +\&\f(CW\*(C`vmldAcos2\*(C'\fR, \f(CW\*(C`vmlsExp4\*(C'\fR, \f(CW\*(C`vmlsLn4\*(C'\fR, \f(CW\*(C`vmlsLog104\*(C'\fR, +\&\f(CW\*(C`vmlsLog104\*(C'\fR, \f(CW\*(C`vmlsPow4\*(C'\fR, \f(CW\*(C`vmlsTanh4\*(C'\fR, \f(CW\*(C`vmlsTan4\*(C'\fR, +\&\f(CW\*(C`vmlsAtan4\*(C'\fR, \f(CW\*(C`vmlsAtanh4\*(C'\fR, \f(CW\*(C`vmlsCbrt4\*(C'\fR, \f(CW\*(C`vmlsSinh4\*(C'\fR, +\&\f(CW\*(C`vmlsSin4\*(C'\fR, \f(CW\*(C`vmlsAsinh4\*(C'\fR, \f(CW\*(C`vmlsAsin4\*(C'\fR, \f(CW\*(C`vmlsCosh4\*(C'\fR, +\&\f(CW\*(C`vmlsCos4\*(C'\fR, \f(CW\*(C`vmlsAcosh4\*(C'\fR and \f(CW\*(C`vmlsAcos4\*(C'\fR for corresponding +function type when \fB\-mveclibabi=svml\fR is used and \f(CW\*(C`_\|_vrd2_sin\*(C'\fR, +\&\f(CW\*(C`_\|_vrd2_cos\*(C'\fR, \f(CW\*(C`_\|_vrd2_exp\*(C'\fR, \f(CW\*(C`_\|_vrd2_log\*(C'\fR, \f(CW\*(C`_\|_vrd2_log2\*(C'\fR, +\&\f(CW\*(C`_\|_vrd2_log10\*(C'\fR, \f(CW\*(C`_\|_vrs4_sinf\*(C'\fR, \f(CW\*(C`_\|_vrs4_cosf\*(C'\fR, +\&\f(CW\*(C`_\|_vrs4_expf\*(C'\fR, \f(CW\*(C`_\|_vrs4_logf\*(C'\fR, \f(CW\*(C`_\|_vrs4_log2f\*(C'\fR, +\&\f(CW\*(C`_\|_vrs4_log10f\*(C'\fR and \f(CW\*(C`_\|_vrs4_powf\*(C'\fR for corresponding function type +when \fB\-mveclibabi=acml\fR is used. Both \fB\-ftree\-vectorize\fR and +\&\fB\-funsafe\-math\-optimizations\fR have to be enabled. A \s-1SVML\s0 or \s-1ACML\s0 \s-1ABI\s0 +compatible library will have to be specified at link time. +.IP "\fB\-mabi=\fR\fIname\fR" 4 +.IX Item "-mabi=name" +Generate code for the specified calling convention. Permissible values +are: \fBsysv\fR for the \s-1ABI\s0 used on GNU/Linux and other systems and +\&\fBms\fR for the Microsoft \s-1ABI\s0. The default is to use the Microsoft +\&\s-1ABI\s0 when targeting Windows. On all other systems, the default is the +\&\s-1SYSV\s0 \s-1ABI\s0. You can control this behavior for a specific function by +using the function attribute \fBms_abi\fR/\fBsysv_abi\fR. +.IP "\fB\-mpush\-args\fR" 4 +.IX Item "-mpush-args" +.PD 0 +.IP "\fB\-mno\-push\-args\fR" 4 +.IX Item "-mno-push-args" +.PD +Use \s-1PUSH\s0 operations to store outgoing parameters. This method is shorter +and usually equally fast as method using \s-1SUB/MOV\s0 operations and is enabled +by default. In some cases disabling it may improve performance because of +improved scheduling and reduced dependencies. +.IP "\fB\-maccumulate\-outgoing\-args\fR" 4 +.IX Item "-maccumulate-outgoing-args" +If enabled, the maximum amount of space required for outgoing arguments will be +computed in the function prologue. This is faster on most modern CPUs +because of reduced dependencies, improved scheduling and reduced stack usage +when preferred stack boundary is not equal to 2. The drawback is a notable +increase in code size. This switch implies \fB\-mno\-push\-args\fR. +.IP "\fB\-mthreads\fR" 4 +.IX Item "-mthreads" +Support thread-safe exception handling on \fBMingw32\fR. Code that relies +on thread-safe exception handling must compile and link all code with the +\&\fB\-mthreads\fR option. When compiling, \fB\-mthreads\fR defines +\&\fB\-D_MT\fR; when linking, it links in a special thread helper library +\&\fB\-lmingwthrd\fR which cleans up per thread exception handling data. +.IP "\fB\-mno\-align\-stringops\fR" 4 +.IX Item "-mno-align-stringops" +Do not align destination of inlined string operations. This switch reduces +code size and improves performance in case the destination is already aligned, +but \s-1GCC\s0 doesn't know about it. +.IP "\fB\-minline\-all\-stringops\fR" 4 +.IX Item "-minline-all-stringops" +By default \s-1GCC\s0 inlines string operations only when destination is known to be +aligned at least to 4 byte boundary. This enables more inlining, increase code +size, but may improve performance of code that depends on fast memcpy, strlen +and memset for short lengths. +.IP "\fB\-minline\-stringops\-dynamically\fR" 4 +.IX Item "-minline-stringops-dynamically" +For string operation of unknown size, inline runtime checks so for small +blocks inline code is used, while for large blocks library call is used. +.IP "\fB\-mstringop\-strategy=\fR\fIalg\fR" 4 +.IX Item "-mstringop-strategy=alg" +Overwrite internal decision heuristic about particular algorithm to inline +string operation with. The allowed values are \f(CW\*(C`rep_byte\*(C'\fR, +\&\f(CW\*(C`rep_4byte\*(C'\fR, \f(CW\*(C`rep_8byte\*(C'\fR for expanding using i386 \f(CW\*(C`rep\*(C'\fR prefix +of specified size, \f(CW\*(C`byte_loop\*(C'\fR, \f(CW\*(C`loop\*(C'\fR, \f(CW\*(C`unrolled_loop\*(C'\fR for +expanding inline loop, \f(CW\*(C`libcall\*(C'\fR for always expanding library call. +.IP "\fB\-momit\-leaf\-frame\-pointer\fR" 4 +.IX Item "-momit-leaf-frame-pointer" +Don't keep the frame pointer in a register for leaf functions. This +avoids the instructions to save, set up and restore frame pointers and +makes an extra register available in leaf functions. The option +\&\fB\-fomit\-frame\-pointer\fR removes the frame pointer for all functions +which might make debugging harder. +.IP "\fB\-mtls\-direct\-seg\-refs\fR" 4 +.IX Item "-mtls-direct-seg-refs" +.PD 0 +.IP "\fB\-mno\-tls\-direct\-seg\-refs\fR" 4 +.IX Item "-mno-tls-direct-seg-refs" +.PD +Controls whether \s-1TLS\s0 variables may be accessed with offsets from the +\&\s-1TLS\s0 segment register (\f(CW%gs\fR for 32\-bit, \f(CW%fs\fR for 64\-bit), +or whether the thread base pointer must be added. Whether or not this +is legal depends on the operating system, and whether it maps the +segment to cover the entire \s-1TLS\s0 area. +.Sp +For systems that use \s-1GNU\s0 libc, the default is on. +.IP "\fB\-msse2avx\fR" 4 +.IX Item "-msse2avx" +.PD 0 +.IP "\fB\-mno\-sse2avx\fR" 4 +.IX Item "-mno-sse2avx" +.PD +Specify that the assembler should encode \s-1SSE\s0 instructions with \s-1VEX\s0 +prefix. The option \fB\-mavx\fR turns this on by default. +.IP "\fB\-mfentry\fR" 4 +.IX Item "-mfentry" +.PD 0 +.IP "\fB\-mno\-fentry\fR" 4 +.IX Item "-mno-fentry" +.PD +If profiling is active \fB\-pg\fR put the profiling +counter call before prologue. +Note: On x86 architectures the attribute \f(CW\*(C`ms_hook_prologue\*(C'\fR +isn't possible at the moment for \fB\-mfentry\fR and \fB\-pg\fR. +.IP "\fB\-m8bit\-idiv\fR" 4 +.IX Item "-m8bit-idiv" +.PD 0 +.IP "\fB\-mno\-8bit\-idiv\fR" 4 +.IX Item "-mno-8bit-idiv" +.PD +On some processors, like Intel Atom, 8bit unsigned integer divide is +much faster than 32bit/64bit integer divide. This option will generate a +runt-time check. If both dividend and divisor are within range of 0 +to 255, 8bit unsigned integer divide will be used instead of +32bit/64bit integer divide. +.IP "\fB\-mavx256\-split\-unaligned\-load\fR" 4 +.IX Item "-mavx256-split-unaligned-load" +.PD 0 +.IP "\fB\-mavx256\-split\-unaligned\-store\fR" 4 +.IX Item "-mavx256-split-unaligned-store" +.PD +Split 32\-byte \s-1AVX\s0 unaligned load and store. +.PP +These \fB\-m\fR switches are supported in addition to the above +on \s-1AMD\s0 x86\-64 processors in 64\-bit environments. +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" +.PD 0 +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.PD +Generate code for a 32\-bit or 64\-bit environment. +The 32\-bit environment sets int, long and pointer to 32 bits and +generates code that runs on any i386 system. +The 64\-bit environment sets int to 32 bits and long and pointer +to 64 bits and generates code for \s-1AMD\s0's x86\-64 architecture. For +darwin only the \-m64 option turns off the \fB\-fno\-pic\fR and +\&\fB\-mdynamic\-no\-pic\fR options. +.IP "\fB\-mno\-red\-zone\fR" 4 +.IX Item "-mno-red-zone" +Do not use a so called red zone for x86\-64 code. The red zone is mandated +by the x86\-64 \s-1ABI\s0, it is a 128\-byte area beyond the location of the +stack pointer that will not be modified by signal or interrupt handlers +and therefore can be used for temporary data without adjusting the stack +pointer. The flag \fB\-mno\-red\-zone\fR disables this red zone. +.IP "\fB\-mcmodel=small\fR" 4 +.IX Item "-mcmodel=small" +Generate code for the small code model: the program and its symbols must +be linked in the lower 2 \s-1GB\s0 of the address space. Pointers are 64 bits. +Programs can be statically or dynamically linked. This is the default +code model. +.IP "\fB\-mcmodel=kernel\fR" 4 +.IX Item "-mcmodel=kernel" +Generate code for the kernel code model. The kernel runs in the +negative 2 \s-1GB\s0 of the address space. +This model has to be used for Linux kernel code. +.IP "\fB\-mcmodel=medium\fR" 4 +.IX Item "-mcmodel=medium" +Generate code for the medium model: The program is linked in the lower 2 +\&\s-1GB\s0 of the address space. Small symbols are also placed there. Symbols +with sizes larger than \fB\-mlarge\-data\-threshold\fR are put into +large data or bss sections and can be located above 2GB. Programs can +be statically or dynamically linked. +.IP "\fB\-mcmodel=large\fR" 4 +.IX Item "-mcmodel=large" +Generate code for the large model: This model makes no assumptions +about addresses and sizes of sections. +.PP +\fIi386 and x86\-64 Windows Options\fR +.IX Subsection "i386 and x86-64 Windows Options" +.PP +These additional options are available for Windows targets: +.IP "\fB\-mconsole\fR" 4 +.IX Item "-mconsole" +This option is available for Cygwin and MinGW targets. It +specifies that a console application is to be generated, by +instructing the linker to set the \s-1PE\s0 header subsystem type +required for console applications. +This is the default behavior for Cygwin and MinGW targets. +.IP "\fB\-mdll\fR" 4 +.IX Item "-mdll" +This option is available for Cygwin and MinGW targets. It +specifies that a \s-1DLL\s0 \- a dynamic link library \- is to be +generated, enabling the selection of the required runtime +startup object and entry point. +.IP "\fB\-mnop\-fun\-dllimport\fR" 4 +.IX Item "-mnop-fun-dllimport" +This option is available for Cygwin and MinGW targets. It +specifies that the dllimport attribute should be ignored. +.IP "\fB\-mthread\fR" 4 +.IX Item "-mthread" +This option is available for MinGW targets. It specifies +that MinGW-specific thread support is to be used. +.IP "\fB\-municode\fR" 4 +.IX Item "-municode" +This option is available for mingw\-w64 targets. It specifies +that the \s-1UNICODE\s0 macro is getting pre-defined and that the +unicode capable runtime startup code is chosen. +.IP "\fB\-mwin32\fR" 4 +.IX Item "-mwin32" +This option is available for Cygwin and MinGW targets. It +specifies that the typical Windows pre-defined macros are to +be set in the pre-processor, but does not influence the choice +of runtime library/startup code. +.IP "\fB\-mwindows\fR" 4 +.IX Item "-mwindows" +This option is available for Cygwin and MinGW targets. It +specifies that a \s-1GUI\s0 application is to be generated by +instructing the linker to set the \s-1PE\s0 header subsystem type +appropriately. +.IP "\fB\-fno\-set\-stack\-executable\fR" 4 +.IX Item "-fno-set-stack-executable" +This option is available for MinGW targets. It specifies that +the executable flag for stack used by nested functions isn't +set. This is necessary for binaries running in kernel mode of +Windows, as there the user32 \s-1API\s0, which is used to set executable +privileges, isn't available. +.IP "\fB\-mpe\-aligned\-commons\fR" 4 +.IX Item "-mpe-aligned-commons" +This option is available for Cygwin and MinGW targets. It +specifies that the \s-1GNU\s0 extension to the \s-1PE\s0 file format that +permits the correct alignment of \s-1COMMON\s0 variables should be +used when generating code. It will be enabled by default if +\&\s-1GCC\s0 detects that the target assembler found during configuration +supports the feature. +.PP +See also under \fBi386 and x86\-64 Options\fR for standard options. +.PP +\fI\s-1IA\-64\s0 Options\fR +.IX Subsection "IA-64 Options" +.PP +These are the \fB\-m\fR options defined for the Intel \s-1IA\-64\s0 architecture. +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +Generate code for a big endian target. This is the default for HP-UX. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +Generate code for a little endian target. This is the default for \s-1AIX5\s0 +and GNU/Linux. +.IP "\fB\-mgnu\-as\fR" 4 +.IX Item "-mgnu-as" +.PD 0 +.IP "\fB\-mno\-gnu\-as\fR" 4 +.IX Item "-mno-gnu-as" +.PD +Generate (or don't) code for the \s-1GNU\s0 assembler. This is the default. +.IP "\fB\-mgnu\-ld\fR" 4 +.IX Item "-mgnu-ld" +.PD 0 +.IP "\fB\-mno\-gnu\-ld\fR" 4 +.IX Item "-mno-gnu-ld" +.PD +Generate (or don't) code for the \s-1GNU\s0 linker. This is the default. +.IP "\fB\-mno\-pic\fR" 4 +.IX Item "-mno-pic" +Generate code that does not use a global pointer register. The result +is not position independent code, and violates the \s-1IA\-64\s0 \s-1ABI\s0. +.IP "\fB\-mvolatile\-asm\-stop\fR" 4 +.IX Item "-mvolatile-asm-stop" +.PD 0 +.IP "\fB\-mno\-volatile\-asm\-stop\fR" 4 +.IX Item "-mno-volatile-asm-stop" +.PD +Generate (or don't) a stop bit immediately before and after volatile asm +statements. +.IP "\fB\-mregister\-names\fR" 4 +.IX Item "-mregister-names" +.PD 0 +.IP "\fB\-mno\-register\-names\fR" 4 +.IX Item "-mno-register-names" +.PD +Generate (or don't) \fBin\fR, \fBloc\fR, and \fBout\fR register names for +the stacked registers. This may make assembler output more readable. +.IP "\fB\-mno\-sdata\fR" 4 +.IX Item "-mno-sdata" +.PD 0 +.IP "\fB\-msdata\fR" 4 +.IX Item "-msdata" +.PD +Disable (or enable) optimizations that use the small data section. This may +be useful for working around optimizer bugs. +.IP "\fB\-mconstant\-gp\fR" 4 +.IX Item "-mconstant-gp" +Generate code that uses a single constant global pointer value. This is +useful when compiling kernel code. +.IP "\fB\-mauto\-pic\fR" 4 +.IX Item "-mauto-pic" +Generate code that is self-relocatable. This implies \fB\-mconstant\-gp\fR. +This is useful when compiling firmware code. +.IP "\fB\-minline\-float\-divide\-min\-latency\fR" 4 +.IX Item "-minline-float-divide-min-latency" +Generate code for inline divides of floating point values +using the minimum latency algorithm. +.IP "\fB\-minline\-float\-divide\-max\-throughput\fR" 4 +.IX Item "-minline-float-divide-max-throughput" +Generate code for inline divides of floating point values +using the maximum throughput algorithm. +.IP "\fB\-mno\-inline\-float\-divide\fR" 4 +.IX Item "-mno-inline-float-divide" +Do not generate inline code for divides of floating point values. +.IP "\fB\-minline\-int\-divide\-min\-latency\fR" 4 +.IX Item "-minline-int-divide-min-latency" +Generate code for inline divides of integer values +using the minimum latency algorithm. +.IP "\fB\-minline\-int\-divide\-max\-throughput\fR" 4 +.IX Item "-minline-int-divide-max-throughput" +Generate code for inline divides of integer values +using the maximum throughput algorithm. +.IP "\fB\-mno\-inline\-int\-divide\fR" 4 +.IX Item "-mno-inline-int-divide" +Do not generate inline code for divides of integer values. +.IP "\fB\-minline\-sqrt\-min\-latency\fR" 4 +.IX Item "-minline-sqrt-min-latency" +Generate code for inline square roots +using the minimum latency algorithm. +.IP "\fB\-minline\-sqrt\-max\-throughput\fR" 4 +.IX Item "-minline-sqrt-max-throughput" +Generate code for inline square roots +using the maximum throughput algorithm. +.IP "\fB\-mno\-inline\-sqrt\fR" 4 +.IX Item "-mno-inline-sqrt" +Do not generate inline code for sqrt. +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Do (don't) generate code that uses the fused multiply/add or multiply/subtract +instructions. The default is to use these instructions. +.IP "\fB\-mno\-dwarf2\-asm\fR" 4 +.IX Item "-mno-dwarf2-asm" +.PD 0 +.IP "\fB\-mdwarf2\-asm\fR" 4 +.IX Item "-mdwarf2-asm" +.PD +Don't (or do) generate assembler code for the \s-1DWARF2\s0 line number debugging +info. This may be useful when not using the \s-1GNU\s0 assembler. +.IP "\fB\-mearly\-stop\-bits\fR" 4 +.IX Item "-mearly-stop-bits" +.PD 0 +.IP "\fB\-mno\-early\-stop\-bits\fR" 4 +.IX Item "-mno-early-stop-bits" +.PD +Allow stop bits to be placed earlier than immediately preceding the +instruction that triggered the stop bit. This can improve instruction +scheduling, but does not always do so. +.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 +.IX Item "-mfixed-range=register-range" +Generate code treating the given register range as fixed registers. +A fixed register is one that the register allocator can not use. This is +useful when compiling kernel code. A register range is specified as +two registers separated by a dash. Multiple register ranges can be +specified separated by a comma. +.IP "\fB\-mtls\-size=\fR\fItls-size\fR" 4 +.IX Item "-mtls-size=tls-size" +Specify bit size of immediate \s-1TLS\s0 offsets. Valid values are 14, 22, and +64. +.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 +.IX Item "-mtune=cpu-type" +Tune the instruction scheduling for a particular \s-1CPU\s0, Valid values are +itanium, itanium1, merced, itanium2, and mckinley. +.IP "\fB\-milp32\fR" 4 +.IX Item "-milp32" +.PD 0 +.IP "\fB\-mlp64\fR" 4 +.IX Item "-mlp64" +.PD +Generate code for a 32\-bit or 64\-bit environment. +The 32\-bit environment sets int, long and pointer to 32 bits. +The 64\-bit environment sets int to 32 bits and long and pointer +to 64 bits. These are HP-UX specific flags. +.IP "\fB\-mno\-sched\-br\-data\-spec\fR" 4 +.IX Item "-mno-sched-br-data-spec" +.PD 0 +.IP "\fB\-msched\-br\-data\-spec\fR" 4 +.IX Item "-msched-br-data-spec" +.PD +(Dis/En)able data speculative scheduling before reload. +This will result in generation of the ld.a instructions and +the corresponding check instructions (ld.c / chk.a). +The default is 'disable'. +.IP "\fB\-msched\-ar\-data\-spec\fR" 4 +.IX Item "-msched-ar-data-spec" +.PD 0 +.IP "\fB\-mno\-sched\-ar\-data\-spec\fR" 4 +.IX Item "-mno-sched-ar-data-spec" +.PD +(En/Dis)able data speculative scheduling after reload. +This will result in generation of the ld.a instructions and +the corresponding check instructions (ld.c / chk.a). +The default is 'enable'. +.IP "\fB\-mno\-sched\-control\-spec\fR" 4 +.IX Item "-mno-sched-control-spec" +.PD 0 +.IP "\fB\-msched\-control\-spec\fR" 4 +.IX Item "-msched-control-spec" +.PD +(Dis/En)able control speculative scheduling. This feature is +available only during region scheduling (i.e. before reload). +This will result in generation of the ld.s instructions and +the corresponding check instructions chk.s . +The default is 'disable'. +.IP "\fB\-msched\-br\-in\-data\-spec\fR" 4 +.IX Item "-msched-br-in-data-spec" +.PD 0 +.IP "\fB\-mno\-sched\-br\-in\-data\-spec\fR" 4 +.IX Item "-mno-sched-br-in-data-spec" +.PD +(En/Dis)able speculative scheduling of the instructions that +are dependent on the data speculative loads before reload. +This is effective only with \fB\-msched\-br\-data\-spec\fR enabled. +The default is 'enable'. +.IP "\fB\-msched\-ar\-in\-data\-spec\fR" 4 +.IX Item "-msched-ar-in-data-spec" +.PD 0 +.IP "\fB\-mno\-sched\-ar\-in\-data\-spec\fR" 4 +.IX Item "-mno-sched-ar-in-data-spec" +.PD +(En/Dis)able speculative scheduling of the instructions that +are dependent on the data speculative loads after reload. +This is effective only with \fB\-msched\-ar\-data\-spec\fR enabled. +The default is 'enable'. +.IP "\fB\-msched\-in\-control\-spec\fR" 4 +.IX Item "-msched-in-control-spec" +.PD 0 +.IP "\fB\-mno\-sched\-in\-control\-spec\fR" 4 +.IX Item "-mno-sched-in-control-spec" +.PD +(En/Dis)able speculative scheduling of the instructions that +are dependent on the control speculative loads. +This is effective only with \fB\-msched\-control\-spec\fR enabled. +The default is 'enable'. +.IP "\fB\-mno\-sched\-prefer\-non\-data\-spec\-insns\fR" 4 +.IX Item "-mno-sched-prefer-non-data-spec-insns" +.PD 0 +.IP "\fB\-msched\-prefer\-non\-data\-spec\-insns\fR" 4 +.IX Item "-msched-prefer-non-data-spec-insns" +.PD +If enabled, data speculative instructions will be chosen for schedule +only if there are no other choices at the moment. This will make +the use of the data speculation much more conservative. +The default is 'disable'. +.IP "\fB\-mno\-sched\-prefer\-non\-control\-spec\-insns\fR" 4 +.IX Item "-mno-sched-prefer-non-control-spec-insns" +.PD 0 +.IP "\fB\-msched\-prefer\-non\-control\-spec\-insns\fR" 4 +.IX Item "-msched-prefer-non-control-spec-insns" +.PD +If enabled, control speculative instructions will be chosen for schedule +only if there are no other choices at the moment. This will make +the use of the control speculation much more conservative. +The default is 'disable'. +.IP "\fB\-mno\-sched\-count\-spec\-in\-critical\-path\fR" 4 +.IX Item "-mno-sched-count-spec-in-critical-path" +.PD 0 +.IP "\fB\-msched\-count\-spec\-in\-critical\-path\fR" 4 +.IX Item "-msched-count-spec-in-critical-path" +.PD +If enabled, speculative dependencies will be considered during +computation of the instructions priorities. This will make the use of the +speculation a bit more conservative. +The default is 'disable'. +.IP "\fB\-msched\-spec\-ldc\fR" 4 +.IX Item "-msched-spec-ldc" +Use a simple data speculation check. This option is on by default. +.IP "\fB\-msched\-control\-spec\-ldc\fR" 4 +.IX Item "-msched-control-spec-ldc" +Use a simple check for control speculation. This option is on by default. +.IP "\fB\-msched\-stop\-bits\-after\-every\-cycle\fR" 4 +.IX Item "-msched-stop-bits-after-every-cycle" +Place a stop bit after every cycle when scheduling. This option is on +by default. +.IP "\fB\-msched\-fp\-mem\-deps\-zero\-cost\fR" 4 +.IX Item "-msched-fp-mem-deps-zero-cost" +Assume that floating-point stores and loads are not likely to cause a conflict +when placed into the same instruction group. This option is disabled by +default. +.IP "\fB\-msel\-sched\-dont\-check\-control\-spec\fR" 4 +.IX Item "-msel-sched-dont-check-control-spec" +Generate checks for control speculation in selective scheduling. +This flag is disabled by default. +.IP "\fB\-msched\-max\-memory\-insns=\fR\fImax-insns\fR" 4 +.IX Item "-msched-max-memory-insns=max-insns" +Limit on the number of memory insns per instruction group, giving lower +priority to subsequent memory insns attempting to schedule in the same +instruction group. Frequently useful to prevent cache bank conflicts. +The default value is 1. +.IP "\fB\-msched\-max\-memory\-insns\-hard\-limit\fR" 4 +.IX Item "-msched-max-memory-insns-hard-limit" +Disallow more than `msched\-max\-memory\-insns' in instruction group. +Otherwise, limit is `soft' meaning that we would prefer non-memory operations +when limit is reached but may still schedule memory operations. +.PP +\fI\s-1IA\-64/VMS\s0 Options\fR +.IX Subsection "IA-64/VMS Options" +.PP +These \fB\-m\fR options are defined for the \s-1IA\-64/VMS\s0 implementations: +.IP "\fB\-mvms\-return\-codes\fR" 4 +.IX Item "-mvms-return-codes" +Return \s-1VMS\s0 condition codes from main. The default is to return \s-1POSIX\s0 +style condition (e.g. error) codes. +.IP "\fB\-mdebug\-main=\fR\fIprefix\fR" 4 +.IX Item "-mdebug-main=prefix" +Flag the first routine whose name starts with \fIprefix\fR as the main +routine for the debugger. +.IP "\fB\-mmalloc64\fR" 4 +.IX Item "-mmalloc64" +Default to 64bit memory allocation routines. +.PP +\fI\s-1LM32\s0 Options\fR +.IX Subsection "LM32 Options" +.PP +These \fB\-m\fR options are defined for the Lattice Mico32 architecture: +.IP "\fB\-mbarrel\-shift\-enabled\fR" 4 +.IX Item "-mbarrel-shift-enabled" +Enable barrel-shift instructions. +.IP "\fB\-mdivide\-enabled\fR" 4 +.IX Item "-mdivide-enabled" +Enable divide and modulus instructions. +.IP "\fB\-mmultiply\-enabled\fR" 4 +.IX Item "-mmultiply-enabled" +Enable multiply instructions. +.IP "\fB\-msign\-extend\-enabled\fR" 4 +.IX Item "-msign-extend-enabled" +Enable sign extend instructions. +.IP "\fB\-muser\-enabled\fR" 4 +.IX Item "-muser-enabled" +Enable user-defined instructions. +.PP +\fIM32C Options\fR +.IX Subsection "M32C Options" +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +Select the \s-1CPU\s0 for which code is generated. \fIname\fR may be one of +\&\fBr8c\fR for the R8C/Tiny series, \fBm16c\fR for the M16C (up to +/60) series, \fBm32cm\fR for the M16C/80 series, or \fBm32c\fR for +the M32C/80 series. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Specifies that the program will be run on the simulator. This causes +an alternate runtime library to be linked in which supports, for +example, file I/O. You must not use this option when generating +programs that will run on real hardware; you must provide your own +runtime library for whatever I/O functions are needed. +.IP "\fB\-memregs=\fR\fInumber\fR" 4 +.IX Item "-memregs=number" +Specifies the number of memory-based pseudo-registers \s-1GCC\s0 will use +during code generation. These pseudo-registers will be used like real +registers, so there is a tradeoff between \s-1GCC\s0's ability to fit the +code into available registers, and the performance penalty of using +memory instead of registers. Note that all modules in a program must +be compiled with the same value for this option. Because of that, you +must not use this option with the default runtime libraries gcc +builds. +.PP +\fIM32R/D Options\fR +.IX Subsection "M32R/D Options" +.PP +These \fB\-m\fR options are defined for Renesas M32R/D architectures: +.IP "\fB\-m32r2\fR" 4 +.IX Item "-m32r2" +Generate code for the M32R/2. +.IP "\fB\-m32rx\fR" 4 +.IX Item "-m32rx" +Generate code for the M32R/X. +.IP "\fB\-m32r\fR" 4 +.IX Item "-m32r" +Generate code for the M32R. This is the default. +.IP "\fB\-mmodel=small\fR" 4 +.IX Item "-mmodel=small" +Assume all objects live in the lower 16MB of memory (so that their addresses +can be loaded with the \f(CW\*(C`ld24\*(C'\fR instruction), and assume all subroutines +are reachable with the \f(CW\*(C`bl\*(C'\fR instruction. +This is the default. +.Sp +The addressability of a particular object can be set with the +\&\f(CW\*(C`model\*(C'\fR attribute. +.IP "\fB\-mmodel=medium\fR" 4 +.IX Item "-mmodel=medium" +Assume objects may be anywhere in the 32\-bit address space (the compiler +will generate \f(CW\*(C`seth/add3\*(C'\fR instructions to load their addresses), and +assume all subroutines are reachable with the \f(CW\*(C`bl\*(C'\fR instruction. +.IP "\fB\-mmodel=large\fR" 4 +.IX Item "-mmodel=large" +Assume objects may be anywhere in the 32\-bit address space (the compiler +will generate \f(CW\*(C`seth/add3\*(C'\fR instructions to load their addresses), and +assume subroutines may not be reachable with the \f(CW\*(C`bl\*(C'\fR instruction +(the compiler will generate the much slower \f(CW\*(C`seth/add3/jl\*(C'\fR +instruction sequence). +.IP "\fB\-msdata=none\fR" 4 +.IX Item "-msdata=none" +Disable use of the small data area. Variables will be put into +one of \fB.data\fR, \fBbss\fR, or \fB.rodata\fR (unless the +\&\f(CW\*(C`section\*(C'\fR attribute has been specified). +This is the default. +.Sp +The small data area consists of sections \fB.sdata\fR and \fB.sbss\fR. +Objects may be explicitly put in the small data area with the +\&\f(CW\*(C`section\*(C'\fR attribute using one of these sections. +.IP "\fB\-msdata=sdata\fR" 4 +.IX Item "-msdata=sdata" +Put small global and static data in the small data area, but do not +generate special code to reference them. +.IP "\fB\-msdata=use\fR" 4 +.IX Item "-msdata=use" +Put small global and static data in the small data area, and generate +special instructions to reference them. +.IP "\fB\-G\fR \fInum\fR" 4 +.IX Item "-G num" +Put global and static objects less than or equal to \fInum\fR bytes +into the small data or bss sections instead of the normal data or bss +sections. The default value of \fInum\fR is 8. +The \fB\-msdata\fR option must be set to one of \fBsdata\fR or \fBuse\fR +for this option to have any effect. +.Sp +All modules should be compiled with the same \fB\-G\fR \fInum\fR value. +Compiling with different values of \fInum\fR may or may not work; if it +doesn't the linker will give an error message\-\-\-incorrect code will not be +generated. +.IP "\fB\-mdebug\fR" 4 +.IX Item "-mdebug" +Makes the M32R specific code in the compiler display some statistics +that might help in debugging programs. +.IP "\fB\-malign\-loops\fR" 4 +.IX Item "-malign-loops" +Align all loops to a 32\-byte boundary. +.IP "\fB\-mno\-align\-loops\fR" 4 +.IX Item "-mno-align-loops" +Do not enforce a 32\-byte alignment for loops. This is the default. +.IP "\fB\-missue\-rate=\fR\fInumber\fR" 4 +.IX Item "-missue-rate=number" +Issue \fInumber\fR instructions per cycle. \fInumber\fR can only be 1 +or 2. +.IP "\fB\-mbranch\-cost=\fR\fInumber\fR" 4 +.IX Item "-mbranch-cost=number" +\&\fInumber\fR can only be 1 or 2. If it is 1 then branches will be +preferred over conditional code, if it is 2, then the opposite will +apply. +.IP "\fB\-mflush\-trap=\fR\fInumber\fR" 4 +.IX Item "-mflush-trap=number" +Specifies the trap number to use to flush the cache. The default is +12. Valid numbers are between 0 and 15 inclusive. +.IP "\fB\-mno\-flush\-trap\fR" 4 +.IX Item "-mno-flush-trap" +Specifies that the cache cannot be flushed by using a trap. +.IP "\fB\-mflush\-func=\fR\fIname\fR" 4 +.IX Item "-mflush-func=name" +Specifies the name of the operating system function to call to flush +the cache. The default is \fI_flush_cache\fR, but a function call +will only be used if a trap is not available. +.IP "\fB\-mno\-flush\-func\fR" 4 +.IX Item "-mno-flush-func" +Indicates that there is no \s-1OS\s0 function for flushing the cache. +.PP +\fIM680x0 Options\fR +.IX Subsection "M680x0 Options" +.PP +These are the \fB\-m\fR options defined for M680x0 and ColdFire processors. +The default settings depend on which architecture was selected when +the compiler was configured; the defaults for the most common choices +are given below. +.IP "\fB\-march=\fR\fIarch\fR" 4 +.IX Item "-march=arch" +Generate code for a specific M680x0 or ColdFire instruction set +architecture. Permissible values of \fIarch\fR for M680x0 +architectures are: \fB68000\fR, \fB68010\fR, \fB68020\fR, +\&\fB68030\fR, \fB68040\fR, \fB68060\fR and \fBcpu32\fR. ColdFire +architectures are selected according to Freescale's \s-1ISA\s0 classification +and the permissible values are: \fBisaa\fR, \fBisaaplus\fR, +\&\fBisab\fR and \fBisac\fR. +.Sp +gcc defines a macro \fB_\|_mcf\fR\fIarch\fR\fB_\|_\fR whenever it is generating +code for a ColdFire target. The \fIarch\fR in this macro is one of the +\&\fB\-march\fR arguments given above. +.Sp +When used together, \fB\-march\fR and \fB\-mtune\fR select code +that runs on a family of similar processors but that is optimized +for a particular microarchitecture. +.IP "\fB\-mcpu=\fR\fIcpu\fR" 4 +.IX Item "-mcpu=cpu" +Generate code for a specific M680x0 or ColdFire processor. +The M680x0 \fIcpu\fRs are: \fB68000\fR, \fB68010\fR, \fB68020\fR, +\&\fB68030\fR, \fB68040\fR, \fB68060\fR, \fB68302\fR, \fB68332\fR +and \fBcpu32\fR. The ColdFire \fIcpu\fRs are given by the table +below, which also classifies the CPUs into families: +.RS 4 +.IP "Family : \fB\-mcpu\fR arguments" 4 +.IX Item "Family : -mcpu arguments" +.PD 0 +.IP "\fB51\fR : \fB51\fR \fB51ac\fR \fB51cn\fR \fB51em\fR \fB51qe\fR" 4 +.IX Item "51 : 51 51ac 51cn 51em 51qe" +.IP "\fB5206\fR : \fB5202\fR \fB5204\fR \fB5206\fR" 4 +.IX Item "5206 : 5202 5204 5206" +.IP "\fB5206e\fR : \fB5206e\fR" 4 +.IX Item "5206e : 5206e" +.IP "\fB5208\fR : \fB5207\fR \fB5208\fR" 4 +.IX Item "5208 : 5207 5208" +.IP "\fB5211a\fR : \fB5210a\fR \fB5211a\fR" 4 +.IX Item "5211a : 5210a 5211a" +.IP "\fB5213\fR : \fB5211\fR \fB5212\fR \fB5213\fR" 4 +.IX Item "5213 : 5211 5212 5213" +.IP "\fB5216\fR : \fB5214\fR \fB5216\fR" 4 +.IX Item "5216 : 5214 5216" +.IP "\fB52235\fR : \fB52230\fR \fB52231\fR \fB52232\fR \fB52233\fR \fB52234\fR \fB52235\fR" 4 +.IX Item "52235 : 52230 52231 52232 52233 52234 52235" +.IP "\fB5225\fR : \fB5224\fR \fB5225\fR" 4 +.IX Item "5225 : 5224 5225" +.IP "\fB52259\fR : \fB52252\fR \fB52254\fR \fB52255\fR \fB52256\fR \fB52258\fR \fB52259\fR" 4 +.IX Item "52259 : 52252 52254 52255 52256 52258 52259" +.IP "\fB5235\fR : \fB5232\fR \fB5233\fR \fB5234\fR \fB5235\fR \fB523x\fR" 4 +.IX Item "5235 : 5232 5233 5234 5235 523x" +.IP "\fB5249\fR : \fB5249\fR" 4 +.IX Item "5249 : 5249" +.IP "\fB5250\fR : \fB5250\fR" 4 +.IX Item "5250 : 5250" +.IP "\fB5271\fR : \fB5270\fR \fB5271\fR" 4 +.IX Item "5271 : 5270 5271" +.IP "\fB5272\fR : \fB5272\fR" 4 +.IX Item "5272 : 5272" +.IP "\fB5275\fR : \fB5274\fR \fB5275\fR" 4 +.IX Item "5275 : 5274 5275" +.IP "\fB5282\fR : \fB5280\fR \fB5281\fR \fB5282\fR \fB528x\fR" 4 +.IX Item "5282 : 5280 5281 5282 528x" +.IP "\fB53017\fR : \fB53011\fR \fB53012\fR \fB53013\fR \fB53014\fR \fB53015\fR \fB53016\fR \fB53017\fR" 4 +.IX Item "53017 : 53011 53012 53013 53014 53015 53016 53017" +.IP "\fB5307\fR : \fB5307\fR" 4 +.IX Item "5307 : 5307" +.IP "\fB5329\fR : \fB5327\fR \fB5328\fR \fB5329\fR \fB532x\fR" 4 +.IX Item "5329 : 5327 5328 5329 532x" +.IP "\fB5373\fR : \fB5372\fR \fB5373\fR \fB537x\fR" 4 +.IX Item "5373 : 5372 5373 537x" +.IP "\fB5407\fR : \fB5407\fR" 4 +.IX Item "5407 : 5407" +.IP "\fB5475\fR : \fB5470\fR \fB5471\fR \fB5472\fR \fB5473\fR \fB5474\fR \fB5475\fR \fB547x\fR \fB5480\fR \fB5481\fR \fB5482\fR \fB5483\fR \fB5484\fR \fB5485\fR" 4 +.IX Item "5475 : 5470 5471 5472 5473 5474 5475 547x 5480 5481 5482 5483 5484 5485" +.RE +.RS 4 +.PD +.Sp +\&\fB\-mcpu=\fR\fIcpu\fR overrides \fB\-march=\fR\fIarch\fR if +\&\fIarch\fR is compatible with \fIcpu\fR. Other combinations of +\&\fB\-mcpu\fR and \fB\-march\fR are rejected. +.Sp +gcc defines the macro \fB_\|_mcf_cpu_\fR\fIcpu\fR when ColdFire target +\&\fIcpu\fR is selected. It also defines \fB_\|_mcf_family_\fR\fIfamily\fR, +where the value of \fIfamily\fR is given by the table above. +.RE +.IP "\fB\-mtune=\fR\fItune\fR" 4 +.IX Item "-mtune=tune" +Tune the code for a particular microarchitecture, within the +constraints set by \fB\-march\fR and \fB\-mcpu\fR. +The M680x0 microarchitectures are: \fB68000\fR, \fB68010\fR, +\&\fB68020\fR, \fB68030\fR, \fB68040\fR, \fB68060\fR +and \fBcpu32\fR. The ColdFire microarchitectures +are: \fBcfv1\fR, \fBcfv2\fR, \fBcfv3\fR, \fBcfv4\fR and \fBcfv4e\fR. +.Sp +You can also use \fB\-mtune=68020\-40\fR for code that needs +to run relatively well on 68020, 68030 and 68040 targets. +\&\fB\-mtune=68020\-60\fR is similar but includes 68060 targets +as well. These two options select the same tuning decisions as +\&\fB\-m68020\-40\fR and \fB\-m68020\-60\fR respectively. +.Sp +gcc defines the macros \fB_\|_mc\fR\fIarch\fR and \fB_\|_mc\fR\fIarch\fR\fB_\|_\fR +when tuning for 680x0 architecture \fIarch\fR. It also defines +\&\fBmc\fR\fIarch\fR unless either \fB\-ansi\fR or a non-GNU \fB\-std\fR +option is used. If gcc is tuning for a range of architectures, +as selected by \fB\-mtune=68020\-40\fR or \fB\-mtune=68020\-60\fR, +it defines the macros for every architecture in the range. +.Sp +gcc also defines the macro \fB_\|_m\fR\fIuarch\fR\fB_\|_\fR when tuning for +ColdFire microarchitecture \fIuarch\fR, where \fIuarch\fR is one +of the arguments given above. +.IP "\fB\-m68000\fR" 4 +.IX Item "-m68000" +.PD 0 +.IP "\fB\-mc68000\fR" 4 +.IX Item "-mc68000" +.PD +Generate output for a 68000. This is the default +when the compiler is configured for 68000\-based systems. +It is equivalent to \fB\-march=68000\fR. +.Sp +Use this option for microcontrollers with a 68000 or \s-1EC000\s0 core, +including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356. +.IP "\fB\-m68010\fR" 4 +.IX Item "-m68010" +Generate output for a 68010. This is the default +when the compiler is configured for 68010\-based systems. +It is equivalent to \fB\-march=68010\fR. +.IP "\fB\-m68020\fR" 4 +.IX Item "-m68020" +.PD 0 +.IP "\fB\-mc68020\fR" 4 +.IX Item "-mc68020" +.PD +Generate output for a 68020. This is the default +when the compiler is configured for 68020\-based systems. +It is equivalent to \fB\-march=68020\fR. +.IP "\fB\-m68030\fR" 4 +.IX Item "-m68030" +Generate output for a 68030. This is the default when the compiler is +configured for 68030\-based systems. It is equivalent to +\&\fB\-march=68030\fR. +.IP "\fB\-m68040\fR" 4 +.IX Item "-m68040" +Generate output for a 68040. This is the default when the compiler is +configured for 68040\-based systems. It is equivalent to +\&\fB\-march=68040\fR. +.Sp +This option inhibits the use of 68881/68882 instructions that have to be +emulated by software on the 68040. Use this option if your 68040 does not +have code to emulate those instructions. +.IP "\fB\-m68060\fR" 4 +.IX Item "-m68060" +Generate output for a 68060. This is the default when the compiler is +configured for 68060\-based systems. It is equivalent to +\&\fB\-march=68060\fR. +.Sp +This option inhibits the use of 68020 and 68881/68882 instructions that +have to be emulated by software on the 68060. Use this option if your 68060 +does not have code to emulate those instructions. +.IP "\fB\-mcpu32\fR" 4 +.IX Item "-mcpu32" +Generate output for a \s-1CPU32\s0. This is the default +when the compiler is configured for CPU32\-based systems. +It is equivalent to \fB\-march=cpu32\fR. +.Sp +Use this option for microcontrollers with a +\&\s-1CPU32\s0 or \s-1CPU32+\s0 core, including the 68330, 68331, 68332, 68333, 68334, +68336, 68340, 68341, 68349 and 68360. +.IP "\fB\-m5200\fR" 4 +.IX Item "-m5200" +Generate output for a 520X ColdFire \s-1CPU\s0. This is the default +when the compiler is configured for 520X\-based systems. +It is equivalent to \fB\-mcpu=5206\fR, and is now deprecated +in favor of that option. +.Sp +Use this option for microcontroller with a 5200 core, including +the \s-1MCF5202\s0, \s-1MCF5203\s0, \s-1MCF5204\s0 and \s-1MCF5206\s0. +.IP "\fB\-m5206e\fR" 4 +.IX Item "-m5206e" +Generate output for a 5206e ColdFire \s-1CPU\s0. The option is now +deprecated in favor of the equivalent \fB\-mcpu=5206e\fR. +.IP "\fB\-m528x\fR" 4 +.IX Item "-m528x" +Generate output for a member of the ColdFire 528X family. +The option is now deprecated in favor of the equivalent +\&\fB\-mcpu=528x\fR. +.IP "\fB\-m5307\fR" 4 +.IX Item "-m5307" +Generate output for a ColdFire 5307 \s-1CPU\s0. The option is now deprecated +in favor of the equivalent \fB\-mcpu=5307\fR. +.IP "\fB\-m5407\fR" 4 +.IX Item "-m5407" +Generate output for a ColdFire 5407 \s-1CPU\s0. The option is now deprecated +in favor of the equivalent \fB\-mcpu=5407\fR. +.IP "\fB\-mcfv4e\fR" 4 +.IX Item "-mcfv4e" +Generate output for a ColdFire V4e family \s-1CPU\s0 (e.g. 547x/548x). +This includes use of hardware floating point instructions. +The option is equivalent to \fB\-mcpu=547x\fR, and is now +deprecated in favor of that option. +.IP "\fB\-m68020\-40\fR" 4 +.IX Item "-m68020-40" +Generate output for a 68040, without using any of the new instructions. +This results in code which can run relatively efficiently on either a +68020/68881 or a 68030 or a 68040. The generated code does use the +68881 instructions that are emulated on the 68040. +.Sp +The option is equivalent to \fB\-march=68020\fR \fB\-mtune=68020\-40\fR. +.IP "\fB\-m68020\-60\fR" 4 +.IX Item "-m68020-60" +Generate output for a 68060, without using any of the new instructions. +This results in code which can run relatively efficiently on either a +68020/68881 or a 68030 or a 68040. The generated code does use the +68881 instructions that are emulated on the 68060. +.Sp +The option is equivalent to \fB\-march=68020\fR \fB\-mtune=68020\-60\fR. +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD 0 +.IP "\fB\-m68881\fR" 4 +.IX Item "-m68881" +.PD +Generate floating-point instructions. This is the default for 68020 +and above, and for ColdFire devices that have an \s-1FPU\s0. It defines the +macro \fB_\|_HAVE_68881_\|_\fR on M680x0 targets and \fB_\|_mcffpu_\|_\fR +on ColdFire targets. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Do not generate floating-point instructions; use library calls instead. +This is the default for 68000, 68010, and 68832 targets. It is also +the default for ColdFire devices that have no \s-1FPU\s0. +.IP "\fB\-mdiv\fR" 4 +.IX Item "-mdiv" +.PD 0 +.IP "\fB\-mno\-div\fR" 4 +.IX Item "-mno-div" +.PD +Generate (do not generate) ColdFire hardware divide and remainder +instructions. If \fB\-march\fR is used without \fB\-mcpu\fR, +the default is \*(L"on\*(R" for ColdFire architectures and \*(L"off\*(R" for M680x0 +architectures. Otherwise, the default is taken from the target \s-1CPU\s0 +(either the default \s-1CPU\s0, or the one specified by \fB\-mcpu\fR). For +example, the default is \*(L"off\*(R" for \fB\-mcpu=5206\fR and \*(L"on\*(R" for +\&\fB\-mcpu=5206e\fR. +.Sp +gcc defines the macro \fB_\|_mcfhwdiv_\|_\fR when this option is enabled. +.IP "\fB\-mshort\fR" 4 +.IX Item "-mshort" +Consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide, like \f(CW\*(C`short int\*(C'\fR. +Additionally, parameters passed on the stack are also aligned to a +16\-bit boundary even on targets whose \s-1API\s0 mandates promotion to 32\-bit. +.IP "\fB\-mno\-short\fR" 4 +.IX Item "-mno-short" +Do not consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide. This is the default. +.IP "\fB\-mnobitfield\fR" 4 +.IX Item "-mnobitfield" +.PD 0 +.IP "\fB\-mno\-bitfield\fR" 4 +.IX Item "-mno-bitfield" +.PD +Do not use the bit-field instructions. The \fB\-m68000\fR, \fB\-mcpu32\fR +and \fB\-m5200\fR options imply \fB\-mnobitfield\fR. +.IP "\fB\-mbitfield\fR" 4 +.IX Item "-mbitfield" +Do use the bit-field instructions. The \fB\-m68020\fR option implies +\&\fB\-mbitfield\fR. This is the default if you use a configuration +designed for a 68020. +.IP "\fB\-mrtd\fR" 4 +.IX Item "-mrtd" +Use a different function-calling convention, in which functions +that take a fixed number of arguments return with the \f(CW\*(C`rtd\*(C'\fR +instruction, which pops their arguments while returning. This +saves one instruction in the caller since there is no need to pop +the arguments there. +.Sp +This calling convention is incompatible with the one normally +used on Unix, so you cannot use it if you need to call libraries +compiled with the Unix compiler. +.Sp +Also, you must provide function prototypes for all functions that +take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR); +otherwise incorrect code will be generated for calls to those +functions. +.Sp +In addition, seriously incorrect code will result if you call a +function with too many arguments. (Normally, extra arguments are +harmlessly ignored.) +.Sp +The \f(CW\*(C`rtd\*(C'\fR instruction is supported by the 68010, 68020, 68030, +68040, 68060 and \s-1CPU32\s0 processors, but not by the 68000 or 5200. +.IP "\fB\-mno\-rtd\fR" 4 +.IX Item "-mno-rtd" +Do not use the calling conventions selected by \fB\-mrtd\fR. +This is the default. +.IP "\fB\-malign\-int\fR" 4 +.IX Item "-malign-int" +.PD 0 +.IP "\fB\-mno\-align\-int\fR" 4 +.IX Item "-mno-align-int" +.PD +Control whether \s-1GCC\s0 aligns \f(CW\*(C`int\*(C'\fR, \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`long long\*(C'\fR, +\&\f(CW\*(C`float\*(C'\fR, \f(CW\*(C`double\*(C'\fR, and \f(CW\*(C`long double\*(C'\fR variables on a 32\-bit +boundary (\fB\-malign\-int\fR) or a 16\-bit boundary (\fB\-mno\-align\-int\fR). +Aligning variables on 32\-bit boundaries produces code that runs somewhat +faster on processors with 32\-bit busses at the expense of more memory. +.Sp +\&\fBWarning:\fR if you use the \fB\-malign\-int\fR switch, \s-1GCC\s0 will +align structures containing the above types differently than +most published application binary interface specifications for the m68k. +.IP "\fB\-mpcrel\fR" 4 +.IX Item "-mpcrel" +Use the pc-relative addressing mode of the 68000 directly, instead of +using a global offset table. At present, this option implies \fB\-fpic\fR, +allowing at most a 16\-bit offset for pc-relative addressing. \fB\-fPIC\fR is +not presently supported with \fB\-mpcrel\fR, though this could be supported for +68020 and higher processors. +.IP "\fB\-mno\-strict\-align\fR" 4 +.IX Item "-mno-strict-align" +.PD 0 +.IP "\fB\-mstrict\-align\fR" 4 +.IX Item "-mstrict-align" +.PD +Do not (do) assume that unaligned memory references will be handled by +the system. +.IP "\fB\-msep\-data\fR" 4 +.IX Item "-msep-data" +Generate code that allows the data segment to be located in a different +area of memory from the text segment. This allows for execute in place in +an environment without virtual memory management. This option implies +\&\fB\-fPIC\fR. +.IP "\fB\-mno\-sep\-data\fR" 4 +.IX Item "-mno-sep-data" +Generate code that assumes that the data segment follows the text segment. +This is the default. +.IP "\fB\-mid\-shared\-library\fR" 4 +.IX Item "-mid-shared-library" +Generate code that supports shared libraries via the library \s-1ID\s0 method. +This allows for execute in place and shared libraries in an environment +without virtual memory management. This option implies \fB\-fPIC\fR. +.IP "\fB\-mno\-id\-shared\-library\fR" 4 +.IX Item "-mno-id-shared-library" +Generate code that doesn't assume \s-1ID\s0 based shared libraries are being used. +This is the default. +.IP "\fB\-mshared\-library\-id=n\fR" 4 +.IX Item "-mshared-library-id=n" +Specified the identification number of the \s-1ID\s0 based shared library being +compiled. Specifying a value of 0 will generate more compact code, specifying +other values will force the allocation of that number to the current +library but is no more space or time efficient than omitting this option. +.IP "\fB\-mxgot\fR" 4 +.IX Item "-mxgot" +.PD 0 +.IP "\fB\-mno\-xgot\fR" 4 +.IX Item "-mno-xgot" +.PD +When generating position-independent code for ColdFire, generate code +that works if the \s-1GOT\s0 has more than 8192 entries. This code is +larger and slower than code generated without this option. On M680x0 +processors, this option is not needed; \fB\-fPIC\fR suffices. +.Sp +\&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT\s0. +While this is relatively efficient, it only works if the \s-1GOT\s0 +is smaller than about 64k. Anything larger causes the linker +to report an error such as: +.Sp +.Vb 1 +\& relocation truncated to fit: R_68K_GOT16O foobar +.Ve +.Sp +If this happens, you should recompile your code with \fB\-mxgot\fR. +It should then work with very large GOTs. However, code generated with +\&\fB\-mxgot\fR is less efficient, since it takes 4 instructions to fetch +the value of a global symbol. +.Sp +Note that some linkers, including newer versions of the \s-1GNU\s0 linker, +can create multiple GOTs and sort \s-1GOT\s0 entries. If you have such a linker, +you should only need to use \fB\-mxgot\fR when compiling a single +object file that accesses more than 8192 \s-1GOT\s0 entries. Very few do. +.Sp +These options have no effect unless \s-1GCC\s0 is generating +position-independent code. +.PP +\fIM68hc1x Options\fR +.IX Subsection "M68hc1x Options" +.PP +These are the \fB\-m\fR options defined for the 68hc11 and 68hc12 +microcontrollers. The default values for these options depends on +which style of microcontroller was selected when the compiler was configured; +the defaults for the most common choices are given below. +.IP "\fB\-m6811\fR" 4 +.IX Item "-m6811" +.PD 0 +.IP "\fB\-m68hc11\fR" 4 +.IX Item "-m68hc11" +.PD +Generate output for a 68HC11. This is the default +when the compiler is configured for 68HC11\-based systems. +.IP "\fB\-m6812\fR" 4 +.IX Item "-m6812" +.PD 0 +.IP "\fB\-m68hc12\fR" 4 +.IX Item "-m68hc12" +.PD +Generate output for a 68HC12. This is the default +when the compiler is configured for 68HC12\-based systems. +.IP "\fB\-m68S12\fR" 4 +.IX Item "-m68S12" +.PD 0 +.IP "\fB\-m68hcs12\fR" 4 +.IX Item "-m68hcs12" +.PD +Generate output for a 68HCS12. +.IP "\fB\-mauto\-incdec\fR" 4 +.IX Item "-mauto-incdec" +Enable the use of 68HC12 pre and post auto-increment and auto-decrement +addressing modes. +.IP "\fB\-minmax\fR" 4 +.IX Item "-minmax" +.PD 0 +.IP "\fB\-mnominmax\fR" 4 +.IX Item "-mnominmax" +.PD +Enable the use of 68HC12 min and max instructions. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +.PD 0 +.IP "\fB\-mno\-long\-calls\fR" 4 +.IX Item "-mno-long-calls" +.PD +Treat all calls as being far away (near). If calls are assumed to be +far away, the compiler will use the \f(CW\*(C`call\*(C'\fR instruction to +call a function and the \f(CW\*(C`rtc\*(C'\fR instruction for returning. +.IP "\fB\-mshort\fR" 4 +.IX Item "-mshort" +Consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide, like \f(CW\*(C`short int\*(C'\fR. +.IP "\fB\-msoft\-reg\-count=\fR\fIcount\fR" 4 +.IX Item "-msoft-reg-count=count" +Specify the number of pseudo-soft registers which are used for the +code generation. The maximum number is 32. Using more pseudo-soft +register may or may not result in better code depending on the program. +The default is 4 for 68HC11 and 2 for 68HC12. +.PP +\fIMCore Options\fR +.IX Subsection "MCore Options" +.PP +These are the \fB\-m\fR options defined for the Motorola M*Core +processors. +.IP "\fB\-mhardlit\fR" 4 +.IX Item "-mhardlit" +.PD 0 +.IP "\fB\-mno\-hardlit\fR" 4 +.IX Item "-mno-hardlit" +.PD +Inline constants into the code stream if it can be done in two +instructions or less. +.IP "\fB\-mdiv\fR" 4 +.IX Item "-mdiv" +.PD 0 +.IP "\fB\-mno\-div\fR" 4 +.IX Item "-mno-div" +.PD +Use the divide instruction. (Enabled by default). +.IP "\fB\-mrelax\-immediate\fR" 4 +.IX Item "-mrelax-immediate" +.PD 0 +.IP "\fB\-mno\-relax\-immediate\fR" 4 +.IX Item "-mno-relax-immediate" +.PD +Allow arbitrary sized immediates in bit operations. +.IP "\fB\-mwide\-bitfields\fR" 4 +.IX Item "-mwide-bitfields" +.PD 0 +.IP "\fB\-mno\-wide\-bitfields\fR" 4 +.IX Item "-mno-wide-bitfields" +.PD +Always treat bit-fields as int-sized. +.IP "\fB\-m4byte\-functions\fR" 4 +.IX Item "-m4byte-functions" +.PD 0 +.IP "\fB\-mno\-4byte\-functions\fR" 4 +.IX Item "-mno-4byte-functions" +.PD +Force all functions to be aligned to a four byte boundary. +.IP "\fB\-mcallgraph\-data\fR" 4 +.IX Item "-mcallgraph-data" +.PD 0 +.IP "\fB\-mno\-callgraph\-data\fR" 4 +.IX Item "-mno-callgraph-data" +.PD +Emit callgraph information. +.IP "\fB\-mslow\-bytes\fR" 4 +.IX Item "-mslow-bytes" +.PD 0 +.IP "\fB\-mno\-slow\-bytes\fR" 4 +.IX Item "-mno-slow-bytes" +.PD +Prefer word access when reading byte quantities. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +.PD 0 +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +.PD +Generate code for a little endian target. +.IP "\fB\-m210\fR" 4 +.IX Item "-m210" +.PD 0 +.IP "\fB\-m340\fR" 4 +.IX Item "-m340" +.PD +Generate code for the 210 processor. +.IP "\fB\-mno\-lsim\fR" 4 +.IX Item "-mno-lsim" +Assume that run-time support has been provided and so omit the +simulator library (\fIlibsim.a)\fR from the linker command line. +.IP "\fB\-mstack\-increment=\fR\fIsize\fR" 4 +.IX Item "-mstack-increment=size" +Set the maximum amount for a single stack increment operation. Large +values can increase the speed of programs which contain functions +that need a large amount of stack space, but they can also trigger a +segmentation fault if the stack is extended too much. The default +value is 0x1000. +.PP +\fIMeP Options\fR +.IX Subsection "MeP Options" +.IP "\fB\-mabsdiff\fR" 4 +.IX Item "-mabsdiff" +Enables the \f(CW\*(C`abs\*(C'\fR instruction, which is the absolute difference +between two registers. +.IP "\fB\-mall\-opts\fR" 4 +.IX Item "-mall-opts" +Enables all the optional instructions \- average, multiply, divide, bit +operations, leading zero, absolute difference, min/max, clip, and +saturation. +.IP "\fB\-maverage\fR" 4 +.IX Item "-maverage" +Enables the \f(CW\*(C`ave\*(C'\fR instruction, which computes the average of two +registers. +.IP "\fB\-mbased=\fR\fIn\fR" 4 +.IX Item "-mbased=n" +Variables of size \fIn\fR bytes or smaller will be placed in the +\&\f(CW\*(C`.based\*(C'\fR section by default. Based variables use the \f(CW$tp\fR +register as a base register, and there is a 128 byte limit to the +\&\f(CW\*(C`.based\*(C'\fR section. +.IP "\fB\-mbitops\fR" 4 +.IX Item "-mbitops" +Enables the bit operation instructions \- bit test (\f(CW\*(C`btstm\*(C'\fR), set +(\f(CW\*(C`bsetm\*(C'\fR), clear (\f(CW\*(C`bclrm\*(C'\fR), invert (\f(CW\*(C`bnotm\*(C'\fR), and +test-and-set (\f(CW\*(C`tas\*(C'\fR). +.IP "\fB\-mc=\fR\fIname\fR" 4 +.IX Item "-mc=name" +Selects which section constant data will be placed in. \fIname\fR may +be \f(CW\*(C`tiny\*(C'\fR, \f(CW\*(C`near\*(C'\fR, or \f(CW\*(C`far\*(C'\fR. +.IP "\fB\-mclip\fR" 4 +.IX Item "-mclip" +Enables the \f(CW\*(C`clip\*(C'\fR instruction. Note that \f(CW\*(C`\-mclip\*(C'\fR is not +useful unless you also provide \f(CW\*(C`\-mminmax\*(C'\fR. +.IP "\fB\-mconfig=\fR\fIname\fR" 4 +.IX Item "-mconfig=name" +Selects one of the build-in core configurations. Each MeP chip has +one or more modules in it; each module has a core \s-1CPU\s0 and a variety of +coprocessors, optional instructions, and peripherals. The +\&\f(CW\*(C`MeP\-Integrator\*(C'\fR tool, not part of \s-1GCC\s0, provides these +configurations through this option; using this option is the same as +using all the corresponding command line options. The default +configuration is \f(CW\*(C`default\*(C'\fR. +.IP "\fB\-mcop\fR" 4 +.IX Item "-mcop" +Enables the coprocessor instructions. By default, this is a 32\-bit +coprocessor. Note that the coprocessor is normally enabled via the +\&\f(CW\*(C`\-mconfig=\*(C'\fR option. +.IP "\fB\-mcop32\fR" 4 +.IX Item "-mcop32" +Enables the 32\-bit coprocessor's instructions. +.IP "\fB\-mcop64\fR" 4 +.IX Item "-mcop64" +Enables the 64\-bit coprocessor's instructions. +.IP "\fB\-mivc2\fR" 4 +.IX Item "-mivc2" +Enables \s-1IVC2\s0 scheduling. \s-1IVC2\s0 is a 64\-bit \s-1VLIW\s0 coprocessor. +.IP "\fB\-mdc\fR" 4 +.IX Item "-mdc" +Causes constant variables to be placed in the \f(CW\*(C`.near\*(C'\fR section. +.IP "\fB\-mdiv\fR" 4 +.IX Item "-mdiv" +Enables the \f(CW\*(C`div\*(C'\fR and \f(CW\*(C`divu\*(C'\fR instructions. +.IP "\fB\-meb\fR" 4 +.IX Item "-meb" +Generate big-endian code. +.IP "\fB\-mel\fR" 4 +.IX Item "-mel" +Generate little-endian code. +.IP "\fB\-mio\-volatile\fR" 4 +.IX Item "-mio-volatile" +Tells the compiler that any variable marked with the \f(CW\*(C`io\*(C'\fR +attribute is to be considered volatile. +.IP "\fB\-ml\fR" 4 +.IX Item "-ml" +Causes variables to be assigned to the \f(CW\*(C`.far\*(C'\fR section by default. +.IP "\fB\-mleadz\fR" 4 +.IX Item "-mleadz" +Enables the \f(CW\*(C`leadz\*(C'\fR (leading zero) instruction. +.IP "\fB\-mm\fR" 4 +.IX Item "-mm" +Causes variables to be assigned to the \f(CW\*(C`.near\*(C'\fR section by default. +.IP "\fB\-mminmax\fR" 4 +.IX Item "-mminmax" +Enables the \f(CW\*(C`min\*(C'\fR and \f(CW\*(C`max\*(C'\fR instructions. +.IP "\fB\-mmult\fR" 4 +.IX Item "-mmult" +Enables the multiplication and multiply-accumulate instructions. +.IP "\fB\-mno\-opts\fR" 4 +.IX Item "-mno-opts" +Disables all the optional instructions enabled by \f(CW\*(C`\-mall\-opts\*(C'\fR. +.IP "\fB\-mrepeat\fR" 4 +.IX Item "-mrepeat" +Enables the \f(CW\*(C`repeat\*(C'\fR and \f(CW\*(C`erepeat\*(C'\fR instructions, used for +low-overhead looping. +.IP "\fB\-ms\fR" 4 +.IX Item "-ms" +Causes all variables to default to the \f(CW\*(C`.tiny\*(C'\fR section. Note +that there is a 65536 byte limit to this section. Accesses to these +variables use the \f(CW%gp\fR base register. +.IP "\fB\-msatur\fR" 4 +.IX Item "-msatur" +Enables the saturation instructions. Note that the compiler does not +currently generate these itself, but this option is included for +compatibility with other tools, like \f(CW\*(C`as\*(C'\fR. +.IP "\fB\-msdram\fR" 4 +.IX Item "-msdram" +Link the SDRAM-based runtime instead of the default ROM-based runtime. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Link the simulator runtime libraries. +.IP "\fB\-msimnovec\fR" 4 +.IX Item "-msimnovec" +Link the simulator runtime libraries, excluding built-in support +for reset and exception vectors and tables. +.IP "\fB\-mtf\fR" 4 +.IX Item "-mtf" +Causes all functions to default to the \f(CW\*(C`.far\*(C'\fR section. Without +this option, functions default to the \f(CW\*(C`.near\*(C'\fR section. +.IP "\fB\-mtiny=\fR\fIn\fR" 4 +.IX Item "-mtiny=n" +Variables that are \fIn\fR bytes or smaller will be allocated to the +\&\f(CW\*(C`.tiny\*(C'\fR section. These variables use the \f(CW$gp\fR base +register. The default for this option is 4, but note that there's a +65536 byte limit to the \f(CW\*(C`.tiny\*(C'\fR section. +.PP +\fIMicroBlaze Options\fR +.IX Subsection "MicroBlaze Options" +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Use software emulation for floating point (default). +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +Use hardware floating point instructions. +.IP "\fB\-mmemcpy\fR" 4 +.IX Item "-mmemcpy" +Do not optimize block moves, use \f(CW\*(C`memcpy\*(C'\fR. +.IP "\fB\-mno\-clearbss\fR" 4 +.IX Item "-mno-clearbss" +This option is deprecated. Use \fB\-fno\-zero\-initialized\-in\-bss\fR instead. +.IP "\fB\-mcpu=\fR\fIcpu-type\fR" 4 +.IX Item "-mcpu=cpu-type" +Use features of and schedule code for given \s-1CPU\s0. +Supported values are in the format \fBv\fR\fIX\fR\fB.\fR\fI\s-1YY\s0\fR\fB.\fR\fIZ\fR, +where \fIX\fR is a major version, \fI\s-1YY\s0\fR is the minor version, and +\&\fIZ\fR is compatibility code. Example values are \fBv3.00.a\fR, +\&\fBv4.00.b\fR, \fBv5.00.a\fR, \fBv5.00.b\fR, \fBv5.00.b\fR, \fBv6.00.a\fR. +.IP "\fB\-mxl\-soft\-mul\fR" 4 +.IX Item "-mxl-soft-mul" +Use software multiply emulation (default). +.IP "\fB\-mxl\-soft\-div\fR" 4 +.IX Item "-mxl-soft-div" +Use software emulation for divides (default). +.IP "\fB\-mxl\-barrel\-shift\fR" 4 +.IX Item "-mxl-barrel-shift" +Use the hardware barrel shifter. +.IP "\fB\-mxl\-pattern\-compare\fR" 4 +.IX Item "-mxl-pattern-compare" +Use pattern compare instructions. +.IP "\fB\-msmall\-divides\fR" 4 +.IX Item "-msmall-divides" +Use table lookup optimization for small signed integer divisions. +.IP "\fB\-mxl\-stack\-check\fR" 4 +.IX Item "-mxl-stack-check" +This option is deprecated. Use \-fstack\-check instead. +.IP "\fB\-mxl\-gp\-opt\fR" 4 +.IX Item "-mxl-gp-opt" +Use \s-1GP\s0 relative sdata/sbss sections. +.IP "\fB\-mxl\-multiply\-high\fR" 4 +.IX Item "-mxl-multiply-high" +Use multiply high instructions for high part of 32x32 multiply. +.IP "\fB\-mxl\-float\-convert\fR" 4 +.IX Item "-mxl-float-convert" +Use hardware floating point conversion instructions. +.IP "\fB\-mxl\-float\-sqrt\fR" 4 +.IX Item "-mxl-float-sqrt" +Use hardware floating point square root instruction. +.IP "\fB\-mxl\-mode\-\fR\fIapp-model\fR" 4 +.IX Item "-mxl-mode-app-model" +Select application model \fIapp-model\fR. Valid models are +.RS 4 +.IP "\fBexecutable\fR" 4 +.IX Item "executable" +normal executable (default), uses startup code \fIcrt0.o\fR. +.IP "\fBxmdstub\fR" 4 +.IX Item "xmdstub" +for use with Xilinx Microprocessor Debugger (\s-1XMD\s0) based +software intrusive debug agent called xmdstub. This uses startup file +\&\fIcrt1.o\fR and sets the start address of the program to be 0x800. +.IP "\fBbootstrap\fR" 4 +.IX Item "bootstrap" +for applications that are loaded using a bootloader. +This model uses startup file \fIcrt2.o\fR which does not contain a processor +reset vector handler. This is suitable for transferring control on a +processor reset to the bootloader rather than the application. +.IP "\fBnovectors\fR" 4 +.IX Item "novectors" +for applications that do not require any of the +MicroBlaze vectors. This option may be useful for applications running +within a monitoring application. This model uses \fIcrt3.o\fR as a startup file. +.RE +.RS 4 +.Sp +Option \fB\-xl\-mode\-\fR\fIapp-model\fR is a deprecated alias for +\&\fB\-mxl\-mode\-\fR\fIapp-model\fR. +.RE +.PP +\fI\s-1MIPS\s0 Options\fR +.IX Subsection "MIPS Options" +.IP "\fB\-EB\fR" 4 +.IX Item "-EB" +Generate big-endian code. +.IP "\fB\-EL\fR" 4 +.IX Item "-EL" +Generate little-endian code. This is the default for \fBmips*el\-*\-*\fR +configurations. +.IP "\fB\-march=\fR\fIarch\fR" 4 +.IX Item "-march=arch" +Generate code that will run on \fIarch\fR, which can be the name of a +generic \s-1MIPS\s0 \s-1ISA\s0, or the name of a particular processor. +The \s-1ISA\s0 names are: +\&\fBmips1\fR, \fBmips2\fR, \fBmips3\fR, \fBmips4\fR, +\&\fBmips32\fR, \fBmips32r2\fR, \fBmips64\fR and \fBmips64r2\fR. +The processor names are: +\&\fB4kc\fR, \fB4km\fR, \fB4kp\fR, \fB4ksc\fR, +\&\fB4kec\fR, \fB4kem\fR, \fB4kep\fR, \fB4ksd\fR, +\&\fB5kc\fR, \fB5kf\fR, +\&\fB20kc\fR, +\&\fB24kc\fR, \fB24kf2_1\fR, \fB24kf1_1\fR, +\&\fB24kec\fR, \fB24kef2_1\fR, \fB24kef1_1\fR, +\&\fB34kc\fR, \fB34kf2_1\fR, \fB34kf1_1\fR, +\&\fB74kc\fR, \fB74kf2_1\fR, \fB74kf1_1\fR, \fB74kf3_2\fR, +\&\fB1004kc\fR, \fB1004kf2_1\fR, \fB1004kf1_1\fR, +\&\fBloongson2e\fR, \fBloongson2f\fR, \fBloongson3a\fR, +\&\fBm4k\fR, +\&\fBocteon\fR, +\&\fBorion\fR, +\&\fBr2000\fR, \fBr3000\fR, \fBr3900\fR, \fBr4000\fR, \fBr4400\fR, +\&\fBr4600\fR, \fBr4650\fR, \fBr6000\fR, \fBr8000\fR, +\&\fBrm7000\fR, \fBrm9000\fR, +\&\fBr10000\fR, \fBr12000\fR, \fBr14000\fR, \fBr16000\fR, +\&\fBsb1\fR, +\&\fBsr71000\fR, +\&\fBvr4100\fR, \fBvr4111\fR, \fBvr4120\fR, \fBvr4130\fR, \fBvr4300\fR, +\&\fBvr5000\fR, \fBvr5400\fR, \fBvr5500\fR +and \fBxlr\fR. +The special value \fBfrom-abi\fR selects the +most compatible architecture for the selected \s-1ABI\s0 (that is, +\&\fBmips1\fR for 32\-bit ABIs and \fBmips3\fR for 64\-bit ABIs). +.Sp +Native Linux/GNU toolchains also support the value \fBnative\fR, +which selects the best architecture option for the host processor. +\&\fB\-march=native\fR has no effect if \s-1GCC\s0 does not recognize +the processor. +.Sp +In processor names, a final \fB000\fR can be abbreviated as \fBk\fR +(for example, \fB\-march=r2k\fR). Prefixes are optional, and +\&\fBvr\fR may be written \fBr\fR. +.Sp +Names of the form \fIn\fR\fBf2_1\fR refer to processors with +FPUs clocked at half the rate of the core, names of the form +\&\fIn\fR\fBf1_1\fR refer to processors with FPUs clocked at the same +rate as the core, and names of the form \fIn\fR\fBf3_2\fR refer to +processors with FPUs clocked a ratio of 3:2 with respect to the core. +For compatibility reasons, \fIn\fR\fBf\fR is accepted as a synonym +for \fIn\fR\fBf2_1\fR while \fIn\fR\fBx\fR and \fIb\fR\fBfx\fR are +accepted as synonyms for \fIn\fR\fBf1_1\fR. +.Sp +\&\s-1GCC\s0 defines two macros based on the value of this option. The first +is \fB_MIPS_ARCH\fR, which gives the name of target architecture, as +a string. The second has the form \fB_MIPS_ARCH_\fR\fIfoo\fR, +where \fIfoo\fR is the capitalized value of \fB_MIPS_ARCH\fR. +For example, \fB\-march=r2000\fR will set \fB_MIPS_ARCH\fR +to \fB\*(L"r2000\*(R"\fR and define the macro \fB_MIPS_ARCH_R2000\fR. +.Sp +Note that the \fB_MIPS_ARCH\fR macro uses the processor names given +above. In other words, it will have the full prefix and will not +abbreviate \fB000\fR as \fBk\fR. In the case of \fBfrom-abi\fR, +the macro names the resolved architecture (either \fB\*(L"mips1\*(R"\fR or +\&\fB\*(L"mips3\*(R"\fR). It names the default architecture when no +\&\fB\-march\fR option is given. +.IP "\fB\-mtune=\fR\fIarch\fR" 4 +.IX Item "-mtune=arch" +Optimize for \fIarch\fR. Among other things, this option controls +the way instructions are scheduled, and the perceived cost of arithmetic +operations. The list of \fIarch\fR values is the same as for +\&\fB\-march\fR. +.Sp +When this option is not used, \s-1GCC\s0 will optimize for the processor +specified by \fB\-march\fR. By using \fB\-march\fR and +\&\fB\-mtune\fR together, it is possible to generate code that will +run on a family of processors, but optimize the code for one +particular member of that family. +.Sp +\&\fB\-mtune\fR defines the macros \fB_MIPS_TUNE\fR and +\&\fB_MIPS_TUNE_\fR\fIfoo\fR, which work in the same way as the +\&\fB\-march\fR ones described above. +.IP "\fB\-mips1\fR" 4 +.IX Item "-mips1" +Equivalent to \fB\-march=mips1\fR. +.IP "\fB\-mips2\fR" 4 +.IX Item "-mips2" +Equivalent to \fB\-march=mips2\fR. +.IP "\fB\-mips3\fR" 4 +.IX Item "-mips3" +Equivalent to \fB\-march=mips3\fR. +.IP "\fB\-mips4\fR" 4 +.IX Item "-mips4" +Equivalent to \fB\-march=mips4\fR. +.IP "\fB\-mips32\fR" 4 +.IX Item "-mips32" +Equivalent to \fB\-march=mips32\fR. +.IP "\fB\-mips32r2\fR" 4 +.IX Item "-mips32r2" +Equivalent to \fB\-march=mips32r2\fR. +.IP "\fB\-mips64\fR" 4 +.IX Item "-mips64" +Equivalent to \fB\-march=mips64\fR. +.IP "\fB\-mips64r2\fR" 4 +.IX Item "-mips64r2" +Equivalent to \fB\-march=mips64r2\fR. +.IP "\fB\-mips16\fR" 4 +.IX Item "-mips16" +.PD 0 +.IP "\fB\-mno\-mips16\fR" 4 +.IX Item "-mno-mips16" +.PD +Generate (do not generate) \s-1MIPS16\s0 code. If \s-1GCC\s0 is targetting a +\&\s-1MIPS32\s0 or \s-1MIPS64\s0 architecture, it will make use of the MIPS16e \s-1ASE\s0. +.Sp +\&\s-1MIPS16\s0 code generation can also be controlled on a per-function basis +by means of \f(CW\*(C`mips16\*(C'\fR and \f(CW\*(C`nomips16\*(C'\fR attributes. +.IP "\fB\-mflip\-mips16\fR" 4 +.IX Item "-mflip-mips16" +Generate \s-1MIPS16\s0 code on alternating functions. This option is provided +for regression testing of mixed MIPS16/non\-MIPS16 code generation, and is +not intended for ordinary use in compiling user code. +.IP "\fB\-minterlink\-mips16\fR" 4 +.IX Item "-minterlink-mips16" +.PD 0 +.IP "\fB\-mno\-interlink\-mips16\fR" 4 +.IX Item "-mno-interlink-mips16" +.PD +Require (do not require) that non\-MIPS16 code be link-compatible with +\&\s-1MIPS16\s0 code. +.Sp +For example, non\-MIPS16 code cannot jump directly to \s-1MIPS16\s0 code; +it must either use a call or an indirect jump. \fB\-minterlink\-mips16\fR +therefore disables direct jumps unless \s-1GCC\s0 knows that the target of the +jump is not \s-1MIPS16\s0. +.IP "\fB\-mabi=32\fR" 4 +.IX Item "-mabi=32" +.PD 0 +.IP "\fB\-mabi=o64\fR" 4 +.IX Item "-mabi=o64" +.IP "\fB\-mabi=n32\fR" 4 +.IX Item "-mabi=n32" +.IP "\fB\-mabi=64\fR" 4 +.IX Item "-mabi=64" +.IP "\fB\-mabi=eabi\fR" 4 +.IX Item "-mabi=eabi" +.PD +Generate code for the given \s-1ABI\s0. +.Sp +Note that the \s-1EABI\s0 has a 32\-bit and a 64\-bit variant. \s-1GCC\s0 normally +generates 64\-bit code when you select a 64\-bit architecture, but you +can use \fB\-mgp32\fR to get 32\-bit code instead. +.Sp +For information about the O64 \s-1ABI\s0, see +<\fBhttp://gcc.gnu.org/projects/mipso64\-abi.html\fR>. +.Sp +\&\s-1GCC\s0 supports a variant of the o32 \s-1ABI\s0 in which floating-point registers +are 64 rather than 32 bits wide. You can select this combination with +\&\fB\-mabi=32\fR \fB\-mfp64\fR. This \s-1ABI\s0 relies on the \fBmthc1\fR +and \fBmfhc1\fR instructions and is therefore only supported for +\&\s-1MIPS32R2\s0 processors. +.Sp +The register assignments for arguments and return values remain the +same, but each scalar value is passed in a single 64\-bit register +rather than a pair of 32\-bit registers. For example, scalar +floating-point values are returned in \fB\f(CB$f0\fB\fR only, not a +\&\fB\f(CB$f0\fB\fR/\fB\f(CB$f1\fB\fR pair. The set of call-saved registers also +remains the same, but all 64 bits are saved. +.IP "\fB\-mabicalls\fR" 4 +.IX Item "-mabicalls" +.PD 0 +.IP "\fB\-mno\-abicalls\fR" 4 +.IX Item "-mno-abicalls" +.PD +Generate (do not generate) code that is suitable for SVR4\-style +dynamic objects. \fB\-mabicalls\fR is the default for SVR4\-based +systems. +.IP "\fB\-mshared\fR" 4 +.IX Item "-mshared" +.PD 0 +.IP "\fB\-mno\-shared\fR" 4 +.IX Item "-mno-shared" +.PD +Generate (do not generate) code that is fully position-independent, +and that can therefore be linked into shared libraries. This option +only affects \fB\-mabicalls\fR. +.Sp +All \fB\-mabicalls\fR code has traditionally been position-independent, +regardless of options like \fB\-fPIC\fR and \fB\-fpic\fR. However, +as an extension, the \s-1GNU\s0 toolchain allows executables to use absolute +accesses for locally-binding symbols. It can also use shorter \s-1GP\s0 +initialization sequences and generate direct calls to locally-defined +functions. This mode is selected by \fB\-mno\-shared\fR. +.Sp +\&\fB\-mno\-shared\fR depends on binutils 2.16 or higher and generates +objects that can only be linked by the \s-1GNU\s0 linker. However, the option +does not affect the \s-1ABI\s0 of the final executable; it only affects the \s-1ABI\s0 +of relocatable objects. Using \fB\-mno\-shared\fR will generally make +executables both smaller and quicker. +.Sp +\&\fB\-mshared\fR is the default. +.IP "\fB\-mplt\fR" 4 +.IX Item "-mplt" +.PD 0 +.IP "\fB\-mno\-plt\fR" 4 +.IX Item "-mno-plt" +.PD +Assume (do not assume) that the static and dynamic linkers +support PLTs and copy relocations. This option only affects +\&\fB\-mno\-shared \-mabicalls\fR. For the n64 \s-1ABI\s0, this option +has no effect without \fB\-msym32\fR. +.Sp +You can make \fB\-mplt\fR the default by configuring +\&\s-1GCC\s0 with \fB\-\-with\-mips\-plt\fR. The default is +\&\fB\-mno\-plt\fR otherwise. +.IP "\fB\-mxgot\fR" 4 +.IX Item "-mxgot" +.PD 0 +.IP "\fB\-mno\-xgot\fR" 4 +.IX Item "-mno-xgot" +.PD +Lift (do not lift) the usual restrictions on the size of the global +offset table. +.Sp +\&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT\s0. +While this is relatively efficient, it will only work if the \s-1GOT\s0 +is smaller than about 64k. Anything larger will cause the linker +to report an error such as: +.Sp +.Vb 1 +\& relocation truncated to fit: R_MIPS_GOT16 foobar +.Ve +.Sp +If this happens, you should recompile your code with \fB\-mxgot\fR. +It should then work with very large GOTs, although it will also be +less efficient, since it will take three instructions to fetch the +value of a global symbol. +.Sp +Note that some linkers can create multiple GOTs. If you have such a +linker, you should only need to use \fB\-mxgot\fR when a single object +file accesses more than 64k's worth of \s-1GOT\s0 entries. Very few do. +.Sp +These options have no effect unless \s-1GCC\s0 is generating position +independent code. +.IP "\fB\-mgp32\fR" 4 +.IX Item "-mgp32" +Assume that general-purpose registers are 32 bits wide. +.IP "\fB\-mgp64\fR" 4 +.IX Item "-mgp64" +Assume that general-purpose registers are 64 bits wide. +.IP "\fB\-mfp32\fR" 4 +.IX Item "-mfp32" +Assume that floating-point registers are 32 bits wide. +.IP "\fB\-mfp64\fR" 4 +.IX Item "-mfp64" +Assume that floating-point registers are 64 bits wide. +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +Use floating-point coprocessor instructions. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Do not use floating-point coprocessor instructions. Implement +floating-point calculations using library calls instead. +.IP "\fB\-msingle\-float\fR" 4 +.IX Item "-msingle-float" +Assume that the floating-point coprocessor only supports single-precision +operations. +.IP "\fB\-mdouble\-float\fR" 4 +.IX Item "-mdouble-float" +Assume that the floating-point coprocessor supports double-precision +operations. This is the default. +.IP "\fB\-mllsc\fR" 4 +.IX Item "-mllsc" +.PD 0 +.IP "\fB\-mno\-llsc\fR" 4 +.IX Item "-mno-llsc" +.PD +Use (do not use) \fBll\fR, \fBsc\fR, and \fBsync\fR instructions to +implement atomic memory built-in functions. When neither option is +specified, \s-1GCC\s0 will use the instructions if the target architecture +supports them. +.Sp +\&\fB\-mllsc\fR is useful if the runtime environment can emulate the +instructions and \fB\-mno\-llsc\fR can be useful when compiling for +nonstandard ISAs. You can make either option the default by +configuring \s-1GCC\s0 with \fB\-\-with\-llsc\fR and \fB\-\-without\-llsc\fR +respectively. \fB\-\-with\-llsc\fR is the default for some +configurations; see the installation documentation for details. +.IP "\fB\-mdsp\fR" 4 +.IX Item "-mdsp" +.PD 0 +.IP "\fB\-mno\-dsp\fR" 4 +.IX Item "-mno-dsp" +.PD +Use (do not use) revision 1 of the \s-1MIPS\s0 \s-1DSP\s0 \s-1ASE\s0. + This option defines the +preprocessor macro \fB_\|_mips_dsp\fR. It also defines +\&\fB_\|_mips_dsp_rev\fR to 1. +.IP "\fB\-mdspr2\fR" 4 +.IX Item "-mdspr2" +.PD 0 +.IP "\fB\-mno\-dspr2\fR" 4 +.IX Item "-mno-dspr2" +.PD +Use (do not use) revision 2 of the \s-1MIPS\s0 \s-1DSP\s0 \s-1ASE\s0. + This option defines the +preprocessor macros \fB_\|_mips_dsp\fR and \fB_\|_mips_dspr2\fR. +It also defines \fB_\|_mips_dsp_rev\fR to 2. +.IP "\fB\-msmartmips\fR" 4 +.IX Item "-msmartmips" +.PD 0 +.IP "\fB\-mno\-smartmips\fR" 4 +.IX Item "-mno-smartmips" +.PD +Use (do not use) the \s-1MIPS\s0 SmartMIPS \s-1ASE\s0. +.IP "\fB\-mpaired\-single\fR" 4 +.IX Item "-mpaired-single" +.PD 0 +.IP "\fB\-mno\-paired\-single\fR" 4 +.IX Item "-mno-paired-single" +.PD +Use (do not use) paired-single floating-point instructions. + This option requires +hardware floating-point support to be enabled. +.IP "\fB\-mdmx\fR" 4 +.IX Item "-mdmx" +.PD 0 +.IP "\fB\-mno\-mdmx\fR" 4 +.IX Item "-mno-mdmx" +.PD +Use (do not use) \s-1MIPS\s0 Digital Media Extension instructions. +This option can only be used when generating 64\-bit code and requires +hardware floating-point support to be enabled. +.IP "\fB\-mips3d\fR" 4 +.IX Item "-mips3d" +.PD 0 +.IP "\fB\-mno\-mips3d\fR" 4 +.IX Item "-mno-mips3d" +.PD +Use (do not use) the \s-1MIPS\-3D\s0 \s-1ASE\s0. +The option \fB\-mips3d\fR implies \fB\-mpaired\-single\fR. +.IP "\fB\-mmt\fR" 4 +.IX Item "-mmt" +.PD 0 +.IP "\fB\-mno\-mt\fR" 4 +.IX Item "-mno-mt" +.PD +Use (do not use) \s-1MT\s0 Multithreading instructions. +.IP "\fB\-mlong64\fR" 4 +.IX Item "-mlong64" +Force \f(CW\*(C`long\*(C'\fR types to be 64 bits wide. See \fB\-mlong32\fR for +an explanation of the default and the way that the pointer size is +determined. +.IP "\fB\-mlong32\fR" 4 +.IX Item "-mlong32" +Force \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`int\*(C'\fR, and pointer types to be 32 bits wide. +.Sp +The default size of \f(CW\*(C`int\*(C'\fRs, \f(CW\*(C`long\*(C'\fRs and pointers depends on +the \s-1ABI\s0. All the supported ABIs use 32\-bit \f(CW\*(C`int\*(C'\fRs. The n64 \s-1ABI\s0 +uses 64\-bit \f(CW\*(C`long\*(C'\fRs, as does the 64\-bit \s-1EABI\s0; the others use +32\-bit \f(CW\*(C`long\*(C'\fRs. Pointers are the same size as \f(CW\*(C`long\*(C'\fRs, +or the same size as integer registers, whichever is smaller. +.IP "\fB\-msym32\fR" 4 +.IX Item "-msym32" +.PD 0 +.IP "\fB\-mno\-sym32\fR" 4 +.IX Item "-mno-sym32" +.PD +Assume (do not assume) that all symbols have 32\-bit values, regardless +of the selected \s-1ABI\s0. This option is useful in combination with +\&\fB\-mabi=64\fR and \fB\-mno\-abicalls\fR because it allows \s-1GCC\s0 +to generate shorter and faster references to symbolic addresses. +.IP "\fB\-G\fR \fInum\fR" 4 +.IX Item "-G num" +Put definitions of externally-visible data in a small data section +if that data is no bigger than \fInum\fR bytes. \s-1GCC\s0 can then access +the data more efficiently; see \fB\-mgpopt\fR for details. +.Sp +The default \fB\-G\fR option depends on the configuration. +.IP "\fB\-mlocal\-sdata\fR" 4 +.IX Item "-mlocal-sdata" +.PD 0 +.IP "\fB\-mno\-local\-sdata\fR" 4 +.IX Item "-mno-local-sdata" +.PD +Extend (do not extend) the \fB\-G\fR behavior to local data too, +such as to static variables in C. \fB\-mlocal\-sdata\fR is the +default for all configurations. +.Sp +If the linker complains that an application is using too much small data, +you might want to try rebuilding the less performance-critical parts with +\&\fB\-mno\-local\-sdata\fR. You might also want to build large +libraries with \fB\-mno\-local\-sdata\fR, so that the libraries leave +more room for the main program. +.IP "\fB\-mextern\-sdata\fR" 4 +.IX Item "-mextern-sdata" +.PD 0 +.IP "\fB\-mno\-extern\-sdata\fR" 4 +.IX Item "-mno-extern-sdata" +.PD +Assume (do not assume) that externally-defined data will be in +a small data section if that data is within the \fB\-G\fR limit. +\&\fB\-mextern\-sdata\fR is the default for all configurations. +.Sp +If you compile a module \fIMod\fR with \fB\-mextern\-sdata\fR \fB\-G\fR +\&\fInum\fR \fB\-mgpopt\fR, and \fIMod\fR references a variable \fIVar\fR +that is no bigger than \fInum\fR bytes, you must make sure that \fIVar\fR +is placed in a small data section. If \fIVar\fR is defined by another +module, you must either compile that module with a high-enough +\&\fB\-G\fR setting or attach a \f(CW\*(C`section\*(C'\fR attribute to \fIVar\fR's +definition. If \fIVar\fR is common, you must link the application +with a high-enough \fB\-G\fR setting. +.Sp +The easiest way of satisfying these restrictions is to compile +and link every module with the same \fB\-G\fR option. However, +you may wish to build a library that supports several different +small data limits. You can do this by compiling the library with +the highest supported \fB\-G\fR setting and additionally using +\&\fB\-mno\-extern\-sdata\fR to stop the library from making assumptions +about externally-defined data. +.IP "\fB\-mgpopt\fR" 4 +.IX Item "-mgpopt" +.PD 0 +.IP "\fB\-mno\-gpopt\fR" 4 +.IX Item "-mno-gpopt" +.PD +Use (do not use) GP-relative accesses for symbols that are known to be +in a small data section; see \fB\-G\fR, \fB\-mlocal\-sdata\fR and +\&\fB\-mextern\-sdata\fR. \fB\-mgpopt\fR is the default for all +configurations. +.Sp +\&\fB\-mno\-gpopt\fR is useful for cases where the \f(CW$gp\fR register +might not hold the value of \f(CW\*(C`_gp\*(C'\fR. For example, if the code is +part of a library that might be used in a boot monitor, programs that +call boot monitor routines will pass an unknown value in \f(CW$gp\fR. +(In such situations, the boot monitor itself would usually be compiled +with \fB\-G0\fR.) +.Sp +\&\fB\-mno\-gpopt\fR implies \fB\-mno\-local\-sdata\fR and +\&\fB\-mno\-extern\-sdata\fR. +.IP "\fB\-membedded\-data\fR" 4 +.IX Item "-membedded-data" +.PD 0 +.IP "\fB\-mno\-embedded\-data\fR" 4 +.IX Item "-mno-embedded-data" +.PD +Allocate variables to the read-only data section first if possible, then +next in the small data section if possible, otherwise in data. This gives +slightly slower code than the default, but reduces the amount of \s-1RAM\s0 required +when executing, and thus may be preferred for some embedded systems. +.IP "\fB\-muninit\-const\-in\-rodata\fR" 4 +.IX Item "-muninit-const-in-rodata" +.PD 0 +.IP "\fB\-mno\-uninit\-const\-in\-rodata\fR" 4 +.IX Item "-mno-uninit-const-in-rodata" +.PD +Put uninitialized \f(CW\*(C`const\*(C'\fR variables in the read-only data section. +This option is only meaningful in conjunction with \fB\-membedded\-data\fR. +.IP "\fB\-mcode\-readable=\fR\fIsetting\fR" 4 +.IX Item "-mcode-readable=setting" +Specify whether \s-1GCC\s0 may generate code that reads from executable sections. +There are three possible settings: +.RS 4 +.IP "\fB\-mcode\-readable=yes\fR" 4 +.IX Item "-mcode-readable=yes" +Instructions may freely access executable sections. This is the +default setting. +.IP "\fB\-mcode\-readable=pcrel\fR" 4 +.IX Item "-mcode-readable=pcrel" +\&\s-1MIPS16\s0 PC-relative load instructions can access executable sections, +but other instructions must not do so. This option is useful on 4KSc +and 4KSd processors when the code TLBs have the Read Inhibit bit set. +It is also useful on processors that can be configured to have a dual +instruction/data \s-1SRAM\s0 interface and that, like the M4K, automatically +redirect PC-relative loads to the instruction \s-1RAM\s0. +.IP "\fB\-mcode\-readable=no\fR" 4 +.IX Item "-mcode-readable=no" +Instructions must not access executable sections. This option can be +useful on targets that are configured to have a dual instruction/data +\&\s-1SRAM\s0 interface but that (unlike the M4K) do not automatically redirect +PC-relative loads to the instruction \s-1RAM\s0. +.RE +.RS 4 +.RE +.IP "\fB\-msplit\-addresses\fR" 4 +.IX Item "-msplit-addresses" +.PD 0 +.IP "\fB\-mno\-split\-addresses\fR" 4 +.IX Item "-mno-split-addresses" +.PD +Enable (disable) use of the \f(CW\*(C`%hi()\*(C'\fR and \f(CW\*(C`%lo()\*(C'\fR assembler +relocation operators. This option has been superseded by +\&\fB\-mexplicit\-relocs\fR but is retained for backwards compatibility. +.IP "\fB\-mexplicit\-relocs\fR" 4 +.IX Item "-mexplicit-relocs" +.PD 0 +.IP "\fB\-mno\-explicit\-relocs\fR" 4 +.IX Item "-mno-explicit-relocs" +.PD +Use (do not use) assembler relocation operators when dealing with symbolic +addresses. The alternative, selected by \fB\-mno\-explicit\-relocs\fR, +is to use assembler macros instead. +.Sp +\&\fB\-mexplicit\-relocs\fR is the default if \s-1GCC\s0 was configured +to use an assembler that supports relocation operators. +.IP "\fB\-mcheck\-zero\-division\fR" 4 +.IX Item "-mcheck-zero-division" +.PD 0 +.IP "\fB\-mno\-check\-zero\-division\fR" 4 +.IX Item "-mno-check-zero-division" +.PD +Trap (do not trap) on integer division by zero. +.Sp +The default is \fB\-mcheck\-zero\-division\fR. +.IP "\fB\-mdivide\-traps\fR" 4 +.IX Item "-mdivide-traps" +.PD 0 +.IP "\fB\-mdivide\-breaks\fR" 4 +.IX Item "-mdivide-breaks" +.PD +\&\s-1MIPS\s0 systems check for division by zero by generating either a +conditional trap or a break instruction. Using traps results in +smaller code, but is only supported on \s-1MIPS\s0 \s-1II\s0 and later. Also, some +versions of the Linux kernel have a bug that prevents trap from +generating the proper signal (\f(CW\*(C`SIGFPE\*(C'\fR). Use \fB\-mdivide\-traps\fR to +allow conditional traps on architectures that support them and +\&\fB\-mdivide\-breaks\fR to force the use of breaks. +.Sp +The default is usually \fB\-mdivide\-traps\fR, but this can be +overridden at configure time using \fB\-\-with\-divide=breaks\fR. +Divide-by-zero checks can be completely disabled using +\&\fB\-mno\-check\-zero\-division\fR. +.IP "\fB\-mmemcpy\fR" 4 +.IX Item "-mmemcpy" +.PD 0 +.IP "\fB\-mno\-memcpy\fR" 4 +.IX Item "-mno-memcpy" +.PD +Force (do not force) the use of \f(CW\*(C`memcpy()\*(C'\fR for non-trivial block +moves. The default is \fB\-mno\-memcpy\fR, which allows \s-1GCC\s0 to inline +most constant-sized copies. +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +.PD 0 +.IP "\fB\-mno\-long\-calls\fR" 4 +.IX Item "-mno-long-calls" +.PD +Disable (do not disable) use of the \f(CW\*(C`jal\*(C'\fR instruction. Calling +functions using \f(CW\*(C`jal\*(C'\fR is more efficient but requires the caller +and callee to be in the same 256 megabyte segment. +.Sp +This option has no effect on abicalls code. The default is +\&\fB\-mno\-long\-calls\fR. +.IP "\fB\-mmad\fR" 4 +.IX Item "-mmad" +.PD 0 +.IP "\fB\-mno\-mad\fR" 4 +.IX Item "-mno-mad" +.PD +Enable (disable) use of the \f(CW\*(C`mad\*(C'\fR, \f(CW\*(C`madu\*(C'\fR and \f(CW\*(C`mul\*(C'\fR +instructions, as provided by the R4650 \s-1ISA\s0. +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Enable (disable) use of the floating point multiply-accumulate +instructions, when they are available. The default is +\&\fB\-mfused\-madd\fR. +.Sp +When multiply-accumulate instructions are used, the intermediate +product is calculated to infinite precision and is not subject to +the \s-1FCSR\s0 Flush to Zero bit. This may be undesirable in some +circumstances. +.IP "\fB\-nocpp\fR" 4 +.IX Item "-nocpp" +Tell the \s-1MIPS\s0 assembler to not run its preprocessor over user +assembler files (with a \fB.s\fR suffix) when assembling them. +.IP "\fB\-mfix\-r4000\fR" 4 +.IX Item "-mfix-r4000" +.PD 0 +.IP "\fB\-mno\-fix\-r4000\fR" 4 +.IX Item "-mno-fix-r4000" +.PD +Work around certain R4000 \s-1CPU\s0 errata: +.RS 4 +.IP "\-" 4 +A double-word or a variable shift may give an incorrect result if executed +immediately after starting an integer division. +.IP "\-" 4 +A double-word or a variable shift may give an incorrect result if executed +while an integer multiplication is in progress. +.IP "\-" 4 +An integer division may give an incorrect result if started in a delay slot +of a taken branch or a jump. +.RE +.RS 4 +.RE +.IP "\fB\-mfix\-r4400\fR" 4 +.IX Item "-mfix-r4400" +.PD 0 +.IP "\fB\-mno\-fix\-r4400\fR" 4 +.IX Item "-mno-fix-r4400" +.PD +Work around certain R4400 \s-1CPU\s0 errata: +.RS 4 +.IP "\-" 4 +A double-word or a variable shift may give an incorrect result if executed +immediately after starting an integer division. +.RE +.RS 4 +.RE +.IP "\fB\-mfix\-r10000\fR" 4 +.IX Item "-mfix-r10000" +.PD 0 +.IP "\fB\-mno\-fix\-r10000\fR" 4 +.IX Item "-mno-fix-r10000" +.PD +Work around certain R10000 errata: +.RS 4 +.IP "\-" 4 +\&\f(CW\*(C`ll\*(C'\fR/\f(CW\*(C`sc\*(C'\fR sequences may not behave atomically on revisions +prior to 3.0. They may deadlock on revisions 2.6 and earlier. +.RE +.RS 4 +.Sp +This option can only be used if the target architecture supports +branch-likely instructions. \fB\-mfix\-r10000\fR is the default when +\&\fB\-march=r10000\fR is used; \fB\-mno\-fix\-r10000\fR is the default +otherwise. +.RE +.IP "\fB\-mfix\-vr4120\fR" 4 +.IX Item "-mfix-vr4120" +.PD 0 +.IP "\fB\-mno\-fix\-vr4120\fR" 4 +.IX Item "-mno-fix-vr4120" +.PD +Work around certain \s-1VR4120\s0 errata: +.RS 4 +.IP "\-" 4 +\&\f(CW\*(C`dmultu\*(C'\fR does not always produce the correct result. +.IP "\-" 4 +\&\f(CW\*(C`div\*(C'\fR and \f(CW\*(C`ddiv\*(C'\fR do not always produce the correct result if one +of the operands is negative. +.RE +.RS 4 +.Sp +The workarounds for the division errata rely on special functions in +\&\fIlibgcc.a\fR. At present, these functions are only provided by +the \f(CW\*(C`mips64vr*\-elf\*(C'\fR configurations. +.Sp +Other \s-1VR4120\s0 errata require a nop to be inserted between certain pairs of +instructions. These errata are handled by the assembler, not by \s-1GCC\s0 itself. +.RE +.IP "\fB\-mfix\-vr4130\fR" 4 +.IX Item "-mfix-vr4130" +Work around the \s-1VR4130\s0 \f(CW\*(C`mflo\*(C'\fR/\f(CW\*(C`mfhi\*(C'\fR errata. The +workarounds are implemented by the assembler rather than by \s-1GCC\s0, +although \s-1GCC\s0 will avoid using \f(CW\*(C`mflo\*(C'\fR and \f(CW\*(C`mfhi\*(C'\fR if the +\&\s-1VR4130\s0 \f(CW\*(C`macc\*(C'\fR, \f(CW\*(C`macchi\*(C'\fR, \f(CW\*(C`dmacc\*(C'\fR and \f(CW\*(C`dmacchi\*(C'\fR +instructions are available instead. +.IP "\fB\-mfix\-sb1\fR" 4 +.IX Item "-mfix-sb1" +.PD 0 +.IP "\fB\-mno\-fix\-sb1\fR" 4 +.IX Item "-mno-fix-sb1" +.PD +Work around certain \s-1SB\-1\s0 \s-1CPU\s0 core errata. +(This flag currently works around the \s-1SB\-1\s0 revision 2 +\&\*(L"F1\*(R" and \*(L"F2\*(R" floating point errata.) +.IP "\fB\-mr10k\-cache\-barrier=\fR\fIsetting\fR" 4 +.IX Item "-mr10k-cache-barrier=setting" +Specify whether \s-1GCC\s0 should insert cache barriers to avoid the +side-effects of speculation on R10K processors. +.Sp +In common with many processors, the R10K tries to predict the outcome +of a conditional branch and speculatively executes instructions from +the \*(L"taken\*(R" branch. It later aborts these instructions if the +predicted outcome was wrong. However, on the R10K, even aborted +instructions can have side effects. +.Sp +This problem only affects kernel stores and, depending on the system, +kernel loads. As an example, a speculatively-executed store may load +the target memory into cache and mark the cache line as dirty, even if +the store itself is later aborted. If a \s-1DMA\s0 operation writes to the +same area of memory before the \*(L"dirty\*(R" line is flushed, the cached +data will overwrite the DMA-ed data. See the R10K processor manual +for a full description, including other potential problems. +.Sp +One workaround is to insert cache barrier instructions before every memory +access that might be speculatively executed and that might have side +effects even if aborted. \fB\-mr10k\-cache\-barrier=\fR\fIsetting\fR +controls \s-1GCC\s0's implementation of this workaround. It assumes that +aborted accesses to any byte in the following regions will not have +side effects: +.RS 4 +.IP "1." 4 +the memory occupied by the current function's stack frame; +.IP "2." 4 +the memory occupied by an incoming stack argument; +.IP "3." 4 +the memory occupied by an object with a link-time-constant address. +.RE +.RS 4 +.Sp +It is the kernel's responsibility to ensure that speculative +accesses to these regions are indeed safe. +.Sp +If the input program contains a function declaration such as: +.Sp +.Vb 1 +\& void foo (void); +.Ve +.Sp +then the implementation of \f(CW\*(C`foo\*(C'\fR must allow \f(CW\*(C`j foo\*(C'\fR and +\&\f(CW\*(C`jal foo\*(C'\fR to be executed speculatively. \s-1GCC\s0 honors this +restriction for functions it compiles itself. It expects non-GCC +functions (such as hand-written assembly code) to do the same. +.Sp +The option has three forms: +.IP "\fB\-mr10k\-cache\-barrier=load\-store\fR" 4 +.IX Item "-mr10k-cache-barrier=load-store" +Insert a cache barrier before a load or store that might be +speculatively executed and that might have side effects even +if aborted. +.IP "\fB\-mr10k\-cache\-barrier=store\fR" 4 +.IX Item "-mr10k-cache-barrier=store" +Insert a cache barrier before a store that might be speculatively +executed and that might have side effects even if aborted. +.IP "\fB\-mr10k\-cache\-barrier=none\fR" 4 +.IX Item "-mr10k-cache-barrier=none" +Disable the insertion of cache barriers. This is the default setting. +.RE +.RS 4 +.RE +.IP "\fB\-mflush\-func=\fR\fIfunc\fR" 4 +.IX Item "-mflush-func=func" +.PD 0 +.IP "\fB\-mno\-flush\-func\fR" 4 +.IX Item "-mno-flush-func" +.PD +Specifies the function to call to flush the I and D caches, or to not +call any such function. If called, the function must take the same +arguments as the common \f(CW\*(C`_flush_func()\*(C'\fR, that is, the address of the +memory range for which the cache is being flushed, the size of the +memory range, and the number 3 (to flush both caches). The default +depends on the target \s-1GCC\s0 was configured for, but commonly is either +\&\fB_flush_func\fR or \fB_\|_cpu_flush\fR. +.IP "\fBmbranch\-cost=\fR\fInum\fR" 4 +.IX Item "mbranch-cost=num" +Set the cost of branches to roughly \fInum\fR \*(L"simple\*(R" instructions. +This cost is only a heuristic and is not guaranteed to produce +consistent results across releases. A zero cost redundantly selects +the default, which is based on the \fB\-mtune\fR setting. +.IP "\fB\-mbranch\-likely\fR" 4 +.IX Item "-mbranch-likely" +.PD 0 +.IP "\fB\-mno\-branch\-likely\fR" 4 +.IX Item "-mno-branch-likely" +.PD +Enable or disable use of Branch Likely instructions, regardless of the +default for the selected architecture. By default, Branch Likely +instructions may be generated if they are supported by the selected +architecture. An exception is for the \s-1MIPS32\s0 and \s-1MIPS64\s0 architectures +and processors which implement those architectures; for those, Branch +Likely instructions will not be generated by default because the \s-1MIPS32\s0 +and \s-1MIPS64\s0 architectures specifically deprecate their use. +.IP "\fB\-mfp\-exceptions\fR" 4 +.IX Item "-mfp-exceptions" +.PD 0 +.IP "\fB\-mno\-fp\-exceptions\fR" 4 +.IX Item "-mno-fp-exceptions" +.PD +Specifies whether \s-1FP\s0 exceptions are enabled. This affects how we schedule +\&\s-1FP\s0 instructions for some processors. The default is that \s-1FP\s0 exceptions are +enabled. +.Sp +For instance, on the \s-1SB\-1\s0, if \s-1FP\s0 exceptions are disabled, and we are emitting +64\-bit code, then we can use both \s-1FP\s0 pipes. Otherwise, we can only use one +\&\s-1FP\s0 pipe. +.IP "\fB\-mvr4130\-align\fR" 4 +.IX Item "-mvr4130-align" +.PD 0 +.IP "\fB\-mno\-vr4130\-align\fR" 4 +.IX Item "-mno-vr4130-align" +.PD +The \s-1VR4130\s0 pipeline is two-way superscalar, but can only issue two +instructions together if the first one is 8\-byte aligned. When this +option is enabled, \s-1GCC\s0 will align pairs of instructions that it +thinks should execute in parallel. +.Sp +This option only has an effect when optimizing for the \s-1VR4130\s0. +It normally makes code faster, but at the expense of making it bigger. +It is enabled by default at optimization level \fB\-O3\fR. +.IP "\fB\-msynci\fR" 4 +.IX Item "-msynci" +.PD 0 +.IP "\fB\-mno\-synci\fR" 4 +.IX Item "-mno-synci" +.PD +Enable (disable) generation of \f(CW\*(C`synci\*(C'\fR instructions on +architectures that support it. The \f(CW\*(C`synci\*(C'\fR instructions (if +enabled) will be generated when \f(CW\*(C`_\|_builtin_\|_\|_clear_cache()\*(C'\fR is +compiled. +.Sp +This option defaults to \f(CW\*(C`\-mno\-synci\*(C'\fR, but the default can be +overridden by configuring with \f(CW\*(C`\-\-with\-synci\*(C'\fR. +.Sp +When compiling code for single processor systems, it is generally safe +to use \f(CW\*(C`synci\*(C'\fR. However, on many multi-core (\s-1SMP\s0) systems, it +will not invalidate the instruction caches on all cores and may lead +to undefined behavior. +.IP "\fB\-mrelax\-pic\-calls\fR" 4 +.IX Item "-mrelax-pic-calls" +.PD 0 +.IP "\fB\-mno\-relax\-pic\-calls\fR" 4 +.IX Item "-mno-relax-pic-calls" +.PD +Try to turn \s-1PIC\s0 calls that are normally dispatched via register +\&\f(CW$25\fR into direct calls. This is only possible if the linker can +resolve the destination at link-time and if the destination is within +range for a direct call. +.Sp +\&\fB\-mrelax\-pic\-calls\fR is the default if \s-1GCC\s0 was configured to use +an assembler and a linker that supports the \f(CW\*(C`.reloc\*(C'\fR assembly +directive and \f(CW\*(C`\-mexplicit\-relocs\*(C'\fR is in effect. With +\&\f(CW\*(C`\-mno\-explicit\-relocs\*(C'\fR, this optimization can be performed by the +assembler and the linker alone without help from the compiler. +.IP "\fB\-mmcount\-ra\-address\fR" 4 +.IX Item "-mmcount-ra-address" +.PD 0 +.IP "\fB\-mno\-mcount\-ra\-address\fR" 4 +.IX Item "-mno-mcount-ra-address" +.PD +Emit (do not emit) code that allows \f(CW\*(C`_mcount\*(C'\fR to modify the +calling function's return address. When enabled, this option extends +the usual \f(CW\*(C`_mcount\*(C'\fR interface with a new \fIra-address\fR +parameter, which has type \f(CW\*(C`intptr_t *\*(C'\fR and is passed in register +\&\f(CW$12\fR. \f(CW\*(C`_mcount\*(C'\fR can then modify the return address by +doing both of the following: +.RS 4 +.IP "\(bu" 4 +Returning the new address in register \f(CW$31\fR. +.IP "\(bu" 4 +Storing the new address in \f(CW\*(C`*\f(CIra\-address\f(CW\*(C'\fR, +if \fIra-address\fR is nonnull. +.RE +.RS 4 +.Sp +The default is \fB\-mno\-mcount\-ra\-address\fR. +.RE +.PP +\fI\s-1MMIX\s0 Options\fR +.IX Subsection "MMIX Options" +.PP +These options are defined for the \s-1MMIX:\s0 +.IP "\fB\-mlibfuncs\fR" 4 +.IX Item "-mlibfuncs" +.PD 0 +.IP "\fB\-mno\-libfuncs\fR" 4 +.IX Item "-mno-libfuncs" +.PD +Specify that intrinsic library functions are being compiled, passing all +values in registers, no matter the size. +.IP "\fB\-mepsilon\fR" 4 +.IX Item "-mepsilon" +.PD 0 +.IP "\fB\-mno\-epsilon\fR" 4 +.IX Item "-mno-epsilon" +.PD +Generate floating-point comparison instructions that compare with respect +to the \f(CW\*(C`rE\*(C'\fR epsilon register. +.IP "\fB\-mabi=mmixware\fR" 4 +.IX Item "-mabi=mmixware" +.PD 0 +.IP "\fB\-mabi=gnu\fR" 4 +.IX Item "-mabi=gnu" +.PD +Generate code that passes function parameters and return values that (in +the called function) are seen as registers \f(CW$0\fR and up, as opposed to +the \s-1GNU\s0 \s-1ABI\s0 which uses global registers \f(CW$231\fR and up. +.IP "\fB\-mzero\-extend\fR" 4 +.IX Item "-mzero-extend" +.PD 0 +.IP "\fB\-mno\-zero\-extend\fR" 4 +.IX Item "-mno-zero-extend" +.PD +When reading data from memory in sizes shorter than 64 bits, use (do not +use) zero-extending load instructions by default, rather than +sign-extending ones. +.IP "\fB\-mknuthdiv\fR" 4 +.IX Item "-mknuthdiv" +.PD 0 +.IP "\fB\-mno\-knuthdiv\fR" 4 +.IX Item "-mno-knuthdiv" +.PD +Make the result of a division yielding a remainder have the same sign as +the divisor. With the default, \fB\-mno\-knuthdiv\fR, the sign of the +remainder follows the sign of the dividend. Both methods are +arithmetically valid, the latter being almost exclusively used. +.IP "\fB\-mtoplevel\-symbols\fR" 4 +.IX Item "-mtoplevel-symbols" +.PD 0 +.IP "\fB\-mno\-toplevel\-symbols\fR" 4 +.IX Item "-mno-toplevel-symbols" +.PD +Prepend (do not prepend) a \fB:\fR to all global symbols, so the assembly +code can be used with the \f(CW\*(C`PREFIX\*(C'\fR assembly directive. +.IP "\fB\-melf\fR" 4 +.IX Item "-melf" +Generate an executable in the \s-1ELF\s0 format, rather than the default +\&\fBmmo\fR format used by the \fBmmix\fR simulator. +.IP "\fB\-mbranch\-predict\fR" 4 +.IX Item "-mbranch-predict" +.PD 0 +.IP "\fB\-mno\-branch\-predict\fR" 4 +.IX Item "-mno-branch-predict" +.PD +Use (do not use) the probable-branch instructions, when static branch +prediction indicates a probable branch. +.IP "\fB\-mbase\-addresses\fR" 4 +.IX Item "-mbase-addresses" +.PD 0 +.IP "\fB\-mno\-base\-addresses\fR" 4 +.IX Item "-mno-base-addresses" +.PD +Generate (do not generate) code that uses \fIbase addresses\fR. Using a +base address automatically generates a request (handled by the assembler +and the linker) for a constant to be set up in a global register. The +register is used for one or more base address requests within the range 0 +to 255 from the value held in the register. The generally leads to short +and fast code, but the number of different data items that can be +addressed is limited. This means that a program that uses lots of static +data may require \fB\-mno\-base\-addresses\fR. +.IP "\fB\-msingle\-exit\fR" 4 +.IX Item "-msingle-exit" +.PD 0 +.IP "\fB\-mno\-single\-exit\fR" 4 +.IX Item "-mno-single-exit" +.PD +Force (do not force) generated code to have a single exit point in each +function. +.PP +\fI\s-1MN10300\s0 Options\fR +.IX Subsection "MN10300 Options" +.PP +These \fB\-m\fR options are defined for Matsushita \s-1MN10300\s0 architectures: +.IP "\fB\-mmult\-bug\fR" 4 +.IX Item "-mmult-bug" +Generate code to avoid bugs in the multiply instructions for the \s-1MN10300\s0 +processors. This is the default. +.IP "\fB\-mno\-mult\-bug\fR" 4 +.IX Item "-mno-mult-bug" +Do not generate code to avoid bugs in the multiply instructions for the +\&\s-1MN10300\s0 processors. +.IP "\fB\-mam33\fR" 4 +.IX Item "-mam33" +Generate code which uses features specific to the \s-1AM33\s0 processor. +.IP "\fB\-mno\-am33\fR" 4 +.IX Item "-mno-am33" +Do not generate code which uses features specific to the \s-1AM33\s0 processor. This +is the default. +.IP "\fB\-mam33\-2\fR" 4 +.IX Item "-mam33-2" +Generate code which uses features specific to the \s-1AM33/2\s0.0 processor. +.IP "\fB\-mam34\fR" 4 +.IX Item "-mam34" +Generate code which uses features specific to the \s-1AM34\s0 processor. +.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 +.IX Item "-mtune=cpu-type" +Use the timing characteristics of the indicated \s-1CPU\s0 type when +scheduling instructions. This does not change the targeted processor +type. The \s-1CPU\s0 type must be one of \fBmn10300\fR, \fBam33\fR, +\&\fBam33\-2\fR or \fBam34\fR. +.IP "\fB\-mreturn\-pointer\-on\-d0\fR" 4 +.IX Item "-mreturn-pointer-on-d0" +When generating a function which returns a pointer, return the pointer +in both \f(CW\*(C`a0\*(C'\fR and \f(CW\*(C`d0\*(C'\fR. Otherwise, the pointer is returned +only in a0, and attempts to call such functions without a prototype +would result in errors. Note that this option is on by default; use +\&\fB\-mno\-return\-pointer\-on\-d0\fR to disable it. +.IP "\fB\-mno\-crt0\fR" 4 +.IX Item "-mno-crt0" +Do not link in the C run-time initialization object file. +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +Indicate to the linker that it should perform a relaxation optimization pass +to shorten branches, calls and absolute memory addresses. This option only +has an effect when used on the command line for the final link step. +.Sp +This option makes symbolic debugging impossible. +.IP "\fB\-mliw\fR" 4 +.IX Item "-mliw" +Allow the compiler to generate \fILong Instruction Word\fR +instructions if the target is the \fB\s-1AM33\s0\fR or later. This is the +default. This option defines the preprocessor macro \fB_\|_LIW_\|_\fR. +.IP "\fB\-mnoliw\fR" 4 +.IX Item "-mnoliw" +Do not allow the compiler to generate \fILong Instruction Word\fR +instructions. This option defines the preprocessor macro +\&\fB_\|_NO_LIW_\|_\fR. +.PP +\fI\s-1PDP\-11\s0 Options\fR +.IX Subsection "PDP-11 Options" +.PP +These options are defined for the \s-1PDP\-11:\s0 +.IP "\fB\-mfpu\fR" 4 +.IX Item "-mfpu" +Use hardware \s-1FPP\s0 floating point. This is the default. (\s-1FIS\s0 floating +point on the \s-1PDP\-11/40\s0 is not supported.) +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Do not use hardware floating point. +.IP "\fB\-mac0\fR" 4 +.IX Item "-mac0" +Return floating-point results in ac0 (fr0 in Unix assembler syntax). +.IP "\fB\-mno\-ac0\fR" 4 +.IX Item "-mno-ac0" +Return floating-point results in memory. This is the default. +.IP "\fB\-m40\fR" 4 +.IX Item "-m40" +Generate code for a \s-1PDP\-11/40\s0. +.IP "\fB\-m45\fR" 4 +.IX Item "-m45" +Generate code for a \s-1PDP\-11/45\s0. This is the default. +.IP "\fB\-m10\fR" 4 +.IX Item "-m10" +Generate code for a \s-1PDP\-11/10\s0. +.IP "\fB\-mbcopy\-builtin\fR" 4 +.IX Item "-mbcopy-builtin" +Use inline \f(CW\*(C`movmemhi\*(C'\fR patterns for copying memory. This is the +default. +.IP "\fB\-mbcopy\fR" 4 +.IX Item "-mbcopy" +Do not use inline \f(CW\*(C`movmemhi\*(C'\fR patterns for copying memory. +.IP "\fB\-mint16\fR" 4 +.IX Item "-mint16" +.PD 0 +.IP "\fB\-mno\-int32\fR" 4 +.IX Item "-mno-int32" +.PD +Use 16\-bit \f(CW\*(C`int\*(C'\fR. This is the default. +.IP "\fB\-mint32\fR" 4 +.IX Item "-mint32" +.PD 0 +.IP "\fB\-mno\-int16\fR" 4 +.IX Item "-mno-int16" +.PD +Use 32\-bit \f(CW\*(C`int\*(C'\fR. +.IP "\fB\-mfloat64\fR" 4 +.IX Item "-mfloat64" +.PD 0 +.IP "\fB\-mno\-float32\fR" 4 +.IX Item "-mno-float32" +.PD +Use 64\-bit \f(CW\*(C`float\*(C'\fR. This is the default. +.IP "\fB\-mfloat32\fR" 4 +.IX Item "-mfloat32" +.PD 0 +.IP "\fB\-mno\-float64\fR" 4 +.IX Item "-mno-float64" +.PD +Use 32\-bit \f(CW\*(C`float\*(C'\fR. +.IP "\fB\-mabshi\fR" 4 +.IX Item "-mabshi" +Use \f(CW\*(C`abshi2\*(C'\fR pattern. This is the default. +.IP "\fB\-mno\-abshi\fR" 4 +.IX Item "-mno-abshi" +Do not use \f(CW\*(C`abshi2\*(C'\fR pattern. +.IP "\fB\-mbranch\-expensive\fR" 4 +.IX Item "-mbranch-expensive" +Pretend that branches are expensive. This is for experimenting with +code generation only. +.IP "\fB\-mbranch\-cheap\fR" 4 +.IX Item "-mbranch-cheap" +Do not pretend that branches are expensive. This is the default. +.IP "\fB\-munix\-asm\fR" 4 +.IX Item "-munix-asm" +Use Unix assembler syntax. This is the default when configured for +\&\fBpdp11\-*\-bsd\fR. +.IP "\fB\-mdec\-asm\fR" 4 +.IX Item "-mdec-asm" +Use \s-1DEC\s0 assembler syntax. This is the default when configured for any +\&\s-1PDP\-11\s0 target other than \fBpdp11\-*\-bsd\fR. +.PP +\fIpicoChip Options\fR +.IX Subsection "picoChip Options" +.PP +These \fB\-m\fR options are defined for picoChip implementations: +.IP "\fB\-mae=\fR\fIae_type\fR" 4 +.IX Item "-mae=ae_type" +Set the instruction set, register set, and instruction scheduling +parameters for array element type \fIae_type\fR. Supported values +for \fIae_type\fR are \fB\s-1ANY\s0\fR, \fB\s-1MUL\s0\fR, and \fB\s-1MAC\s0\fR. +.Sp +\&\fB\-mae=ANY\fR selects a completely generic \s-1AE\s0 type. Code +generated with this option will run on any of the other \s-1AE\s0 types. The +code will not be as efficient as it would be if compiled for a specific +\&\s-1AE\s0 type, and some types of operation (e.g., multiplication) will not +work properly on all types of \s-1AE\s0. +.Sp +\&\fB\-mae=MUL\fR selects a \s-1MUL\s0 \s-1AE\s0 type. This is the most useful \s-1AE\s0 type +for compiled code, and is the default. +.Sp +\&\fB\-mae=MAC\fR selects a DSP-style \s-1MAC\s0 \s-1AE\s0. Code compiled with this +option may suffer from poor performance of byte (char) manipulation, +since the \s-1DSP\s0 \s-1AE\s0 does not provide hardware support for byte load/stores. +.IP "\fB\-msymbol\-as\-address\fR" 4 +.IX Item "-msymbol-as-address" +Enable the compiler to directly use a symbol name as an address in a +load/store instruction, without first loading it into a +register. Typically, the use of this option will generate larger +programs, which run faster than when the option isn't used. However, the +results vary from program to program, so it is left as a user option, +rather than being permanently enabled. +.IP "\fB\-mno\-inefficient\-warnings\fR" 4 +.IX Item "-mno-inefficient-warnings" +Disables warnings about the generation of inefficient code. These +warnings can be generated, for example, when compiling code which +performs byte-level memory operations on the \s-1MAC\s0 \s-1AE\s0 type. The \s-1MAC\s0 \s-1AE\s0 has +no hardware support for byte-level memory operations, so all byte +load/stores must be synthesized from word load/store operations. This is +inefficient and a warning will be generated indicating to the programmer +that they should rewrite the code to avoid byte operations, or to target +an \s-1AE\s0 type which has the necessary hardware support. This option enables +the warning to be turned off. +.PP +\fIPowerPC Options\fR +.IX Subsection "PowerPC Options" +.PP +These are listed under +.PP +\fI\s-1IBM\s0 \s-1RS/6000\s0 and PowerPC Options\fR +.IX Subsection "IBM RS/6000 and PowerPC Options" +.PP +These \fB\-m\fR options are defined for the \s-1IBM\s0 \s-1RS/6000\s0 and PowerPC: +.IP "\fB\-mpower\fR" 4 +.IX Item "-mpower" +.PD 0 +.IP "\fB\-mno\-power\fR" 4 +.IX Item "-mno-power" +.IP "\fB\-mpower2\fR" 4 +.IX Item "-mpower2" +.IP "\fB\-mno\-power2\fR" 4 +.IX Item "-mno-power2" +.IP "\fB\-mpowerpc\fR" 4 +.IX Item "-mpowerpc" +.IP "\fB\-mno\-powerpc\fR" 4 +.IX Item "-mno-powerpc" +.IP "\fB\-mpowerpc\-gpopt\fR" 4 +.IX Item "-mpowerpc-gpopt" +.IP "\fB\-mno\-powerpc\-gpopt\fR" 4 +.IX Item "-mno-powerpc-gpopt" +.IP "\fB\-mpowerpc\-gfxopt\fR" 4 +.IX Item "-mpowerpc-gfxopt" +.IP "\fB\-mno\-powerpc\-gfxopt\fR" 4 +.IX Item "-mno-powerpc-gfxopt" +.IP "\fB\-mpowerpc64\fR" 4 +.IX Item "-mpowerpc64" +.IP "\fB\-mno\-powerpc64\fR" 4 +.IX Item "-mno-powerpc64" +.IP "\fB\-mmfcrf\fR" 4 +.IX Item "-mmfcrf" +.IP "\fB\-mno\-mfcrf\fR" 4 +.IX Item "-mno-mfcrf" +.IP "\fB\-mpopcntb\fR" 4 +.IX Item "-mpopcntb" +.IP "\fB\-mno\-popcntb\fR" 4 +.IX Item "-mno-popcntb" +.IP "\fB\-mpopcntd\fR" 4 +.IX Item "-mpopcntd" +.IP "\fB\-mno\-popcntd\fR" 4 +.IX Item "-mno-popcntd" +.IP "\fB\-mfprnd\fR" 4 +.IX Item "-mfprnd" +.IP "\fB\-mno\-fprnd\fR" 4 +.IX Item "-mno-fprnd" +.IP "\fB\-mcmpb\fR" 4 +.IX Item "-mcmpb" +.IP "\fB\-mno\-cmpb\fR" 4 +.IX Item "-mno-cmpb" +.IP "\fB\-mmfpgpr\fR" 4 +.IX Item "-mmfpgpr" +.IP "\fB\-mno\-mfpgpr\fR" 4 +.IX Item "-mno-mfpgpr" +.IP "\fB\-mhard\-dfp\fR" 4 +.IX Item "-mhard-dfp" +.IP "\fB\-mno\-hard\-dfp\fR" 4 +.IX Item "-mno-hard-dfp" +.PD +\&\s-1GCC\s0 supports two related instruction set architectures for the +\&\s-1RS/6000\s0 and PowerPC. The \fI\s-1POWER\s0\fR instruction set are those +instructions supported by the \fBrios\fR chip set used in the original +\&\s-1RS/6000\s0 systems and the \fIPowerPC\fR instruction set is the +architecture of the Freescale MPC5xx, MPC6xx, MPC8xx microprocessors, and +the \s-1IBM\s0 4xx, 6xx, and follow-on microprocessors. +.Sp +Neither architecture is a subset of the other. However there is a +large common subset of instructions supported by both. An \s-1MQ\s0 +register is included in processors supporting the \s-1POWER\s0 architecture. +.Sp +You use these options to specify which instructions are available on the +processor you are using. The default value of these options is +determined when configuring \s-1GCC\s0. Specifying the +\&\fB\-mcpu=\fR\fIcpu_type\fR overrides the specification of these +options. We recommend you use the \fB\-mcpu=\fR\fIcpu_type\fR option +rather than the options listed above. +.Sp +The \fB\-mpower\fR option allows \s-1GCC\s0 to generate instructions that +are found only in the \s-1POWER\s0 architecture and to use the \s-1MQ\s0 register. +Specifying \fB\-mpower2\fR implies \fB\-power\fR and also allows \s-1GCC\s0 +to generate instructions that are present in the \s-1POWER2\s0 architecture but +not the original \s-1POWER\s0 architecture. +.Sp +The \fB\-mpowerpc\fR option allows \s-1GCC\s0 to generate instructions that +are found only in the 32\-bit subset of the PowerPC architecture. +Specifying \fB\-mpowerpc\-gpopt\fR implies \fB\-mpowerpc\fR and also allows +\&\s-1GCC\s0 to use the optional PowerPC architecture instructions in the +General Purpose group, including floating-point square root. Specifying +\&\fB\-mpowerpc\-gfxopt\fR implies \fB\-mpowerpc\fR and also allows \s-1GCC\s0 to +use the optional PowerPC architecture instructions in the Graphics +group, including floating-point select. +.Sp +The \fB\-mmfcrf\fR option allows \s-1GCC\s0 to generate the move from +condition register field instruction implemented on the \s-1POWER4\s0 +processor and other processors that support the PowerPC V2.01 +architecture. +The \fB\-mpopcntb\fR option allows \s-1GCC\s0 to generate the popcount and +double precision \s-1FP\s0 reciprocal estimate instruction implemented on the +\&\s-1POWER5\s0 processor and other processors that support the PowerPC V2.02 +architecture. +The \fB\-mpopcntd\fR option allows \s-1GCC\s0 to generate the popcount +instruction implemented on the \s-1POWER7\s0 processor and other processors +that support the PowerPC V2.06 architecture. +The \fB\-mfprnd\fR option allows \s-1GCC\s0 to generate the \s-1FP\s0 round to +integer instructions implemented on the \s-1POWER5+\s0 processor and other +processors that support the PowerPC V2.03 architecture. +The \fB\-mcmpb\fR option allows \s-1GCC\s0 to generate the compare bytes +instruction implemented on the \s-1POWER6\s0 processor and other processors +that support the PowerPC V2.05 architecture. +The \fB\-mmfpgpr\fR option allows \s-1GCC\s0 to generate the \s-1FP\s0 move to/from +general purpose register instructions implemented on the \s-1POWER6X\s0 +processor and other processors that support the extended PowerPC V2.05 +architecture. +The \fB\-mhard\-dfp\fR option allows \s-1GCC\s0 to generate the decimal floating +point instructions implemented on some \s-1POWER\s0 processors. +.Sp +The \fB\-mpowerpc64\fR option allows \s-1GCC\s0 to generate the additional +64\-bit instructions that are found in the full PowerPC64 architecture +and to treat GPRs as 64\-bit, doubleword quantities. \s-1GCC\s0 defaults to +\&\fB\-mno\-powerpc64\fR. +.Sp +If you specify both \fB\-mno\-power\fR and \fB\-mno\-powerpc\fR, \s-1GCC\s0 +will use only the instructions in the common subset of both +architectures plus some special \s-1AIX\s0 common-mode calls, and will not use +the \s-1MQ\s0 register. Specifying both \fB\-mpower\fR and \fB\-mpowerpc\fR +permits \s-1GCC\s0 to use any instruction from either architecture and to +allow use of the \s-1MQ\s0 register; specify this for the Motorola \s-1MPC601\s0. +.IP "\fB\-mnew\-mnemonics\fR" 4 +.IX Item "-mnew-mnemonics" +.PD 0 +.IP "\fB\-mold\-mnemonics\fR" 4 +.IX Item "-mold-mnemonics" +.PD +Select which mnemonics to use in the generated assembler code. With +\&\fB\-mnew\-mnemonics\fR, \s-1GCC\s0 uses the assembler mnemonics defined for +the PowerPC architecture. With \fB\-mold\-mnemonics\fR it uses the +assembler mnemonics defined for the \s-1POWER\s0 architecture. Instructions +defined in only one architecture have only one mnemonic; \s-1GCC\s0 uses that +mnemonic irrespective of which of these options is specified. +.Sp +\&\s-1GCC\s0 defaults to the mnemonics appropriate for the architecture in +use. Specifying \fB\-mcpu=\fR\fIcpu_type\fR sometimes overrides the +value of these option. Unless you are building a cross-compiler, you +should normally not specify either \fB\-mnew\-mnemonics\fR or +\&\fB\-mold\-mnemonics\fR, but should instead accept the default. +.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 +.IX Item "-mcpu=cpu_type" +Set architecture type, register usage, choice of mnemonics, and +instruction scheduling parameters for machine type \fIcpu_type\fR. +Supported values for \fIcpu_type\fR are \fB401\fR, \fB403\fR, +\&\fB405\fR, \fB405fp\fR, \fB440\fR, \fB440fp\fR, \fB464\fR, \fB464fp\fR, +\&\fB476\fR, \fB476fp\fR, \fB505\fR, \fB601\fR, \fB602\fR, \fB603\fR, +\&\fB603e\fR, \fB604\fR, \fB604e\fR, \fB620\fR, \fB630\fR, \fB740\fR, +\&\fB7400\fR, \fB7450\fR, \fB750\fR, \fB801\fR, \fB821\fR, \fB823\fR, +\&\fB860\fR, \fB970\fR, \fB8540\fR, \fBa2\fR, \fBe300c2\fR, +\&\fBe300c3\fR, \fBe500mc\fR, \fBe500mc64\fR, \fBec603e\fR, \fBG3\fR, +\&\fBG4\fR, \fBG5\fR, \fBtitan\fR, \fBpower\fR, \fBpower2\fR, \fBpower3\fR, +\&\fBpower4\fR, \fBpower5\fR, \fBpower5+\fR, \fBpower6\fR, \fBpower6x\fR, +\&\fBpower7\fR, \fBcommon\fR, \fBpowerpc\fR, \fBpowerpc64\fR, \fBrios\fR, +\&\fBrios1\fR, \fBrios2\fR, \fBrsc\fR, and \fBrs64\fR. +.Sp +\&\fB\-mcpu=common\fR selects a completely generic processor. Code +generated under this option will run on any \s-1POWER\s0 or PowerPC processor. +\&\s-1GCC\s0 will use only the instructions in the common subset of both +architectures, and will not use the \s-1MQ\s0 register. \s-1GCC\s0 assumes a generic +processor model for scheduling purposes. +.Sp +\&\fB\-mcpu=power\fR, \fB\-mcpu=power2\fR, \fB\-mcpu=powerpc\fR, and +\&\fB\-mcpu=powerpc64\fR specify generic \s-1POWER\s0, \s-1POWER2\s0, pure 32\-bit +PowerPC (i.e., not \s-1MPC601\s0), and 64\-bit PowerPC architecture machine +types, with an appropriate, generic processor model assumed for +scheduling purposes. +.Sp +The other options specify a specific processor. Code generated under +those options will run best on that processor, and may not run at all on +others. +.Sp +The \fB\-mcpu\fR options automatically enable or disable the +following options: +.Sp +\&\fB\-maltivec \-mfprnd \-mhard\-float \-mmfcrf \-mmultiple +\&\-mnew\-mnemonics \-mpopcntb \-mpopcntd \-mpower \-mpower2 \-mpowerpc64 +\&\-mpowerpc\-gpopt \-mpowerpc\-gfxopt \-msingle\-float \-mdouble\-float +\&\-msimple\-fpu \-mstring \-mmulhw \-mdlmzb \-mmfpgpr \-mvsx\fR +.Sp +The particular options set for any particular \s-1CPU\s0 will vary between +compiler versions, depending on what setting seems to produce optimal +code for that \s-1CPU\s0; it doesn't necessarily reflect the actual hardware's +capabilities. If you wish to set an individual option to a particular +value, you may specify it after the \fB\-mcpu\fR option, like +\&\fB\-mcpu=970 \-mno\-altivec\fR. +.Sp +On \s-1AIX\s0, the \fB\-maltivec\fR and \fB\-mpowerpc64\fR options are +not enabled or disabled by the \fB\-mcpu\fR option at present because +\&\s-1AIX\s0 does not have full support for these options. You may still +enable or disable them individually if you're sure it'll work in your +environment. +.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4 +.IX Item "-mtune=cpu_type" +Set the instruction scheduling parameters for machine type +\&\fIcpu_type\fR, but do not set the architecture type, register usage, or +choice of mnemonics, as \fB\-mcpu=\fR\fIcpu_type\fR would. The same +values for \fIcpu_type\fR are used for \fB\-mtune\fR as for +\&\fB\-mcpu\fR. If both are specified, the code generated will use the +architecture, registers, and mnemonics set by \fB\-mcpu\fR, but the +scheduling parameters set by \fB\-mtune\fR. +.IP "\fB\-mcmodel=small\fR" 4 +.IX Item "-mcmodel=small" +Generate PowerPC64 code for the small model: The \s-1TOC\s0 is limited to +64k. +.IP "\fB\-mcmodel=medium\fR" 4 +.IX Item "-mcmodel=medium" +Generate PowerPC64 code for the medium model: The \s-1TOC\s0 and other static +data may be up to a total of 4G in size. +.IP "\fB\-mcmodel=large\fR" 4 +.IX Item "-mcmodel=large" +Generate PowerPC64 code for the large model: The \s-1TOC\s0 may be up to 4G +in size. Other data and code is only limited by the 64\-bit address +space. +.IP "\fB\-maltivec\fR" 4 +.IX Item "-maltivec" +.PD 0 +.IP "\fB\-mno\-altivec\fR" 4 +.IX Item "-mno-altivec" +.PD +Generate code that uses (does not use) AltiVec instructions, and also +enable the use of built-in functions that allow more direct access to +the AltiVec instruction set. You may also need to set +\&\fB\-mabi=altivec\fR to adjust the current \s-1ABI\s0 with AltiVec \s-1ABI\s0 +enhancements. +.IP "\fB\-mvrsave\fR" 4 +.IX Item "-mvrsave" +.PD 0 +.IP "\fB\-mno\-vrsave\fR" 4 +.IX Item "-mno-vrsave" +.PD +Generate \s-1VRSAVE\s0 instructions when generating AltiVec code. +.IP "\fB\-mgen\-cell\-microcode\fR" 4 +.IX Item "-mgen-cell-microcode" +Generate Cell microcode instructions +.IP "\fB\-mwarn\-cell\-microcode\fR" 4 +.IX Item "-mwarn-cell-microcode" +Warning when a Cell microcode instruction is going to emitted. An example +of a Cell microcode instruction is a variable shift. +.IP "\fB\-msecure\-plt\fR" 4 +.IX Item "-msecure-plt" +Generate code that allows ld and ld.so to build executables and shared +libraries with non-exec .plt and .got sections. This is a PowerPC +32\-bit \s-1SYSV\s0 \s-1ABI\s0 option. +.IP "\fB\-mbss\-plt\fR" 4 +.IX Item "-mbss-plt" +Generate code that uses a \s-1BSS\s0 .plt section that ld.so fills in, and +requires .plt and .got sections that are both writable and executable. +This is a PowerPC 32\-bit \s-1SYSV\s0 \s-1ABI\s0 option. +.IP "\fB\-misel\fR" 4 +.IX Item "-misel" +.PD 0 +.IP "\fB\-mno\-isel\fR" 4 +.IX Item "-mno-isel" +.PD +This switch enables or disables the generation of \s-1ISEL\s0 instructions. +.IP "\fB\-misel=\fR\fIyes/no\fR" 4 +.IX Item "-misel=yes/no" +This switch has been deprecated. Use \fB\-misel\fR and +\&\fB\-mno\-isel\fR instead. +.IP "\fB\-mspe\fR" 4 +.IX Item "-mspe" +.PD 0 +.IP "\fB\-mno\-spe\fR" 4 +.IX Item "-mno-spe" +.PD +This switch enables or disables the generation of \s-1SPE\s0 simd +instructions. +.IP "\fB\-mpaired\fR" 4 +.IX Item "-mpaired" +.PD 0 +.IP "\fB\-mno\-paired\fR" 4 +.IX Item "-mno-paired" +.PD +This switch enables or disables the generation of \s-1PAIRED\s0 simd +instructions. +.IP "\fB\-mspe=\fR\fIyes/no\fR" 4 +.IX Item "-mspe=yes/no" +This option has been deprecated. Use \fB\-mspe\fR and +\&\fB\-mno\-spe\fR instead. +.IP "\fB\-mvsx\fR" 4 +.IX Item "-mvsx" +.PD 0 +.IP "\fB\-mno\-vsx\fR" 4 +.IX Item "-mno-vsx" +.PD +Generate code that uses (does not use) vector/scalar (\s-1VSX\s0) +instructions, and also enable the use of built-in functions that allow +more direct access to the \s-1VSX\s0 instruction set. +.IP "\fB\-mfloat\-gprs=\fR\fIyes/single/double/no\fR" 4 +.IX Item "-mfloat-gprs=yes/single/double/no" +.PD 0 +.IP "\fB\-mfloat\-gprs\fR" 4 +.IX Item "-mfloat-gprs" +.PD +This switch enables or disables the generation of floating point +operations on the general purpose registers for architectures that +support it. +.Sp +The argument \fIyes\fR or \fIsingle\fR enables the use of +single-precision floating point operations. +.Sp +The argument \fIdouble\fR enables the use of single and +double-precision floating point operations. +.Sp +The argument \fIno\fR disables floating point operations on the +general purpose registers. +.Sp +This option is currently only available on the MPC854x. +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" +.PD 0 +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.PD +Generate code for 32\-bit or 64\-bit environments of Darwin and \s-1SVR4\s0 +targets (including GNU/Linux). The 32\-bit environment sets int, long +and pointer to 32 bits and generates code that runs on any PowerPC +variant. The 64\-bit environment sets int to 32 bits and long and +pointer to 64 bits, and generates code for PowerPC64, as for +\&\fB\-mpowerpc64\fR. +.IP "\fB\-mfull\-toc\fR" 4 +.IX Item "-mfull-toc" +.PD 0 +.IP "\fB\-mno\-fp\-in\-toc\fR" 4 +.IX Item "-mno-fp-in-toc" +.IP "\fB\-mno\-sum\-in\-toc\fR" 4 +.IX Item "-mno-sum-in-toc" +.IP "\fB\-mminimal\-toc\fR" 4 +.IX Item "-mminimal-toc" +.PD +Modify generation of the \s-1TOC\s0 (Table Of Contents), which is created for +every executable file. The \fB\-mfull\-toc\fR option is selected by +default. In that case, \s-1GCC\s0 will allocate at least one \s-1TOC\s0 entry for +each unique non-automatic variable reference in your program. \s-1GCC\s0 +will also place floating-point constants in the \s-1TOC\s0. However, only +16,384 entries are available in the \s-1TOC\s0. +.Sp +If you receive a linker error message that saying you have overflowed +the available \s-1TOC\s0 space, you can reduce the amount of \s-1TOC\s0 space used +with the \fB\-mno\-fp\-in\-toc\fR and \fB\-mno\-sum\-in\-toc\fR options. +\&\fB\-mno\-fp\-in\-toc\fR prevents \s-1GCC\s0 from putting floating-point +constants in the \s-1TOC\s0 and \fB\-mno\-sum\-in\-toc\fR forces \s-1GCC\s0 to +generate code to calculate the sum of an address and a constant at +run-time instead of putting that sum into the \s-1TOC\s0. You may specify one +or both of these options. Each causes \s-1GCC\s0 to produce very slightly +slower and larger code at the expense of conserving \s-1TOC\s0 space. +.Sp +If you still run out of space in the \s-1TOC\s0 even when you specify both of +these options, specify \fB\-mminimal\-toc\fR instead. This option causes +\&\s-1GCC\s0 to make only one \s-1TOC\s0 entry for every file. When you specify this +option, \s-1GCC\s0 will produce code that is slower and larger but which +uses extremely little \s-1TOC\s0 space. You may wish to use this option +only on files that contain less frequently executed code. +.IP "\fB\-maix64\fR" 4 +.IX Item "-maix64" +.PD 0 +.IP "\fB\-maix32\fR" 4 +.IX Item "-maix32" +.PD +Enable 64\-bit \s-1AIX\s0 \s-1ABI\s0 and calling convention: 64\-bit pointers, 64\-bit +\&\f(CW\*(C`long\*(C'\fR type, and the infrastructure needed to support them. +Specifying \fB\-maix64\fR implies \fB\-mpowerpc64\fR and +\&\fB\-mpowerpc\fR, while \fB\-maix32\fR disables the 64\-bit \s-1ABI\s0 and +implies \fB\-mno\-powerpc64\fR. \s-1GCC\s0 defaults to \fB\-maix32\fR. +.IP "\fB\-mxl\-compat\fR" 4 +.IX Item "-mxl-compat" +.PD 0 +.IP "\fB\-mno\-xl\-compat\fR" 4 +.IX Item "-mno-xl-compat" +.PD +Produce code that conforms more closely to \s-1IBM\s0 \s-1XL\s0 compiler semantics +when using AIX-compatible \s-1ABI\s0. Pass floating-point arguments to +prototyped functions beyond the register save area (\s-1RSA\s0) on the stack +in addition to argument FPRs. Do not assume that most significant +double in 128\-bit long double value is properly rounded when comparing +values and converting to double. Use \s-1XL\s0 symbol names for long double +support routines. +.Sp +The \s-1AIX\s0 calling convention was extended but not initially documented to +handle an obscure K&R C case of calling a function that takes the +address of its arguments with fewer arguments than declared. \s-1IBM\s0 \s-1XL\s0 +compilers access floating point arguments which do not fit in the +\&\s-1RSA\s0 from the stack when a subroutine is compiled without +optimization. Because always storing floating-point arguments on the +stack is inefficient and rarely needed, this option is not enabled by +default and only is necessary when calling subroutines compiled by \s-1IBM\s0 +\&\s-1XL\s0 compilers without optimization. +.IP "\fB\-mpe\fR" 4 +.IX Item "-mpe" +Support \fI\s-1IBM\s0 \s-1RS/6000\s0 \s-1SP\s0\fR \fIParallel Environment\fR (\s-1PE\s0). Link an +application written to use message passing with special startup code to +enable the application to run. The system must have \s-1PE\s0 installed in the +standard location (\fI/usr/lpp/ppe.poe/\fR), or the \fIspecs\fR file +must be overridden with the \fB\-specs=\fR option to specify the +appropriate directory location. The Parallel Environment does not +support threads, so the \fB\-mpe\fR option and the \fB\-pthread\fR +option are incompatible. +.IP "\fB\-malign\-natural\fR" 4 +.IX Item "-malign-natural" +.PD 0 +.IP "\fB\-malign\-power\fR" 4 +.IX Item "-malign-power" +.PD +On \s-1AIX\s0, 32\-bit Darwin, and 64\-bit PowerPC GNU/Linux, the option +\&\fB\-malign\-natural\fR overrides the ABI-defined alignment of larger +types, such as floating-point doubles, on their natural size-based boundary. +The option \fB\-malign\-power\fR instructs \s-1GCC\s0 to follow the ABI-specified +alignment rules. \s-1GCC\s0 defaults to the standard alignment defined in the \s-1ABI\s0. +.Sp +On 64\-bit Darwin, natural alignment is the default, and \fB\-malign\-power\fR +is not supported. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD 0 +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD +Generate code that does not use (uses) the floating-point register set. +Software floating point emulation is provided if you use the +\&\fB\-msoft\-float\fR option, and pass the option to \s-1GCC\s0 when linking. +.IP "\fB\-msingle\-float\fR" 4 +.IX Item "-msingle-float" +.PD 0 +.IP "\fB\-mdouble\-float\fR" 4 +.IX Item "-mdouble-float" +.PD +Generate code for single or double-precision floating point operations. +\&\fB\-mdouble\-float\fR implies \fB\-msingle\-float\fR. +.IP "\fB\-msimple\-fpu\fR" 4 +.IX Item "-msimple-fpu" +Do not generate sqrt and div instructions for hardware floating point unit. +.IP "\fB\-mfpu\fR" 4 +.IX Item "-mfpu" +Specify type of floating point unit. Valid values are \fIsp_lite\fR +(equivalent to \-msingle\-float \-msimple\-fpu), \fIdp_lite\fR (equivalent +to \-mdouble\-float \-msimple\-fpu), \fIsp_full\fR (equivalent to \-msingle\-float), +and \fIdp_full\fR (equivalent to \-mdouble\-float). +.IP "\fB\-mxilinx\-fpu\fR" 4 +.IX Item "-mxilinx-fpu" +Perform optimizations for floating point unit on Xilinx \s-1PPC\s0 405/440. +.IP "\fB\-mmultiple\fR" 4 +.IX Item "-mmultiple" +.PD 0 +.IP "\fB\-mno\-multiple\fR" 4 +.IX Item "-mno-multiple" +.PD +Generate code that uses (does not use) the load multiple word +instructions and the store multiple word instructions. These +instructions are generated by default on \s-1POWER\s0 systems, and not +generated on PowerPC systems. Do not use \fB\-mmultiple\fR on little +endian PowerPC systems, since those instructions do not work when the +processor is in little endian mode. The exceptions are \s-1PPC740\s0 and +\&\s-1PPC750\s0 which permit the instructions usage in little endian mode. +.IP "\fB\-mstring\fR" 4 +.IX Item "-mstring" +.PD 0 +.IP "\fB\-mno\-string\fR" 4 +.IX Item "-mno-string" +.PD +Generate code that uses (does not use) the load string instructions +and the store string word instructions to save multiple registers and +do small block moves. These instructions are generated by default on +\&\s-1POWER\s0 systems, and not generated on PowerPC systems. Do not use +\&\fB\-mstring\fR on little endian PowerPC systems, since those +instructions do not work when the processor is in little endian mode. +The exceptions are \s-1PPC740\s0 and \s-1PPC750\s0 which permit the instructions +usage in little endian mode. +.IP "\fB\-mupdate\fR" 4 +.IX Item "-mupdate" +.PD 0 +.IP "\fB\-mno\-update\fR" 4 +.IX Item "-mno-update" +.PD +Generate code that uses (does not use) the load or store instructions +that update the base register to the address of the calculated memory +location. These instructions are generated by default. If you use +\&\fB\-mno\-update\fR, there is a small window between the time that the +stack pointer is updated and the address of the previous frame is +stored, which means code that walks the stack frame across interrupts or +signals may get corrupted data. +.IP "\fB\-mavoid\-indexed\-addresses\fR" 4 +.IX Item "-mavoid-indexed-addresses" +.PD 0 +.IP "\fB\-mno\-avoid\-indexed\-addresses\fR" 4 +.IX Item "-mno-avoid-indexed-addresses" +.PD +Generate code that tries to avoid (not avoid) the use of indexed load +or store instructions. These instructions can incur a performance +penalty on Power6 processors in certain situations, such as when +stepping through large arrays that cross a 16M boundary. This option +is enabled by default when targetting Power6 and disabled otherwise. +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Generate code that uses (does not use) the floating point multiply and +accumulate instructions. These instructions are generated by default +if hardware floating point is used. The machine dependent +\&\fB\-mfused\-madd\fR option is now mapped to the machine independent +\&\fB\-ffp\-contract=fast\fR option, and \fB\-mno\-fused\-madd\fR is +mapped to \fB\-ffp\-contract=off\fR. +.IP "\fB\-mmulhw\fR" 4 +.IX Item "-mmulhw" +.PD 0 +.IP "\fB\-mno\-mulhw\fR" 4 +.IX Item "-mno-mulhw" +.PD +Generate code that uses (does not use) the half-word multiply and +multiply-accumulate instructions on the \s-1IBM\s0 405, 440, 464 and 476 processors. +These instructions are generated by default when targetting those +processors. +.IP "\fB\-mdlmzb\fR" 4 +.IX Item "-mdlmzb" +.PD 0 +.IP "\fB\-mno\-dlmzb\fR" 4 +.IX Item "-mno-dlmzb" +.PD +Generate code that uses (does not use) the string-search \fBdlmzb\fR +instruction on the \s-1IBM\s0 405, 440, 464 and 476 processors. This instruction is +generated by default when targetting those processors. +.IP "\fB\-mno\-bit\-align\fR" 4 +.IX Item "-mno-bit-align" +.PD 0 +.IP "\fB\-mbit\-align\fR" 4 +.IX Item "-mbit-align" +.PD +On System V.4 and embedded PowerPC systems do not (do) force structures +and unions that contain bit-fields to be aligned to the base type of the +bit-field. +.Sp +For example, by default a structure containing nothing but 8 +\&\f(CW\*(C`unsigned\*(C'\fR bit-fields of length 1 would be aligned to a 4 byte +boundary and have a size of 4 bytes. By using \fB\-mno\-bit\-align\fR, +the structure would be aligned to a 1 byte boundary and be one byte in +size. +.IP "\fB\-mno\-strict\-align\fR" 4 +.IX Item "-mno-strict-align" +.PD 0 +.IP "\fB\-mstrict\-align\fR" 4 +.IX Item "-mstrict-align" +.PD +On System V.4 and embedded PowerPC systems do not (do) assume that +unaligned memory references will be handled by the system. +.IP "\fB\-mrelocatable\fR" 4 +.IX Item "-mrelocatable" +.PD 0 +.IP "\fB\-mno\-relocatable\fR" 4 +.IX Item "-mno-relocatable" +.PD +Generate code that allows (does not allow) a static executable to be +relocated to a different address at runtime. A simple embedded +PowerPC system loader should relocate the entire contents of +\&\f(CW\*(C`.got2\*(C'\fR and 4\-byte locations listed in the \f(CW\*(C`.fixup\*(C'\fR section, +a table of 32\-bit addresses generated by this option. For this to +work, all objects linked together must be compiled with +\&\fB\-mrelocatable\fR or \fB\-mrelocatable\-lib\fR. +\&\fB\-mrelocatable\fR code aligns the stack to an 8 byte boundary. +.IP "\fB\-mrelocatable\-lib\fR" 4 +.IX Item "-mrelocatable-lib" +.PD 0 +.IP "\fB\-mno\-relocatable\-lib\fR" 4 +.IX Item "-mno-relocatable-lib" +.PD +Like \fB\-mrelocatable\fR, \fB\-mrelocatable\-lib\fR generates a +\&\f(CW\*(C`.fixup\*(C'\fR section to allow static executables to be relocated at +runtime, but \fB\-mrelocatable\-lib\fR does not use the smaller stack +alignment of \fB\-mrelocatable\fR. Objects compiled with +\&\fB\-mrelocatable\-lib\fR may be linked with objects compiled with +any combination of the \fB\-mrelocatable\fR options. +.IP "\fB\-mno\-toc\fR" 4 +.IX Item "-mno-toc" +.PD 0 +.IP "\fB\-mtoc\fR" 4 +.IX Item "-mtoc" +.PD +On System V.4 and embedded PowerPC systems do not (do) assume that +register 2 contains a pointer to a global area pointing to the addresses +used in the program. +.IP "\fB\-mlittle\fR" 4 +.IX Item "-mlittle" +.PD 0 +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +.PD +On System V.4 and embedded PowerPC systems compile code for the +processor in little endian mode. The \fB\-mlittle\-endian\fR option is +the same as \fB\-mlittle\fR. +.IP "\fB\-mbig\fR" 4 +.IX Item "-mbig" +.PD 0 +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +.PD +On System V.4 and embedded PowerPC systems compile code for the +processor in big endian mode. The \fB\-mbig\-endian\fR option is +the same as \fB\-mbig\fR. +.IP "\fB\-mdynamic\-no\-pic\fR" 4 +.IX Item "-mdynamic-no-pic" +On Darwin and Mac \s-1OS\s0 X systems, compile code so that it is not +relocatable, but that its external references are relocatable. The +resulting code is suitable for applications, but not shared +libraries. +.IP "\fB\-msingle\-pic\-base\fR" 4 +.IX Item "-msingle-pic-base" +Treat the register used for \s-1PIC\s0 addressing as read-only, rather than +loading it in the prologue for each function. The run-time system is +responsible for initializing this register with an appropriate value +before execution begins. +.IP "\fB\-mprioritize\-restricted\-insns=\fR\fIpriority\fR" 4 +.IX Item "-mprioritize-restricted-insns=priority" +This option controls the priority that is assigned to +dispatch-slot restricted instructions during the second scheduling +pass. The argument \fIpriority\fR takes the value \fI0/1/2\fR to assign +\&\fIno/highest/second\-highest\fR priority to dispatch slot restricted +instructions. +.IP "\fB\-msched\-costly\-dep=\fR\fIdependence_type\fR" 4 +.IX Item "-msched-costly-dep=dependence_type" +This option controls which dependences are considered costly +by the target during instruction scheduling. The argument +\&\fIdependence_type\fR takes one of the following values: +\&\fIno\fR: no dependence is costly, +\&\fIall\fR: all dependences are costly, +\&\fItrue_store_to_load\fR: a true dependence from store to load is costly, +\&\fIstore_to_load\fR: any dependence from store to load is costly, +\&\fInumber\fR: any dependence which latency >= \fInumber\fR is costly. +.IP "\fB\-minsert\-sched\-nops=\fR\fIscheme\fR" 4 +.IX Item "-minsert-sched-nops=scheme" +This option controls which nop insertion scheme will be used during +the second scheduling pass. The argument \fIscheme\fR takes one of the +following values: +\&\fIno\fR: Don't insert nops. +\&\fIpad\fR: Pad with nops any dispatch group which has vacant issue slots, +according to the scheduler's grouping. +\&\fIregroup_exact\fR: Insert nops to force costly dependent insns into +separate groups. Insert exactly as many nops as needed to force an insn +to a new group, according to the estimated processor grouping. +\&\fInumber\fR: Insert nops to force costly dependent insns into +separate groups. Insert \fInumber\fR nops to force an insn to a new group. +.IP "\fB\-mcall\-sysv\fR" 4 +.IX Item "-mcall-sysv" +On System V.4 and embedded PowerPC systems compile code using calling +conventions that adheres to the March 1995 draft of the System V +Application Binary Interface, PowerPC processor supplement. This is the +default unless you configured \s-1GCC\s0 using \fBpowerpc\-*\-eabiaix\fR. +.IP "\fB\-mcall\-sysv\-eabi\fR" 4 +.IX Item "-mcall-sysv-eabi" +.PD 0 +.IP "\fB\-mcall\-eabi\fR" 4 +.IX Item "-mcall-eabi" +.PD +Specify both \fB\-mcall\-sysv\fR and \fB\-meabi\fR options. +.IP "\fB\-mcall\-sysv\-noeabi\fR" 4 +.IX Item "-mcall-sysv-noeabi" +Specify both \fB\-mcall\-sysv\fR and \fB\-mno\-eabi\fR options. +.IP "\fB\-mcall\-aixdesc\fR" 4 +.IX Item "-mcall-aixdesc" +On System V.4 and embedded PowerPC systems compile code for the \s-1AIX\s0 +operating system. +.IP "\fB\-mcall\-linux\fR" 4 +.IX Item "-mcall-linux" +On System V.4 and embedded PowerPC systems compile code for the +Linux-based \s-1GNU\s0 system. +.IP "\fB\-mcall\-gnu\fR" 4 +.IX Item "-mcall-gnu" +On System V.4 and embedded PowerPC systems compile code for the +Hurd-based \s-1GNU\s0 system. +.IP "\fB\-mcall\-freebsd\fR" 4 +.IX Item "-mcall-freebsd" +On System V.4 and embedded PowerPC systems compile code for the +FreeBSD operating system. +.IP "\fB\-mcall\-netbsd\fR" 4 +.IX Item "-mcall-netbsd" +On System V.4 and embedded PowerPC systems compile code for the +NetBSD operating system. +.IP "\fB\-mcall\-openbsd\fR" 4 +.IX Item "-mcall-openbsd" +On System V.4 and embedded PowerPC systems compile code for the +OpenBSD operating system. +.IP "\fB\-maix\-struct\-return\fR" 4 +.IX Item "-maix-struct-return" +Return all structures in memory (as specified by the \s-1AIX\s0 \s-1ABI\s0). +.IP "\fB\-msvr4\-struct\-return\fR" 4 +.IX Item "-msvr4-struct-return" +Return structures smaller than 8 bytes in registers (as specified by the +\&\s-1SVR4\s0 \s-1ABI\s0). +.IP "\fB\-mabi=\fR\fIabi-type\fR" 4 +.IX Item "-mabi=abi-type" +Extend the current \s-1ABI\s0 with a particular extension, or remove such extension. +Valid values are \fIaltivec\fR, \fIno-altivec\fR, \fIspe\fR, +\&\fIno-spe\fR, \fIibmlongdouble\fR, \fIieeelongdouble\fR. +.IP "\fB\-mabi=spe\fR" 4 +.IX Item "-mabi=spe" +Extend the current \s-1ABI\s0 with \s-1SPE\s0 \s-1ABI\s0 extensions. This does not change +the default \s-1ABI\s0, instead it adds the \s-1SPE\s0 \s-1ABI\s0 extensions to the current +\&\s-1ABI\s0. +.IP "\fB\-mabi=no\-spe\fR" 4 +.IX Item "-mabi=no-spe" +Disable Booke \s-1SPE\s0 \s-1ABI\s0 extensions for the current \s-1ABI\s0. +.IP "\fB\-mabi=ibmlongdouble\fR" 4 +.IX Item "-mabi=ibmlongdouble" +Change the current \s-1ABI\s0 to use \s-1IBM\s0 extended precision long double. +This is a PowerPC 32\-bit \s-1SYSV\s0 \s-1ABI\s0 option. +.IP "\fB\-mabi=ieeelongdouble\fR" 4 +.IX Item "-mabi=ieeelongdouble" +Change the current \s-1ABI\s0 to use \s-1IEEE\s0 extended precision long double. +This is a PowerPC 32\-bit Linux \s-1ABI\s0 option. +.IP "\fB\-mprototype\fR" 4 +.IX Item "-mprototype" +.PD 0 +.IP "\fB\-mno\-prototype\fR" 4 +.IX Item "-mno-prototype" +.PD +On System V.4 and embedded PowerPC systems assume that all calls to +variable argument functions are properly prototyped. Otherwise, the +compiler must insert an instruction before every non prototyped call to +set or clear bit 6 of the condition code register (\fI\s-1CR\s0\fR) to +indicate whether floating point values were passed in the floating point +registers in case the function takes a variable arguments. With +\&\fB\-mprototype\fR, only calls to prototyped variable argument functions +will set or clear the bit. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +On embedded PowerPC systems, assume that the startup module is called +\&\fIsim\-crt0.o\fR and that the standard C libraries are \fIlibsim.a\fR and +\&\fIlibc.a\fR. This is the default for \fBpowerpc\-*\-eabisim\fR +configurations. +.IP "\fB\-mmvme\fR" 4 +.IX Item "-mmvme" +On embedded PowerPC systems, assume that the startup module is called +\&\fIcrt0.o\fR and the standard C libraries are \fIlibmvme.a\fR and +\&\fIlibc.a\fR. +.IP "\fB\-mads\fR" 4 +.IX Item "-mads" +On embedded PowerPC systems, assume that the startup module is called +\&\fIcrt0.o\fR and the standard C libraries are \fIlibads.a\fR and +\&\fIlibc.a\fR. +.IP "\fB\-myellowknife\fR" 4 +.IX Item "-myellowknife" +On embedded PowerPC systems, assume that the startup module is called +\&\fIcrt0.o\fR and the standard C libraries are \fIlibyk.a\fR and +\&\fIlibc.a\fR. +.IP "\fB\-mvxworks\fR" 4 +.IX Item "-mvxworks" +On System V.4 and embedded PowerPC systems, specify that you are +compiling for a VxWorks system. +.IP "\fB\-memb\fR" 4 +.IX Item "-memb" +On embedded PowerPC systems, set the \fI\s-1PPC_EMB\s0\fR bit in the \s-1ELF\s0 flags +header to indicate that \fBeabi\fR extended relocations are used. +.IP "\fB\-meabi\fR" 4 +.IX Item "-meabi" +.PD 0 +.IP "\fB\-mno\-eabi\fR" 4 +.IX Item "-mno-eabi" +.PD +On System V.4 and embedded PowerPC systems do (do not) adhere to the +Embedded Applications Binary Interface (eabi) which is a set of +modifications to the System V.4 specifications. Selecting \fB\-meabi\fR +means that the stack is aligned to an 8 byte boundary, a function +\&\f(CW\*(C`_\|_eabi\*(C'\fR is called to from \f(CW\*(C`main\*(C'\fR to set up the eabi +environment, and the \fB\-msdata\fR option can use both \f(CW\*(C`r2\*(C'\fR and +\&\f(CW\*(C`r13\*(C'\fR to point to two separate small data areas. Selecting +\&\fB\-mno\-eabi\fR means that the stack is aligned to a 16 byte boundary, +do not call an initialization function from \f(CW\*(C`main\*(C'\fR, and the +\&\fB\-msdata\fR option will only use \f(CW\*(C`r13\*(C'\fR to point to a single +small data area. The \fB\-meabi\fR option is on by default if you +configured \s-1GCC\s0 using one of the \fBpowerpc*\-*\-eabi*\fR options. +.IP "\fB\-msdata=eabi\fR" 4 +.IX Item "-msdata=eabi" +On System V.4 and embedded PowerPC systems, put small initialized +\&\f(CW\*(C`const\*(C'\fR global and static data in the \fB.sdata2\fR section, which +is pointed to by register \f(CW\*(C`r2\*(C'\fR. Put small initialized +non\-\f(CW\*(C`const\*(C'\fR global and static data in the \fB.sdata\fR section, +which is pointed to by register \f(CW\*(C`r13\*(C'\fR. Put small uninitialized +global and static data in the \fB.sbss\fR section, which is adjacent to +the \fB.sdata\fR section. The \fB\-msdata=eabi\fR option is +incompatible with the \fB\-mrelocatable\fR option. The +\&\fB\-msdata=eabi\fR option also sets the \fB\-memb\fR option. +.IP "\fB\-msdata=sysv\fR" 4 +.IX Item "-msdata=sysv" +On System V.4 and embedded PowerPC systems, put small global and static +data in the \fB.sdata\fR section, which is pointed to by register +\&\f(CW\*(C`r13\*(C'\fR. Put small uninitialized global and static data in the +\&\fB.sbss\fR section, which is adjacent to the \fB.sdata\fR section. +The \fB\-msdata=sysv\fR option is incompatible with the +\&\fB\-mrelocatable\fR option. +.IP "\fB\-msdata=default\fR" 4 +.IX Item "-msdata=default" +.PD 0 +.IP "\fB\-msdata\fR" 4 +.IX Item "-msdata" +.PD +On System V.4 and embedded PowerPC systems, if \fB\-meabi\fR is used, +compile code the same as \fB\-msdata=eabi\fR, otherwise compile code the +same as \fB\-msdata=sysv\fR. +.IP "\fB\-msdata=data\fR" 4 +.IX Item "-msdata=data" +On System V.4 and embedded PowerPC systems, put small global +data in the \fB.sdata\fR section. Put small uninitialized global +data in the \fB.sbss\fR section. Do not use register \f(CW\*(C`r13\*(C'\fR +to address small data however. This is the default behavior unless +other \fB\-msdata\fR options are used. +.IP "\fB\-msdata=none\fR" 4 +.IX Item "-msdata=none" +.PD 0 +.IP "\fB\-mno\-sdata\fR" 4 +.IX Item "-mno-sdata" +.PD +On embedded PowerPC systems, put all initialized global and static data +in the \fB.data\fR section, and all uninitialized data in the +\&\fB.bss\fR section. +.IP "\fB\-mblock\-move\-inline\-limit=\fR\fInum\fR" 4 +.IX Item "-mblock-move-inline-limit=num" +Inline all block moves (such as calls to \f(CW\*(C`memcpy\*(C'\fR or structure +copies) less than or equal to \fInum\fR bytes. The minimum value for +\&\fInum\fR is 32 bytes on 32\-bit targets and 64 bytes on 64\-bit +targets. The default value is target-specific. +.IP "\fB\-G\fR \fInum\fR" 4 +.IX Item "-G num" +On embedded PowerPC systems, put global and static items less than or +equal to \fInum\fR bytes into the small data or bss sections instead of +the normal data or bss section. By default, \fInum\fR is 8. The +\&\fB\-G\fR \fInum\fR switch is also passed to the linker. +All modules should be compiled with the same \fB\-G\fR \fInum\fR value. +.IP "\fB\-mregnames\fR" 4 +.IX Item "-mregnames" +.PD 0 +.IP "\fB\-mno\-regnames\fR" 4 +.IX Item "-mno-regnames" +.PD +On System V.4 and embedded PowerPC systems do (do not) emit register +names in the assembly language output using symbolic forms. +.IP "\fB\-mlongcall\fR" 4 +.IX Item "-mlongcall" +.PD 0 +.IP "\fB\-mno\-longcall\fR" 4 +.IX Item "-mno-longcall" +.PD +By default assume that all calls are far away so that a longer more +expensive calling sequence is required. This is required for calls +further than 32 megabytes (33,554,432 bytes) from the current location. +A short call will be generated if the compiler knows +the call cannot be that far away. This setting can be overridden by +the \f(CW\*(C`shortcall\*(C'\fR function attribute, or by \f(CW\*(C`#pragma +longcall(0)\*(C'\fR. +.Sp +Some linkers are capable of detecting out-of-range calls and generating +glue code on the fly. On these systems, long calls are unnecessary and +generate slower code. As of this writing, the \s-1AIX\s0 linker can do this, +as can the \s-1GNU\s0 linker for PowerPC/64. It is planned to add this feature +to the \s-1GNU\s0 linker for 32\-bit PowerPC systems as well. +.Sp +On Darwin/PPC systems, \f(CW\*(C`#pragma longcall\*(C'\fR will generate \*(L"jbsr +callee, L42\*(R", plus a \*(L"branch island\*(R" (glue code). The two target +addresses represent the callee and the \*(L"branch island\*(R". The +Darwin/PPC linker will prefer the first address and generate a \*(L"bl +callee\*(R" if the \s-1PPC\s0 \*(L"bl\*(R" instruction will reach the callee directly; +otherwise, the linker will generate \*(L"bl L42\*(R" to call the \*(L"branch +island\*(R". The \*(L"branch island\*(R" is appended to the body of the +calling function; it computes the full 32\-bit address of the callee +and jumps to it. +.Sp +On Mach-O (Darwin) systems, this option directs the compiler emit to +the glue for every direct call, and the Darwin linker decides whether +to use or discard it. +.Sp +In the future, we may cause \s-1GCC\s0 to ignore all longcall specifications +when the linker is known to generate glue. +.IP "\fB\-mtls\-markers\fR" 4 +.IX Item "-mtls-markers" +.PD 0 +.IP "\fB\-mno\-tls\-markers\fR" 4 +.IX Item "-mno-tls-markers" +.PD +Mark (do not mark) calls to \f(CW\*(C`_\|_tls_get_addr\*(C'\fR with a relocation +specifying the function argument. The relocation allows ld to +reliably associate function call with argument setup instructions for +\&\s-1TLS\s0 optimization, which in turn allows gcc to better schedule the +sequence. +.IP "\fB\-pthread\fR" 4 +.IX Item "-pthread" +Adds support for multithreading with the \fIpthreads\fR library. +This option sets flags for both the preprocessor and linker. +.IP "\fB\-mrecip\fR" 4 +.IX Item "-mrecip" +.PD 0 +.IP "\fB\-mno\-recip\fR" 4 +.IX Item "-mno-recip" +.PD +This option will enable \s-1GCC\s0 to use the reciprocal estimate and +reciprocal square root estimate instructions with additional +Newton-Raphson steps to increase precision instead of doing a divide or +square root and divide for floating point arguments. You should use +the \fB\-ffast\-math\fR option when using \fB\-mrecip\fR (or at +least \fB\-funsafe\-math\-optimizations\fR, +\&\fB\-finite\-math\-only\fR, \fB\-freciprocal\-math\fR and +\&\fB\-fno\-trapping\-math\fR). Note that while the throughput of the +sequence is generally higher than the throughput of the non-reciprocal +instruction, the precision of the sequence can be decreased by up to 2 +ulp (i.e. the inverse of 1.0 equals 0.99999994) for reciprocal square +roots. +.IP "\fB\-mrecip=\fR\fIopt\fR" 4 +.IX Item "-mrecip=opt" +This option allows to control which reciprocal estimate instructions +may be used. \fIopt\fR is a comma separated list of options, that may +be preceded by a \f(CW\*(C`!\*(C'\fR to invert the option: +\&\f(CW\*(C`all\*(C'\fR: enable all estimate instructions, +\&\f(CW\*(C`default\*(C'\fR: enable the default instructions, equivalent to \fB\-mrecip\fR, +\&\f(CW\*(C`none\*(C'\fR: disable all estimate instructions, equivalent to \fB\-mno\-recip\fR; +\&\f(CW\*(C`div\*(C'\fR: enable the reciprocal approximation instructions for both single and double precision; +\&\f(CW\*(C`divf\*(C'\fR: enable the single precision reciprocal approximation instructions; +\&\f(CW\*(C`divd\*(C'\fR: enable the double precision reciprocal approximation instructions; +\&\f(CW\*(C`rsqrt\*(C'\fR: enable the reciprocal square root approximation instructions for both single and double precision; +\&\f(CW\*(C`rsqrtf\*(C'\fR: enable the single precision reciprocal square root approximation instructions; +\&\f(CW\*(C`rsqrtd\*(C'\fR: enable the double precision reciprocal square root approximation instructions; +.Sp +So for example, \fB\-mrecip=all,!rsqrtd\fR would enable the +all of the reciprocal estimate instructions, except for the +\&\f(CW\*(C`FRSQRTE\*(C'\fR, \f(CW\*(C`XSRSQRTEDP\*(C'\fR, and \f(CW\*(C`XVRSQRTEDP\*(C'\fR instructions +which handle the double precision reciprocal square root calculations. +.IP "\fB\-mrecip\-precision\fR" 4 +.IX Item "-mrecip-precision" +.PD 0 +.IP "\fB\-mno\-recip\-precision\fR" 4 +.IX Item "-mno-recip-precision" +.PD +Assume (do not assume) that the reciprocal estimate instructions +provide higher precision estimates than is mandated by the powerpc +\&\s-1ABI\s0. Selecting \fB\-mcpu=power6\fR or \fB\-mcpu=power7\fR +automatically selects \fB\-mrecip\-precision\fR. The double +precision square root estimate instructions are not generated by +default on low precision machines, since they do not provide an +estimate that converges after three steps. +.IP "\fB\-mveclibabi=\fR\fItype\fR" 4 +.IX Item "-mveclibabi=type" +Specifies the \s-1ABI\s0 type to use for vectorizing intrinsics using an +external library. The only type supported at present is \f(CW\*(C`mass\*(C'\fR, +which specifies to use \s-1IBM\s0's Mathematical Acceleration Subsystem +(\s-1MASS\s0) libraries for vectorizing intrinsics using external libraries. +\&\s-1GCC\s0 will currently emit calls to \f(CW\*(C`acosd2\*(C'\fR, \f(CW\*(C`acosf4\*(C'\fR, +\&\f(CW\*(C`acoshd2\*(C'\fR, \f(CW\*(C`acoshf4\*(C'\fR, \f(CW\*(C`asind2\*(C'\fR, \f(CW\*(C`asinf4\*(C'\fR, +\&\f(CW\*(C`asinhd2\*(C'\fR, \f(CW\*(C`asinhf4\*(C'\fR, \f(CW\*(C`atan2d2\*(C'\fR, \f(CW\*(C`atan2f4\*(C'\fR, +\&\f(CW\*(C`atand2\*(C'\fR, \f(CW\*(C`atanf4\*(C'\fR, \f(CW\*(C`atanhd2\*(C'\fR, \f(CW\*(C`atanhf4\*(C'\fR, +\&\f(CW\*(C`cbrtd2\*(C'\fR, \f(CW\*(C`cbrtf4\*(C'\fR, \f(CW\*(C`cosd2\*(C'\fR, \f(CW\*(C`cosf4\*(C'\fR, +\&\f(CW\*(C`coshd2\*(C'\fR, \f(CW\*(C`coshf4\*(C'\fR, \f(CW\*(C`erfcd2\*(C'\fR, \f(CW\*(C`erfcf4\*(C'\fR, +\&\f(CW\*(C`erfd2\*(C'\fR, \f(CW\*(C`erff4\*(C'\fR, \f(CW\*(C`exp2d2\*(C'\fR, \f(CW\*(C`exp2f4\*(C'\fR, +\&\f(CW\*(C`expd2\*(C'\fR, \f(CW\*(C`expf4\*(C'\fR, \f(CW\*(C`expm1d2\*(C'\fR, \f(CW\*(C`expm1f4\*(C'\fR, +\&\f(CW\*(C`hypotd2\*(C'\fR, \f(CW\*(C`hypotf4\*(C'\fR, \f(CW\*(C`lgammad2\*(C'\fR, \f(CW\*(C`lgammaf4\*(C'\fR, +\&\f(CW\*(C`log10d2\*(C'\fR, \f(CW\*(C`log10f4\*(C'\fR, \f(CW\*(C`log1pd2\*(C'\fR, \f(CW\*(C`log1pf4\*(C'\fR, +\&\f(CW\*(C`log2d2\*(C'\fR, \f(CW\*(C`log2f4\*(C'\fR, \f(CW\*(C`logd2\*(C'\fR, \f(CW\*(C`logf4\*(C'\fR, +\&\f(CW\*(C`powd2\*(C'\fR, \f(CW\*(C`powf4\*(C'\fR, \f(CW\*(C`sind2\*(C'\fR, \f(CW\*(C`sinf4\*(C'\fR, \f(CW\*(C`sinhd2\*(C'\fR, +\&\f(CW\*(C`sinhf4\*(C'\fR, \f(CW\*(C`sqrtd2\*(C'\fR, \f(CW\*(C`sqrtf4\*(C'\fR, \f(CW\*(C`tand2\*(C'\fR, +\&\f(CW\*(C`tanf4\*(C'\fR, \f(CW\*(C`tanhd2\*(C'\fR, and \f(CW\*(C`tanhf4\*(C'\fR when generating code +for power7. Both \fB\-ftree\-vectorize\fR and +\&\fB\-funsafe\-math\-optimizations\fR have to be enabled. The \s-1MASS\s0 +libraries will have to be specified at link time. +.IP "\fB\-mfriz\fR" 4 +.IX Item "-mfriz" +.PD 0 +.IP "\fB\-mno\-friz\fR" 4 +.IX Item "-mno-friz" +.PD +Generate (do not generate) the \f(CW\*(C`friz\*(C'\fR instruction when the +\&\fB\-funsafe\-math\-optimizations\fR option is used to optimize +rounding a floating point value to 64\-bit integer and back to floating +point. The \f(CW\*(C`friz\*(C'\fR instruction does not return the same value if +the floating point number is too large to fit in an integer. +.PP +\fI\s-1RX\s0 Options\fR +.IX Subsection "RX Options" +.PP +These command line options are defined for \s-1RX\s0 targets: +.IP "\fB\-m64bit\-doubles\fR" 4 +.IX Item "-m64bit-doubles" +.PD 0 +.IP "\fB\-m32bit\-doubles\fR" 4 +.IX Item "-m32bit-doubles" +.PD +Make the \f(CW\*(C`double\*(C'\fR data type be 64\-bits (\fB\-m64bit\-doubles\fR) +or 32\-bits (\fB\-m32bit\-doubles\fR) in size. The default is +\&\fB\-m32bit\-doubles\fR. \fINote\fR \s-1RX\s0 floating point hardware only +works on 32\-bit values, which is why the default is +\&\fB\-m32bit\-doubles\fR. +.IP "\fB\-fpu\fR" 4 +.IX Item "-fpu" +.PD 0 +.IP "\fB\-nofpu\fR" 4 +.IX Item "-nofpu" +.PD +Enables (\fB\-fpu\fR) or disables (\fB\-nofpu\fR) the use of \s-1RX\s0 +floating point hardware. The default is enabled for the \fI\s-1RX600\s0\fR +series and disabled for the \fI\s-1RX200\s0\fR series. +.Sp +Floating point instructions will only be generated for 32\-bit floating +point values however, so if the \fB\-m64bit\-doubles\fR option is in +use then the \s-1FPU\s0 hardware will not be used for doubles. +.Sp +\&\fINote\fR If the \fB\-fpu\fR option is enabled then +\&\fB\-funsafe\-math\-optimizations\fR is also enabled automatically. +This is because the \s-1RX\s0 \s-1FPU\s0 instructions are themselves unsafe. +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +Selects the type of \s-1RX\s0 \s-1CPU\s0 to be targeted. Currently three types are +supported, the generic \fI\s-1RX600\s0\fR and \fI\s-1RX200\s0\fR series hardware and +the specific \fI\s-1RX610\s0\fR \s-1CPU\s0. The default is \fI\s-1RX600\s0\fR. +.Sp +The only difference between \fI\s-1RX600\s0\fR and \fI\s-1RX610\s0\fR is that the +\&\fI\s-1RX610\s0\fR does not support the \f(CW\*(C`MVTIPL\*(C'\fR instruction. +.Sp +The \fI\s-1RX200\s0\fR series does not have a hardware floating point unit +and so \fB\-nofpu\fR is enabled by default when this type is +selected. +.IP "\fB\-mbig\-endian\-data\fR" 4 +.IX Item "-mbig-endian-data" +.PD 0 +.IP "\fB\-mlittle\-endian\-data\fR" 4 +.IX Item "-mlittle-endian-data" +.PD +Store data (but not code) in the big-endian format. The default is +\&\fB\-mlittle\-endian\-data\fR, i.e. to store data in the little endian +format. +.IP "\fB\-msmall\-data\-limit=\fR\fIN\fR" 4 +.IX Item "-msmall-data-limit=N" +Specifies the maximum size in bytes of global and static variables +which can be placed into the small data area. Using the small data +area can lead to smaller and faster code, but the size of area is +limited and it is up to the programmer to ensure that the area does +not overflow. Also when the small data area is used one of the \s-1RX\s0's +registers (\f(CW\*(C`r13\*(C'\fR) is reserved for use pointing to this area, so +it is no longer available for use by the compiler. This could result +in slower and/or larger code if variables which once could have been +held in \f(CW\*(C`r13\*(C'\fR are now pushed onto the stack. +.Sp +Note, common variables (variables which have not been initialised) and +constants are not placed into the small data area as they are assigned +to other sections in the output executable. +.Sp +The default value is zero, which disables this feature. Note, this +feature is not enabled by default with higher optimization levels +(\fB\-O2\fR etc) because of the potentially detrimental effects of +reserving register \f(CW\*(C`r13\*(C'\fR. It is up to the programmer to +experiment and discover whether this feature is of benefit to their +program. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +.PD 0 +.IP "\fB\-mno\-sim\fR" 4 +.IX Item "-mno-sim" +.PD +Use the simulator runtime. The default is to use the libgloss board +specific runtime. +.IP "\fB\-mas100\-syntax\fR" 4 +.IX Item "-mas100-syntax" +.PD 0 +.IP "\fB\-mno\-as100\-syntax\fR" 4 +.IX Item "-mno-as100-syntax" +.PD +When generating assembler output use a syntax that is compatible with +Renesas's \s-1AS100\s0 assembler. This syntax can also be handled by the \s-1GAS\s0 +assembler but it has some restrictions so generating it is not the +default option. +.IP "\fB\-mmax\-constant\-size=\fR\fIN\fR" 4 +.IX Item "-mmax-constant-size=N" +Specifies the maximum size, in bytes, of a constant that can be used as +an operand in a \s-1RX\s0 instruction. Although the \s-1RX\s0 instruction set does +allow constants of up to 4 bytes in length to be used in instructions, +a longer value equates to a longer instruction. Thus in some +circumstances it can be beneficial to restrict the size of constants +that are used in instructions. Constants that are too big are instead +placed into a constant pool and referenced via register indirection. +.Sp +The value \fIN\fR can be between 0 and 4. A value of 0 (the default) +or 4 means that constants of any size are allowed. +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +Enable linker relaxation. Linker relaxation is a process whereby the +linker will attempt to reduce the size of a program by finding shorter +versions of various instructions. Disabled by default. +.IP "\fB\-mint\-register=\fR\fIN\fR" 4 +.IX Item "-mint-register=N" +Specify the number of registers to reserve for fast interrupt handler +functions. The value \fIN\fR can be between 0 and 4. A value of 1 +means that register \f(CW\*(C`r13\*(C'\fR will be reserved for the exclusive use +of fast interrupt handlers. A value of 2 reserves \f(CW\*(C`r13\*(C'\fR and +\&\f(CW\*(C`r12\*(C'\fR. A value of 3 reserves \f(CW\*(C`r13\*(C'\fR, \f(CW\*(C`r12\*(C'\fR and +\&\f(CW\*(C`r11\*(C'\fR, and a value of 4 reserves \f(CW\*(C`r13\*(C'\fR through \f(CW\*(C`r10\*(C'\fR. +A value of 0, the default, does not reserve any registers. +.IP "\fB\-msave\-acc\-in\-interrupts\fR" 4 +.IX Item "-msave-acc-in-interrupts" +Specifies that interrupt handler functions should preserve the +accumulator register. This is only necessary if normal code might use +the accumulator register, for example because it performs 64\-bit +multiplications. The default is to ignore the accumulator as this +makes the interrupt handlers faster. +.PP +\&\fINote:\fR The generic \s-1GCC\s0 command line \fB\-ffixed\-\fR\fIreg\fR +has special significance to the \s-1RX\s0 port when used with the +\&\f(CW\*(C`interrupt\*(C'\fR function attribute. This attribute indicates a +function intended to process fast interrupts. \s-1GCC\s0 will will ensure +that it only uses the registers \f(CW\*(C`r10\*(C'\fR, \f(CW\*(C`r11\*(C'\fR, \f(CW\*(C`r12\*(C'\fR +and/or \f(CW\*(C`r13\*(C'\fR and only provided that the normal use of the +corresponding registers have been restricted via the +\&\fB\-ffixed\-\fR\fIreg\fR or \fB\-mint\-register\fR command line +options. +.PP +\fIS/390 and zSeries Options\fR +.IX Subsection "S/390 and zSeries Options" +.PP +These are the \fB\-m\fR options defined for the S/390 and zSeries architecture. +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD 0 +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD +Use (do not use) the hardware floating-point instructions and registers +for floating-point operations. When \fB\-msoft\-float\fR is specified, +functions in \fIlibgcc.a\fR will be used to perform floating-point +operations. When \fB\-mhard\-float\fR is specified, the compiler +generates \s-1IEEE\s0 floating-point instructions. This is the default. +.IP "\fB\-mhard\-dfp\fR" 4 +.IX Item "-mhard-dfp" +.PD 0 +.IP "\fB\-mno\-hard\-dfp\fR" 4 +.IX Item "-mno-hard-dfp" +.PD +Use (do not use) the hardware decimal-floating-point instructions for +decimal-floating-point operations. When \fB\-mno\-hard\-dfp\fR is +specified, functions in \fIlibgcc.a\fR will be used to perform +decimal-floating-point operations. When \fB\-mhard\-dfp\fR is +specified, the compiler generates decimal-floating-point hardware +instructions. This is the default for \fB\-march=z9\-ec\fR or higher. +.IP "\fB\-mlong\-double\-64\fR" 4 +.IX Item "-mlong-double-64" +.PD 0 +.IP "\fB\-mlong\-double\-128\fR" 4 +.IX Item "-mlong-double-128" +.PD +These switches control the size of \f(CW\*(C`long double\*(C'\fR type. A size +of 64bit makes the \f(CW\*(C`long double\*(C'\fR type equivalent to the \f(CW\*(C`double\*(C'\fR +type. This is the default. +.IP "\fB\-mbackchain\fR" 4 +.IX Item "-mbackchain" +.PD 0 +.IP "\fB\-mno\-backchain\fR" 4 +.IX Item "-mno-backchain" +.PD +Store (do not store) the address of the caller's frame as backchain pointer +into the callee's stack frame. +A backchain may be needed to allow debugging using tools that do not understand +\&\s-1DWARF\-2\s0 call frame information. +When \fB\-mno\-packed\-stack\fR is in effect, the backchain pointer is stored +at the bottom of the stack frame; when \fB\-mpacked\-stack\fR is in effect, +the backchain is placed into the topmost word of the 96/160 byte register +save area. +.Sp +In general, code compiled with \fB\-mbackchain\fR is call-compatible with +code compiled with \fB\-mmo\-backchain\fR; however, use of the backchain +for debugging purposes usually requires that the whole binary is built with +\&\fB\-mbackchain\fR. Note that the combination of \fB\-mbackchain\fR, +\&\fB\-mpacked\-stack\fR and \fB\-mhard\-float\fR is not supported. In order +to build a linux kernel use \fB\-msoft\-float\fR. +.Sp +The default is to not maintain the backchain. +.IP "\fB\-mpacked\-stack\fR" 4 +.IX Item "-mpacked-stack" +.PD 0 +.IP "\fB\-mno\-packed\-stack\fR" 4 +.IX Item "-mno-packed-stack" +.PD +Use (do not use) the packed stack layout. When \fB\-mno\-packed\-stack\fR is +specified, the compiler uses the all fields of the 96/160 byte register save +area only for their default purpose; unused fields still take up stack space. +When \fB\-mpacked\-stack\fR is specified, register save slots are densely +packed at the top of the register save area; unused space is reused for other +purposes, allowing for more efficient use of the available stack space. +However, when \fB\-mbackchain\fR is also in effect, the topmost word of +the save area is always used to store the backchain, and the return address +register is always saved two words below the backchain. +.Sp +As long as the stack frame backchain is not used, code generated with +\&\fB\-mpacked\-stack\fR is call-compatible with code generated with +\&\fB\-mno\-packed\-stack\fR. Note that some non-FSF releases of \s-1GCC\s0 2.95 for +S/390 or zSeries generated code that uses the stack frame backchain at run +time, not just for debugging purposes. Such code is not call-compatible +with code compiled with \fB\-mpacked\-stack\fR. Also, note that the +combination of \fB\-mbackchain\fR, +\&\fB\-mpacked\-stack\fR and \fB\-mhard\-float\fR is not supported. In order +to build a linux kernel use \fB\-msoft\-float\fR. +.Sp +The default is to not use the packed stack layout. +.IP "\fB\-msmall\-exec\fR" 4 +.IX Item "-msmall-exec" +.PD 0 +.IP "\fB\-mno\-small\-exec\fR" 4 +.IX Item "-mno-small-exec" +.PD +Generate (or do not generate) code using the \f(CW\*(C`bras\*(C'\fR instruction +to do subroutine calls. +This only works reliably if the total executable size does not +exceed 64k. The default is to use the \f(CW\*(C`basr\*(C'\fR instruction instead, +which does not have this limitation. +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.PD 0 +.IP "\fB\-m31\fR" 4 +.IX Item "-m31" +.PD +When \fB\-m31\fR is specified, generate code compliant to the +GNU/Linux for S/390 \s-1ABI\s0. When \fB\-m64\fR is specified, generate +code compliant to the GNU/Linux for zSeries \s-1ABI\s0. This allows \s-1GCC\s0 in +particular to generate 64\-bit instructions. For the \fBs390\fR +targets, the default is \fB\-m31\fR, while the \fBs390x\fR +targets default to \fB\-m64\fR. +.IP "\fB\-mzarch\fR" 4 +.IX Item "-mzarch" +.PD 0 +.IP "\fB\-mesa\fR" 4 +.IX Item "-mesa" +.PD +When \fB\-mzarch\fR is specified, generate code using the +instructions available on z/Architecture. +When \fB\-mesa\fR is specified, generate code using the +instructions available on \s-1ESA/390\s0. Note that \fB\-mesa\fR is +not possible with \fB\-m64\fR. +When generating code compliant to the GNU/Linux for S/390 \s-1ABI\s0, +the default is \fB\-mesa\fR. When generating code compliant +to the GNU/Linux for zSeries \s-1ABI\s0, the default is \fB\-mzarch\fR. +.IP "\fB\-mmvcle\fR" 4 +.IX Item "-mmvcle" +.PD 0 +.IP "\fB\-mno\-mvcle\fR" 4 +.IX Item "-mno-mvcle" +.PD +Generate (or do not generate) code using the \f(CW\*(C`mvcle\*(C'\fR instruction +to perform block moves. When \fB\-mno\-mvcle\fR is specified, +use a \f(CW\*(C`mvc\*(C'\fR loop instead. This is the default unless optimizing for +size. +.IP "\fB\-mdebug\fR" 4 +.IX Item "-mdebug" +.PD 0 +.IP "\fB\-mno\-debug\fR" 4 +.IX Item "-mno-debug" +.PD +Print (or do not print) additional debug information when compiling. +The default is to not print debug information. +.IP "\fB\-march=\fR\fIcpu-type\fR" 4 +.IX Item "-march=cpu-type" +Generate code that will run on \fIcpu-type\fR, which is the name of a system +representing a certain processor type. Possible values for +\&\fIcpu-type\fR are \fBg5\fR, \fBg6\fR, \fBz900\fR, \fBz990\fR, +\&\fBz9\-109\fR, \fBz9\-ec\fR and \fBz10\fR. +When generating code using the instructions available on z/Architecture, +the default is \fB\-march=z900\fR. Otherwise, the default is +\&\fB\-march=g5\fR. +.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 +.IX Item "-mtune=cpu-type" +Tune to \fIcpu-type\fR everything applicable about the generated code, +except for the \s-1ABI\s0 and the set of available instructions. +The list of \fIcpu-type\fR values is the same as for \fB\-march\fR. +The default is the value used for \fB\-march\fR. +.IP "\fB\-mtpf\-trace\fR" 4 +.IX Item "-mtpf-trace" +.PD 0 +.IP "\fB\-mno\-tpf\-trace\fR" 4 +.IX Item "-mno-tpf-trace" +.PD +Generate code that adds (does not add) in \s-1TPF\s0 \s-1OS\s0 specific branches to trace +routines in the operating system. This option is off by default, even +when compiling for the \s-1TPF\s0 \s-1OS\s0. +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Generate code that uses (does not use) the floating point multiply and +accumulate instructions. These instructions are generated by default if +hardware floating point is used. +.IP "\fB\-mwarn\-framesize=\fR\fIframesize\fR" 4 +.IX Item "-mwarn-framesize=framesize" +Emit a warning if the current function exceeds the given frame size. Because +this is a compile time check it doesn't need to be a real problem when the program +runs. It is intended to identify functions which most probably cause +a stack overflow. It is useful to be used in an environment with limited stack +size e.g. the linux kernel. +.IP "\fB\-mwarn\-dynamicstack\fR" 4 +.IX Item "-mwarn-dynamicstack" +Emit a warning if the function calls alloca or uses dynamically +sized arrays. This is generally a bad idea with a limited stack size. +.IP "\fB\-mstack\-guard=\fR\fIstack-guard\fR" 4 +.IX Item "-mstack-guard=stack-guard" +.PD 0 +.IP "\fB\-mstack\-size=\fR\fIstack-size\fR" 4 +.IX Item "-mstack-size=stack-size" +.PD +If these options are provided the s390 back end emits additional instructions in +the function prologue which trigger a trap if the stack size is \fIstack-guard\fR +bytes above the \fIstack-size\fR (remember that the stack on s390 grows downward). +If the \fIstack-guard\fR option is omitted the smallest power of 2 larger than +the frame size of the compiled function is chosen. +These options are intended to be used to help debugging stack overflow problems. +The additionally emitted code causes only little overhead and hence can also be +used in production like systems without greater performance degradation. The given +values have to be exact powers of 2 and \fIstack-size\fR has to be greater than +\&\fIstack-guard\fR without exceeding 64k. +In order to be efficient the extra code makes the assumption that the stack starts +at an address aligned to the value given by \fIstack-size\fR. +The \fIstack-guard\fR option can only be used in conjunction with \fIstack-size\fR. +.PP +\fIScore Options\fR +.IX Subsection "Score Options" +.PP +These options are defined for Score implementations: +.IP "\fB\-meb\fR" 4 +.IX Item "-meb" +Compile code for big endian mode. This is the default. +.IP "\fB\-mel\fR" 4 +.IX Item "-mel" +Compile code for little endian mode. +.IP "\fB\-mnhwloop\fR" 4 +.IX Item "-mnhwloop" +Disable generate bcnz instruction. +.IP "\fB\-muls\fR" 4 +.IX Item "-muls" +Enable generate unaligned load and store instruction. +.IP "\fB\-mmac\fR" 4 +.IX Item "-mmac" +Enable the use of multiply-accumulate instructions. Disabled by default. +.IP "\fB\-mscore5\fR" 4 +.IX Item "-mscore5" +Specify the \s-1SCORE5\s0 as the target architecture. +.IP "\fB\-mscore5u\fR" 4 +.IX Item "-mscore5u" +Specify the \s-1SCORE5U\s0 of the target architecture. +.IP "\fB\-mscore7\fR" 4 +.IX Item "-mscore7" +Specify the \s-1SCORE7\s0 as the target architecture. This is the default. +.IP "\fB\-mscore7d\fR" 4 +.IX Item "-mscore7d" +Specify the \s-1SCORE7D\s0 as the target architecture. +.PP +\fI\s-1SH\s0 Options\fR +.IX Subsection "SH Options" +.PP +These \fB\-m\fR options are defined for the \s-1SH\s0 implementations: +.IP "\fB\-m1\fR" 4 +.IX Item "-m1" +Generate code for the \s-1SH1\s0. +.IP "\fB\-m2\fR" 4 +.IX Item "-m2" +Generate code for the \s-1SH2\s0. +.IP "\fB\-m2e\fR" 4 +.IX Item "-m2e" +Generate code for the SH2e. +.IP "\fB\-m2a\-nofpu\fR" 4 +.IX Item "-m2a-nofpu" +Generate code for the SH2a without \s-1FPU\s0, or for a SH2a\-FPU in such a way +that the floating-point unit is not used. +.IP "\fB\-m2a\-single\-only\fR" 4 +.IX Item "-m2a-single-only" +Generate code for the SH2a\-FPU, in such a way that no double-precision +floating point operations are used. +.IP "\fB\-m2a\-single\fR" 4 +.IX Item "-m2a-single" +Generate code for the SH2a\-FPU assuming the floating-point unit is in +single-precision mode by default. +.IP "\fB\-m2a\fR" 4 +.IX Item "-m2a" +Generate code for the SH2a\-FPU assuming the floating-point unit is in +double-precision mode by default. +.IP "\fB\-m3\fR" 4 +.IX Item "-m3" +Generate code for the \s-1SH3\s0. +.IP "\fB\-m3e\fR" 4 +.IX Item "-m3e" +Generate code for the SH3e. +.IP "\fB\-m4\-nofpu\fR" 4 +.IX Item "-m4-nofpu" +Generate code for the \s-1SH4\s0 without a floating-point unit. +.IP "\fB\-m4\-single\-only\fR" 4 +.IX Item "-m4-single-only" +Generate code for the \s-1SH4\s0 with a floating-point unit that only +supports single-precision arithmetic. +.IP "\fB\-m4\-single\fR" 4 +.IX Item "-m4-single" +Generate code for the \s-1SH4\s0 assuming the floating-point unit is in +single-precision mode by default. +.IP "\fB\-m4\fR" 4 +.IX Item "-m4" +Generate code for the \s-1SH4\s0. +.IP "\fB\-m4a\-nofpu\fR" 4 +.IX Item "-m4a-nofpu" +Generate code for the SH4al\-dsp, or for a SH4a in such a way that the +floating-point unit is not used. +.IP "\fB\-m4a\-single\-only\fR" 4 +.IX Item "-m4a-single-only" +Generate code for the SH4a, in such a way that no double-precision +floating point operations are used. +.IP "\fB\-m4a\-single\fR" 4 +.IX Item "-m4a-single" +Generate code for the SH4a assuming the floating-point unit is in +single-precision mode by default. +.IP "\fB\-m4a\fR" 4 +.IX Item "-m4a" +Generate code for the SH4a. +.IP "\fB\-m4al\fR" 4 +.IX Item "-m4al" +Same as \fB\-m4a\-nofpu\fR, except that it implicitly passes +\&\fB\-dsp\fR to the assembler. \s-1GCC\s0 doesn't generate any \s-1DSP\s0 +instructions at the moment. +.IP "\fB\-mb\fR" 4 +.IX Item "-mb" +Compile code for the processor in big endian mode. +.IP "\fB\-ml\fR" 4 +.IX Item "-ml" +Compile code for the processor in little endian mode. +.IP "\fB\-mdalign\fR" 4 +.IX Item "-mdalign" +Align doubles at 64\-bit boundaries. Note that this changes the calling +conventions, and thus some functions from the standard C library will +not work unless you recompile it first with \fB\-mdalign\fR. +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +Shorten some address references at link time, when possible; uses the +linker option \fB\-relax\fR. +.IP "\fB\-mbigtable\fR" 4 +.IX Item "-mbigtable" +Use 32\-bit offsets in \f(CW\*(C`switch\*(C'\fR tables. The default is to use +16\-bit offsets. +.IP "\fB\-mbitops\fR" 4 +.IX Item "-mbitops" +Enable the use of bit manipulation instructions on \s-1SH2A\s0. +.IP "\fB\-mfmovd\fR" 4 +.IX Item "-mfmovd" +Enable the use of the instruction \f(CW\*(C`fmovd\*(C'\fR. Check \fB\-mdalign\fR for +alignment constraints. +.IP "\fB\-mhitachi\fR" 4 +.IX Item "-mhitachi" +Comply with the calling conventions defined by Renesas. +.IP "\fB\-mrenesas\fR" 4 +.IX Item "-mrenesas" +Comply with the calling conventions defined by Renesas. +.IP "\fB\-mno\-renesas\fR" 4 +.IX Item "-mno-renesas" +Comply with the calling conventions defined for \s-1GCC\s0 before the Renesas +conventions were available. This option is the default for all +targets of the \s-1SH\s0 toolchain except for \fBsh-symbianelf\fR. +.IP "\fB\-mnomacsave\fR" 4 +.IX Item "-mnomacsave" +Mark the \f(CW\*(C`MAC\*(C'\fR register as call-clobbered, even if +\&\fB\-mhitachi\fR is given. +.IP "\fB\-mieee\fR" 4 +.IX Item "-mieee" +Increase IEEE-compliance of floating-point code. +At the moment, this is equivalent to \fB\-fno\-finite\-math\-only\fR. +When generating 16 bit \s-1SH\s0 opcodes, getting IEEE-conforming results for +comparisons of NANs / infinities incurs extra overhead in every +floating point comparison, therefore the default is set to +\&\fB\-ffinite\-math\-only\fR. +.IP "\fB\-minline\-ic_invalidate\fR" 4 +.IX Item "-minline-ic_invalidate" +Inline code to invalidate instruction cache entries after setting up +nested function trampolines. +This option has no effect if \-musermode is in effect and the selected +code generation option (e.g. \-m4) does not allow the use of the icbi +instruction. +If the selected code generation option does not allow the use of the icbi +instruction, and \-musermode is not in effect, the inlined code will +manipulate the instruction cache address array directly with an associative +write. This not only requires privileged mode, but it will also +fail if the cache line had been mapped via the \s-1TLB\s0 and has become unmapped. +.IP "\fB\-misize\fR" 4 +.IX Item "-misize" +Dump instruction size and location in the assembly code. +.IP "\fB\-mpadstruct\fR" 4 +.IX Item "-mpadstruct" +This option is deprecated. It pads structures to multiple of 4 bytes, +which is incompatible with the \s-1SH\s0 \s-1ABI\s0. +.IP "\fB\-mspace\fR" 4 +.IX Item "-mspace" +Optimize for space instead of speed. Implied by \fB\-Os\fR. +.IP "\fB\-mprefergot\fR" 4 +.IX Item "-mprefergot" +When generating position-independent code, emit function calls using +the Global Offset Table instead of the Procedure Linkage Table. +.IP "\fB\-musermode\fR" 4 +.IX Item "-musermode" +Don't generate privileged mode only code; implies \-mno\-inline\-ic_invalidate +if the inlined code would not work in user mode. +This is the default when the target is \f(CW\*(C`sh\-*\-linux*\*(C'\fR. +.IP "\fB\-multcost=\fR\fInumber\fR" 4 +.IX Item "-multcost=number" +Set the cost to assume for a multiply insn. +.IP "\fB\-mdiv=\fR\fIstrategy\fR" 4 +.IX Item "-mdiv=strategy" +Set the division strategy to use for SHmedia code. \fIstrategy\fR must be +one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, +inv:call2, inv:fp . +\&\*(L"fp\*(R" performs the operation in floating point. This has a very high latency, +but needs only a few instructions, so it might be a good choice if +your code has enough easily exploitable \s-1ILP\s0 to allow the compiler to +schedule the floating point instructions together with other instructions. +Division by zero causes a floating point exception. +\&\*(L"inv\*(R" uses integer operations to calculate the inverse of the divisor, +and then multiplies the dividend with the inverse. This strategy allows +cse and hoisting of the inverse calculation. Division by zero calculates +an unspecified result, but does not trap. +\&\*(L"inv:minlat\*(R" is a variant of \*(L"inv\*(R" where if no cse / hoisting opportunities +have been found, or if the entire operation has been hoisted to the same +place, the last stages of the inverse calculation are intertwined with the +final multiply to reduce the overall latency, at the expense of using a few +more instructions, and thus offering fewer scheduling opportunities with +other code. +\&\*(L"call\*(R" calls a library function that usually implements the inv:minlat +strategy. +This gives high code density for m5\-*media\-nofpu compilations. +\&\*(L"call2\*(R" uses a different entry point of the same library function, where it +assumes that a pointer to a lookup table has already been set up, which +exposes the pointer load to cse / code hoisting optimizations. +\&\*(L"inv:call\*(R", \*(L"inv:call2\*(R" and \*(L"inv:fp\*(R" all use the \*(L"inv\*(R" algorithm for initial +code generation, but if the code stays unoptimized, revert to the \*(L"call\*(R", +\&\*(L"call2\*(R", or \*(L"fp\*(R" strategies, respectively. Note that the +potentially-trapping side effect of division by zero is carried by a +separate instruction, so it is possible that all the integer instructions +are hoisted out, but the marker for the side effect stays where it is. +A recombination to fp operations or a call is not possible in that case. +\&\*(L"inv20u\*(R" and \*(L"inv20l\*(R" are variants of the \*(L"inv:minlat\*(R" strategy. In the case +that the inverse calculation was nor separated from the multiply, they speed +up division where the dividend fits into 20 bits (plus sign where applicable), +by inserting a test to skip a number of operations in this case; this test +slows down the case of larger dividends. inv20u assumes the case of a such +a small dividend to be unlikely, and inv20l assumes it to be likely. +.IP "\fB\-maccumulate\-outgoing\-args\fR" 4 +.IX Item "-maccumulate-outgoing-args" +Reserve space once for outgoing arguments in the function prologue rather +than around each call. Generally beneficial for performance and size. Also +needed for unwinding to avoid changing the stack frame around conditional code. +.IP "\fB\-mdivsi3_libfunc=\fR\fIname\fR" 4 +.IX Item "-mdivsi3_libfunc=name" +Set the name of the library function used for 32 bit signed division to +\&\fIname\fR. This only affect the name used in the call and inv:call +division strategies, and the compiler will still expect the same +sets of input/output/clobbered registers as if this option was not present. +.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 +.IX Item "-mfixed-range=register-range" +Generate code treating the given register range as fixed registers. +A fixed register is one that the register allocator can not use. This is +useful when compiling kernel code. A register range is specified as +two registers separated by a dash. Multiple register ranges can be +specified separated by a comma. +.IP "\fB\-madjust\-unroll\fR" 4 +.IX Item "-madjust-unroll" +Throttle unrolling to avoid thrashing target registers. +This option only has an effect if the gcc code base supports the +\&\s-1TARGET_ADJUST_UNROLL_MAX\s0 target hook. +.IP "\fB\-mindexed\-addressing\fR" 4 +.IX Item "-mindexed-addressing" +Enable the use of the indexed addressing mode for SHmedia32/SHcompact. +This is only safe if the hardware and/or \s-1OS\s0 implement 32 bit wrap-around +semantics for the indexed addressing mode. The architecture allows the +implementation of processors with 64 bit \s-1MMU\s0, which the \s-1OS\s0 could use to +get 32 bit addressing, but since no current hardware implementation supports +this or any other way to make the indexed addressing mode safe to use in +the 32 bit \s-1ABI\s0, the default is \-mno\-indexed\-addressing. +.IP "\fB\-mgettrcost=\fR\fInumber\fR" 4 +.IX Item "-mgettrcost=number" +Set the cost assumed for the gettr instruction to \fInumber\fR. +The default is 2 if \fB\-mpt\-fixed\fR is in effect, 100 otherwise. +.IP "\fB\-mpt\-fixed\fR" 4 +.IX Item "-mpt-fixed" +Assume pt* instructions won't trap. This will generally generate better +scheduled code, but is unsafe on current hardware. The current architecture +definition says that ptabs and ptrel trap when the target anded with 3 is 3. +This has the unintentional effect of making it unsafe to schedule ptabs / +ptrel before a branch, or hoist it out of a loop. For example, +_\|_do_global_ctors, a part of libgcc that runs constructors at program +startup, calls functions in a list which is delimited by \-1. With the +\&\-mpt\-fixed option, the ptabs will be done before testing against \-1. +That means that all the constructors will be run a bit quicker, but when +the loop comes to the end of the list, the program crashes because ptabs +loads \-1 into a target register. Since this option is unsafe for any +hardware implementing the current architecture specification, the default +is \-mno\-pt\-fixed. Unless the user specifies a specific cost with +\&\fB\-mgettrcost\fR, \-mno\-pt\-fixed also implies \fB\-mgettrcost=100\fR; +this deters register allocation using target registers for storing +ordinary integers. +.IP "\fB\-minvalid\-symbols\fR" 4 +.IX Item "-minvalid-symbols" +Assume symbols might be invalid. Ordinary function symbols generated by +the compiler will always be valid to load with movi/shori/ptabs or +movi/shori/ptrel, but with assembler and/or linker tricks it is possible +to generate symbols that will cause ptabs / ptrel to trap. +This option is only meaningful when \fB\-mno\-pt\-fixed\fR is in effect. +It will then prevent cross-basic-block cse, hoisting and most scheduling +of symbol loads. The default is \fB\-mno\-invalid\-symbols\fR. +.PP +\fISolaris 2 Options\fR +.IX Subsection "Solaris 2 Options" +.PP +These \fB\-m\fR options are supported on Solaris 2: +.IP "\fB\-mimpure\-text\fR" 4 +.IX Item "-mimpure-text" +\&\fB\-mimpure\-text\fR, used in addition to \fB\-shared\fR, tells +the compiler to not pass \fB\-z text\fR to the linker when linking a +shared object. Using this option, you can link position-dependent +code into a shared object. +.Sp +\&\fB\-mimpure\-text\fR suppresses the \*(L"relocations remain against +allocatable but non-writable sections\*(R" linker error message. +However, the necessary relocations will trigger copy-on-write, and the +shared object is not actually shared across processes. Instead of +using \fB\-mimpure\-text\fR, you should compile all source code with +\&\fB\-fpic\fR or \fB\-fPIC\fR. +.PP +These switches are supported in addition to the above on Solaris 2: +.IP "\fB\-threads\fR" 4 +.IX Item "-threads" +Add support for multithreading using the Solaris threads library. This +option sets flags for both the preprocessor and linker. This option does +not affect the thread safety of object code produced by the compiler or +that of libraries supplied with it. +.IP "\fB\-pthreads\fR" 4 +.IX Item "-pthreads" +Add support for multithreading using the \s-1POSIX\s0 threads library. This +option sets flags for both the preprocessor and linker. This option does +not affect the thread safety of object code produced by the compiler or +that of libraries supplied with it. +.IP "\fB\-pthread\fR" 4 +.IX Item "-pthread" +This is a synonym for \fB\-pthreads\fR. +.PP +\fI\s-1SPARC\s0 Options\fR +.IX Subsection "SPARC Options" +.PP +These \fB\-m\fR options are supported on the \s-1SPARC:\s0 +.IP "\fB\-mno\-app\-regs\fR" 4 +.IX Item "-mno-app-regs" +.PD 0 +.IP "\fB\-mapp\-regs\fR" 4 +.IX Item "-mapp-regs" +.PD +Specify \fB\-mapp\-regs\fR to generate output using the global registers +2 through 4, which the \s-1SPARC\s0 \s-1SVR4\s0 \s-1ABI\s0 reserves for applications. This +is the default. +.Sp +To be fully \s-1SVR4\s0 \s-1ABI\s0 compliant at the cost of some performance loss, +specify \fB\-mno\-app\-regs\fR. You should compile libraries and system +software with this option. +.IP "\fB\-mfpu\fR" 4 +.IX Item "-mfpu" +.PD 0 +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD +Generate output containing floating point instructions. This is the +default. +.IP "\fB\-mno\-fpu\fR" 4 +.IX Item "-mno-fpu" +.PD 0 +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD +Generate output containing library calls for floating point. +\&\fBWarning:\fR the requisite libraries are not available for all \s-1SPARC\s0 +targets. Normally the facilities of the machine's usual C compiler are +used, but this cannot be done directly in cross-compilation. You must make +your own arrangements to provide suitable library functions for +cross-compilation. The embedded targets \fBsparc\-*\-aout\fR and +\&\fBsparclite\-*\-*\fR do provide software floating point support. +.Sp +\&\fB\-msoft\-float\fR changes the calling convention in the output file; +therefore, it is only useful if you compile \fIall\fR of a program with +this option. In particular, you need to compile \fIlibgcc.a\fR, the +library that comes with \s-1GCC\s0, with \fB\-msoft\-float\fR in order for +this to work. +.IP "\fB\-mhard\-quad\-float\fR" 4 +.IX Item "-mhard-quad-float" +Generate output containing quad-word (long double) floating point +instructions. +.IP "\fB\-msoft\-quad\-float\fR" 4 +.IX Item "-msoft-quad-float" +Generate output containing library calls for quad-word (long double) +floating point instructions. The functions called are those specified +in the \s-1SPARC\s0 \s-1ABI\s0. This is the default. +.Sp +As of this writing, there are no \s-1SPARC\s0 implementations that have hardware +support for the quad-word floating point instructions. They all invoke +a trap handler for one of these instructions, and then the trap handler +emulates the effect of the instruction. Because of the trap handler overhead, +this is much slower than calling the \s-1ABI\s0 library routines. Thus the +\&\fB\-msoft\-quad\-float\fR option is the default. +.IP "\fB\-mno\-unaligned\-doubles\fR" 4 +.IX Item "-mno-unaligned-doubles" +.PD 0 +.IP "\fB\-munaligned\-doubles\fR" 4 +.IX Item "-munaligned-doubles" +.PD +Assume that doubles have 8 byte alignment. This is the default. +.Sp +With \fB\-munaligned\-doubles\fR, \s-1GCC\s0 assumes that doubles have 8 byte +alignment only if they are contained in another type, or if they have an +absolute address. Otherwise, it assumes they have 4 byte alignment. +Specifying this option avoids some rare compatibility problems with code +generated by other compilers. It is not the default because it results +in a performance loss, especially for floating point code. +.IP "\fB\-mno\-faster\-structs\fR" 4 +.IX Item "-mno-faster-structs" +.PD 0 +.IP "\fB\-mfaster\-structs\fR" 4 +.IX Item "-mfaster-structs" +.PD +With \fB\-mfaster\-structs\fR, the compiler assumes that structures +should have 8 byte alignment. This enables the use of pairs of +\&\f(CW\*(C`ldd\*(C'\fR and \f(CW\*(C`std\*(C'\fR instructions for copies in structure +assignment, in place of twice as many \f(CW\*(C`ld\*(C'\fR and \f(CW\*(C`st\*(C'\fR pairs. +However, the use of this changed alignment directly violates the \s-1SPARC\s0 +\&\s-1ABI\s0. Thus, it's intended only for use on targets where the developer +acknowledges that their resulting code will not be directly in line with +the rules of the \s-1ABI\s0. +.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 +.IX Item "-mcpu=cpu_type" +Set the instruction set, register set, and instruction scheduling parameters +for machine type \fIcpu_type\fR. Supported values for \fIcpu_type\fR are +\&\fBv7\fR, \fBcypress\fR, \fBv8\fR, \fBsupersparc\fR, \fBhypersparc\fR, +\&\fBleon\fR, \fBsparclite\fR, \fBf930\fR, \fBf934\fR, \fBsparclite86x\fR, +\&\fBsparclet\fR, \fBtsc701\fR, \fBv9\fR, \fBultrasparc\fR, +\&\fBultrasparc3\fR, \fBniagara\fR and \fBniagara2\fR. +.Sp +Default instruction scheduling parameters are used for values that select +an architecture and not an implementation. These are \fBv7\fR, \fBv8\fR, +\&\fBsparclite\fR, \fBsparclet\fR, \fBv9\fR. +.Sp +Here is a list of each supported architecture and their supported +implementations. +.Sp +.Vb 5 +\& v7: cypress +\& v8: supersparc, hypersparc, leon +\& sparclite: f930, f934, sparclite86x +\& sparclet: tsc701 +\& v9: ultrasparc, ultrasparc3, niagara, niagara2 +.Ve +.Sp +By default (unless configured otherwise), \s-1GCC\s0 generates code for the V7 +variant of the \s-1SPARC\s0 architecture. With \fB\-mcpu=cypress\fR, the compiler +additionally optimizes it for the Cypress \s-1CY7C602\s0 chip, as used in the +SPARCStation/SPARCServer 3xx series. This is also appropriate for the older +SPARCStation 1, 2, \s-1IPX\s0 etc. +.Sp +With \fB\-mcpu=v8\fR, \s-1GCC\s0 generates code for the V8 variant of the \s-1SPARC\s0 +architecture. The only difference from V7 code is that the compiler emits +the integer multiply and integer divide instructions which exist in \s-1SPARC\-V8\s0 +but not in \s-1SPARC\-V7\s0. With \fB\-mcpu=supersparc\fR, the compiler additionally +optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and +2000 series. +.Sp +With \fB\-mcpu=sparclite\fR, \s-1GCC\s0 generates code for the SPARClite variant of +the \s-1SPARC\s0 architecture. This adds the integer multiply, integer divide step +and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClite but not in \s-1SPARC\-V7\s0. +With \fB\-mcpu=f930\fR, the compiler additionally optimizes it for the +Fujitsu \s-1MB86930\s0 chip, which is the original SPARClite, with no \s-1FPU\s0. With +\&\fB\-mcpu=f934\fR, the compiler additionally optimizes it for the Fujitsu +\&\s-1MB86934\s0 chip, which is the more recent SPARClite with \s-1FPU\s0. +.Sp +With \fB\-mcpu=sparclet\fR, \s-1GCC\s0 generates code for the SPARClet variant of +the \s-1SPARC\s0 architecture. This adds the integer multiply, multiply/accumulate, +integer divide step and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClet +but not in \s-1SPARC\-V7\s0. With \fB\-mcpu=tsc701\fR, the compiler additionally +optimizes it for the \s-1TEMIC\s0 SPARClet chip. +.Sp +With \fB\-mcpu=v9\fR, \s-1GCC\s0 generates code for the V9 variant of the \s-1SPARC\s0 +architecture. This adds 64\-bit integer and floating-point move instructions, +3 additional floating-point condition code registers and conditional move +instructions. With \fB\-mcpu=ultrasparc\fR, the compiler additionally +optimizes it for the Sun UltraSPARC I/II/IIi chips. With +\&\fB\-mcpu=ultrasparc3\fR, the compiler additionally optimizes it for the +Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips. With +\&\fB\-mcpu=niagara\fR, the compiler additionally optimizes it for +Sun UltraSPARC T1 chips. With \fB\-mcpu=niagara2\fR, the compiler +additionally optimizes it for Sun UltraSPARC T2 chips. +.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4 +.IX Item "-mtune=cpu_type" +Set the instruction scheduling parameters for machine type +\&\fIcpu_type\fR, but do not set the instruction set or register set that the +option \fB\-mcpu=\fR\fIcpu_type\fR would. +.Sp +The same values for \fB\-mcpu=\fR\fIcpu_type\fR can be used for +\&\fB\-mtune=\fR\fIcpu_type\fR, but the only useful values are those +that select a particular \s-1CPU\s0 implementation. Those are \fBcypress\fR, +\&\fBsupersparc\fR, \fBhypersparc\fR, \fBleon\fR, \fBf930\fR, \fBf934\fR, +\&\fBsparclite86x\fR, \fBtsc701\fR, \fBultrasparc\fR, \fBultrasparc3\fR, +\&\fBniagara\fR, and \fBniagara2\fR. +.IP "\fB\-mv8plus\fR" 4 +.IX Item "-mv8plus" +.PD 0 +.IP "\fB\-mno\-v8plus\fR" 4 +.IX Item "-mno-v8plus" +.PD +With \fB\-mv8plus\fR, \s-1GCC\s0 generates code for the \s-1SPARC\-V8+\s0 \s-1ABI\s0. The +difference from the V8 \s-1ABI\s0 is that the global and out registers are +considered 64\-bit wide. This is enabled by default on Solaris in 32\-bit +mode for all \s-1SPARC\-V9\s0 processors. +.IP "\fB\-mvis\fR" 4 +.IX Item "-mvis" +.PD 0 +.IP "\fB\-mno\-vis\fR" 4 +.IX Item "-mno-vis" +.PD +With \fB\-mvis\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC +Visual Instruction Set extensions. The default is \fB\-mno\-vis\fR. +.IP "\fB\-mfix\-at697f\fR" 4 +.IX Item "-mfix-at697f" +Enable the documented workaround for the single erratum of the Atmel \s-1AT697F\s0 +processor (which corresponds to erratum #13 of the \s-1AT697E\s0 processor). +.PP +These \fB\-m\fR options are supported in addition to the above +on \s-1SPARC\-V9\s0 processors in 64\-bit environments: +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +Generate code for a processor running in little-endian mode. It is only +available for a few configurations and most notably not on Solaris and Linux. +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" +.PD 0 +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.PD +Generate code for a 32\-bit or 64\-bit environment. +The 32\-bit environment sets int, long and pointer to 32 bits. +The 64\-bit environment sets int to 32 bits and long and pointer +to 64 bits. +.IP "\fB\-mcmodel=medlow\fR" 4 +.IX Item "-mcmodel=medlow" +Generate code for the Medium/Low code model: 64\-bit addresses, programs +must be linked in the low 32 bits of memory. Programs can be statically +or dynamically linked. +.IP "\fB\-mcmodel=medmid\fR" 4 +.IX Item "-mcmodel=medmid" +Generate code for the Medium/Middle code model: 64\-bit addresses, programs +must be linked in the low 44 bits of memory, the text and data segments must +be less than 2GB in size and the data segment must be located within 2GB of +the text segment. +.IP "\fB\-mcmodel=medany\fR" 4 +.IX Item "-mcmodel=medany" +Generate code for the Medium/Anywhere code model: 64\-bit addresses, programs +may be linked anywhere in memory, the text and data segments must be less +than 2GB in size and the data segment must be located within 2GB of the +text segment. +.IP "\fB\-mcmodel=embmedany\fR" 4 +.IX Item "-mcmodel=embmedany" +Generate code for the Medium/Anywhere code model for embedded systems: +64\-bit addresses, the text and data segments must be less than 2GB in +size, both starting anywhere in memory (determined at link time). The +global register \f(CW%g4\fR points to the base of the data segment. Programs +are statically linked and \s-1PIC\s0 is not supported. +.IP "\fB\-mstack\-bias\fR" 4 +.IX Item "-mstack-bias" +.PD 0 +.IP "\fB\-mno\-stack\-bias\fR" 4 +.IX Item "-mno-stack-bias" +.PD +With \fB\-mstack\-bias\fR, \s-1GCC\s0 assumes that the stack pointer, and +frame pointer if present, are offset by \-2047 which must be added back +when making stack frame references. This is the default in 64\-bit mode. +Otherwise, assume no such offset is present. +.PP +\fI\s-1SPU\s0 Options\fR +.IX Subsection "SPU Options" +.PP +These \fB\-m\fR options are supported on the \s-1SPU:\s0 +.IP "\fB\-mwarn\-reloc\fR" 4 +.IX Item "-mwarn-reloc" +.PD 0 +.IP "\fB\-merror\-reloc\fR" 4 +.IX Item "-merror-reloc" +.PD +The loader for \s-1SPU\s0 does not handle dynamic relocations. By default, \s-1GCC\s0 +will give an error when it generates code that requires a dynamic +relocation. \fB\-mno\-error\-reloc\fR disables the error, +\&\fB\-mwarn\-reloc\fR will generate a warning instead. +.IP "\fB\-msafe\-dma\fR" 4 +.IX Item "-msafe-dma" +.PD 0 +.IP "\fB\-munsafe\-dma\fR" 4 +.IX Item "-munsafe-dma" +.PD +Instructions which initiate or test completion of \s-1DMA\s0 must not be +reordered with respect to loads and stores of the memory which is being +accessed. Users typically address this problem using the volatile +keyword, but that can lead to inefficient code in places where the +memory is known to not change. Rather than mark the memory as volatile +we treat the \s-1DMA\s0 instructions as potentially effecting all memory. With +\&\fB\-munsafe\-dma\fR users must use the volatile keyword to protect +memory accesses. +.IP "\fB\-mbranch\-hints\fR" 4 +.IX Item "-mbranch-hints" +By default, \s-1GCC\s0 will generate a branch hint instruction to avoid +pipeline stalls for always taken or probably taken branches. A hint +will not be generated closer than 8 instructions away from its branch. +There is little reason to disable them, except for debugging purposes, +or to make an object a little bit smaller. +.IP "\fB\-msmall\-mem\fR" 4 +.IX Item "-msmall-mem" +.PD 0 +.IP "\fB\-mlarge\-mem\fR" 4 +.IX Item "-mlarge-mem" +.PD +By default, \s-1GCC\s0 generates code assuming that addresses are never larger +than 18 bits. With \fB\-mlarge\-mem\fR code is generated that assumes +a full 32 bit address. +.IP "\fB\-mstdmain\fR" 4 +.IX Item "-mstdmain" +By default, \s-1GCC\s0 links against startup code that assumes the SPU-style +main function interface (which has an unconventional parameter list). +With \fB\-mstdmain\fR, \s-1GCC\s0 will link your program against startup +code that assumes a C99\-style interface to \f(CW\*(C`main\*(C'\fR, including a +local copy of \f(CW\*(C`argv\*(C'\fR strings. +.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 +.IX Item "-mfixed-range=register-range" +Generate code treating the given register range as fixed registers. +A fixed register is one that the register allocator can not use. This is +useful when compiling kernel code. A register range is specified as +two registers separated by a dash. Multiple register ranges can be +specified separated by a comma. +.IP "\fB\-mea32\fR" 4 +.IX Item "-mea32" +.PD 0 +.IP "\fB\-mea64\fR" 4 +.IX Item "-mea64" +.PD +Compile code assuming that pointers to the \s-1PPU\s0 address space accessed +via the \f(CW\*(C`_\|_ea\*(C'\fR named address space qualifier are either 32 or 64 +bits wide. The default is 32 bits. As this is an \s-1ABI\s0 changing option, +all object code in an executable must be compiled with the same setting. +.IP "\fB\-maddress\-space\-conversion\fR" 4 +.IX Item "-maddress-space-conversion" +.PD 0 +.IP "\fB\-mno\-address\-space\-conversion\fR" 4 +.IX Item "-mno-address-space-conversion" +.PD +Allow/disallow treating the \f(CW\*(C`_\|_ea\*(C'\fR address space as superset +of the generic address space. This enables explicit type casts +between \f(CW\*(C`_\|_ea\*(C'\fR and generic pointer as well as implicit +conversions of generic pointers to \f(CW\*(C`_\|_ea\*(C'\fR pointers. The +default is to allow address space pointer conversions. +.IP "\fB\-mcache\-size=\fR\fIcache-size\fR" 4 +.IX Item "-mcache-size=cache-size" +This option controls the version of libgcc that the compiler links to an +executable and selects a software-managed cache for accessing variables +in the \f(CW\*(C`_\|_ea\*(C'\fR address space with a particular cache size. Possible +options for \fIcache-size\fR are \fB8\fR, \fB16\fR, \fB32\fR, \fB64\fR +and \fB128\fR. The default cache size is 64KB. +.IP "\fB\-matomic\-updates\fR" 4 +.IX Item "-matomic-updates" +.PD 0 +.IP "\fB\-mno\-atomic\-updates\fR" 4 +.IX Item "-mno-atomic-updates" +.PD +This option controls the version of libgcc that the compiler links to an +executable and selects whether atomic updates to the software-managed +cache of PPU-side variables are used. If you use atomic updates, changes +to a \s-1PPU\s0 variable from \s-1SPU\s0 code using the \f(CW\*(C`_\|_ea\*(C'\fR named address space +qualifier will not interfere with changes to other \s-1PPU\s0 variables residing +in the same cache line from \s-1PPU\s0 code. If you do not use atomic updates, +such interference may occur; however, writing back cache lines will be +more efficient. The default behavior is to use atomic updates. +.IP "\fB\-mdual\-nops\fR" 4 +.IX Item "-mdual-nops" +.PD 0 +.IP "\fB\-mdual\-nops=\fR\fIn\fR" 4 +.IX Item "-mdual-nops=n" +.PD +By default, \s-1GCC\s0 will insert nops to increase dual issue when it expects +it to increase performance. \fIn\fR can be a value from 0 to 10. A +smaller \fIn\fR will insert fewer nops. 10 is the default, 0 is the +same as \fB\-mno\-dual\-nops\fR. Disabled with \fB\-Os\fR. +.IP "\fB\-mhint\-max\-nops=\fR\fIn\fR" 4 +.IX Item "-mhint-max-nops=n" +Maximum number of nops to insert for a branch hint. A branch hint must +be at least 8 instructions away from the branch it is effecting. \s-1GCC\s0 +will insert up to \fIn\fR nops to enforce this, otherwise it will not +generate the branch hint. +.IP "\fB\-mhint\-max\-distance=\fR\fIn\fR" 4 +.IX Item "-mhint-max-distance=n" +The encoding of the branch hint instruction limits the hint to be within +256 instructions of the branch it is effecting. By default, \s-1GCC\s0 makes +sure it is within 125. +.IP "\fB\-msafe\-hints\fR" 4 +.IX Item "-msafe-hints" +Work around a hardware bug which causes the \s-1SPU\s0 to stall indefinitely. +By default, \s-1GCC\s0 will insert the \f(CW\*(C`hbrp\*(C'\fR instruction to make sure +this stall won't happen. +.PP +\fIOptions for System V\fR +.IX Subsection "Options for System V" +.PP +These additional options are available on System V Release 4 for +compatibility with other compilers on those systems: +.IP "\fB\-G\fR" 4 +.IX Item "-G" +Create a shared object. +It is recommended that \fB\-symbolic\fR or \fB\-shared\fR be used instead. +.IP "\fB\-Qy\fR" 4 +.IX Item "-Qy" +Identify the versions of each tool used by the compiler, in a +\&\f(CW\*(C`.ident\*(C'\fR assembler directive in the output. +.IP "\fB\-Qn\fR" 4 +.IX Item "-Qn" +Refrain from adding \f(CW\*(C`.ident\*(C'\fR directives to the output file (this is +the default). +.IP "\fB\-YP,\fR\fIdirs\fR" 4 +.IX Item "-YP,dirs" +Search the directories \fIdirs\fR, and no others, for libraries +specified with \fB\-l\fR. +.IP "\fB\-Ym,\fR\fIdir\fR" 4 +.IX Item "-Ym,dir" +Look in the directory \fIdir\fR to find the M4 preprocessor. +The assembler uses this option. +.PP +\fIV850 Options\fR +.IX Subsection "V850 Options" +.PP +These \fB\-m\fR options are defined for V850 implementations: +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" +.PD 0 +.IP "\fB\-mno\-long\-calls\fR" 4 +.IX Item "-mno-long-calls" +.PD +Treat all calls as being far away (near). If calls are assumed to be +far away, the compiler will always load the functions address up into a +register, and call indirect through the pointer. +.IP "\fB\-mno\-ep\fR" 4 +.IX Item "-mno-ep" +.PD 0 +.IP "\fB\-mep\fR" 4 +.IX Item "-mep" +.PD +Do not optimize (do optimize) basic blocks that use the same index +pointer 4 or more times to copy pointer into the \f(CW\*(C`ep\*(C'\fR register, and +use the shorter \f(CW\*(C`sld\*(C'\fR and \f(CW\*(C`sst\*(C'\fR instructions. The \fB\-mep\fR +option is on by default if you optimize. +.IP "\fB\-mno\-prolog\-function\fR" 4 +.IX Item "-mno-prolog-function" +.PD 0 +.IP "\fB\-mprolog\-function\fR" 4 +.IX Item "-mprolog-function" +.PD +Do not use (do use) external functions to save and restore registers +at the prologue and epilogue of a function. The external functions +are slower, but use less code space if more than one function saves +the same number of registers. The \fB\-mprolog\-function\fR option +is on by default if you optimize. +.IP "\fB\-mspace\fR" 4 +.IX Item "-mspace" +Try to make the code as small as possible. At present, this just turns +on the \fB\-mep\fR and \fB\-mprolog\-function\fR options. +.IP "\fB\-mtda=\fR\fIn\fR" 4 +.IX Item "-mtda=n" +Put static or global variables whose size is \fIn\fR bytes or less into +the tiny data area that register \f(CW\*(C`ep\*(C'\fR points to. The tiny data +area can hold up to 256 bytes in total (128 bytes for byte references). +.IP "\fB\-msda=\fR\fIn\fR" 4 +.IX Item "-msda=n" +Put static or global variables whose size is \fIn\fR bytes or less into +the small data area that register \f(CW\*(C`gp\*(C'\fR points to. The small data +area can hold up to 64 kilobytes. +.IP "\fB\-mzda=\fR\fIn\fR" 4 +.IX Item "-mzda=n" +Put static or global variables whose size is \fIn\fR bytes or less into +the first 32 kilobytes of memory. +.IP "\fB\-mv850\fR" 4 +.IX Item "-mv850" +Specify that the target processor is the V850. +.IP "\fB\-mbig\-switch\fR" 4 +.IX Item "-mbig-switch" +Generate code suitable for big switch tables. Use this option only if +the assembler/linker complain about out of range branches within a switch +table. +.IP "\fB\-mapp\-regs\fR" 4 +.IX Item "-mapp-regs" +This option will cause r2 and r5 to be used in the code generated by +the compiler. This setting is the default. +.IP "\fB\-mno\-app\-regs\fR" 4 +.IX Item "-mno-app-regs" +This option will cause r2 and r5 to be treated as fixed registers. +.IP "\fB\-mv850e2v3\fR" 4 +.IX Item "-mv850e2v3" +Specify that the target processor is the V850E2V3. The preprocessor +constants \fB_\|_v850e2v3_\|_\fR will be defined if +this option is used. +.IP "\fB\-mv850e2\fR" 4 +.IX Item "-mv850e2" +Specify that the target processor is the V850E2. The preprocessor +constants \fB_\|_v850e2_\|_\fR will be defined if +.IP "\fB\-mv850e1\fR" 4 +.IX Item "-mv850e1" +Specify that the target processor is the V850E1. The preprocessor +constants \fB_\|_v850e1_\|_\fR and \fB_\|_v850e_\|_\fR will be defined if +.IP "\fB\-mv850es\fR" 4 +.IX Item "-mv850es" +Specify that the target processor is the V850ES. This is an alias for +the \fB\-mv850e1\fR option. +.IP "\fB\-mv850e\fR" 4 +.IX Item "-mv850e" +Specify that the target processor is the V850E. The preprocessor +constant \fB_\|_v850e_\|_\fR will be defined if this option is used. +.Sp +If neither \fB\-mv850\fR nor \fB\-mv850e\fR nor \fB\-mv850e1\fR +nor \fB\-mv850e2\fR nor \fB\-mv850e2v3\fR +are defined then a default target processor will be chosen and the +relevant \fB_\|_v850*_\|_\fR preprocessor constant will be defined. +.Sp +The preprocessor constants \fB_\|_v850\fR and \fB_\|_v851_\|_\fR are always +defined, regardless of which processor variant is the target. +.IP "\fB\-mdisable\-callt\fR" 4 +.IX Item "-mdisable-callt" +This option will suppress generation of the \s-1CALLT\s0 instruction for the +v850e, v850e1, v850e2 and v850e2v3 flavors of the v850 architecture. The default is +\&\fB\-mno\-disable\-callt\fR which allows the \s-1CALLT\s0 instruction to be used. +.PP +\fI\s-1VAX\s0 Options\fR +.IX Subsection "VAX Options" +.PP +These \fB\-m\fR options are defined for the \s-1VAX:\s0 +.IP "\fB\-munix\fR" 4 +.IX Item "-munix" +Do not output certain jump instructions (\f(CW\*(C`aobleq\*(C'\fR and so on) +that the Unix assembler for the \s-1VAX\s0 cannot handle across long +ranges. +.IP "\fB\-mgnu\fR" 4 +.IX Item "-mgnu" +Do output those jump instructions, on the assumption that you +will assemble with the \s-1GNU\s0 assembler. +.IP "\fB\-mg\fR" 4 +.IX Item "-mg" +Output code for g\-format floating point numbers instead of d\-format. +.PP +\fIVxWorks Options\fR +.IX Subsection "VxWorks Options" +.PP +The options in this section are defined for all VxWorks targets. +Options specific to the target hardware are listed with the other +options for that target. +.IP "\fB\-mrtp\fR" 4 +.IX Item "-mrtp" +\&\s-1GCC\s0 can generate code for both VxWorks kernels and real time processes +(RTPs). This option switches from the former to the latter. It also +defines the preprocessor macro \f(CW\*(C`_\|_RTP_\|_\*(C'\fR. +.IP "\fB\-non\-static\fR" 4 +.IX Item "-non-static" +Link an \s-1RTP\s0 executable against shared libraries rather than static +libraries. The options \fB\-static\fR and \fB\-shared\fR can +also be used for RTPs; \fB\-static\fR +is the default. +.IP "\fB\-Bstatic\fR" 4 +.IX Item "-Bstatic" +.PD 0 +.IP "\fB\-Bdynamic\fR" 4 +.IX Item "-Bdynamic" +.PD +These options are passed down to the linker. They are defined for +compatibility with Diab. +.IP "\fB\-Xbind\-lazy\fR" 4 +.IX Item "-Xbind-lazy" +Enable lazy binding of function calls. This option is equivalent to +\&\fB\-Wl,\-z,now\fR and is defined for compatibility with Diab. +.IP "\fB\-Xbind\-now\fR" 4 +.IX Item "-Xbind-now" +Disable lazy binding of function calls. This option is the default and +is defined for compatibility with Diab. +.PP +\fIx86\-64 Options\fR +.IX Subsection "x86-64 Options" +.PP +These are listed under +.PP +\fIXstormy16 Options\fR +.IX Subsection "Xstormy16 Options" +.PP +These options are defined for Xstormy16: +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +Choose startup files and linker script suitable for the simulator. +.PP +\fIXtensa Options\fR +.IX Subsection "Xtensa Options" +.PP +These options are supported for Xtensa targets: +.IP "\fB\-mconst16\fR" 4 +.IX Item "-mconst16" +.PD 0 +.IP "\fB\-mno\-const16\fR" 4 +.IX Item "-mno-const16" +.PD +Enable or disable use of \f(CW\*(C`CONST16\*(C'\fR instructions for loading +constant values. The \f(CW\*(C`CONST16\*(C'\fR instruction is currently not a +standard option from Tensilica. When enabled, \f(CW\*(C`CONST16\*(C'\fR +instructions are always used in place of the standard \f(CW\*(C`L32R\*(C'\fR +instructions. The use of \f(CW\*(C`CONST16\*(C'\fR is enabled by default only if +the \f(CW\*(C`L32R\*(C'\fR instruction is not available. +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" +.PD 0 +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" +.PD +Enable or disable use of fused multiply/add and multiply/subtract +instructions in the floating-point option. This has no effect if the +floating-point option is not also enabled. Disabling fused multiply/add +and multiply/subtract instructions forces the compiler to use separate +instructions for the multiply and add/subtract operations. This may be +desirable in some cases where strict \s-1IEEE\s0 754\-compliant results are +required: the fused multiply add/subtract instructions do not round the +intermediate result, thereby producing results with \fImore\fR bits of +precision than specified by the \s-1IEEE\s0 standard. Disabling fused multiply +add/subtract instructions also ensures that the program output is not +sensitive to the compiler's ability to combine multiply and add/subtract +operations. +.IP "\fB\-mserialize\-volatile\fR" 4 +.IX Item "-mserialize-volatile" +.PD 0 +.IP "\fB\-mno\-serialize\-volatile\fR" 4 +.IX Item "-mno-serialize-volatile" +.PD +When this option is enabled, \s-1GCC\s0 inserts \f(CW\*(C`MEMW\*(C'\fR instructions before +\&\f(CW\*(C`volatile\*(C'\fR memory references to guarantee sequential consistency. +The default is \fB\-mserialize\-volatile\fR. Use +\&\fB\-mno\-serialize\-volatile\fR to omit the \f(CW\*(C`MEMW\*(C'\fR instructions. +.IP "\fB\-mforce\-no\-pic\fR" 4 +.IX Item "-mforce-no-pic" +For targets, like GNU/Linux, where all user-mode Xtensa code must be +position-independent code (\s-1PIC\s0), this option disables \s-1PIC\s0 for compiling +kernel code. +.IP "\fB\-mtext\-section\-literals\fR" 4 +.IX Item "-mtext-section-literals" +.PD 0 +.IP "\fB\-mno\-text\-section\-literals\fR" 4 +.IX Item "-mno-text-section-literals" +.PD +Control the treatment of literal pools. The default is +\&\fB\-mno\-text\-section\-literals\fR, which places literals in a separate +section in the output file. This allows the literal pool to be placed +in a data \s-1RAM/ROM\s0, and it also allows the linker to combine literal +pools from separate object files to remove redundant literals and +improve code size. With \fB\-mtext\-section\-literals\fR, the literals +are interspersed in the text section in order to keep them as close as +possible to their references. This may be necessary for large assembly +files. +.IP "\fB\-mtarget\-align\fR" 4 +.IX Item "-mtarget-align" +.PD 0 +.IP "\fB\-mno\-target\-align\fR" 4 +.IX Item "-mno-target-align" +.PD +When this option is enabled, \s-1GCC\s0 instructs the assembler to +automatically align instructions to reduce branch penalties at the +expense of some code density. The assembler attempts to widen density +instructions to align branch targets and the instructions following call +instructions. If there are not enough preceding safe density +instructions to align a target, no widening will be performed. The +default is \fB\-mtarget\-align\fR. These options do not affect the +treatment of auto-aligned instructions like \f(CW\*(C`LOOP\*(C'\fR, which the +assembler will always align, either by widening density instructions or +by inserting no-op instructions. +.IP "\fB\-mlongcalls\fR" 4 +.IX Item "-mlongcalls" +.PD 0 +.IP "\fB\-mno\-longcalls\fR" 4 +.IX Item "-mno-longcalls" +.PD +When this option is enabled, \s-1GCC\s0 instructs the assembler to translate +direct calls to indirect calls unless it can determine that the target +of a direct call is in the range allowed by the call instruction. This +translation typically occurs for calls to functions in other source +files. Specifically, the assembler translates a direct \f(CW\*(C`CALL\*(C'\fR +instruction into an \f(CW\*(C`L32R\*(C'\fR followed by a \f(CW\*(C`CALLX\*(C'\fR instruction. +The default is \fB\-mno\-longcalls\fR. This option should be used in +programs where the call target can potentially be out of range. This +option is implemented in the assembler, not the compiler, so the +assembly code generated by \s-1GCC\s0 will still show direct call +instructions\-\-\-look at the disassembled object code to see the actual +instructions. Note that the assembler will use an indirect call for +every cross-file call, not just those that really will be out of range. +.PP +\fIzSeries Options\fR +.IX Subsection "zSeries Options" +.PP +These are listed under +.SS "Options for Code Generation Conventions" +.IX Subsection "Options for Code Generation Conventions" +These machine-independent options control the interface conventions +used in code generation. +.PP +Most of them have both positive and negative forms; the negative form +of \fB\-ffoo\fR would be \fB\-fno\-foo\fR. In the table below, only +one of the forms is listed\-\-\-the one which is not the default. You +can figure out the other form by either removing \fBno\-\fR or adding +it. +.IP "\fB\-fbounds\-check\fR" 4 +.IX Item "-fbounds-check" +For front-ends that support it, generate additional code to check that +indices used to access arrays are within the declared range. This is +currently only supported by the Java and Fortran front-ends, where +this option defaults to true and false respectively. +.IP "\fB\-ftrapv\fR" 4 +.IX Item "-ftrapv" +This option generates traps for signed overflow on addition, subtraction, +multiplication operations. +.IP "\fB\-fwrapv\fR" 4 +.IX Item "-fwrapv" +This option instructs the compiler to assume that signed arithmetic +overflow of addition, subtraction and multiplication wraps around +using twos-complement representation. This flag enables some optimizations +and disables others. This option is enabled by default for the Java +front-end, as required by the Java language specification. +.IP "\fB\-fexceptions\fR" 4 +.IX Item "-fexceptions" +Enable exception handling. Generates extra code needed to propagate +exceptions. For some targets, this implies \s-1GCC\s0 will generate frame +unwind information for all functions, which can produce significant data +size overhead, although it does not affect execution. If you do not +specify this option, \s-1GCC\s0 will enable it by default for languages like +\&\*(C+ which normally require exception handling, and disable it for +languages like C that do not normally require it. However, you may need +to enable this option when compiling C code that needs to interoperate +properly with exception handlers written in \*(C+. You may also wish to +disable this option if you are compiling older \*(C+ programs that don't +use exception handling. +.IP "\fB\-fnon\-call\-exceptions\fR" 4 +.IX Item "-fnon-call-exceptions" +Generate code that allows trapping instructions to throw exceptions. +Note that this requires platform-specific runtime support that does +not exist everywhere. Moreover, it only allows \fItrapping\fR +instructions to throw exceptions, i.e. memory references or floating +point instructions. It does not allow exceptions to be thrown from +arbitrary signal handlers such as \f(CW\*(C`SIGALRM\*(C'\fR. +.IP "\fB\-funwind\-tables\fR" 4 +.IX Item "-funwind-tables" +Similar to \fB\-fexceptions\fR, except that it will just generate any needed +static data, but will not affect the generated code in any other way. +You will normally not enable this option; instead, a language processor +that needs this handling would enable it on your behalf. +.IP "\fB\-fasynchronous\-unwind\-tables\fR" 4 +.IX Item "-fasynchronous-unwind-tables" +Generate unwind table in dwarf2 format, if supported by target machine. The +table is exact at each instruction boundary, so it can be used for stack +unwinding from asynchronous events (such as debugger or garbage collector). +.IP "\fB\-fpcc\-struct\-return\fR" 4 +.IX Item "-fpcc-struct-return" +Return \*(L"short\*(R" \f(CW\*(C`struct\*(C'\fR and \f(CW\*(C`union\*(C'\fR values in memory like +longer ones, rather than in registers. This convention is less +efficient, but it has the advantage of allowing intercallability between +GCC-compiled files and files compiled with other compilers, particularly +the Portable C Compiler (pcc). +.Sp +The precise convention for returning structures in memory depends +on the target configuration macros. +.Sp +Short structures and unions are those whose size and alignment match +that of some integer type. +.Sp +\&\fBWarning:\fR code compiled with the \fB\-fpcc\-struct\-return\fR +switch is not binary compatible with code compiled with the +\&\fB\-freg\-struct\-return\fR switch. +Use it to conform to a non-default application binary interface. +.IP "\fB\-freg\-struct\-return\fR" 4 +.IX Item "-freg-struct-return" +Return \f(CW\*(C`struct\*(C'\fR and \f(CW\*(C`union\*(C'\fR values in registers when possible. +This is more efficient for small structures than +\&\fB\-fpcc\-struct\-return\fR. +.Sp +If you specify neither \fB\-fpcc\-struct\-return\fR nor +\&\fB\-freg\-struct\-return\fR, \s-1GCC\s0 defaults to whichever convention is +standard for the target. If there is no standard convention, \s-1GCC\s0 +defaults to \fB\-fpcc\-struct\-return\fR, except on targets where \s-1GCC\s0 is +the principal compiler. In those cases, we can choose the standard, and +we chose the more efficient register return alternative. +.Sp +\&\fBWarning:\fR code compiled with the \fB\-freg\-struct\-return\fR +switch is not binary compatible with code compiled with the +\&\fB\-fpcc\-struct\-return\fR switch. +Use it to conform to a non-default application binary interface. +.IP "\fB\-fshort\-enums\fR" 4 +.IX Item "-fshort-enums" +Allocate to an \f(CW\*(C`enum\*(C'\fR type only as many bytes as it needs for the +declared range of possible values. Specifically, the \f(CW\*(C`enum\*(C'\fR type +will be equivalent to the smallest integer type which has enough room. +.Sp +\&\fBWarning:\fR the \fB\-fshort\-enums\fR switch causes \s-1GCC\s0 to generate +code that is not binary compatible with code generated without that switch. +Use it to conform to a non-default application binary interface. +.IP "\fB\-fshort\-double\fR" 4 +.IX Item "-fshort-double" +Use the same size for \f(CW\*(C`double\*(C'\fR as for \f(CW\*(C`float\*(C'\fR. +.Sp +\&\fBWarning:\fR the \fB\-fshort\-double\fR switch causes \s-1GCC\s0 to generate +code that is not binary compatible with code generated without that switch. +Use it to conform to a non-default application binary interface. +.IP "\fB\-fshort\-wchar\fR" 4 +.IX Item "-fshort-wchar" +Override the underlying type for \fBwchar_t\fR to be \fBshort +unsigned int\fR instead of the default for the target. This option is +useful for building programs to run under \s-1WINE\s0. +.Sp +\&\fBWarning:\fR the \fB\-fshort\-wchar\fR switch causes \s-1GCC\s0 to generate +code that is not binary compatible with code generated without that switch. +Use it to conform to a non-default application binary interface. +.IP "\fB\-fno\-common\fR" 4 +.IX Item "-fno-common" +In C code, controls the placement of uninitialized global variables. +Unix C compilers have traditionally permitted multiple definitions of +such variables in different compilation units by placing the variables +in a common block. +This is the behavior specified by \fB\-fcommon\fR, and is the default +for \s-1GCC\s0 on most targets. +On the other hand, this behavior is not required by \s-1ISO\s0 C, and on some +targets may carry a speed or code size penalty on variable references. +The \fB\-fno\-common\fR option specifies that the compiler should place +uninitialized global variables in the data section of the object file, +rather than generating them as common blocks. +This has the effect that if the same variable is declared +(without \f(CW\*(C`extern\*(C'\fR) in two different compilations, +you will get a multiple-definition error when you link them. +In this case, you must compile with \fB\-fcommon\fR instead. +Compiling with \fB\-fno\-common\fR is useful on targets for which +it provides better performance, or if you wish to verify that the +program will work on other systems which always treat uninitialized +variable declarations this way. +.IP "\fB\-fno\-ident\fR" 4 +.IX Item "-fno-ident" +Ignore the \fB#ident\fR directive. +.IP "\fB\-finhibit\-size\-directive\fR" 4 +.IX Item "-finhibit-size-directive" +Don't output a \f(CW\*(C`.size\*(C'\fR assembler directive, or anything else that +would cause trouble if the function is split in the middle, and the +two halves are placed at locations far apart in memory. This option is +used when compiling \fIcrtstuff.c\fR; you should not need to use it +for anything else. +.IP "\fB\-fverbose\-asm\fR" 4 +.IX Item "-fverbose-asm" +Put extra commentary information in the generated assembly code to +make it more readable. This option is generally only of use to those +who actually need to read the generated assembly code (perhaps while +debugging the compiler itself). +.Sp +\&\fB\-fno\-verbose\-asm\fR, the default, causes the +extra information to be omitted and is useful when comparing two assembler +files. +.IP "\fB\-frecord\-gcc\-switches\fR" 4 +.IX Item "-frecord-gcc-switches" +This switch causes the command line that was used to invoke the +compiler to be recorded into the object file that is being created. +This switch is only implemented on some targets and the exact format +of the recording is target and binary file format dependent, but it +usually takes the form of a section containing \s-1ASCII\s0 text. This +switch is related to the \fB\-fverbose\-asm\fR switch, but that +switch only records information in the assembler output file as +comments, so it never reaches the object file. +.IP "\fB\-fpic\fR" 4 +.IX Item "-fpic" +Generate position-independent code (\s-1PIC\s0) suitable for use in a shared +library, if supported for the target machine. Such code accesses all +constant addresses through a global offset table (\s-1GOT\s0). The dynamic +loader resolves the \s-1GOT\s0 entries when the program starts (the dynamic +loader is not part of \s-1GCC\s0; it is part of the operating system). If +the \s-1GOT\s0 size for the linked executable exceeds a machine-specific +maximum size, you get an error message from the linker indicating that +\&\fB\-fpic\fR does not work; in that case, recompile with \fB\-fPIC\fR +instead. (These maximums are 8k on the \s-1SPARC\s0 and 32k +on the m68k and \s-1RS/6000\s0. The 386 has no such limit.) +.Sp +Position-independent code requires special support, and therefore works +only on certain machines. For the 386, \s-1GCC\s0 supports \s-1PIC\s0 for System V +but not for the Sun 386i. Code generated for the \s-1IBM\s0 \s-1RS/6000\s0 is always +position-independent. +.Sp +When this flag is set, the macros \f(CW\*(C`_\|_pic_\|_\*(C'\fR and \f(CW\*(C`_\|_PIC_\|_\*(C'\fR +are defined to 1. +.IP "\fB\-fPIC\fR" 4 +.IX Item "-fPIC" +If supported for the target machine, emit position-independent code, +suitable for dynamic linking and avoiding any limit on the size of the +global offset table. This option makes a difference on the m68k, +PowerPC and \s-1SPARC\s0. +.Sp +Position-independent code requires special support, and therefore works +only on certain machines. +.Sp +When this flag is set, the macros \f(CW\*(C`_\|_pic_\|_\*(C'\fR and \f(CW\*(C`_\|_PIC_\|_\*(C'\fR +are defined to 2. +.IP "\fB\-fpie\fR" 4 +.IX Item "-fpie" +.PD 0 +.IP "\fB\-fPIE\fR" 4 +.IX Item "-fPIE" +.PD +These options are similar to \fB\-fpic\fR and \fB\-fPIC\fR, but +generated position independent code can be only linked into executables. +Usually these options are used when \fB\-pie\fR \s-1GCC\s0 option will be +used during linking. +.Sp +\&\fB\-fpie\fR and \fB\-fPIE\fR both define the macros +\&\f(CW\*(C`_\|_pie_\|_\*(C'\fR and \f(CW\*(C`_\|_PIE_\|_\*(C'\fR. The macros have the value 1 +for \fB\-fpie\fR and 2 for \fB\-fPIE\fR. +.IP "\fB\-fno\-jump\-tables\fR" 4 +.IX Item "-fno-jump-tables" +Do not use jump tables for switch statements even where it would be +more efficient than other code generation strategies. This option is +of use in conjunction with \fB\-fpic\fR or \fB\-fPIC\fR for +building code which forms part of a dynamic linker and cannot +reference the address of a jump table. On some targets, jump tables +do not require a \s-1GOT\s0 and this option is not needed. +.IP "\fB\-ffixed\-\fR\fIreg\fR" 4 +.IX Item "-ffixed-reg" +Treat the register named \fIreg\fR as a fixed register; generated code +should never refer to it (except perhaps as a stack pointer, frame +pointer or in some other fixed role). +.Sp +\&\fIreg\fR must be the name of a register. The register names accepted +are machine-specific and are defined in the \f(CW\*(C`REGISTER_NAMES\*(C'\fR +macro in the machine description macro file. +.Sp +This flag does not have a negative form, because it specifies a +three-way choice. +.IP "\fB\-fcall\-used\-\fR\fIreg\fR" 4 +.IX Item "-fcall-used-reg" +Treat the register named \fIreg\fR as an allocable register that is +clobbered by function calls. It may be allocated for temporaries or +variables that do not live across a call. Functions compiled this way +will not save and restore the register \fIreg\fR. +.Sp +It is an error to used this flag with the frame pointer or stack pointer. +Use of this flag for other registers that have fixed pervasive roles in +the machine's execution model will produce disastrous results. +.Sp +This flag does not have a negative form, because it specifies a +three-way choice. +.IP "\fB\-fcall\-saved\-\fR\fIreg\fR" 4 +.IX Item "-fcall-saved-reg" +Treat the register named \fIreg\fR as an allocable register saved by +functions. It may be allocated even for temporaries or variables that +live across a call. Functions compiled this way will save and restore +the register \fIreg\fR if they use it. +.Sp +It is an error to used this flag with the frame pointer or stack pointer. +Use of this flag for other registers that have fixed pervasive roles in +the machine's execution model will produce disastrous results. +.Sp +A different sort of disaster will result from the use of this flag for +a register in which function values may be returned. +.Sp +This flag does not have a negative form, because it specifies a +three-way choice. +.IP "\fB\-fpack\-struct[=\fR\fIn\fR\fB]\fR" 4 +.IX Item "-fpack-struct[=n]" +Without a value specified, pack all structure members together without +holes. When a value is specified (which must be a small power of two), pack +structure members according to this value, representing the maximum +alignment (that is, objects with default alignment requirements larger than +this will be output potentially unaligned at the next fitting location. +.Sp +\&\fBWarning:\fR the \fB\-fpack\-struct\fR switch causes \s-1GCC\s0 to generate +code that is not binary compatible with code generated without that switch. +Additionally, it makes the code suboptimal. +Use it to conform to a non-default application binary interface. +.IP "\fB\-finstrument\-functions\fR" 4 +.IX Item "-finstrument-functions" +Generate instrumentation calls for entry and exit to functions. Just +after function entry and just before function exit, the following +profiling functions will be called with the address of the current +function and its call site. (On some platforms, +\&\f(CW\*(C`_\|_builtin_return_address\*(C'\fR does not work beyond the current +function, so the call site information may not be available to the +profiling functions otherwise.) +.Sp +.Vb 4 +\& void _\|_cyg_profile_func_enter (void *this_fn, +\& void *call_site); +\& void _\|_cyg_profile_func_exit (void *this_fn, +\& void *call_site); +.Ve +.Sp +The first argument is the address of the start of the current function, +which may be looked up exactly in the symbol table. +.Sp +This instrumentation is also done for functions expanded inline in other +functions. The profiling calls will indicate where, conceptually, the +inline function is entered and exited. This means that addressable +versions of such functions must be available. If all your uses of a +function are expanded inline, this may mean an additional expansion of +code size. If you use \fBextern inline\fR in your C code, an +addressable version of such functions must be provided. (This is +normally the case anyways, but if you get lucky and the optimizer always +expands the functions inline, you might have gotten away without +providing static copies.) +.Sp +A function may be given the attribute \f(CW\*(C`no_instrument_function\*(C'\fR, in +which case this instrumentation will not be done. This can be used, for +example, for the profiling functions listed above, high-priority +interrupt routines, and any functions from which the profiling functions +cannot safely be called (perhaps signal handlers, if the profiling +routines generate output or allocate memory). +.IP "\fB\-finstrument\-functions\-exclude\-file\-list=\fR\fIfile\fR\fB,\fR\fIfile\fR\fB,...\fR" 4 +.IX Item "-finstrument-functions-exclude-file-list=file,file,..." +Set the list of functions that are excluded from instrumentation (see +the description of \f(CW\*(C`\-finstrument\-functions\*(C'\fR). If the file that +contains a function definition matches with one of \fIfile\fR, then +that function is not instrumented. The match is done on substrings: +if the \fIfile\fR parameter is a substring of the file name, it is +considered to be a match. +.Sp +For example: +.Sp +.Vb 1 +\& \-finstrument\-functions\-exclude\-file\-list=/bits/stl,include/sys +.Ve +.Sp +will exclude any inline function defined in files whose pathnames +contain \f(CW\*(C`/bits/stl\*(C'\fR or \f(CW\*(C`include/sys\*(C'\fR. +.Sp +If, for some reason, you want to include letter \f(CW\*(Aq,\*(Aq\fR in one of +\&\fIsym\fR, write \f(CW\*(Aq,\*(Aq\fR. For example, +\&\f(CW\*(C`\-finstrument\-functions\-exclude\-file\-list=\*(Aq,,tmp\*(Aq\*(C'\fR +(note the single quote surrounding the option). +.IP "\fB\-finstrument\-functions\-exclude\-function\-list=\fR\fIsym\fR\fB,\fR\fIsym\fR\fB,...\fR" 4 +.IX Item "-finstrument-functions-exclude-function-list=sym,sym,..." +This is similar to \f(CW\*(C`\-finstrument\-functions\-exclude\-file\-list\*(C'\fR, +but this option sets the list of function names to be excluded from +instrumentation. The function name to be matched is its user-visible +name, such as \f(CW\*(C`vector<int> blah(const vector<int> &)\*(C'\fR, not the +internal mangled name (e.g., \f(CW\*(C`_Z4blahRSt6vectorIiSaIiEE\*(C'\fR). The +match is done on substrings: if the \fIsym\fR parameter is a substring +of the function name, it is considered to be a match. For C99 and \*(C+ +extended identifiers, the function name must be given in \s-1UTF\-8\s0, not +using universal character names. +.IP "\fB\-fstack\-check\fR" 4 +.IX Item "-fstack-check" +Generate code to verify that you do not go beyond the boundary of the +stack. You should specify this flag if you are running in an +environment with multiple threads, but only rarely need to specify it in +a single-threaded environment since stack overflow is automatically +detected on nearly all systems if there is only one stack. +.Sp +Note that this switch does not actually cause checking to be done; the +operating system or the language runtime must do that. The switch causes +generation of code to ensure that they see the stack being extended. +.Sp +You can additionally specify a string parameter: \f(CW\*(C`no\*(C'\fR means no +checking, \f(CW\*(C`generic\*(C'\fR means force the use of old-style checking, +\&\f(CW\*(C`specific\*(C'\fR means use the best checking method and is equivalent +to bare \fB\-fstack\-check\fR. +.Sp +Old-style checking is a generic mechanism that requires no specific +target support in the compiler but comes with the following drawbacks: +.RS 4 +.IP "1." 4 +Modified allocation strategy for large objects: they will always be +allocated dynamically if their size exceeds a fixed threshold. +.IP "2." 4 +Fixed limit on the size of the static frame of functions: when it is +topped by a particular function, stack checking is not reliable and +a warning is issued by the compiler. +.IP "3." 4 +Inefficiency: because of both the modified allocation strategy and the +generic implementation, the performances of the code are hampered. +.RE +.RS 4 +.Sp +Note that old-style stack checking is also the fallback method for +\&\f(CW\*(C`specific\*(C'\fR if no target support has been added in the compiler. +.RE +.IP "\fB\-fstack\-limit\-register=\fR\fIreg\fR" 4 +.IX Item "-fstack-limit-register=reg" +.PD 0 +.IP "\fB\-fstack\-limit\-symbol=\fR\fIsym\fR" 4 +.IX Item "-fstack-limit-symbol=sym" +.IP "\fB\-fno\-stack\-limit\fR" 4 +.IX Item "-fno-stack-limit" +.PD +Generate code to ensure that the stack does not grow beyond a certain value, +either the value of a register or the address of a symbol. If the stack +would grow beyond the value, a signal is raised. For most targets, +the signal is raised before the stack overruns the boundary, so +it is possible to catch the signal without taking special precautions. +.Sp +For instance, if the stack starts at absolute address \fB0x80000000\fR +and grows downwards, you can use the flags +\&\fB\-fstack\-limit\-symbol=_\|_stack_limit\fR and +\&\fB\-Wl,\-\-defsym,_\|_stack_limit=0x7ffe0000\fR to enforce a stack limit +of 128KB. Note that this may only work with the \s-1GNU\s0 linker. +.IP "\fB\-fsplit\-stack\fR" 4 +.IX Item "-fsplit-stack" +Generate code to automatically split the stack before it overflows. +The resulting program has a discontiguous stack which can only +overflow if the program is unable to allocate any more memory. This +is most useful when running threaded programs, as it is no longer +necessary to calculate a good stack size to use for each thread. This +is currently only implemented for the i386 and x86_64 backends running +GNU/Linux. +.Sp +When code compiled with \fB\-fsplit\-stack\fR calls code compiled +without \fB\-fsplit\-stack\fR, there may not be much stack space +available for the latter code to run. If compiling all code, +including library code, with \fB\-fsplit\-stack\fR is not an option, +then the linker can fix up these calls so that the code compiled +without \fB\-fsplit\-stack\fR always has a large stack. Support for +this is implemented in the gold linker in \s-1GNU\s0 binutils release 2.21 +and later. +.IP "\fB\-fleading\-underscore\fR" 4 +.IX Item "-fleading-underscore" +This option and its counterpart, \fB\-fno\-leading\-underscore\fR, forcibly +change the way C symbols are represented in the object file. One use +is to help link with legacy assembly code. +.Sp +\&\fBWarning:\fR the \fB\-fleading\-underscore\fR switch causes \s-1GCC\s0 to +generate code that is not binary compatible with code generated without that +switch. Use it to conform to a non-default application binary interface. +Not all targets provide complete support for this switch. +.IP "\fB\-ftls\-model=\fR\fImodel\fR" 4 +.IX Item "-ftls-model=model" +Alter the thread-local storage model to be used. +The \fImodel\fR argument should be one of \f(CW\*(C`global\-dynamic\*(C'\fR, +\&\f(CW\*(C`local\-dynamic\*(C'\fR, \f(CW\*(C`initial\-exec\*(C'\fR or \f(CW\*(C`local\-exec\*(C'\fR. +.Sp +The default without \fB\-fpic\fR is \f(CW\*(C`initial\-exec\*(C'\fR; with +\&\fB\-fpic\fR the default is \f(CW\*(C`global\-dynamic\*(C'\fR. +.IP "\fB\-fvisibility=\fR\fIdefault|internal|hidden|protected\fR" 4 +.IX Item "-fvisibility=default|internal|hidden|protected" +Set the default \s-1ELF\s0 image symbol visibility to the specified option\-\-\-all +symbols will be marked with this unless overridden within the code. +Using this feature can very substantially improve linking and +load times of shared object libraries, produce more optimized +code, provide near-perfect \s-1API\s0 export and prevent symbol clashes. +It is \fBstrongly\fR recommended that you use this in any shared objects +you distribute. +.Sp +Despite the nomenclature, \f(CW\*(C`default\*(C'\fR always means public; i.e., +available to be linked against from outside the shared object. +\&\f(CW\*(C`protected\*(C'\fR and \f(CW\*(C`internal\*(C'\fR are pretty useless in real-world +usage so the only other commonly used option will be \f(CW\*(C`hidden\*(C'\fR. +The default if \fB\-fvisibility\fR isn't specified is +\&\f(CW\*(C`default\*(C'\fR, i.e., make every +symbol public\-\-\-this causes the same behavior as previous versions of +\&\s-1GCC\s0. +.Sp +A good explanation of the benefits offered by ensuring \s-1ELF\s0 +symbols have the correct visibility is given by \*(L"How To Write +Shared Libraries\*(R" by Ulrich Drepper (which can be found at +<\fBhttp://people.redhat.com/~drepper/\fR>)\-\-\-however a superior +solution made possible by this option to marking things hidden when +the default is public is to make the default hidden and mark things +public. This is the norm with \s-1DLL\s0's on Windows and with \fB\-fvisibility=hidden\fR +and \f(CW\*(C`_\|_attribute_\|_ ((visibility("default")))\*(C'\fR instead of +\&\f(CW\*(C`_\|_declspec(dllexport)\*(C'\fR you get almost identical semantics with +identical syntax. This is a great boon to those working with +cross-platform projects. +.Sp +For those adding visibility support to existing code, you may find +\&\fB#pragma \s-1GCC\s0 visibility\fR of use. This works by you enclosing +the declarations you wish to set visibility for with (for example) +\&\fB#pragma \s-1GCC\s0 visibility push(hidden)\fR and +\&\fB#pragma \s-1GCC\s0 visibility pop\fR. +Bear in mind that symbol visibility should be viewed \fBas +part of the \s-1API\s0 interface contract\fR and thus all new code should +always specify visibility when it is not the default; i.e., declarations +only for use within the local \s-1DSO\s0 should \fBalways\fR be marked explicitly +as hidden as so to avoid \s-1PLT\s0 indirection overheads\-\-\-making this +abundantly clear also aids readability and self-documentation of the code. +Note that due to \s-1ISO\s0 \*(C+ specification requirements, operator new and +operator delete must always be of default visibility. +.Sp +Be aware that headers from outside your project, in particular system +headers and headers from any other library you use, may not be +expecting to be compiled with visibility other than the default. You +may need to explicitly say \fB#pragma \s-1GCC\s0 visibility push(default)\fR +before including any such headers. +.Sp +\&\fBextern\fR declarations are not affected by \fB\-fvisibility\fR, so +a lot of code can be recompiled with \fB\-fvisibility=hidden\fR with +no modifications. However, this means that calls to \fBextern\fR +functions with no explicit visibility will use the \s-1PLT\s0, so it is more +effective to use \fB_\|_attribute ((visibility))\fR and/or +\&\fB#pragma \s-1GCC\s0 visibility\fR to tell the compiler which \fBextern\fR +declarations should be treated as hidden. +.Sp +Note that \fB\-fvisibility\fR does affect \*(C+ vague linkage +entities. This means that, for instance, an exception class that will +be thrown between DSOs must be explicitly marked with default +visibility so that the \fBtype_info\fR nodes will be unified between +the DSOs. +.Sp +An overview of these techniques, their benefits and how to use them +is at <\fBhttp://gcc.gnu.org/wiki/Visibility\fR>. +.IP "\fB\-fstrict\-volatile\-bitfields\fR" 4 +.IX Item "-fstrict-volatile-bitfields" +This option should be used if accesses to volatile bitfields (or other +structure fields, although the compiler usually honors those types +anyway) should use a single access of the width of the +field's type, aligned to a natural alignment if possible. For +example, targets with memory-mapped peripheral registers might require +all such accesses to be 16 bits wide; with this flag the user could +declare all peripheral bitfields as \*(L"unsigned short\*(R" (assuming short +is 16 bits on these targets) to force \s-1GCC\s0 to use 16 bit accesses +instead of, perhaps, a more efficient 32 bit access. +.Sp +If this option is disabled, the compiler will use the most efficient +instruction. In the previous example, that might be a 32\-bit load +instruction, even though that will access bytes that do not contain +any portion of the bitfield, or memory-mapped registers unrelated to +the one being updated. +.Sp +If the target requires strict alignment, and honoring the field +type would require violating this alignment, a warning is issued. +If the field has \f(CW\*(C`packed\*(C'\fR attribute, the access is done without +honoring the field type. If the field doesn't have \f(CW\*(C`packed\*(C'\fR +attribute, the access is done honoring the field type. In both cases, +\&\s-1GCC\s0 assumes that the user knows something about the target hardware +that it is unaware of. +.Sp +The default value of this option is determined by the application binary +interface for the target processor. +.SH "ENVIRONMENT" +.IX Header "ENVIRONMENT" +This section describes several environment variables that affect how \s-1GCC\s0 +operates. Some of them work by specifying directories or prefixes to use +when searching for various kinds of files. Some are used to specify other +aspects of the compilation environment. +.PP +Note that you can also specify places to search using options such as +\&\fB\-B\fR, \fB\-I\fR and \fB\-L\fR. These +take precedence over places specified using environment variables, which +in turn take precedence over those specified by the configuration of \s-1GCC\s0. +.IP "\fB\s-1LANG\s0\fR" 4 +.IX Item "LANG" +.PD 0 +.IP "\fB\s-1LC_CTYPE\s0\fR" 4 +.IX Item "LC_CTYPE" +.IP "\fB\s-1LC_MESSAGES\s0\fR" 4 +.IX Item "LC_MESSAGES" +.IP "\fB\s-1LC_ALL\s0\fR" 4 +.IX Item "LC_ALL" +.PD +These environment variables control the way that \s-1GCC\s0 uses +localization information that allow \s-1GCC\s0 to work with different +national conventions. \s-1GCC\s0 inspects the locale categories +\&\fB\s-1LC_CTYPE\s0\fR and \fB\s-1LC_MESSAGES\s0\fR if it has been configured to do +so. These locale categories can be set to any value supported by your +installation. A typical value is \fBen_GB.UTF\-8\fR for English in the United +Kingdom encoded in \s-1UTF\-8\s0. +.Sp +The \fB\s-1LC_CTYPE\s0\fR environment variable specifies character +classification. \s-1GCC\s0 uses it to determine the character boundaries in +a string; this is needed for some multibyte encodings that contain quote +and escape characters that would otherwise be interpreted as a string +end or escape. +.Sp +The \fB\s-1LC_MESSAGES\s0\fR environment variable specifies the language to +use in diagnostic messages. +.Sp +If the \fB\s-1LC_ALL\s0\fR environment variable is set, it overrides the value +of \fB\s-1LC_CTYPE\s0\fR and \fB\s-1LC_MESSAGES\s0\fR; otherwise, \fB\s-1LC_CTYPE\s0\fR +and \fB\s-1LC_MESSAGES\s0\fR default to the value of the \fB\s-1LANG\s0\fR +environment variable. If none of these variables are set, \s-1GCC\s0 +defaults to traditional C English behavior. +.IP "\fB\s-1TMPDIR\s0\fR" 4 +.IX Item "TMPDIR" +If \fB\s-1TMPDIR\s0\fR is set, it specifies the directory to use for temporary +files. \s-1GCC\s0 uses temporary files to hold the output of one stage of +compilation which is to be used as input to the next stage: for example, +the output of the preprocessor, which is the input to the compiler +proper. +.IP "\fB\s-1GCC_EXEC_PREFIX\s0\fR" 4 +.IX Item "GCC_EXEC_PREFIX" +If \fB\s-1GCC_EXEC_PREFIX\s0\fR is set, it specifies a prefix to use in the +names of the subprograms executed by the compiler. No slash is added +when this prefix is combined with the name of a subprogram, but you can +specify a prefix that ends with a slash if you wish. +.Sp +If \fB\s-1GCC_EXEC_PREFIX\s0\fR is not set, \s-1GCC\s0 will attempt to figure out +an appropriate prefix to use based on the pathname it was invoked with. +.Sp +If \s-1GCC\s0 cannot find the subprogram using the specified prefix, it +tries looking in the usual places for the subprogram. +.Sp +The default value of \fB\s-1GCC_EXEC_PREFIX\s0\fR is +\&\fI\fIprefix\fI/lib/gcc/\fR where \fIprefix\fR is the prefix to +the installed compiler. In many cases \fIprefix\fR is the value +of \f(CW\*(C`prefix\*(C'\fR when you ran the \fIconfigure\fR script. +.Sp +Other prefixes specified with \fB\-B\fR take precedence over this prefix. +.Sp +This prefix is also used for finding files such as \fIcrt0.o\fR that are +used for linking. +.Sp +In addition, the prefix is used in an unusual way in finding the +directories to search for header files. For each of the standard +directories whose name normally begins with \fB/usr/local/lib/gcc\fR +(more precisely, with the value of \fB\s-1GCC_INCLUDE_DIR\s0\fR), \s-1GCC\s0 tries +replacing that beginning with the specified prefix to produce an +alternate directory name. Thus, with \fB\-Bfoo/\fR, \s-1GCC\s0 will search +\&\fIfoo/bar\fR where it would normally search \fI/usr/local/lib/bar\fR. +These alternate directories are searched first; the standard directories +come next. If a standard directory begins with the configured +\&\fIprefix\fR then the value of \fIprefix\fR is replaced by +\&\fB\s-1GCC_EXEC_PREFIX\s0\fR when looking for header files. +.IP "\fB\s-1COMPILER_PATH\s0\fR" 4 +.IX Item "COMPILER_PATH" +The value of \fB\s-1COMPILER_PATH\s0\fR is a colon-separated list of +directories, much like \fB\s-1PATH\s0\fR. \s-1GCC\s0 tries the directories thus +specified when searching for subprograms, if it can't find the +subprograms using \fB\s-1GCC_EXEC_PREFIX\s0\fR. +.IP "\fB\s-1LIBRARY_PATH\s0\fR" 4 +.IX Item "LIBRARY_PATH" +The value of \fB\s-1LIBRARY_PATH\s0\fR is a colon-separated list of +directories, much like \fB\s-1PATH\s0\fR. When configured as a native compiler, +\&\s-1GCC\s0 tries the directories thus specified when searching for special +linker files, if it can't find them using \fB\s-1GCC_EXEC_PREFIX\s0\fR. Linking +using \s-1GCC\s0 also uses these directories when searching for ordinary +libraries for the \fB\-l\fR option (but directories specified with +\&\fB\-L\fR come first). +.IP "\fB\s-1LANG\s0\fR" 4 +.IX Item "LANG" +This variable is used to pass locale information to the compiler. One way in +which this information is used is to determine the character set to be used +when character literals, string literals and comments are parsed in C and \*(C+. +When the compiler is configured to allow multibyte characters, +the following values for \fB\s-1LANG\s0\fR are recognized: +.RS 4 +.IP "\fBC\-JIS\fR" 4 +.IX Item "C-JIS" +Recognize \s-1JIS\s0 characters. +.IP "\fBC\-SJIS\fR" 4 +.IX Item "C-SJIS" +Recognize \s-1SJIS\s0 characters. +.IP "\fBC\-EUCJP\fR" 4 +.IX Item "C-EUCJP" +Recognize \s-1EUCJP\s0 characters. +.RE +.RS 4 +.Sp +If \fB\s-1LANG\s0\fR is not defined, or if it has some other value, then the +compiler will use mblen and mbtowc as defined by the default locale to +recognize and translate multibyte characters. +.RE +.PP +Some additional environments variables affect the behavior of the +preprocessor. +.IP "\fB\s-1CPATH\s0\fR" 4 +.IX Item "CPATH" +.PD 0 +.IP "\fBC_INCLUDE_PATH\fR" 4 +.IX Item "C_INCLUDE_PATH" +.IP "\fB\s-1CPLUS_INCLUDE_PATH\s0\fR" 4 +.IX Item "CPLUS_INCLUDE_PATH" +.IP "\fB\s-1OBJC_INCLUDE_PATH\s0\fR" 4 +.IX Item "OBJC_INCLUDE_PATH" +.PD +Each variable's value is a list of directories separated by a special +character, much like \fB\s-1PATH\s0\fR, in which to look for header files. +The special character, \f(CW\*(C`PATH_SEPARATOR\*(C'\fR, is target-dependent and +determined at \s-1GCC\s0 build time. For Microsoft Windows-based targets it is a +semicolon, and for almost all other targets it is a colon. +.Sp +\&\fB\s-1CPATH\s0\fR specifies a list of directories to be searched as if +specified with \fB\-I\fR, but after any paths given with \fB\-I\fR +options on the command line. This environment variable is used +regardless of which language is being preprocessed. +.Sp +The remaining environment variables apply only when preprocessing the +particular language indicated. Each specifies a list of directories +to be searched as if specified with \fB\-isystem\fR, but after any +paths given with \fB\-isystem\fR options on the command line. +.Sp +In all these variables, an empty element instructs the compiler to +search its current working directory. Empty elements can appear at the +beginning or end of a path. For instance, if the value of +\&\fB\s-1CPATH\s0\fR is \f(CW\*(C`:/special/include\*(C'\fR, that has the same +effect as \fB\-I.\ \-I/special/include\fR. +.IP "\fB\s-1DEPENDENCIES_OUTPUT\s0\fR" 4 +.IX Item "DEPENDENCIES_OUTPUT" +If this variable is set, its value specifies how to output +dependencies for Make based on the non-system header files processed +by the compiler. System header files are ignored in the dependency +output. +.Sp +The value of \fB\s-1DEPENDENCIES_OUTPUT\s0\fR can be just a file name, in +which case the Make rules are written to that file, guessing the target +name from the source file name. Or the value can have the form +\&\fIfile\fR\fB \fR\fItarget\fR, in which case the rules are written to +file \fIfile\fR using \fItarget\fR as the target name. +.Sp +In other words, this environment variable is equivalent to combining +the options \fB\-MM\fR and \fB\-MF\fR, +with an optional \fB\-MT\fR switch too. +.IP "\fB\s-1SUNPRO_DEPENDENCIES\s0\fR" 4 +.IX Item "SUNPRO_DEPENDENCIES" +This variable is the same as \fB\s-1DEPENDENCIES_OUTPUT\s0\fR (see above), +except that system header files are not ignored, so it implies +\&\fB\-M\fR rather than \fB\-MM\fR. However, the dependence on the +main input file is omitted. +.SH "BUGS" +.IX Header "BUGS" +For instructions on reporting bugs, see +<\fBhttp://gcc.gnu.org/bugs.html\fR>. +.SH "FOOTNOTES" +.IX Header "FOOTNOTES" +.IP "1." 4 +On some systems, \fBgcc \-shared\fR +needs to build supplementary stub code for constructors to work. On +multi-libbed systems, \fBgcc \-shared\fR must select the correct support +libraries to link against. Failing to supply the correct flags may lead +to subtle defects. Supplying them in cases where they are not necessary +is innocuous. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fIgpl\fR\|(7), \fIgfdl\fR\|(7), \fIfsf\-funding\fR\|(7), +\&\fIcpp\fR\|(1), \fIgcov\fR\|(1), \fIas\fR\|(1), \fIld\fR\|(1), \fIgdb\fR\|(1), \fIadb\fR\|(1), \fIdbx\fR\|(1), \fIsdb\fR\|(1) +and the Info entries for \fIgcc\fR, \fIcpp\fR, \fIas\fR, +\&\fIld\fR, \fIbinutils\fR and \fIgdb\fR. +.SH "AUTHOR" +.IX Header "AUTHOR" +See the Info entry for \fBgcc\fR, or +<\fBhttp://gcc.gnu.org/onlinedocs/gcc/Contributors.html\fR>, +for contributors to \s-1GCC\s0. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, +1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 or +any later version published by the Free Software Foundation; with the +Invariant Sections being \*(L"\s-1GNU\s0 General Public License\*(R" and \*(L"Funding +Free Software\*(R", the Front-Cover texts being (a) (see below), and with +the Back-Cover Texts being (b) (see below). A copy of the license is +included in the \fIgfdl\fR\|(7) man page. +.PP +(a) The \s-1FSF\s0's Front-Cover Text is: +.PP +.Vb 1 +\& A GNU Manual +.Ve +.PP +(b) The \s-1FSF\s0's Back-Cover Text is: +.PP +.Vb 3 +\& You have freedom to copy and modify this GNU Manual, like GNU +\& software. Copies published by the Free Software Foundation raise +\& funds for GNU development. +.Ve diff --git a/share/man/man1/arm-eabi-gcov.1 b/share/man/man1/arm-eabi-gcov.1 new file mode 100644 index 0000000..579c0f3 --- /dev/null +++ b/share/man/man1/arm-eabi-gcov.1 @@ -0,0 +1,681 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "GCOV 1" +.TH GCOV 1 "2012-01-06" "gcc-4.6.x-google" "GNU" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +gcov \- coverage testing tool +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +gcov [\fB\-v\fR|\fB\-\-version\fR] [\fB\-h\fR|\fB\-\-help\fR] + [\fB\-a\fR|\fB\-\-all\-blocks\fR] + [\fB\-b\fR|\fB\-\-branch\-probabilities\fR] + [\fB\-c\fR|\fB\-\-branch\-counts\fR] + [\fB\-m\fR|\fB\-\-pmu\-profile\fR] + [\fB\-n\fR|\fB\-\-no\-output\fR] + [\fB\-l\fR|\fB\-\-long\-file\-names\fR] + [\fB\-p\fR|\fB\-\-preserve\-paths\fR] + [\fB\-q\fR|\fB\-\-pmu_profile\-path\fR] + [\fB\-f\fR|\fB\-\-function\-summaries\fR] + [\fB\-o\fR|\fB\-\-object\-directory\fR \fIdirectory|file\fR] \fIsourcefiles\fR + [\fB\-u\fR|\fB\-\-unconditional\-branches\fR] + [\fB\-i\fR|\fB\-\-intermediate\-format\fR] + [\fB\-d\fR|\fB\-\-display\-progress\fR] +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +\&\fBgcov\fR is a test coverage program. Use it in concert with \s-1GCC\s0 +to analyze your programs to help create more efficient, faster running +code and to discover untested parts of your program. You can use +\&\fBgcov\fR as a profiling tool to help discover where your +optimization efforts will best affect your code. You can also use +\&\fBgcov\fR along with the other profiling tool, \fBgprof\fR, to +assess which parts of your code use the greatest amount of computing +time. +.PP +Profiling tools help you analyze your code's performance. Using a +profiler such as \fBgcov\fR or \fBgprof\fR, you can find out some +basic performance statistics, such as: +.IP "\(bu" 4 +how often each line of code executes +.IP "\(bu" 4 +what lines of code are actually executed +.IP "\(bu" 4 +how much computing time each section of code uses +.PP +Once you know these things about how your code works when compiled, you +can look at each module to see which modules should be optimized. +\&\fBgcov\fR helps you determine where to work on optimization. +.PP +Software developers also use coverage testing in concert with +testsuites, to make sure software is actually good enough for a release. +Testsuites can verify that a program works as expected; a coverage +program tests to see how much of the program is exercised by the +testsuite. Developers can then determine what kinds of test cases need +to be added to the testsuites to create both better testing and a better +final product. +.PP +You should compile your code without optimization if you plan to use +\&\fBgcov\fR because the optimization, by combining some lines of code +into one function, may not give you as much information as you need to +look for `hot spots' where the code is using a great deal of computer +time. Likewise, because \fBgcov\fR accumulates statistics by line (at +the lowest resolution), it works best with a programming style that +places only one statement on each line. If you use complicated macros +that expand to loops or to other control structures, the statistics are +less helpful\-\-\-they only report on the line where the macro call +appears. If your complex macros behave like functions, you can replace +them with inline functions to solve this problem. +.PP +\&\fBgcov\fR creates a logfile called \fI\fIsourcefile\fI.gcov\fR which +indicates how many times each line of a source file \fI\fIsourcefile\fI.c\fR +has executed. You can use these logfiles along with \fBgprof\fR to aid +in fine-tuning the performance of your programs. \fBgprof\fR gives +timing information you can use along with the information you get from +\&\fBgcov\fR. +.PP +\&\fBgcov\fR works only on code compiled with \s-1GCC\s0. It is not +compatible with any other profiling or test coverage mechanism. +.SH "OPTIONS" +.IX Header "OPTIONS" +.IP "\fB\-h\fR" 4 +.IX Item "-h" +.PD 0 +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +.PD +Display help about using \fBgcov\fR (on the standard output), and +exit without doing any further processing. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +.PD 0 +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +.PD +Display the \fBgcov\fR version number (on the standard output), +and exit without doing any further processing. +.IP "\fB\-a\fR" 4 +.IX Item "-a" +.PD 0 +.IP "\fB\-\-all\-blocks\fR" 4 +.IX Item "--all-blocks" +.PD +Write individual execution counts for every basic block. Normally gcov +outputs execution counts only for the main blocks of a line. With this +option you can determine if blocks within a single line are not being +executed. +.IP "\fB\-b\fR" 4 +.IX Item "-b" +.PD 0 +.IP "\fB\-\-branch\-probabilities\fR" 4 +.IX Item "--branch-probabilities" +.PD +Write branch frequencies to the output file, and write branch summary +info to the standard output. This option allows you to see how often +each branch in your program was taken. Unconditional branches will not +be shown, unless the \fB\-u\fR option is given. +.IP "\fB\-c\fR" 4 +.IX Item "-c" +.PD 0 +.IP "\fB\-\-branch\-counts\fR" 4 +.IX Item "--branch-counts" +.PD +Write branch frequencies as the number of branches taken, rather than +the percentage of branches taken. +.IP "\fB\-m\fR" 4 +.IX Item "-m" +.PD 0 +.IP "\fB\-\-pmu\-profile\fR" 4 +.IX Item "--pmu-profile" +.PD +Output the additional \s-1PMU\s0 profile information if available. +.IP "\fB\-q\fR" 4 +.IX Item "-q" +.PD 0 +.IP "\fB\-\-pmu_profile\-path\fR" 4 +.IX Item "--pmu_profile-path" +.PD +\&\s-1PMU\s0 profile path (default \fIpmuprofile.gcda\fR). +.IP "\fB\-n\fR" 4 +.IX Item "-n" +.PD 0 +.IP "\fB\-\-no\-output\fR" 4 +.IX Item "--no-output" +.PD +Do not create the \fBgcov\fR output file. +.IP "\fB\-l\fR" 4 +.IX Item "-l" +.PD 0 +.IP "\fB\-\-long\-file\-names\fR" 4 +.IX Item "--long-file-names" +.PD +Create long file names for included source files. For example, if the +header file \fIx.h\fR contains code, and was included in the file +\&\fIa.c\fR, then running \fBgcov\fR on the file \fIa.c\fR will produce +an output file called \fIa.c##x.h.gcov\fR instead of \fIx.h.gcov\fR. +This can be useful if \fIx.h\fR is included in multiple source +files. If you use the \fB\-p\fR option, both the including and +included file names will be complete path names. +.IP "\fB\-p\fR" 4 +.IX Item "-p" +.PD 0 +.IP "\fB\-\-preserve\-paths\fR" 4 +.IX Item "--preserve-paths" +.PD +Preserve complete path information in the names of generated +\&\fI.gcov\fR files. Without this option, just the filename component is +used. With this option, all directories are used, with \fB/\fR characters +translated to \fB#\fR characters, \fI.\fR directory components +removed and \fI..\fR +components renamed to \fB^\fR. This is useful if sourcefiles are in several +different directories. It also affects the \fB\-l\fR option. +.IP "\fB\-f\fR" 4 +.IX Item "-f" +.PD 0 +.IP "\fB\-\-function\-summaries\fR" 4 +.IX Item "--function-summaries" +.PD +Output summaries for each function in addition to the file level summary. +.IP "\fB\-o\fR \fIdirectory|file\fR" 4 +.IX Item "-o directory|file" +.PD 0 +.IP "\fB\-\-object\-directory\fR \fIdirectory\fR" 4 +.IX Item "--object-directory directory" +.IP "\fB\-\-object\-file\fR \fIfile\fR" 4 +.IX Item "--object-file file" +.PD +Specify either the directory containing the gcov data files, or the +object path name. The \fI.gcno\fR, and +\&\fI.gcda\fR data files are searched for using this option. If a directory +is specified, the data files are in that directory and named after the +source file name, without its extension. If a file is specified here, +the data files are named after that file, without its extension. If this +option is not supplied, it defaults to the current directory. +.IP "\fB\-u\fR" 4 +.IX Item "-u" +.PD 0 +.IP "\fB\-\-unconditional\-branches\fR" 4 +.IX Item "--unconditional-branches" +.PD +When branch probabilities are given, include those of unconditional branches. +Unconditional branches are normally not interesting. +.IP "\fB\-d\fR" 4 +.IX Item "-d" +.PD 0 +.IP "\fB\-\-display\-progress\fR" 4 +.IX Item "--display-progress" +.PD +Display the progress on the standard output. +.IP "\fB\-i\fR" 4 +.IX Item "-i" +.PD 0 +.IP "\fB\-\-intermediate\-format\fR" 4 +.IX Item "--intermediate-format" +.PD +Output gcov file in an intermediate text format that can be used by +\&\fBlcov\fR or other applications. It will output a single *.gcov file per +*.gcda file. No source code is required. +.Sp +The format of the intermediate \fI.gcov\fR file is plain text with +one entry per line +.Sp +.Vb 5 +\& SF:<source_file_name> +\& FN:<line_number>,<function_name> +\& FNDA:<execution_count>,<function_name> +\& BA:<line_num>,<branch_coverage_type> +\& DA:<line number>,<execution_count> +\& +\& Where the <branch_coverage_type> is +\& 0 (Branch not executed) +\& 1 (Branch executed, but not taken) +\& 2 (Branch executed and taken) +\& +\& There can be multiple SF entries in an intermediate gcov file. All +\& entries following SF pertain to that source file until the next SF +\& entry. +.Ve +.PP +\&\fBgcov\fR should be run with the current directory the same as that +when you invoked the compiler. Otherwise it will not be able to locate +the source files. \fBgcov\fR produces files called +\&\fI\fImangledname\fI.gcov\fR in the current directory. These contain +the coverage information of the source file they correspond to. +One \fI.gcov\fR file is produced for each source file containing code, +which was compiled to produce the data files. The \fImangledname\fR part +of the output file name is usually simply the source file name, but can +be something more complicated if the \fB\-l\fR or \fB\-p\fR options are +given. Refer to those options for details. +.PP +The \fI.gcov\fR files contain the \fB:\fR separated fields along with +program source code. The format is +.PP +.Vb 1 +\& <execution_count>:<line_number>:<source line text> +.Ve +.PP +Additional block information may succeed each line, when requested by +command line option. The \fIexecution_count\fR is \fB\-\fR for lines +containing no code and \fB#####\fR for lines which were never executed. +Some lines of information at the start have \fIline_number\fR of zero. +.PP +The preamble lines are of the form +.PP +.Vb 1 +\& \-:0:<tag>:<value> +.Ve +.PP +The ordering and number of these preamble lines will be augmented as +\&\fBgcov\fR development progresses \-\-\- do not rely on them remaining +unchanged. Use \fItag\fR to locate a particular preamble line. +.PP +The additional block information is of the form +.PP +.Vb 1 +\& <tag> <information> +.Ve +.PP +The \fIinformation\fR is human readable, but designed to be simple +enough for machine parsing too. +.PP +When printing percentages, 0% and 100% are only printed when the values +are \fIexactly\fR 0% and 100% respectively. Other values which would +conventionally be rounded to 0% or 100% are instead printed as the +nearest non-boundary value. +.PP +When using \fBgcov\fR, you must first compile your program with two +special \s-1GCC\s0 options: \fB\-fprofile\-arcs \-ftest\-coverage\fR. +This tells the compiler to generate additional information needed by +gcov (basically a flow graph of the program) and also includes +additional code in the object files for generating the extra profiling +information needed by gcov. These additional files are placed in the +directory where the object file is located. +.PP +Running the program will cause profile output to be generated. For each +source file compiled with \fB\-fprofile\-arcs\fR, an accompanying +\&\fI.gcda\fR file will be placed in the object file directory. +.PP +Running \fBgcov\fR with your program's source file names as arguments +will now produce a listing of the code along with frequency of execution +for each line. For example, if your program is called \fItmp.c\fR, this +is what you see when you use the basic \fBgcov\fR facility: +.PP +.Vb 5 +\& $ gcc \-fprofile\-arcs \-ftest\-coverage tmp.c +\& $ a.out +\& $ gcov tmp.c +\& 90.00% of 10 source lines executed in file tmp.c +\& Creating tmp.c.gcov. +.Ve +.PP +The file \fItmp.c.gcov\fR contains output from \fBgcov\fR. +Here is a sample: +.PP +.Vb 10 +\& \-: 0:Source:tmp.c +\& \-: 0:Graph:tmp.gcno +\& \-: 0:Data:tmp.gcda +\& \-: 0:Runs:1 +\& \-: 0:Programs:1 +\& \-: 1:#include <stdio.h> +\& \-: 2: +\& \-: 3:int main (void) +\& 1: 4:{ +\& 1: 5: int i, total; +\& \-: 6: +\& 1: 7: total = 0; +\& \-: 8: +\& 11: 9: for (i = 0; i < 10; i++) +\& 10: 10: total += i; +\& \-: 11: +\& 1: 12: if (total != 45) +\& #####: 13: printf ("Failure\en"); +\& \-: 14: else +\& 1: 15: printf ("Success\en"); +\& 1: 16: return 0; +\& \-: 17:} +.Ve +.PP +When you use the \fB\-a\fR option, you will get individual block +counts, and the output looks like this: +.PP +.Vb 10 +\& \-: 0:Source:tmp.c +\& \-: 0:Graph:tmp.gcno +\& \-: 0:Data:tmp.gcda +\& \-: 0:Runs:1 +\& \-: 0:Programs:1 +\& \-: 1:#include <stdio.h> +\& \-: 2: +\& \-: 3:int main (void) +\& 1: 4:{ +\& 1: 4\-block 0 +\& 1: 5: int i, total; +\& \-: 6: +\& 1: 7: total = 0; +\& \-: 8: +\& 11: 9: for (i = 0; i < 10; i++) +\& 11: 9\-block 0 +\& 10: 10: total += i; +\& 10: 10\-block 0 +\& \-: 11: +\& 1: 12: if (total != 45) +\& 1: 12\-block 0 +\& #####: 13: printf ("Failure\en"); +\& $$$$$: 13\-block 0 +\& \-: 14: else +\& 1: 15: printf ("Success\en"); +\& 1: 15\-block 0 +\& 1: 16: return 0; +\& 1: 16\-block 0 +\& \-: 17:} +.Ve +.PP +In this mode, each basic block is only shown on one line \*(-- the last +line of the block. A multi-line block will only contribute to the +execution count of that last line, and other lines will not be shown +to contain code, unless previous blocks end on those lines. +The total execution count of a line is shown and subsequent lines show +the execution counts for individual blocks that end on that line. After each +block, the branch and call counts of the block will be shown, if the +\&\fB\-b\fR option is given. +.PP +Because of the way \s-1GCC\s0 instruments calls, a call count can be shown +after a line with no individual blocks. +As you can see, line 13 contains a basic block that was not executed. +.PP +When you use the \fB\-b\fR option, your output looks like this: +.PP +.Vb 6 +\& $ gcov \-b tmp.c +\& 90.00% of 10 source lines executed in file tmp.c +\& 80.00% of 5 branches executed in file tmp.c +\& 80.00% of 5 branches taken at least once in file tmp.c +\& 50.00% of 2 calls executed in file tmp.c +\& Creating tmp.c.gcov. +.Ve +.PP +Here is a sample of a resulting \fItmp.c.gcov\fR file: +.PP +.Vb 10 +\& \-: 0:Source:tmp.c +\& \-: 0:Graph:tmp.gcno +\& \-: 0:Data:tmp.gcda +\& \-: 0:Runs:1 +\& \-: 0:Programs:1 +\& \-: 1:#include <stdio.h> +\& \-: 2: +\& \-: 3:int main (void) +\& function main called 1 returned 1 blocks executed 75% +\& 1: 4:{ +\& 1: 5: int i, total; +\& \-: 6: +\& 1: 7: total = 0; +\& \-: 8: +\& 11: 9: for (i = 0; i < 10; i++) +\& branch 0 taken 91% (fallthrough) +\& branch 1 taken 9% +\& 10: 10: total += i; +\& \-: 11: +\& 1: 12: if (total != 45) +\& branch 0 taken 0% (fallthrough) +\& branch 1 taken 100% +\& #####: 13: printf ("Failure\en"); +\& call 0 never executed +\& \-: 14: else +\& 1: 15: printf ("Success\en"); +\& call 0 called 1 returned 100% +\& 1: 16: return 0; +\& \-: 17:} +.Ve +.PP +For each function, a line is printed showing how many times the function +is called, how many times it returns and what percentage of the +function's blocks were executed. +.PP +For each basic block, a line is printed after the last line of the basic +block describing the branch or call that ends the basic block. There can +be multiple branches and calls listed for a single source line if there +are multiple basic blocks that end on that line. In this case, the +branches and calls are each given a number. There is no simple way to map +these branches and calls back to source constructs. In general, though, +the lowest numbered branch or call will correspond to the leftmost construct +on the source line. +.PP +For a branch, if it was executed at least once, then a percentage +indicating the number of times the branch was taken divided by the +number of times the branch was executed will be printed. Otherwise, the +message \*(L"never executed\*(R" is printed. +.PP +For a call, if it was executed at least once, then a percentage +indicating the number of times the call returned divided by the number +of times the call was executed will be printed. This will usually be +100%, but may be less for functions that call \f(CW\*(C`exit\*(C'\fR or \f(CW\*(C`longjmp\*(C'\fR, +and thus may not return every time they are called. +.PP +The execution counts are cumulative. If the example program were +executed again without removing the \fI.gcda\fR file, the count for the +number of times each line in the source was executed would be added to +the results of the previous run(s). This is potentially useful in +several ways. For example, it could be used to accumulate data over a +number of program runs as part of a test verification suite, or to +provide more accurate long-term information over a large number of +program runs. +.PP +The data in the \fI.gcda\fR files is saved immediately before the program +exits. For each source file compiled with \fB\-fprofile\-arcs\fR, the +profiling code first attempts to read in an existing \fI.gcda\fR file; if +the file doesn't match the executable (differing number of basic block +counts) it will ignore the contents of the file. It then adds in the +new execution counts and finally writes the data to the file. +.SS "Using \fBgcov\fP with \s-1GCC\s0 Optimization" +.IX Subsection "Using gcov with GCC Optimization" +If you plan to use \fBgcov\fR to help optimize your code, you must +first compile your program with two special \s-1GCC\s0 options: +\&\fB\-fprofile\-arcs \-ftest\-coverage\fR. Aside from that, you can use any +other \s-1GCC\s0 options; but if you want to prove that every single line +in your program was executed, you should not compile with optimization +at the same time. On some machines the optimizer can eliminate some +simple code lines by combining them with other lines. For example, code +like this: +.PP +.Vb 4 +\& if (a != b) +\& c = 1; +\& else +\& c = 0; +.Ve +.PP +can be compiled into one instruction on some machines. In this case, +there is no way for \fBgcov\fR to calculate separate execution counts +for each line because there isn't separate code for each line. Hence +the \fBgcov\fR output looks like this if you compiled the program with +optimization: +.PP +.Vb 4 +\& 100: 12:if (a != b) +\& 100: 13: c = 1; +\& 100: 14:else +\& 100: 15: c = 0; +.Ve +.PP +The output shows that this block of code, combined by optimization, +executed 100 times. In one sense this result is correct, because there +was only one instruction representing all four of these lines. However, +the output does not indicate how many times the result was 0 and how +many times the result was 1. +.PP +Inlineable functions can create unexpected line counts. Line counts are +shown for the source code of the inlineable function, but what is shown +depends on where the function is inlined, or if it is not inlined at all. +.PP +If the function is not inlined, the compiler must emit an out of line +copy of the function, in any object file that needs it. If +\&\fIfileA.o\fR and \fIfileB.o\fR both contain out of line bodies of a +particular inlineable function, they will also both contain coverage +counts for that function. When \fIfileA.o\fR and \fIfileB.o\fR are +linked together, the linker will, on many systems, select one of those +out of line bodies for all calls to that function, and remove or ignore +the other. Unfortunately, it will not remove the coverage counters for +the unused function body. Hence when instrumented, all but one use of +that function will show zero counts. +.PP +If the function is inlined in several places, the block structure in +each location might not be the same. For instance, a condition might +now be calculable at compile time in some instances. Because the +coverage of all the uses of the inline function will be shown for the +same source lines, the line counts themselves might seem inconsistent. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fIgpl\fR\|(7), \fIgfdl\fR\|(7), \fIfsf\-funding\fR\|(7), \fIgcc\fR\|(1) and the Info entry for \fIgcc\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1996, 1997, 1999, 2000, 2001, 2002, 2003, 2004, +2005, 2008, 2010 Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 or +any later version published by the Free Software Foundation; with the +Invariant Sections being \*(L"\s-1GNU\s0 General Public License\*(R" and \*(L"Funding +Free Software\*(R", the Front-Cover texts being (a) (see below), and with +the Back-Cover Texts being (b) (see below). A copy of the license is +included in the \fIgfdl\fR\|(7) man page. +.PP +(a) The \s-1FSF\s0's Front-Cover Text is: +.PP +.Vb 1 +\& A GNU Manual +.Ve +.PP +(b) The \s-1FSF\s0's Back-Cover Text is: +.PP +.Vb 3 +\& You have freedom to copy and modify this GNU Manual, like GNU +\& software. Copies published by the Free Software Foundation raise +\& funds for GNU development. +.Ve diff --git a/share/man/man1/arm-eabi-gdb.1 b/share/man/man1/arm-eabi-gdb.1 new file mode 100644 index 0000000..d14eb78 --- /dev/null +++ b/share/man/man1/arm-eabi-gdb.1 @@ -0,0 +1,381 @@ +.\" Copyright (C) 1991, 1999, 2010, 2011 Free Software Foundation, Inc. +.\" See section COPYING for conditions for redistribution +.\" $Id: gdb.1,v 1.4 1999/01/05 00:50:50 jsm Exp $ +.TH gdb 1 "22may2002" "GNU Tools" "GNU Tools" +.SH NAME +gdb \- The GNU Debugger +.SH SYNOPSIS +.na +.TP +.B gdb +.RB "[\|" \-help "\|]" +.RB "[\|" \-nx "\|]" +.RB "[\|" \-q "\|]" +.RB "[\|" \-batch "\|]" +.RB "[\|" \-cd=\c +.I dir\c +\|] +.RB "[\|" \-f "\|]" +.RB "[\|" "\-b\ "\c +.IR bps "\|]" +.RB "[\|" "\-tty="\c +.IR dev "\|]" +.RB "[\|" "\-s "\c +.I symfile\c +\&\|] +.RB "[\|" "\-e "\c +.I prog\c +\&\|] +.RB "[\|" "\-se "\c +.I prog\c +\&\|] +.RB "[\|" "\-c "\c +.I core\c +\&\|] +.RB "[\|" "\-x "\c +.I cmds\c +\&\|] +.RB "[\|" "\-d "\c +.I dir\c +\&\|] +.RB "[\|" \c +.I prog\c +.RB "[\|" \c +.IR core \||\| procID\c +\&\|]\&\|] +.ad b +.SH DESCRIPTION +The purpose of a debugger such as GDB is to allow you to see what is +going on ``inside'' another program while it executes\(em\&or what another +program was doing at the moment it crashed. + +GDB can do four main kinds of things (plus other things in support of +these) to help you catch bugs in the act: + +.TP +\ \ \ \(bu +Start your program, specifying anything that might affect its behavior. + +.TP +\ \ \ \(bu +Make your program stop on specified conditions. + +.TP +\ \ \ \(bu +Examine what has happened, when your program has stopped. + +.TP +\ \ \ \(bu +Change things in your program, so you can experiment with correcting the +effects of one bug and go on to learn about another. +.PP + +You can use GDB to debug programs written in C, C++, and Modula-2. +Fortran support will be added when a GNU Fortran compiler is ready. + +GDB is invoked with the shell command \c +.B gdb\c +\&. Once started, it reads +commands from the terminal until you tell it to exit with the GDB +command \c +.B quit\c +\&. You can get online help from \c +.B gdb\c +\& itself +by using the command \c +.B help\c +\&. + +You can run \c +.B gdb\c +\& with no arguments or options; but the most +usual way to start GDB is with one argument or two, specifying an +executable program as the argument: +.sp +.br +gdb\ program +.br +.sp + +You can also start with both an executable program and a core file specified: +.sp +.br +gdb\ program\ core +.br +.sp + +You can, instead, specify a process ID as a second argument, if you want +to debug a running process: +.sp +.br +gdb\ program\ 1234 +.br +.sp + +would attach GDB to process \c +.B 1234\c +\& (unless you also have a file +named `\|\c +.B 1234\c +\&\|'; GDB does check for a core file first). + +Here are some of the most frequently needed GDB commands: +.TP +.B break \fR[\|\fIfile\fB:\fR\|]\fIfunction +\& +Set a breakpoint at \c +.I function\c +\& (in \c +.I file\c +\&). +.TP +.B run \fR[\|\fIarglist\fR\|] +Start your program (with \c +.I arglist\c +\&, if specified). +.TP +.B bt +Backtrace: display the program stack. +.TP +.BI print " expr"\c +\& +Display the value of an expression. +.TP +.B c +Continue running your program (after stopping, e.g. at a breakpoint). +.TP +.B next +Execute next program line (after stopping); step \c +.I over\c +\& any +function calls in the line. +.TP +.B edit \fR[\|\fIfile\fB:\fR\|]\fIfunction +look at the program line where it is presently stopped. +.TP +.B list \fR[\|\fIfile\fB:\fR\|]\fIfunction +type the text of the program in the vicinity of where it is presently stopped. +.TP +.B step +Execute next program line (after stopping); step \c +.I into\c +\& any +function calls in the line. +.TP +.B help \fR[\|\fIname\fR\|] +Show information about GDB command \c +.I name\c +\&, or general information +about using GDB. +.TP +.B quit +Exit from GDB. +.PP +For full details on GDB, see \c +.I +Using GDB: A Guide to the GNU Source-Level Debugger\c +\&, by Richard M. Stallman and Roland H. Pesch. The same text is available online +as the \c +.B gdb\c +\& entry in the \c +.B info\c +\& program. +.SH OPTIONS +Any arguments other than options specify an executable +file and core file (or process ID); that is, the first argument +encountered with no +associated option flag is equivalent to a `\|\c +.B \-se\c +\&\|' option, and the +second, if any, is equivalent to a `\|\c +.B \-c\c +\&\|' option if it's the name of a file. Many options have +both long and short forms; both are shown here. The long forms are also +recognized if you truncate them, so long as enough of the option is +present to be unambiguous. (If you prefer, you can flag option +arguments with `\|\c +.B +\c +\&\|' rather than `\|\c +.B \-\c +\&\|', though we illustrate the +more usual convention.) + +All the options and command line arguments you give are processed +in sequential order. The order makes a difference when the +`\|\c +.B \-x\c +\&\|' option is used. + +.TP +.B \-help +.TP +.B \-h +List all options, with brief explanations. + +.TP +.BI "\-symbols=" "file"\c +.TP +.BI "\-s " "file"\c +\& +Read symbol table from file \c +.I file\c +\&. + +.TP +.B \-write +Enable writing into executable and core files. + +.TP +.BI "\-exec=" "file"\c +.TP +.BI "\-e " "file"\c +\& +Use file \c +.I file\c +\& as the executable file to execute when +appropriate, and for examining pure data in conjunction with a core +dump. + +.TP +.BI "\-se=" "file"\c +\& +Read symbol table from file \c +.I file\c +\& and use it as the executable +file. + +.TP +.BI "\-core=" "file"\c +.TP +.BI "\-c " "file"\c +\& +Use file \c +.I file\c +\& as a core dump to examine. + +.TP +.BI "\-command=" "file"\c +.TP +.BI "\-x " "file"\c +\& +Execute GDB commands from file \c +.I file\c +\&. + +.TP +.BI "\-directory=" "directory"\c +.TP +.BI "\-d " "directory"\c +\& +Add \c +.I directory\c +\& to the path to search for source files. +.PP + +.TP +.B \-nx +.TP +.B \-n +Do not execute commands from any `\|\c +.B .gdbinit\c +\&\|' initialization files. +Normally, the commands in these files are executed after all the +command options and arguments have been processed. + + +.TP +.B \-quiet +.TP +.B \-q +``Quiet''. Do not print the introductory and copyright messages. These +messages are also suppressed in batch mode. + +.TP +.B \-batch +Run in batch mode. Exit with status \c +.B 0\c +\& after processing all the command +files specified with `\|\c +.B \-x\c +\&\|' (and `\|\c +.B .gdbinit\c +\&\|', if not inhibited). +Exit with nonzero status if an error occurs in executing the GDB +commands in the command files. + +Batch mode may be useful for running GDB as a filter, for example to +download and run a program on another computer; in order to make this +more useful, the message +.sp +.br +Program\ exited\ normally. +.br +.sp + +(which is ordinarily issued whenever a program running under GDB control +terminates) is not issued when running in batch mode. + +.TP +.BI "\-cd=" "directory"\c +\& +Run GDB using \c +.I directory\c +\& as its working directory, +instead of the current directory. + +.TP +.B \-fullname +.TP +.B \-f +Emacs sets this option when it runs GDB as a subprocess. It tells GDB +to output the full file name and line number in a standard, +recognizable fashion each time a stack frame is displayed (which +includes each time the program stops). This recognizable format looks +like two `\|\c +.B \032\c +\&\|' characters, followed by the file name, line number +and character position separated by colons, and a newline. The +Emacs-to-GDB interface program uses the two `\|\c +.B \032\c +\&\|' characters as +a signal to display the source code for the frame. + +.TP +.BI "\-b " "bps"\c +\& +Set the line speed (baud rate or bits per second) of any serial +interface used by GDB for remote debugging. + +.TP +.BI "\-tty=" "device"\c +\& +Run using \c +.I device\c +\& for your program's standard input and output. +.PP + +.SH "SEE ALSO" +.RB "`\|" gdb "\|'" +entry in +.B info\c +\&; +.I +Using GDB: A Guide to the GNU Source-Level Debugger\c +, Richard M. Stallman and Roland H. Pesch, July 1991. +.SH COPYING +Copyright (c) 1991, 2010 Free Software Foundation, Inc. +.PP +Permission is granted to make and distribute verbatim copies of +this manual provided the copyright notice and this permission notice +are preserved on all copies. +.PP +Permission is granted to copy and distribute modified versions of this +manual under the conditions for verbatim copying, provided that the +entire resulting derived work is distributed under the terms of a +permission notice identical to this one. +.PP +Permission is granted to copy and distribute translations of this +manual into another language, under the above conditions for modified +versions, except that this permission notice may be included in +translations approved by the Free Software Foundation instead of in +the original English. diff --git a/share/man/man1/arm-eabi-gdbtui.1 b/share/man/man1/arm-eabi-gdbtui.1 new file mode 100644 index 0000000..d14eb78 --- /dev/null +++ b/share/man/man1/arm-eabi-gdbtui.1 @@ -0,0 +1,381 @@ +.\" Copyright (C) 1991, 1999, 2010, 2011 Free Software Foundation, Inc. +.\" See section COPYING for conditions for redistribution +.\" $Id: gdb.1,v 1.4 1999/01/05 00:50:50 jsm Exp $ +.TH gdb 1 "22may2002" "GNU Tools" "GNU Tools" +.SH NAME +gdb \- The GNU Debugger +.SH SYNOPSIS +.na +.TP +.B gdb +.RB "[\|" \-help "\|]" +.RB "[\|" \-nx "\|]" +.RB "[\|" \-q "\|]" +.RB "[\|" \-batch "\|]" +.RB "[\|" \-cd=\c +.I dir\c +\|] +.RB "[\|" \-f "\|]" +.RB "[\|" "\-b\ "\c +.IR bps "\|]" +.RB "[\|" "\-tty="\c +.IR dev "\|]" +.RB "[\|" "\-s "\c +.I symfile\c +\&\|] +.RB "[\|" "\-e "\c +.I prog\c +\&\|] +.RB "[\|" "\-se "\c +.I prog\c +\&\|] +.RB "[\|" "\-c "\c +.I core\c +\&\|] +.RB "[\|" "\-x "\c +.I cmds\c +\&\|] +.RB "[\|" "\-d "\c +.I dir\c +\&\|] +.RB "[\|" \c +.I prog\c +.RB "[\|" \c +.IR core \||\| procID\c +\&\|]\&\|] +.ad b +.SH DESCRIPTION +The purpose of a debugger such as GDB is to allow you to see what is +going on ``inside'' another program while it executes\(em\&or what another +program was doing at the moment it crashed. + +GDB can do four main kinds of things (plus other things in support of +these) to help you catch bugs in the act: + +.TP +\ \ \ \(bu +Start your program, specifying anything that might affect its behavior. + +.TP +\ \ \ \(bu +Make your program stop on specified conditions. + +.TP +\ \ \ \(bu +Examine what has happened, when your program has stopped. + +.TP +\ \ \ \(bu +Change things in your program, so you can experiment with correcting the +effects of one bug and go on to learn about another. +.PP + +You can use GDB to debug programs written in C, C++, and Modula-2. +Fortran support will be added when a GNU Fortran compiler is ready. + +GDB is invoked with the shell command \c +.B gdb\c +\&. Once started, it reads +commands from the terminal until you tell it to exit with the GDB +command \c +.B quit\c +\&. You can get online help from \c +.B gdb\c +\& itself +by using the command \c +.B help\c +\&. + +You can run \c +.B gdb\c +\& with no arguments or options; but the most +usual way to start GDB is with one argument or two, specifying an +executable program as the argument: +.sp +.br +gdb\ program +.br +.sp + +You can also start with both an executable program and a core file specified: +.sp +.br +gdb\ program\ core +.br +.sp + +You can, instead, specify a process ID as a second argument, if you want +to debug a running process: +.sp +.br +gdb\ program\ 1234 +.br +.sp + +would attach GDB to process \c +.B 1234\c +\& (unless you also have a file +named `\|\c +.B 1234\c +\&\|'; GDB does check for a core file first). + +Here are some of the most frequently needed GDB commands: +.TP +.B break \fR[\|\fIfile\fB:\fR\|]\fIfunction +\& +Set a breakpoint at \c +.I function\c +\& (in \c +.I file\c +\&). +.TP +.B run \fR[\|\fIarglist\fR\|] +Start your program (with \c +.I arglist\c +\&, if specified). +.TP +.B bt +Backtrace: display the program stack. +.TP +.BI print " expr"\c +\& +Display the value of an expression. +.TP +.B c +Continue running your program (after stopping, e.g. at a breakpoint). +.TP +.B next +Execute next program line (after stopping); step \c +.I over\c +\& any +function calls in the line. +.TP +.B edit \fR[\|\fIfile\fB:\fR\|]\fIfunction +look at the program line where it is presently stopped. +.TP +.B list \fR[\|\fIfile\fB:\fR\|]\fIfunction +type the text of the program in the vicinity of where it is presently stopped. +.TP +.B step +Execute next program line (after stopping); step \c +.I into\c +\& any +function calls in the line. +.TP +.B help \fR[\|\fIname\fR\|] +Show information about GDB command \c +.I name\c +\&, or general information +about using GDB. +.TP +.B quit +Exit from GDB. +.PP +For full details on GDB, see \c +.I +Using GDB: A Guide to the GNU Source-Level Debugger\c +\&, by Richard M. Stallman and Roland H. Pesch. The same text is available online +as the \c +.B gdb\c +\& entry in the \c +.B info\c +\& program. +.SH OPTIONS +Any arguments other than options specify an executable +file and core file (or process ID); that is, the first argument +encountered with no +associated option flag is equivalent to a `\|\c +.B \-se\c +\&\|' option, and the +second, if any, is equivalent to a `\|\c +.B \-c\c +\&\|' option if it's the name of a file. Many options have +both long and short forms; both are shown here. The long forms are also +recognized if you truncate them, so long as enough of the option is +present to be unambiguous. (If you prefer, you can flag option +arguments with `\|\c +.B +\c +\&\|' rather than `\|\c +.B \-\c +\&\|', though we illustrate the +more usual convention.) + +All the options and command line arguments you give are processed +in sequential order. The order makes a difference when the +`\|\c +.B \-x\c +\&\|' option is used. + +.TP +.B \-help +.TP +.B \-h +List all options, with brief explanations. + +.TP +.BI "\-symbols=" "file"\c +.TP +.BI "\-s " "file"\c +\& +Read symbol table from file \c +.I file\c +\&. + +.TP +.B \-write +Enable writing into executable and core files. + +.TP +.BI "\-exec=" "file"\c +.TP +.BI "\-e " "file"\c +\& +Use file \c +.I file\c +\& as the executable file to execute when +appropriate, and for examining pure data in conjunction with a core +dump. + +.TP +.BI "\-se=" "file"\c +\& +Read symbol table from file \c +.I file\c +\& and use it as the executable +file. + +.TP +.BI "\-core=" "file"\c +.TP +.BI "\-c " "file"\c +\& +Use file \c +.I file\c +\& as a core dump to examine. + +.TP +.BI "\-command=" "file"\c +.TP +.BI "\-x " "file"\c +\& +Execute GDB commands from file \c +.I file\c +\&. + +.TP +.BI "\-directory=" "directory"\c +.TP +.BI "\-d " "directory"\c +\& +Add \c +.I directory\c +\& to the path to search for source files. +.PP + +.TP +.B \-nx +.TP +.B \-n +Do not execute commands from any `\|\c +.B .gdbinit\c +\&\|' initialization files. +Normally, the commands in these files are executed after all the +command options and arguments have been processed. + + +.TP +.B \-quiet +.TP +.B \-q +``Quiet''. Do not print the introductory and copyright messages. These +messages are also suppressed in batch mode. + +.TP +.B \-batch +Run in batch mode. Exit with status \c +.B 0\c +\& after processing all the command +files specified with `\|\c +.B \-x\c +\&\|' (and `\|\c +.B .gdbinit\c +\&\|', if not inhibited). +Exit with nonzero status if an error occurs in executing the GDB +commands in the command files. + +Batch mode may be useful for running GDB as a filter, for example to +download and run a program on another computer; in order to make this +more useful, the message +.sp +.br +Program\ exited\ normally. +.br +.sp + +(which is ordinarily issued whenever a program running under GDB control +terminates) is not issued when running in batch mode. + +.TP +.BI "\-cd=" "directory"\c +\& +Run GDB using \c +.I directory\c +\& as its working directory, +instead of the current directory. + +.TP +.B \-fullname +.TP +.B \-f +Emacs sets this option when it runs GDB as a subprocess. It tells GDB +to output the full file name and line number in a standard, +recognizable fashion each time a stack frame is displayed (which +includes each time the program stops). This recognizable format looks +like two `\|\c +.B \032\c +\&\|' characters, followed by the file name, line number +and character position separated by colons, and a newline. The +Emacs-to-GDB interface program uses the two `\|\c +.B \032\c +\&\|' characters as +a signal to display the source code for the frame. + +.TP +.BI "\-b " "bps"\c +\& +Set the line speed (baud rate or bits per second) of any serial +interface used by GDB for remote debugging. + +.TP +.BI "\-tty=" "device"\c +\& +Run using \c +.I device\c +\& for your program's standard input and output. +.PP + +.SH "SEE ALSO" +.RB "`\|" gdb "\|'" +entry in +.B info\c +\&; +.I +Using GDB: A Guide to the GNU Source-Level Debugger\c +, Richard M. Stallman and Roland H. Pesch, July 1991. +.SH COPYING +Copyright (c) 1991, 2010 Free Software Foundation, Inc. +.PP +Permission is granted to make and distribute verbatim copies of +this manual provided the copyright notice and this permission notice +are preserved on all copies. +.PP +Permission is granted to copy and distribute modified versions of this +manual under the conditions for verbatim copying, provided that the +entire resulting derived work is distributed under the terms of a +permission notice identical to this one. +.PP +Permission is granted to copy and distribute translations of this +manual into another language, under the above conditions for modified +versions, except that this permission notice may be included in +translations approved by the Free Software Foundation instead of in +the original English. diff --git a/share/man/man1/arm-eabi-gprof.1 b/share/man/man1/arm-eabi-gprof.1 new file mode 100644 index 0000000..bf7b523 --- /dev/null +++ b/share/man/man1/arm-eabi-gprof.1 @@ -0,0 +1,757 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "GPROF 1" +.TH GPROF 1 " " "binutils-2.21" "GNU" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +gprof \- display call graph profile data +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +gprof [ \-[abcDhilLrsTvwxyz] ] [ \-[ACeEfFJnNOpPqQZ][\fIname\fR] ] + [ \-I \fIdirs\fR ] [ \-d[\fInum\fR] ] [ \-k \fIfrom/to\fR ] + [ \-m \fImin-count\fR ] [ \-R \fImap_file\fR ] [ \-t \fItable-length\fR ] + [ \-\-[no\-]annotated\-source[=\fIname\fR] ] + [ \-\-[no\-]exec\-counts[=\fIname\fR] ] + [ \-\-[no\-]flat\-profile[=\fIname\fR] ] [ \-\-[no\-]graph[=\fIname\fR] ] + [ \-\-[no\-]time=\fIname\fR] [ \-\-all\-lines ] [ \-\-brief ] + [ \-\-debug[=\fIlevel\fR] ] [ \-\-function\-ordering ] + [ \-\-file\-ordering \fImap_file\fR ] [ \-\-directory\-path=\fIdirs\fR ] + [ \-\-display\-unused\-functions ] [ \-\-file\-format=\fIname\fR ] + [ \-\-file\-info ] [ \-\-help ] [ \-\-line ] [ \-\-min\-count=\fIn\fR ] + [ \-\-no\-static ] [ \-\-print\-path ] [ \-\-separate\-files ] + [ \-\-static\-call\-graph ] [ \-\-sum ] [ \-\-table\-length=\fIlen\fR ] + [ \-\-traditional ] [ \-\-version ] [ \-\-width=\fIn\fR ] + [ \-\-ignore\-non\-functions ] [ \-\-demangle[=\fI\s-1STYLE\s0\fR] ] + [ \-\-no\-demangle ] [\-\-external\-symbol\-table=name] + [ \fIimage-file\fR ] [ \fIprofile-file\fR ... ] +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +\&\f(CW\*(C`gprof\*(C'\fR produces an execution profile of C, Pascal, or Fortran77 +programs. The effect of called routines is incorporated in the profile +of each caller. The profile data is taken from the call graph profile file +(\fIgmon.out\fR default) which is created by programs +that are compiled with the \fB\-pg\fR option of +\&\f(CW\*(C`cc\*(C'\fR, \f(CW\*(C`pc\*(C'\fR, and \f(CW\*(C`f77\*(C'\fR. +The \fB\-pg\fR option also links in versions of the library routines +that are compiled for profiling. \f(CW\*(C`Gprof\*(C'\fR reads the given object +file (the default is \f(CW\*(C`a.out\*(C'\fR) and establishes the relation between +its symbol table and the call graph profile from \fIgmon.out\fR. +If more than one profile file is specified, the \f(CW\*(C`gprof\*(C'\fR +output shows the sum of the profile information in the given profile files. +.PP +\&\f(CW\*(C`Gprof\*(C'\fR calculates the amount of time spent in each routine. +Next, these times are propagated along the edges of the call graph. +Cycles are discovered, and calls into a cycle are made to share the time +of the cycle. +.PP +Several forms of output are available from the analysis. +.PP +The \fIflat profile\fR shows how much time your program spent in each function, +and how many times that function was called. If you simply want to know +which functions burn most of the cycles, it is stated concisely here. +.PP +The \fIcall graph\fR shows, for each function, which functions called it, which +other functions it called, and how many times. There is also an estimate +of how much time was spent in the subroutines of each function. This can +suggest places where you might try to eliminate function calls that use a +lot of time. +.PP +The \fIannotated source\fR listing is a copy of the program's +source code, labeled with the number of times each line of the +program was executed. +.SH "OPTIONS" +.IX Header "OPTIONS" +These options specify which of several output formats +\&\f(CW\*(C`gprof\*(C'\fR should produce. +.PP +Many of these options take an optional \fIsymspec\fR to specify +functions to be included or excluded. These options can be +specified multiple times, with different symspecs, to include +or exclude sets of symbols. +.PP +Specifying any of these options overrides the default (\fB\-p \-q\fR), +which prints a flat profile and call graph analysis +for all functions. +.ie n .IP """\-A[\f(CIsymspec\f(CW]""" 4 +.el .IP "\f(CW\-A[\f(CIsymspec\f(CW]\fR" 4 +.IX Item "-A[symspec]" +.PD 0 +.ie n .IP """\-\-annotated\-source[=\f(CIsymspec\f(CW]""" 4 +.el .IP "\f(CW\-\-annotated\-source[=\f(CIsymspec\f(CW]\fR" 4 +.IX Item "--annotated-source[=symspec]" +.PD +The \fB\-A\fR option causes \f(CW\*(C`gprof\*(C'\fR to print annotated source code. +If \fIsymspec\fR is specified, print output only for matching symbols. +.ie n .IP """\-b""" 4 +.el .IP "\f(CW\-b\fR" 4 +.IX Item "-b" +.PD 0 +.ie n .IP """\-\-brief""" 4 +.el .IP "\f(CW\-\-brief\fR" 4 +.IX Item "--brief" +.PD +If the \fB\-b\fR option is given, \f(CW\*(C`gprof\*(C'\fR doesn't print the +verbose blurbs that try to explain the meaning of all of the fields in +the tables. This is useful if you intend to print out the output, or +are tired of seeing the blurbs. +.ie n .IP """\-C[\f(CIsymspec\f(CW]""" 4 +.el .IP "\f(CW\-C[\f(CIsymspec\f(CW]\fR" 4 +.IX Item "-C[symspec]" +.PD 0 +.ie n .IP """\-\-exec\-counts[=\f(CIsymspec\f(CW]""" 4 +.el .IP "\f(CW\-\-exec\-counts[=\f(CIsymspec\f(CW]\fR" 4 +.IX Item "--exec-counts[=symspec]" +.PD +The \fB\-C\fR option causes \f(CW\*(C`gprof\*(C'\fR to +print a tally of functions and the number of times each was called. +If \fIsymspec\fR is specified, print tally only for matching symbols. +.Sp +If the profile data file contains basic-block count records, specifying +the \fB\-l\fR option, along with \fB\-C\fR, will cause basic-block +execution counts to be tallied and displayed. +.ie n .IP """\-i""" 4 +.el .IP "\f(CW\-i\fR" 4 +.IX Item "-i" +.PD 0 +.ie n .IP """\-\-file\-info""" 4 +.el .IP "\f(CW\-\-file\-info\fR" 4 +.IX Item "--file-info" +.PD +The \fB\-i\fR option causes \f(CW\*(C`gprof\*(C'\fR to display summary information +about the profile data file(s) and then exit. The number of histogram, +call graph, and basic-block count records is displayed. +.ie n .IP """\-I \f(CIdirs\f(CW""" 4 +.el .IP "\f(CW\-I \f(CIdirs\f(CW\fR" 4 +.IX Item "-I dirs" +.PD 0 +.ie n .IP """\-\-directory\-path=\f(CIdirs\f(CW""" 4 +.el .IP "\f(CW\-\-directory\-path=\f(CIdirs\f(CW\fR" 4 +.IX Item "--directory-path=dirs" +.PD +The \fB\-I\fR option specifies a list of search directories in +which to find source files. Environment variable \fI\s-1GPROF_PATH\s0\fR +can also be used to convey this information. +Used mostly for annotated source output. +.ie n .IP """\-J[\f(CIsymspec\f(CW]""" 4 +.el .IP "\f(CW\-J[\f(CIsymspec\f(CW]\fR" 4 +.IX Item "-J[symspec]" +.PD 0 +.ie n .IP """\-\-no\-annotated\-source[=\f(CIsymspec\f(CW]""" 4 +.el .IP "\f(CW\-\-no\-annotated\-source[=\f(CIsymspec\f(CW]\fR" 4 +.IX Item "--no-annotated-source[=symspec]" +.PD +The \fB\-J\fR option causes \f(CW\*(C`gprof\*(C'\fR not to +print annotated source code. +If \fIsymspec\fR is specified, \f(CW\*(C`gprof\*(C'\fR prints annotated source, +but excludes matching symbols. +.ie n .IP """\-L""" 4 +.el .IP "\f(CW\-L\fR" 4 +.IX Item "-L" +.PD 0 +.ie n .IP """\-\-print\-path""" 4 +.el .IP "\f(CW\-\-print\-path\fR" 4 +.IX Item "--print-path" +.PD +Normally, source filenames are printed with the path +component suppressed. The \fB\-L\fR option causes \f(CW\*(C`gprof\*(C'\fR +to print the full pathname of +source filenames, which is determined +from symbolic debugging information in the image file +and is relative to the directory in which the compiler +was invoked. +.ie n .IP """\-p[\f(CIsymspec\f(CW]""" 4 +.el .IP "\f(CW\-p[\f(CIsymspec\f(CW]\fR" 4 +.IX Item "-p[symspec]" +.PD 0 +.ie n .IP """\-\-flat\-profile[=\f(CIsymspec\f(CW]""" 4 +.el .IP "\f(CW\-\-flat\-profile[=\f(CIsymspec\f(CW]\fR" 4 +.IX Item "--flat-profile[=symspec]" +.PD +The \fB\-p\fR option causes \f(CW\*(C`gprof\*(C'\fR to print a flat profile. +If \fIsymspec\fR is specified, print flat profile only for matching symbols. +.ie n .IP """\-P[\f(CIsymspec\f(CW]""" 4 +.el .IP "\f(CW\-P[\f(CIsymspec\f(CW]\fR" 4 +.IX Item "-P[symspec]" +.PD 0 +.ie n .IP """\-\-no\-flat\-profile[=\f(CIsymspec\f(CW]""" 4 +.el .IP "\f(CW\-\-no\-flat\-profile[=\f(CIsymspec\f(CW]\fR" 4 +.IX Item "--no-flat-profile[=symspec]" +.PD +The \fB\-P\fR option causes \f(CW\*(C`gprof\*(C'\fR to suppress printing a flat profile. +If \fIsymspec\fR is specified, \f(CW\*(C`gprof\*(C'\fR prints a flat profile, +but excludes matching symbols. +.ie n .IP """\-q[\f(CIsymspec\f(CW]""" 4 +.el .IP "\f(CW\-q[\f(CIsymspec\f(CW]\fR" 4 +.IX Item "-q[symspec]" +.PD 0 +.ie n .IP """\-\-graph[=\f(CIsymspec\f(CW]""" 4 +.el .IP "\f(CW\-\-graph[=\f(CIsymspec\f(CW]\fR" 4 +.IX Item "--graph[=symspec]" +.PD +The \fB\-q\fR option causes \f(CW\*(C`gprof\*(C'\fR to print the call graph analysis. +If \fIsymspec\fR is specified, print call graph only for matching symbols +and their children. +.ie n .IP """\-Q[\f(CIsymspec\f(CW]""" 4 +.el .IP "\f(CW\-Q[\f(CIsymspec\f(CW]\fR" 4 +.IX Item "-Q[symspec]" +.PD 0 +.ie n .IP """\-\-no\-graph[=\f(CIsymspec\f(CW]""" 4 +.el .IP "\f(CW\-\-no\-graph[=\f(CIsymspec\f(CW]\fR" 4 +.IX Item "--no-graph[=symspec]" +.PD +The \fB\-Q\fR option causes \f(CW\*(C`gprof\*(C'\fR to suppress printing the +call graph. +If \fIsymspec\fR is specified, \f(CW\*(C`gprof\*(C'\fR prints a call graph, +but excludes matching symbols. +.ie n .IP """\-t""" 4 +.el .IP "\f(CW\-t\fR" 4 +.IX Item "-t" +.PD 0 +.ie n .IP """\-\-table\-length=\f(CInum\f(CW""" 4 +.el .IP "\f(CW\-\-table\-length=\f(CInum\f(CW\fR" 4 +.IX Item "--table-length=num" +.PD +The \fB\-t\fR option causes the \fInum\fR most active source lines in +each source file to be listed when source annotation is enabled. The +default is 10. +.ie n .IP """\-y""" 4 +.el .IP "\f(CW\-y\fR" 4 +.IX Item "-y" +.PD 0 +.ie n .IP """\-\-separate\-files""" 4 +.el .IP "\f(CW\-\-separate\-files\fR" 4 +.IX Item "--separate-files" +.PD +This option affects annotated source output only. +Normally, \f(CW\*(C`gprof\*(C'\fR prints annotated source files +to standard-output. If this option is specified, +annotated source for a file named \fIpath/\fIfilename\fI\fR +is generated in the file \fI\fIfilename\fI\-ann\fR. If the underlying +file system would truncate \fI\fIfilename\fI\-ann\fR so that it +overwrites the original \fI\fIfilename\fI\fR, \f(CW\*(C`gprof\*(C'\fR generates +annotated source in the file \fI\fIfilename\fI.ann\fR instead (if the +original file name has an extension, that extension is \fIreplaced\fR +with \fI.ann\fR). +.ie n .IP """\-Z[\f(CIsymspec\f(CW]""" 4 +.el .IP "\f(CW\-Z[\f(CIsymspec\f(CW]\fR" 4 +.IX Item "-Z[symspec]" +.PD 0 +.ie n .IP """\-\-no\-exec\-counts[=\f(CIsymspec\f(CW]""" 4 +.el .IP "\f(CW\-\-no\-exec\-counts[=\f(CIsymspec\f(CW]\fR" 4 +.IX Item "--no-exec-counts[=symspec]" +.PD +The \fB\-Z\fR option causes \f(CW\*(C`gprof\*(C'\fR not to +print a tally of functions and the number of times each was called. +If \fIsymspec\fR is specified, print tally, but exclude matching symbols. +.ie n .IP """\-r""" 4 +.el .IP "\f(CW\-r\fR" 4 +.IX Item "-r" +.PD 0 +.ie n .IP """\-\-function\-ordering""" 4 +.el .IP "\f(CW\-\-function\-ordering\fR" 4 +.IX Item "--function-ordering" +.PD +The \fB\-\-function\-ordering\fR option causes \f(CW\*(C`gprof\*(C'\fR to print a +suggested function ordering for the program based on profiling data. +This option suggests an ordering which may improve paging, tlb and +cache behavior for the program on systems which support arbitrary +ordering of functions in an executable. +.Sp +The exact details of how to force the linker to place functions +in a particular order is system dependent and out of the scope of this +manual. +.ie n .IP """\-R \f(CImap_file\f(CW""" 4 +.el .IP "\f(CW\-R \f(CImap_file\f(CW\fR" 4 +.IX Item "-R map_file" +.PD 0 +.ie n .IP """\-\-file\-ordering \f(CImap_file\f(CW""" 4 +.el .IP "\f(CW\-\-file\-ordering \f(CImap_file\f(CW\fR" 4 +.IX Item "--file-ordering map_file" +.PD +The \fB\-\-file\-ordering\fR option causes \f(CW\*(C`gprof\*(C'\fR to print a +suggested .o link line ordering for the program based on profiling data. +This option suggests an ordering which may improve paging, tlb and +cache behavior for the program on systems which do not support arbitrary +ordering of functions in an executable. +.Sp +Use of the \fB\-a\fR argument is highly recommended with this option. +.Sp +The \fImap_file\fR argument is a pathname to a file which provides +function name to object file mappings. The format of the file is similar to +the output of the program \f(CW\*(C`nm\*(C'\fR. +.Sp +.Vb 8 +\& c\-parse.o:00000000 T yyparse +\& c\-parse.o:00000004 C yyerrflag +\& c\-lang.o:00000000 T maybe_objc_method_name +\& c\-lang.o:00000000 T print_lang_statistics +\& c\-lang.o:00000000 T recognize_objc_keyword +\& c\-decl.o:00000000 T print_lang_identifier +\& c\-decl.o:00000000 T print_lang_type +\& ... +.Ve +.Sp +To create a \fImap_file\fR with \s-1GNU\s0 \f(CW\*(C`nm\*(C'\fR, type a command like +\&\f(CW\*(C`nm \-\-extern\-only \-\-defined\-only \-v \-\-print\-file\-name program\-name\*(C'\fR. +.ie n .IP """\-T""" 4 +.el .IP "\f(CW\-T\fR" 4 +.IX Item "-T" +.PD 0 +.ie n .IP """\-\-traditional""" 4 +.el .IP "\f(CW\-\-traditional\fR" 4 +.IX Item "--traditional" +.PD +The \fB\-T\fR option causes \f(CW\*(C`gprof\*(C'\fR to print its output in +\&\*(L"traditional\*(R" \s-1BSD\s0 style. +.ie n .IP """\-w \f(CIwidth\f(CW""" 4 +.el .IP "\f(CW\-w \f(CIwidth\f(CW\fR" 4 +.IX Item "-w width" +.PD 0 +.ie n .IP """\-\-width=\f(CIwidth\f(CW""" 4 +.el .IP "\f(CW\-\-width=\f(CIwidth\f(CW\fR" 4 +.IX Item "--width=width" +.PD +Sets width of output lines to \fIwidth\fR. +Currently only used when printing the function index at the bottom +of the call graph. +.ie n .IP """\-x""" 4 +.el .IP "\f(CW\-x\fR" 4 +.IX Item "-x" +.PD 0 +.ie n .IP """\-\-all\-lines""" 4 +.el .IP "\f(CW\-\-all\-lines\fR" 4 +.IX Item "--all-lines" +.PD +This option affects annotated source output only. +By default, only the lines at the beginning of a basic-block +are annotated. If this option is specified, every line in +a basic-block is annotated by repeating the annotation for the +first line. This behavior is similar to \f(CW\*(C`tcov\*(C'\fR's \fB\-a\fR. +.ie n .IP """\-\-demangle[=\f(CIstyle\f(CW]""" 4 +.el .IP "\f(CW\-\-demangle[=\f(CIstyle\f(CW]\fR" 4 +.IX Item "--demangle[=style]" +.PD 0 +.ie n .IP """\-\-no\-demangle""" 4 +.el .IP "\f(CW\-\-no\-demangle\fR" 4 +.IX Item "--no-demangle" +.PD +These options control whether \*(C+ symbol names should be demangled when +printing output. The default is to demangle symbols. The +\&\f(CW\*(C`\-\-no\-demangle\*(C'\fR option may be used to turn off demangling. Different +compilers have different mangling styles. The optional demangling style +argument can be used to choose an appropriate demangling style for your +compiler. +.SS "Analysis Options" +.IX Subsection "Analysis Options" +.ie n .IP """\-a""" 4 +.el .IP "\f(CW\-a\fR" 4 +.IX Item "-a" +.PD 0 +.ie n .IP """\-\-no\-static""" 4 +.el .IP "\f(CW\-\-no\-static\fR" 4 +.IX Item "--no-static" +.PD +The \fB\-a\fR option causes \f(CW\*(C`gprof\*(C'\fR to suppress the printing of +statically declared (private) functions. (These are functions whose +names are not listed as global, and which are not visible outside the +file/function/block where they were defined.) Time spent in these +functions, calls to/from them, etc., will all be attributed to the +function that was loaded directly before it in the executable file. +This option affects both the flat profile and the call graph. +.ie n .IP """\-c""" 4 +.el .IP "\f(CW\-c\fR" 4 +.IX Item "-c" +.PD 0 +.ie n .IP """\-\-static\-call\-graph""" 4 +.el .IP "\f(CW\-\-static\-call\-graph\fR" 4 +.IX Item "--static-call-graph" +.PD +The \fB\-c\fR option causes the call graph of the program to be +augmented by a heuristic which examines the text space of the object +file and identifies function calls in the binary machine code. +Since normal call graph records are only generated when functions are +entered, this option identifies children that could have been called, +but never were. Calls to functions that were not compiled with +profiling enabled are also identified, but only if symbol table +entries are present for them. +Calls to dynamic library routines are typically \fInot\fR found +by this option. +Parents or children identified via this heuristic +are indicated in the call graph with call counts of \fB0\fR. +.ie n .IP """\-D""" 4 +.el .IP "\f(CW\-D\fR" 4 +.IX Item "-D" +.PD 0 +.ie n .IP """\-\-ignore\-non\-functions""" 4 +.el .IP "\f(CW\-\-ignore\-non\-functions\fR" 4 +.IX Item "--ignore-non-functions" +.PD +The \fB\-D\fR option causes \f(CW\*(C`gprof\*(C'\fR to ignore symbols which +are not known to be functions. This option will give more accurate +profile data on systems where it is supported (Solaris and \s-1HPUX\s0 for +example). +.ie n .IP """\-k \f(CIfrom\f(CW/\f(CIto\f(CW""" 4 +.el .IP "\f(CW\-k \f(CIfrom\f(CW/\f(CIto\f(CW\fR" 4 +.IX Item "-k from/to" +The \fB\-k\fR option allows you to delete from the call graph any arcs from +symbols matching symspec \fIfrom\fR to those matching symspec \fIto\fR. +.ie n .IP """\-l""" 4 +.el .IP "\f(CW\-l\fR" 4 +.IX Item "-l" +.PD 0 +.ie n .IP """\-\-line""" 4 +.el .IP "\f(CW\-\-line\fR" 4 +.IX Item "--line" +.PD +The \fB\-l\fR option enables line-by-line profiling, which causes +histogram hits to be charged to individual source code lines, +instead of functions. This feature only works with programs compiled +by older versions of the \f(CW\*(C`gcc\*(C'\fR compiler. Newer versions of +\&\f(CW\*(C`gcc\*(C'\fR are designed to work with the \f(CW\*(C`gcov\*(C'\fR tool instead. +.Sp +If the program was compiled with basic-block counting enabled, +this option will also identify how many times each line of +code was executed. +While line-by-line profiling can help isolate where in a large function +a program is spending its time, it also significantly increases +the running time of \f(CW\*(C`gprof\*(C'\fR, and magnifies statistical +inaccuracies. +.ie n .IP """\-m \f(CInum\f(CW""" 4 +.el .IP "\f(CW\-m \f(CInum\f(CW\fR" 4 +.IX Item "-m num" +.PD 0 +.ie n .IP """\-\-min\-count=\f(CInum\f(CW""" 4 +.el .IP "\f(CW\-\-min\-count=\f(CInum\f(CW\fR" 4 +.IX Item "--min-count=num" +.PD +This option affects execution count output only. +Symbols that are executed less than \fInum\fR times are suppressed. +.ie n .IP """\-n\f(CIsymspec\f(CW""" 4 +.el .IP "\f(CW\-n\f(CIsymspec\f(CW\fR" 4 +.IX Item "-nsymspec" +.PD 0 +.ie n .IP """\-\-time=\f(CIsymspec\f(CW""" 4 +.el .IP "\f(CW\-\-time=\f(CIsymspec\f(CW\fR" 4 +.IX Item "--time=symspec" +.PD +The \fB\-n\fR option causes \f(CW\*(C`gprof\*(C'\fR, in its call graph analysis, +to only propagate times for symbols matching \fIsymspec\fR. +.ie n .IP """\-N\f(CIsymspec\f(CW""" 4 +.el .IP "\f(CW\-N\f(CIsymspec\f(CW\fR" 4 +.IX Item "-Nsymspec" +.PD 0 +.ie n .IP """\-\-no\-time=\f(CIsymspec\f(CW""" 4 +.el .IP "\f(CW\-\-no\-time=\f(CIsymspec\f(CW\fR" 4 +.IX Item "--no-time=symspec" +.PD +The \fB\-n\fR option causes \f(CW\*(C`gprof\*(C'\fR, in its call graph analysis, +not to propagate times for symbols matching \fIsymspec\fR. +.ie n .IP """\-S\f(CIfilename\f(CW""" 4 +.el .IP "\f(CW\-S\f(CIfilename\f(CW\fR" 4 +.IX Item "-Sfilename" +.PD 0 +.ie n .IP """\-\-external\-symbol\-table=\f(CIfilename\f(CW""" 4 +.el .IP "\f(CW\-\-external\-symbol\-table=\f(CIfilename\f(CW\fR" 4 +.IX Item "--external-symbol-table=filename" +.PD +The \fB\-S\fR option causes \f(CW\*(C`gprof\*(C'\fR to read an external symbol table +file, such as \fI/proc/kallsyms\fR, rather than read the symbol table +from the given object file (the default is \f(CW\*(C`a.out\*(C'\fR). This is useful +for profiling kernel modules. +.ie n .IP """\-z""" 4 +.el .IP "\f(CW\-z\fR" 4 +.IX Item "-z" +.PD 0 +.ie n .IP """\-\-display\-unused\-functions""" 4 +.el .IP "\f(CW\-\-display\-unused\-functions\fR" 4 +.IX Item "--display-unused-functions" +.PD +If you give the \fB\-z\fR option, \f(CW\*(C`gprof\*(C'\fR will mention all +functions in the flat profile, even those that were never called, and +that had no time spent in them. This is useful in conjunction with the +\&\fB\-c\fR option for discovering which routines were never called. +.SS "Miscellaneous Options" +.IX Subsection "Miscellaneous Options" +.ie n .IP """\-d[\f(CInum\f(CW]""" 4 +.el .IP "\f(CW\-d[\f(CInum\f(CW]\fR" 4 +.IX Item "-d[num]" +.PD 0 +.ie n .IP """\-\-debug[=\f(CInum\f(CW]""" 4 +.el .IP "\f(CW\-\-debug[=\f(CInum\f(CW]\fR" 4 +.IX Item "--debug[=num]" +.PD +The \fB\-d\fR \fInum\fR option specifies debugging options. +If \fInum\fR is not specified, enable all debugging. +.ie n .IP """\-h""" 4 +.el .IP "\f(CW\-h\fR" 4 +.IX Item "-h" +.PD 0 +.ie n .IP """\-\-help""" 4 +.el .IP "\f(CW\-\-help\fR" 4 +.IX Item "--help" +.PD +The \fB\-h\fR option prints command line usage. +.ie n .IP """\-O\f(CIname\f(CW""" 4 +.el .IP "\f(CW\-O\f(CIname\f(CW\fR" 4 +.IX Item "-Oname" +.PD 0 +.ie n .IP """\-\-file\-format=\f(CIname\f(CW""" 4 +.el .IP "\f(CW\-\-file\-format=\f(CIname\f(CW\fR" 4 +.IX Item "--file-format=name" +.PD +Selects the format of the profile data files. Recognized formats are +\&\fBauto\fR (the default), \fBbsd\fR, \fB4.4bsd\fR, \fBmagic\fR, and +\&\fBprof\fR (not yet supported). +.ie n .IP """\-s""" 4 +.el .IP "\f(CW\-s\fR" 4 +.IX Item "-s" +.PD 0 +.ie n .IP """\-\-sum""" 4 +.el .IP "\f(CW\-\-sum\fR" 4 +.IX Item "--sum" +.PD +The \fB\-s\fR option causes \f(CW\*(C`gprof\*(C'\fR to summarize the information +in the profile data files it read in, and write out a profile data +file called \fIgmon.sum\fR, which contains all the information from +the profile data files that \f(CW\*(C`gprof\*(C'\fR read in. The file \fIgmon.sum\fR +may be one of the specified input files; the effect of this is to +merge the data in the other input files into \fIgmon.sum\fR. +.Sp +Eventually you can run \f(CW\*(C`gprof\*(C'\fR again without \fB\-s\fR to analyze the +cumulative data in the file \fIgmon.sum\fR. +.ie n .IP """\-v""" 4 +.el .IP "\f(CW\-v\fR" 4 +.IX Item "-v" +.PD 0 +.ie n .IP """\-\-version""" 4 +.el .IP "\f(CW\-\-version\fR" 4 +.IX Item "--version" +.PD +The \fB\-v\fR flag causes \f(CW\*(C`gprof\*(C'\fR to print the current version +number, and then exit. +.SS "Deprecated Options" +.IX Subsection "Deprecated Options" +These options have been replaced with newer versions that use symspecs. +.ie n .IP """\-e \f(CIfunction_name\f(CW""" 4 +.el .IP "\f(CW\-e \f(CIfunction_name\f(CW\fR" 4 +.IX Item "-e function_name" +The \fB\-e\fR \fIfunction\fR option tells \f(CW\*(C`gprof\*(C'\fR to not print +information about the function \fIfunction_name\fR (and its +children...) in the call graph. The function will still be listed +as a child of any functions that call it, but its index number will be +shown as \fB[not printed]\fR. More than one \fB\-e\fR option may be +given; only one \fIfunction_name\fR may be indicated with each \fB\-e\fR +option. +.ie n .IP """\-E \f(CIfunction_name\f(CW""" 4 +.el .IP "\f(CW\-E \f(CIfunction_name\f(CW\fR" 4 +.IX Item "-E function_name" +The \f(CW\*(C`\-E \f(CIfunction\f(CW\*(C'\fR option works like the \f(CW\*(C`\-e\*(C'\fR option, but +time spent in the function (and children who were not called from +anywhere else), will not be used to compute the percentages-of-time for +the call graph. More than one \fB\-E\fR option may be given; only one +\&\fIfunction_name\fR may be indicated with each \fB\-E\fR option. +.ie n .IP """\-f \f(CIfunction_name\f(CW""" 4 +.el .IP "\f(CW\-f \f(CIfunction_name\f(CW\fR" 4 +.IX Item "-f function_name" +The \fB\-f\fR \fIfunction\fR option causes \f(CW\*(C`gprof\*(C'\fR to limit the +call graph to the function \fIfunction_name\fR and its children (and +their children...). More than one \fB\-f\fR option may be given; +only one \fIfunction_name\fR may be indicated with each \fB\-f\fR +option. +.ie n .IP """\-F \f(CIfunction_name\f(CW""" 4 +.el .IP "\f(CW\-F \f(CIfunction_name\f(CW\fR" 4 +.IX Item "-F function_name" +The \fB\-F\fR \fIfunction\fR option works like the \f(CW\*(C`\-f\*(C'\fR option, but +only time spent in the function and its children (and their +children...) will be used to determine total-time and +percentages-of-time for the call graph. More than one \fB\-F\fR option +may be given; only one \fIfunction_name\fR may be indicated with each +\&\fB\-F\fR option. The \fB\-F\fR option overrides the \fB\-E\fR option. +.SH "FILES" +.IX Header "FILES" +.ie n .IP """\f(CIa.out\f(CW""" 4 +.el .IP "\f(CW\f(CIa.out\f(CW\fR" 4 +.IX Item "a.out" +the namelist and text space. +.ie n .IP """\f(CIgmon.out\f(CW""" 4 +.el .IP "\f(CW\f(CIgmon.out\f(CW\fR" 4 +.IX Item "gmon.out" +dynamic call graph and profile. +.ie n .IP """\f(CIgmon.sum\f(CW""" 4 +.el .IP "\f(CW\f(CIgmon.sum\f(CW\fR" 4 +.IX Item "gmon.sum" +summarized dynamic call graph and profile. +.SH "BUGS" +.IX Header "BUGS" +The granularity of the sampling is shown, but remains +statistical at best. +We assume that the time for each execution of a function +can be expressed by the total time for the function divided +by the number of times the function is called. +Thus the time propagated along the call graph arcs to the function's +parents is directly proportional to the number of times that +arc is traversed. +.PP +Parents that are not themselves profiled will have the time of +their profiled children propagated to them, but they will appear +to be spontaneously invoked in the call graph listing, and will +not have their time propagated further. +Similarly, signal catchers, even though profiled, will appear +to be spontaneous (although for more obscure reasons). +Any profiled children of signal catchers should have their times +propagated properly, unless the signal catcher was invoked during +the execution of the profiling routine, in which case all is lost. +.PP +The profiled program must call \f(CW\*(C`exit\*(C'\fR(2) +or return normally for the profiling information to be saved +in the \fIgmon.out\fR file. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fImonitor\fR\|(3), \fIprofil\fR\|(2), \fIcc\fR\|(1), \fIprof\fR\|(1), and the Info entry for \fIgprof\fR. +.PP +\&\*(L"An Execution Profiler for Modular Programs\*(R", +by S. Graham, P. Kessler, M. McKusick; +Software \- Practice and Experience, +Vol. 13, pp. 671\-685, 1983. +.PP +\&\*(L"gprof: A Call Graph Execution Profiler\*(R", +by S. Graham, P. Kessler, M. McKusick; +Proceedings of the \s-1SIGPLAN\s0 '82 Symposium on Compiler Construction, +\&\s-1SIGPLAN\s0 Notices, Vol. 17, No 6, pp. 120\-126, June 1982. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1988, 1992, 1997, 1998, 1999, 2000, 2001, 2003, +2007, 2008, 2009 Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 +or any later version published by the Free Software Foundation; +with no Invariant Sections, with no Front-Cover Texts, and with no +Back-Cover Texts. A copy of the license is included in the +section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". diff --git a/share/man/man1/arm-eabi-ld.1 b/share/man/man1/arm-eabi-ld.1 new file mode 100644 index 0000000..8b5c3d8 --- /dev/null +++ b/share/man/man1/arm-eabi-ld.1 @@ -0,0 +1,2413 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "LD 1" +.TH LD 1 " " "binutils-2.21" "GNU Development Tools" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +ld \- The GNU linker +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +ld [\fBoptions\fR] \fIobjfile\fR ... +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +\&\fBld\fR combines a number of object and archive files, relocates +their data and ties up symbol references. Usually the last step in +compiling a program is to run \fBld\fR. +.PP +\&\fBld\fR accepts Linker Command Language files written in +a superset of \s-1AT&T\s0's Link Editor Command Language syntax, +to provide explicit and total control over the linking process. +.PP +This man page does not describe the command language; see the +\&\fBld\fR entry in \f(CW\*(C`info\*(C'\fR for full details on the command +language and on other aspects of the \s-1GNU\s0 linker. +.PP +This version of \fBld\fR uses the general purpose \s-1BFD\s0 libraries +to operate on object files. This allows \fBld\fR to read, combine, and +write object files in many different formats\-\-\-for example, \s-1COFF\s0 or +\&\f(CW\*(C`a.out\*(C'\fR. Different formats may be linked together to produce any +available kind of object file. +.PP +Aside from its flexibility, the \s-1GNU\s0 linker is more helpful than other +linkers in providing diagnostic information. Many linkers abandon +execution immediately upon encountering an error; whenever possible, +\&\fBld\fR continues executing, allowing you to identify other errors +(or, in some cases, to get an output file in spite of the error). +.PP +The \s-1GNU\s0 linker \fBld\fR is meant to cover a broad range of situations, +and to be as compatible as possible with other linkers. As a result, +you have many choices to control its behavior. +.SH "OPTIONS" +.IX Header "OPTIONS" +The linker supports a plethora of command-line options, but in actual +practice few of them are used in any particular context. +For instance, a frequent use of \fBld\fR is to link standard Unix +object files on a standard, supported Unix system. On such a system, to +link a file \f(CW\*(C`hello.o\*(C'\fR: +.PP +.Vb 1 +\& ld \-o <output> /lib/crt0.o hello.o \-lc +.Ve +.PP +This tells \fBld\fR to produce a file called \fIoutput\fR as the +result of linking the file \f(CW\*(C`/lib/crt0.o\*(C'\fR with \f(CW\*(C`hello.o\*(C'\fR and +the library \f(CW\*(C`libc.a\*(C'\fR, which will come from the standard search +directories. (See the discussion of the \fB\-l\fR option below.) +.PP +Some of the command-line options to \fBld\fR may be specified at any +point in the command line. However, options which refer to files, such +as \fB\-l\fR or \fB\-T\fR, cause the file to be read at the point at +which the option appears in the command line, relative to the object +files and other file options. Repeating non-file options with a +different argument will either have no further effect, or override prior +occurrences (those further to the left on the command line) of that +option. Options which may be meaningfully specified more than once are +noted in the descriptions below. +.PP +Non-option arguments are object files or archives which are to be linked +together. They may follow, precede, or be mixed in with command-line +options, except that an object file argument may not be placed between +an option and its argument. +.PP +Usually the linker is invoked with at least one object file, but you can +specify other forms of binary input files using \fB\-l\fR, \fB\-R\fR, +and the script command language. If \fIno\fR binary input files at all +are specified, the linker does not produce any output, and issues the +message \fBNo input files\fR. +.PP +If the linker cannot recognize the format of an object file, it will +assume that it is a linker script. A script specified in this way +augments the main linker script used for the link (either the default +linker script or the one specified by using \fB\-T\fR). This feature +permits the linker to link against a file which appears to be an object +or an archive, but actually merely defines some symbol values, or uses +\&\f(CW\*(C`INPUT\*(C'\fR or \f(CW\*(C`GROUP\*(C'\fR to load other objects. Specifying a +script in this way merely augments the main linker script, with the +extra commands placed after the main script; use the \fB\-T\fR option +to replace the default linker script entirely, but note the effect of +the \f(CW\*(C`INSERT\*(C'\fR command. +.PP +For options whose names are a single letter, +option arguments must either follow the option letter without intervening +whitespace, or be given as separate arguments immediately following the +option that requires them. +.PP +For options whose names are multiple letters, either one dash or two can +precede the option name; for example, \fB\-trace\-symbol\fR and +\&\fB\-\-trace\-symbol\fR are equivalent. Note\-\-\-there is one exception to +this rule. Multiple letter options that start with a lower case 'o' can +only be preceded by two dashes. This is to reduce confusion with the +\&\fB\-o\fR option. So for example \fB\-omagic\fR sets the output file +name to \fBmagic\fR whereas \fB\-\-omagic\fR sets the \s-1NMAGIC\s0 flag on the +output. +.PP +Arguments to multiple-letter options must either be separated from the +option name by an equals sign, or be given as separate arguments +immediately following the option that requires them. For example, +\&\fB\-\-trace\-symbol foo\fR and \fB\-\-trace\-symbol=foo\fR are equivalent. +Unique abbreviations of the names of multiple-letter options are +accepted. +.PP +Note\-\-\-if the linker is being invoked indirectly, via a compiler driver +(e.g. \fBgcc\fR) then all the linker command line options should be +prefixed by \fB\-Wl,\fR (or whatever is appropriate for the particular +compiler driver) like this: +.PP +.Vb 1 +\& gcc \-Wl,\-\-start\-group foo.o bar.o \-Wl,\-\-end\-group +.Ve +.PP +This is important, because otherwise the compiler driver program may +silently drop the linker options, resulting in a bad link. Confusion +may also arise when passing options that require values through a +driver, as the use of a space between option and argument acts as +a separator, and causes the driver to pass only the option to the linker +and the argument to the compiler. In this case, it is simplest to use +the joined forms of both single\- and multiple-letter options, such as: +.PP +.Vb 1 +\& gcc foo.o bar.o \-Wl,\-eENTRY \-Wl,\-Map=a.map +.Ve +.PP +Here is a table of the generic command line switches accepted by the \s-1GNU\s0 +linker: +.IP "\fB@\fR\fIfile\fR" 4 +.IX Item "@file" +Read command-line options from \fIfile\fR. The options read are +inserted in place of the original @\fIfile\fR option. If \fIfile\fR +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +.Sp +Options in \fIfile\fR are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The \fIfile\fR may itself contain additional +@\fIfile\fR options; any such options will be processed recursively. +.IP "\fB\-a\fR \fIkeyword\fR" 4 +.IX Item "-a keyword" +This option is supported for \s-1HP/UX\s0 compatibility. The \fIkeyword\fR +argument must be one of the strings \fBarchive\fR, \fBshared\fR, or +\&\fBdefault\fR. \fB\-aarchive\fR is functionally equivalent to +\&\fB\-Bstatic\fR, and the other two keywords are functionally equivalent +to \fB\-Bdynamic\fR. This option may be used any number of times. +.IP "\fB\-\-audit\fR \fI\s-1AUDITLIB\s0\fR" 4 +.IX Item "--audit AUDITLIB" +Adds \fI\s-1AUDITLIB\s0\fR to the \f(CW\*(C`DT_AUDIT\*(C'\fR entry of the dynamic section. +\&\fI\s-1AUDITLIB\s0\fR is not checked for existence, nor will it use the \s-1DT_SONAME\s0 +specified in the library. If specified multiple times \f(CW\*(C`DT_AUDIT\*(C'\fR +will contain a colon separated list of audit interfaces to use. If the linker +finds an object with an audit entry while searching for shared libraries, +it will add a corresponding \f(CW\*(C`DT_DEPAUDIT\*(C'\fR entry in the output file. +This option is only meaningful on \s-1ELF\s0 platforms supporting the rtld-audit +interface. +.IP "\fB\-A\fR \fIarchitecture\fR" 4 +.IX Item "-A architecture" +.PD 0 +.IP "\fB\-\-architecture=\fR\fIarchitecture\fR" 4 +.IX Item "--architecture=architecture" +.PD +In the current release of \fBld\fR, this option is useful only for the +Intel 960 family of architectures. In that \fBld\fR configuration, the +\&\fIarchitecture\fR argument identifies the particular architecture in +the 960 family, enabling some safeguards and modifying the +archive-library search path. +.Sp +Future releases of \fBld\fR may support similar functionality for +other architecture families. +.IP "\fB\-b\fR \fIinput-format\fR" 4 +.IX Item "-b input-format" +.PD 0 +.IP "\fB\-\-format=\fR\fIinput-format\fR" 4 +.IX Item "--format=input-format" +.PD +\&\fBld\fR may be configured to support more than one kind of object +file. If your \fBld\fR is configured this way, you can use the +\&\fB\-b\fR option to specify the binary format for input object files +that follow this option on the command line. Even when \fBld\fR is +configured to support alternative object formats, you don't usually need +to specify this, as \fBld\fR should be configured to expect as a +default input format the most usual format on each machine. +\&\fIinput-format\fR is a text string, the name of a particular format +supported by the \s-1BFD\s0 libraries. (You can list the available binary +formats with \fBobjdump \-i\fR.) +.Sp +You may want to use this option if you are linking files with an unusual +binary format. You can also use \fB\-b\fR to switch formats explicitly (when +linking object files of different formats), by including +\&\fB\-b\fR \fIinput-format\fR before each group of object files in a +particular format. +.Sp +The default format is taken from the environment variable +\&\f(CW\*(C`GNUTARGET\*(C'\fR. +.Sp +You can also define the input format from a script, using the command +\&\f(CW\*(C`TARGET\*(C'\fR; +.IP "\fB\-c\fR \fIMRI-commandfile\fR" 4 +.IX Item "-c MRI-commandfile" +.PD 0 +.IP "\fB\-\-mri\-script=\fR\fIMRI-commandfile\fR" 4 +.IX Item "--mri-script=MRI-commandfile" +.PD +For compatibility with linkers produced by \s-1MRI\s0, \fBld\fR accepts script +files written in an alternate, restricted command language, described in +the \s-1MRI\s0 Compatible Script Files section of \s-1GNU\s0 ld documentation. +Introduce \s-1MRI\s0 script files with +the option \fB\-c\fR; use the \fB\-T\fR option to run linker +scripts written in the general-purpose \fBld\fR scripting language. +If \fIMRI-cmdfile\fR does not exist, \fBld\fR looks for it in the directories +specified by any \fB\-L\fR options. +.IP "\fB\-d\fR" 4 +.IX Item "-d" +.PD 0 +.IP "\fB\-dc\fR" 4 +.IX Item "-dc" +.IP "\fB\-dp\fR" 4 +.IX Item "-dp" +.PD +These three options are equivalent; multiple forms are supported for +compatibility with other linkers. They assign space to common symbols +even if a relocatable output file is specified (with \fB\-r\fR). The +script command \f(CW\*(C`FORCE_COMMON_ALLOCATION\*(C'\fR has the same effect. +.IP "\fB\-\-depaudit\fR \fI\s-1AUDITLIB\s0\fR" 4 +.IX Item "--depaudit AUDITLIB" +.PD 0 +.IP "\fB\-P\fR \fI\s-1AUDITLIB\s0\fR" 4 +.IX Item "-P AUDITLIB" +.PD +Adds \fI\s-1AUDITLIB\s0\fR to the \f(CW\*(C`DT_DEPAUDIT\*(C'\fR entry of the dynamic section. +\&\fI\s-1AUDITLIB\s0\fR is not checked for existence, nor will it use the \s-1DT_SONAME\s0 +specified in the library. If specified multiple times \f(CW\*(C`DT_DEPAUDIT\*(C'\fR +will contain a colon separated list of audit interfaces to use. This +option is only meaningful on \s-1ELF\s0 platforms supporting the rtld-audit interface. +The \-P option is provided for Solaris compatibility. +.IP "\fB\-e\fR \fIentry\fR" 4 +.IX Item "-e entry" +.PD 0 +.IP "\fB\-\-entry=\fR\fIentry\fR" 4 +.IX Item "--entry=entry" +.PD +Use \fIentry\fR as the explicit symbol for beginning execution of your +program, rather than the default entry point. If there is no symbol +named \fIentry\fR, the linker will try to parse \fIentry\fR as a number, +and use that as the entry address (the number will be interpreted in +base 10; you may use a leading \fB0x\fR for base 16, or a leading +\&\fB0\fR for base 8). +.IP "\fB\-\-exclude\-libs\fR \fIlib\fR\fB,\fR\fIlib\fR\fB,...\fR" 4 +.IX Item "--exclude-libs lib,lib,..." +Specifies a list of archive libraries from which symbols should not be automatically +exported. The library names may be delimited by commas or colons. Specifying +\&\f(CW\*(C`\-\-exclude\-libs ALL\*(C'\fR excludes symbols in all archive libraries from +automatic export. This option is available only for the i386 \s-1PE\s0 targeted +port of the linker and for \s-1ELF\s0 targeted ports. For i386 \s-1PE\s0, symbols +explicitly listed in a .def file are still exported, regardless of this +option. For \s-1ELF\s0 targeted ports, symbols affected by this option will +be treated as hidden. +.IP "\fB\-\-exclude\-modules\-for\-implib\fR \fImodule\fR\fB,\fR\fImodule\fR\fB,...\fR" 4 +.IX Item "--exclude-modules-for-implib module,module,..." +Specifies a list of object files or archive members, from which symbols +should not be automatically exported, but which should be copied wholesale +into the import library being generated during the link. The module names +may be delimited by commas or colons, and must match exactly the filenames +used by \fBld\fR to open the files; for archive members, this is simply +the member name, but for object files the name listed must include and +match precisely any path used to specify the input file on the linker's +command-line. This option is available only for the i386 \s-1PE\s0 targeted port +of the linker. Symbols explicitly listed in a .def file are still exported, +regardless of this option. +.IP "\fB\-E\fR" 4 +.IX Item "-E" +.PD 0 +.IP "\fB\-\-export\-dynamic\fR" 4 +.IX Item "--export-dynamic" +.IP "\fB\-\-no\-export\-dynamic\fR" 4 +.IX Item "--no-export-dynamic" +.PD +When creating a dynamically linked executable, using the \fB\-E\fR +option or the \fB\-\-export\-dynamic\fR option causes the linker to add +all symbols to the dynamic symbol table. The dynamic symbol table is the +set of symbols which are visible from dynamic objects at run time. +.Sp +If you do not use either of these options (or use the +\&\fB\-\-no\-export\-dynamic\fR option to restore the default behavior), the +dynamic symbol table will normally contain only those symbols which are +referenced by some dynamic object mentioned in the link. +.Sp +If you use \f(CW\*(C`dlopen\*(C'\fR to load a dynamic object which needs to refer +back to the symbols defined by the program, rather than some other +dynamic object, then you will probably need to use this option when +linking the program itself. +.Sp +You can also use the dynamic list to control what symbols should +be added to the dynamic symbol table if the output format supports it. +See the description of \fB\-\-dynamic\-list\fR. +.Sp +Note that this option is specific to \s-1ELF\s0 targeted ports. \s-1PE\s0 targets +support a similar function to export all symbols from a \s-1DLL\s0 or \s-1EXE\s0; see +the description of \fB\-\-export\-all\-symbols\fR below. +.IP "\fB\-EB\fR" 4 +.IX Item "-EB" +Link big-endian objects. This affects the default output format. +.IP "\fB\-EL\fR" 4 +.IX Item "-EL" +Link little-endian objects. This affects the default output format. +.IP "\fB\-f\fR \fIname\fR" 4 +.IX Item "-f name" +.PD 0 +.IP "\fB\-\-auxiliary=\fR\fIname\fR" 4 +.IX Item "--auxiliary=name" +.PD +When creating an \s-1ELF\s0 shared object, set the internal \s-1DT_AUXILIARY\s0 field +to the specified name. This tells the dynamic linker that the symbol +table of the shared object should be used as an auxiliary filter on the +symbol table of the shared object \fIname\fR. +.Sp +If you later link a program against this filter object, then, when you +run the program, the dynamic linker will see the \s-1DT_AUXILIARY\s0 field. If +the dynamic linker resolves any symbols from the filter object, it will +first check whether there is a definition in the shared object +\&\fIname\fR. If there is one, it will be used instead of the definition +in the filter object. The shared object \fIname\fR need not exist. +Thus the shared object \fIname\fR may be used to provide an alternative +implementation of certain functions, perhaps for debugging or for +machine specific performance. +.Sp +This option may be specified more than once. The \s-1DT_AUXILIARY\s0 entries +will be created in the order in which they appear on the command line. +.IP "\fB\-F\fR \fIname\fR" 4 +.IX Item "-F name" +.PD 0 +.IP "\fB\-\-filter=\fR\fIname\fR" 4 +.IX Item "--filter=name" +.PD +When creating an \s-1ELF\s0 shared object, set the internal \s-1DT_FILTER\s0 field to +the specified name. This tells the dynamic linker that the symbol table +of the shared object which is being created should be used as a filter +on the symbol table of the shared object \fIname\fR. +.Sp +If you later link a program against this filter object, then, when you +run the program, the dynamic linker will see the \s-1DT_FILTER\s0 field. The +dynamic linker will resolve symbols according to the symbol table of the +filter object as usual, but it will actually link to the definitions +found in the shared object \fIname\fR. Thus the filter object can be +used to select a subset of the symbols provided by the object +\&\fIname\fR. +.Sp +Some older linkers used the \fB\-F\fR option throughout a compilation +toolchain for specifying object-file format for both input and output +object files. +The \s-1GNU\s0 linker uses other mechanisms for this purpose: the +\&\fB\-b\fR, \fB\-\-format\fR, \fB\-\-oformat\fR options, the +\&\f(CW\*(C`TARGET\*(C'\fR command in linker scripts, and the \f(CW\*(C`GNUTARGET\*(C'\fR +environment variable. +The \s-1GNU\s0 linker will ignore the \fB\-F\fR option when not +creating an \s-1ELF\s0 shared object. +.IP "\fB\-fini=\fR\fIname\fR" 4 +.IX Item "-fini=name" +When creating an \s-1ELF\s0 executable or shared object, call \s-1NAME\s0 when the +executable or shared object is unloaded, by setting \s-1DT_FINI\s0 to the +address of the function. By default, the linker uses \f(CW\*(C`_fini\*(C'\fR as +the function to call. +.IP "\fB\-g\fR" 4 +.IX Item "-g" +Ignored. Provided for compatibility with other tools. +.IP "\fB\-G\fR \fIvalue\fR" 4 +.IX Item "-G value" +.PD 0 +.IP "\fB\-\-gpsize=\fR\fIvalue\fR" 4 +.IX Item "--gpsize=value" +.PD +Set the maximum size of objects to be optimized using the \s-1GP\s0 register to +\&\fIsize\fR. This is only meaningful for object file formats such as +\&\s-1MIPS\s0 \s-1ECOFF\s0 which supports putting large and small objects into different +sections. This is ignored for other object file formats. +.IP "\fB\-h\fR \fIname\fR" 4 +.IX Item "-h name" +.PD 0 +.IP "\fB\-soname=\fR\fIname\fR" 4 +.IX Item "-soname=name" +.PD +When creating an \s-1ELF\s0 shared object, set the internal \s-1DT_SONAME\s0 field to +the specified name. When an executable is linked with a shared object +which has a \s-1DT_SONAME\s0 field, then when the executable is run the dynamic +linker will attempt to load the shared object specified by the \s-1DT_SONAME\s0 +field rather than the using the file name given to the linker. +.IP "\fB\-i\fR" 4 +.IX Item "-i" +Perform an incremental link (same as option \fB\-r\fR). +.IP "\fB\-init=\fR\fIname\fR" 4 +.IX Item "-init=name" +When creating an \s-1ELF\s0 executable or shared object, call \s-1NAME\s0 when the +executable or shared object is loaded, by setting \s-1DT_INIT\s0 to the address +of the function. By default, the linker uses \f(CW\*(C`_init\*(C'\fR as the +function to call. +.IP "\fB\-l\fR \fInamespec\fR" 4 +.IX Item "-l namespec" +.PD 0 +.IP "\fB\-\-library=\fR\fInamespec\fR" 4 +.IX Item "--library=namespec" +.PD +Add the archive or object file specified by \fInamespec\fR to the +list of files to link. This option may be used any number of times. +If \fInamespec\fR is of the form \fI:\fIfilename\fI\fR, \fBld\fR +will search the library path for a file called \fIfilename\fR, otherwise it +will search the library path for a file called \fIlib\fInamespec\fI.a\fR. +.Sp +On systems which support shared libraries, \fBld\fR may also search for +files other than \fIlib\fInamespec\fI.a\fR. Specifically, on \s-1ELF\s0 +and SunOS systems, \fBld\fR will search a directory for a library +called \fIlib\fInamespec\fI.so\fR before searching for one called +\&\fIlib\fInamespec\fI.a\fR. (By convention, a \f(CW\*(C`.so\*(C'\fR extension +indicates a shared library.) Note that this behavior does not apply +to \fI:\fIfilename\fI\fR, which always specifies a file called +\&\fIfilename\fR. +.Sp +The linker will search an archive only once, at the location where it is +specified on the command line. If the archive defines a symbol which +was undefined in some object which appeared before the archive on the +command line, the linker will include the appropriate file(s) from the +archive. However, an undefined symbol in an object appearing later on +the command line will not cause the linker to search the archive again. +.Sp +See the \fB\-(\fR option for a way to force the linker to search +archives multiple times. +.Sp +You may list the same archive multiple times on the command line. +.Sp +This type of archive searching is standard for Unix linkers. However, +if you are using \fBld\fR on \s-1AIX\s0, note that it is different from the +behaviour of the \s-1AIX\s0 linker. +.IP "\fB\-L\fR \fIsearchdir\fR" 4 +.IX Item "-L searchdir" +.PD 0 +.IP "\fB\-\-library\-path=\fR\fIsearchdir\fR" 4 +.IX Item "--library-path=searchdir" +.PD +Add path \fIsearchdir\fR to the list of paths that \fBld\fR will search +for archive libraries and \fBld\fR control scripts. You may use this +option any number of times. The directories are searched in the order +in which they are specified on the command line. Directories specified +on the command line are searched before the default directories. All +\&\fB\-L\fR options apply to all \fB\-l\fR options, regardless of the +order in which the options appear. \fB\-L\fR options do not affect +how \fBld\fR searches for a linker script unless \fB\-T\fR +option is specified. +.Sp +If \fIsearchdir\fR begins with \f(CW\*(C`=\*(C'\fR, then the \f(CW\*(C`=\*(C'\fR will be replaced +by the \fIsysroot prefix\fR, a path specified when the linker is configured. +.Sp +The default set of paths searched (without being specified with +\&\fB\-L\fR) depends on which emulation mode \fBld\fR is using, and in +some cases also on how it was configured. +.Sp +The paths can also be specified in a link script with the +\&\f(CW\*(C`SEARCH_DIR\*(C'\fR command. Directories specified this way are searched +at the point in which the linker script appears in the command line. +.IP "\fB\-m\fR \fIemulation\fR" 4 +.IX Item "-m emulation" +Emulate the \fIemulation\fR linker. You can list the available +emulations with the \fB\-\-verbose\fR or \fB\-V\fR options. +.Sp +If the \fB\-m\fR option is not used, the emulation is taken from the +\&\f(CW\*(C`LDEMULATION\*(C'\fR environment variable, if that is defined. +.Sp +Otherwise, the default emulation depends upon how the linker was +configured. +.IP "\fB\-M\fR" 4 +.IX Item "-M" +.PD 0 +.IP "\fB\-\-print\-map\fR" 4 +.IX Item "--print-map" +.PD +Print a link map to the standard output. A link map provides +information about the link, including the following: +.RS 4 +.IP "\(bu" 4 +Where object files are mapped into memory. +.IP "\(bu" 4 +How common symbols are allocated. +.IP "\(bu" 4 +All archive members included in the link, with a mention of the symbol +which caused the archive member to be brought in. +.IP "\(bu" 4 +The values assigned to symbols. +.Sp +Note \- symbols whose values are computed by an expression which +involves a reference to a previous value of the same symbol may not +have correct result displayed in the link map. This is because the +linker discards intermediate results and only retains the final value +of an expression. Under such circumstances the linker will display +the final value enclosed by square brackets. Thus for example a +linker script containing: +.Sp +.Vb 3 +\& foo = 1 +\& foo = foo * 4 +\& foo = foo + 8 +.Ve +.Sp +will produce the following output in the link map if the \fB\-M\fR +option is used: +.Sp +.Vb 3 +\& 0x00000001 foo = 0x1 +\& [0x0000000c] foo = (foo * 0x4) +\& [0x0000000c] foo = (foo + 0x8) +.Ve +.Sp +See \fBExpressions\fR for more information about expressions in linker +scripts. +.RE +.RS 4 +.RE +.IP "\fB\-n\fR" 4 +.IX Item "-n" +.PD 0 +.IP "\fB\-\-nmagic\fR" 4 +.IX Item "--nmagic" +.PD +Turn off page alignment of sections, and disable linking against shared +libraries. If the output format supports Unix style magic numbers, +mark the output as \f(CW\*(C`NMAGIC\*(C'\fR. +.IP "\fB\-N\fR" 4 +.IX Item "-N" +.PD 0 +.IP "\fB\-\-omagic\fR" 4 +.IX Item "--omagic" +.PD +Set the text and data sections to be readable and writable. Also, do +not page-align the data segment, and disable linking against shared +libraries. If the output format supports Unix style magic numbers, +mark the output as \f(CW\*(C`OMAGIC\*(C'\fR. Note: Although a writable text section +is allowed for PE-COFF targets, it does not conform to the format +specification published by Microsoft. +.IP "\fB\-\-no\-omagic\fR" 4 +.IX Item "--no-omagic" +This option negates most of the effects of the \fB\-N\fR option. It +sets the text section to be read-only, and forces the data segment to +be page-aligned. Note \- this option does not enable linking against +shared libraries. Use \fB\-Bdynamic\fR for this. +.IP "\fB\-o\fR \fIoutput\fR" 4 +.IX Item "-o output" +.PD 0 +.IP "\fB\-\-output=\fR\fIoutput\fR" 4 +.IX Item "--output=output" +.PD +Use \fIoutput\fR as the name for the program produced by \fBld\fR; if this +option is not specified, the name \fIa.out\fR is used by default. The +script command \f(CW\*(C`OUTPUT\*(C'\fR can also specify the output file name. +.IP "\fB\-O\fR \fIlevel\fR" 4 +.IX Item "-O level" +If \fIlevel\fR is a numeric values greater than zero \fBld\fR optimizes +the output. This might take significantly longer and therefore probably +should only be enabled for the final binary. At the moment this +option only affects \s-1ELF\s0 shared library generation. Future releases of +the linker may make more use of this option. Also currently there is +no difference in the linker's behaviour for different non-zero values +of this option. Again this may change with future releases. +.IP "\fB\-q\fR" 4 +.IX Item "-q" +.PD 0 +.IP "\fB\-\-emit\-relocs\fR" 4 +.IX Item "--emit-relocs" +.PD +Leave relocation sections and contents in fully linked executables. +Post link analysis and optimization tools may need this information in +order to perform correct modifications of executables. This results +in larger executables. +.Sp +This option is currently only supported on \s-1ELF\s0 platforms. +.IP "\fB\-\-force\-dynamic\fR" 4 +.IX Item "--force-dynamic" +Force the output file to have dynamic sections. This option is specific +to VxWorks targets. +.IP "\fB\-r\fR" 4 +.IX Item "-r" +.PD 0 +.IP "\fB\-\-relocatable\fR" 4 +.IX Item "--relocatable" +.PD +Generate relocatable output\-\-\-i.e., generate an output file that can in +turn serve as input to \fBld\fR. This is often called \fIpartial +linking\fR. As a side effect, in environments that support standard Unix +magic numbers, this option also sets the output file's magic number to +\&\f(CW\*(C`OMAGIC\*(C'\fR. +If this option is not specified, an absolute file is produced. When +linking \*(C+ programs, this option \fIwill not\fR resolve references to +constructors; to do that, use \fB\-Ur\fR. +.Sp +When an input file does not have the same format as the output file, +partial linking is only supported if that input file does not contain any +relocations. Different output formats can have further restrictions; for +example some \f(CW\*(C`a.out\*(C'\fR\-based formats do not support partial linking +with input files in other formats at all. +.Sp +This option does the same thing as \fB\-i\fR. +.IP "\fB\-R\fR \fIfilename\fR" 4 +.IX Item "-R filename" +.PD 0 +.IP "\fB\-\-just\-symbols=\fR\fIfilename\fR" 4 +.IX Item "--just-symbols=filename" +.PD +Read symbol names and their addresses from \fIfilename\fR, but do not +relocate it or include it in the output. This allows your output file +to refer symbolically to absolute locations of memory defined in other +programs. You may use this option more than once. +.Sp +For compatibility with other \s-1ELF\s0 linkers, if the \fB\-R\fR option is +followed by a directory name, rather than a file name, it is treated as +the \fB\-rpath\fR option. +.IP "\fB\-s\fR" 4 +.IX Item "-s" +.PD 0 +.IP "\fB\-\-strip\-all\fR" 4 +.IX Item "--strip-all" +.PD +Omit all symbol information from the output file. +.IP "\fB\-S\fR" 4 +.IX Item "-S" +.PD 0 +.IP "\fB\-\-strip\-debug\fR" 4 +.IX Item "--strip-debug" +.PD +Omit debugger symbol information (but not all symbols) from the output file. +.IP "\fB\-t\fR" 4 +.IX Item "-t" +.PD 0 +.IP "\fB\-\-trace\fR" 4 +.IX Item "--trace" +.PD +Print the names of the input files as \fBld\fR processes them. +.IP "\fB\-T\fR \fIscriptfile\fR" 4 +.IX Item "-T scriptfile" +.PD 0 +.IP "\fB\-\-script=\fR\fIscriptfile\fR" 4 +.IX Item "--script=scriptfile" +.PD +Use \fIscriptfile\fR as the linker script. This script replaces +\&\fBld\fR's default linker script (rather than adding to it), so +\&\fIcommandfile\fR must specify everything necessary to describe the +output file. If \fIscriptfile\fR does not exist in +the current directory, \f(CW\*(C`ld\*(C'\fR looks for it in the directories +specified by any preceding \fB\-L\fR options. Multiple \fB\-T\fR +options accumulate. +.IP "\fB\-dT\fR \fIscriptfile\fR" 4 +.IX Item "-dT scriptfile" +.PD 0 +.IP "\fB\-\-default\-script=\fR\fIscriptfile\fR" 4 +.IX Item "--default-script=scriptfile" +.PD +Use \fIscriptfile\fR as the default linker script. +.Sp +This option is similar to the \fB\-\-script\fR option except that +processing of the script is delayed until after the rest of the +command line has been processed. This allows options placed after the +\&\fB\-\-default\-script\fR option on the command line to affect the +behaviour of the linker script, which can be important when the linker +command line cannot be directly controlled by the user. (eg because +the command line is being constructed by another tool, such as +\&\fBgcc\fR). +.IP "\fB\-u\fR \fIsymbol\fR" 4 +.IX Item "-u symbol" +.PD 0 +.IP "\fB\-\-undefined=\fR\fIsymbol\fR" 4 +.IX Item "--undefined=symbol" +.PD +Force \fIsymbol\fR to be entered in the output file as an undefined +symbol. Doing this may, for example, trigger linking of additional +modules from standard libraries. \fB\-u\fR may be repeated with +different option arguments to enter additional undefined symbols. This +option is equivalent to the \f(CW\*(C`EXTERN\*(C'\fR linker script command. +.IP "\fB\-Ur\fR" 4 +.IX Item "-Ur" +For anything other than \*(C+ programs, this option is equivalent to +\&\fB\-r\fR: it generates relocatable output\-\-\-i.e., an output file that can in +turn serve as input to \fBld\fR. When linking \*(C+ programs, \fB\-Ur\fR +\&\fIdoes\fR resolve references to constructors, unlike \fB\-r\fR. +It does not work to use \fB\-Ur\fR on files that were themselves linked +with \fB\-Ur\fR; once the constructor table has been built, it cannot +be added to. Use \fB\-Ur\fR only for the last partial link, and +\&\fB\-r\fR for the others. +.IP "\fB\-\-unique[=\fR\fI\s-1SECTION\s0\fR\fB]\fR" 4 +.IX Item "--unique[=SECTION]" +Creates a separate output section for every input section matching +\&\fI\s-1SECTION\s0\fR, or if the optional wildcard \fI\s-1SECTION\s0\fR argument is +missing, for every orphan input section. An orphan section is one not +specifically mentioned in a linker script. You may use this option +multiple times on the command line; It prevents the normal merging of +input sections with the same name, overriding output section assignments +in a linker script. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +.PD 0 +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +.IP "\fB\-V\fR" 4 +.IX Item "-V" +.PD +Display the version number for \fBld\fR. The \fB\-V\fR option also +lists the supported emulations. +.IP "\fB\-x\fR" 4 +.IX Item "-x" +.PD 0 +.IP "\fB\-\-discard\-all\fR" 4 +.IX Item "--discard-all" +.PD +Delete all local symbols. +.IP "\fB\-X\fR" 4 +.IX Item "-X" +.PD 0 +.IP "\fB\-\-discard\-locals\fR" 4 +.IX Item "--discard-locals" +.PD +Delete all temporary local symbols. (These symbols start with +system-specific local label prefixes, typically \fB.L\fR for \s-1ELF\s0 systems +or \fBL\fR for traditional a.out systems.) +.IP "\fB\-y\fR \fIsymbol\fR" 4 +.IX Item "-y symbol" +.PD 0 +.IP "\fB\-\-trace\-symbol=\fR\fIsymbol\fR" 4 +.IX Item "--trace-symbol=symbol" +.PD +Print the name of each linked file in which \fIsymbol\fR appears. This +option may be given any number of times. On many systems it is necessary +to prepend an underscore. +.Sp +This option is useful when you have an undefined symbol in your link but +don't know where the reference is coming from. +.IP "\fB\-Y\fR \fIpath\fR" 4 +.IX Item "-Y path" +Add \fIpath\fR to the default library search path. This option exists +for Solaris compatibility. +.IP "\fB\-z\fR \fIkeyword\fR" 4 +.IX Item "-z keyword" +The recognized keywords are: +.RS 4 +.IP "\fBcombreloc\fR" 4 +.IX Item "combreloc" +Combines multiple reloc sections and sorts them to make dynamic symbol +lookup caching possible. +.IP "\fBdefs\fR" 4 +.IX Item "defs" +Disallows undefined symbols in object files. Undefined symbols in +shared libraries are still allowed. +.IP "\fBexecstack\fR" 4 +.IX Item "execstack" +Marks the object as requiring executable stack. +.IP "\fBinitfirst\fR" 4 +.IX Item "initfirst" +This option is only meaningful when building a shared object. +It marks the object so that its runtime initialization will occur +before the runtime initialization of any other objects brought into +the process at the same time. Similarly the runtime finalization of +the object will occur after the runtime finalization of any other +objects. +.IP "\fBinterpose\fR" 4 +.IX Item "interpose" +Marks the object that its symbol table interposes before all symbols +but the primary executable. +.IP "\fBlazy\fR" 4 +.IX Item "lazy" +When generating an executable or shared library, mark it to tell the +dynamic linker to defer function call resolution to the point when +the function is called (lazy binding), rather than at load time. +Lazy binding is the default. +.IP "\fBloadfltr\fR" 4 +.IX Item "loadfltr" +Marks the object that its filters be processed immediately at +runtime. +.IP "\fBmuldefs\fR" 4 +.IX Item "muldefs" +Allows multiple definitions. +.IP "\fBnocombreloc\fR" 4 +.IX Item "nocombreloc" +Disables multiple reloc sections combining. +.IP "\fBnocopyreloc\fR" 4 +.IX Item "nocopyreloc" +Disables production of copy relocs. +.IP "\fBnodefaultlib\fR" 4 +.IX Item "nodefaultlib" +Marks the object that the search for dependencies of this object will +ignore any default library search paths. +.IP "\fBnodelete\fR" 4 +.IX Item "nodelete" +Marks the object shouldn't be unloaded at runtime. +.IP "\fBnodlopen\fR" 4 +.IX Item "nodlopen" +Marks the object not available to \f(CW\*(C`dlopen\*(C'\fR. +.IP "\fBnodump\fR" 4 +.IX Item "nodump" +Marks the object can not be dumped by \f(CW\*(C`dldump\*(C'\fR. +.IP "\fBnoexecstack\fR" 4 +.IX Item "noexecstack" +Marks the object as not requiring executable stack. +.IP "\fBnorelro\fR" 4 +.IX Item "norelro" +Don't create an \s-1ELF\s0 \f(CW\*(C`PT_GNU_RELRO\*(C'\fR segment header in the object. +.IP "\fBnow\fR" 4 +.IX Item "now" +When generating an executable or shared library, mark it to tell the +dynamic linker to resolve all symbols when the program is started, or +when the shared library is linked to using dlopen, instead of +deferring function call resolution to the point when the function is +first called. +.IP "\fBorigin\fR" 4 +.IX Item "origin" +Marks the object may contain \f(CW$ORIGIN\fR. +.IP "\fBrelro\fR" 4 +.IX Item "relro" +Create an \s-1ELF\s0 \f(CW\*(C`PT_GNU_RELRO\*(C'\fR segment header in the object. +.IP "\fBmax\-page\-size=\fR\fIvalue\fR" 4 +.IX Item "max-page-size=value" +Set the emulation maximum page size to \fIvalue\fR. +.IP "\fBcommon\-page\-size=\fR\fIvalue\fR" 4 +.IX Item "common-page-size=value" +Set the emulation common page size to \fIvalue\fR. +.RE +.RS 4 +.Sp +Other keywords are ignored for Solaris compatibility. +.RE +.IP "\fB\-(\fR \fIarchives\fR \fB\-)\fR" 4 +.IX Item "-( archives -)" +.PD 0 +.IP "\fB\-\-start\-group\fR \fIarchives\fR \fB\-\-end\-group\fR" 4 +.IX Item "--start-group archives --end-group" +.PD +The \fIarchives\fR should be a list of archive files. They may be +either explicit file names, or \fB\-l\fR options. +.Sp +The specified archives are searched repeatedly until no new undefined +references are created. Normally, an archive is searched only once in +the order that it is specified on the command line. If a symbol in that +archive is needed to resolve an undefined symbol referred to by an +object in an archive that appears later on the command line, the linker +would not be able to resolve that reference. By grouping the archives, +they all be searched repeatedly until all possible references are +resolved. +.Sp +Using this option has a significant performance cost. It is best to use +it only when there are unavoidable circular references between two or +more archives. +.IP "\fB\-\-accept\-unknown\-input\-arch\fR" 4 +.IX Item "--accept-unknown-input-arch" +.PD 0 +.IP "\fB\-\-no\-accept\-unknown\-input\-arch\fR" 4 +.IX Item "--no-accept-unknown-input-arch" +.PD +Tells the linker to accept input files whose architecture cannot be +recognised. The assumption is that the user knows what they are doing +and deliberately wants to link in these unknown input files. This was +the default behaviour of the linker, before release 2.14. The default +behaviour from release 2.14 onwards is to reject such input files, and +so the \fB\-\-accept\-unknown\-input\-arch\fR option has been added to +restore the old behaviour. +.IP "\fB\-\-as\-needed\fR" 4 +.IX Item "--as-needed" +.PD 0 +.IP "\fB\-\-no\-as\-needed\fR" 4 +.IX Item "--no-as-needed" +.PD +This option affects \s-1ELF\s0 \s-1DT_NEEDED\s0 tags for dynamic libraries mentioned +on the command line after the \fB\-\-as\-needed\fR option. Normally +the linker will add a \s-1DT_NEEDED\s0 tag for each dynamic library mentioned +on the command line, regardless of whether the library is actually +needed or not. \fB\-\-as\-needed\fR causes a \s-1DT_NEEDED\s0 tag to only be +emitted for a library that satisfies an undefined symbol reference +from a regular object file or, if the library is not found in the +\&\s-1DT_NEEDED\s0 lists of other libraries linked up to that point, an +undefined symbol reference from another dynamic library. +\&\fB\-\-no\-as\-needed\fR restores the default behaviour. +.IP "\fB\-\-add\-needed\fR" 4 +.IX Item "--add-needed" +.PD 0 +.IP "\fB\-\-no\-add\-needed\fR" 4 +.IX Item "--no-add-needed" +.PD +These two options have been deprecated because of the similarity of +their names to the \fB\-\-as\-needed\fR and \fB\-\-no\-as\-needed\fR +options. They have been replaced by \fB\-\-copy\-dt\-needed\-entries\fR +and \fB\-\-no\-copy\-dt\-needed\-entries\fR. +.IP "\fB\-assert\fR \fIkeyword\fR" 4 +.IX Item "-assert keyword" +This option is ignored for SunOS compatibility. +.IP "\fB\-Bdynamic\fR" 4 +.IX Item "-Bdynamic" +.PD 0 +.IP "\fB\-dy\fR" 4 +.IX Item "-dy" +.IP "\fB\-call_shared\fR" 4 +.IX Item "-call_shared" +.PD +Link against dynamic libraries. This is only meaningful on platforms +for which shared libraries are supported. This option is normally the +default on such platforms. The different variants of this option are +for compatibility with various systems. You may use this option +multiple times on the command line: it affects library searching for +\&\fB\-l\fR options which follow it. +.IP "\fB\-Bgroup\fR" 4 +.IX Item "-Bgroup" +Set the \f(CW\*(C`DF_1_GROUP\*(C'\fR flag in the \f(CW\*(C`DT_FLAGS_1\*(C'\fR entry in the dynamic +section. This causes the runtime linker to handle lookups in this +object and its dependencies to be performed only inside the group. +\&\fB\-\-unresolved\-symbols=report\-all\fR is implied. This option is +only meaningful on \s-1ELF\s0 platforms which support shared libraries. +.IP "\fB\-Bstatic\fR" 4 +.IX Item "-Bstatic" +.PD 0 +.IP "\fB\-dn\fR" 4 +.IX Item "-dn" +.IP "\fB\-non_shared\fR" 4 +.IX Item "-non_shared" +.IP "\fB\-static\fR" 4 +.IX Item "-static" +.PD +Do not link against shared libraries. This is only meaningful on +platforms for which shared libraries are supported. The different +variants of this option are for compatibility with various systems. You +may use this option multiple times on the command line: it affects +library searching for \fB\-l\fR options which follow it. This +option also implies \fB\-\-unresolved\-symbols=report\-all\fR. This +option can be used with \fB\-shared\fR. Doing so means that a +shared library is being created but that all of the library's external +references must be resolved by pulling in entries from static +libraries. +.IP "\fB\-Bsymbolic\fR" 4 +.IX Item "-Bsymbolic" +When creating a shared library, bind references to global symbols to the +definition within the shared library, if any. Normally, it is possible +for a program linked against a shared library to override the definition +within the shared library. This option is only meaningful on \s-1ELF\s0 +platforms which support shared libraries. +.IP "\fB\-Bsymbolic\-functions\fR" 4 +.IX Item "-Bsymbolic-functions" +When creating a shared library, bind references to global function +symbols to the definition within the shared library, if any. +This option is only meaningful on \s-1ELF\s0 platforms which support shared +libraries. +.IP "\fB\-\-dynamic\-list=\fR\fIdynamic-list-file\fR" 4 +.IX Item "--dynamic-list=dynamic-list-file" +Specify the name of a dynamic list file to the linker. This is +typically used when creating shared libraries to specify a list of +global symbols whose references shouldn't be bound to the definition +within the shared library, or creating dynamically linked executables +to specify a list of symbols which should be added to the symbol table +in the executable. This option is only meaningful on \s-1ELF\s0 platforms +which support shared libraries. +.Sp +The format of the dynamic list is the same as the version node without +scope and node name. See \fB\s-1VERSION\s0\fR for more information. +.IP "\fB\-\-dynamic\-list\-data\fR" 4 +.IX Item "--dynamic-list-data" +Include all global data symbols to the dynamic list. +.IP "\fB\-\-dynamic\-list\-cpp\-new\fR" 4 +.IX Item "--dynamic-list-cpp-new" +Provide the builtin dynamic list for \*(C+ operator new and delete. It +is mainly useful for building shared libstdc++. +.IP "\fB\-\-dynamic\-list\-cpp\-typeinfo\fR" 4 +.IX Item "--dynamic-list-cpp-typeinfo" +Provide the builtin dynamic list for \*(C+ runtime type identification. +.IP "\fB\-\-check\-sections\fR" 4 +.IX Item "--check-sections" +.PD 0 +.IP "\fB\-\-no\-check\-sections\fR" 4 +.IX Item "--no-check-sections" +.PD +Asks the linker \fInot\fR to check section addresses after they have +been assigned to see if there are any overlaps. Normally the linker will +perform this check, and if it finds any overlaps it will produce +suitable error messages. The linker does know about, and does make +allowances for sections in overlays. The default behaviour can be +restored by using the command line switch \fB\-\-check\-sections\fR. +Section overlap is not usually checked for relocatable links. You can +force checking in that case by using the \fB\-\-check\-sections\fR +option. +.IP "\fB\-\-copy\-dt\-needed\-entries\fR" 4 +.IX Item "--copy-dt-needed-entries" +.PD 0 +.IP "\fB\-\-no\-copy\-dt\-needed\-entries\fR" 4 +.IX Item "--no-copy-dt-needed-entries" +.PD +This option affects the treatment of dynamic libraries referred to +by \s-1DT_NEEDED\s0 tags \fIinside\fR \s-1ELF\s0 dynamic libraries mentioned on the +command line. Normally the linker will add a \s-1DT_NEEDED\s0 tag to the +output binary for each library mentioned in a \s-1DT_NEEDED\s0 tag in an +input dynamic library. With \fB\-\-no\-copy\-dt\-needed\-entries\fR +specified on the command line however any dynamic libraries that +follow it will have their \s-1DT_NEEDED\s0 entries ignored. The default +behaviour can be restored with \fB\-\-copy\-dt\-needed\-entries\fR. +.Sp +This option also has an effect on the resolution of symbols in dynamic +libraries. With the default setting dynamic libraries mentioned on +the command line will be recursively searched, following their +\&\s-1DT_NEEDED\s0 tags to other libraries, in order to resolve symbols +required by the output binary. With +\&\fB\-\-no\-copy\-dt\-needed\-entries\fR specified however the searching +of dynamic libraries that follow it will stop with the dynamic +library itself. No \s-1DT_NEEDED\s0 links will be traversed to resolve +symbols. +.IP "\fB\-\-cref\fR" 4 +.IX Item "--cref" +Output a cross reference table. If a linker map file is being +generated, the cross reference table is printed to the map file. +Otherwise, it is printed on the standard output. +.Sp +The format of the table is intentionally simple, so that it may be +easily processed by a script if necessary. The symbols are printed out, +sorted by name. For each symbol, a list of file names is given. If the +symbol is defined, the first file listed is the location of the +definition. The remaining files contain references to the symbol. +.IP "\fB\-\-no\-define\-common\fR" 4 +.IX Item "--no-define-common" +This option inhibits the assignment of addresses to common symbols. +The script command \f(CW\*(C`INHIBIT_COMMON_ALLOCATION\*(C'\fR has the same effect. +.Sp +The \fB\-\-no\-define\-common\fR option allows decoupling +the decision to assign addresses to Common symbols from the choice +of the output file type; otherwise a non-Relocatable output type +forces assigning addresses to Common symbols. +Using \fB\-\-no\-define\-common\fR allows Common symbols that are referenced +from a shared library to be assigned addresses only in the main program. +This eliminates the unused duplicate space in the shared library, +and also prevents any possible confusion over resolving to the wrong +duplicate when there are many dynamic modules with specialized search +paths for runtime symbol resolution. +.IP "\fB\-\-defsym=\fR\fIsymbol\fR\fB=\fR\fIexpression\fR" 4 +.IX Item "--defsym=symbol=expression" +Create a global symbol in the output file, containing the absolute +address given by \fIexpression\fR. You may use this option as many +times as necessary to define multiple symbols in the command line. A +limited form of arithmetic is supported for the \fIexpression\fR in this +context: you may give a hexadecimal constant or the name of an existing +symbol, or use \f(CW\*(C`+\*(C'\fR and \f(CW\*(C`\-\*(C'\fR to add or subtract hexadecimal +constants or symbols. If you need more elaborate expressions, consider +using the linker command language from a script. \fINote:\fR there should be no white +space between \fIsymbol\fR, the equals sign ("\fB=\fR"), and +\&\fIexpression\fR. +.IP "\fB\-\-demangle[=\fR\fIstyle\fR\fB]\fR" 4 +.IX Item "--demangle[=style]" +.PD 0 +.IP "\fB\-\-no\-demangle\fR" 4 +.IX Item "--no-demangle" +.PD +These options control whether to demangle symbol names in error messages +and other output. When the linker is told to demangle, it tries to +present symbol names in a readable fashion: it strips leading +underscores if they are used by the object file format, and converts \*(C+ +mangled symbol names into user readable names. Different compilers have +different mangling styles. The optional demangling style argument can be used +to choose an appropriate demangling style for your compiler. The linker will +demangle by default unless the environment variable \fB\s-1COLLECT_NO_DEMANGLE\s0\fR +is set. These options may be used to override the default. +.IP "\fB\-I\fR\fIfile\fR" 4 +.IX Item "-Ifile" +.PD 0 +.IP "\fB\-\-dynamic\-linker=\fR\fIfile\fR" 4 +.IX Item "--dynamic-linker=file" +.PD +Set the name of the dynamic linker. This is only meaningful when +generating dynamically linked \s-1ELF\s0 executables. The default dynamic +linker is normally correct; don't use this unless you know what you are +doing. +.IP "\fB\-\-fatal\-warnings\fR" 4 +.IX Item "--fatal-warnings" +.PD 0 +.IP "\fB\-\-no\-fatal\-warnings\fR" 4 +.IX Item "--no-fatal-warnings" +.PD +Treat all warnings as errors. The default behaviour can be restored +with the option \fB\-\-no\-fatal\-warnings\fR. +.IP "\fB\-\-force\-exe\-suffix\fR" 4 +.IX Item "--force-exe-suffix" +Make sure that an output file has a .exe suffix. +.Sp +If a successfully built fully linked output file does not have a +\&\f(CW\*(C`.exe\*(C'\fR or \f(CW\*(C`.dll\*(C'\fR suffix, this option forces the linker to copy +the output file to one of the same name with a \f(CW\*(C`.exe\*(C'\fR suffix. This +option is useful when using unmodified Unix makefiles on a Microsoft +Windows host, since some versions of Windows won't run an image unless +it ends in a \f(CW\*(C`.exe\*(C'\fR suffix. +.IP "\fB\-\-gc\-sections\fR" 4 +.IX Item "--gc-sections" +.PD 0 +.IP "\fB\-\-no\-gc\-sections\fR" 4 +.IX Item "--no-gc-sections" +.PD +Enable garbage collection of unused input sections. It is ignored on +targets that do not support this option. The default behaviour (of not +performing this garbage collection) can be restored by specifying +\&\fB\-\-no\-gc\-sections\fR on the command line. +.Sp +\&\fB\-\-gc\-sections\fR decides which input sections are used by +examining symbols and relocations. The section containing the entry +symbol and all sections containing symbols undefined on the +command-line will be kept, as will sections containing symbols +referenced by dynamic objects. Note that when building shared +libraries, the linker must assume that any visible symbol is +referenced. Once this initial set of sections has been determined, +the linker recursively marks as used any section referenced by their +relocations. See \fB\-\-entry\fR and \fB\-\-undefined\fR. +.Sp +This option can be set when doing a partial link (enabled with option +\&\fB\-r\fR). In this case the root of symbols kept must be explicitly +specified either by an \fB\-\-entry\fR or \fB\-\-undefined\fR option or by +a \f(CW\*(C`ENTRY\*(C'\fR command in the linker script. +.IP "\fB\-\-print\-gc\-sections\fR" 4 +.IX Item "--print-gc-sections" +.PD 0 +.IP "\fB\-\-no\-print\-gc\-sections\fR" 4 +.IX Item "--no-print-gc-sections" +.PD +List all sections removed by garbage collection. The listing is +printed on stderr. This option is only effective if garbage +collection has been enabled via the \fB\-\-gc\-sections\fR) option. The +default behaviour (of not listing the sections that are removed) can +be restored by specifying \fB\-\-no\-print\-gc\-sections\fR on the command +line. +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +Print a summary of the command-line options on the standard output and exit. +.IP "\fB\-\-target\-help\fR" 4 +.IX Item "--target-help" +Print a summary of all target specific options on the standard output and exit. +.IP "\fB\-Map=\fR\fImapfile\fR" 4 +.IX Item "-Map=mapfile" +Print a link map to the file \fImapfile\fR. See the description of the +\&\fB\-M\fR option, above. +.IP "\fB\-\-no\-keep\-memory\fR" 4 +.IX Item "--no-keep-memory" +\&\fBld\fR normally optimizes for speed over memory usage by caching the +symbol tables of input files in memory. This option tells \fBld\fR to +instead optimize for memory usage, by rereading the symbol tables as +necessary. This may be required if \fBld\fR runs out of memory space +while linking a large executable. +.IP "\fB\-\-no\-undefined\fR" 4 +.IX Item "--no-undefined" +.PD 0 +.IP "\fB\-z defs\fR" 4 +.IX Item "-z defs" +.PD +Report unresolved symbol references from regular object files. This +is done even if the linker is creating a non-symbolic shared library. +The switch \fB\-\-[no\-]allow\-shlib\-undefined\fR controls the +behaviour for reporting unresolved references found in shared +libraries being linked in. +.IP "\fB\-\-allow\-multiple\-definition\fR" 4 +.IX Item "--allow-multiple-definition" +.PD 0 +.IP "\fB\-z muldefs\fR" 4 +.IX Item "-z muldefs" +.PD +Normally when a symbol is defined multiple times, the linker will +report a fatal error. These options allow multiple definitions and the +first definition will be used. +.IP "\fB\-\-allow\-shlib\-undefined\fR" 4 +.IX Item "--allow-shlib-undefined" +.PD 0 +.IP "\fB\-\-no\-allow\-shlib\-undefined\fR" 4 +.IX Item "--no-allow-shlib-undefined" +.PD +Allows or disallows undefined symbols in shared libraries. +This switch is similar to \fB\-\-no\-undefined\fR except that it +determines the behaviour when the undefined symbols are in a +shared library rather than a regular object file. It does not affect +how undefined symbols in regular object files are handled. +.Sp +The default behaviour is to report errors for any undefined symbols +referenced in shared libraries if the linker is being used to create +an executable, but to allow them if the linker is being used to create +a shared library. +.Sp +The reasons for allowing undefined symbol references in shared +libraries specified at link time are that: +.RS 4 +.IP "\(bu" 4 +A shared library specified at link time may not be the same as the one +that is available at load time, so the symbol might actually be +resolvable at load time. +.IP "\(bu" 4 +There are some operating systems, eg BeOS and \s-1HPPA\s0, where undefined +symbols in shared libraries are normal. +.Sp +The BeOS kernel for example patches shared libraries at load time to +select whichever function is most appropriate for the current +architecture. This is used, for example, to dynamically select an +appropriate memset function. +.RE +.RS 4 +.RE +.IP "\fB\-\-no\-undefined\-version\fR" 4 +.IX Item "--no-undefined-version" +Normally when a symbol has an undefined version, the linker will ignore +it. This option disallows symbols with undefined version and a fatal error +will be issued instead. +.IP "\fB\-\-default\-symver\fR" 4 +.IX Item "--default-symver" +Create and use a default symbol version (the soname) for unversioned +exported symbols. +.IP "\fB\-\-default\-imported\-symver\fR" 4 +.IX Item "--default-imported-symver" +Create and use a default symbol version (the soname) for unversioned +imported symbols. +.IP "\fB\-\-no\-warn\-mismatch\fR" 4 +.IX Item "--no-warn-mismatch" +Normally \fBld\fR will give an error if you try to link together input +files that are mismatched for some reason, perhaps because they have +been compiled for different processors or for different endiannesses. +This option tells \fBld\fR that it should silently permit such possible +errors. This option should only be used with care, in cases when you +have taken some special action that ensures that the linker errors are +inappropriate. +.IP "\fB\-\-no\-warn\-search\-mismatch\fR" 4 +.IX Item "--no-warn-search-mismatch" +Normally \fBld\fR will give a warning if it finds an incompatible +library during a library search. This option silences the warning. +.IP "\fB\-\-no\-whole\-archive\fR" 4 +.IX Item "--no-whole-archive" +Turn off the effect of the \fB\-\-whole\-archive\fR option for subsequent +archive files. +.IP "\fB\-\-noinhibit\-exec\fR" 4 +.IX Item "--noinhibit-exec" +Retain the executable output file whenever it is still usable. +Normally, the linker will not produce an output file if it encounters +errors during the link process; it exits without writing an output file +when it issues any error whatsoever. +.IP "\fB\-nostdlib\fR" 4 +.IX Item "-nostdlib" +Only search library directories explicitly specified on the +command line. Library directories specified in linker scripts +(including linker scripts specified on the command line) are ignored. +.IP "\fB\-\-oformat=\fR\fIoutput-format\fR" 4 +.IX Item "--oformat=output-format" +\&\fBld\fR may be configured to support more than one kind of object +file. If your \fBld\fR is configured this way, you can use the +\&\fB\-\-oformat\fR option to specify the binary format for the output +object file. Even when \fBld\fR is configured to support alternative +object formats, you don't usually need to specify this, as \fBld\fR +should be configured to produce as a default output format the most +usual format on each machine. \fIoutput-format\fR is a text string, the +name of a particular format supported by the \s-1BFD\s0 libraries. (You can +list the available binary formats with \fBobjdump \-i\fR.) The script +command \f(CW\*(C`OUTPUT_FORMAT\*(C'\fR can also specify the output format, but +this option overrides it. +.IP "\fB\-pie\fR" 4 +.IX Item "-pie" +.PD 0 +.IP "\fB\-\-pic\-executable\fR" 4 +.IX Item "--pic-executable" +.PD +Create a position independent executable. This is currently only supported on +\&\s-1ELF\s0 platforms. Position independent executables are similar to shared +libraries in that they are relocated by the dynamic linker to the virtual +address the \s-1OS\s0 chooses for them (which can vary between invocations). Like +normal dynamically linked executables they can be executed and symbols +defined in the executable cannot be overridden by shared libraries. +.IP "\fB\-qmagic\fR" 4 +.IX Item "-qmagic" +This option is ignored for Linux compatibility. +.IP "\fB\-Qy\fR" 4 +.IX Item "-Qy" +This option is ignored for \s-1SVR4\s0 compatibility. +.IP "\fB\-\-relax\fR" 4 +.IX Item "--relax" +.PD 0 +.IP "\fB\-\-no\-relax\fR" 4 +.IX Item "--no-relax" +.PD +An option with machine dependent effects. +This option is only supported on a few targets. +.Sp +On some platforms the \fB\-\-relax\fR option performs target specific, +global optimizations that become possible when the linker resolves +addressing in the program, such as relaxing address modes, +synthesizing new instructions, selecting shorter version of current +instructions, and combinig constant values. +.Sp +On some platforms these link time global optimizations may make symbolic +debugging of the resulting executable impossible. +This is known to be the case for the Matsushita \s-1MN10200\s0 and \s-1MN10300\s0 +family of processors. +.Sp +On platforms where this is not supported, \fB\-\-relax\fR is accepted, +but ignored. +.Sp +On platforms where \fB\-\-relax\fR is accepted the option +\&\fB\-\-no\-relax\fR can be used to disable the feature. +.IP "\fB\-\-retain\-symbols\-file=\fR\fIfilename\fR" 4 +.IX Item "--retain-symbols-file=filename" +Retain \fIonly\fR the symbols listed in the file \fIfilename\fR, +discarding all others. \fIfilename\fR is simply a flat file, with one +symbol name per line. This option is especially useful in environments +(such as VxWorks) +where a large global symbol table is accumulated gradually, to conserve +run-time memory. +.Sp +\&\fB\-\-retain\-symbols\-file\fR does \fInot\fR discard undefined symbols, +or symbols needed for relocations. +.Sp +You may only specify \fB\-\-retain\-symbols\-file\fR once in the command +line. It overrides \fB\-s\fR and \fB\-S\fR. +.IP "\fB\-rpath=\fR\fIdir\fR" 4 +.IX Item "-rpath=dir" +Add a directory to the runtime library search path. This is used when +linking an \s-1ELF\s0 executable with shared objects. All \fB\-rpath\fR +arguments are concatenated and passed to the runtime linker, which uses +them to locate shared objects at runtime. The \fB\-rpath\fR option is +also used when locating shared objects which are needed by shared +objects explicitly included in the link; see the description of the +\&\fB\-rpath\-link\fR option. If \fB\-rpath\fR is not used when linking an +\&\s-1ELF\s0 executable, the contents of the environment variable +\&\f(CW\*(C`LD_RUN_PATH\*(C'\fR will be used if it is defined. +.Sp +The \fB\-rpath\fR option may also be used on SunOS. By default, on +SunOS, the linker will form a runtime search patch out of all the +\&\fB\-L\fR options it is given. If a \fB\-rpath\fR option is used, the +runtime search path will be formed exclusively using the \fB\-rpath\fR +options, ignoring the \fB\-L\fR options. This can be useful when using +gcc, which adds many \fB\-L\fR options which may be on \s-1NFS\s0 mounted +file systems. +.Sp +For compatibility with other \s-1ELF\s0 linkers, if the \fB\-R\fR option is +followed by a directory name, rather than a file name, it is treated as +the \fB\-rpath\fR option. +.IP "\fB\-rpath\-link=\fR\fIdir\fR" 4 +.IX Item "-rpath-link=dir" +When using \s-1ELF\s0 or SunOS, one shared library may require another. This +happens when an \f(CW\*(C`ld \-shared\*(C'\fR link includes a shared library as one +of the input files. +.Sp +When the linker encounters such a dependency when doing a non-shared, +non-relocatable link, it will automatically try to locate the required +shared library and include it in the link, if it is not included +explicitly. In such a case, the \fB\-rpath\-link\fR option +specifies the first set of directories to search. The +\&\fB\-rpath\-link\fR option may specify a sequence of directory names +either by specifying a list of names separated by colons, or by +appearing multiple times. +.Sp +This option should be used with caution as it overrides the search path +that may have been hard compiled into a shared library. In such a case it +is possible to use unintentionally a different search path than the +runtime linker would do. +.Sp +The linker uses the following search paths to locate required shared +libraries: +.RS 4 +.IP "1." 4 +Any directories specified by \fB\-rpath\-link\fR options. +.IP "2." 4 +Any directories specified by \fB\-rpath\fR options. The difference +between \fB\-rpath\fR and \fB\-rpath\-link\fR is that directories +specified by \fB\-rpath\fR options are included in the executable and +used at runtime, whereas the \fB\-rpath\-link\fR option is only effective +at link time. Searching \fB\-rpath\fR in this way is only supported +by native linkers and cross linkers which have been configured with +the \fB\-\-with\-sysroot\fR option. +.IP "3." 4 +On an \s-1ELF\s0 system, for native linkers, if the \fB\-rpath\fR and +\&\fB\-rpath\-link\fR options were not used, search the contents of the +environment variable \f(CW\*(C`LD_RUN_PATH\*(C'\fR. +.IP "4." 4 +On SunOS, if the \fB\-rpath\fR option was not used, search any +directories specified using \fB\-L\fR options. +.IP "5." 4 +For a native linker, the search the contents of the environment +variable \f(CW\*(C`LD_LIBRARY_PATH\*(C'\fR. +.IP "6." 4 +For a native \s-1ELF\s0 linker, the directories in \f(CW\*(C`DT_RUNPATH\*(C'\fR or +\&\f(CW\*(C`DT_RPATH\*(C'\fR of a shared library are searched for shared +libraries needed by it. The \f(CW\*(C`DT_RPATH\*(C'\fR entries are ignored if +\&\f(CW\*(C`DT_RUNPATH\*(C'\fR entries exist. +.IP "7." 4 +The default directories, normally \fI/lib\fR and \fI/usr/lib\fR. +.IP "8." 4 +For a native linker on an \s-1ELF\s0 system, if the file \fI/etc/ld.so.conf\fR +exists, the list of directories found in that file. +.RE +.RS 4 +.Sp +If the required shared library is not found, the linker will issue a +warning and continue with the link. +.RE +.IP "\fB\-shared\fR" 4 +.IX Item "-shared" +.PD 0 +.IP "\fB\-Bshareable\fR" 4 +.IX Item "-Bshareable" +.PD +Create a shared library. This is currently only supported on \s-1ELF\s0, \s-1XCOFF\s0 +and SunOS platforms. On SunOS, the linker will automatically create a +shared library if the \fB\-e\fR option is not used and there are +undefined symbols in the link. +.IP "\fB\-\-sort\-common\fR" 4 +.IX Item "--sort-common" +.PD 0 +.IP "\fB\-\-sort\-common=ascending\fR" 4 +.IX Item "--sort-common=ascending" +.IP "\fB\-\-sort\-common=descending\fR" 4 +.IX Item "--sort-common=descending" +.PD +This option tells \fBld\fR to sort the common symbols by alignment in +ascending or descending order when it places them in the appropriate output +sections. The symbol alignments considered are sixteen-byte or larger, +eight-byte, four-byte, two-byte, and one-byte. This is to prevent gaps +between symbols due to alignment constraints. If no sorting order is +specified, then descending order is assumed. +.IP "\fB\-\-sort\-section=name\fR" 4 +.IX Item "--sort-section=name" +This option will apply \f(CW\*(C`SORT_BY_NAME\*(C'\fR to all wildcard section +patterns in the linker script. +.IP "\fB\-\-sort\-section=alignment\fR" 4 +.IX Item "--sort-section=alignment" +This option will apply \f(CW\*(C`SORT_BY_ALIGNMENT\*(C'\fR to all wildcard section +patterns in the linker script. +.IP "\fB\-\-split\-by\-file[=\fR\fIsize\fR\fB]\fR" 4 +.IX Item "--split-by-file[=size]" +Similar to \fB\-\-split\-by\-reloc\fR but creates a new output section for +each input file when \fIsize\fR is reached. \fIsize\fR defaults to a +size of 1 if not given. +.IP "\fB\-\-split\-by\-reloc[=\fR\fIcount\fR\fB]\fR" 4 +.IX Item "--split-by-reloc[=count]" +Tries to creates extra sections in the output file so that no single +output section in the file contains more than \fIcount\fR relocations. +This is useful when generating huge relocatable files for downloading into +certain real time kernels with the \s-1COFF\s0 object file format; since \s-1COFF\s0 +cannot represent more than 65535 relocations in a single section. Note +that this will fail to work with object file formats which do not +support arbitrary sections. The linker will not split up individual +input sections for redistribution, so if a single input section contains +more than \fIcount\fR relocations one output section will contain that +many relocations. \fIcount\fR defaults to a value of 32768. +.IP "\fB\-\-stats\fR" 4 +.IX Item "--stats" +Compute and display statistics about the operation of the linker, such +as execution time and memory usage. +.IP "\fB\-\-sysroot=\fR\fIdirectory\fR" 4 +.IX Item "--sysroot=directory" +Use \fIdirectory\fR as the location of the sysroot, overriding the +configure-time default. This option is only supported by linkers +that were configured using \fB\-\-with\-sysroot\fR. +.IP "\fB\-\-traditional\-format\fR" 4 +.IX Item "--traditional-format" +For some targets, the output of \fBld\fR is different in some ways from +the output of some existing linker. This switch requests \fBld\fR to +use the traditional format instead. +.Sp +For example, on SunOS, \fBld\fR combines duplicate entries in the +symbol string table. This can reduce the size of an output file with +full debugging information by over 30 percent. Unfortunately, the SunOS +\&\f(CW\*(C`dbx\*(C'\fR program can not read the resulting program (\f(CW\*(C`gdb\*(C'\fR has no +trouble). The \fB\-\-traditional\-format\fR switch tells \fBld\fR to not +combine duplicate entries. +.IP "\fB\-\-section\-start=\fR\fIsectionname\fR\fB=\fR\fIorg\fR" 4 +.IX Item "--section-start=sectionname=org" +Locate a section in the output file at the absolute +address given by \fIorg\fR. You may use this option as many +times as necessary to locate multiple sections in the command +line. +\&\fIorg\fR must be a single hexadecimal integer; +for compatibility with other linkers, you may omit the leading +\&\fB0x\fR usually associated with hexadecimal values. \fINote:\fR there +should be no white space between \fIsectionname\fR, the equals +sign ("\fB=\fR"), and \fIorg\fR. +.IP "\fB\-Tbss=\fR\fIorg\fR" 4 +.IX Item "-Tbss=org" +.PD 0 +.IP "\fB\-Tdata=\fR\fIorg\fR" 4 +.IX Item "-Tdata=org" +.IP "\fB\-Ttext=\fR\fIorg\fR" 4 +.IX Item "-Ttext=org" +.PD +Same as \fB\-\-section\-start\fR, with \f(CW\*(C`.bss\*(C'\fR, \f(CW\*(C`.data\*(C'\fR or +\&\f(CW\*(C`.text\*(C'\fR as the \fIsectionname\fR. +.IP "\fB\-Ttext\-segment=\fR\fIorg\fR" 4 +.IX Item "-Ttext-segment=org" +When creating an \s-1ELF\s0 executable or shared object, it will set the address +of the first byte of the text segment. +.IP "\fB\-\-unresolved\-symbols=\fR\fImethod\fR" 4 +.IX Item "--unresolved-symbols=method" +Determine how to handle unresolved symbols. There are four possible +values for \fBmethod\fR: +.RS 4 +.IP "\fBignore-all\fR" 4 +.IX Item "ignore-all" +Do not report any unresolved symbols. +.IP "\fBreport-all\fR" 4 +.IX Item "report-all" +Report all unresolved symbols. This is the default. +.IP "\fBignore-in-object-files\fR" 4 +.IX Item "ignore-in-object-files" +Report unresolved symbols that are contained in shared libraries, but +ignore them if they come from regular object files. +.IP "\fBignore-in-shared-libs\fR" 4 +.IX Item "ignore-in-shared-libs" +Report unresolved symbols that come from regular object files, but +ignore them if they come from shared libraries. This can be useful +when creating a dynamic binary and it is known that all the shared +libraries that it should be referencing are included on the linker's +command line. +.RE +.RS 4 +.Sp +The behaviour for shared libraries on their own can also be controlled +by the \fB\-\-[no\-]allow\-shlib\-undefined\fR option. +.Sp +Normally the linker will generate an error message for each reported +unresolved symbol but the option \fB\-\-warn\-unresolved\-symbols\fR +can change this to a warning. +.RE +.IP "\fB\-\-dll\-verbose\fR" 4 +.IX Item "--dll-verbose" +.PD 0 +.IP "\fB\-\-verbose\fR" 4 +.IX Item "--verbose" +.PD +Display the version number for \fBld\fR and list the linker emulations +supported. Display which input files can and cannot be opened. Display +the linker script being used by the linker. +.IP "\fB\-\-version\-script=\fR\fIversion-scriptfile\fR" 4 +.IX Item "--version-script=version-scriptfile" +Specify the name of a version script to the linker. This is typically +used when creating shared libraries to specify additional information +about the version hierarchy for the library being created. This option +is only fully supported on \s-1ELF\s0 platforms which support shared libraries; +see \fB\s-1VERSION\s0\fR. It is partially supported on \s-1PE\s0 platforms, which can +use version scripts to filter symbol visibility in auto-export mode: any +symbols marked \fBlocal\fR in the version script will not be exported. +.IP "\fB\-\-warn\-common\fR" 4 +.IX Item "--warn-common" +Warn when a common symbol is combined with another common symbol or with +a symbol definition. Unix linkers allow this somewhat sloppy practise, +but linkers on some other operating systems do not. This option allows +you to find potential problems from combining global symbols. +Unfortunately, some C libraries use this practise, so you may get some +warnings about symbols in the libraries as well as in your programs. +.Sp +There are three kinds of global symbols, illustrated here by C examples: +.RS 4 +.IP "\fBint i = 1;\fR" 4 +.IX Item "int i = 1;" +A definition, which goes in the initialized data section of the output +file. +.IP "\fBextern int i;\fR" 4 +.IX Item "extern int i;" +An undefined reference, which does not allocate space. +There must be either a definition or a common symbol for the +variable somewhere. +.IP "\fBint i;\fR" 4 +.IX Item "int i;" +A common symbol. If there are only (one or more) common symbols for a +variable, it goes in the uninitialized data area of the output file. +The linker merges multiple common symbols for the same variable into a +single symbol. If they are of different sizes, it picks the largest +size. The linker turns a common symbol into a declaration, if there is +a definition of the same variable. +.RE +.RS 4 +.Sp +The \fB\-\-warn\-common\fR option can produce five kinds of warnings. +Each warning consists of a pair of lines: the first describes the symbol +just encountered, and the second describes the previous symbol +encountered with the same name. One or both of the two symbols will be +a common symbol. +.IP "1." 4 +Turning a common symbol into a reference, because there is already a +definition for the symbol. +.Sp +.Vb 3 +\& <file>(<section>): warning: common of \`<symbol>\*(Aq +\& overridden by definition +\& <file>(<section>): warning: defined here +.Ve +.IP "2." 4 +Turning a common symbol into a reference, because a later definition for +the symbol is encountered. This is the same as the previous case, +except that the symbols are encountered in a different order. +.Sp +.Vb 3 +\& <file>(<section>): warning: definition of \`<symbol>\*(Aq +\& overriding common +\& <file>(<section>): warning: common is here +.Ve +.IP "3." 4 +Merging a common symbol with a previous same-sized common symbol. +.Sp +.Vb 3 +\& <file>(<section>): warning: multiple common +\& of \`<symbol>\*(Aq +\& <file>(<section>): warning: previous common is here +.Ve +.IP "4." 4 +Merging a common symbol with a previous larger common symbol. +.Sp +.Vb 3 +\& <file>(<section>): warning: common of \`<symbol>\*(Aq +\& overridden by larger common +\& <file>(<section>): warning: larger common is here +.Ve +.IP "5." 4 +Merging a common symbol with a previous smaller common symbol. This is +the same as the previous case, except that the symbols are +encountered in a different order. +.Sp +.Vb 3 +\& <file>(<section>): warning: common of \`<symbol>\*(Aq +\& overriding smaller common +\& <file>(<section>): warning: smaller common is here +.Ve +.RE +.RS 4 +.RE +.IP "\fB\-\-warn\-constructors\fR" 4 +.IX Item "--warn-constructors" +Warn if any global constructors are used. This is only useful for a few +object file formats. For formats like \s-1COFF\s0 or \s-1ELF\s0, the linker can not +detect the use of global constructors. +.IP "\fB\-\-warn\-multiple\-gp\fR" 4 +.IX Item "--warn-multiple-gp" +Warn if multiple global pointer values are required in the output file. +This is only meaningful for certain processors, such as the Alpha. +Specifically, some processors put large-valued constants in a special +section. A special register (the global pointer) points into the middle +of this section, so that constants can be loaded efficiently via a +base-register relative addressing mode. Since the offset in +base-register relative mode is fixed and relatively small (e.g., 16 +bits), this limits the maximum size of the constant pool. Thus, in +large programs, it is often necessary to use multiple global pointer +values in order to be able to address all possible constants. This +option causes a warning to be issued whenever this case occurs. +.IP "\fB\-\-warn\-once\fR" 4 +.IX Item "--warn-once" +Only warn once for each undefined symbol, rather than once per module +which refers to it. +.IP "\fB\-\-warn\-section\-align\fR" 4 +.IX Item "--warn-section-align" +Warn if the address of an output section is changed because of +alignment. Typically, the alignment will be set by an input section. +The address will only be changed if it not explicitly specified; that +is, if the \f(CW\*(C`SECTIONS\*(C'\fR command does not specify a start address for +the section. +.IP "\fB\-\-warn\-shared\-textrel\fR" 4 +.IX Item "--warn-shared-textrel" +Warn if the linker adds a \s-1DT_TEXTREL\s0 to a shared object. +.IP "\fB\-\-warn\-alternate\-em\fR" 4 +.IX Item "--warn-alternate-em" +Warn if an object has alternate \s-1ELF\s0 machine code. +.IP "\fB\-\-warn\-unresolved\-symbols\fR" 4 +.IX Item "--warn-unresolved-symbols" +If the linker is going to report an unresolved symbol (see the option +\&\fB\-\-unresolved\-symbols\fR) it will normally generate an error. +This option makes it generate a warning instead. +.IP "\fB\-\-error\-unresolved\-symbols\fR" 4 +.IX Item "--error-unresolved-symbols" +This restores the linker's default behaviour of generating errors when +it is reporting unresolved symbols. +.IP "\fB\-\-whole\-archive\fR" 4 +.IX Item "--whole-archive" +For each archive mentioned on the command line after the +\&\fB\-\-whole\-archive\fR option, include every object file in the archive +in the link, rather than searching the archive for the required object +files. This is normally used to turn an archive file into a shared +library, forcing every object to be included in the resulting shared +library. This option may be used more than once. +.Sp +Two notes when using this option from gcc: First, gcc doesn't know +about this option, so you have to use \fB\-Wl,\-whole\-archive\fR. +Second, don't forget to use \fB\-Wl,\-no\-whole\-archive\fR after your +list of archives, because gcc will add its own list of archives to +your link and you may not want this flag to affect those as well. +.IP "\fB\-\-wrap=\fR\fIsymbol\fR" 4 +.IX Item "--wrap=symbol" +Use a wrapper function for \fIsymbol\fR. Any undefined reference to +\&\fIsymbol\fR will be resolved to \f(CW\*(C`_\|_wrap_\f(CIsymbol\f(CW\*(C'\fR. Any +undefined reference to \f(CW\*(C`_\|_real_\f(CIsymbol\f(CW\*(C'\fR will be resolved to +\&\fIsymbol\fR. +.Sp +This can be used to provide a wrapper for a system function. The +wrapper function should be called \f(CW\*(C`_\|_wrap_\f(CIsymbol\f(CW\*(C'\fR. If it +wishes to call the system function, it should call +\&\f(CW\*(C`_\|_real_\f(CIsymbol\f(CW\*(C'\fR. +.Sp +Here is a trivial example: +.Sp +.Vb 6 +\& void * +\& _\|_wrap_malloc (size_t c) +\& { +\& printf ("malloc called with %zu\en", c); +\& return _\|_real_malloc (c); +\& } +.Ve +.Sp +If you link other code with this file using \fB\-\-wrap malloc\fR, then +all calls to \f(CW\*(C`malloc\*(C'\fR will call the function \f(CW\*(C`_\|_wrap_malloc\*(C'\fR +instead. The call to \f(CW\*(C`_\|_real_malloc\*(C'\fR in \f(CW\*(C`_\|_wrap_malloc\*(C'\fR will +call the real \f(CW\*(C`malloc\*(C'\fR function. +.Sp +You may wish to provide a \f(CW\*(C`_\|_real_malloc\*(C'\fR function as well, so that +links without the \fB\-\-wrap\fR option will succeed. If you do this, +you should not put the definition of \f(CW\*(C`_\|_real_malloc\*(C'\fR in the same +file as \f(CW\*(C`_\|_wrap_malloc\*(C'\fR; if you do, the assembler may resolve the +call before the linker has a chance to wrap it to \f(CW\*(C`malloc\*(C'\fR. +.IP "\fB\-\-eh\-frame\-hdr\fR" 4 +.IX Item "--eh-frame-hdr" +Request creation of \f(CW\*(C`.eh_frame_hdr\*(C'\fR section and \s-1ELF\s0 +\&\f(CW\*(C`PT_GNU_EH_FRAME\*(C'\fR segment header. +.IP "\fB\-\-enable\-new\-dtags\fR" 4 +.IX Item "--enable-new-dtags" +.PD 0 +.IP "\fB\-\-disable\-new\-dtags\fR" 4 +.IX Item "--disable-new-dtags" +.PD +This linker can create the new dynamic tags in \s-1ELF\s0. But the older \s-1ELF\s0 +systems may not understand them. If you specify +\&\fB\-\-enable\-new\-dtags\fR, the dynamic tags will be created as needed. +If you specify \fB\-\-disable\-new\-dtags\fR, no new dynamic tags will be +created. By default, the new dynamic tags are not created. Note that +those options are only available for \s-1ELF\s0 systems. +.IP "\fB\-\-hash\-size=\fR\fInumber\fR" 4 +.IX Item "--hash-size=number" +Set the default size of the linker's hash tables to a prime number +close to \fInumber\fR. Increasing this value can reduce the length of +time it takes the linker to perform its tasks, at the expense of +increasing the linker's memory requirements. Similarly reducing this +value can reduce the memory requirements at the expense of speed. +.IP "\fB\-\-hash\-style=\fR\fIstyle\fR" 4 +.IX Item "--hash-style=style" +Set the type of linker's hash table(s). \fIstyle\fR can be either +\&\f(CW\*(C`sysv\*(C'\fR for classic \s-1ELF\s0 \f(CW\*(C`.hash\*(C'\fR section, \f(CW\*(C`gnu\*(C'\fR for +new style \s-1GNU\s0 \f(CW\*(C`.gnu.hash\*(C'\fR section or \f(CW\*(C`both\*(C'\fR for both +the classic \s-1ELF\s0 \f(CW\*(C`.hash\*(C'\fR and new style \s-1GNU\s0 \f(CW\*(C`.gnu.hash\*(C'\fR +hash tables. The default is \f(CW\*(C`sysv\*(C'\fR. +.IP "\fB\-\-reduce\-memory\-overheads\fR" 4 +.IX Item "--reduce-memory-overheads" +This option reduces memory requirements at ld runtime, at the expense of +linking speed. This was introduced to select the old O(n^2) algorithm +for link map file generation, rather than the new O(n) algorithm which uses +about 40% more memory for symbol storage. +.Sp +Another effect of the switch is to set the default hash table size to +1021, which again saves memory at the cost of lengthening the linker's +run time. This is not done however if the \fB\-\-hash\-size\fR switch +has been used. +.Sp +The \fB\-\-reduce\-memory\-overheads\fR switch may be also be used to +enable other tradeoffs in future versions of the linker. +.IP "\fB\-\-build\-id\fR" 4 +.IX Item "--build-id" +.PD 0 +.IP "\fB\-\-build\-id=\fR\fIstyle\fR" 4 +.IX Item "--build-id=style" +.PD +Request creation of \f(CW\*(C`.note.gnu.build\-id\*(C'\fR \s-1ELF\s0 note section. +The contents of the note are unique bits identifying this linked +file. \fIstyle\fR can be \f(CW\*(C`uuid\*(C'\fR to use 128 random bits, +\&\f(CW\*(C`sha1\*(C'\fR to use a 160\-bit \s-1SHA1\s0 hash on the normative +parts of the output contents, \f(CW\*(C`md5\*(C'\fR to use a 128\-bit +\&\s-1MD5\s0 hash on the normative parts of the output contents, or +\&\f(CW\*(C`0x\f(CIhexstring\f(CW\*(C'\fR to use a chosen bit string specified as +an even number of hexadecimal digits (\f(CW\*(C`\-\*(C'\fR and \f(CW\*(C`:\*(C'\fR +characters between digit pairs are ignored). If \fIstyle\fR is +omitted, \f(CW\*(C`sha1\*(C'\fR is used. +.Sp +The \f(CW\*(C`md5\*(C'\fR and \f(CW\*(C`sha1\*(C'\fR styles produces an identifier +that is always the same in an identical output file, but will be +unique among all nonidentical output files. It is not intended +to be compared as a checksum for the file's contents. A linked +file may be changed later by other tools, but the build \s-1ID\s0 bit +string identifying the original linked file does not change. +.Sp +Passing \f(CW\*(C`none\*(C'\fR for \fIstyle\fR disables the setting from any +\&\f(CW\*(C`\-\-build\-id\*(C'\fR options earlier on the command line. +.PP +The i386 \s-1PE\s0 linker supports the \fB\-shared\fR option, which causes +the output to be a dynamically linked library (\s-1DLL\s0) instead of a +normal executable. You should name the output \f(CW\*(C`*.dll\*(C'\fR when you +use this option. In addition, the linker fully supports the standard +\&\f(CW\*(C`*.def\*(C'\fR files, which may be specified on the linker command line +like an object file (in fact, it should precede archives it exports +symbols from, to ensure that they get linked in, just like a normal +object file). +.PP +In addition to the options common to all targets, the i386 \s-1PE\s0 linker +support additional command line options that are specific to the i386 +\&\s-1PE\s0 target. Options that take values may be separated from their +values by either a space or an equals sign. +.IP "\fB\-\-add\-stdcall\-alias\fR" 4 +.IX Item "--add-stdcall-alias" +If given, symbols with a stdcall suffix (@\fInn\fR) will be exported +as-is and also with the suffix stripped. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-base\-file\fR \fIfile\fR" 4 +.IX Item "--base-file file" +Use \fIfile\fR as the name of a file in which to save the base +addresses of all the relocations needed for generating DLLs with +\&\fIdlltool\fR. +[This is an i386 \s-1PE\s0 specific option] +.IP "\fB\-\-dll\fR" 4 +.IX Item "--dll" +Create a \s-1DLL\s0 instead of a regular executable. You may also use +\&\fB\-shared\fR or specify a \f(CW\*(C`LIBRARY\*(C'\fR in a given \f(CW\*(C`.def\*(C'\fR +file. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-enable\-long\-section\-names\fR" 4 +.IX Item "--enable-long-section-names" +.PD 0 +.IP "\fB\-\-disable\-long\-section\-names\fR" 4 +.IX Item "--disable-long-section-names" +.PD +The \s-1PE\s0 variants of the Coff object format add an extension that permits +the use of section names longer than eight characters, the normal limit +for Coff. By default, these names are only allowed in object files, as +fully-linked executable images do not carry the Coff string table required +to support the longer names. As a \s-1GNU\s0 extension, it is possible to +allow their use in executable images as well, or to (probably pointlessly!) +disallow it in object files, by using these two options. Executable images +generated with these long section names are slightly non-standard, carrying +as they do a string table, and may generate confusing output when examined +with non-GNU PE-aware tools, such as file viewers and dumpers. However, +\&\s-1GDB\s0 relies on the use of \s-1PE\s0 long section names to find Dwarf\-2 debug +information sections in an executable image at runtime, and so if neither +option is specified on the command-line, \fBld\fR will enable long +section names, overriding the default and technically correct behaviour, +when it finds the presence of debug information while linking an executable +image and not stripping symbols. +[This option is valid for all \s-1PE\s0 targeted ports of the linker] +.IP "\fB\-\-enable\-stdcall\-fixup\fR" 4 +.IX Item "--enable-stdcall-fixup" +.PD 0 +.IP "\fB\-\-disable\-stdcall\-fixup\fR" 4 +.IX Item "--disable-stdcall-fixup" +.PD +If the link finds a symbol that it cannot resolve, it will attempt to +do \*(L"fuzzy linking\*(R" by looking for another defined symbol that differs +only in the format of the symbol name (cdecl vs stdcall) and will +resolve that symbol by linking to the match. For example, the +undefined symbol \f(CW\*(C`_foo\*(C'\fR might be linked to the function +\&\f(CW\*(C`_foo@12\*(C'\fR, or the undefined symbol \f(CW\*(C`_bar@16\*(C'\fR might be linked +to the function \f(CW\*(C`_bar\*(C'\fR. When the linker does this, it prints a +warning, since it normally should have failed to link, but sometimes +import libraries generated from third-party dlls may need this feature +to be usable. If you specify \fB\-\-enable\-stdcall\-fixup\fR, this +feature is fully enabled and warnings are not printed. If you specify +\&\fB\-\-disable\-stdcall\-fixup\fR, this feature is disabled and such +mismatches are considered to be errors. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-leading\-underscore\fR" 4 +.IX Item "--leading-underscore" +.PD 0 +.IP "\fB\-\-no\-leading\-underscore\fR" 4 +.IX Item "--no-leading-underscore" +.PD +For most targets default symbol-prefix is an underscore and is defined +in target's description. By this option it is possible to +disable/enable the default underscore symbol-prefix. +.IP "\fB\-\-export\-all\-symbols\fR" 4 +.IX Item "--export-all-symbols" +If given, all global symbols in the objects used to build a \s-1DLL\s0 will +be exported by the \s-1DLL\s0. Note that this is the default if there +otherwise wouldn't be any exported symbols. When symbols are +explicitly exported via \s-1DEF\s0 files or implicitly exported via function +attributes, the default is to not export anything else unless this +option is given. Note that the symbols \f(CW\*(C`DllMain@12\*(C'\fR, +\&\f(CW\*(C`DllEntryPoint@0\*(C'\fR, \f(CW\*(C`DllMainCRTStartup@12\*(C'\fR, and +\&\f(CW\*(C`impure_ptr\*(C'\fR will not be automatically +exported. Also, symbols imported from other DLLs will not be +re-exported, nor will symbols specifying the \s-1DLL\s0's internal layout +such as those beginning with \f(CW\*(C`_head_\*(C'\fR or ending with +\&\f(CW\*(C`_iname\*(C'\fR. In addition, no symbols from \f(CW\*(C`libgcc\*(C'\fR, +\&\f(CW\*(C`libstd++\*(C'\fR, \f(CW\*(C`libmingw32\*(C'\fR, or \f(CW\*(C`crtX.o\*(C'\fR will be exported. +Symbols whose names begin with \f(CW\*(C`_\|_rtti_\*(C'\fR or \f(CW\*(C`_\|_builtin_\*(C'\fR will +not be exported, to help with \*(C+ DLLs. Finally, there is an +extensive list of cygwin-private symbols that are not exported +(obviously, this applies on when building DLLs for cygwin targets). +These cygwin-excludes are: \f(CW\*(C`_cygwin_dll_entry@12\*(C'\fR, +\&\f(CW\*(C`_cygwin_crt0_common@8\*(C'\fR, \f(CW\*(C`_cygwin_noncygwin_dll_entry@12\*(C'\fR, +\&\f(CW\*(C`_fmode\*(C'\fR, \f(CW\*(C`_impure_ptr\*(C'\fR, \f(CW\*(C`cygwin_attach_dll\*(C'\fR, +\&\f(CW\*(C`cygwin_premain0\*(C'\fR, \f(CW\*(C`cygwin_premain1\*(C'\fR, \f(CW\*(C`cygwin_premain2\*(C'\fR, +\&\f(CW\*(C`cygwin_premain3\*(C'\fR, and \f(CW\*(C`environ\*(C'\fR. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-exclude\-symbols\fR \fIsymbol\fR\fB,\fR\fIsymbol\fR\fB,...\fR" 4 +.IX Item "--exclude-symbols symbol,symbol,..." +Specifies a list of symbols which should not be automatically +exported. The symbol names may be delimited by commas or colons. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-exclude\-all\-symbols\fR" 4 +.IX Item "--exclude-all-symbols" +Specifies no symbols should be automatically exported. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-file\-alignment\fR" 4 +.IX Item "--file-alignment" +Specify the file alignment. Sections in the file will always begin at +file offsets which are multiples of this number. This defaults to +512. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-heap\fR \fIreserve\fR" 4 +.IX Item "--heap reserve" +.PD 0 +.IP "\fB\-\-heap\fR \fIreserve\fR\fB,\fR\fIcommit\fR" 4 +.IX Item "--heap reserve,commit" +.PD +Specify the number of bytes of memory to reserve (and optionally commit) +to be used as heap for this program. The default is 1Mb reserved, 4K +committed. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-image\-base\fR \fIvalue\fR" 4 +.IX Item "--image-base value" +Use \fIvalue\fR as the base address of your program or dll. This is +the lowest memory location that will be used when your program or dll +is loaded. To reduce the need to relocate and improve performance of +your dlls, each should have a unique base address and not overlap any +other dlls. The default is 0x400000 for executables, and 0x10000000 +for dlls. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-kill\-at\fR" 4 +.IX Item "--kill-at" +If given, the stdcall suffixes (@\fInn\fR) will be stripped from +symbols before they are exported. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-large\-address\-aware\fR" 4 +.IX Item "--large-address-aware" +If given, the appropriate bit in the \*(L"Characteristics\*(R" field of the \s-1COFF\s0 +header is set to indicate that this executable supports virtual addresses +greater than 2 gigabytes. This should be used in conjunction with the /3GB +or /USERVA=\fIvalue\fR megabytes switch in the \*(L"[operating systems]\*(R" +section of the \s-1BOOT\s0.INI. Otherwise, this bit has no effect. +[This option is specific to \s-1PE\s0 targeted ports of the linker] +.IP "\fB\-\-major\-image\-version\fR \fIvalue\fR" 4 +.IX Item "--major-image-version value" +Sets the major number of the \*(L"image version\*(R". Defaults to 1. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-major\-os\-version\fR \fIvalue\fR" 4 +.IX Item "--major-os-version value" +Sets the major number of the \*(L"os version\*(R". Defaults to 4. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-major\-subsystem\-version\fR \fIvalue\fR" 4 +.IX Item "--major-subsystem-version value" +Sets the major number of the \*(L"subsystem version\*(R". Defaults to 4. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-minor\-image\-version\fR \fIvalue\fR" 4 +.IX Item "--minor-image-version value" +Sets the minor number of the \*(L"image version\*(R". Defaults to 0. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-minor\-os\-version\fR \fIvalue\fR" 4 +.IX Item "--minor-os-version value" +Sets the minor number of the \*(L"os version\*(R". Defaults to 0. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-minor\-subsystem\-version\fR \fIvalue\fR" 4 +.IX Item "--minor-subsystem-version value" +Sets the minor number of the \*(L"subsystem version\*(R". Defaults to 0. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-output\-def\fR \fIfile\fR" 4 +.IX Item "--output-def file" +The linker will create the file \fIfile\fR which will contain a \s-1DEF\s0 +file corresponding to the \s-1DLL\s0 the linker is generating. This \s-1DEF\s0 file +(which should be called \f(CW\*(C`*.def\*(C'\fR) may be used to create an import +library with \f(CW\*(C`dlltool\*(C'\fR or may be used as a reference to +automatically or implicitly exported symbols. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-out\-implib\fR \fIfile\fR" 4 +.IX Item "--out-implib file" +The linker will create the file \fIfile\fR which will contain an +import lib corresponding to the \s-1DLL\s0 the linker is generating. This +import lib (which should be called \f(CW\*(C`*.dll.a\*(C'\fR or \f(CW\*(C`*.a\*(C'\fR +may be used to link clients against the generated \s-1DLL\s0; this behaviour +makes it possible to skip a separate \f(CW\*(C`dlltool\*(C'\fR import library +creation step. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-enable\-auto\-image\-base\fR" 4 +.IX Item "--enable-auto-image-base" +Automatically choose the image base for DLLs, unless one is specified +using the \f(CW\*(C`\-\-image\-base\*(C'\fR argument. By using a hash generated +from the dllname to create unique image bases for each \s-1DLL\s0, in-memory +collisions and relocations which can delay program execution are +avoided. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-disable\-auto\-image\-base\fR" 4 +.IX Item "--disable-auto-image-base" +Do not automatically generate a unique image base. If there is no +user-specified image base (\f(CW\*(C`\-\-image\-base\*(C'\fR) then use the platform +default. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-dll\-search\-prefix\fR \fIstring\fR" 4 +.IX Item "--dll-search-prefix string" +When linking dynamically to a dll without an import library, +search for \f(CW\*(C`<string><basename>.dll\*(C'\fR in preference to +\&\f(CW\*(C`lib<basename>.dll\*(C'\fR. This behaviour allows easy distinction +between DLLs built for the various \*(L"subplatforms\*(R": native, cygwin, +uwin, pw, etc. For instance, cygwin DLLs typically use +\&\f(CW\*(C`\-\-dll\-search\-prefix=cyg\*(C'\fR. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-enable\-auto\-import\fR" 4 +.IX Item "--enable-auto-import" +Do sophisticated linking of \f(CW\*(C`_symbol\*(C'\fR to \f(CW\*(C`_\|_imp_\|_symbol\*(C'\fR for +\&\s-1DATA\s0 imports from DLLs, and create the necessary thunking symbols when +building the import libraries with those \s-1DATA\s0 exports. Note: Use of the +\&'auto\-import' extension will cause the text section of the image file +to be made writable. This does not conform to the PE-COFF format +specification published by Microsoft. +.Sp +Note \- use of the 'auto\-import' extension will also cause read only +data which would normally be placed into the .rdata section to be +placed into the .data section instead. This is in order to work +around a problem with consts that is described here: +http://www.cygwin.com/ml/cygwin/2004\-09/msg01101.html +.Sp +Using 'auto\-import' generally will 'just work' \*(-- but sometimes you may +see this message: +.Sp +"variable '<var>' can't be auto-imported. Please read the +documentation for ld's \f(CW\*(C`\-\-enable\-auto\-import\*(C'\fR for details." +.Sp +This message occurs when some (sub)expression accesses an address +ultimately given by the sum of two constants (Win32 import tables only +allow one). Instances where this may occur include accesses to member +fields of struct variables imported from a \s-1DLL\s0, as well as using a +constant index into an array variable imported from a \s-1DLL\s0. Any +multiword variable (arrays, structs, long long, etc) may trigger +this error condition. However, regardless of the exact data type +of the offending exported variable, ld will always detect it, issue +the warning, and exit. +.Sp +There are several ways to address this difficulty, regardless of the +data type of the exported variable: +.Sp +One way is to use \-\-enable\-runtime\-pseudo\-reloc switch. This leaves the task +of adjusting references in your client code for runtime environment, so +this method works only when runtime environment supports this feature. +.Sp +A second solution is to force one of the 'constants' to be a variable \*(-- +that is, unknown and un-optimizable at compile time. For arrays, +there are two possibilities: a) make the indexee (the array's address) +a variable, or b) make the 'constant' index a variable. Thus: +.Sp +.Vb 3 +\& extern type extern_array[]; +\& extern_array[1] \-\-> +\& { volatile type *t=extern_array; t[1] } +.Ve +.Sp +or +.Sp +.Vb 3 +\& extern type extern_array[]; +\& extern_array[1] \-\-> +\& { volatile int t=1; extern_array[t] } +.Ve +.Sp +For structs (and most other multiword data types) the only option +is to make the struct itself (or the long long, or the ...) variable: +.Sp +.Vb 3 +\& extern struct s extern_struct; +\& extern_struct.field \-\-> +\& { volatile struct s *t=&extern_struct; t\->field } +.Ve +.Sp +or +.Sp +.Vb 3 +\& extern long long extern_ll; +\& extern_ll \-\-> +\& { volatile long long * local_ll=&extern_ll; *local_ll } +.Ve +.Sp +A third method of dealing with this difficulty is to abandon +\&'auto\-import' for the offending symbol and mark it with +\&\f(CW\*(C`_\|_declspec(dllimport)\*(C'\fR. However, in practise that +requires using compile-time #defines to indicate whether you are +building a \s-1DLL\s0, building client code that will link to the \s-1DLL\s0, or +merely building/linking to a static library. In making the choice +between the various methods of resolving the 'direct address with +constant offset' problem, you should consider typical real-world usage: +.Sp +Original: +.Sp +.Vb 7 +\& \-\-foo.h +\& extern int arr[]; +\& \-\-foo.c +\& #include "foo.h" +\& void main(int argc, char **argv){ +\& printf("%d\en",arr[1]); +\& } +.Ve +.Sp +Solution 1: +.Sp +.Vb 9 +\& \-\-foo.h +\& extern int arr[]; +\& \-\-foo.c +\& #include "foo.h" +\& void main(int argc, char **argv){ +\& /* This workaround is for win32 and cygwin; do not "optimize" */ +\& volatile int *parr = arr; +\& printf("%d\en",parr[1]); +\& } +.Ve +.Sp +Solution 2: +.Sp +.Vb 10 +\& \-\-foo.h +\& /* Note: auto\-export is assumed (no _\|_declspec(dllexport)) */ +\& #if (defined(_WIN32) || defined(_\|_CYGWIN_\|_)) && \e +\& !(defined(FOO_BUILD_DLL) || defined(FOO_STATIC)) +\& #define FOO_IMPORT _\|_declspec(dllimport) +\& #else +\& #define FOO_IMPORT +\& #endif +\& extern FOO_IMPORT int arr[]; +\& \-\-foo.c +\& #include "foo.h" +\& void main(int argc, char **argv){ +\& printf("%d\en",arr[1]); +\& } +.Ve +.Sp +A fourth way to avoid this problem is to re-code your +library to use a functional interface rather than a data interface +for the offending variables (e.g. \fIset_foo()\fR and \fIget_foo()\fR accessor +functions). +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-disable\-auto\-import\fR" 4 +.IX Item "--disable-auto-import" +Do not attempt to do sophisticated linking of \f(CW\*(C`_symbol\*(C'\fR to +\&\f(CW\*(C`_\|_imp_\|_symbol\*(C'\fR for \s-1DATA\s0 imports from DLLs. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-enable\-runtime\-pseudo\-reloc\fR" 4 +.IX Item "--enable-runtime-pseudo-reloc" +If your code contains expressions described in \-\-enable\-auto\-import section, +that is, \s-1DATA\s0 imports from \s-1DLL\s0 with non-zero offset, this switch will create +a vector of 'runtime pseudo relocations' which can be used by runtime +environment to adjust references to such data in your client code. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-disable\-runtime\-pseudo\-reloc\fR" 4 +.IX Item "--disable-runtime-pseudo-reloc" +Do not create pseudo relocations for non-zero offset \s-1DATA\s0 imports from +DLLs. This is the default. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-enable\-extra\-pe\-debug\fR" 4 +.IX Item "--enable-extra-pe-debug" +Show additional debug info related to auto-import symbol thunking. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-section\-alignment\fR" 4 +.IX Item "--section-alignment" +Sets the section alignment. Sections in memory will always begin at +addresses which are a multiple of this number. Defaults to 0x1000. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-stack\fR \fIreserve\fR" 4 +.IX Item "--stack reserve" +.PD 0 +.IP "\fB\-\-stack\fR \fIreserve\fR\fB,\fR\fIcommit\fR" 4 +.IX Item "--stack reserve,commit" +.PD +Specify the number of bytes of memory to reserve (and optionally commit) +to be used as stack for this program. The default is 2Mb reserved, 4K +committed. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.IP "\fB\-\-subsystem\fR \fIwhich\fR" 4 +.IX Item "--subsystem which" +.PD 0 +.IP "\fB\-\-subsystem\fR \fIwhich\fR\fB:\fR\fImajor\fR" 4 +.IX Item "--subsystem which:major" +.IP "\fB\-\-subsystem\fR \fIwhich\fR\fB:\fR\fImajor\fR\fB.\fR\fIminor\fR" 4 +.IX Item "--subsystem which:major.minor" +.PD +Specifies the subsystem under which your program will execute. The +legal values for \fIwhich\fR are \f(CW\*(C`native\*(C'\fR, \f(CW\*(C`windows\*(C'\fR, +\&\f(CW\*(C`console\*(C'\fR, \f(CW\*(C`posix\*(C'\fR, and \f(CW\*(C`xbox\*(C'\fR. You may optionally set +the subsystem version also. Numeric values are also accepted for +\&\fIwhich\fR. +[This option is specific to the i386 \s-1PE\s0 targeted port of the linker] +.Sp +The following options set flags in the \f(CW\*(C`DllCharacteristics\*(C'\fR field +of the \s-1PE\s0 file header: +[These options are specific to \s-1PE\s0 targeted ports of the linker] +.IP "\fB\-\-dynamicbase\fR" 4 +.IX Item "--dynamicbase" +The image base address may be relocated using address space layout +randomization (\s-1ASLR\s0). This feature was introduced with \s-1MS\s0 Windows +Vista for i386 \s-1PE\s0 targets. +.IP "\fB\-\-forceinteg\fR" 4 +.IX Item "--forceinteg" +Code integrity checks are enforced. +.IP "\fB\-\-nxcompat\fR" 4 +.IX Item "--nxcompat" +The image is compatible with the Data Execution Prevention. +This feature was introduced with \s-1MS\s0 Windows \s-1XP\s0 \s-1SP2\s0 for i386 \s-1PE\s0 targets. +.IP "\fB\-\-no\-isolation\fR" 4 +.IX Item "--no-isolation" +Although the image understands isolation, do not isolate the image. +.IP "\fB\-\-no\-seh\fR" 4 +.IX Item "--no-seh" +The image does not use \s-1SEH\s0. No \s-1SE\s0 handler may be called from +this image. +.IP "\fB\-\-no\-bind\fR" 4 +.IX Item "--no-bind" +Do not bind this image. +.IP "\fB\-\-wdmdriver\fR" 4 +.IX Item "--wdmdriver" +The driver uses the \s-1MS\s0 Windows Driver Model. +.IP "\fB\-\-tsaware\fR" 4 +.IX Item "--tsaware" +The image is Terminal Server aware. +.PP +The 68HC11 and 68HC12 linkers support specific options to control the +memory bank switching mapping and trampoline code generation. +.IP "\fB\-\-no\-trampoline\fR" 4 +.IX Item "--no-trampoline" +This option disables the generation of trampoline. By default a trampoline +is generated for each far function which is called using a \f(CW\*(C`jsr\*(C'\fR +instruction (this happens when a pointer to a far function is taken). +.IP "\fB\-\-bank\-window\fR \fIname\fR" 4 +.IX Item "--bank-window name" +This option indicates to the linker the name of the memory region in +the \fB\s-1MEMORY\s0\fR specification that describes the memory bank window. +The definition of such region is then used by the linker to compute +paging and addresses within the memory window. +.PP +The following options are supported to control handling of \s-1GOT\s0 generation +when linking for 68K targets. +.IP "\fB\-\-got=\fR\fItype\fR" 4 +.IX Item "--got=type" +This option tells the linker which \s-1GOT\s0 generation scheme to use. +\&\fItype\fR should be one of \fBsingle\fR, \fBnegative\fR, +\&\fBmultigot\fR or \fBtarget\fR. For more information refer to the +Info entry for \fIld\fR. +.SH "ENVIRONMENT" +.IX Header "ENVIRONMENT" +You can change the behaviour of \fBld\fR with the environment variables +\&\f(CW\*(C`GNUTARGET\*(C'\fR, +\&\f(CW\*(C`LDEMULATION\*(C'\fR and \f(CW\*(C`COLLECT_NO_DEMANGLE\*(C'\fR. +.PP +\&\f(CW\*(C`GNUTARGET\*(C'\fR determines the input-file object format if you don't +use \fB\-b\fR (or its synonym \fB\-\-format\fR). Its value should be one +of the \s-1BFD\s0 names for an input format. If there is no +\&\f(CW\*(C`GNUTARGET\*(C'\fR in the environment, \fBld\fR uses the natural format +of the target. If \f(CW\*(C`GNUTARGET\*(C'\fR is set to \f(CW\*(C`default\*(C'\fR then \s-1BFD\s0 +attempts to discover the input format by examining binary input files; +this method often succeeds, but there are potential ambiguities, since +there is no method of ensuring that the magic number used to specify +object-file formats is unique. However, the configuration procedure for +\&\s-1BFD\s0 on each system places the conventional format for that system first +in the search-list, so ambiguities are resolved in favor of convention. +.PP +\&\f(CW\*(C`LDEMULATION\*(C'\fR determines the default emulation if you don't use the +\&\fB\-m\fR option. The emulation can affect various aspects of linker +behaviour, particularly the default linker script. You can list the +available emulations with the \fB\-\-verbose\fR or \fB\-V\fR options. If +the \fB\-m\fR option is not used, and the \f(CW\*(C`LDEMULATION\*(C'\fR environment +variable is not defined, the default emulation depends upon how the +linker was configured. +.PP +Normally, the linker will default to demangling symbols. However, if +\&\f(CW\*(C`COLLECT_NO_DEMANGLE\*(C'\fR is set in the environment, then it will +default to not demangling symbols. This environment variable is used in +a similar fashion by the \f(CW\*(C`gcc\*(C'\fR linker wrapper program. The default +may be overridden by the \fB\-\-demangle\fR and \fB\-\-no\-demangle\fR +options. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fIar\fR\|(1), \fInm\fR\|(1), \fIobjcopy\fR\|(1), \fIobjdump\fR\|(1), \fIreadelf\fR\|(1) and +the Info entries for \fIbinutils\fR and +\&\fIld\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, +1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free +Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 +or any later version published by the Free Software Foundation; +with no Invariant Sections, with no Front-Cover Texts, and with no +Back-Cover Texts. A copy of the license is included in the +section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". diff --git a/share/man/man1/arm-eabi-nlmconv.1 b/share/man/man1/arm-eabi-nlmconv.1 new file mode 100644 index 0000000..a43abb1 --- /dev/null +++ b/share/man/man1/arm-eabi-nlmconv.1 @@ -0,0 +1,244 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "NLMCONV 1" +.TH NLMCONV 1 " " "binutils-2.21" "GNU Development Tools" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +nlmconv \- converts object code into an NLM. +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +nlmconv [\fB\-I\fR \fIbfdname\fR|\fB\-\-input\-target=\fR\fIbfdname\fR] + [\fB\-O\fR \fIbfdname\fR|\fB\-\-output\-target=\fR\fIbfdname\fR] + [\fB\-T\fR \fIheaderfile\fR|\fB\-\-header\-file=\fR\fIheaderfile\fR] + [\fB\-d\fR|\fB\-\-debug\fR] [\fB\-l\fR \fIlinker\fR|\fB\-\-linker=\fR\fIlinker\fR] + [\fB\-h\fR|\fB\-\-help\fR] [\fB\-V\fR|\fB\-\-version\fR] + \fIinfile\fR \fIoutfile\fR +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +\&\fBnlmconv\fR converts the relocatable \fBi386\fR object file +\&\fIinfile\fR into the NetWare Loadable Module \fIoutfile\fR, optionally +reading \fIheaderfile\fR for \s-1NLM\s0 header information. For instructions +on writing the \s-1NLM\s0 command file language used in header files, see the +\&\fBlinkers\fR section, \fB\s-1NLMLINK\s0\fR in particular, of the \fI\s-1NLM\s0 +Development and Tools Overview\fR, which is part of the \s-1NLM\s0 Software +Developer's Kit (\*(L"\s-1NLM\s0 \s-1SDK\s0\*(R"), available from Novell, Inc. +\&\fBnlmconv\fR uses the \s-1GNU\s0 Binary File Descriptor library to read +\&\fIinfile\fR; +.PP +\&\fBnlmconv\fR can perform a link step. In other words, you can list +more than one object file for input if you list them in the definitions +file (rather than simply specifying one input file on the command line). +In this case, \fBnlmconv\fR calls the linker for you. +.SH "OPTIONS" +.IX Header "OPTIONS" +.IP "\fB\-I\fR \fIbfdname\fR" 4 +.IX Item "-I bfdname" +.PD 0 +.IP "\fB\-\-input\-target=\fR\fIbfdname\fR" 4 +.IX Item "--input-target=bfdname" +.PD +Object format of the input file. \fBnlmconv\fR can usually determine +the format of a given file (so no default is necessary). +.IP "\fB\-O\fR \fIbfdname\fR" 4 +.IX Item "-O bfdname" +.PD 0 +.IP "\fB\-\-output\-target=\fR\fIbfdname\fR" 4 +.IX Item "--output-target=bfdname" +.PD +Object format of the output file. \fBnlmconv\fR infers the output +format based on the input format, e.g. for a \fBi386\fR input file the +output format is \fBnlm32\-i386\fR. +.IP "\fB\-T\fR \fIheaderfile\fR" 4 +.IX Item "-T headerfile" +.PD 0 +.IP "\fB\-\-header\-file=\fR\fIheaderfile\fR" 4 +.IX Item "--header-file=headerfile" +.PD +Reads \fIheaderfile\fR for \s-1NLM\s0 header information. For instructions on +writing the \s-1NLM\s0 command file language used in header files, see see the +\&\fBlinkers\fR section, of the \fI\s-1NLM\s0 Development and Tools +Overview\fR, which is part of the \s-1NLM\s0 Software Developer's Kit, available +from Novell, Inc. +.IP "\fB\-d\fR" 4 +.IX Item "-d" +.PD 0 +.IP "\fB\-\-debug\fR" 4 +.IX Item "--debug" +.PD +Displays (on standard error) the linker command line used by \fBnlmconv\fR. +.IP "\fB\-l\fR \fIlinker\fR" 4 +.IX Item "-l linker" +.PD 0 +.IP "\fB\-\-linker=\fR\fIlinker\fR" 4 +.IX Item "--linker=linker" +.PD +Use \fIlinker\fR for any linking. \fIlinker\fR can be an absolute or a +relative pathname. +.IP "\fB\-h\fR" 4 +.IX Item "-h" +.PD 0 +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +.PD +Prints a usage summary. +.IP "\fB\-V\fR" 4 +.IX Item "-V" +.PD 0 +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +.PD +Prints the version number for \fBnlmconv\fR. +.IP "\fB@\fR\fIfile\fR" 4 +.IX Item "@file" +Read command-line options from \fIfile\fR. The options read are +inserted in place of the original @\fIfile\fR option. If \fIfile\fR +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +.Sp +Options in \fIfile\fR are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The \fIfile\fR may itself contain additional +@\fIfile\fR options; any such options will be processed recursively. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +the Info entries for \fIbinutils\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 +or any later version published by the Free Software Foundation; +with no Invariant Sections, with no Front-Cover Texts, and with no +Back-Cover Texts. A copy of the license is included in the +section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". diff --git a/share/man/man1/arm-eabi-nm.1 b/share/man/man1/arm-eabi-nm.1 new file mode 100644 index 0000000..8f629f9 --- /dev/null +++ b/share/man/man1/arm-eabi-nm.1 @@ -0,0 +1,516 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "NM 1" +.TH NM 1 " " "binutils-2.21" "GNU Development Tools" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +nm \- list symbols from object files +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +nm [\fB\-a\fR|\fB\-\-debug\-syms\fR] + [\fB\-g\fR|\fB\-\-extern\-only\fR][\fB\-\-plugin\fR \fIname\fR] + [\fB\-B\fR] [\fB\-C\fR|\fB\-\-demangle\fR[=\fIstyle\fR]] [\fB\-D\fR|\fB\-\-dynamic\fR] + [\fB\-S\fR|\fB\-\-print\-size\fR] [\fB\-s\fR|\fB\-\-print\-armap\fR] + [\fB\-A\fR|\fB\-o\fR|\fB\-\-print\-file\-name\fR][\fB\-\-special\-syms\fR] + [\fB\-n\fR|\fB\-v\fR|\fB\-\-numeric\-sort\fR] [\fB\-p\fR|\fB\-\-no\-sort\fR] + [\fB\-r\fR|\fB\-\-reverse\-sort\fR] [\fB\-\-size\-sort\fR] [\fB\-u\fR|\fB\-\-undefined\-only\fR] + [\fB\-t\fR \fIradix\fR|\fB\-\-radix=\fR\fIradix\fR] [\fB\-P\fR|\fB\-\-portability\fR] + [\fB\-\-target=\fR\fIbfdname\fR] [\fB\-f\fR\fIformat\fR|\fB\-\-format=\fR\fIformat\fR] + [\fB\-\-defined\-only\fR] [\fB\-l\fR|\fB\-\-line\-numbers\fR] [\fB\-\-no\-demangle\fR] + [\fB\-V\fR|\fB\-\-version\fR] [\fB\-X 32_64\fR] [\fB\-\-help\fR] [\fIobjfile\fR...] +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +\&\s-1GNU\s0 \fBnm\fR lists the symbols from object files \fIobjfile\fR.... +If no object files are listed as arguments, \fBnm\fR assumes the file +\&\fIa.out\fR. +.PP +For each symbol, \fBnm\fR shows: +.IP "\(bu" 4 +The symbol value, in the radix selected by options (see below), or +hexadecimal by default. +.IP "\(bu" 4 +The symbol type. At least the following types are used; others are, as +well, depending on the object file format. If lowercase, the symbol is +local; if uppercase, the symbol is global (external). +.RS 4 +.ie n .IP """A""" 4 +.el .IP "\f(CWA\fR" 4 +.IX Item "A" +The symbol's value is absolute, and will not be changed by further +linking. +.ie n .IP """B""" 4 +.el .IP "\f(CWB\fR" 4 +.IX Item "B" +.PD 0 +.ie n .IP """b""" 4 +.el .IP "\f(CWb\fR" 4 +.IX Item "b" +.PD +The symbol is in the uninitialized data section (known as \s-1BSS\s0). +.ie n .IP """C""" 4 +.el .IP "\f(CWC\fR" 4 +.IX Item "C" +The symbol is common. Common symbols are uninitialized data. When +linking, multiple common symbols may appear with the same name. If the +symbol is defined anywhere, the common symbols are treated as undefined +references. +.ie n .IP """D""" 4 +.el .IP "\f(CWD\fR" 4 +.IX Item "D" +.PD 0 +.ie n .IP """d""" 4 +.el .IP "\f(CWd\fR" 4 +.IX Item "d" +.PD +The symbol is in the initialized data section. +.ie n .IP """G""" 4 +.el .IP "\f(CWG\fR" 4 +.IX Item "G" +.PD 0 +.ie n .IP """g""" 4 +.el .IP "\f(CWg\fR" 4 +.IX Item "g" +.PD +The symbol is in an initialized data section for small objects. Some +object file formats permit more efficient access to small data objects, +such as a global int variable as opposed to a large global array. +.ie n .IP """i""" 4 +.el .IP "\f(CWi\fR" 4 +.IX Item "i" +For \s-1PE\s0 format files this indicates that the symbol is in a section +specific to the implementation of DLLs. For \s-1ELF\s0 format files this +indicates that the symbol is an indirect function. This is a \s-1GNU\s0 +extension to the standard set of \s-1ELF\s0 symbol types. It indicates a +symbol which if referenced by a relocation does not evaluate to its +address, but instead must be invoked at runtime. The runtime +execution will then return the value to be used in the relocation. +.ie n .IP """N""" 4 +.el .IP "\f(CWN\fR" 4 +.IX Item "N" +The symbol is a debugging symbol. +.ie n .IP """p""" 4 +.el .IP "\f(CWp\fR" 4 +.IX Item "p" +The symbols is in a stack unwind section. +.ie n .IP """R""" 4 +.el .IP "\f(CWR\fR" 4 +.IX Item "R" +.PD 0 +.ie n .IP """r""" 4 +.el .IP "\f(CWr\fR" 4 +.IX Item "r" +.PD +The symbol is in a read only data section. +.ie n .IP """S""" 4 +.el .IP "\f(CWS\fR" 4 +.IX Item "S" +.PD 0 +.ie n .IP """s""" 4 +.el .IP "\f(CWs\fR" 4 +.IX Item "s" +.PD +The symbol is in an uninitialized data section for small objects. +.ie n .IP """T""" 4 +.el .IP "\f(CWT\fR" 4 +.IX Item "T" +.PD 0 +.ie n .IP """t""" 4 +.el .IP "\f(CWt\fR" 4 +.IX Item "t" +.PD +The symbol is in the text (code) section. +.ie n .IP """U""" 4 +.el .IP "\f(CWU\fR" 4 +.IX Item "U" +The symbol is undefined. +.ie n .IP """u""" 4 +.el .IP "\f(CWu\fR" 4 +.IX Item "u" +The symbol is a unique global symbol. This is a \s-1GNU\s0 extension to the +standard set of \s-1ELF\s0 symbol bindings. For such a symbol the dynamic linker +will make sure that in the entire process there is just one symbol with +this name and type in use. +.ie n .IP """V""" 4 +.el .IP "\f(CWV\fR" 4 +.IX Item "V" +.PD 0 +.ie n .IP """v""" 4 +.el .IP "\f(CWv\fR" 4 +.IX Item "v" +.PD +The symbol is a weak object. When a weak defined symbol is linked with +a normal defined symbol, the normal defined symbol is used with no error. +When a weak undefined symbol is linked and the symbol is not defined, +the value of the weak symbol becomes zero with no error. On some +systems, uppercase indicates that a default value has been specified. +.ie n .IP """W""" 4 +.el .IP "\f(CWW\fR" 4 +.IX Item "W" +.PD 0 +.ie n .IP """w""" 4 +.el .IP "\f(CWw\fR" 4 +.IX Item "w" +.PD +The symbol is a weak symbol that has not been specifically tagged as a +weak object symbol. When a weak defined symbol is linked with a normal +defined symbol, the normal defined symbol is used with no error. +When a weak undefined symbol is linked and the symbol is not defined, +the value of the symbol is determined in a system-specific manner without +error. On some systems, uppercase indicates that a default value has been +specified. +.ie n .IP """\-""" 4 +.el .IP "\f(CW\-\fR" 4 +.IX Item "-" +The symbol is a stabs symbol in an a.out object file. In this case, the +next values printed are the stabs other field, the stabs desc field, and +the stab type. Stabs symbols are used to hold debugging information. +.ie n .IP """?""" 4 +.el .IP "\f(CW?\fR" 4 +.IX Item "?" +The symbol type is unknown, or object file format specific. +.RE +.RS 4 +.RE +.IP "\(bu" 4 +The symbol name. +.SH "OPTIONS" +.IX Header "OPTIONS" +The long and short forms of options, shown here as alternatives, are +equivalent. +.IP "\fB\-A\fR" 4 +.IX Item "-A" +.PD 0 +.IP "\fB\-o\fR" 4 +.IX Item "-o" +.IP "\fB\-\-print\-file\-name\fR" 4 +.IX Item "--print-file-name" +.PD +Precede each symbol by the name of the input file (or archive member) +in which it was found, rather than identifying the input file once only, +before all of its symbols. +.IP "\fB\-a\fR" 4 +.IX Item "-a" +.PD 0 +.IP "\fB\-\-debug\-syms\fR" 4 +.IX Item "--debug-syms" +.PD +Display all symbols, even debugger-only symbols; normally these are not +listed. +.IP "\fB\-B\fR" 4 +.IX Item "-B" +The same as \fB\-\-format=bsd\fR (for compatibility with the \s-1MIPS\s0 \fBnm\fR). +.IP "\fB\-C\fR" 4 +.IX Item "-C" +.PD 0 +.IP "\fB\-\-demangle[=\fR\fIstyle\fR\fB]\fR" 4 +.IX Item "--demangle[=style]" +.PD +Decode (\fIdemangle\fR) low-level symbol names into user-level names. +Besides removing any initial underscore prepended by the system, this +makes \*(C+ function names readable. Different compilers have different +mangling styles. The optional demangling style argument can be used to +choose an appropriate demangling style for your compiler. +.IP "\fB\-\-no\-demangle\fR" 4 +.IX Item "--no-demangle" +Do not demangle low-level symbol names. This is the default. +.IP "\fB\-D\fR" 4 +.IX Item "-D" +.PD 0 +.IP "\fB\-\-dynamic\fR" 4 +.IX Item "--dynamic" +.PD +Display the dynamic symbols rather than the normal symbols. This is +only meaningful for dynamic objects, such as certain types of shared +libraries. +.IP "\fB\-f\fR \fIformat\fR" 4 +.IX Item "-f format" +.PD 0 +.IP "\fB\-\-format=\fR\fIformat\fR" 4 +.IX Item "--format=format" +.PD +Use the output format \fIformat\fR, which can be \f(CW\*(C`bsd\*(C'\fR, +\&\f(CW\*(C`sysv\*(C'\fR, or \f(CW\*(C`posix\*(C'\fR. The default is \f(CW\*(C`bsd\*(C'\fR. +Only the first character of \fIformat\fR is significant; it can be +either upper or lower case. +.IP "\fB\-g\fR" 4 +.IX Item "-g" +.PD 0 +.IP "\fB\-\-extern\-only\fR" 4 +.IX Item "--extern-only" +.PD +Display only external symbols. +.IP "\fB\-\-plugin\fR \fIname\fR" 4 +.IX Item "--plugin name" +Load the plugin called \fIname\fR to add support for extra target +types. This option is only available if the toolchain has been built +with plugin support enabled. +.IP "\fB\-l\fR" 4 +.IX Item "-l" +.PD 0 +.IP "\fB\-\-line\-numbers\fR" 4 +.IX Item "--line-numbers" +.PD +For each symbol, use debugging information to try to find a filename and +line number. For a defined symbol, look for the line number of the +address of the symbol. For an undefined symbol, look for the line +number of a relocation entry which refers to the symbol. If line number +information can be found, print it after the other symbol information. +.IP "\fB\-n\fR" 4 +.IX Item "-n" +.PD 0 +.IP "\fB\-v\fR" 4 +.IX Item "-v" +.IP "\fB\-\-numeric\-sort\fR" 4 +.IX Item "--numeric-sort" +.PD +Sort symbols numerically by their addresses, rather than alphabetically +by their names. +.IP "\fB\-p\fR" 4 +.IX Item "-p" +.PD 0 +.IP "\fB\-\-no\-sort\fR" 4 +.IX Item "--no-sort" +.PD +Do not bother to sort the symbols in any order; print them in the order +encountered. +.IP "\fB\-P\fR" 4 +.IX Item "-P" +.PD 0 +.IP "\fB\-\-portability\fR" 4 +.IX Item "--portability" +.PD +Use the \s-1POSIX\s0.2 standard output format instead of the default format. +Equivalent to \fB\-f posix\fR. +.IP "\fB\-S\fR" 4 +.IX Item "-S" +.PD 0 +.IP "\fB\-\-print\-size\fR" 4 +.IX Item "--print-size" +.PD +Print both value and size of defined symbols for the \f(CW\*(C`bsd\*(C'\fR output style. +This option has no effect for object formats that do not record symbol +sizes, unless \fB\-\-size\-sort\fR is also used in which case a +calculated size is displayed. +.IP "\fB\-s\fR" 4 +.IX Item "-s" +.PD 0 +.IP "\fB\-\-print\-armap\fR" 4 +.IX Item "--print-armap" +.PD +When listing symbols from archive members, include the index: a mapping +(stored in the archive by \fBar\fR or \fBranlib\fR) of which modules +contain definitions for which names. +.IP "\fB\-r\fR" 4 +.IX Item "-r" +.PD 0 +.IP "\fB\-\-reverse\-sort\fR" 4 +.IX Item "--reverse-sort" +.PD +Reverse the order of the sort (whether numeric or alphabetic); let the +last come first. +.IP "\fB\-\-size\-sort\fR" 4 +.IX Item "--size-sort" +Sort symbols by size. The size is computed as the difference between +the value of the symbol and the value of the symbol with the next higher +value. If the \f(CW\*(C`bsd\*(C'\fR output format is used the size of the symbol +is printed, rather than the value, and \fB\-S\fR must be used in order +both size and value to be printed. +.IP "\fB\-\-special\-syms\fR" 4 +.IX Item "--special-syms" +Display symbols which have a target-specific special meaning. These +symbols are usually used by the target for some special processing and +are not normally helpful when included included in the normal symbol +lists. For example for \s-1ARM\s0 targets this option would skip the mapping +symbols used to mark transitions between \s-1ARM\s0 code, \s-1THUMB\s0 code and +data. +.IP "\fB\-t\fR \fIradix\fR" 4 +.IX Item "-t radix" +.PD 0 +.IP "\fB\-\-radix=\fR\fIradix\fR" 4 +.IX Item "--radix=radix" +.PD +Use \fIradix\fR as the radix for printing the symbol values. It must be +\&\fBd\fR for decimal, \fBo\fR for octal, or \fBx\fR for hexadecimal. +.IP "\fB\-\-target=\fR\fIbfdname\fR" 4 +.IX Item "--target=bfdname" +Specify an object code format other than your system's default format. +.IP "\fB\-u\fR" 4 +.IX Item "-u" +.PD 0 +.IP "\fB\-\-undefined\-only\fR" 4 +.IX Item "--undefined-only" +.PD +Display only undefined symbols (those external to each object file). +.IP "\fB\-\-defined\-only\fR" 4 +.IX Item "--defined-only" +Display only defined symbols for each object file. +.IP "\fB\-V\fR" 4 +.IX Item "-V" +.PD 0 +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +.PD +Show the version number of \fBnm\fR and exit. +.IP "\fB\-X\fR" 4 +.IX Item "-X" +This option is ignored for compatibility with the \s-1AIX\s0 version of +\&\fBnm\fR. It takes one parameter which must be the string +\&\fB32_64\fR. The default mode of \s-1AIX\s0 \fBnm\fR corresponds +to \fB\-X 32\fR, which is not supported by \s-1GNU\s0 \fBnm\fR. +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +Show a summary of the options to \fBnm\fR and exit. +.IP "\fB@\fR\fIfile\fR" 4 +.IX Item "@file" +Read command-line options from \fIfile\fR. The options read are +inserted in place of the original @\fIfile\fR option. If \fIfile\fR +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +.Sp +Options in \fIfile\fR are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The \fIfile\fR may itself contain additional +@\fIfile\fR options; any such options will be processed recursively. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fIar\fR\|(1), \fIobjdump\fR\|(1), \fIranlib\fR\|(1), and the Info entries for \fIbinutils\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 +or any later version published by the Free Software Foundation; +with no Invariant Sections, with no Front-Cover Texts, and with no +Back-Cover Texts. A copy of the license is included in the +section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". diff --git a/share/man/man1/arm-eabi-objcopy.1 b/share/man/man1/arm-eabi-objcopy.1 new file mode 100644 index 0000000..fcceb65 --- /dev/null +++ b/share/man/man1/arm-eabi-objcopy.1 @@ -0,0 +1,960 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "OBJCOPY 1" +.TH OBJCOPY 1 " " "binutils-2.21" "GNU Development Tools" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +objcopy \- copy and translate object files +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +objcopy [\fB\-F\fR \fIbfdname\fR|\fB\-\-target=\fR\fIbfdname\fR] + [\fB\-I\fR \fIbfdname\fR|\fB\-\-input\-target=\fR\fIbfdname\fR] + [\fB\-O\fR \fIbfdname\fR|\fB\-\-output\-target=\fR\fIbfdname\fR] + [\fB\-B\fR \fIbfdarch\fR|\fB\-\-binary\-architecture=\fR\fIbfdarch\fR] + [\fB\-S\fR|\fB\-\-strip\-all\fR] + [\fB\-g\fR|\fB\-\-strip\-debug\fR] + [\fB\-K\fR \fIsymbolname\fR|\fB\-\-keep\-symbol=\fR\fIsymbolname\fR] + [\fB\-N\fR \fIsymbolname\fR|\fB\-\-strip\-symbol=\fR\fIsymbolname\fR] + [\fB\-\-strip\-unneeded\-symbol=\fR\fIsymbolname\fR] + [\fB\-G\fR \fIsymbolname\fR|\fB\-\-keep\-global\-symbol=\fR\fIsymbolname\fR] + [\fB\-\-localize\-hidden\fR] + [\fB\-L\fR \fIsymbolname\fR|\fB\-\-localize\-symbol=\fR\fIsymbolname\fR] + [\fB\-\-globalize\-symbol=\fR\fIsymbolname\fR] + [\fB\-W\fR \fIsymbolname\fR|\fB\-\-weaken\-symbol=\fR\fIsymbolname\fR] + [\fB\-w\fR|\fB\-\-wildcard\fR] + [\fB\-x\fR|\fB\-\-discard\-all\fR] + [\fB\-X\fR|\fB\-\-discard\-locals\fR] + [\fB\-b\fR \fIbyte\fR|\fB\-\-byte=\fR\fIbyte\fR] + [\fB\-i\fR [\fIbreadth\fR]|\fB\-\-interleave\fR[=\fIbreadth\fR]] + [\fB\-\-interleave\-width=\fR\fIwidth\fR] + [\fB\-j\fR \fIsectionname\fR|\fB\-\-only\-section=\fR\fIsectionname\fR] + [\fB\-R\fR \fIsectionname\fR|\fB\-\-remove\-section=\fR\fIsectionname\fR] + [\fB\-p\fR|\fB\-\-preserve\-dates\fR] + [\fB\-\-debugging\fR] + [\fB\-\-gap\-fill=\fR\fIval\fR] + [\fB\-\-pad\-to=\fR\fIaddress\fR] + [\fB\-\-set\-start=\fR\fIval\fR] + [\fB\-\-adjust\-start=\fR\fIincr\fR] + [\fB\-\-change\-addresses=\fR\fIincr\fR] + [\fB\-\-change\-section\-address\fR \fIsection\fR{=,+,\-}\fIval\fR] + [\fB\-\-change\-section\-lma\fR \fIsection\fR{=,+,\-}\fIval\fR] + [\fB\-\-change\-section\-vma\fR \fIsection\fR{=,+,\-}\fIval\fR] + [\fB\-\-change\-warnings\fR] [\fB\-\-no\-change\-warnings\fR] + [\fB\-\-set\-section\-flags\fR \fIsection\fR=\fIflags\fR] + [\fB\-\-add\-section\fR \fIsectionname\fR=\fIfilename\fR] + [\fB\-\-rename\-section\fR \fIoldname\fR=\fInewname\fR[,\fIflags\fR]] + [\fB\-\-long\-section\-names\fR {enable,disable,keep}] + [\fB\-\-change\-leading\-char\fR] [\fB\-\-remove\-leading\-char\fR] + [\fB\-\-reverse\-bytes=\fR\fInum\fR] + [\fB\-\-srec\-len=\fR\fIival\fR] [\fB\-\-srec\-forceS3\fR] + [\fB\-\-redefine\-sym\fR \fIold\fR=\fInew\fR] + [\fB\-\-redefine\-syms=\fR\fIfilename\fR] + [\fB\-\-weaken\fR] + [\fB\-\-keep\-symbols=\fR\fIfilename\fR] + [\fB\-\-strip\-symbols=\fR\fIfilename\fR] + [\fB\-\-strip\-unneeded\-symbols=\fR\fIfilename\fR] + [\fB\-\-keep\-global\-symbols=\fR\fIfilename\fR] + [\fB\-\-localize\-symbols=\fR\fIfilename\fR] + [\fB\-\-globalize\-symbols=\fR\fIfilename\fR] + [\fB\-\-weaken\-symbols=\fR\fIfilename\fR] + [\fB\-\-alt\-machine\-code=\fR\fIindex\fR] + [\fB\-\-prefix\-symbols=\fR\fIstring\fR] + [\fB\-\-prefix\-sections=\fR\fIstring\fR] + [\fB\-\-prefix\-alloc\-sections=\fR\fIstring\fR] + [\fB\-\-add\-gnu\-debuglink=\fR\fIpath-to-file\fR] + [\fB\-\-keep\-file\-symbols\fR] + [\fB\-\-only\-keep\-debug\fR] + [\fB\-\-extract\-symbol\fR] + [\fB\-\-writable\-text\fR] + [\fB\-\-readonly\-text\fR] + [\fB\-\-pure\fR] + [\fB\-\-impure\fR] + [\fB\-\-file\-alignment=\fR\fInum\fR] + [\fB\-\-heap=\fR\fIsize\fR] + [\fB\-\-image\-base=\fR\fIaddress\fR] + [\fB\-\-section\-alignment=\fR\fInum\fR] + [\fB\-\-stack=\fR\fIsize\fR] + [\fB\-\-subsystem=\fR\fIwhich\fR:\fImajor\fR.\fIminor\fR] + [\fB\-\-compress\-debug\-sections\fR] + [\fB\-\-decompress\-debug\-sections\fR] + [\fB\-v\fR|\fB\-\-verbose\fR] + [\fB\-V\fR|\fB\-\-version\fR] + [\fB\-\-help\fR] [\fB\-\-info\fR] + \fIinfile\fR [\fIoutfile\fR] +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +The \s-1GNU\s0 \fBobjcopy\fR utility copies the contents of an object +file to another. \fBobjcopy\fR uses the \s-1GNU\s0 \s-1BFD\s0 Library to +read and write the object files. It can write the destination object +file in a format different from that of the source object file. The +exact behavior of \fBobjcopy\fR is controlled by command-line options. +Note that \fBobjcopy\fR should be able to copy a fully linked file +between any two formats. However, copying a relocatable object file +between any two formats may not work as expected. +.PP +\&\fBobjcopy\fR creates temporary files to do its translations and +deletes them afterward. \fBobjcopy\fR uses \s-1BFD\s0 to do all its +translation work; it has access to all the formats described in \s-1BFD\s0 +and thus is able to recognize most formats without being told +explicitly. +.PP +\&\fBobjcopy\fR can be used to generate S\-records by using an output +target of \fBsrec\fR (e.g., use \fB\-O srec\fR). +.PP +\&\fBobjcopy\fR can be used to generate a raw binary file by using an +output target of \fBbinary\fR (e.g., use \fB\-O binary\fR). When +\&\fBobjcopy\fR generates a raw binary file, it will essentially produce +a memory dump of the contents of the input object file. All symbols and +relocation information will be discarded. The memory dump will start at +the load address of the lowest section copied into the output file. +.PP +When generating an S\-record or a raw binary file, it may be helpful to +use \fB\-S\fR to remove sections containing debugging information. In +some cases \fB\-R\fR will be useful to remove sections which contain +information that is not needed by the binary file. +.PP +Note\-\-\-\fBobjcopy\fR is not able to change the endianness of its input +files. If the input format has an endianness (some formats do not), +\&\fBobjcopy\fR can only copy the inputs into file formats that have the +same endianness or which have no endianness (e.g., \fBsrec\fR). +(However, see the \fB\-\-reverse\-bytes\fR option.) +.SH "OPTIONS" +.IX Header "OPTIONS" +.IP "\fIinfile\fR" 4 +.IX Item "infile" +.PD 0 +.IP "\fIoutfile\fR" 4 +.IX Item "outfile" +.PD +The input and output files, respectively. +If you do not specify \fIoutfile\fR, \fBobjcopy\fR creates a +temporary file and destructively renames the result with +the name of \fIinfile\fR. +.IP "\fB\-I\fR \fIbfdname\fR" 4 +.IX Item "-I bfdname" +.PD 0 +.IP "\fB\-\-input\-target=\fR\fIbfdname\fR" 4 +.IX Item "--input-target=bfdname" +.PD +Consider the source file's object format to be \fIbfdname\fR, rather than +attempting to deduce it. +.IP "\fB\-O\fR \fIbfdname\fR" 4 +.IX Item "-O bfdname" +.PD 0 +.IP "\fB\-\-output\-target=\fR\fIbfdname\fR" 4 +.IX Item "--output-target=bfdname" +.PD +Write the output file using the object format \fIbfdname\fR. +.IP "\fB\-F\fR \fIbfdname\fR" 4 +.IX Item "-F bfdname" +.PD 0 +.IP "\fB\-\-target=\fR\fIbfdname\fR" 4 +.IX Item "--target=bfdname" +.PD +Use \fIbfdname\fR as the object format for both the input and the output +file; i.e., simply transfer data from source to destination with no +translation. +.IP "\fB\-B\fR \fIbfdarch\fR" 4 +.IX Item "-B bfdarch" +.PD 0 +.IP "\fB\-\-binary\-architecture=\fR\fIbfdarch\fR" 4 +.IX Item "--binary-architecture=bfdarch" +.PD +Useful when transforming a architecture-less input file into an object file. +In this case the output architecture can be set to \fIbfdarch\fR. This +option will be ignored if the input file has a known \fIbfdarch\fR. You +can access this binary data inside a program by referencing the special +symbols that are created by the conversion process. These symbols are +called _binary_\fIobjfile\fR_start, _binary_\fIobjfile\fR_end and +_binary_\fIobjfile\fR_size. e.g. you can transform a picture file into +an object file and then access it in your code using these symbols. +.IP "\fB\-j\fR \fIsectionname\fR" 4 +.IX Item "-j sectionname" +.PD 0 +.IP "\fB\-\-only\-section=\fR\fIsectionname\fR" 4 +.IX Item "--only-section=sectionname" +.PD +Copy only the named section from the input file to the output file. +This option may be given more than once. Note that using this option +inappropriately may make the output file unusable. +.IP "\fB\-R\fR \fIsectionname\fR" 4 +.IX Item "-R sectionname" +.PD 0 +.IP "\fB\-\-remove\-section=\fR\fIsectionname\fR" 4 +.IX Item "--remove-section=sectionname" +.PD +Remove any section named \fIsectionname\fR from the output file. This +option may be given more than once. Note that using this option +inappropriately may make the output file unusable. +.IP "\fB\-S\fR" 4 +.IX Item "-S" +.PD 0 +.IP "\fB\-\-strip\-all\fR" 4 +.IX Item "--strip-all" +.PD +Do not copy relocation and symbol information from the source file. +.IP "\fB\-g\fR" 4 +.IX Item "-g" +.PD 0 +.IP "\fB\-\-strip\-debug\fR" 4 +.IX Item "--strip-debug" +.PD +Do not copy debugging symbols or sections from the source file. +.IP "\fB\-\-strip\-unneeded\fR" 4 +.IX Item "--strip-unneeded" +Strip all symbols that are not needed for relocation processing. +.IP "\fB\-K\fR \fIsymbolname\fR" 4 +.IX Item "-K symbolname" +.PD 0 +.IP "\fB\-\-keep\-symbol=\fR\fIsymbolname\fR" 4 +.IX Item "--keep-symbol=symbolname" +.PD +When stripping symbols, keep symbol \fIsymbolname\fR even if it would +normally be stripped. This option may be given more than once. +.IP "\fB\-N\fR \fIsymbolname\fR" 4 +.IX Item "-N symbolname" +.PD 0 +.IP "\fB\-\-strip\-symbol=\fR\fIsymbolname\fR" 4 +.IX Item "--strip-symbol=symbolname" +.PD +Do not copy symbol \fIsymbolname\fR from the source file. This option +may be given more than once. +.IP "\fB\-\-strip\-unneeded\-symbol=\fR\fIsymbolname\fR" 4 +.IX Item "--strip-unneeded-symbol=symbolname" +Do not copy symbol \fIsymbolname\fR from the source file unless it is needed +by a relocation. This option may be given more than once. +.IP "\fB\-G\fR \fIsymbolname\fR" 4 +.IX Item "-G symbolname" +.PD 0 +.IP "\fB\-\-keep\-global\-symbol=\fR\fIsymbolname\fR" 4 +.IX Item "--keep-global-symbol=symbolname" +.PD +Keep only symbol \fIsymbolname\fR global. Make all other symbols local +to the file, so that they are not visible externally. This option may +be given more than once. +.IP "\fB\-\-localize\-hidden\fR" 4 +.IX Item "--localize-hidden" +In an \s-1ELF\s0 object, mark all symbols that have hidden or internal visibility +as local. This option applies on top of symbol-specific localization options +such as \fB\-L\fR. +.IP "\fB\-L\fR \fIsymbolname\fR" 4 +.IX Item "-L symbolname" +.PD 0 +.IP "\fB\-\-localize\-symbol=\fR\fIsymbolname\fR" 4 +.IX Item "--localize-symbol=symbolname" +.PD +Make symbol \fIsymbolname\fR local to the file, so that it is not +visible externally. This option may be given more than once. +.IP "\fB\-W\fR \fIsymbolname\fR" 4 +.IX Item "-W symbolname" +.PD 0 +.IP "\fB\-\-weaken\-symbol=\fR\fIsymbolname\fR" 4 +.IX Item "--weaken-symbol=symbolname" +.PD +Make symbol \fIsymbolname\fR weak. This option may be given more than once. +.IP "\fB\-\-globalize\-symbol=\fR\fIsymbolname\fR" 4 +.IX Item "--globalize-symbol=symbolname" +Give symbol \fIsymbolname\fR global scoping so that it is visible +outside of the file in which it is defined. This option may be given +more than once. +.IP "\fB\-w\fR" 4 +.IX Item "-w" +.PD 0 +.IP "\fB\-\-wildcard\fR" 4 +.IX Item "--wildcard" +.PD +Permit regular expressions in \fIsymbolname\fRs used in other command +line options. The question mark (?), asterisk (*), backslash (\e) and +square brackets ([]) operators can be used anywhere in the symbol +name. If the first character of the symbol name is the exclamation +point (!) then the sense of the switch is reversed for that symbol. +For example: +.Sp +.Vb 1 +\& \-w \-W !foo \-W fo* +.Ve +.Sp +would cause objcopy to weaken all symbols that start with \*(L"fo\*(R" +except for the symbol \*(L"foo\*(R". +.IP "\fB\-x\fR" 4 +.IX Item "-x" +.PD 0 +.IP "\fB\-\-discard\-all\fR" 4 +.IX Item "--discard-all" +.PD +Do not copy non-global symbols from the source file. +.IP "\fB\-X\fR" 4 +.IX Item "-X" +.PD 0 +.IP "\fB\-\-discard\-locals\fR" 4 +.IX Item "--discard-locals" +.PD +Do not copy compiler-generated local symbols. +(These usually start with \fBL\fR or \fB.\fR.) +.IP "\fB\-b\fR \fIbyte\fR" 4 +.IX Item "-b byte" +.PD 0 +.IP "\fB\-\-byte=\fR\fIbyte\fR" 4 +.IX Item "--byte=byte" +.PD +If interleaving has been enabled via the \fB\-\-interleave\fR option +then start the range of bytes to keep at the \fIbyte\fRth byte. +\&\fIbyte\fR can be in the range from 0 to \fIbreadth\fR\-1, where +\&\fIbreadth\fR is the value given by the \fB\-\-interleave\fR option. +.IP "\fB\-i [\fR\fIbreadth\fR\fB]\fR" 4 +.IX Item "-i [breadth]" +.PD 0 +.IP "\fB\-\-interleave[=\fR\fIbreadth\fR\fB]\fR" 4 +.IX Item "--interleave[=breadth]" +.PD +Only copy a range out of every \fIbreadth\fR bytes. (Header data is +not affected). Select which byte in the range begins the copy with +the \fB\-\-byte\fR option. Select the width of the range with the +\&\fB\-\-interleave\-width\fR option. +.Sp +This option is useful for creating files to program \s-1ROM\s0. It is +typically used with an \f(CW\*(C`srec\*(C'\fR output target. Note that +\&\fBobjcopy\fR will complain if you do not specify the +\&\fB\-\-byte\fR option as well. +.Sp +The default interleave breadth is 4, so with \fB\-\-byte\fR set to 0, +\&\fBobjcopy\fR would copy the first byte out of every four bytes +from the input to the output. +.IP "\fB\-\-interleave\-width=\fR\fIwidth\fR" 4 +.IX Item "--interleave-width=width" +When used with the \fB\-\-interleave\fR option, copy \fIwidth\fR +bytes at a time. The start of the range of bytes to be copied is set +by the \fB\-\-byte\fR option, and the extent of the range is set with +the \fB\-\-interleave\fR option. +.Sp +The default value for this option is 1. The value of \fIwidth\fR plus +the \fIbyte\fR value set by the \fB\-\-byte\fR option must not exceed +the interleave breadth set by the \fB\-\-interleave\fR option. +.Sp +This option can be used to create images for two 16\-bit flashes interleaved +in a 32\-bit bus by passing \fB\-b 0 \-i 4 \-\-interleave\-width=2\fR +and \fB\-b 2 \-i 4 \-\-interleave\-width=2\fR to two \fBobjcopy\fR +commands. If the input was '12345678' then the outputs would be +\&'1256' and '3478' respectively. +.IP "\fB\-p\fR" 4 +.IX Item "-p" +.PD 0 +.IP "\fB\-\-preserve\-dates\fR" 4 +.IX Item "--preserve-dates" +.PD +Set the access and modification dates of the output file to be the same +as those of the input file. +.IP "\fB\-\-debugging\fR" 4 +.IX Item "--debugging" +Convert debugging information, if possible. This is not the default +because only certain debugging formats are supported, and the +conversion process can be time consuming. +.IP "\fB\-\-gap\-fill\fR \fIval\fR" 4 +.IX Item "--gap-fill val" +Fill gaps between sections with \fIval\fR. This operation applies to +the \fIload address\fR (\s-1LMA\s0) of the sections. It is done by increasing +the size of the section with the lower address, and filling in the extra +space created with \fIval\fR. +.IP "\fB\-\-pad\-to\fR \fIaddress\fR" 4 +.IX Item "--pad-to address" +Pad the output file up to the load address \fIaddress\fR. This is +done by increasing the size of the last section. The extra space is +filled in with the value specified by \fB\-\-gap\-fill\fR (default zero). +.IP "\fB\-\-set\-start\fR \fIval\fR" 4 +.IX Item "--set-start val" +Set the start address of the new file to \fIval\fR. Not all object file +formats support setting the start address. +.IP "\fB\-\-change\-start\fR \fIincr\fR" 4 +.IX Item "--change-start incr" +.PD 0 +.IP "\fB\-\-adjust\-start\fR \fIincr\fR" 4 +.IX Item "--adjust-start incr" +.PD +Change the start address by adding \fIincr\fR. Not all object file +formats support setting the start address. +.IP "\fB\-\-change\-addresses\fR \fIincr\fR" 4 +.IX Item "--change-addresses incr" +.PD 0 +.IP "\fB\-\-adjust\-vma\fR \fIincr\fR" 4 +.IX Item "--adjust-vma incr" +.PD +Change the \s-1VMA\s0 and \s-1LMA\s0 addresses of all sections, as well as the start +address, by adding \fIincr\fR. Some object file formats do not permit +section addresses to be changed arbitrarily. Note that this does not +relocate the sections; if the program expects sections to be loaded at a +certain address, and this option is used to change the sections such +that they are loaded at a different address, the program may fail. +.IP "\fB\-\-change\-section\-address\fR \fIsection\fR\fB{=,+,\-}\fR\fIval\fR" 4 +.IX Item "--change-section-address section{=,+,-}val" +.PD 0 +.IP "\fB\-\-adjust\-section\-vma\fR \fIsection\fR\fB{=,+,\-}\fR\fIval\fR" 4 +.IX Item "--adjust-section-vma section{=,+,-}val" +.PD +Set or change both the \s-1VMA\s0 address and the \s-1LMA\s0 address of the named +\&\fIsection\fR. If \fB=\fR is used, the section address is set to +\&\fIval\fR. Otherwise, \fIval\fR is added to or subtracted from the +section address. See the comments under \fB\-\-change\-addresses\fR, +above. If \fIsection\fR does not exist in the input file, a warning will +be issued, unless \fB\-\-no\-change\-warnings\fR is used. +.IP "\fB\-\-change\-section\-lma\fR \fIsection\fR\fB{=,+,\-}\fR\fIval\fR" 4 +.IX Item "--change-section-lma section{=,+,-}val" +Set or change the \s-1LMA\s0 address of the named \fIsection\fR. The \s-1LMA\s0 +address is the address where the section will be loaded into memory at +program load time. Normally this is the same as the \s-1VMA\s0 address, which +is the address of the section at program run time, but on some systems, +especially those where a program is held in \s-1ROM\s0, the two can be +different. If \fB=\fR is used, the section address is set to +\&\fIval\fR. Otherwise, \fIval\fR is added to or subtracted from the +section address. See the comments under \fB\-\-change\-addresses\fR, +above. If \fIsection\fR does not exist in the input file, a warning +will be issued, unless \fB\-\-no\-change\-warnings\fR is used. +.IP "\fB\-\-change\-section\-vma\fR \fIsection\fR\fB{=,+,\-}\fR\fIval\fR" 4 +.IX Item "--change-section-vma section{=,+,-}val" +Set or change the \s-1VMA\s0 address of the named \fIsection\fR. The \s-1VMA\s0 +address is the address where the section will be located once the +program has started executing. Normally this is the same as the \s-1LMA\s0 +address, which is the address where the section will be loaded into +memory, but on some systems, especially those where a program is held in +\&\s-1ROM\s0, the two can be different. If \fB=\fR is used, the section address +is set to \fIval\fR. Otherwise, \fIval\fR is added to or subtracted +from the section address. See the comments under +\&\fB\-\-change\-addresses\fR, above. If \fIsection\fR does not exist in +the input file, a warning will be issued, unless +\&\fB\-\-no\-change\-warnings\fR is used. +.IP "\fB\-\-change\-warnings\fR" 4 +.IX Item "--change-warnings" +.PD 0 +.IP "\fB\-\-adjust\-warnings\fR" 4 +.IX Item "--adjust-warnings" +.PD +If \fB\-\-change\-section\-address\fR or \fB\-\-change\-section\-lma\fR or +\&\fB\-\-change\-section\-vma\fR is used, and the named section does not +exist, issue a warning. This is the default. +.IP "\fB\-\-no\-change\-warnings\fR" 4 +.IX Item "--no-change-warnings" +.PD 0 +.IP "\fB\-\-no\-adjust\-warnings\fR" 4 +.IX Item "--no-adjust-warnings" +.PD +Do not issue a warning if \fB\-\-change\-section\-address\fR or +\&\fB\-\-adjust\-section\-lma\fR or \fB\-\-adjust\-section\-vma\fR is used, even +if the named section does not exist. +.IP "\fB\-\-set\-section\-flags\fR \fIsection\fR\fB=\fR\fIflags\fR" 4 +.IX Item "--set-section-flags section=flags" +Set the flags for the named section. The \fIflags\fR argument is a +comma separated string of flag names. The recognized names are +\&\fBalloc\fR, \fBcontents\fR, \fBload\fR, \fBnoload\fR, +\&\fBreadonly\fR, \fBcode\fR, \fBdata\fR, \fBrom\fR, \fBshare\fR, and +\&\fBdebug\fR. You can set the \fBcontents\fR flag for a section which +does not have contents, but it is not meaningful to clear the +\&\fBcontents\fR flag of a section which does have contents\*(--just remove +the section instead. Not all flags are meaningful for all object file +formats. +.IP "\fB\-\-add\-section\fR \fIsectionname\fR\fB=\fR\fIfilename\fR" 4 +.IX Item "--add-section sectionname=filename" +Add a new section named \fIsectionname\fR while copying the file. The +contents of the new section are taken from the file \fIfilename\fR. The +size of the section will be the size of the file. This option only +works on file formats which can support sections with arbitrary names. +.IP "\fB\-\-rename\-section\fR \fIoldname\fR\fB=\fR\fInewname\fR\fB[,\fR\fIflags\fR\fB]\fR" 4 +.IX Item "--rename-section oldname=newname[,flags]" +Rename a section from \fIoldname\fR to \fInewname\fR, optionally +changing the section's flags to \fIflags\fR in the process. This has +the advantage over usng a linker script to perform the rename in that +the output stays as an object file and does not become a linked +executable. +.Sp +This option is particularly helpful when the input format is binary, +since this will always create a section called .data. If for example, +you wanted instead to create a section called .rodata containing binary +data you could use the following command line to achieve it: +.Sp +.Vb 3 +\& objcopy \-I binary \-O <output_format> \-B <architecture> \e +\& \-\-rename\-section .data=.rodata,alloc,load,readonly,data,contents \e +\& <input_binary_file> <output_object_file> +.Ve +.IP "\fB\-\-long\-section\-names {enable,disable,keep}\fR" 4 +.IX Item "--long-section-names {enable,disable,keep}" +Controls the handling of long section names when processing \f(CW\*(C`COFF\*(C'\fR +and \f(CW\*(C`PE\-COFF\*(C'\fR object formats. The default behaviour, \fBkeep\fR, +is to preserve long section names if any are present in the input file. +The \fBenable\fR and \fBdisable\fR options forcibly enable or disable +the use of long section names in the output object; when \fBdisable\fR +is in effect, any long section names in the input object will be truncated. +The \fBenable\fR option will only emit long section names if any are +present in the inputs; this is mostly the same as \fBkeep\fR, but it +is left undefined whether the \fBenable\fR option might force the +creation of an empty string table in the output file. +.IP "\fB\-\-change\-leading\-char\fR" 4 +.IX Item "--change-leading-char" +Some object file formats use special characters at the start of +symbols. The most common such character is underscore, which compilers +often add before every symbol. This option tells \fBobjcopy\fR to +change the leading character of every symbol when it converts between +object file formats. If the object file formats use the same leading +character, this option has no effect. Otherwise, it will add a +character, or remove a character, or change a character, as +appropriate. +.IP "\fB\-\-remove\-leading\-char\fR" 4 +.IX Item "--remove-leading-char" +If the first character of a global symbol is a special symbol leading +character used by the object file format, remove the character. The +most common symbol leading character is underscore. This option will +remove a leading underscore from all global symbols. This can be useful +if you want to link together objects of different file formats with +different conventions for symbol names. This is different from +\&\fB\-\-change\-leading\-char\fR because it always changes the symbol name +when appropriate, regardless of the object file format of the output +file. +.IP "\fB\-\-reverse\-bytes=\fR\fInum\fR" 4 +.IX Item "--reverse-bytes=num" +Reverse the bytes in a section with output contents. A section length must +be evenly divisible by the value given in order for the swap to be able to +take place. Reversing takes place before the interleaving is performed. +.Sp +This option is used typically in generating \s-1ROM\s0 images for problematic +target systems. For example, on some target boards, the 32\-bit words +fetched from 8\-bit ROMs are re-assembled in little-endian byte order +regardless of the \s-1CPU\s0 byte order. Depending on the programming model, the +endianness of the \s-1ROM\s0 may need to be modified. +.Sp +Consider a simple file with a section containing the following eight +bytes: \f(CW12345678\fR. +.Sp +Using \fB\-\-reverse\-bytes=2\fR for the above example, the bytes in the +output file would be ordered \f(CW21436587\fR. +.Sp +Using \fB\-\-reverse\-bytes=4\fR for the above example, the bytes in the +output file would be ordered \f(CW43218765\fR. +.Sp +By using \fB\-\-reverse\-bytes=2\fR for the above example, followed by +\&\fB\-\-reverse\-bytes=4\fR on the output file, the bytes in the second +output file would be ordered \f(CW34127856\fR. +.IP "\fB\-\-srec\-len=\fR\fIival\fR" 4 +.IX Item "--srec-len=ival" +Meaningful only for srec output. Set the maximum length of the Srecords +being produced to \fIival\fR. This length covers both address, data and +crc fields. +.IP "\fB\-\-srec\-forceS3\fR" 4 +.IX Item "--srec-forceS3" +Meaningful only for srec output. Avoid generation of S1/S2 records, +creating S3\-only record format. +.IP "\fB\-\-redefine\-sym\fR \fIold\fR\fB=\fR\fInew\fR" 4 +.IX Item "--redefine-sym old=new" +Change the name of a symbol \fIold\fR, to \fInew\fR. This can be useful +when one is trying link two things together for which you have no +source, and there are name collisions. +.IP "\fB\-\-redefine\-syms=\fR\fIfilename\fR" 4 +.IX Item "--redefine-syms=filename" +Apply \fB\-\-redefine\-sym\fR to each symbol pair "\fIold\fR \fInew\fR" +listed in the file \fIfilename\fR. \fIfilename\fR is simply a flat file, +with one symbol pair per line. Line comments may be introduced by the hash +character. This option may be given more than once. +.IP "\fB\-\-weaken\fR" 4 +.IX Item "--weaken" +Change all global symbols in the file to be weak. This can be useful +when building an object which will be linked against other objects using +the \fB\-R\fR option to the linker. This option is only effective when +using an object file format which supports weak symbols. +.IP "\fB\-\-keep\-symbols=\fR\fIfilename\fR" 4 +.IX Item "--keep-symbols=filename" +Apply \fB\-\-keep\-symbol\fR option to each symbol listed in the file +\&\fIfilename\fR. \fIfilename\fR is simply a flat file, with one symbol +name per line. Line comments may be introduced by the hash character. +This option may be given more than once. +.IP "\fB\-\-strip\-symbols=\fR\fIfilename\fR" 4 +.IX Item "--strip-symbols=filename" +Apply \fB\-\-strip\-symbol\fR option to each symbol listed in the file +\&\fIfilename\fR. \fIfilename\fR is simply a flat file, with one symbol +name per line. Line comments may be introduced by the hash character. +This option may be given more than once. +.IP "\fB\-\-strip\-unneeded\-symbols=\fR\fIfilename\fR" 4 +.IX Item "--strip-unneeded-symbols=filename" +Apply \fB\-\-strip\-unneeded\-symbol\fR option to each symbol listed in +the file \fIfilename\fR. \fIfilename\fR is simply a flat file, with one +symbol name per line. Line comments may be introduced by the hash +character. This option may be given more than once. +.IP "\fB\-\-keep\-global\-symbols=\fR\fIfilename\fR" 4 +.IX Item "--keep-global-symbols=filename" +Apply \fB\-\-keep\-global\-symbol\fR option to each symbol listed in the +file \fIfilename\fR. \fIfilename\fR is simply a flat file, with one +symbol name per line. Line comments may be introduced by the hash +character. This option may be given more than once. +.IP "\fB\-\-localize\-symbols=\fR\fIfilename\fR" 4 +.IX Item "--localize-symbols=filename" +Apply \fB\-\-localize\-symbol\fR option to each symbol listed in the file +\&\fIfilename\fR. \fIfilename\fR is simply a flat file, with one symbol +name per line. Line comments may be introduced by the hash character. +This option may be given more than once. +.IP "\fB\-\-globalize\-symbols=\fR\fIfilename\fR" 4 +.IX Item "--globalize-symbols=filename" +Apply \fB\-\-globalize\-symbol\fR option to each symbol listed in the file +\&\fIfilename\fR. \fIfilename\fR is simply a flat file, with one symbol +name per line. Line comments may be introduced by the hash character. +This option may be given more than once. +.IP "\fB\-\-weaken\-symbols=\fR\fIfilename\fR" 4 +.IX Item "--weaken-symbols=filename" +Apply \fB\-\-weaken\-symbol\fR option to each symbol listed in the file +\&\fIfilename\fR. \fIfilename\fR is simply a flat file, with one symbol +name per line. Line comments may be introduced by the hash character. +This option may be given more than once. +.IP "\fB\-\-alt\-machine\-code=\fR\fIindex\fR" 4 +.IX Item "--alt-machine-code=index" +If the output architecture has alternate machine codes, use the +\&\fIindex\fRth code instead of the default one. This is useful in case +a machine is assigned an official code and the tool-chain adopts the +new code, but other applications still depend on the original code +being used. For \s-1ELF\s0 based architectures if the \fIindex\fR +alternative does not exist then the value is treated as an absolute +number to be stored in the e_machine field of the \s-1ELF\s0 header. +.IP "\fB\-\-writable\-text\fR" 4 +.IX Item "--writable-text" +Mark the output text as writable. This option isn't meaningful for all +object file formats. +.IP "\fB\-\-readonly\-text\fR" 4 +.IX Item "--readonly-text" +Make the output text write protected. This option isn't meaningful for all +object file formats. +.IP "\fB\-\-pure\fR" 4 +.IX Item "--pure" +Mark the output file as demand paged. This option isn't meaningful for all +object file formats. +.IP "\fB\-\-impure\fR" 4 +.IX Item "--impure" +Mark the output file as impure. This option isn't meaningful for all +object file formats. +.IP "\fB\-\-prefix\-symbols=\fR\fIstring\fR" 4 +.IX Item "--prefix-symbols=string" +Prefix all symbols in the output file with \fIstring\fR. +.IP "\fB\-\-prefix\-sections=\fR\fIstring\fR" 4 +.IX Item "--prefix-sections=string" +Prefix all section names in the output file with \fIstring\fR. +.IP "\fB\-\-prefix\-alloc\-sections=\fR\fIstring\fR" 4 +.IX Item "--prefix-alloc-sections=string" +Prefix all the names of all allocated sections in the output file with +\&\fIstring\fR. +.IP "\fB\-\-add\-gnu\-debuglink=\fR\fIpath-to-file\fR" 4 +.IX Item "--add-gnu-debuglink=path-to-file" +Creates a .gnu_debuglink section which contains a reference to \fIpath-to-file\fR +and adds it to the output file. +.IP "\fB\-\-keep\-file\-symbols\fR" 4 +.IX Item "--keep-file-symbols" +When stripping a file, perhaps with \fB\-\-strip\-debug\fR or +\&\fB\-\-strip\-unneeded\fR, retain any symbols specifying source file names, +which would otherwise get stripped. +.IP "\fB\-\-only\-keep\-debug\fR" 4 +.IX Item "--only-keep-debug" +Strip a file, removing contents of any sections that would not be +stripped by \fB\-\-strip\-debug\fR and leaving the debugging sections +intact. In \s-1ELF\s0 files, this preserves all note sections in the output. +.Sp +The intention is that this option will be used in conjunction with +\&\fB\-\-add\-gnu\-debuglink\fR to create a two part executable. One a +stripped binary which will occupy less space in \s-1RAM\s0 and in a +distribution and the second a debugging information file which is only +needed if debugging abilities are required. The suggested procedure +to create these files is as follows: +.RS 4 +.IP "1.<Link the executable as normal. Assuming that is is called>" 4 +.IX Item "1.<Link the executable as normal. Assuming that is is called>" +\&\f(CW\*(C`foo\*(C'\fR then... +.ie n .IP "1.<Run ""objcopy \-\-only\-keep\-debug foo foo.dbg"" to>" 4 +.el .IP "1.<Run \f(CWobjcopy \-\-only\-keep\-debug foo foo.dbg\fR to>" 4 +.IX Item "1.<Run objcopy --only-keep-debug foo foo.dbg to>" +create a file containing the debugging info. +.ie n .IP "1.<Run ""objcopy \-\-strip\-debug foo"" to create a>" 4 +.el .IP "1.<Run \f(CWobjcopy \-\-strip\-debug foo\fR to create a>" 4 +.IX Item "1.<Run objcopy --strip-debug foo to create a>" +stripped executable. +.ie n .IP "1.<Run ""objcopy \-\-add\-gnu\-debuglink=foo.dbg foo"">" 4 +.el .IP "1.<Run \f(CWobjcopy \-\-add\-gnu\-debuglink=foo.dbg foo\fR>" 4 +.IX Item "1.<Run objcopy --add-gnu-debuglink=foo.dbg foo>" +to add a link to the debugging info into the stripped executable. +.RE +.RS 4 +.Sp +Note\-\-\-the choice of \f(CW\*(C`.dbg\*(C'\fR as an extension for the debug info +file is arbitrary. Also the \f(CW\*(C`\-\-only\-keep\-debug\*(C'\fR step is +optional. You could instead do this: +.IP "1.<Link the executable as normal.>" 4 +.IX Item "1.<Link the executable as normal.>" +.PD 0 +.ie n .IP "1.<Copy ""foo"" to ""foo.full"">" 4 +.el .IP "1.<Copy \f(CWfoo\fR to \f(CWfoo.full\fR>" 4 +.IX Item "1.<Copy foo to foo.full>" +.ie n .IP "1.<Run ""objcopy \-\-strip\-debug foo"">" 4 +.el .IP "1.<Run \f(CWobjcopy \-\-strip\-debug foo\fR>" 4 +.IX Item "1.<Run objcopy --strip-debug foo>" +.ie n .IP "1.<Run ""objcopy \-\-add\-gnu\-debuglink=foo.full foo"">" 4 +.el .IP "1.<Run \f(CWobjcopy \-\-add\-gnu\-debuglink=foo.full foo\fR>" 4 +.IX Item "1.<Run objcopy --add-gnu-debuglink=foo.full foo>" +.RE +.RS 4 +.PD +.Sp +i.e., the file pointed to by the \fB\-\-add\-gnu\-debuglink\fR can be the +full executable. It does not have to be a file created by the +\&\fB\-\-only\-keep\-debug\fR switch. +.Sp +Note\-\-\-this switch is only intended for use on fully linked files. It +does not make sense to use it on object files where the debugging +information may be incomplete. Besides the gnu_debuglink feature +currently only supports the presence of one filename containing +debugging information, not multiple filenames on a one-per-object-file +basis. +.RE +.IP "\fB\-\-file\-alignment\fR \fInum\fR" 4 +.IX Item "--file-alignment num" +Specify the file alignment. Sections in the file will always begin at +file offsets which are multiples of this number. This defaults to +512. +[This option is specific to \s-1PE\s0 targets.] +.IP "\fB\-\-heap\fR \fIreserve\fR" 4 +.IX Item "--heap reserve" +.PD 0 +.IP "\fB\-\-heap\fR \fIreserve\fR\fB,\fR\fIcommit\fR" 4 +.IX Item "--heap reserve,commit" +.PD +Specify the number of bytes of memory to reserve (and optionally commit) +to be used as heap for this program. +[This option is specific to \s-1PE\s0 targets.] +.IP "\fB\-\-image\-base\fR \fIvalue\fR" 4 +.IX Item "--image-base value" +Use \fIvalue\fR as the base address of your program or dll. This is +the lowest memory location that will be used when your program or dll +is loaded. To reduce the need to relocate and improve performance of +your dlls, each should have a unique base address and not overlap any +other dlls. The default is 0x400000 for executables, and 0x10000000 +for dlls. +[This option is specific to \s-1PE\s0 targets.] +.IP "\fB\-\-section\-alignment\fR \fInum\fR" 4 +.IX Item "--section-alignment num" +Sets the section alignment. Sections in memory will always begin at +addresses which are a multiple of this number. Defaults to 0x1000. +[This option is specific to \s-1PE\s0 targets.] +.IP "\fB\-\-stack\fR \fIreserve\fR" 4 +.IX Item "--stack reserve" +.PD 0 +.IP "\fB\-\-stack\fR \fIreserve\fR\fB,\fR\fIcommit\fR" 4 +.IX Item "--stack reserve,commit" +.PD +Specify the number of bytes of memory to reserve (and optionally commit) +to be used as stack for this program. +[This option is specific to \s-1PE\s0 targets.] +.IP "\fB\-\-subsystem\fR \fIwhich\fR" 4 +.IX Item "--subsystem which" +.PD 0 +.IP "\fB\-\-subsystem\fR \fIwhich\fR\fB:\fR\fImajor\fR" 4 +.IX Item "--subsystem which:major" +.IP "\fB\-\-subsystem\fR \fIwhich\fR\fB:\fR\fImajor\fR\fB.\fR\fIminor\fR" 4 +.IX Item "--subsystem which:major.minor" +.PD +Specifies the subsystem under which your program will execute. The +legal values for \fIwhich\fR are \f(CW\*(C`native\*(C'\fR, \f(CW\*(C`windows\*(C'\fR, +\&\f(CW\*(C`console\*(C'\fR, \f(CW\*(C`posix\*(C'\fR, \f(CW\*(C`efi\-app\*(C'\fR, \f(CW\*(C`efi\-bsd\*(C'\fR, +\&\f(CW\*(C`efi\-rtd\*(C'\fR, \f(CW\*(C`sal\-rtd\*(C'\fR, and \f(CW\*(C`xbox\*(C'\fR. You may optionally set +the subsystem version also. Numeric values are also accepted for +\&\fIwhich\fR. +[This option is specific to \s-1PE\s0 targets.] +.IP "\fB\-\-extract\-symbol\fR" 4 +.IX Item "--extract-symbol" +Keep the file's section flags and symbols but remove all section data. +Specifically, the option: +.RS 4 +.IP "*<removes the contents of all sections;>" 4 +.IX Item "*<removes the contents of all sections;>" +.PD 0 +.IP "*<sets the size of every section to zero; and>" 4 +.IX Item "*<sets the size of every section to zero; and>" +.IP "*<sets the file's start address to zero.>" 4 +.IX Item "*<sets the file's start address to zero.>" +.RE +.RS 4 +.PD +.Sp +This option is used to build a \fI.sym\fR file for a VxWorks kernel. +It can also be a useful way of reducing the size of a \fB\-\-just\-symbols\fR +linker input file. +.RE +.IP "\fB\-\-compress\-debug\-sections\fR" 4 +.IX Item "--compress-debug-sections" +Compress \s-1DWARF\s0 debug sections using zlib. +.IP "\fB\-\-decompress\-debug\-sections\fR" 4 +.IX Item "--decompress-debug-sections" +Decompress \s-1DWARF\s0 debug sections using zlib. +.IP "\fB\-V\fR" 4 +.IX Item "-V" +.PD 0 +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +.PD +Show the version number of \fBobjcopy\fR. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +.PD 0 +.IP "\fB\-\-verbose\fR" 4 +.IX Item "--verbose" +.PD +Verbose output: list all object files modified. In the case of +archives, \fBobjcopy \-V\fR lists all members of the archive. +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +Show a summary of the options to \fBobjcopy\fR. +.IP "\fB\-\-info\fR" 4 +.IX Item "--info" +Display a list showing all architectures and object formats available. +.IP "\fB@\fR\fIfile\fR" 4 +.IX Item "@file" +Read command-line options from \fIfile\fR. The options read are +inserted in place of the original @\fIfile\fR option. If \fIfile\fR +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +.Sp +Options in \fIfile\fR are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The \fIfile\fR may itself contain additional +@\fIfile\fR options; any such options will be processed recursively. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fIld\fR\|(1), \fIobjdump\fR\|(1), and the Info entries for \fIbinutils\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 +or any later version published by the Free Software Foundation; +with no Invariant Sections, with no Front-Cover Texts, and with no +Back-Cover Texts. A copy of the license is included in the +section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". diff --git a/share/man/man1/arm-eabi-objdump.1 b/share/man/man1/arm-eabi-objdump.1 new file mode 100644 index 0000000..02c7075 --- /dev/null +++ b/share/man/man1/arm-eabi-objdump.1 @@ -0,0 +1,799 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "OBJDUMP 1" +.TH OBJDUMP 1 " " "binutils-2.21" "GNU Development Tools" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +objdump \- display information from object files. +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +objdump [\fB\-a\fR|\fB\-\-archive\-headers\fR] + [\fB\-b\fR \fIbfdname\fR|\fB\-\-target=\fR\fIbfdname\fR] + [\fB\-C\fR|\fB\-\-demangle\fR[=\fIstyle\fR] ] + [\fB\-d\fR|\fB\-\-disassemble\fR] + [\fB\-D\fR|\fB\-\-disassemble\-all\fR] + [\fB\-z\fR|\fB\-\-disassemble\-zeroes\fR] + [\fB\-EB\fR|\fB\-EL\fR|\fB\-\-endian=\fR{big | little }] + [\fB\-f\fR|\fB\-\-file\-headers\fR] + [\fB\-F\fR|\fB\-\-file\-offsets\fR] + [\fB\-\-file\-start\-context\fR] + [\fB\-g\fR|\fB\-\-debugging\fR] + [\fB\-e\fR|\fB\-\-debugging\-tags\fR] + [\fB\-h\fR|\fB\-\-section\-headers\fR|\fB\-\-headers\fR] + [\fB\-i\fR|\fB\-\-info\fR] + [\fB\-j\fR \fIsection\fR|\fB\-\-section=\fR\fIsection\fR] + [\fB\-l\fR|\fB\-\-line\-numbers\fR] + [\fB\-S\fR|\fB\-\-source\fR] + [\fB\-m\fR \fImachine\fR|\fB\-\-architecture=\fR\fImachine\fR] + [\fB\-M\fR \fIoptions\fR|\fB\-\-disassembler\-options=\fR\fIoptions\fR] + [\fB\-p\fR|\fB\-\-private\-headers\fR] + [\fB\-r\fR|\fB\-\-reloc\fR] + [\fB\-R\fR|\fB\-\-dynamic\-reloc\fR] + [\fB\-s\fR|\fB\-\-full\-contents\fR] + [\fB\-W[lLiaprmfFsoRt]\fR| + \fB\-\-dwarf\fR[=rawline,=decodedline,=info,=abbrev,=pubnames,=aranges,=macro,=frames,=frames\-interp,=str,=loc,=Ranges,=pubtypes,=trace_info,=trace_abbrev,=trace_aranges]] + [\fB\-G\fR|\fB\-\-stabs\fR] + [\fB\-t\fR|\fB\-\-syms\fR] + [\fB\-T\fR|\fB\-\-dynamic\-syms\fR] + [\fB\-x\fR|\fB\-\-all\-headers\fR] + [\fB\-w\fR|\fB\-\-wide\fR] + [\fB\-\-start\-address=\fR\fIaddress\fR] + [\fB\-\-stop\-address=\fR\fIaddress\fR] + [\fB\-\-prefix\-addresses\fR] + [\fB\-\-[no\-]show\-raw\-insn\fR] + [\fB\-\-adjust\-vma=\fR\fIoffset\fR] + [\fB\-\-special\-syms\fR] + [\fB\-\-prefix=\fR\fIprefix\fR] + [\fB\-\-prefix\-strip=\fR\fIlevel\fR] + [\fB\-\-insn\-width=\fR\fIwidth\fR] + [\fB\-V\fR|\fB\-\-version\fR] + [\fB\-H\fR|\fB\-\-help\fR] + \fIobjfile\fR... +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +\&\fBobjdump\fR displays information about one or more object files. +The options control what particular information to display. This +information is mostly useful to programmers who are working on the +compilation tools, as opposed to programmers who just want their +program to compile and work. +.PP +\&\fIobjfile\fR... are the object files to be examined. When you +specify archives, \fBobjdump\fR shows information on each of the member +object files. +.SH "OPTIONS" +.IX Header "OPTIONS" +The long and short forms of options, shown here as alternatives, are +equivalent. At least one option from the list +\&\fB\-a,\-d,\-D,\-e,\-f,\-g,\-G,\-h,\-H,\-p,\-r,\-R,\-s,\-S,\-t,\-T,\-V,\-x\fR must be given. +.IP "\fB\-a\fR" 4 +.IX Item "-a" +.PD 0 +.IP "\fB\-\-archive\-header\fR" 4 +.IX Item "--archive-header" +.PD +If any of the \fIobjfile\fR files are archives, display the archive +header information (in a format similar to \fBls \-l\fR). Besides the +information you could list with \fBar tv\fR, \fBobjdump \-a\fR shows +the object file format of each archive member. +.IP "\fB\-\-adjust\-vma=\fR\fIoffset\fR" 4 +.IX Item "--adjust-vma=offset" +When dumping information, first add \fIoffset\fR to all the section +addresses. This is useful if the section addresses do not correspond to +the symbol table, which can happen when putting sections at particular +addresses when using a format which can not represent section addresses, +such as a.out. +.IP "\fB\-b\fR \fIbfdname\fR" 4 +.IX Item "-b bfdname" +.PD 0 +.IP "\fB\-\-target=\fR\fIbfdname\fR" 4 +.IX Item "--target=bfdname" +.PD +Specify that the object-code format for the object files is +\&\fIbfdname\fR. This option may not be necessary; \fIobjdump\fR can +automatically recognize many formats. +.Sp +For example, +.Sp +.Vb 1 +\& objdump \-b oasys \-m vax \-h fu.o +.Ve +.Sp +displays summary information from the section headers (\fB\-h\fR) of +\&\fIfu.o\fR, which is explicitly identified (\fB\-m\fR) as a \s-1VAX\s0 object +file in the format produced by Oasys compilers. You can list the +formats available with the \fB\-i\fR option. +.IP "\fB\-C\fR" 4 +.IX Item "-C" +.PD 0 +.IP "\fB\-\-demangle[=\fR\fIstyle\fR\fB]\fR" 4 +.IX Item "--demangle[=style]" +.PD +Decode (\fIdemangle\fR) low-level symbol names into user-level names. +Besides removing any initial underscore prepended by the system, this +makes \*(C+ function names readable. Different compilers have different +mangling styles. The optional demangling style argument can be used to +choose an appropriate demangling style for your compiler. +.IP "\fB\-g\fR" 4 +.IX Item "-g" +.PD 0 +.IP "\fB\-\-debugging\fR" 4 +.IX Item "--debugging" +.PD +Display debugging information. This attempts to parse \s-1STABS\s0 and \s-1IEEE\s0 +debugging format information stored in the file and print it out using +a C like syntax. If neither of these formats are found this option +falls back on the \fB\-W\fR option to print any \s-1DWARF\s0 information in +the file. +.IP "\fB\-e\fR" 4 +.IX Item "-e" +.PD 0 +.IP "\fB\-\-debugging\-tags\fR" 4 +.IX Item "--debugging-tags" +.PD +Like \fB\-g\fR, but the information is generated in a format compatible +with ctags tool. +.IP "\fB\-d\fR" 4 +.IX Item "-d" +.PD 0 +.IP "\fB\-\-disassemble\fR" 4 +.IX Item "--disassemble" +.PD +Display the assembler mnemonics for the machine instructions from +\&\fIobjfile\fR. This option only disassembles those sections which are +expected to contain instructions. +.IP "\fB\-D\fR" 4 +.IX Item "-D" +.PD 0 +.IP "\fB\-\-disassemble\-all\fR" 4 +.IX Item "--disassemble-all" +.PD +Like \fB\-d\fR, but disassemble the contents of all sections, not just +those expected to contain instructions. +.Sp +If the target is an \s-1ARM\s0 architecture this switch also has the effect +of forcing the disassembler to decode pieces of data found in code +sections as if they were instructions. +.IP "\fB\-\-prefix\-addresses\fR" 4 +.IX Item "--prefix-addresses" +When disassembling, print the complete address on each line. This is +the older disassembly format. +.IP "\fB\-EB\fR" 4 +.IX Item "-EB" +.PD 0 +.IP "\fB\-EL\fR" 4 +.IX Item "-EL" +.IP "\fB\-\-endian={big|little}\fR" 4 +.IX Item "--endian={big|little}" +.PD +Specify the endianness of the object files. This only affects +disassembly. This can be useful when disassembling a file format which +does not describe endianness information, such as S\-records. +.IP "\fB\-f\fR" 4 +.IX Item "-f" +.PD 0 +.IP "\fB\-\-file\-headers\fR" 4 +.IX Item "--file-headers" +.PD +Display summary information from the overall header of +each of the \fIobjfile\fR files. +.IP "\fB\-F\fR" 4 +.IX Item "-F" +.PD 0 +.IP "\fB\-\-file\-offsets\fR" 4 +.IX Item "--file-offsets" +.PD +When disassembling sections, whenever a symbol is displayed, also +display the file offset of the region of data that is about to be +dumped. If zeroes are being skipped, then when disassembly resumes, +tell the user how many zeroes were skipped and the file offset of the +location from where the disassembly resumes. When dumping sections, +display the file offset of the location from where the dump starts. +.IP "\fB\-\-file\-start\-context\fR" 4 +.IX Item "--file-start-context" +Specify that when displaying interlisted source code/disassembly +(assumes \fB\-S\fR) from a file that has not yet been displayed, extend the +context to the start of the file. +.IP "\fB\-h\fR" 4 +.IX Item "-h" +.PD 0 +.IP "\fB\-\-section\-headers\fR" 4 +.IX Item "--section-headers" +.IP "\fB\-\-headers\fR" 4 +.IX Item "--headers" +.PD +Display summary information from the section headers of the +object file. +.Sp +File segments may be relocated to nonstandard addresses, for example by +using the \fB\-Ttext\fR, \fB\-Tdata\fR, or \fB\-Tbss\fR options to +\&\fBld\fR. However, some object file formats, such as a.out, do not +store the starting address of the file segments. In those situations, +although \fBld\fR relocates the sections correctly, using \fBobjdump +\&\-h\fR to list the file section headers cannot show the correct addresses. +Instead, it shows the usual addresses, which are implicit for the +target. +.IP "\fB\-H\fR" 4 +.IX Item "-H" +.PD 0 +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +.PD +Print a summary of the options to \fBobjdump\fR and exit. +.IP "\fB\-i\fR" 4 +.IX Item "-i" +.PD 0 +.IP "\fB\-\-info\fR" 4 +.IX Item "--info" +.PD +Display a list showing all architectures and object formats available +for specification with \fB\-b\fR or \fB\-m\fR. +.IP "\fB\-j\fR \fIname\fR" 4 +.IX Item "-j name" +.PD 0 +.IP "\fB\-\-section=\fR\fIname\fR" 4 +.IX Item "--section=name" +.PD +Display information only for section \fIname\fR. +.IP "\fB\-l\fR" 4 +.IX Item "-l" +.PD 0 +.IP "\fB\-\-line\-numbers\fR" 4 +.IX Item "--line-numbers" +.PD +Label the display (using debugging information) with the filename and +source line numbers corresponding to the object code or relocs shown. +Only useful with \fB\-d\fR, \fB\-D\fR, or \fB\-r\fR. +.IP "\fB\-m\fR \fImachine\fR" 4 +.IX Item "-m machine" +.PD 0 +.IP "\fB\-\-architecture=\fR\fImachine\fR" 4 +.IX Item "--architecture=machine" +.PD +Specify the architecture to use when disassembling object files. This +can be useful when disassembling object files which do not describe +architecture information, such as S\-records. You can list the available +architectures with the \fB\-i\fR option. +.Sp +If the target is an \s-1ARM\s0 architecture then this switch has an +additional effect. It restricts the disassembly to only those +instructions supported by the architecture specified by \fImachine\fR. +If it is necessary to use this switch because the input file does not +contain any architecture information, but it is also desired to +disassemble all the instructions use \fB\-marm\fR. +.IP "\fB\-M\fR \fIoptions\fR" 4 +.IX Item "-M options" +.PD 0 +.IP "\fB\-\-disassembler\-options=\fR\fIoptions\fR" 4 +.IX Item "--disassembler-options=options" +.PD +Pass target specific information to the disassembler. Only supported on +some targets. If it is necessary to specify more than one +disassembler option then multiple \fB\-M\fR options can be used or +can be placed together into a comma separated list. +.Sp +If the target is an \s-1ARM\s0 architecture then this switch can be used to +select which register name set is used during disassembler. Specifying +\&\fB\-M reg-names-std\fR (the default) will select the register names as +used in \s-1ARM\s0's instruction set documentation, but with register 13 called +\&'sp', register 14 called 'lr' and register 15 called 'pc'. Specifying +\&\fB\-M reg-names-apcs\fR will select the name set used by the \s-1ARM\s0 +Procedure Call Standard, whilst specifying \fB\-M reg-names-raw\fR will +just use \fBr\fR followed by the register number. +.Sp +There are also two variants on the \s-1APCS\s0 register naming scheme enabled +by \fB\-M reg-names-atpcs\fR and \fB\-M reg-names-special-atpcs\fR which +use the ARM/Thumb Procedure Call Standard naming conventions. (Either +with the normal register names or the special register names). +.Sp +This option can also be used for \s-1ARM\s0 architectures to force the +disassembler to interpret all instructions as Thumb instructions by +using the switch \fB\-\-disassembler\-options=force\-thumb\fR. This can be +useful when attempting to disassemble thumb code produced by other +compilers. +.Sp +For the x86, some of the options duplicate functions of the \fB\-m\fR +switch, but allow finer grained control. Multiple selections from the +following may be specified as a comma separated string. +\&\fBx86\-64\fR, \fBi386\fR and \fBi8086\fR select disassembly for +the given architecture. \fBintel\fR and \fBatt\fR select between +intel syntax mode and \s-1AT&T\s0 syntax mode. +\&\fBintel-mnemonic\fR and \fBatt-mnemonic\fR select between +intel mnemonic mode and \s-1AT&T\s0 mnemonic mode. \fBintel-mnemonic\fR +implies \fBintel\fR and \fBatt-mnemonic\fR implies \fBatt\fR. +\&\fBaddr64\fR, \fBaddr32\fR, +\&\fBaddr16\fR, \fBdata32\fR and \fBdata16\fR specify the default +address size and operand size. These four options will be overridden if +\&\fBx86\-64\fR, \fBi386\fR or \fBi8086\fR appear later in the +option string. Lastly, \fBsuffix\fR, when in \s-1AT&T\s0 mode, +instructs the disassembler to print a mnemonic suffix even when the +suffix could be inferred by the operands. +.Sp +For PowerPC, \fBbooke\fR controls the disassembly of BookE +instructions. \fB32\fR and \fB64\fR select PowerPC and +PowerPC64 disassembly, respectively. \fBe300\fR selects +disassembly for the e300 family. \fB440\fR selects disassembly for +the PowerPC 440. \fBppcps\fR selects disassembly for the paired +single instructions of the \s-1PPC750CL\s0. +.Sp +For \s-1MIPS\s0, this option controls the printing of instruction mnemonic +names and register names in disassembled instructions. Multiple +selections from the following may be specified as a comma separated +string, and invalid options are ignored: +.RS 4 +.ie n .IP """no\-aliases""" 4 +.el .IP "\f(CWno\-aliases\fR" 4 +.IX Item "no-aliases" +Print the 'raw' instruction mnemonic instead of some pseudo +instruction mnemonic. I.e., print 'daddu' or 'or' instead of 'move', +\&'sll' instead of 'nop', etc. +.ie n .IP """gpr\-names=\f(CIABI\f(CW""" 4 +.el .IP "\f(CWgpr\-names=\f(CIABI\f(CW\fR" 4 +.IX Item "gpr-names=ABI" +Print \s-1GPR\s0 (general-purpose register) names as appropriate +for the specified \s-1ABI\s0. By default, \s-1GPR\s0 names are selected according to +the \s-1ABI\s0 of the binary being disassembled. +.ie n .IP """fpr\-names=\f(CIABI\f(CW""" 4 +.el .IP "\f(CWfpr\-names=\f(CIABI\f(CW\fR" 4 +.IX Item "fpr-names=ABI" +Print \s-1FPR\s0 (floating-point register) names as +appropriate for the specified \s-1ABI\s0. By default, \s-1FPR\s0 numbers are printed +rather than names. +.ie n .IP """cp0\-names=\f(CIARCH\f(CW""" 4 +.el .IP "\f(CWcp0\-names=\f(CIARCH\f(CW\fR" 4 +.IX Item "cp0-names=ARCH" +Print \s-1CP0\s0 (system control coprocessor; coprocessor 0) register names +as appropriate for the \s-1CPU\s0 or architecture specified by +\&\fI\s-1ARCH\s0\fR. By default, \s-1CP0\s0 register names are selected according to +the architecture and \s-1CPU\s0 of the binary being disassembled. +.ie n .IP """hwr\-names=\f(CIARCH\f(CW""" 4 +.el .IP "\f(CWhwr\-names=\f(CIARCH\f(CW\fR" 4 +.IX Item "hwr-names=ARCH" +Print \s-1HWR\s0 (hardware register, used by the \f(CW\*(C`rdhwr\*(C'\fR instruction) names +as appropriate for the \s-1CPU\s0 or architecture specified by +\&\fI\s-1ARCH\s0\fR. By default, \s-1HWR\s0 names are selected according to +the architecture and \s-1CPU\s0 of the binary being disassembled. +.ie n .IP """reg\-names=\f(CIABI\f(CW""" 4 +.el .IP "\f(CWreg\-names=\f(CIABI\f(CW\fR" 4 +.IX Item "reg-names=ABI" +Print \s-1GPR\s0 and \s-1FPR\s0 names as appropriate for the selected \s-1ABI\s0. +.ie n .IP """reg\-names=\f(CIARCH\f(CW""" 4 +.el .IP "\f(CWreg\-names=\f(CIARCH\f(CW\fR" 4 +.IX Item "reg-names=ARCH" +Print CPU-specific register names (\s-1CP0\s0 register and \s-1HWR\s0 names) +as appropriate for the selected \s-1CPU\s0 or architecture. +.RE +.RS 4 +.Sp +For any of the options listed above, \fI\s-1ABI\s0\fR or +\&\fI\s-1ARCH\s0\fR may be specified as \fBnumeric\fR to have numbers printed +rather than names, for the selected types of registers. +You can list the available values of \fI\s-1ABI\s0\fR and \fI\s-1ARCH\s0\fR using +the \fB\-\-help\fR option. +.Sp +For \s-1VAX\s0, you can specify function entry addresses with \fB\-M +entry:0xf00ba\fR. You can use this multiple times to properly +disassemble \s-1VAX\s0 binary files that don't contain symbol tables (like +\&\s-1ROM\s0 dumps). In these cases, the function entry mask would otherwise +be decoded as \s-1VAX\s0 instructions, which would probably lead the rest +of the function being wrongly disassembled. +.RE +.IP "\fB\-p\fR" 4 +.IX Item "-p" +.PD 0 +.IP "\fB\-\-private\-headers\fR" 4 +.IX Item "--private-headers" +.PD +Print information that is specific to the object file format. The exact +information printed depends upon the object file format. For some +object file formats, no additional information is printed. +.IP "\fB\-r\fR" 4 +.IX Item "-r" +.PD 0 +.IP "\fB\-\-reloc\fR" 4 +.IX Item "--reloc" +.PD +Print the relocation entries of the file. If used with \fB\-d\fR or +\&\fB\-D\fR, the relocations are printed interspersed with the +disassembly. +.IP "\fB\-R\fR" 4 +.IX Item "-R" +.PD 0 +.IP "\fB\-\-dynamic\-reloc\fR" 4 +.IX Item "--dynamic-reloc" +.PD +Print the dynamic relocation entries of the file. This is only +meaningful for dynamic objects, such as certain types of shared +libraries. As for \fB\-r\fR, if used with \fB\-d\fR or +\&\fB\-D\fR, the relocations are printed interspersed with the +disassembly. +.IP "\fB\-s\fR" 4 +.IX Item "-s" +.PD 0 +.IP "\fB\-\-full\-contents\fR" 4 +.IX Item "--full-contents" +.PD +Display the full contents of any sections requested. By default all +non-empty sections are displayed. +.IP "\fB\-S\fR" 4 +.IX Item "-S" +.PD 0 +.IP "\fB\-\-source\fR" 4 +.IX Item "--source" +.PD +Display source code intermixed with disassembly, if possible. Implies +\&\fB\-d\fR. +.IP "\fB\-\-prefix=\fR\fIprefix\fR" 4 +.IX Item "--prefix=prefix" +Specify \fIprefix\fR to add to the absolute paths when used with +\&\fB\-S\fR. +.IP "\fB\-\-prefix\-strip=\fR\fIlevel\fR" 4 +.IX Item "--prefix-strip=level" +Indicate how many initial directory names to strip off the hardwired +absolute paths. It has no effect without \fB\-\-prefix=\fR\fIprefix\fR. +.IP "\fB\-\-show\-raw\-insn\fR" 4 +.IX Item "--show-raw-insn" +When disassembling instructions, print the instruction in hex as well as +in symbolic form. This is the default except when +\&\fB\-\-prefix\-addresses\fR is used. +.IP "\fB\-\-no\-show\-raw\-insn\fR" 4 +.IX Item "--no-show-raw-insn" +When disassembling instructions, do not print the instruction bytes. +This is the default when \fB\-\-prefix\-addresses\fR is used. +.IP "\fB\-\-insn\-width=\fR\fIwidth\fR" 4 +.IX Item "--insn-width=width" +Display \fIwidth\fR bytes on a single line when disassembling +instructions. +.IP "\fB\-W[lLiaprmfFsoRt]\fR" 4 +.IX Item "-W[lLiaprmfFsoRt]" +.PD 0 +.IP "\fB\-\-dwarf[=rawline,=decodedline,=info,=abbrev,=pubnames,=aranges,=macro,=frames,=frames\-interp,=str,=loc,=Ranges,=pubtypes,=trace_info,=trace_abbrev,=trace_aranges]\fR" 4 +.IX Item "--dwarf[=rawline,=decodedline,=info,=abbrev,=pubnames,=aranges,=macro,=frames,=frames-interp,=str,=loc,=Ranges,=pubtypes,=trace_info,=trace_abbrev,=trace_aranges]" +.PD +Displays the contents of the debug sections in the file, if any are +present. If one of the optional letters or words follows the switch +then only data found in those specific sections will be dumped. +.Sp +Note that there is no single letter option to display the content of +trace sections. +.IP "\fB\-G\fR" 4 +.IX Item "-G" +.PD 0 +.IP "\fB\-\-stabs\fR" 4 +.IX Item "--stabs" +.PD +Display the full contents of any sections requested. Display the +contents of the .stab and .stab.index and .stab.excl sections from an +\&\s-1ELF\s0 file. This is only useful on systems (such as Solaris 2.0) in which +\&\f(CW\*(C`.stab\*(C'\fR debugging symbol-table entries are carried in an \s-1ELF\s0 +section. In most other file formats, debugging symbol-table entries are +interleaved with linkage symbols, and are visible in the \fB\-\-syms\fR +output. +.IP "\fB\-\-start\-address=\fR\fIaddress\fR" 4 +.IX Item "--start-address=address" +Start displaying data at the specified address. This affects the output +of the \fB\-d\fR, \fB\-r\fR and \fB\-s\fR options. +.IP "\fB\-\-stop\-address=\fR\fIaddress\fR" 4 +.IX Item "--stop-address=address" +Stop displaying data at the specified address. This affects the output +of the \fB\-d\fR, \fB\-r\fR and \fB\-s\fR options. +.IP "\fB\-t\fR" 4 +.IX Item "-t" +.PD 0 +.IP "\fB\-\-syms\fR" 4 +.IX Item "--syms" +.PD +Print the symbol table entries of the file. +This is similar to the information provided by the \fBnm\fR program, +although the display format is different. The format of the output +depends upon the format of the file being dumped, but there are two main +types. One looks like this: +.Sp +.Vb 2 +\& [ 4](sec 3)(fl 0x00)(ty 0)(scl 3) (nx 1) 0x00000000 .bss +\& [ 6](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000000 fred +.Ve +.Sp +where the number inside the square brackets is the number of the entry +in the symbol table, the \fIsec\fR number is the section number, the +\&\fIfl\fR value are the symbol's flag bits, the \fIty\fR number is the +symbol's type, the \fIscl\fR number is the symbol's storage class and +the \fInx\fR value is the number of auxilary entries associated with +the symbol. The last two fields are the symbol's value and its name. +.Sp +The other common output format, usually seen with \s-1ELF\s0 based files, +looks like this: +.Sp +.Vb 2 +\& 00000000 l d .bss 00000000 .bss +\& 00000000 g .text 00000000 fred +.Ve +.Sp +Here the first number is the symbol's value (sometimes refered to as +its address). The next field is actually a set of characters and +spaces indicating the flag bits that are set on the symbol. These +characters are described below. Next is the section with which the +symbol is associated or \fI*ABS*\fR if the section is absolute (ie +not connected with any section), or \fI*UND*\fR if the section is +referenced in the file being dumped, but not defined there. +.Sp +After the section name comes another field, a number, which for common +symbols is the alignment and for other symbol is the size. Finally +the symbol's name is displayed. +.Sp +The flag characters are divided into 7 groups as follows: +.RS 4 +.ie n .IP """l""" 4 +.el .IP "\f(CWl\fR" 4 +.IX Item "l" +.PD 0 +.ie n .IP """g""" 4 +.el .IP "\f(CWg\fR" 4 +.IX Item "g" +.ie n .IP """u""" 4 +.el .IP "\f(CWu\fR" 4 +.IX Item "u" +.ie n .IP """!""" 4 +.el .IP "\f(CW!\fR" 4 +.IX Item "!" +.PD +The symbol is a local (l), global (g), unique global (u), neither +global nor local (a space) or both global and local (!). A +symbol can be neither local or global for a variety of reasons, e.g., +because it is used for debugging, but it is probably an indication of +a bug if it is ever both local and global. Unique global symbols are +a \s-1GNU\s0 extension to the standard set of \s-1ELF\s0 symbol bindings. For such +a symbol the dynamic linker will make sure that in the entire process +there is just one symbol with this name and type in use. +.ie n .IP """w""" 4 +.el .IP "\f(CWw\fR" 4 +.IX Item "w" +The symbol is weak (w) or strong (a space). +.ie n .IP """C""" 4 +.el .IP "\f(CWC\fR" 4 +.IX Item "C" +The symbol denotes a constructor (C) or an ordinary symbol (a space). +.ie n .IP """W""" 4 +.el .IP "\f(CWW\fR" 4 +.IX Item "W" +The symbol is a warning (W) or a normal symbol (a space). A warning +symbol's name is a message to be displayed if the symbol following the +warning symbol is ever referenced. +.ie n .IP """I""" 4 +.el .IP "\f(CWI\fR" 4 +.IX Item "I" +.PD 0 +.ie n .IP """i""" 4 +.el .IP "\f(CWi\fR" 4 +.IX Item "i" +.PD +The symbol is an indirect reference to another symbol (I), a function +to be evaluated during reloc processing (i) or a normal symbol (a +space). +.ie n .IP """d""" 4 +.el .IP "\f(CWd\fR" 4 +.IX Item "d" +.PD 0 +.ie n .IP """D""" 4 +.el .IP "\f(CWD\fR" 4 +.IX Item "D" +.PD +The symbol is a debugging symbol (d) or a dynamic symbol (D) or a +normal symbol (a space). +.ie n .IP """F""" 4 +.el .IP "\f(CWF\fR" 4 +.IX Item "F" +.PD 0 +.ie n .IP """f""" 4 +.el .IP "\f(CWf\fR" 4 +.IX Item "f" +.ie n .IP """O""" 4 +.el .IP "\f(CWO\fR" 4 +.IX Item "O" +.PD +The symbol is the name of a function (F) or a file (f) or an object +(O) or just a normal symbol (a space). +.RE +.RS 4 +.RE +.IP "\fB\-T\fR" 4 +.IX Item "-T" +.PD 0 +.IP "\fB\-\-dynamic\-syms\fR" 4 +.IX Item "--dynamic-syms" +.PD +Print the dynamic symbol table entries of the file. This is only +meaningful for dynamic objects, such as certain types of shared +libraries. This is similar to the information provided by the \fBnm\fR +program when given the \fB\-D\fR (\fB\-\-dynamic\fR) option. +.IP "\fB\-\-special\-syms\fR" 4 +.IX Item "--special-syms" +When displaying symbols include those which the target considers to be +special in some way and which would not normally be of interest to the +user. +.IP "\fB\-V\fR" 4 +.IX Item "-V" +.PD 0 +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +.PD +Print the version number of \fBobjdump\fR and exit. +.IP "\fB\-x\fR" 4 +.IX Item "-x" +.PD 0 +.IP "\fB\-\-all\-headers\fR" 4 +.IX Item "--all-headers" +.PD +Display all available header information, including the symbol table and +relocation entries. Using \fB\-x\fR is equivalent to specifying all of +\&\fB\-a \-f \-h \-p \-r \-t\fR. +.IP "\fB\-w\fR" 4 +.IX Item "-w" +.PD 0 +.IP "\fB\-\-wide\fR" 4 +.IX Item "--wide" +.PD +Format some lines for output devices that have more than 80 columns. +Also do not truncate symbol names when they are displayed. +.IP "\fB\-z\fR" 4 +.IX Item "-z" +.PD 0 +.IP "\fB\-\-disassemble\-zeroes\fR" 4 +.IX Item "--disassemble-zeroes" +.PD +Normally the disassembly output will skip blocks of zeroes. This +option directs the disassembler to disassemble those blocks, just like +any other data. +.IP "\fB@\fR\fIfile\fR" 4 +.IX Item "@file" +Read command-line options from \fIfile\fR. The options read are +inserted in place of the original @\fIfile\fR option. If \fIfile\fR +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +.Sp +Options in \fIfile\fR are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The \fIfile\fR may itself contain additional +@\fIfile\fR options; any such options will be processed recursively. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fInm\fR\|(1), \fIreadelf\fR\|(1), and the Info entries for \fIbinutils\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 +or any later version published by the Free Software Foundation; +with no Invariant Sections, with no Front-Cover Texts, and with no +Back-Cover Texts. A copy of the license is included in the +section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". diff --git a/share/man/man1/arm-eabi-ranlib.1 b/share/man/man1/arm-eabi-ranlib.1 new file mode 100644 index 0000000..781d9ef --- /dev/null +++ b/share/man/man1/arm-eabi-ranlib.1 @@ -0,0 +1,192 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "RANLIB 1" +.TH RANLIB 1 " " "binutils-2.21" "GNU Development Tools" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +ranlib \- generate index to archive. +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +ranlib [\fB\-vVt\fR] \fIarchive\fR +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +\&\fBranlib\fR generates an index to the contents of an archive and +stores it in the archive. The index lists each symbol defined by a +member of an archive that is a relocatable object file. +.PP +You may use \fBnm \-s\fR or \fBnm \-\-print\-armap\fR to list this index. +.PP +An archive with such an index speeds up linking to the library and +allows routines in the library to call each other without regard to +their placement in the archive. +.PP +The \s-1GNU\s0 \fBranlib\fR program is another form of \s-1GNU\s0 \fBar\fR; running +\&\fBranlib\fR is completely equivalent to executing \fBar \-s\fR. +.SH "OPTIONS" +.IX Header "OPTIONS" +.IP "\fB\-v\fR" 4 +.IX Item "-v" +.PD 0 +.IP "\fB\-V\fR" 4 +.IX Item "-V" +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +.PD +Show the version number of \fBranlib\fR. +.IP "\fB\-t\fR" 4 +.IX Item "-t" +Update the timestamp of the symbol map of an archive. +.IP "\fB@\fR\fIfile\fR" 4 +.IX Item "@file" +Read command-line options from \fIfile\fR. The options read are +inserted in place of the original @\fIfile\fR option. If \fIfile\fR +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +.Sp +Options in \fIfile\fR are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The \fIfile\fR may itself contain additional +@\fIfile\fR options; any such options will be processed recursively. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fIar\fR\|(1), \fInm\fR\|(1), and the Info entries for \fIbinutils\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 +or any later version published by the Free Software Foundation; +with no Invariant Sections, with no Front-Cover Texts, and with no +Back-Cover Texts. A copy of the license is included in the +section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". diff --git a/share/man/man1/arm-eabi-readelf.1 b/share/man/man1/arm-eabi-readelf.1 new file mode 100644 index 0000000..5fe93d7 --- /dev/null +++ b/share/man/man1/arm-eabi-readelf.1 @@ -0,0 +1,426 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "READELF 1" +.TH READELF 1 " " "binutils-2.21" "GNU Development Tools" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +readelf \- Displays information about ELF files. +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +readelf [\fB\-a\fR|\fB\-\-all\fR] + [\fB\-h\fR|\fB\-\-file\-header\fR] + [\fB\-l\fR|\fB\-\-program\-headers\fR|\fB\-\-segments\fR] + [\fB\-S\fR|\fB\-\-section\-headers\fR|\fB\-\-sections\fR] + [\fB\-g\fR|\fB\-\-section\-groups\fR] + [\fB\-t\fR|\fB\-\-section\-details\fR] + [\fB\-e\fR|\fB\-\-headers\fR] + [\fB\-s\fR|\fB\-\-syms\fR|\fB\-\-symbols\fR] + [\fB\-\-dyn\-syms\fR] + [\fB\-n\fR|\fB\-\-notes\fR] + [\fB\-r\fR|\fB\-\-relocs\fR] + [\fB\-u\fR|\fB\-\-unwind\fR] + [\fB\-d\fR|\fB\-\-dynamic\fR] + [\fB\-V\fR|\fB\-\-version\-info\fR] + [\fB\-A\fR|\fB\-\-arch\-specific\fR] + [\fB\-D\fR|\fB\-\-use\-dynamic\fR] + [\fB\-x\fR <number or name>|\fB\-\-hex\-dump=\fR<number or name>] + [\fB\-p\fR <number or name>|\fB\-\-string\-dump=\fR<number or name>] + [\fB\-R\fR <number or name>|\fB\-\-relocated\-dump=\fR<number or name>] + [\fB\-c\fR|\fB\-\-archive\-index\fR] + [\fB\-w[lLiaprmfFsoRt]\fR| + \fB\-\-debug\-dump\fR[=rawline,=decodedline,=info,=abbrev,=pubnames,=aranges,=macro,=frames,=frames\-interp,=str,=loc,=Ranges,=pubtypes,=trace_info,=trace_abbrev,=trace_aranges]] + [\fB\-I\fR|\fB\-\-histogram\fR] + [\fB\-v\fR|\fB\-\-version\fR] + [\fB\-W\fR|\fB\-\-wide\fR] + [\fB\-H\fR|\fB\-\-help\fR] + \fIelffile\fR... +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +\&\fBreadelf\fR displays information about one or more \s-1ELF\s0 format object +files. The options control what particular information to display. +.PP +\&\fIelffile\fR... are the object files to be examined. 32\-bit and +64\-bit \s-1ELF\s0 files are supported, as are archives containing \s-1ELF\s0 files. +.PP +This program performs a similar function to \fBobjdump\fR but it +goes into more detail and it exists independently of the \s-1BFD\s0 +library, so if there is a bug in \s-1BFD\s0 then readelf will not be +affected. +.SH "OPTIONS" +.IX Header "OPTIONS" +The long and short forms of options, shown here as alternatives, are +equivalent. At least one option besides \fB\-v\fR or \fB\-H\fR must be +given. +.IP "\fB\-a\fR" 4 +.IX Item "-a" +.PD 0 +.IP "\fB\-\-all\fR" 4 +.IX Item "--all" +.PD +Equivalent to specifying \fB\-\-file\-header\fR, +\&\fB\-\-program\-headers\fR, \fB\-\-sections\fR, \fB\-\-symbols\fR, +\&\fB\-\-relocs\fR, \fB\-\-dynamic\fR, \fB\-\-notes\fR and +\&\fB\-\-version\-info\fR. +.IP "\fB\-h\fR" 4 +.IX Item "-h" +.PD 0 +.IP "\fB\-\-file\-header\fR" 4 +.IX Item "--file-header" +.PD +Displays the information contained in the \s-1ELF\s0 header at the start of the +file. +.IP "\fB\-l\fR" 4 +.IX Item "-l" +.PD 0 +.IP "\fB\-\-program\-headers\fR" 4 +.IX Item "--program-headers" +.IP "\fB\-\-segments\fR" 4 +.IX Item "--segments" +.PD +Displays the information contained in the file's segment headers, if it +has any. +.IP "\fB\-S\fR" 4 +.IX Item "-S" +.PD 0 +.IP "\fB\-\-sections\fR" 4 +.IX Item "--sections" +.IP "\fB\-\-section\-headers\fR" 4 +.IX Item "--section-headers" +.PD +Displays the information contained in the file's section headers, if it +has any. +.IP "\fB\-g\fR" 4 +.IX Item "-g" +.PD 0 +.IP "\fB\-\-section\-groups\fR" 4 +.IX Item "--section-groups" +.PD +Displays the information contained in the file's section groups, if it +has any. +.IP "\fB\-t\fR" 4 +.IX Item "-t" +.PD 0 +.IP "\fB\-\-section\-details\fR" 4 +.IX Item "--section-details" +.PD +Displays the detailed section information. Implies \fB\-S\fR. +.IP "\fB\-s\fR" 4 +.IX Item "-s" +.PD 0 +.IP "\fB\-\-symbols\fR" 4 +.IX Item "--symbols" +.IP "\fB\-\-syms\fR" 4 +.IX Item "--syms" +.PD +Displays the entries in symbol table section of the file, if it has one. +.IP "\fB\-\-dyn\-syms\fR" 4 +.IX Item "--dyn-syms" +Displays the entries in dynamic symbol table section of the file, if it +has one. +.IP "\fB\-e\fR" 4 +.IX Item "-e" +.PD 0 +.IP "\fB\-\-headers\fR" 4 +.IX Item "--headers" +.PD +Display all the headers in the file. Equivalent to \fB\-h \-l \-S\fR. +.IP "\fB\-n\fR" 4 +.IX Item "-n" +.PD 0 +.IP "\fB\-\-notes\fR" 4 +.IX Item "--notes" +.PD +Displays the contents of the \s-1NOTE\s0 segments and/or sections, if any. +.IP "\fB\-r\fR" 4 +.IX Item "-r" +.PD 0 +.IP "\fB\-\-relocs\fR" 4 +.IX Item "--relocs" +.PD +Displays the contents of the file's relocation section, if it has one. +.IP "\fB\-u\fR" 4 +.IX Item "-u" +.PD 0 +.IP "\fB\-\-unwind\fR" 4 +.IX Item "--unwind" +.PD +Displays the contents of the file's unwind section, if it has one. Only +the unwind sections for \s-1IA64\s0 \s-1ELF\s0 files, as well as \s-1ARM\s0 unwind tables +(\f(CW\*(C`.ARM.exidx\*(C'\fR / \f(CW\*(C`.ARM.extab\*(C'\fR) are currently supported. +.IP "\fB\-d\fR" 4 +.IX Item "-d" +.PD 0 +.IP "\fB\-\-dynamic\fR" 4 +.IX Item "--dynamic" +.PD +Displays the contents of the file's dynamic section, if it has one. +.IP "\fB\-V\fR" 4 +.IX Item "-V" +.PD 0 +.IP "\fB\-\-version\-info\fR" 4 +.IX Item "--version-info" +.PD +Displays the contents of the version sections in the file, it they +exist. +.IP "\fB\-A\fR" 4 +.IX Item "-A" +.PD 0 +.IP "\fB\-\-arch\-specific\fR" 4 +.IX Item "--arch-specific" +.PD +Displays architecture-specific information in the file, if there +is any. +.IP "\fB\-D\fR" 4 +.IX Item "-D" +.PD 0 +.IP "\fB\-\-use\-dynamic\fR" 4 +.IX Item "--use-dynamic" +.PD +When displaying symbols, this option makes \fBreadelf\fR use the +symbol hash tables in the file's dynamic section, rather than the +symbol table sections. +.IP "\fB\-x <number or name>\fR" 4 +.IX Item "-x <number or name>" +.PD 0 +.IP "\fB\-\-hex\-dump=<number or name>\fR" 4 +.IX Item "--hex-dump=<number or name>" +.PD +Displays the contents of the indicated section as a hexadecimal bytes. +A number identifies a particular section by index in the section table; +any other string identifies all sections with that name in the object file. +.IP "\fB\-R <number or name>\fR" 4 +.IX Item "-R <number or name>" +.PD 0 +.IP "\fB\-\-relocated\-dump=<number or name>\fR" 4 +.IX Item "--relocated-dump=<number or name>" +.PD +Displays the contents of the indicated section as a hexadecimal +bytes. A number identifies a particular section by index in the +section table; any other string identifies all sections with that name +in the object file. The contents of the section will be relocated +before they are displayed. +.IP "\fB\-p <number or name>\fR" 4 +.IX Item "-p <number or name>" +.PD 0 +.IP "\fB\-\-string\-dump=<number or name>\fR" 4 +.IX Item "--string-dump=<number or name>" +.PD +Displays the contents of the indicated section as printable strings. +A number identifies a particular section by index in the section table; +any other string identifies all sections with that name in the object file. +.IP "\fB\-c\fR" 4 +.IX Item "-c" +.PD 0 +.IP "\fB\-\-archive\-index\fR" 4 +.IX Item "--archive-index" +.PD +Displays the file symbol index infomation contained in the header part +of binary archives. Performs the same function as the \fBt\fR +command to \fBar\fR, but without using the \s-1BFD\s0 library. +.IP "\fB\-w[lLiaprmfFsoRt]\fR" 4 +.IX Item "-w[lLiaprmfFsoRt]" +.PD 0 +.IP "\fB\-\-debug\-dump[=rawline,=decodedline,=info,=abbrev,=pubnames,=aranges,=macro,=frames,=frames\-interp,=str,=loc,=Ranges,=pubtypes,=trace_info,=trace_abbrev,=trace_aranges]\fR" 4 +.IX Item "--debug-dump[=rawline,=decodedline,=info,=abbrev,=pubnames,=aranges,=macro,=frames,=frames-interp,=str,=loc,=Ranges,=pubtypes,=trace_info,=trace_abbrev,=trace_aranges]" +.PD +Displays the contents of the debug sections in the file, if any are +present. If one of the optional letters or words follows the switch +then only data found in those specific sections will be dumped. +.Sp +Note that there is no single letter option to display the content of +trace sections. +.Sp +Note: the \fB=decodedline\fR option will display the interpreted +contents of a .debug_line section whereas the \fB=rawline\fR option +dumps the contents in a raw format. +.Sp +Note: the \fB=frames\-interp\fR option will display the interpreted +contents of a .debug_frame section whereas the \fB=frames\fR option +dumps the contents in a raw format. +.IP "\fB\-I\fR" 4 +.IX Item "-I" +.PD 0 +.IP "\fB\-\-histogram\fR" 4 +.IX Item "--histogram" +.PD +Display a histogram of bucket list lengths when displaying the contents +of the symbol tables. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +.PD 0 +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +.PD +Display the version number of readelf. +.IP "\fB\-W\fR" 4 +.IX Item "-W" +.PD 0 +.IP "\fB\-\-wide\fR" 4 +.IX Item "--wide" +.PD +Don't break output lines to fit into 80 columns. By default +\&\fBreadelf\fR breaks section header and segment listing lines for +64\-bit \s-1ELF\s0 files, so that they fit into 80 columns. This option causes +\&\fBreadelf\fR to print each section header resp. each segment one a +single line, which is far more readable on terminals wider than 80 columns. +.IP "\fB\-H\fR" 4 +.IX Item "-H" +.PD 0 +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +.PD +Display the command line options understood by \fBreadelf\fR. +.IP "\fB@\fR\fIfile\fR" 4 +.IX Item "@file" +Read command-line options from \fIfile\fR. The options read are +inserted in place of the original @\fIfile\fR option. If \fIfile\fR +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +.Sp +Options in \fIfile\fR are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The \fIfile\fR may itself contain additional +@\fIfile\fR options; any such options will be processed recursively. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fIobjdump\fR\|(1), and the Info entries for \fIbinutils\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 +or any later version published by the Free Software Foundation; +with no Invariant Sections, with no Front-Cover Texts, and with no +Back-Cover Texts. A copy of the license is included in the +section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". diff --git a/share/man/man1/arm-eabi-run.1 b/share/man/man1/arm-eabi-run.1 new file mode 100644 index 0000000..8bc2706 --- /dev/null +++ b/share/man/man1/arm-eabi-run.1 @@ -0,0 +1,475 @@ +.\" Copyright (c) 1993, 2004, 2010, 2011 Free Software Foundation +.\" See section COPYING for conditions for redistribution +.TH run 1 "13oct1993" "GNU Tools" "GNU Tools" +.de BP +.sp +.ti -.2i +\(** +.. + +.SH NAME +run\(em\&Simulator front-end + +.SH SYNOPSIS +.hy 0 +.na +.TP +.B run +.RB "[\|" \-v "\|]" +." .RB "[\|" \-t "\|]" +.RB "[\|" \-p +.IR freq "\|]" +.RB "[\|" \-m +.IR memory "\|]" +.RB "[\|" \--sysroot +.IR filepath "\|]" +.I program +.ad b +.hy 1 +.SH DESCRIPTION + +Use `\|\c +.BI run " program"\c +\&\|' to execute a binary by interpreting machine instructions on your +host computer. + +.B run +is the same emulator used by GDB's `\|\c +.B target sim\c +\&\|' command. You can run it directly by executing +.B run +if you just want to see your program execute, and do not need any +debugger functionality. You can also use +.B run +to generate profiling information for analysis with +.BR gprof . + +.SH OPTIONS + +.TP +.B \-v +Verbose output. Display the name of the program to run before +execution; after execution, display the number of instructions +executed, the number of machine cycles emulated, the number of +pipeline stalls, the real time taken, the emulated execution time +taken, and a summary of how much profiling information was generated. +." +." .TP +." .B \-t +." `trace', calls a sim_trace routine that does nothing. + +.TP +.BI \-p " freq" +Generate profile information (for use with +.B gprof\c +\&). +.I freq +is the profiling frequency. Write the profiling information to a file called +.BR gmon.out . + +.TP +.BI \-m " memory" +Set the memory size for the emulated machine to two to the power +.IR memory . +The default value is 19, emulating a board with 524288 bytes of memory. + +.TP +.BI \--sysroot " filepath" +Prepend +.IR filepath +to all simulator system calls that pass absolute file paths. +Change working directory to +.IR filepath +at program start. Not all simulators support this option; those +that don't, will ignore it. + +.PP + +.SH "SEE ALSO" +.RB "`\|" gprof "\|'" +entry in +.B info\c +\&; +.RB "`\|" gdb "\|'" +entry in +.B info\c +\&; +.I +Using GDB: A Guide to the GNU Source-Level Debugger\c +, Richard M. Stallman and Roland H. Pesch. + +.SH COPYING +Copyright (c) 1993, 2000 Free Software Foundation, Inc. +.PP +This document is distributed under the terms of the GNU Free +Documentation License, version 1.1. That license is described in the +sources for this manual page, but it is not displayed here in order to +make this manual more consise. Copies of this license can also be +obtained from: http://www.gnu.org/copyleft/. + +\" GNU Free Documentation License +\" Version 1.1, March 2000 + +\" Copyright (C) 2000 Free Software Foundation, Inc. +\" 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +\" Everyone is permitted to copy and distribute verbatim +\" copies of this license document, but changing it is +\" not allowed. +\" .PP +\" 0. PREAMBLE +\" .PP +\" The purpose of this License is to make a manual, textbook, or other +\" written document "free" in the sense of freedom: to assure everyone +\" the effective freedom to copy and redistribute it, with or without +\" modifying it, either commercially or noncommercially. Secondarily, +\" this License preserves for the author and publisher a way to get +\" credit for their work, while not being considered responsible for +\" modifications made by others. +\" .PP +\" This License is a kind of "copyleft", which means that derivative +\" works of the document must themselves be free in the same sense. It +\" complements the GNU General Public License, which is a copyleft +\" license designed for free software. +\" .PP +\" We have designed this License in order to use it for manuals for free +\" software, because free software needs free documentation: a free +\" program should come with manuals providing the same freedoms that the +\" software does. But this License is not limited to software manuals; +\" it can be used for any textual work, regardless of subject matter or +\" whether it is published as a printed book. We recommend this License +\" principally for works whose purpose is instruction or reference. +\" .PP +\" 1. APPLICABILITY AND DEFINITIONS +\" .PP +\" This License applies to any manual or other work that contains a +\" notice placed by the copyright holder saying it can be distributed +\" under the terms of this License. The "Document", below, refers to any +\" such manual or work. Any member of the public is a licensee, and is +\" addressed as "you". +\" .PP +\" A "Modified Version" of the Document means any work containing the +\" Document or a portion of it, either copied verbatim, or with +\" modifications and/or translated into another language. +\" .PP +\" A "Secondary Section" is a named appendix or a front-matter section of +\" the Document that deals exclusively with the relationship of the +\" publishers or authors of the Document to the Document's overall subject +\" (or to related matters) and contains nothing that could fall directly +\" within that overall subject. (For example, if the Document is in part a +\" textbook of mathematics, a Secondary Section may not explain any +\" mathematics.) The relationship could be a matter of historical +\" connection with the subject or with related matters, or of legal, +\" commercial, philosophical, ethical or political position regarding +\" them. +\" .PP +\" The "Invariant Sections" are certain Secondary Sections whose titles +\" are designated, as being those of Invariant Sections, in the notice +\" that says that the Document is released under this License. +\" .PP +\" The "Cover Texts" are certain short passages of text that are listed, +\" as Front-Cover Texts or Back-Cover Texts, in the notice that says that +\" the Document is released under this License. +\" .PP +\" A "Transparent" copy of the Document means a machine-readable copy, +\" represented in a format whose specification is available to the +\" general public, whose contents can be viewed and edited directly and +\" straightforwardly with generic text editors or (for images composed of +\" pixels) generic paint programs or (for drawings) some widely available +\" drawing editor, and that is suitable for input to text formatters or +\" for automatic translation to a variety of formats suitable for input +\" to text formatters. A copy made in an otherwise Transparent file +\" format whose markup has been designed to thwart or discourage +\" subsequent modification by readers is not Transparent. A copy that is +\" not "Transparent" is called "Opaque". +\" .PP +\" Examples of suitable formats for Transparent copies include plain +\" ASCII without markup, Texinfo input format, LaTeX input format, SGML +\" or XML using a publicly available DTD, and standard-conforming simple +\" HTML designed for human modification. Opaque formats include +\" PostScript, PDF, proprietary formats that can be read and edited only +\" by proprietary word processors, SGML or XML for which the DTD and/or +\" processing tools are not generally available, and the +\" machine-generated HTML produced by some word processors for output +\" purposes only. +\" .PP +\" The "Title Page" means, for a printed book, the title page itself, +\" plus such following pages as are needed to hold, legibly, the material +\" this License requires to appear in the title page. For works in +\" formats which do not have any title page as such, "Title Page" means +\" the text near the most prominent appearance of the work's title, +\" preceding the beginning of the body of the text. +\" .PP +\" 2. VERBATIM COPYING +\" .PP +\" You may copy and distribute the Document in any medium, either +\" commercially or noncommercially, provided that this License, the +\" copyright notices, and the license notice saying this License applies +\" to the Document are reproduced in all copies, and that you add no other +\" conditions whatsoever to those of this License. You may not use +\" technical measures to obstruct or control the reading or further +\" copying of the copies you make or distribute. However, you may accept +\" compensation in exchange for copies. If you distribute a large enough +\" number of copies you must also follow the conditions in section 3. +\" .PP +\" You may also lend copies, under the same conditions stated above, and +\" you may publicly display copies. +\" .PP +\" 3. COPYING IN QUANTITY +\" .PP +\" If you publish printed copies of the Document numbering more than 100, +\" and the Document's license notice requires Cover Texts, you must enclose +\" the copies in covers that carry, clearly and legibly, all these Cover +\" Texts: Front-Cover Texts on the front cover, and Back-Cover Texts on +\" the back cover. Both covers must also clearly and legibly identify +\" you as the publisher of these copies. The front cover must present +\" the full title with all words of the title equally prominent and +\" visible. You may add other material on the covers in addition. +\" Copying with changes limited to the covers, as long as they preserve +\" the title of the Document and satisfy these conditions, can be treated +\" as verbatim copying in other respects. +\" .PP +\" If the required texts for either cover are too voluminous to fit +\" legibly, you should put the first ones listed (as many as fit +\" reasonably) on the actual cover, and continue the rest onto adjacent +\" pages. +\" .PP +\" If you publish or distribute Opaque copies of the Document numbering +\" more than 100, you must either include a machine-readable Transparent +\" copy along with each Opaque copy, or state in or with each Opaque copy +\" a publicly-accessible computer-network location containing a complete +\" Transparent copy of the Document, free of added material, which the +\" general network-using public has access to download anonymously at no +\" charge using public-standard network protocols. If you use the latter +\" option, you must take reasonably prudent steps, when you begin +\" distribution of Opaque copies in quantity, to ensure that this +\" Transparent copy will remain thus accessible at the stated location +\" until at least one year after the last time you distribute an Opaque +\" copy (directly or through your agents or retailers) of that edition to +\" the public. +\" .PP +\" It is requested, but not required, that you contact the authors of the +\" Document well before redistributing any large number of copies, to give +\" them a chance to provide you with an updated version of the Document. +\" .PP +\" 4. MODIFICATIONS +\" .PP +\" You may copy and distribute a Modified Version of the Document under +\" the conditions of sections 2 and 3 above, provided that you release +\" the Modified Version under precisely this License, with the Modified +\" Version filling the role of the Document, thus licensing distribution +\" and modification of the Modified Version to whoever possesses a copy +\" of it. In addition, you must do these things in the Modified Version: +\" .PP +\" A. Use in the Title Page (and on the covers, if any) a title distinct +\" from that of the Document, and from those of previous versions +\" (which should, if there were any, be listed in the History section +\" of the Document). You may use the same title as a previous version +\" if the original publisher of that version gives permission. +\" .PP +\" B. List on the Title Page, as authors, one or more persons or entities +\" responsible for authorship of the modifications in the Modified +\" Version, together with at least five of the principal authors of the +\" Document (all of its principal authors, if it has less than five). +\" .PP +\" C. State on the Title page the name of the publisher of the +\" Modified Version, as the publisher. +\" .PP +\" D. Preserve all the copyright notices of the Document. +\" .PP +\" E. Add an appropriate copyright notice for your modifications +\" adjacent to the other copyright notices. +\" .PP +\" F. Include, immediately after the copyright notices, a license notice +\" giving the public permission to use the Modified Version under the +\" terms of this License, in the form shown in the Addendum below. +\" Preserve in that license notice the full lists of Invariant Sections +\" and required Cover Texts given in the Document's license notice. +\" .PP +\" H. Include an unaltered copy of this License. +\" .PP +\" I. Preserve the section entitled "History", and its title, and add to +\" it an item stating at least the title, year, new authors, and +\" publisher of the Modified Version as given on the Title Page. If +\" there is no section entitled "History" in the Document, create one +\" stating the title, year, authors, and publisher of the Document as +\" given on its Title Page, then add an item describing the Modified +\" Version as stated in the previous sentence. +\" .PP +\" J. Preserve the network location, if any, given in the Document for +\" public access to a Transparent copy of the Document, and likewise +\" the network locations given in the Document for previous versions +\" it was based on. These may be placed in the "History" section. +\" You may omit a network location for a work that was published at +\" least four years before the Document itself, or if the original +\" publisher of the version it refers to gives permission. +\" .PP +\" K. In any section entitled "Acknowledgements" or "Dedications", +\" preserve the section's title, and preserve in the section all the +\" substance and tone of each of the contributor acknowledgements +\" and/or dedications given therein. +\" .PP +\" L. Preserve all the Invariant Sections of the Document, +\" unaltered in their text and in their titles. Section numbers +\" or the equivalent are not considered part of the section titles. +\" .PP +\" M. Delete any section entitled "Endorsements". Such a section +\" may not be included in the Modified Version. +\" .PP +\" N. Do not retitle any existing section as "Endorsements" +\" or to conflict in title with any Invariant Section. +\" .PP +\" If the Modified Version includes new front-matter sections or +\" appendices that qualify as Secondary Sections and contain no material +\" copied from the Document, you may at your option designate some or all +\" of these sections as invariant. To do this, add their titles to the +\" list of Invariant Sections in the Modified Version's license notice. +\" These titles must be distinct from any other section titles. +\" .PP +\" You may add a section entitled "Endorsements", provided it contains +\" nothing but endorsements of your Modified Version by various +\" parties--for example, statements of peer review or that the text has +\" been approved by an organization as the authoritative definition of a +\" standard. +\" .PP +\" You may add a passage of up to five words as a Front-Cover Text, and a +\" passage of up to 25 words as a Back-Cover Text, to the end of the list +\" of Cover Texts in the Modified Version. Only one passage of +\" Front-Cover Text and one of Back-Cover Text may be added by (or +\" through arrangements made by) any one entity. If the Document already +\" includes a cover text for the same cover, previously added by you or +\" by arrangement made by the same entity you are acting on behalf of, +\" you may not add another; but you may replace the old one, on explicit +\" permission from the previous publisher that added the old one. +\" .PP +\" The author(s) and publisher(s) of the Document do not by this License +\" give permission to use their names for publicity for or to assert or +\" imply endorsement of any Modified Version. +\" .PP + +\" 5. COMBINING DOCUMENTS +\" .PP +\" You may combine the Document with other documents released under this +\" License, under the terms defined in section 4 above for modified +\" versions, provided that you include in the combination all of the +\" Invariant Sections of all of the original documents, unmodified, and +\" list them all as Invariant Sections of your combined work in its +\" license notice. +\" .PP +\" The combined work need only contain one copy of this License, and +\" multiple identical Invariant Sections may be replaced with a single +\" copy. If there are multiple Invariant Sections with the same name but +\" different contents, make the title of each such section unique by +\" adding at the end of it, in parentheses, the name of the original +\" author or publisher of that section if known, or else a unique number. +\" Make the same adjustment to the section titles in the list of +\" Invariant Sections in the license notice of the combined work. +\" .PP +\" In the combination, you must combine any sections entitled "History" +\" in the various original documents, forming one section entitled +\" "History"; likewise combine any sections entitled "Acknowledgements", +\" and any sections entitled "Dedications". You must delete all sections +\" entitled "Endorsements." +\" .PP + +\" 6. COLLECTIONS OF DOCUMENTS +\" .PP +\" You may make a collection consisting of the Document and other documents +\" released under this License, and replace the individual copies of this +\" License in the various documents with a single copy that is included in +\" the collection, provided that you follow the rules of this License for +\" verbatim copying of each of the documents in all other respects. +\" .PP +\" You may extract a single document from such a collection, and distribute +\" it individually under this License, provided you insert a copy of this +\" License into the extracted document, and follow this License in all +\" other respects regarding verbatim copying of that document. +\" .PP + +\" 7. AGGREGATION WITH INDEPENDENT WORKS +\" .PP +\" A compilation of the Document or its derivatives with other separate +\" and independent documents or works, in or on a volume of a storage or +\" distribution medium, does not as a whole count as a Modified Version +\" of the Document, provided no compilation copyright is claimed for the +\" compilation. Such a compilation is called an "aggregate", and this +\" License does not apply to the other self-contained works thus compiled +\" with the Document, on account of their being thus compiled, if they +\" are not themselves derivative works of the Document. +\" .PP +\" If the Cover Text requirement of section 3 is applicable to these +\" copies of the Document, then if the Document is less than one quarter +\" of the entire aggregate, the Document's Cover Texts may be placed on +\" covers that surround only the Document within the aggregate. +\" Otherwise they must appear on covers around the whole aggregate. +\" .PP + +\" 8. TRANSLATION +\" .PP +\" Translation is considered a kind of modification, so you may +\" distribute translations of the Document under the terms of section 4. +\" Replacing Invariant Sections with translations requires special +\" permission from their copyright holders, but you may include +\" translations of some or all Invariant Sections in addition to the +\" original versions of these Invariant Sections. You may include a +\" translation of this License provided that you also include the +\" original English version of this License. In case of a disagreement +\" between the translation and the original English version of this +\" License, the original English version will prevail. +\" .PP + +\" 9. TERMINATION +\" .PP +\" You may not copy, modify, sublicense, or distribute the Document except +\" as expressly provided for under this License. Any other attempt to +\" copy, modify, sublicense or distribute the Document is void, and will +\" automatically terminate your rights under this License. However, +\" parties who have received copies, or rights, from you under this +\" License will not have their licenses terminated so long as such +\" parties remain in full compliance. +\" .PP + +\" 10. FUTURE REVISIONS OF THIS LICENSE +\" .PP +\" The Free Software Foundation may publish new, revised versions +\" of the GNU Free Documentation License from time to time. Such new +\" versions will be similar in spirit to the present version, but may +\" differ in detail to address new problems or concerns. See +\" http://www.gnu.org/copyleft/. +\" .PP +\" Each version of the License is given a distinguishing version number. +\" If the Document specifies that a particular numbered version of this +\" License "or any later version" applies to it, you have the option of +\" following the terms and conditions either of that specified version or +\" of any later version that has been published (not as a draft) by the +\" Free Software Foundation. If the Document does not specify a version +\" number of this License, you may choose any version ever published (not +\" as a draft) by the Free Software Foundation. +\" .PP + +\" ADDENDUM: How to use this License for your documents +\" .PP +\" To use this License in a document you have written, include a copy of +\" the License in the document and put the following copyright and +\" license notices just after the title page: +\" .PP +\" Copyright (c) YEAR YOUR NAME. +\" Permission is granted to copy, distribute and/or +\" modify this document under the terms of the GNU +\" Free Documentation License, Version 1.1 or any later +\" version published by the Free Software Foundation; +\" with the Invariant Sections being LIST THEIR TITLES, +\" with the Front-Cover Texts being LIST, and with the +\" Back-Cover Texts being LIST. A copy of the license +\" is included in the section entitled "GNU Free +\" Documentation License". +\" .PP +\" If you have no Invariant Sections, write "with no Invariant Sections" +\" instead of saying which ones are invariant. If you have no +\" Front-Cover Texts, write "no Front-Cover Texts" instead of +\" "Front-Cover Texts being LIST"; likewise for Back-Cover Texts. +\" .PP +\" If your document contains nontrivial examples of program code, we +\" recommend releasing these examples in parallel under your choice of +\" free software license, such as the GNU General Public License, +\" to permit their use in free software. diff --git a/share/man/man1/arm-eabi-size.1 b/share/man/man1/arm-eabi-size.1 new file mode 100644 index 0000000..5320b58 --- /dev/null +++ b/share/man/man1/arm-eabi-size.1 @@ -0,0 +1,268 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "SIZE 1" +.TH SIZE 1 " " "binutils-2.21" "GNU Development Tools" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +size \- list section sizes and total size. +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +size [\fB\-A\fR|\fB\-B\fR|\fB\-\-format=\fR\fIcompatibility\fR] + [\fB\-\-help\fR] + [\fB\-d\fR|\fB\-o\fR|\fB\-x\fR|\fB\-\-radix=\fR\fInumber\fR] + [\fB\-\-common\fR] + [\fB\-t\fR|\fB\-\-totals\fR] + [\fB\-\-target=\fR\fIbfdname\fR] [\fB\-V\fR|\fB\-\-version\fR] + [\fIobjfile\fR...] +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +The \s-1GNU\s0 \fBsize\fR utility lists the section sizes\-\-\-and the total +size\-\-\-for each of the object or archive files \fIobjfile\fR in its +argument list. By default, one line of output is generated for each +object file or each module in an archive. +.PP +\&\fIobjfile\fR... are the object files to be examined. +If none are specified, the file \f(CW\*(C`a.out\*(C'\fR will be used. +.SH "OPTIONS" +.IX Header "OPTIONS" +The command line options have the following meanings: +.IP "\fB\-A\fR" 4 +.IX Item "-A" +.PD 0 +.IP "\fB\-B\fR" 4 +.IX Item "-B" +.IP "\fB\-\-format=\fR\fIcompatibility\fR" 4 +.IX Item "--format=compatibility" +.PD +Using one of these options, you can choose whether the output from \s-1GNU\s0 +\&\fBsize\fR resembles output from System V \fBsize\fR (using \fB\-A\fR, +or \fB\-\-format=sysv\fR), or Berkeley \fBsize\fR (using \fB\-B\fR, or +\&\fB\-\-format=berkeley\fR). The default is the one-line format similar to +Berkeley's. +.Sp +Here is an example of the Berkeley (default) format of output from +\&\fBsize\fR: +.Sp +.Vb 4 +\& $ size \-\-format=Berkeley ranlib size +\& text data bss dec hex filename +\& 294880 81920 11592 388392 5ed28 ranlib +\& 294880 81920 11888 388688 5ee50 size +.Ve +.Sp +This is the same data, but displayed closer to System V conventions: +.Sp +.Vb 7 +\& $ size \-\-format=SysV ranlib size +\& ranlib : +\& section size addr +\& .text 294880 8192 +\& .data 81920 303104 +\& .bss 11592 385024 +\& Total 388392 +\& +\& +\& size : +\& section size addr +\& .text 294880 8192 +\& .data 81920 303104 +\& .bss 11888 385024 +\& Total 388688 +.Ve +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +Show a summary of acceptable arguments and options. +.IP "\fB\-d\fR" 4 +.IX Item "-d" +.PD 0 +.IP "\fB\-o\fR" 4 +.IX Item "-o" +.IP "\fB\-x\fR" 4 +.IX Item "-x" +.IP "\fB\-\-radix=\fR\fInumber\fR" 4 +.IX Item "--radix=number" +.PD +Using one of these options, you can control whether the size of each +section is given in decimal (\fB\-d\fR, or \fB\-\-radix=10\fR); octal +(\fB\-o\fR, or \fB\-\-radix=8\fR); or hexadecimal (\fB\-x\fR, or +\&\fB\-\-radix=16\fR). In \fB\-\-radix=\fR\fInumber\fR, only the three +values (8, 10, 16) are supported. The total size is always given in two +radices; decimal and hexadecimal for \fB\-d\fR or \fB\-x\fR output, or +octal and hexadecimal if you're using \fB\-o\fR. +.IP "\fB\-\-common\fR" 4 +.IX Item "--common" +Print total size of common symbols in each file. When using Berkeley +format these are included in the bss size. +.IP "\fB\-t\fR" 4 +.IX Item "-t" +.PD 0 +.IP "\fB\-\-totals\fR" 4 +.IX Item "--totals" +.PD +Show totals of all objects listed (Berkeley format listing mode only). +.IP "\fB\-\-target=\fR\fIbfdname\fR" 4 +.IX Item "--target=bfdname" +Specify that the object-code format for \fIobjfile\fR is +\&\fIbfdname\fR. This option may not be necessary; \fBsize\fR can +automatically recognize many formats. +.IP "\fB\-V\fR" 4 +.IX Item "-V" +.PD 0 +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +.PD +Display the version number of \fBsize\fR. +.IP "\fB@\fR\fIfile\fR" 4 +.IX Item "@file" +Read command-line options from \fIfile\fR. The options read are +inserted in place of the original @\fIfile\fR option. If \fIfile\fR +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +.Sp +Options in \fIfile\fR are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The \fIfile\fR may itself contain additional +@\fIfile\fR options; any such options will be processed recursively. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fIar\fR\|(1), \fIobjdump\fR\|(1), \fIreadelf\fR\|(1), and the Info entries for \fIbinutils\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 +or any later version published by the Free Software Foundation; +with no Invariant Sections, with no Front-Cover Texts, and with no +Back-Cover Texts. A copy of the license is included in the +section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". diff --git a/share/man/man1/arm-eabi-strings.1 b/share/man/man1/arm-eabi-strings.1 new file mode 100644 index 0000000..02aff53 --- /dev/null +++ b/share/man/man1/arm-eabi-strings.1 @@ -0,0 +1,257 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "STRINGS 1" +.TH STRINGS 1 " " "binutils-2.21" "GNU Development Tools" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +strings \- print the strings of printable characters in files. +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +strings [\fB\-afovV\fR] [\fB\-\fR\fImin-len\fR] + [\fB\-n\fR \fImin-len\fR] [\fB\-\-bytes=\fR\fImin-len\fR] + [\fB\-t\fR \fIradix\fR] [\fB\-\-radix=\fR\fIradix\fR] + [\fB\-e\fR \fIencoding\fR] [\fB\-\-encoding=\fR\fIencoding\fR] + [\fB\-\fR] [\fB\-\-all\fR] [\fB\-\-print\-file\-name\fR] + [\fB\-T\fR \fIbfdname\fR] [\fB\-\-target=\fR\fIbfdname\fR] + [\fB\-\-help\fR] [\fB\-\-version\fR] \fIfile\fR... +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +For each \fIfile\fR given, \s-1GNU\s0 \fBstrings\fR prints the printable +character sequences that are at least 4 characters long (or the number +given with the options below) and are followed by an unprintable +character. By default, it only prints the strings from the initialized +and loaded sections of object files; for other types of files, it prints +the strings from the whole file. +.PP +\&\fBstrings\fR is mainly useful for determining the contents of non-text +files. +.SH "OPTIONS" +.IX Header "OPTIONS" +.IP "\fB\-a\fR" 4 +.IX Item "-a" +.PD 0 +.IP "\fB\-\-all\fR" 4 +.IX Item "--all" +.IP "\fB\-\fR" 4 +.IX Item "-" +.PD +Do not scan only the initialized and loaded sections of object files; +scan the whole files. +.IP "\fB\-f\fR" 4 +.IX Item "-f" +.PD 0 +.IP "\fB\-\-print\-file\-name\fR" 4 +.IX Item "--print-file-name" +.PD +Print the name of the file before each string. +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +Print a summary of the program usage on the standard output and exit. +.IP "\fB\-\fR\fImin-len\fR" 4 +.IX Item "-min-len" +.PD 0 +.IP "\fB\-n\fR \fImin-len\fR" 4 +.IX Item "-n min-len" +.IP "\fB\-\-bytes=\fR\fImin-len\fR" 4 +.IX Item "--bytes=min-len" +.PD +Print sequences of characters that are at least \fImin-len\fR characters +long, instead of the default 4. +.IP "\fB\-o\fR" 4 +.IX Item "-o" +Like \fB\-t o\fR. Some other versions of \fBstrings\fR have \fB\-o\fR +act like \fB\-t d\fR instead. Since we can not be compatible with both +ways, we simply chose one. +.IP "\fB\-t\fR \fIradix\fR" 4 +.IX Item "-t radix" +.PD 0 +.IP "\fB\-\-radix=\fR\fIradix\fR" 4 +.IX Item "--radix=radix" +.PD +Print the offset within the file before each string. The single +character argument specifies the radix of the offset\-\-\-\fBo\fR for +octal, \fBx\fR for hexadecimal, or \fBd\fR for decimal. +.IP "\fB\-e\fR \fIencoding\fR" 4 +.IX Item "-e encoding" +.PD 0 +.IP "\fB\-\-encoding=\fR\fIencoding\fR" 4 +.IX Item "--encoding=encoding" +.PD +Select the character encoding of the strings that are to be found. +Possible values for \fIencoding\fR are: \fBs\fR = single\-7\-bit\-byte +characters (\s-1ASCII\s0, \s-1ISO\s0 8859, etc., default), \fBS\fR = +single\-8\-bit\-byte characters, \fBb\fR = 16\-bit bigendian, \fBl\fR = +16\-bit littleendian, \fBB\fR = 32\-bit bigendian, \fBL\fR = 32\-bit +littleendian. Useful for finding wide character strings. (\fBl\fR +and \fBb\fR apply to, for example, Unicode \s-1UTF\-16/UCS\-2\s0 encodings). +.IP "\fB\-T\fR \fIbfdname\fR" 4 +.IX Item "-T bfdname" +.PD 0 +.IP "\fB\-\-target=\fR\fIbfdname\fR" 4 +.IX Item "--target=bfdname" +.PD +Specify an object code format other than your system's default format. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +.PD 0 +.IP "\fB\-V\fR" 4 +.IX Item "-V" +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +.PD +Print the program version number on the standard output and exit. +.IP "\fB@\fR\fIfile\fR" 4 +.IX Item "@file" +Read command-line options from \fIfile\fR. The options read are +inserted in place of the original @\fIfile\fR option. If \fIfile\fR +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +.Sp +Options in \fIfile\fR are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The \fIfile\fR may itself contain additional +@\fIfile\fR options; any such options will be processed recursively. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fIar\fR\|(1), \fInm\fR\|(1), \fIobjdump\fR\|(1), \fIranlib\fR\|(1), \fIreadelf\fR\|(1) +and the Info entries for \fIbinutils\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 +or any later version published by the Free Software Foundation; +with no Invariant Sections, with no Front-Cover Texts, and with no +Back-Cover Texts. A copy of the license is included in the +section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". diff --git a/share/man/man1/arm-eabi-strip.1 b/share/man/man1/arm-eabi-strip.1 new file mode 100644 index 0000000..bc66900 --- /dev/null +++ b/share/man/man1/arm-eabi-strip.1 @@ -0,0 +1,392 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "STRIP 1" +.TH STRIP 1 " " "binutils-2.21" "GNU Development Tools" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +strip \- Discard symbols from object files. +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +strip [\fB\-F\fR \fIbfdname\fR |\fB\-\-target=\fR\fIbfdname\fR] + [\fB\-I\fR \fIbfdname\fR |\fB\-\-input\-target=\fR\fIbfdname\fR] + [\fB\-O\fR \fIbfdname\fR |\fB\-\-output\-target=\fR\fIbfdname\fR] + [\fB\-s\fR|\fB\-\-strip\-all\fR] + [\fB\-S\fR|\fB\-g\fR|\fB\-d\fR|\fB\-\-strip\-debug\fR] + [\fB\-K\fR \fIsymbolname\fR |\fB\-\-keep\-symbol=\fR\fIsymbolname\fR] + [\fB\-N\fR \fIsymbolname\fR |\fB\-\-strip\-symbol=\fR\fIsymbolname\fR] + [\fB\-w\fR|\fB\-\-wildcard\fR] + [\fB\-x\fR|\fB\-\-discard\-all\fR] [\fB\-X\fR |\fB\-\-discard\-locals\fR] + [\fB\-R\fR \fIsectionname\fR |\fB\-\-remove\-section=\fR\fIsectionname\fR] + [\fB\-o\fR \fIfile\fR] [\fB\-p\fR|\fB\-\-preserve\-dates\fR] + [\fB\-\-keep\-file\-symbols\fR] + [\fB\-\-only\-keep\-debug\fR] + [\fB\-v\fR |\fB\-\-verbose\fR] [\fB\-V\fR|\fB\-\-version\fR] + [\fB\-\-help\fR] [\fB\-\-info\fR] + \fIobjfile\fR... +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +\&\s-1GNU\s0 \fBstrip\fR discards all symbols from object files +\&\fIobjfile\fR. The list of object files may include archives. +At least one object file must be given. +.PP +\&\fBstrip\fR modifies the files named in its argument, +rather than writing modified copies under different names. +.SH "OPTIONS" +.IX Header "OPTIONS" +.IP "\fB\-F\fR \fIbfdname\fR" 4 +.IX Item "-F bfdname" +.PD 0 +.IP "\fB\-\-target=\fR\fIbfdname\fR" 4 +.IX Item "--target=bfdname" +.PD +Treat the original \fIobjfile\fR as a file with the object +code format \fIbfdname\fR, and rewrite it in the same format. +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +Show a summary of the options to \fBstrip\fR and exit. +.IP "\fB\-\-info\fR" 4 +.IX Item "--info" +Display a list showing all architectures and object formats available. +.IP "\fB\-I\fR \fIbfdname\fR" 4 +.IX Item "-I bfdname" +.PD 0 +.IP "\fB\-\-input\-target=\fR\fIbfdname\fR" 4 +.IX Item "--input-target=bfdname" +.PD +Treat the original \fIobjfile\fR as a file with the object +code format \fIbfdname\fR. +.IP "\fB\-O\fR \fIbfdname\fR" 4 +.IX Item "-O bfdname" +.PD 0 +.IP "\fB\-\-output\-target=\fR\fIbfdname\fR" 4 +.IX Item "--output-target=bfdname" +.PD +Replace \fIobjfile\fR with a file in the output format \fIbfdname\fR. +.IP "\fB\-R\fR \fIsectionname\fR" 4 +.IX Item "-R sectionname" +.PD 0 +.IP "\fB\-\-remove\-section=\fR\fIsectionname\fR" 4 +.IX Item "--remove-section=sectionname" +.PD +Remove any section named \fIsectionname\fR from the output file. This +option may be given more than once. Note that using this option +inappropriately may make the output file unusable. +.IP "\fB\-s\fR" 4 +.IX Item "-s" +.PD 0 +.IP "\fB\-\-strip\-all\fR" 4 +.IX Item "--strip-all" +.PD +Remove all symbols. +.IP "\fB\-g\fR" 4 +.IX Item "-g" +.PD 0 +.IP "\fB\-S\fR" 4 +.IX Item "-S" +.IP "\fB\-d\fR" 4 +.IX Item "-d" +.IP "\fB\-\-strip\-debug\fR" 4 +.IX Item "--strip-debug" +.PD +Remove debugging symbols only. +.IP "\fB\-\-strip\-unneeded\fR" 4 +.IX Item "--strip-unneeded" +Remove all symbols that are not needed for relocation processing. +.IP "\fB\-K\fR \fIsymbolname\fR" 4 +.IX Item "-K symbolname" +.PD 0 +.IP "\fB\-\-keep\-symbol=\fR\fIsymbolname\fR" 4 +.IX Item "--keep-symbol=symbolname" +.PD +When stripping symbols, keep symbol \fIsymbolname\fR even if it would +normally be stripped. This option may be given more than once. +.IP "\fB\-N\fR \fIsymbolname\fR" 4 +.IX Item "-N symbolname" +.PD 0 +.IP "\fB\-\-strip\-symbol=\fR\fIsymbolname\fR" 4 +.IX Item "--strip-symbol=symbolname" +.PD +Remove symbol \fIsymbolname\fR from the source file. This option may be +given more than once, and may be combined with strip options other than +\&\fB\-K\fR. +.IP "\fB\-o\fR \fIfile\fR" 4 +.IX Item "-o file" +Put the stripped output in \fIfile\fR, rather than replacing the +existing file. When this argument is used, only one \fIobjfile\fR +argument may be specified. +.IP "\fB\-p\fR" 4 +.IX Item "-p" +.PD 0 +.IP "\fB\-\-preserve\-dates\fR" 4 +.IX Item "--preserve-dates" +.PD +Preserve the access and modification dates of the file. +.IP "\fB\-w\fR" 4 +.IX Item "-w" +.PD 0 +.IP "\fB\-\-wildcard\fR" 4 +.IX Item "--wildcard" +.PD +Permit regular expressions in \fIsymbolname\fRs used in other command +line options. The question mark (?), asterisk (*), backslash (\e) and +square brackets ([]) operators can be used anywhere in the symbol +name. If the first character of the symbol name is the exclamation +point (!) then the sense of the switch is reversed for that symbol. +For example: +.Sp +.Vb 1 +\& \-w \-K !foo \-K fo* +.Ve +.Sp +would cause strip to only keep symbols that start with the letters +\&\*(L"fo\*(R", but to discard the symbol \*(L"foo\*(R". +.IP "\fB\-x\fR" 4 +.IX Item "-x" +.PD 0 +.IP "\fB\-\-discard\-all\fR" 4 +.IX Item "--discard-all" +.PD +Remove non-global symbols. +.IP "\fB\-X\fR" 4 +.IX Item "-X" +.PD 0 +.IP "\fB\-\-discard\-locals\fR" 4 +.IX Item "--discard-locals" +.PD +Remove compiler-generated local symbols. +(These usually start with \fBL\fR or \fB.\fR.) +.IP "\fB\-\-keep\-file\-symbols\fR" 4 +.IX Item "--keep-file-symbols" +When stripping a file, perhaps with \fB\-\-strip\-debug\fR or +\&\fB\-\-strip\-unneeded\fR, retain any symbols specifying source file names, +which would otherwise get stripped. +.IP "\fB\-\-only\-keep\-debug\fR" 4 +.IX Item "--only-keep-debug" +Strip a file, removing contents of any sections that would not be +stripped by \fB\-\-strip\-debug\fR and leaving the debugging sections +intact. In \s-1ELF\s0 files, this preserves all note sections in the output. +.Sp +The intention is that this option will be used in conjunction with +\&\fB\-\-add\-gnu\-debuglink\fR to create a two part executable. One a +stripped binary which will occupy less space in \s-1RAM\s0 and in a +distribution and the second a debugging information file which is only +needed if debugging abilities are required. The suggested procedure +to create these files is as follows: +.RS 4 +.IP "1.<Link the executable as normal. Assuming that is is called>" 4 +.IX Item "1.<Link the executable as normal. Assuming that is is called>" +\&\f(CW\*(C`foo\*(C'\fR then... +.ie n .IP "1.<Run ""objcopy \-\-only\-keep\-debug foo foo.dbg"" to>" 4 +.el .IP "1.<Run \f(CWobjcopy \-\-only\-keep\-debug foo foo.dbg\fR to>" 4 +.IX Item "1.<Run objcopy --only-keep-debug foo foo.dbg to>" +create a file containing the debugging info. +.ie n .IP "1.<Run ""objcopy \-\-strip\-debug foo"" to create a>" 4 +.el .IP "1.<Run \f(CWobjcopy \-\-strip\-debug foo\fR to create a>" 4 +.IX Item "1.<Run objcopy --strip-debug foo to create a>" +stripped executable. +.ie n .IP "1.<Run ""objcopy \-\-add\-gnu\-debuglink=foo.dbg foo"">" 4 +.el .IP "1.<Run \f(CWobjcopy \-\-add\-gnu\-debuglink=foo.dbg foo\fR>" 4 +.IX Item "1.<Run objcopy --add-gnu-debuglink=foo.dbg foo>" +to add a link to the debugging info into the stripped executable. +.RE +.RS 4 +.Sp +Note\-\-\-the choice of \f(CW\*(C`.dbg\*(C'\fR as an extension for the debug info +file is arbitrary. Also the \f(CW\*(C`\-\-only\-keep\-debug\*(C'\fR step is +optional. You could instead do this: +.IP "1.<Link the executable as normal.>" 4 +.IX Item "1.<Link the executable as normal.>" +.PD 0 +.ie n .IP "1.<Copy ""foo"" to ""foo.full"">" 4 +.el .IP "1.<Copy \f(CWfoo\fR to \f(CWfoo.full\fR>" 4 +.IX Item "1.<Copy foo to foo.full>" +.ie n .IP "1.<Run ""strip \-\-strip\-debug foo"">" 4 +.el .IP "1.<Run \f(CWstrip \-\-strip\-debug foo\fR>" 4 +.IX Item "1.<Run strip --strip-debug foo>" +.ie n .IP "1.<Run ""objcopy \-\-add\-gnu\-debuglink=foo.full foo"">" 4 +.el .IP "1.<Run \f(CWobjcopy \-\-add\-gnu\-debuglink=foo.full foo\fR>" 4 +.IX Item "1.<Run objcopy --add-gnu-debuglink=foo.full foo>" +.RE +.RS 4 +.PD +.Sp +i.e., the file pointed to by the \fB\-\-add\-gnu\-debuglink\fR can be the +full executable. It does not have to be a file created by the +\&\fB\-\-only\-keep\-debug\fR switch. +.Sp +Note\-\-\-this switch is only intended for use on fully linked files. It +does not make sense to use it on object files where the debugging +information may be incomplete. Besides the gnu_debuglink feature +currently only supports the presence of one filename containing +debugging information, not multiple filenames on a one-per-object-file +basis. +.RE +.IP "\fB\-V\fR" 4 +.IX Item "-V" +.PD 0 +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +.PD +Show the version number for \fBstrip\fR. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +.PD 0 +.IP "\fB\-\-verbose\fR" 4 +.IX Item "--verbose" +.PD +Verbose output: list all object files modified. In the case of +archives, \fBstrip \-v\fR lists all members of the archive. +.IP "\fB@\fR\fIfile\fR" 4 +.IX Item "@file" +Read command-line options from \fIfile\fR. The options read are +inserted in place of the original @\fIfile\fR option. If \fIfile\fR +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +.Sp +Options in \fIfile\fR are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The \fIfile\fR may itself contain additional +@\fIfile\fR options; any such options will be processed recursively. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +the Info entries for \fIbinutils\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 +or any later version published by the Free Software Foundation; +with no Invariant Sections, with no Front-Cover Texts, and with no +Back-Cover Texts. A copy of the license is included in the +section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". diff --git a/share/man/man1/arm-eabi-windmc.1 b/share/man/man1/arm-eabi-windmc.1 new file mode 100644 index 0000000..8449e40 --- /dev/null +++ b/share/man/man1/arm-eabi-windmc.1 @@ -0,0 +1,353 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "WINDMC 1" +.TH WINDMC 1 " " "binutils-2.21" "GNU Development Tools" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +windmc \- generates Windows message resources. +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +windmc [options] input-file +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +\&\fBwindmc\fR reads message definitions from an input file (.mc) and +translate them into a set of output files. The output files may be of +four kinds: +.ie n .IP """h""" 4 +.el .IP "\f(CWh\fR" 4 +.IX Item "h" +A C header file containing the message definitions. +.ie n .IP """rc""" 4 +.el .IP "\f(CWrc\fR" 4 +.IX Item "rc" +A resource file compilable by the \fBwindres\fR tool. +.ie n .IP """bin""" 4 +.el .IP "\f(CWbin\fR" 4 +.IX Item "bin" +One or more binary files containing the resource data for a specific +message language. +.ie n .IP """dbg""" 4 +.el .IP "\f(CWdbg\fR" 4 +.IX Item "dbg" +A C include file that maps message id's to their symbolic name. +.PP +The exact description of these different formats is available in +documentation from Microsoft. +.PP +When \fBwindmc\fR converts from the \f(CW\*(C`mc\*(C'\fR format to the \f(CW\*(C`bin\*(C'\fR +format, \f(CW\*(C`rc\*(C'\fR, \f(CW\*(C`h\*(C'\fR, and optional \f(CW\*(C`dbg\*(C'\fR it is acting like the +Windows Message Compiler. +.SH "OPTIONS" +.IX Header "OPTIONS" +.IP "\fB\-a\fR" 4 +.IX Item "-a" +.PD 0 +.IP "\fB\-\-ascii_in\fR" 4 +.IX Item "--ascii_in" +.PD +Specifies that the input file specified is \s-1ASCII\s0. This is the default +behaviour. +.IP "\fB\-A\fR" 4 +.IX Item "-A" +.PD 0 +.IP "\fB\-\-ascii_out\fR" 4 +.IX Item "--ascii_out" +.PD +Specifies that messages in the output \f(CW\*(C`bin\*(C'\fR files should be in \s-1ASCII\s0 +format. +.IP "\fB\-b\fR" 4 +.IX Item "-b" +.PD 0 +.IP "\fB\-\-binprefix\fR" 4 +.IX Item "--binprefix" +.PD +Specifies that \f(CW\*(C`bin\*(C'\fR filenames should have to be prefixed by the +basename of the source file. +.IP "\fB\-c\fR" 4 +.IX Item "-c" +.PD 0 +.IP "\fB\-\-customflag\fR" 4 +.IX Item "--customflag" +.PD +Sets the customer bit in all message id's. +.IP "\fB\-C\fR \fIcodepage\fR" 4 +.IX Item "-C codepage" +.PD 0 +.IP "\fB\-\-codepage_in\fR \fIcodepage\fR" 4 +.IX Item "--codepage_in codepage" +.PD +Sets the default codepage to be used to convert input file to \s-1UTF16\s0. The +default is ocdepage 1252. +.IP "\fB\-d\fR" 4 +.IX Item "-d" +.PD 0 +.IP "\fB\-\-decimal_values\fR" 4 +.IX Item "--decimal_values" +.PD +Outputs the constants in the header file in decimal. Default is using +hexadecimal output. +.IP "\fB\-e\fR \fIext\fR" 4 +.IX Item "-e ext" +.PD 0 +.IP "\fB\-\-extension\fR \fIext\fR" 4 +.IX Item "--extension ext" +.PD +The extension for the header file. The default is .h extension. +.IP "\fB\-F\fR \fItarget\fR" 4 +.IX Item "-F target" +.PD 0 +.IP "\fB\-\-target\fR \fItarget\fR" 4 +.IX Item "--target target" +.PD +Specify the \s-1BFD\s0 format to use for a bin file as output. This +is a \s-1BFD\s0 target name; you can use the \fB\-\-help\fR option to see a list +of supported targets. Normally \fBwindmc\fR will use the default +format, which is the first one listed by the \fB\-\-help\fR option. +.IP "\fB\-h\fR \fIpath\fR" 4 +.IX Item "-h path" +.PD 0 +.IP "\fB\-\-headerdir\fR \fIpath\fR" 4 +.IX Item "--headerdir path" +.PD +The target directory of the generated header file. The default is the +current directory. +.IP "\fB\-H\fR" 4 +.IX Item "-H" +.PD 0 +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +.PD +Displays a list of command line options and then exits. +.IP "\fB\-m\fR \fIcharacters\fR" 4 +.IX Item "-m characters" +.PD 0 +.IP "\fB\-\-maxlength\fR \fIcharacters\fR" 4 +.IX Item "--maxlength characters" +.PD +Instructs \fBwindmc\fR to generate a warning if the length +of any message exceeds the number specified. +.IP "\fB\-n\fR" 4 +.IX Item "-n" +.PD 0 +.IP "\fB\-\-nullterminate\fR" 4 +.IX Item "--nullterminate" +.PD +Terminate message text in \f(CW\*(C`bin\*(C'\fR files by zero. By default they are +terminated by \s-1CR/LF\s0. +.IP "\fB\-o\fR" 4 +.IX Item "-o" +.PD 0 +.IP "\fB\-\-hresult_use\fR" 4 +.IX Item "--hresult_use" +.PD +Not yet implemented. Instructs \f(CW\*(C`windmc\*(C'\fR to generate an \s-1OLE2\s0 header +file, using \s-1HRESULT\s0 definitions. Status codes are used if the flag is not +specified. +.IP "\fB\-O\fR \fIcodepage\fR" 4 +.IX Item "-O codepage" +.PD 0 +.IP "\fB\-\-codepage_out\fR \fIcodepage\fR" 4 +.IX Item "--codepage_out codepage" +.PD +Sets the default codepage to be used to output text files. The default +is ocdepage 1252. +.IP "\fB\-r\fR \fIpath\fR" 4 +.IX Item "-r path" +.PD 0 +.IP "\fB\-\-rcdir\fR \fIpath\fR" 4 +.IX Item "--rcdir path" +.PD +The target directory for the generated \f(CW\*(C`rc\*(C'\fR script and the generated +\&\f(CW\*(C`bin\*(C'\fR files that the resource compiler script includes. The default +is the current directory. +.IP "\fB\-u\fR" 4 +.IX Item "-u" +.PD 0 +.IP "\fB\-\-unicode_in\fR" 4 +.IX Item "--unicode_in" +.PD +Specifies that the input file is \s-1UTF16\s0. +.IP "\fB\-U\fR" 4 +.IX Item "-U" +.PD 0 +.IP "\fB\-\-unicode_out\fR" 4 +.IX Item "--unicode_out" +.PD +Specifies that messages in the output \f(CW\*(C`bin\*(C'\fR file should be in \s-1UTF16\s0 +format. This is the default behaviour. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +.PD 0 +.IP "\fB\-\-verbose\fR" 4 +.IX Item "--verbose" +.PD +Enable verbose mode. +.IP "\fB\-V\fR" 4 +.IX Item "-V" +.PD 0 +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +.PD +Prints the version number for \fBwindmc\fR. +.IP "\fB\-x\fR \fIpath\fR" 4 +.IX Item "-x path" +.PD 0 +.IP "\fB\-\-xdgb\fR \fIpath\fR" 4 +.IX Item "--xdgb path" +.PD +The path of the \f(CW\*(C`dbg\*(C'\fR C include file that maps message id's to the +symbolic name. No such file is generated without specifying the switch. +.IP "\fB@\fR\fIfile\fR" 4 +.IX Item "@file" +Read command-line options from \fIfile\fR. The options read are +inserted in place of the original @\fIfile\fR option. If \fIfile\fR +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +.Sp +Options in \fIfile\fR are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The \fIfile\fR may itself contain additional +@\fIfile\fR options; any such options will be processed recursively. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +the Info entries for \fIbinutils\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 +or any later version published by the Free Software Foundation; +with no Invariant Sections, with no Front-Cover Texts, and with no +Back-Cover Texts. A copy of the license is included in the +section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". diff --git a/share/man/man1/arm-eabi-windres.1 b/share/man/man1/arm-eabi-windres.1 new file mode 100644 index 0000000..53fe7cc --- /dev/null +++ b/share/man/man1/arm-eabi-windres.1 @@ -0,0 +1,354 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "WINDRES 1" +.TH WINDRES 1 " " "binutils-2.21" "GNU Development Tools" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +windres \- manipulate Windows resources. +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +windres [options] [input\-file] [output\-file] +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +\&\fBwindres\fR reads resources from an input file and copies them into +an output file. Either file may be in one of three formats: +.ie n .IP """rc""" 4 +.el .IP "\f(CWrc\fR" 4 +.IX Item "rc" +A text format read by the Resource Compiler. +.ie n .IP """res""" 4 +.el .IP "\f(CWres\fR" 4 +.IX Item "res" +A binary format generated by the Resource Compiler. +.ie n .IP """coff""" 4 +.el .IP "\f(CWcoff\fR" 4 +.IX Item "coff" +A \s-1COFF\s0 object or executable. +.PP +The exact description of these different formats is available in +documentation from Microsoft. +.PP +When \fBwindres\fR converts from the \f(CW\*(C`rc\*(C'\fR format to the \f(CW\*(C`res\*(C'\fR +format, it is acting like the Windows Resource Compiler. When +\&\fBwindres\fR converts from the \f(CW\*(C`res\*(C'\fR format to the \f(CW\*(C`coff\*(C'\fR +format, it is acting like the Windows \f(CW\*(C`CVTRES\*(C'\fR program. +.PP +When \fBwindres\fR generates an \f(CW\*(C`rc\*(C'\fR file, the output is similar +but not identical to the format expected for the input. When an input +\&\f(CW\*(C`rc\*(C'\fR file refers to an external filename, an output \f(CW\*(C`rc\*(C'\fR file +will instead include the file contents. +.PP +If the input or output format is not specified, \fBwindres\fR will +guess based on the file name, or, for the input file, the file contents. +A file with an extension of \fI.rc\fR will be treated as an \f(CW\*(C`rc\*(C'\fR +file, a file with an extension of \fI.res\fR will be treated as a +\&\f(CW\*(C`res\*(C'\fR file, and a file with an extension of \fI.o\fR or +\&\fI.exe\fR will be treated as a \f(CW\*(C`coff\*(C'\fR file. +.PP +If no output file is specified, \fBwindres\fR will print the resources +in \f(CW\*(C`rc\*(C'\fR format to standard output. +.PP +The normal use is for you to write an \f(CW\*(C`rc\*(C'\fR file, use \fBwindres\fR +to convert it to a \s-1COFF\s0 object file, and then link the \s-1COFF\s0 file into +your application. This will make the resources described in the +\&\f(CW\*(C`rc\*(C'\fR file available to Windows. +.SH "OPTIONS" +.IX Header "OPTIONS" +.IP "\fB\-i\fR \fIfilename\fR" 4 +.IX Item "-i filename" +.PD 0 +.IP "\fB\-\-input\fR \fIfilename\fR" 4 +.IX Item "--input filename" +.PD +The name of the input file. If this option is not used, then +\&\fBwindres\fR will use the first non-option argument as the input file +name. If there are no non-option arguments, then \fBwindres\fR will +read from standard input. \fBwindres\fR can not read a \s-1COFF\s0 file from +standard input. +.IP "\fB\-o\fR \fIfilename\fR" 4 +.IX Item "-o filename" +.PD 0 +.IP "\fB\-\-output\fR \fIfilename\fR" 4 +.IX Item "--output filename" +.PD +The name of the output file. If this option is not used, then +\&\fBwindres\fR will use the first non-option argument, after any used +for the input file name, as the output file name. If there is no +non-option argument, then \fBwindres\fR will write to standard output. +\&\fBwindres\fR can not write a \s-1COFF\s0 file to standard output. Note, +for compatibility with \fBrc\fR the option \fB\-fo\fR is also +accepted, but its use is not recommended. +.IP "\fB\-J\fR \fIformat\fR" 4 +.IX Item "-J format" +.PD 0 +.IP "\fB\-\-input\-format\fR \fIformat\fR" 4 +.IX Item "--input-format format" +.PD +The input format to read. \fIformat\fR may be \fBres\fR, \fBrc\fR, or +\&\fBcoff\fR. If no input format is specified, \fBwindres\fR will +guess, as described above. +.IP "\fB\-O\fR \fIformat\fR" 4 +.IX Item "-O format" +.PD 0 +.IP "\fB\-\-output\-format\fR \fIformat\fR" 4 +.IX Item "--output-format format" +.PD +The output format to generate. \fIformat\fR may be \fBres\fR, +\&\fBrc\fR, or \fBcoff\fR. If no output format is specified, +\&\fBwindres\fR will guess, as described above. +.IP "\fB\-F\fR \fItarget\fR" 4 +.IX Item "-F target" +.PD 0 +.IP "\fB\-\-target\fR \fItarget\fR" 4 +.IX Item "--target target" +.PD +Specify the \s-1BFD\s0 format to use for a \s-1COFF\s0 file as input or output. This +is a \s-1BFD\s0 target name; you can use the \fB\-\-help\fR option to see a list +of supported targets. Normally \fBwindres\fR will use the default +format, which is the first one listed by the \fB\-\-help\fR option. +.IP "\fB\-\-preprocessor\fR \fIprogram\fR" 4 +.IX Item "--preprocessor program" +When \fBwindres\fR reads an \f(CW\*(C`rc\*(C'\fR file, it runs it through the C +preprocessor first. This option may be used to specify the preprocessor +to use, including any leading arguments. The default preprocessor +argument is \f(CW\*(C`gcc \-E \-xc\-header \-DRC_INVOKED\*(C'\fR. +.IP "\fB\-I\fR \fIdirectory\fR" 4 +.IX Item "-I directory" +.PD 0 +.IP "\fB\-\-include\-dir\fR \fIdirectory\fR" 4 +.IX Item "--include-dir directory" +.PD +Specify an include directory to use when reading an \f(CW\*(C`rc\*(C'\fR file. +\&\fBwindres\fR will pass this to the preprocessor as an \fB\-I\fR +option. \fBwindres\fR will also search this directory when looking for +files named in the \f(CW\*(C`rc\*(C'\fR file. If the argument passed to this command +matches any of the supported \fIformats\fR (as described in the \fB\-J\fR +option), it will issue a deprecation warning, and behave just like the +\&\fB\-J\fR option. New programs should not use this behaviour. If a +directory happens to match a \fIformat\fR, simple prefix it with \fB./\fR +to disable the backward compatibility. +.IP "\fB\-D\fR \fItarget\fR" 4 +.IX Item "-D target" +.PD 0 +.IP "\fB\-\-define\fR \fIsym\fR\fB[=\fR\fIval\fR\fB]\fR" 4 +.IX Item "--define sym[=val]" +.PD +Specify a \fB\-D\fR option to pass to the preprocessor when reading an +\&\f(CW\*(C`rc\*(C'\fR file. +.IP "\fB\-U\fR \fItarget\fR" 4 +.IX Item "-U target" +.PD 0 +.IP "\fB\-\-undefine\fR \fIsym\fR" 4 +.IX Item "--undefine sym" +.PD +Specify a \fB\-U\fR option to pass to the preprocessor when reading an +\&\f(CW\*(C`rc\*(C'\fR file. +.IP "\fB\-r\fR" 4 +.IX Item "-r" +Ignored for compatibility with rc. +.IP "\fB\-v\fR" 4 +.IX Item "-v" +Enable verbose mode. This tells you what the preprocessor is if you +didn't specify one. +.IP "\fB\-c\fR \fIval\fR" 4 +.IX Item "-c val" +.PD 0 +.IP "\fB\-\-codepage\fR \fIval\fR" 4 +.IX Item "--codepage val" +.PD +Specify the default codepage to use when reading an \f(CW\*(C`rc\*(C'\fR file. +\&\fIval\fR should be a hexadecimal prefixed by \fB0x\fR or decimal +codepage code. The valid range is from zero up to 0xffff, but the +validity of the codepage is host and configuration dependent. +.IP "\fB\-l\fR \fIval\fR" 4 +.IX Item "-l val" +.PD 0 +.IP "\fB\-\-language\fR \fIval\fR" 4 +.IX Item "--language val" +.PD +Specify the default language to use when reading an \f(CW\*(C`rc\*(C'\fR file. +\&\fIval\fR should be a hexadecimal language code. The low eight bits are +the language, and the high eight bits are the sublanguage. +.IP "\fB\-\-use\-temp\-file\fR" 4 +.IX Item "--use-temp-file" +Use a temporary file to instead of using popen to read the output of +the preprocessor. Use this option if the popen implementation is buggy +on the host (eg., certain non-English language versions of Windows 95 and +Windows 98 are known to have buggy popen where the output will instead +go the console). +.IP "\fB\-\-no\-use\-temp\-file\fR" 4 +.IX Item "--no-use-temp-file" +Use popen, not a temporary file, to read the output of the preprocessor. +This is the default behaviour. +.IP "\fB\-h\fR" 4 +.IX Item "-h" +.PD 0 +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +.PD +Prints a usage summary. +.IP "\fB\-V\fR" 4 +.IX Item "-V" +.PD 0 +.IP "\fB\-\-version\fR" 4 +.IX Item "--version" +.PD +Prints the version number for \fBwindres\fR. +.IP "\fB\-\-yydebug\fR" 4 +.IX Item "--yydebug" +If \fBwindres\fR is compiled with \f(CW\*(C`YYDEBUG\*(C'\fR defined as \f(CW1\fR, +this will turn on parser debugging. +.IP "\fB@\fR\fIfile\fR" 4 +.IX Item "@file" +Read command-line options from \fIfile\fR. The options read are +inserted in place of the original @\fIfile\fR option. If \fIfile\fR +does not exist, or cannot be read, then the option will be treated +literally, and not removed. +.Sp +Options in \fIfile\fR are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The \fIfile\fR may itself contain additional +@\fIfile\fR options; any such options will be processed recursively. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +the Info entries for \fIbinutils\fR. +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +Free Software Foundation, Inc. +.PP +Permission is granted to copy, distribute and/or modify this document +under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 +or any later version published by the Free Software Foundation; +with no Invariant Sections, with no Front-Cover Texts, and with no +Back-Cover Texts. A copy of the license is included in the +section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". diff --git a/share/man/man7/fsf-funding.7 b/share/man/man7/fsf-funding.7 new file mode 100644 index 0000000..d566678 --- /dev/null +++ b/share/man/man7/fsf-funding.7 @@ -0,0 +1,184 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "FSF-FUNDING 7" +.TH FSF-FUNDING 7 "2012-01-06" "gcc-4.6.x-google" "GNU" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +fsf\-funding \- Funding Free Software +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +.SS "Funding Free Software" +.IX Subsection "Funding Free Software" +If you want to have more free software a few years from now, it makes +sense for you to help encourage people to contribute funds for its +development. The most effective approach known is to encourage +commercial redistributors to donate. +.PP +Users of free software systems can boost the pace of development by +encouraging for-a-fee distributors to donate part of their selling price +to free software developers\-\-\-the Free Software Foundation, and others. +.PP +The way to convince distributors to do this is to demand it and expect +it from them. So when you compare distributors, judge them partly by +how much they give to free software development. Show distributors +they must compete to be the one who gives the most. +.PP +To make this approach work, you must insist on numbers that you can +compare, such as, \*(L"We will donate ten dollars to the Frobnitz project +for each disk sold.\*(R" Don't be satisfied with a vague promise, such as +\&\*(L"A portion of the profits are donated,\*(R" since it doesn't give a basis +for comparison. +.PP +Even a precise fraction \*(L"of the profits from this disk\*(R" is not very +meaningful, since creative accounting and unrelated business decisions +can greatly alter what fraction of the sales price counts as profit. +If the price you pay is \f(CW$50\fR, ten percent of the profit is probably +less than a dollar; it might be a few cents, or nothing at all. +.PP +Some redistributors do development work themselves. This is useful too; +but to keep everyone honest, you need to inquire how much they do, and +what kind. Some kinds of development make much more long-term +difference than others. For example, maintaining a separate version of +a program contributes very little; maintaining the standard version of a +program for the whole community contributes much. Easy new ports +contribute little, since someone else would surely do them; difficult +ports such as adding a new \s-1CPU\s0 to the \s-1GNU\s0 Compiler Collection contribute more; +major new features or packages contribute the most. +.PP +By establishing the idea that supporting further development is \*(L"the +proper thing to do\*(R" when distributing free software for a fee, we can +assure a steady flow of resources into making more free software. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fIgpl\fR\|(7), \fIgfdl\fR\|(7). +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 1994 Free Software Foundation, Inc. +Verbatim copying and redistribution of this section is permitted +without royalty; alteration is not permitted. diff --git a/share/man/man7/gfdl.7 b/share/man/man7/gfdl.7 new file mode 100644 index 0000000..bb1f8fd --- /dev/null +++ b/share/man/man7/gfdl.7 @@ -0,0 +1,637 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "GFDL 7" +.TH GFDL 7 "2012-01-06" "gcc-4.6.x-google" "GNU" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +gfdl \- GNU Free Documentation License +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +.SS "\s-1GNU\s0 Free Documentation License" +.IX Subsection "GNU Free Documentation License" +.SS "Version 1.3, 3 November 2008" +.IX Subsection "Version 1.3, 3 November 2008" +.Vb 2 +\& Copyright (c) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. +\& E<lt>B<http://fsf.org/>E<gt> +\& +\& Everyone is permitted to copy and distribute verbatim copies +\& of this license document, but changing it is not allowed. +.Ve +.IP "0." 4 +.IX Item "0." +\&\s-1PREAMBLE\s0 +.Sp +The purpose of this License is to make a manual, textbook, or other +functional and useful document \fIfree\fR in the sense of freedom: to +assure everyone the effective freedom to copy and redistribute it, +with or without modifying it, either commercially or noncommercially. +Secondarily, this License preserves for the author and publisher a way +to get credit for their work, while not being considered responsible +for modifications made by others. +.Sp +This License is a kind of \*(L"copyleft\*(R", which means that derivative +works of the document must themselves be free in the same sense. It +complements the \s-1GNU\s0 General Public License, which is a copyleft +license designed for free software. +.Sp +We have designed this License in order to use it for manuals for free +software, because free software needs free documentation: a free +program should come with manuals providing the same freedoms that the +software does. But this License is not limited to software manuals; +it can be used for any textual work, regardless of subject matter or +whether it is published as a printed book. We recommend this License +principally for works whose purpose is instruction or reference. +.IP "1." 4 +.IX Item "1." +\&\s-1APPLICABILITY\s0 \s-1AND\s0 \s-1DEFINITIONS\s0 +.Sp +This License applies to any manual or other work, in any medium, that +contains a notice placed by the copyright holder saying it can be +distributed under the terms of this License. Such a notice grants a +world-wide, royalty-free license, unlimited in duration, to use that +work under the conditions stated herein. The \*(L"Document\*(R", below, +refers to any such manual or work. Any member of the public is a +licensee, and is addressed as \*(L"you\*(R". You accept the license if you +copy, modify or distribute the work in a way requiring permission +under copyright law. +.Sp +A \*(L"Modified Version\*(R" of the Document means any work containing the +Document or a portion of it, either copied verbatim, or with +modifications and/or translated into another language. +.Sp +A \*(L"Secondary Section\*(R" is a named appendix or a front-matter section +of the Document that deals exclusively with the relationship of the +publishers or authors of the Document to the Document's overall +subject (or to related matters) and contains nothing that could fall +directly within that overall subject. (Thus, if the Document is in +part a textbook of mathematics, a Secondary Section may not explain +any mathematics.) The relationship could be a matter of historical +connection with the subject or with related matters, or of legal, +commercial, philosophical, ethical or political position regarding +them. +.Sp +The \*(L"Invariant Sections\*(R" are certain Secondary Sections whose titles +are designated, as being those of Invariant Sections, in the notice +that says that the Document is released under this License. If a +section does not fit the above definition of Secondary then it is not +allowed to be designated as Invariant. The Document may contain zero +Invariant Sections. If the Document does not identify any Invariant +Sections then there are none. +.Sp +The \*(L"Cover Texts\*(R" are certain short passages of text that are listed, +as Front-Cover Texts or Back-Cover Texts, in the notice that says that +the Document is released under this License. A Front-Cover Text may +be at most 5 words, and a Back-Cover Text may be at most 25 words. +.Sp +A \*(L"Transparent\*(R" copy of the Document means a machine-readable copy, +represented in a format whose specification is available to the +general public, that is suitable for revising the document +straightforwardly with generic text editors or (for images composed of +pixels) generic paint programs or (for drawings) some widely available +drawing editor, and that is suitable for input to text formatters or +for automatic translation to a variety of formats suitable for input +to text formatters. A copy made in an otherwise Transparent file +format whose markup, or absence of markup, has been arranged to thwart +or discourage subsequent modification by readers is not Transparent. +An image format is not Transparent if used for any substantial amount +of text. A copy that is not \*(L"Transparent\*(R" is called \*(L"Opaque\*(R". +.Sp +Examples of suitable formats for Transparent copies include plain +\&\s-1ASCII\s0 without markup, Texinfo input format, LaTeX input +format, \s-1SGML\s0 or \s-1XML\s0 using a publicly available +\&\s-1DTD\s0, and standard-conforming simple \s-1HTML\s0, +PostScript or \s-1PDF\s0 designed for human modification. Examples +of transparent image formats include \s-1PNG\s0, \s-1XCF\s0 and +\&\s-1JPG\s0. Opaque formats include proprietary formats that can be +read and edited only by proprietary word processors, \s-1SGML\s0 or +\&\s-1XML\s0 for which the \s-1DTD\s0 and/or processing tools are +not generally available, and the machine-generated \s-1HTML\s0, +PostScript or \s-1PDF\s0 produced by some word processors for +output purposes only. +.Sp +The \*(L"Title Page\*(R" means, for a printed book, the title page itself, +plus such following pages as are needed to hold, legibly, the material +this License requires to appear in the title page. For works in +formats which do not have any title page as such, \*(L"Title Page\*(R" means +the text near the most prominent appearance of the work's title, +preceding the beginning of the body of the text. +.Sp +The \*(L"publisher\*(R" means any person or entity that distributes copies +of the Document to the public. +.Sp +A section \*(L"Entitled \s-1XYZ\s0\*(R" means a named subunit of the Document whose +title either is precisely \s-1XYZ\s0 or contains \s-1XYZ\s0 in parentheses following +text that translates \s-1XYZ\s0 in another language. (Here \s-1XYZ\s0 stands for a +specific section name mentioned below, such as \*(L"Acknowledgements\*(R", +\&\*(L"Dedications\*(R", \*(L"Endorsements\*(R", or \*(L"History\*(R".) To \*(L"Preserve the Title\*(R" +of such a section when you modify the Document means that it remains a +section \*(L"Entitled \s-1XYZ\s0\*(R" according to this definition. +.Sp +The Document may include Warranty Disclaimers next to the notice which +states that this License applies to the Document. These Warranty +Disclaimers are considered to be included by reference in this +License, but only as regards disclaiming warranties: any other +implication that these Warranty Disclaimers may have is void and has +no effect on the meaning of this License. +.IP "2." 4 +.IX Item "2." +\&\s-1VERBATIM\s0 \s-1COPYING\s0 +.Sp +You may copy and distribute the Document in any medium, either +commercially or noncommercially, provided that this License, the +copyright notices, and the license notice saying this License applies +to the Document are reproduced in all copies, and that you add no other +conditions whatsoever to those of this License. You may not use +technical measures to obstruct or control the reading or further +copying of the copies you make or distribute. However, you may accept +compensation in exchange for copies. If you distribute a large enough +number of copies you must also follow the conditions in section 3. +.Sp +You may also lend copies, under the same conditions stated above, and +you may publicly display copies. +.IP "3." 4 +.IX Item "3." +\&\s-1COPYING\s0 \s-1IN\s0 \s-1QUANTITY\s0 +.Sp +If you publish printed copies (or copies in media that commonly have +printed covers) of the Document, numbering more than 100, and the +Document's license notice requires Cover Texts, you must enclose the +copies in covers that carry, clearly and legibly, all these Cover +Texts: Front-Cover Texts on the front cover, and Back-Cover Texts on +the back cover. Both covers must also clearly and legibly identify +you as the publisher of these copies. The front cover must present +the full title with all words of the title equally prominent and +visible. You may add other material on the covers in addition. +Copying with changes limited to the covers, as long as they preserve +the title of the Document and satisfy these conditions, can be treated +as verbatim copying in other respects. +.Sp +If the required texts for either cover are too voluminous to fit +legibly, you should put the first ones listed (as many as fit +reasonably) on the actual cover, and continue the rest onto adjacent +pages. +.Sp +If you publish or distribute Opaque copies of the Document numbering +more than 100, you must either include a machine-readable Transparent +copy along with each Opaque copy, or state in or with each Opaque copy +a computer-network location from which the general network-using +public has access to download using public-standard network protocols +a complete Transparent copy of the Document, free of added material. +If you use the latter option, you must take reasonably prudent steps, +when you begin distribution of Opaque copies in quantity, to ensure +that this Transparent copy will remain thus accessible at the stated +location until at least one year after the last time you distribute an +Opaque copy (directly or through your agents or retailers) of that +edition to the public. +.Sp +It is requested, but not required, that you contact the authors of the +Document well before redistributing any large number of copies, to give +them a chance to provide you with an updated version of the Document. +.IP "4." 4 +.IX Item "4." +\&\s-1MODIFICATIONS\s0 +.Sp +You may copy and distribute a Modified Version of the Document under +the conditions of sections 2 and 3 above, provided that you release +the Modified Version under precisely this License, with the Modified +Version filling the role of the Document, thus licensing distribution +and modification of the Modified Version to whoever possesses a copy +of it. In addition, you must do these things in the Modified Version: +.RS 4 +.IP "A." 4 +.IX Item "A." +Use in the Title Page (and on the covers, if any) a title distinct +from that of the Document, and from those of previous versions +(which should, if there were any, be listed in the History section +of the Document). You may use the same title as a previous version +if the original publisher of that version gives permission. +.IP "B." 4 +.IX Item "B." +List on the Title Page, as authors, one or more persons or entities +responsible for authorship of the modifications in the Modified +Version, together with at least five of the principal authors of the +Document (all of its principal authors, if it has fewer than five), +unless they release you from this requirement. +.IP "C." 4 +.IX Item "C." +State on the Title page the name of the publisher of the +Modified Version, as the publisher. +.IP "D." 4 +.IX Item "D." +Preserve all the copyright notices of the Document. +.IP "E." 4 +.IX Item "E." +Add an appropriate copyright notice for your modifications +adjacent to the other copyright notices. +.IP "F." 4 +.IX Item "F." +Include, immediately after the copyright notices, a license notice +giving the public permission to use the Modified Version under the +terms of this License, in the form shown in the Addendum below. +.IP "G." 4 +.IX Item "G." +Preserve in that license notice the full lists of Invariant Sections +and required Cover Texts given in the Document's license notice. +.IP "H." 4 +.IX Item "H." +Include an unaltered copy of this License. +.IP "I." 4 +.IX Item "I." +Preserve the section Entitled \*(L"History\*(R", Preserve its Title, and add +to it an item stating at least the title, year, new authors, and +publisher of the Modified Version as given on the Title Page. If +there is no section Entitled \*(L"History\*(R" in the Document, create one +stating the title, year, authors, and publisher of the Document as +given on its Title Page, then add an item describing the Modified +Version as stated in the previous sentence. +.IP "J." 4 +.IX Item "J." +Preserve the network location, if any, given in the Document for +public access to a Transparent copy of the Document, and likewise +the network locations given in the Document for previous versions +it was based on. These may be placed in the \*(L"History\*(R" section. +You may omit a network location for a work that was published at +least four years before the Document itself, or if the original +publisher of the version it refers to gives permission. +.IP "K." 4 +.IX Item "K." +For any section Entitled \*(L"Acknowledgements\*(R" or \*(L"Dedications\*(R", Preserve +the Title of the section, and preserve in the section all the +substance and tone of each of the contributor acknowledgements and/or +dedications given therein. +.IP "L." 4 +.IX Item "L." +Preserve all the Invariant Sections of the Document, +unaltered in their text and in their titles. Section numbers +or the equivalent are not considered part of the section titles. +.IP "M." 4 +.IX Item "M." +Delete any section Entitled \*(L"Endorsements\*(R". Such a section +may not be included in the Modified Version. +.IP "N." 4 +.IX Item "N." +Do not retitle any existing section to be Entitled \*(L"Endorsements\*(R" or +to conflict in title with any Invariant Section. +.IP "O." 4 +.IX Item "O." +Preserve any Warranty Disclaimers. +.RE +.RS 4 +.Sp +If the Modified Version includes new front-matter sections or +appendices that qualify as Secondary Sections and contain no material +copied from the Document, you may at your option designate some or all +of these sections as invariant. To do this, add their titles to the +list of Invariant Sections in the Modified Version's license notice. +These titles must be distinct from any other section titles. +.Sp +You may add a section Entitled \*(L"Endorsements\*(R", provided it contains +nothing but endorsements of your Modified Version by various +parties\-\-\-for example, statements of peer review or that the text has +been approved by an organization as the authoritative definition of a +standard. +.Sp +You may add a passage of up to five words as a Front-Cover Text, and a +passage of up to 25 words as a Back-Cover Text, to the end of the list +of Cover Texts in the Modified Version. Only one passage of +Front-Cover Text and one of Back-Cover Text may be added by (or +through arrangements made by) any one entity. If the Document already +includes a cover text for the same cover, previously added by you or +by arrangement made by the same entity you are acting on behalf of, +you may not add another; but you may replace the old one, on explicit +permission from the previous publisher that added the old one. +.Sp +The author(s) and publisher(s) of the Document do not by this License +give permission to use their names for publicity for or to assert or +imply endorsement of any Modified Version. +.RE +.IP "5." 4 +.IX Item "5." +\&\s-1COMBINING\s0 \s-1DOCUMENTS\s0 +.Sp +You may combine the Document with other documents released under this +License, under the terms defined in section 4 above for modified +versions, provided that you include in the combination all of the +Invariant Sections of all of the original documents, unmodified, and +list them all as Invariant Sections of your combined work in its +license notice, and that you preserve all their Warranty Disclaimers. +.Sp +The combined work need only contain one copy of this License, and +multiple identical Invariant Sections may be replaced with a single +copy. If there are multiple Invariant Sections with the same name but +different contents, make the title of each such section unique by +adding at the end of it, in parentheses, the name of the original +author or publisher of that section if known, or else a unique number. +Make the same adjustment to the section titles in the list of +Invariant Sections in the license notice of the combined work. +.Sp +In the combination, you must combine any sections Entitled \*(L"History\*(R" +in the various original documents, forming one section Entitled +\&\*(L"History\*(R"; likewise combine any sections Entitled \*(L"Acknowledgements\*(R", +and any sections Entitled \*(L"Dedications\*(R". You must delete all +sections Entitled \*(L"Endorsements.\*(R" +.IP "6." 4 +.IX Item "6." +\&\s-1COLLECTIONS\s0 \s-1OF\s0 \s-1DOCUMENTS\s0 +.Sp +You may make a collection consisting of the Document and other documents +released under this License, and replace the individual copies of this +License in the various documents with a single copy that is included in +the collection, provided that you follow the rules of this License for +verbatim copying of each of the documents in all other respects. +.Sp +You may extract a single document from such a collection, and distribute +it individually under this License, provided you insert a copy of this +License into the extracted document, and follow this License in all +other respects regarding verbatim copying of that document. +.IP "7." 4 +.IX Item "7." +\&\s-1AGGREGATION\s0 \s-1WITH\s0 \s-1INDEPENDENT\s0 \s-1WORKS\s0 +.Sp +A compilation of the Document or its derivatives with other separate +and independent documents or works, in or on a volume of a storage or +distribution medium, is called an \*(L"aggregate\*(R" if the copyright +resulting from the compilation is not used to limit the legal rights +of the compilation's users beyond what the individual works permit. +When the Document is included in an aggregate, this License does not +apply to the other works in the aggregate which are not themselves +derivative works of the Document. +.Sp +If the Cover Text requirement of section 3 is applicable to these +copies of the Document, then if the Document is less than one half of +the entire aggregate, the Document's Cover Texts may be placed on +covers that bracket the Document within the aggregate, or the +electronic equivalent of covers if the Document is in electronic form. +Otherwise they must appear on printed covers that bracket the whole +aggregate. +.IP "8." 4 +.IX Item "8." +\&\s-1TRANSLATION\s0 +.Sp +Translation is considered a kind of modification, so you may +distribute translations of the Document under the terms of section 4. +Replacing Invariant Sections with translations requires special +permission from their copyright holders, but you may include +translations of some or all Invariant Sections in addition to the +original versions of these Invariant Sections. You may include a +translation of this License, and all the license notices in the +Document, and any Warranty Disclaimers, provided that you also include +the original English version of this License and the original versions +of those notices and disclaimers. In case of a disagreement between +the translation and the original version of this License or a notice +or disclaimer, the original version will prevail. +.Sp +If a section in the Document is Entitled \*(L"Acknowledgements\*(R", +\&\*(L"Dedications\*(R", or \*(L"History\*(R", the requirement (section 4) to Preserve +its Title (section 1) will typically require changing the actual +title. +.IP "9." 4 +.IX Item "9." +\&\s-1TERMINATION\s0 +.Sp +You may not copy, modify, sublicense, or distribute the Document +except as expressly provided under this License. Any attempt +otherwise to copy, modify, sublicense, or distribute it is void, and +will automatically terminate your rights under this License. +.Sp +However, if you cease all violation of this License, then your license +from a particular copyright holder is reinstated (a) provisionally, +unless and until the copyright holder explicitly and finally +terminates your license, and (b) permanently, if the copyright holder +fails to notify you of the violation by some reasonable means prior to +60 days after the cessation. +.Sp +Moreover, your license from a particular copyright holder is +reinstated permanently if the copyright holder notifies you of the +violation by some reasonable means, this is the first time you have +received notice of violation of this License (for any work) from that +copyright holder, and you cure the violation prior to 30 days after +your receipt of the notice. +.Sp +Termination of your rights under this section does not terminate the +licenses of parties who have received copies or rights from you under +this License. If your rights have been terminated and not permanently +reinstated, receipt of a copy of some or all of the same material does +not give you any rights to use it. +.IP "10." 4 +.IX Item "10." +\&\s-1FUTURE\s0 \s-1REVISIONS\s0 \s-1OF\s0 \s-1THIS\s0 \s-1LICENSE\s0 +.Sp +The Free Software Foundation may publish new, revised versions +of the \s-1GNU\s0 Free Documentation License from time to time. Such new +versions will be similar in spirit to the present version, but may +differ in detail to address new problems or concerns. See +<\fBhttp://www.gnu.org/copyleft/\fR>. +.Sp +Each version of the License is given a distinguishing version number. +If the Document specifies that a particular numbered version of this +License \*(L"or any later version\*(R" applies to it, you have the option of +following the terms and conditions either of that specified version or +of any later version that has been published (not as a draft) by the +Free Software Foundation. If the Document does not specify a version +number of this License, you may choose any version ever published (not +as a draft) by the Free Software Foundation. If the Document +specifies that a proxy can decide which future versions of this +License can be used, that proxy's public statement of acceptance of a +version permanently authorizes you to choose that version for the +Document. +.IP "11." 4 +.IX Item "11." +\&\s-1RELICENSING\s0 +.Sp +\&\*(L"Massive Multiauthor Collaboration Site\*(R" (or \*(L"\s-1MMC\s0 Site\*(R") means any +World Wide Web server that publishes copyrightable works and also +provides prominent facilities for anybody to edit those works. A +public wiki that anybody can edit is an example of such a server. A +\&\*(L"Massive Multiauthor Collaboration\*(R" (or \*(L"\s-1MMC\s0\*(R") contained in the +site means any set of copyrightable works thus published on the \s-1MMC\s0 +site. +.Sp +\&\*(L"CC-BY-SA\*(R" means the Creative Commons Attribution-Share Alike 3.0 +license published by Creative Commons Corporation, a not-for-profit +corporation with a principal place of business in San Francisco, +California, as well as future copyleft versions of that license +published by that same organization. +.Sp +\&\*(L"Incorporate\*(R" means to publish or republish a Document, in whole or +in part, as part of another Document. +.Sp +An \s-1MMC\s0 is \*(L"eligible for relicensing\*(R" if it is licensed under this +License, and if all works that were first published under this License +somewhere other than this \s-1MMC\s0, and subsequently incorporated in whole +or in part into the \s-1MMC\s0, (1) had no cover texts or invariant sections, +and (2) were thus incorporated prior to November 1, 2008. +.Sp +The operator of an \s-1MMC\s0 Site may republish an \s-1MMC\s0 contained in the site +under CC-BY-SA on the same site at any time before August 1, 2009, +provided the \s-1MMC\s0 is eligible for relicensing. +.SS "\s-1ADDENDUM:\s0 How to use this License for your documents" +.IX Subsection "ADDENDUM: How to use this License for your documents" +To use this License in a document you have written, include a copy of +the License in the document and put the following copyright and +license notices just after the title page: +.PP +.Vb 7 +\& Copyright (C) <year> <your name>. +\& Permission is granted to copy, distribute and/or modify this document +\& under the terms of the GNU Free Documentation License, Version 1.3 +\& or any later version published by the Free Software Foundation; +\& with no Invariant Sections, no Front\-Cover Texts, and no Back\-Cover +\& Texts. A copy of the license is included in the section entitled "GNU +\& Free Documentation License". +.Ve +.PP +If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts, +replace the \*(L"with...Texts.\*(R" line with this: +.PP +.Vb 3 +\& with the Invariant Sections being <list their titles>, with +\& the Front\-Cover Texts being <list>, and with the Back\-Cover Texts +\& being <list>. +.Ve +.PP +If you have Invariant Sections without Cover Texts, or some other +combination of the three, merge those two alternatives to suit the +situation. +.PP +If your document contains nontrivial examples of program code, we +recommend releasing these examples in parallel under your choice of +free software license, such as the \s-1GNU\s0 General Public License, +to permit their use in free software. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fIgpl\fR\|(7), \fIfsf\-funding\fR\|(7). +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. +<\fBhttp://fsf.org/\fR> +.PP +Everyone is permitted to copy and distribute verbatim copies +of this license document, but changing it is not allowed. diff --git a/share/man/man7/gpl.7 b/share/man/man7/gpl.7 new file mode 100644 index 0000000..18793ba --- /dev/null +++ b/share/man/man7/gpl.7 @@ -0,0 +1,841 @@ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. Capital omega is used to do unbreakable dashes and +.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, +.\" nothing in troff, for use with C<>. +.tr \(*W- +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.ie \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.el \{\ +. de IX +.. +.\} +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "GPL 7" +.TH GPL 7 "2012-01-06" "gcc-4.6.x-google" "GNU" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +gpl \- GNU General Public License +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +.SS "\s-1GNU\s0 General Public License" +.IX Subsection "GNU General Public License" +.SS "Version 3, 29 June 2007" +.IX Subsection "Version 3, 29 June 2007" +.Vb 1 +\& Copyright (c) 2007 Free Software Foundation, Inc. <http://fsf.org/> +\& +\& Everyone is permitted to copy and distribute verbatim copies of this +\& license document, but changing it is not allowed. +.Ve +.SS "Preamble" +.IX Subsection "Preamble" +The \s-1GNU\s0 General Public License is a free, copyleft license for +software and other kinds of works. +.PP +The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. By contrast, +the \s-1GNU\s0 General Public License is intended to guarantee your freedom +to share and change all versions of a program\*(--to make sure it remains +free software for all its users. We, the Free Software Foundation, +use the \s-1GNU\s0 General Public License for most of our software; it +applies also to any other work released this way by its authors. You +can apply it to your programs, too. +.PP +When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +them if you wish), that you receive source code or can get it if you +want it, that you can change the software or use pieces of it in new +free programs, and that you know you can do these things. +.PP +To protect your rights, we need to prevent others from denying you +these rights or asking you to surrender the rights. Therefore, you +have certain responsibilities if you distribute copies of the +software, or if you modify it: responsibilities to respect the freedom +of others. +.PP +For example, if you distribute copies of such a program, whether +gratis or for a fee, you must pass on to the recipients the same +freedoms that you received. You must make sure that they, too, +receive or can get the source code. And you must show them these +terms so they know their rights. +.PP +Developers that use the \s-1GNU\s0 \s-1GPL\s0 protect your rights with two steps: +(1) assert copyright on the software, and (2) offer you this License +giving you legal permission to copy, distribute and/or modify it. +.PP +For the developers' and authors' protection, the \s-1GPL\s0 clearly explains +that there is no warranty for this free software. For both users' and +authors' sake, the \s-1GPL\s0 requires that modified versions be marked as +changed, so that their problems will not be attributed erroneously to +authors of previous versions. +.PP +Some devices are designed to deny users access to install or run +modified versions of the software inside them, although the +manufacturer can do so. This is fundamentally incompatible with the +aim of protecting users' freedom to change the software. The +systematic pattern of such abuse occurs in the area of products for +individuals to use, which is precisely where it is most unacceptable. +Therefore, we have designed this version of the \s-1GPL\s0 to prohibit the +practice for those products. If such problems arise substantially in +other domains, we stand ready to extend this provision to those +domains in future versions of the \s-1GPL\s0, as needed to protect the +freedom of users. +.PP +Finally, every program is threatened constantly by software patents. +States should not allow patents to restrict development and use of +software on general-purpose computers, but in those that do, we wish +to avoid the special danger that patents applied to a free program +could make it effectively proprietary. To prevent this, the \s-1GPL\s0 +assures that patents cannot be used to render the program non-free. +.PP +The precise terms and conditions for copying, distribution and +modification follow. +.SS "\s-1TERMS\s0 \s-1AND\s0 \s-1CONDITIONS\s0" +.IX Subsection "TERMS AND CONDITIONS" +.IP "0. Definitions." 4 +.IX Item "0. Definitions." +\&\*(L"This License\*(R" refers to version 3 of the \s-1GNU\s0 General Public License. +.Sp +\&\*(L"Copyright\*(R" also means copyright-like laws that apply to other kinds +of works, such as semiconductor masks. +.Sp +\&\*(L"The Program\*(R" refers to any copyrightable work licensed under this +License. Each licensee is addressed as \*(L"you\*(R". \*(L"Licensees\*(R" and +\&\*(L"recipients\*(R" may be individuals or organizations. +.Sp +To \*(L"modify\*(R" a work means to copy from or adapt all or part of the work +in a fashion requiring copyright permission, other than the making of +an exact copy. The resulting work is called a \*(L"modified version\*(R" of +the earlier work or a work \*(L"based on\*(R" the earlier work. +.Sp +A \*(L"covered work\*(R" means either the unmodified Program or a work based +on the Program. +.Sp +To \*(L"propagate\*(R" a work means to do anything with it that, without +permission, would make you directly or secondarily liable for +infringement under applicable copyright law, except executing it on a +computer or modifying a private copy. Propagation includes copying, +distribution (with or without modification), making available to the +public, and in some countries other activities as well. +.Sp +To \*(L"convey\*(R" a work means any kind of propagation that enables other +parties to make or receive copies. Mere interaction with a user +through a computer network, with no transfer of a copy, is not +conveying. +.Sp +An interactive user interface displays \*(L"Appropriate Legal Notices\*(R" to +the extent that it includes a convenient and prominently visible +feature that (1) displays an appropriate copyright notice, and (2) +tells the user that there is no warranty for the work (except to the +extent that warranties are provided), that licensees may convey the +work under this License, and how to view a copy of this License. If +the interface presents a list of user commands or options, such as a +menu, a prominent item in the list meets this criterion. +.IP "1. Source Code." 4 +.IX Item "1. Source Code." +The \*(L"source code\*(R" for a work means the preferred form of the work for +making modifications to it. \*(L"Object code\*(R" means any non-source form +of a work. +.Sp +A \*(L"Standard Interface\*(R" means an interface that either is an official +standard defined by a recognized standards body, or, in the case of +interfaces specified for a particular programming language, one that +is widely used among developers working in that language. +.Sp +The \*(L"System Libraries\*(R" of an executable work include anything, other +than the work as a whole, that (a) is included in the normal form of +packaging a Major Component, but which is not part of that Major +Component, and (b) serves only to enable use of the work with that +Major Component, or to implement a Standard Interface for which an +implementation is available to the public in source code form. A +\&\*(L"Major Component\*(R", in this context, means a major essential component +(kernel, window system, and so on) of the specific operating system +(if any) on which the executable work runs, or a compiler used to +produce the work, or an object code interpreter used to run it. +.Sp +The \*(L"Corresponding Source\*(R" for a work in object code form means all +the source code needed to generate, install, and (for an executable +work) run the object code and to modify the work, including scripts to +control those activities. However, it does not include the work's +System Libraries, or general-purpose tools or generally available free +programs which are used unmodified in performing those activities but +which are not part of the work. For example, Corresponding Source +includes interface definition files associated with source files for +the work, and the source code for shared libraries and dynamically +linked subprograms that the work is specifically designed to require, +such as by intimate data communication or control flow between those +subprograms and other parts of the work. +.Sp +The Corresponding Source need not include anything that users can +regenerate automatically from other parts of the Corresponding Source. +.Sp +The Corresponding Source for a work in source code form is that same +work. +.IP "2. Basic Permissions." 4 +.IX Item "2. Basic Permissions." +All rights granted under this License are granted for the term of +copyright on the Program, and are irrevocable provided the stated +conditions are met. This License explicitly affirms your unlimited +permission to run the unmodified Program. The output from running a +covered work is covered by this License only if the output, given its +content, constitutes a covered work. This License acknowledges your +rights of fair use or other equivalent, as provided by copyright law. +.Sp +You may make, run and propagate covered works that you do not convey, +without conditions so long as your license otherwise remains in force. +You may convey covered works to others for the sole purpose of having +them make modifications exclusively for you, or provide you with +facilities for running those works, provided that you comply with the +terms of this License in conveying all material for which you do not +control copyright. Those thus making or running the covered works for +you must do so exclusively on your behalf, under your direction and +control, on terms that prohibit them from making any copies of your +copyrighted material outside their relationship with you. +.Sp +Conveying under any other circumstances is permitted solely under the +conditions stated below. Sublicensing is not allowed; section 10 +makes it unnecessary. +.IP "3. Protecting Users' Legal Rights From Anti-Circumvention Law." 4 +.IX Item "3. Protecting Users' Legal Rights From Anti-Circumvention Law." +No covered work shall be deemed part of an effective technological +measure under any applicable law fulfilling obligations under article +11 of the \s-1WIPO\s0 copyright treaty adopted on 20 December 1996, or +similar laws prohibiting or restricting circumvention of such +measures. +.Sp +When you convey a covered work, you waive any legal power to forbid +circumvention of technological measures to the extent such +circumvention is effected by exercising rights under this License with +respect to the covered work, and you disclaim any intention to limit +operation or modification of the work as a means of enforcing, against +the work's users, your or third parties' legal rights to forbid +circumvention of technological measures. +.IP "4. Conveying Verbatim Copies." 4 +.IX Item "4. Conveying Verbatim Copies." +You may convey verbatim copies of the Program's source code as you +receive it, in any medium, provided that you conspicuously and +appropriately publish on each copy an appropriate copyright notice; +keep intact all notices stating that this License and any +non-permissive terms added in accord with section 7 apply to the code; +keep intact all notices of the absence of any warranty; and give all +recipients a copy of this License along with the Program. +.Sp +You may charge any price or no price for each copy that you convey, +and you may offer support or warranty protection for a fee. +.IP "5. Conveying Modified Source Versions." 4 +.IX Item "5. Conveying Modified Source Versions." +You may convey a work based on the Program, or the modifications to +produce it from the Program, in the form of source code under the +terms of section 4, provided that you also meet all of these +conditions: +.RS 4 +.IP "a." 4 +.IX Item "a." +The work must carry prominent notices stating that you modified it, +and giving a relevant date. +.IP "b." 4 +.IX Item "b." +The work must carry prominent notices stating that it is released +under this License and any conditions added under section 7. This +requirement modifies the requirement in section 4 to \*(L"keep intact all +notices\*(R". +.IP "c." 4 +.IX Item "c." +You must license the entire work, as a whole, under this License to +anyone who comes into possession of a copy. This License will +therefore apply, along with any applicable section 7 additional terms, +to the whole of the work, and all its parts, regardless of how they +are packaged. This License gives no permission to license the work in +any other way, but it does not invalidate such permission if you have +separately received it. +.IP "d." 4 +.IX Item "d." +If the work has interactive user interfaces, each must display +Appropriate Legal Notices; however, if the Program has interactive +interfaces that do not display Appropriate Legal Notices, your work +need not make them do so. +.RE +.RS 4 +.Sp +A compilation of a covered work with other separate and independent +works, which are not by their nature extensions of the covered work, +and which are not combined with it such as to form a larger program, +in or on a volume of a storage or distribution medium, is called an +\&\*(L"aggregate\*(R" if the compilation and its resulting copyright are not +used to limit the access or legal rights of the compilation's users +beyond what the individual works permit. Inclusion of a covered work +in an aggregate does not cause this License to apply to the other +parts of the aggregate. +.RE +.IP "6. Conveying Non-Source Forms." 4 +.IX Item "6. Conveying Non-Source Forms." +You may convey a covered work in object code form under the terms of +sections 4 and 5, provided that you also convey the machine-readable +Corresponding Source under the terms of this License, in one of these +ways: +.RS 4 +.IP "a." 4 +.IX Item "a." +Convey the object code in, or embodied in, a physical product +(including a physical distribution medium), accompanied by the +Corresponding Source fixed on a durable physical medium customarily +used for software interchange. +.IP "b." 4 +.IX Item "b." +Convey the object code in, or embodied in, a physical product +(including a physical distribution medium), accompanied by a written +offer, valid for at least three years and valid for as long as you +offer spare parts or customer support for that product model, to give +anyone who possesses the object code either (1) a copy of the +Corresponding Source for all the software in the product that is +covered by this License, on a durable physical medium customarily used +for software interchange, for a price no more than your reasonable +cost of physically performing this conveying of source, or (2) access +to copy the Corresponding Source from a network server at no charge. +.IP "c." 4 +.IX Item "c." +Convey individual copies of the object code with a copy of the written +offer to provide the Corresponding Source. This alternative is +allowed only occasionally and noncommercially, and only if you +received the object code with such an offer, in accord with subsection +6b. +.IP "d." 4 +.IX Item "d." +Convey the object code by offering access from a designated place +(gratis or for a charge), and offer equivalent access to the +Corresponding Source in the same way through the same place at no +further charge. You need not require recipients to copy the +Corresponding Source along with the object code. If the place to copy +the object code is a network server, the Corresponding Source may be +on a different server (operated by you or a third party) that supports +equivalent copying facilities, provided you maintain clear directions +next to the object code saying where to find the Corresponding Source. +Regardless of what server hosts the Corresponding Source, you remain +obligated to ensure that it is available for as long as needed to +satisfy these requirements. +.IP "e." 4 +.IX Item "e." +Convey the object code using peer-to-peer transmission, provided you +inform other peers where the object code and Corresponding Source of +the work are being offered to the general public at no charge under +subsection 6d. +.RE +.RS 4 +.Sp +A separable portion of the object code, whose source code is excluded +from the Corresponding Source as a System Library, need not be +included in conveying the object code work. +.Sp +A \*(L"User Product\*(R" is either (1) a \*(L"consumer product\*(R", which means any +tangible personal property which is normally used for personal, +family, or household purposes, or (2) anything designed or sold for +incorporation into a dwelling. In determining whether a product is a +consumer product, doubtful cases shall be resolved in favor of +coverage. For a particular product received by a particular user, +\&\*(L"normally used\*(R" refers to a typical or common use of that class of +product, regardless of the status of the particular user or of the way +in which the particular user actually uses, or expects or is expected +to use, the product. A product is a consumer product regardless of +whether the product has substantial commercial, industrial or +non-consumer uses, unless such uses represent the only significant +mode of use of the product. +.Sp +\&\*(L"Installation Information\*(R" for a User Product means any methods, +procedures, authorization keys, or other information required to +install and execute modified versions of a covered work in that User +Product from a modified version of its Corresponding Source. The +information must suffice to ensure that the continued functioning of +the modified object code is in no case prevented or interfered with +solely because modification has been made. +.Sp +If you convey an object code work under this section in, or with, or +specifically for use in, a User Product, and the conveying occurs as +part of a transaction in which the right of possession and use of the +User Product is transferred to the recipient in perpetuity or for a +fixed term (regardless of how the transaction is characterized), the +Corresponding Source conveyed under this section must be accompanied +by the Installation Information. But this requirement does not apply +if neither you nor any third party retains the ability to install +modified object code on the User Product (for example, the work has +been installed in \s-1ROM\s0). +.Sp +The requirement to provide Installation Information does not include a +requirement to continue to provide support service, warranty, or +updates for a work that has been modified or installed by the +recipient, or for the User Product in which it has been modified or +installed. Access to a network may be denied when the modification +itself materially and adversely affects the operation of the network +or violates the rules and protocols for communication across the +network. +.Sp +Corresponding Source conveyed, and Installation Information provided, +in accord with this section must be in a format that is publicly +documented (and with an implementation available to the public in +source code form), and must require no special password or key for +unpacking, reading or copying. +.RE +.IP "7. Additional Terms." 4 +.IX Item "7. Additional Terms." +\&\*(L"Additional permissions\*(R" are terms that supplement the terms of this +License by making exceptions from one or more of its conditions. +Additional permissions that are applicable to the entire Program shall +be treated as though they were included in this License, to the extent +that they are valid under applicable law. If additional permissions +apply only to part of the Program, that part may be used separately +under those permissions, but the entire Program remains governed by +this License without regard to the additional permissions. +.Sp +When you convey a copy of a covered work, you may at your option +remove any additional permissions from that copy, or from any part of +it. (Additional permissions may be written to require their own +removal in certain cases when you modify the work.) You may place +additional permissions on material, added by you to a covered work, +for which you have or can give appropriate copyright permission. +.Sp +Notwithstanding any other provision of this License, for material you +add to a covered work, you may (if authorized by the copyright holders +of that material) supplement the terms of this License with terms: +.RS 4 +.IP "a." 4 +.IX Item "a." +Disclaiming warranty or limiting liability differently from the terms +of sections 15 and 16 of this License; or +.IP "b." 4 +.IX Item "b." +Requiring preservation of specified reasonable legal notices or author +attributions in that material or in the Appropriate Legal Notices +displayed by works containing it; or +.IP "c." 4 +.IX Item "c." +Prohibiting misrepresentation of the origin of that material, or +requiring that modified versions of such material be marked in +reasonable ways as different from the original version; or +.IP "d." 4 +.IX Item "d." +Limiting the use for publicity purposes of names of licensors or +authors of the material; or +.IP "e." 4 +.IX Item "e." +Declining to grant rights under trademark law for use of some trade +names, trademarks, or service marks; or +.IP "f." 4 +.IX Item "f." +Requiring indemnification of licensors and authors of that material by +anyone who conveys the material (or modified versions of it) with +contractual assumptions of liability to the recipient, for any +liability that these contractual assumptions directly impose on those +licensors and authors. +.RE +.RS 4 +.Sp +All other non-permissive additional terms are considered \*(L"further +restrictions\*(R" within the meaning of section 10. If the Program as you +received it, or any part of it, contains a notice stating that it is +governed by this License along with a term that is a further +restriction, you may remove that term. If a license document contains +a further restriction but permits relicensing or conveying under this +License, you may add to a covered work material governed by the terms +of that license document, provided that the further restriction does +not survive such relicensing or conveying. +.Sp +If you add terms to a covered work in accord with this section, you +must place, in the relevant source files, a statement of the +additional terms that apply to those files, or a notice indicating +where to find the applicable terms. +.Sp +Additional terms, permissive or non-permissive, may be stated in the +form of a separately written license, or stated as exceptions; the +above requirements apply either way. +.RE +.IP "8. Termination." 4 +.IX Item "8. Termination." +You may not propagate or modify a covered work except as expressly +provided under this License. Any attempt otherwise to propagate or +modify it is void, and will automatically terminate your rights under +this License (including any patent licenses granted under the third +paragraph of section 11). +.Sp +However, if you cease all violation of this License, then your license +from a particular copyright holder is reinstated (a) provisionally, +unless and until the copyright holder explicitly and finally +terminates your license, and (b) permanently, if the copyright holder +fails to notify you of the violation by some reasonable means prior to +60 days after the cessation. +.Sp +Moreover, your license from a particular copyright holder is +reinstated permanently if the copyright holder notifies you of the +violation by some reasonable means, this is the first time you have +received notice of violation of this License (for any work) from that +copyright holder, and you cure the violation prior to 30 days after +your receipt of the notice. +.Sp +Termination of your rights under this section does not terminate the +licenses of parties who have received copies or rights from you under +this License. If your rights have been terminated and not permanently +reinstated, you do not qualify to receive new licenses for the same +material under section 10. +.IP "9. Acceptance Not Required for Having Copies." 4 +.IX Item "9. Acceptance Not Required for Having Copies." +You are not required to accept this License in order to receive or run +a copy of the Program. Ancillary propagation of a covered work +occurring solely as a consequence of using peer-to-peer transmission +to receive a copy likewise does not require acceptance. However, +nothing other than this License grants you permission to propagate or +modify any covered work. These actions infringe copyright if you do +not accept this License. Therefore, by modifying or propagating a +covered work, you indicate your acceptance of this License to do so. +.IP "10. Automatic Licensing of Downstream Recipients." 4 +.IX Item "10. Automatic Licensing of Downstream Recipients." +Each time you convey a covered work, the recipient automatically +receives a license from the original licensors, to run, modify and +propagate that work, subject to this License. You are not responsible +for enforcing compliance by third parties with this License. +.Sp +An \*(L"entity transaction\*(R" is a transaction transferring control of an +organization, or substantially all assets of one, or subdividing an +organization, or merging organizations. If propagation of a covered +work results from an entity transaction, each party to that +transaction who receives a copy of the work also receives whatever +licenses to the work the party's predecessor in interest had or could +give under the previous paragraph, plus a right to possession of the +Corresponding Source of the work from the predecessor in interest, if +the predecessor has it or can get it with reasonable efforts. +.Sp +You may not impose any further restrictions on the exercise of the +rights granted or affirmed under this License. For example, you may +not impose a license fee, royalty, or other charge for exercise of +rights granted under this License, and you may not initiate litigation +(including a cross-claim or counterclaim in a lawsuit) alleging that +any patent claim is infringed by making, using, selling, offering for +sale, or importing the Program or any portion of it. +.IP "11. Patents." 4 +.IX Item "11. Patents." +A \*(L"contributor\*(R" is a copyright holder who authorizes use under this +License of the Program or a work on which the Program is based. The +work thus licensed is called the contributor's \*(L"contributor version\*(R". +.Sp +A contributor's \*(L"essential patent claims\*(R" are all patent claims owned +or controlled by the contributor, whether already acquired or +hereafter acquired, that would be infringed by some manner, permitted +by this License, of making, using, or selling its contributor version, +but do not include claims that would be infringed only as a +consequence of further modification of the contributor version. For +purposes of this definition, \*(L"control\*(R" includes the right to grant +patent sublicenses in a manner consistent with the requirements of +this License. +.Sp +Each contributor grants you a non-exclusive, worldwide, royalty-free +patent license under the contributor's essential patent claims, to +make, use, sell, offer for sale, import and otherwise run, modify and +propagate the contents of its contributor version. +.Sp +In the following three paragraphs, a \*(L"patent license\*(R" is any express +agreement or commitment, however denominated, not to enforce a patent +(such as an express permission to practice a patent or covenant not to +sue for patent infringement). To \*(L"grant\*(R" such a patent license to a +party means to make such an agreement or commitment not to enforce a +patent against the party. +.Sp +If you convey a covered work, knowingly relying on a patent license, +and the Corresponding Source of the work is not available for anyone +to copy, free of charge and under the terms of this License, through a +publicly available network server or other readily accessible means, +then you must either (1) cause the Corresponding Source to be so +available, or (2) arrange to deprive yourself of the benefit of the +patent license for this particular work, or (3) arrange, in a manner +consistent with the requirements of this License, to extend the patent +license to downstream recipients. \*(L"Knowingly relying\*(R" means you have +actual knowledge that, but for the patent license, your conveying the +covered work in a country, or your recipient's use of the covered work +in a country, would infringe one or more identifiable patents in that +country that you have reason to believe are valid. +.Sp +If, pursuant to or in connection with a single transaction or +arrangement, you convey, or propagate by procuring conveyance of, a +covered work, and grant a patent license to some of the parties +receiving the covered work authorizing them to use, propagate, modify +or convey a specific copy of the covered work, then the patent license +you grant is automatically extended to all recipients of the covered +work and works based on it. +.Sp +A patent license is \*(L"discriminatory\*(R" if it does not include within the +scope of its coverage, prohibits the exercise of, or is conditioned on +the non-exercise of one or more of the rights that are specifically +granted under this License. You may not convey a covered work if you +are a party to an arrangement with a third party that is in the +business of distributing software, under which you make payment to the +third party based on the extent of your activity of conveying the +work, and under which the third party grants, to any of the parties +who would receive the covered work from you, a discriminatory patent +license (a) in connection with copies of the covered work conveyed by +you (or copies made from those copies), or (b) primarily for and in +connection with specific products or compilations that contain the +covered work, unless you entered into that arrangement, or that patent +license was granted, prior to 28 March 2007. +.Sp +Nothing in this License shall be construed as excluding or limiting +any implied license or other defenses to infringement that may +otherwise be available to you under applicable patent law. +.IP "12. No Surrender of Others' Freedom." 4 +.IX Item "12. No Surrender of Others' Freedom." +If conditions are imposed on you (whether by court order, agreement or +otherwise) that contradict the conditions of this License, they do not +excuse you from the conditions of this License. If you cannot convey +a covered work so as to satisfy simultaneously your obligations under +this License and any other pertinent obligations, then as a +consequence you may not convey it at all. For example, if you agree +to terms that obligate you to collect a royalty for further conveying +from those to whom you convey the Program, the only way you could +satisfy both those terms and this License would be to refrain entirely +from conveying the Program. +.IP "13. Use with the \s-1GNU\s0 Affero General Public License." 4 +.IX Item "13. Use with the GNU Affero General Public License." +Notwithstanding any other provision of this License, you have +permission to link or combine any covered work with a work licensed +under version 3 of the \s-1GNU\s0 Affero General Public License into a single +combined work, and to convey the resulting work. The terms of this +License will continue to apply to the part which is the covered work, +but the special requirements of the \s-1GNU\s0 Affero General Public License, +section 13, concerning interaction through a network will apply to the +combination as such. +.IP "14. Revised Versions of this License." 4 +.IX Item "14. Revised Versions of this License." +The Free Software Foundation may publish revised and/or new versions +of the \s-1GNU\s0 General Public License from time to time. Such new +versions will be similar in spirit to the present version, but may +differ in detail to address new problems or concerns. +.Sp +Each version is given a distinguishing version number. If the Program +specifies that a certain numbered version of the \s-1GNU\s0 General Public +License \*(L"or any later version\*(R" applies to it, you have the option of +following the terms and conditions either of that numbered version or +of any later version published by the Free Software Foundation. If +the Program does not specify a version number of the \s-1GNU\s0 General +Public License, you may choose any version ever published by the Free +Software Foundation. +.Sp +If the Program specifies that a proxy can decide which future versions +of the \s-1GNU\s0 General Public License can be used, that proxy's public +statement of acceptance of a version permanently authorizes you to +choose that version for the Program. +.Sp +Later license versions may give you additional or different +permissions. However, no additional obligations are imposed on any +author or copyright holder as a result of your choosing to follow a +later version. +.IP "15. Disclaimer of Warranty." 4 +.IX Item "15. Disclaimer of Warranty." +\&\s-1THERE\s0 \s-1IS\s0 \s-1NO\s0 \s-1WARRANTY\s0 \s-1FOR\s0 \s-1THE\s0 \s-1PROGRAM\s0, \s-1TO\s0 \s-1THE\s0 \s-1EXTENT\s0 \s-1PERMITTED\s0 \s-1BY\s0 +\&\s-1APPLICABLE\s0 \s-1LAW\s0. \s-1EXCEPT\s0 \s-1WHEN\s0 \s-1OTHERWISE\s0 \s-1STATED\s0 \s-1IN\s0 \s-1WRITING\s0 \s-1THE\s0 \s-1COPYRIGHT\s0 +\&\s-1HOLDERS\s0 \s-1AND/OR\s0 \s-1OTHER\s0 \s-1PARTIES\s0 \s-1PROVIDE\s0 \s-1THE\s0 \s-1PROGRAM\s0 \*(L"\s-1AS\s0 \s-1IS\s0\*(R" \s-1WITHOUT\s0 +\&\s-1WARRANTY\s0 \s-1OF\s0 \s-1ANY\s0 \s-1KIND\s0, \s-1EITHER\s0 \s-1EXPRESSED\s0 \s-1OR\s0 \s-1IMPLIED\s0, \s-1INCLUDING\s0, \s-1BUT\s0 \s-1NOT\s0 +\&\s-1LIMITED\s0 \s-1TO\s0, \s-1THE\s0 \s-1IMPLIED\s0 \s-1WARRANTIES\s0 \s-1OF\s0 \s-1MERCHANTABILITY\s0 \s-1AND\s0 \s-1FITNESS\s0 \s-1FOR\s0 +A \s-1PARTICULAR\s0 \s-1PURPOSE\s0. \s-1THE\s0 \s-1ENTIRE\s0 \s-1RISK\s0 \s-1AS\s0 \s-1TO\s0 \s-1THE\s0 \s-1QUALITY\s0 \s-1AND\s0 +\&\s-1PERFORMANCE\s0 \s-1OF\s0 \s-1THE\s0 \s-1PROGRAM\s0 \s-1IS\s0 \s-1WITH\s0 \s-1YOU\s0. \s-1SHOULD\s0 \s-1THE\s0 \s-1PROGRAM\s0 \s-1PROVE\s0 +\&\s-1DEFECTIVE\s0, \s-1YOU\s0 \s-1ASSUME\s0 \s-1THE\s0 \s-1COST\s0 \s-1OF\s0 \s-1ALL\s0 \s-1NECESSARY\s0 \s-1SERVICING\s0, \s-1REPAIR\s0 \s-1OR\s0 +\&\s-1CORRECTION\s0. +.IP "16. Limitation of Liability." 4 +.IX Item "16. Limitation of Liability." +\&\s-1IN\s0 \s-1NO\s0 \s-1EVENT\s0 \s-1UNLESS\s0 \s-1REQUIRED\s0 \s-1BY\s0 \s-1APPLICABLE\s0 \s-1LAW\s0 \s-1OR\s0 \s-1AGREED\s0 \s-1TO\s0 \s-1IN\s0 \s-1WRITING\s0 +\&\s-1WILL\s0 \s-1ANY\s0 \s-1COPYRIGHT\s0 \s-1HOLDER\s0, \s-1OR\s0 \s-1ANY\s0 \s-1OTHER\s0 \s-1PARTY\s0 \s-1WHO\s0 \s-1MODIFIES\s0 \s-1AND/OR\s0 +\&\s-1CONVEYS\s0 \s-1THE\s0 \s-1PROGRAM\s0 \s-1AS\s0 \s-1PERMITTED\s0 \s-1ABOVE\s0, \s-1BE\s0 \s-1LIABLE\s0 \s-1TO\s0 \s-1YOU\s0 \s-1FOR\s0 \s-1DAMAGES\s0, +\&\s-1INCLUDING\s0 \s-1ANY\s0 \s-1GENERAL\s0, \s-1SPECIAL\s0, \s-1INCIDENTAL\s0 \s-1OR\s0 \s-1CONSEQUENTIAL\s0 \s-1DAMAGES\s0 +\&\s-1ARISING\s0 \s-1OUT\s0 \s-1OF\s0 \s-1THE\s0 \s-1USE\s0 \s-1OR\s0 \s-1INABILITY\s0 \s-1TO\s0 \s-1USE\s0 \s-1THE\s0 \s-1PROGRAM\s0 (\s-1INCLUDING\s0 \s-1BUT\s0 +\&\s-1NOT\s0 \s-1LIMITED\s0 \s-1TO\s0 \s-1LOSS\s0 \s-1OF\s0 \s-1DATA\s0 \s-1OR\s0 \s-1DATA\s0 \s-1BEING\s0 \s-1RENDERED\s0 \s-1INACCURATE\s0 \s-1OR\s0 +\&\s-1LOSSES\s0 \s-1SUSTAINED\s0 \s-1BY\s0 \s-1YOU\s0 \s-1OR\s0 \s-1THIRD\s0 \s-1PARTIES\s0 \s-1OR\s0 A \s-1FAILURE\s0 \s-1OF\s0 \s-1THE\s0 \s-1PROGRAM\s0 +\&\s-1TO\s0 \s-1OPERATE\s0 \s-1WITH\s0 \s-1ANY\s0 \s-1OTHER\s0 \s-1PROGRAMS\s0), \s-1EVEN\s0 \s-1IF\s0 \s-1SUCH\s0 \s-1HOLDER\s0 \s-1OR\s0 \s-1OTHER\s0 +\&\s-1PARTY\s0 \s-1HAS\s0 \s-1BEEN\s0 \s-1ADVISED\s0 \s-1OF\s0 \s-1THE\s0 \s-1POSSIBILITY\s0 \s-1OF\s0 \s-1SUCH\s0 \s-1DAMAGES\s0. +.IP "17. Interpretation of Sections 15 and 16." 4 +.IX Item "17. Interpretation of Sections 15 and 16." +If the disclaimer of warranty and limitation of liability provided +above cannot be given local legal effect according to their terms, +reviewing courts shall apply local law that most closely approximates +an absolute waiver of all civil liability in connection with the +Program, unless a warranty or assumption of liability accompanies a +copy of the Program in return for a fee. +.SS "\s-1END\s0 \s-1OF\s0 \s-1TERMS\s0 \s-1AND\s0 \s-1CONDITIONS\s0" +.IX Subsection "END OF TERMS AND CONDITIONS" +.SS "How to Apply These Terms to Your New Programs" +.IX Subsection "How to Apply These Terms to Your New Programs" +If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these +terms. +.PP +To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +state the exclusion of warranty; and each file should have at least +the \*(L"copyright\*(R" line and a pointer to where the full notice is found. +.PP +.Vb 2 +\& <one line to give the program\*(Aqs name and a brief idea of what it does.> +\& Copyright (C) <year> <name of author> +\& +\& This program is free software: you can redistribute it and/or modify +\& it under the terms of the GNU General Public License as published by +\& the Free Software Foundation, either version 3 of the License, or (at +\& your option) any later version. +\& +\& This program is distributed in the hope that it will be useful, but +\& WITHOUT ANY WARRANTY; without even the implied warranty of +\& MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +\& General Public License for more details. +\& +\& You should have received a copy of the GNU General Public License +\& along with this program. If not, see <http://www.gnu.org/licenses/>. +.Ve +.PP +Also add information on how to contact you by electronic and paper mail. +.PP +If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: +.PP +.Vb 4 +\& <program> Copyright (C) <year> <name of author> +\& This program comes with ABSOLUTELY NO WARRANTY; for details type "show w". +\& This is free software, and you are welcome to redistribute it +\& under certain conditions; type "show c" for details. +.Ve +.PP +The hypothetical commands \fBshow w\fR and \fBshow c\fR should show +the appropriate parts of the General Public License. Of course, your +program's commands might be different; for a \s-1GUI\s0 interface, you would +use an \*(L"about box\*(R". +.PP +You should also get your employer (if you work as a programmer) or school, +if any, to sign a \*(L"copyright disclaimer\*(R" for the program, if necessary. +For more information on this, and how to apply and follow the \s-1GNU\s0 \s-1GPL\s0, see +<\fBhttp://www.gnu.org/licenses/\fR>. +.PP +The \s-1GNU\s0 General Public License does not permit incorporating your +program into proprietary programs. If your program is a subroutine +library, you may consider it more useful to permit linking proprietary +applications with the library. If this is what you want to do, use +the \s-1GNU\s0 Lesser General Public License instead of this License. But +first, please read <\fBhttp://www.gnu.org/philosophy/why\-not\-lgpl.html\fR>. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +\&\fIgfdl\fR\|(7), \fIfsf\-funding\fR\|(7). +.SH "COPYRIGHT" +.IX Header "COPYRIGHT" +Copyright (c) 2007 Free Software Foundation, Inc. +.PP +Everyone is permitted to copy and distribute verbatim copies of this +license document, but changing it is not allowed. |