diff options
author | Yabin Cui <yabinc@google.com> | 2017-05-09 17:31:05 -0700 |
---|---|---|
committer | Yabin Cui <yabinc@google.com> | 2017-05-23 16:53:39 -0700 |
commit | 43301382dadbb57fb48036df44e0d5d2ec370338 (patch) | |
tree | 1de3194312259ca2823b065de0f07140f61c952f | |
parent | adbce4d3b7eb6f4c7c78084feefc208fc8a768fe (diff) | |
download | extras-43301382dadbb57fb48036df44e0d5d2ec370338.tar.gz |
simpleperf: support raw event types.
Provide interface to access event numbers provided by ARMv8 PMU v3.
Make event types case insensitive to make typing easier.
Bug: http://b/38043209
Test: run simpleperf_unit_test.
Change-Id: I49073acbc4d8c9abeafff93e25133664c84a0e9c
-rw-r--r-- | simpleperf/cmd_list.cpp | 59 | ||||
-rw-r--r-- | simpleperf/cmd_stat.cpp | 8 | ||||
-rw-r--r-- | simpleperf/event_type.cpp | 8 | ||||
-rw-r--r-- | simpleperf/event_type.h | 8 | ||||
-rw-r--r-- | simpleperf/event_type_table.h | 171 | ||||
-rwxr-xr-x | simpleperf/generate_event_type_table.py | 80 |
6 files changed, 256 insertions, 78 deletions
diff --git a/simpleperf/cmd_list.cpp b/simpleperf/cmd_list.cpp index 0248aa97..7aa0c966 100644 --- a/simpleperf/cmd_list.cpp +++ b/simpleperf/cmd_list.cpp @@ -20,6 +20,7 @@ #include <vector> #include <android-base/logging.h> +#include <android-base/test_utils.h> #include "command.h" #include "environment.h" @@ -27,17 +28,60 @@ #include "event_fd.h" #include "event_type.h" +static bool IsEventTypeSupported(const EventType& event_type) { + if (event_type.type != PERF_TYPE_RAW) { + perf_event_attr attr = CreateDefaultPerfEventAttr(event_type); + // Exclude kernel to list supported events even when + // /proc/sys/kernel/perf_event_paranoid is 2. + attr.exclude_kernel = 1; + return IsEventAttrSupported(attr); + } + if (event_type.limited_arch == "arm" && GetBuildArch() != ARCH_ARM && + GetBuildArch() != ARCH_ARM64) { + return false; + } + // Because the kernel may not check whether the raw event is supported by the cpu pmu. + // We can't decide whether the raw event is supported by calling perf_event_open(). + // Instead, we can check if it can collect some real number. + perf_event_attr attr = CreateDefaultPerfEventAttr(event_type); + std::unique_ptr<EventFd> event_fd = EventFd::OpenEventFile(attr, gettid(), -1, nullptr); + if (event_fd == nullptr) { + return false; + } + auto work_function = []() { + TemporaryFile tmpfile; + FILE* fp = fopen(tmpfile.path, "w"); + if (fp == nullptr) { + return; + } + for (int i = 0; i < 10; ++i) { + fprintf(fp, "output some data\n"); + } + fclose(fp); + }; + work_function(); + PerfCounter counter; + if (!event_fd->ReadCounter(&counter)) { + return false; + } + return (counter.value != 0u); +} + static void PrintEventTypesOfType(uint32_t type, const std::string& type_name, const std::vector<EventType>& event_types) { printf("List of %s:\n", type_name.c_str()); + if (type == PERF_TYPE_RAW && (GetBuildArch() == ARCH_ARM || GetBuildArch() == ARCH_ARM64)) { + printf(" # Please refer to PMU event numbers listed in ARMv8 manual for details.\n"); + printf(" # A possible link is https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile.\n"); + } for (auto& event_type : event_types) { if (event_type.type == type) { - perf_event_attr attr = CreateDefaultPerfEventAttr(event_type); - // Exclude kernel to list supported events even when - // /proc/sys/kernel/perf_event_paranoid is 2. - attr.exclude_kernel = 1; - if (IsEventAttrSupported(attr)) { - printf(" %s\n", event_type.name.c_str()); + if (IsEventTypeSupported(event_type)) { + printf(" %s", event_type.name.c_str()); + if (!event_type.description.empty()) { + printf("\t\t# %s", event_type.description.c_str()); + } + printf("\n"); } } } @@ -48,7 +92,7 @@ class ListCommand : public Command { public: ListCommand() : Command("list", "list available event types", - "Usage: simpleperf list [hw|sw|cache|tracepoint]\n" + "Usage: simpleperf list [hw|sw|cache|raw|tracepoint]\n" " List all available perf events on this machine.\n") { } @@ -64,6 +108,7 @@ bool ListCommand::Run(const std::vector<std::string>& args) { {"hw", {PERF_TYPE_HARDWARE, "hardware events"}}, {"sw", {PERF_TYPE_SOFTWARE, "software events"}}, {"cache", {PERF_TYPE_HW_CACHE, "hw-cache events"}}, + {"raw", {PERF_TYPE_RAW, "raw events provided by cpu pmu"}}, {"tracepoint", {PERF_TYPE_TRACEPOINT, "tracepoint events"}}, {"user-space-sampler", {SIMPLEPERF_TYPE_USER_SPACE_SAMPLERS, "user-space samplers"}}, }; diff --git a/simpleperf/cmd_stat.cpp b/simpleperf/cmd_stat.cpp index cdd5593a..a0929bcf 100644 --- a/simpleperf/cmd_stat.cpp +++ b/simpleperf/cmd_stat.cpp @@ -238,6 +238,14 @@ class CounterSummaries { sap_mid); } } + if (android::base::EndsWith(s.type_name, "-refill")) { + std::string other_name = s.type_name.substr(0, s.type_name.size() - strlen("-refill")); + const CounterSummary* other = FindSummary(other_name, s.modifier); + if (other != nullptr && other->IsMonitoredAtTheSameTime(s) && other->count != 0) { + double miss_rate = static_cast<double>(s.count) / other->count; + return android::base::StringPrintf("%f%%%cmiss rate", miss_rate * 100, sap_mid); + } + } double rate = s.count / (duration_in_sec / s.scale); if (rate > 1e9) { return android::base::StringPrintf("%.3lf%cG/sec", rate / 1e9, sap_mid); diff --git a/simpleperf/event_type.cpp b/simpleperf/event_type.cpp index bfa6aacd..a69067d5 100644 --- a/simpleperf/event_type.cpp +++ b/simpleperf/event_type.cpp @@ -23,11 +23,13 @@ #include <android-base/file.h> #include <android-base/logging.h> +#include <android-base/strings.h> #include "event_attr.h" #include "utils.h" -#define EVENT_TYPE_TABLE_ENTRY(name, type, config) {name, type, config}, +#define EVENT_TYPE_TABLE_ENTRY(name, type, config, description, limited_arch) \ + {name, type, config, description, limited_arch}, static const std::vector<EventType> static_event_type_array = { #include "event_type_table.h" @@ -54,7 +56,7 @@ static const std::vector<EventType> GetTracepointEventTypes() { LOG(DEBUG) << "unexpected id '" << id_content << "' in " << id_path; continue; } - result.push_back(EventType(system_name + ":" + event_name, PERF_TYPE_TRACEPOINT, id)); + result.push_back(EventType(system_name + ":" + event_name, PERF_TYPE_TRACEPOINT, id, "", "")); } } std::sort(result.begin(), result.end(), @@ -77,7 +79,7 @@ const std::vector<EventType>& GetAllEventTypes() { const EventType* FindEventTypeByName(const std::string& name) { const EventType* result = nullptr; for (auto& event_type : GetAllEventTypes()) { - if (event_type.name == name) { + if (android::base::EqualsIgnoreCase(event_type.name, name)) { result = &event_type; break; } diff --git a/simpleperf/event_type.h b/simpleperf/event_type.h index a1e401f4..a804b083 100644 --- a/simpleperf/event_type.h +++ b/simpleperf/event_type.h @@ -36,8 +36,10 @@ enum { // the event type is supported by the kernel. struct EventType { - EventType(const std::string& name, uint32_t type, uint64_t config) - : name(name), type(type), config(config) { + EventType(const std::string& name, uint32_t type, uint64_t config, + const std::string& description, const std::string& limited_arch) + : name(name), type(type), config(config), description(description), + limited_arch(limited_arch) { } EventType() : type(0), config(0) { @@ -46,6 +48,8 @@ struct EventType { std::string name; uint32_t type; uint64_t config; + std::string description; + std::string limited_arch; }; const std::vector<EventType>& GetAllEventTypes(); diff --git a/simpleperf/event_type_table.h b/simpleperf/event_type_table.h index 123216c9..3ecf2c80 100644 --- a/simpleperf/event_type_table.h +++ b/simpleperf/event_type_table.h @@ -1,67 +1,116 @@ // This file is auto-generated by generate-event_table.py. -{"cpu-cycles", PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES}, -{"instructions", PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS}, -{"cache-references", PERF_TYPE_HARDWARE, PERF_COUNT_HW_CACHE_REFERENCES}, -{"cache-misses", PERF_TYPE_HARDWARE, PERF_COUNT_HW_CACHE_MISSES}, -{"branch-instructions", PERF_TYPE_HARDWARE, PERF_COUNT_HW_BRANCH_INSTRUCTIONS}, -{"branch-misses", PERF_TYPE_HARDWARE, PERF_COUNT_HW_BRANCH_MISSES}, -{"bus-cycles", PERF_TYPE_HARDWARE, PERF_COUNT_HW_BUS_CYCLES}, -{"stalled-cycles-frontend", PERF_TYPE_HARDWARE, PERF_COUNT_HW_STALLED_CYCLES_FRONTEND}, -{"stalled-cycles-backend", PERF_TYPE_HARDWARE, PERF_COUNT_HW_STALLED_CYCLES_BACKEND}, +EVENT_TYPE_TABLE_ENTRY("cpu-cycles", PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, "", "") +EVENT_TYPE_TABLE_ENTRY("instructions", PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, "", "") +EVENT_TYPE_TABLE_ENTRY("cache-references", PERF_TYPE_HARDWARE, PERF_COUNT_HW_CACHE_REFERENCES, "", "") +EVENT_TYPE_TABLE_ENTRY("cache-misses", PERF_TYPE_HARDWARE, PERF_COUNT_HW_CACHE_MISSES, "", "") +EVENT_TYPE_TABLE_ENTRY("branch-instructions", PERF_TYPE_HARDWARE, PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "", "") +EVENT_TYPE_TABLE_ENTRY("branch-misses", PERF_TYPE_HARDWARE, PERF_COUNT_HW_BRANCH_MISSES, "", "") +EVENT_TYPE_TABLE_ENTRY("bus-cycles", PERF_TYPE_HARDWARE, PERF_COUNT_HW_BUS_CYCLES, "", "") +EVENT_TYPE_TABLE_ENTRY("stalled-cycles-frontend", PERF_TYPE_HARDWARE, PERF_COUNT_HW_STALLED_CYCLES_FRONTEND, "", "") +EVENT_TYPE_TABLE_ENTRY("stalled-cycles-backend", PERF_TYPE_HARDWARE, PERF_COUNT_HW_STALLED_CYCLES_BACKEND, "", "") -{"cpu-clock", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_CPU_CLOCK}, -{"task-clock", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_TASK_CLOCK}, -{"page-faults", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_PAGE_FAULTS}, -{"context-switches", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_CONTEXT_SWITCHES}, -{"cpu-migrations", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_CPU_MIGRATIONS}, -{"minor-faults", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_PAGE_FAULTS_MIN}, -{"major-faults", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_PAGE_FAULTS_MAJ}, -{"alignment-faults", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_ALIGNMENT_FAULTS}, -{"emulation-faults", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_EMULATION_FAULTS}, +EVENT_TYPE_TABLE_ENTRY("cpu-clock", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_CPU_CLOCK, "", "") +EVENT_TYPE_TABLE_ENTRY("task-clock", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_TASK_CLOCK, "", "") +EVENT_TYPE_TABLE_ENTRY("page-faults", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_PAGE_FAULTS, "", "") +EVENT_TYPE_TABLE_ENTRY("context-switches", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_CONTEXT_SWITCHES, "", "") +EVENT_TYPE_TABLE_ENTRY("cpu-migrations", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_CPU_MIGRATIONS, "", "") +EVENT_TYPE_TABLE_ENTRY("minor-faults", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_PAGE_FAULTS_MIN, "", "") +EVENT_TYPE_TABLE_ENTRY("major-faults", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_PAGE_FAULTS_MAJ, "", "") +EVENT_TYPE_TABLE_ENTRY("alignment-faults", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_ALIGNMENT_FAULTS, "", "") +EVENT_TYPE_TABLE_ENTRY("emulation-faults", PERF_TYPE_SOFTWARE, PERF_COUNT_SW_EMULATION_FAULTS, "", "") -{"L1-dcache-loads", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1D) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16))}, -{"L1-dcache-load-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1D) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))}, -{"L1-dcache-stores", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1D) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16))}, -{"L1-dcache-store-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1D) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))}, -{"L1-dcache-prefetches", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1D) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16))}, -{"L1-dcache-prefetch-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1D) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))}, -{"L1-icache-loads", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1I) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16))}, -{"L1-icache-load-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1I) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))}, -{"L1-icache-stores", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1I) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16))}, -{"L1-icache-store-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1I) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))}, -{"L1-icache-prefetches", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1I) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16))}, -{"L1-icache-prefetch-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1I) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))}, -{"LLC-loads", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_LL) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16))}, -{"LLC-load-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_LL) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))}, -{"LLC-stores", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_LL) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16))}, -{"LLC-store-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_LL) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))}, -{"LLC-prefetches", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_LL) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16))}, -{"LLC-prefetch-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_LL) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))}, -{"dTLB-loads", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_DTLB) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16))}, -{"dTLB-load-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_DTLB) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))}, -{"dTLB-stores", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_DTLB) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16))}, -{"dTLB-store-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_DTLB) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))}, -{"dTLB-prefetches", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_DTLB) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16))}, -{"dTLB-prefetch-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_DTLB) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))}, -{"iTLB-loads", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_ITLB) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16))}, -{"iTLB-load-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_ITLB) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))}, -{"iTLB-stores", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_ITLB) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16))}, -{"iTLB-store-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_ITLB) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))}, -{"iTLB-prefetches", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_ITLB) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16))}, -{"iTLB-prefetch-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_ITLB) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))}, -{"branch-loads", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_BPU) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16))}, -{"branch-load-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_BPU) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))}, -{"branch-stores", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_BPU) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16))}, -{"branch-store-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_BPU) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))}, -{"branch-prefetches", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_BPU) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16))}, -{"branch-prefetch-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_BPU) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))}, -{"node-loads", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_NODE) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16))}, -{"node-load-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_NODE) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))}, -{"node-stores", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_NODE) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16))}, -{"node-store-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_NODE) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))}, -{"node-prefetches", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_NODE) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16))}, -{"node-prefetch-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_NODE) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))}, +EVENT_TYPE_TABLE_ENTRY("L1-dcache-loads", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1D) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("L1-dcache-load-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1D) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("L1-dcache-stores", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1D) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("L1-dcache-store-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1D) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("L1-dcache-prefetches", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1D) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("L1-dcache-prefetch-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1D) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("L1-icache-loads", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1I) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("L1-icache-load-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1I) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("L1-icache-stores", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1I) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("L1-icache-store-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1I) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("L1-icache-prefetches", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1I) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("L1-icache-prefetch-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_L1I) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("LLC-loads", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_LL) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("LLC-load-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_LL) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("LLC-stores", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_LL) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("LLC-store-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_LL) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("LLC-prefetches", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_LL) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("LLC-prefetch-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_LL) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("dTLB-loads", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_DTLB) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("dTLB-load-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_DTLB) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("dTLB-stores", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_DTLB) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("dTLB-store-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_DTLB) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("dTLB-prefetches", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_DTLB) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("dTLB-prefetch-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_DTLB) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("iTLB-loads", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_ITLB) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("iTLB-load-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_ITLB) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("iTLB-stores", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_ITLB) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("iTLB-store-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_ITLB) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("iTLB-prefetches", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_ITLB) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("iTLB-prefetch-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_ITLB) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("branch-loads", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_BPU) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("branch-load-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_BPU) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("branch-stores", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_BPU) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("branch-store-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_BPU) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("branch-prefetches", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_BPU) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("branch-prefetch-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_BPU) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("node-loads", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_NODE) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("node-load-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_NODE) | (PERF_COUNT_HW_CACHE_OP_READ << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("node-stores", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_NODE) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("node-store-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_NODE) | (PERF_COUNT_HW_CACHE_OP_WRITE << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("node-prefetches", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_NODE) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)), "", "") +EVENT_TYPE_TABLE_ENTRY("node-prefetch-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_HW_CACHE_NODE) | (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)), "", "") -{"inplace-sampler", SIMPLEPERF_TYPE_USER_SPACE_SAMPLERS, SIMPLEPERF_CONFIG_INPLACE_SAMPLER}, +EVENT_TYPE_TABLE_ENTRY("inplace-sampler", SIMPLEPERF_TYPE_USER_SPACE_SAMPLERS, SIMPLEPERF_CONFIG_INPLACE_SAMPLER, "", "") + +EVENT_TYPE_TABLE_ENTRY("raw-sw-incr", PERF_TYPE_RAW, 0x0, "software increment", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l1-icache-refill", PERF_TYPE_RAW, 0x1, "level 1 instruction cache refill", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l1-itlb-refill", PERF_TYPE_RAW, 0x2, "level 1 instruction TLB refill", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l1-dcache-refill", PERF_TYPE_RAW, 0x3, "level 1 data cache refill", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l1-dcache", PERF_TYPE_RAW, 0x4, "level 1 data cache access", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l1-dtlb-refill", PERF_TYPE_RAW, 0x5, "level 1 data TLB refill", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-load-retired", PERF_TYPE_RAW, 0x6, "load (instruction architecturally executed)", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-store-retired", PERF_TYPE_RAW, 0x7, "store (instruction architecturally executed)", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-instruction-retired", PERF_TYPE_RAW, 0x8, "instructions (instruction architecturally executed)", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-exception-taken", PERF_TYPE_RAW, 0x9, "exception taken", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-exception-return", PERF_TYPE_RAW, 0xa, "exception return (instruction architecturally executed)", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-cid-write-retired", PERF_TYPE_RAW, 0xb, "write to CONTEXIDR (instruction architecturally executed)", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-pc-write-retired", PERF_TYPE_RAW, 0xc, "software change of the PC (instruction architecturally executed)", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-br-immed-retired", PERF_TYPE_RAW, 0xd, "immediate branch (instruction architecturally executed)", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-br-return-retired", PERF_TYPE_RAW, 0xe, "procedure return (instruction architecturally executed)", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-unaligned-ldst-retired", PERF_TYPE_RAW, 0xf, "unaligned load or store (instruction architecturally executed)", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-br-mis-pred", PERF_TYPE_RAW, 0x10, "mispredicted or not predicted branch speculatively executed", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-cpu-cycles", PERF_TYPE_RAW, 0x11, "cpu cycles", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-br-pred", PERF_TYPE_RAW, 0x12, "predictable branch speculatively executed", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-mem-access", PERF_TYPE_RAW, 0x13, "data memory access", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l1-icache", PERF_TYPE_RAW, 0x14, "level 1 instruction cache access", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l1-dcache-wb", PERF_TYPE_RAW, 0x15, "level 1 data cache write-back", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l2-dcache", PERF_TYPE_RAW, 0x16, "level 2 data cache access", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l2-dcache-refill", PERF_TYPE_RAW, 0x17, "level 2 data cache refill", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l2-dcache-wb", PERF_TYPE_RAW, 0x18, "level 2 data cache write-back", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-bus-access", PERF_TYPE_RAW, 0x19, "bus access", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-memory-error", PERF_TYPE_RAW, 0x1a, "local memory error", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-inst-spec", PERF_TYPE_RAW, 0x1b, "operation speculatively executed", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-ttbr-write-retired", PERF_TYPE_RAW, 0x1c, "write to TTBR (instruction architecturally executed)", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-bus-cycles", PERF_TYPE_RAW, 0x1d, "bus cycle", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l1-dcache-allocate", PERF_TYPE_RAW, 0x1f, "level 1 data cache allocation without refill", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l2-dcache-allocate", PERF_TYPE_RAW, 0x20, "level 2 data cache allocation without refill", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-br-retired", PERF_TYPE_RAW, 0x21, "branch (instruction architecturally executed)", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-br-mis-pred-retired", PERF_TYPE_RAW, 0x22, "mispredicted branch (instruction architecturally executed)", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-stall-frontend", PERF_TYPE_RAW, 0x23, "no operation issued due to the frontend", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-stall-backend", PERF_TYPE_RAW, 0x24, "no operation issued due to the backend", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l1-dtlb", PERF_TYPE_RAW, 0x25, "level 1 data or unified TLB access", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l1-itlb", PERF_TYPE_RAW, 0x26, "level 1 instruction TLB access", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l2-icache", PERF_TYPE_RAW, 0x27, "level 2 instruction cache access", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l2-icache-refill", PERF_TYPE_RAW, 0x28, "level 2 instruction cache refill", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l3-dcache-allocate", PERF_TYPE_RAW, 0x29, "level 3 data or unified cache allocation without refill", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l3-dcache-refill", PERF_TYPE_RAW, 0x2a, "level 3 data or unified cache refill", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l3-dcache", PERF_TYPE_RAW, 0x2b, "level 3 data or unified cache access", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l3-dcache-wb", PERF_TYPE_RAW, 0x2c, "level 3 data or unified cache write-back", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l2-dtlb-refill", PERF_TYPE_RAW, 0x2d, "level 2 data or unified TLB refill", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l2-itlb-refill", PERF_TYPE_RAW, 0x2e, "level 2 instruction TLB refill", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l2-dtlb", PERF_TYPE_RAW, 0x2f, "level 2 data or unified TLB access", "arm") +EVENT_TYPE_TABLE_ENTRY("raw-l2-itlb", PERF_TYPE_RAW, 0x30, "level 2 instruction TLB access", "arm") diff --git a/simpleperf/generate_event_type_table.py b/simpleperf/generate_event_type_table.py index eaffd60d..f410c13e 100755 --- a/simpleperf/generate_event_type_table.py +++ b/simpleperf/generate_event_type_table.py @@ -16,12 +16,18 @@ # -def gen_event_type_entry_str(event_type_name, event_type, event_config): +def gen_event_type_entry_str(event_type_name, event_type, event_config, description='', + limited_arch=''): """ - return string like: - {"cpu-cycles", PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES}, + return string as below: + EVENT_TYPE_TABLE_ENTRY(event_type_name, event_type, event_config, description, limited_arch) """ - return '{"%s", %s, %s},\n' % (event_type_name, event_type, event_config) + return 'EVENT_TYPE_TABLE_ENTRY("%s", %s, %s, "%s", "%s")\n' % ( + event_type_name, event_type, event_config, description, limited_arch) + +def gen_arm_event_type_entry_str(event_type_name, event_type, event_config, description): + return gen_event_type_entry_str(event_type_name, event_type, event_config, description, + "arm") def gen_hardware_events(): @@ -105,19 +111,83 @@ def gen_hw_cache_events(): return generated_str - def gen_user_space_events(): generated_str = gen_event_type_entry_str("inplace-sampler", "SIMPLEPERF_TYPE_USER_SPACE_SAMPLERS", "SIMPLEPERF_CONFIG_INPLACE_SAMPLER") return generated_str +def gen_arm_raw_events(): + # Refer to "Table D5-7 PMU event numbers" in ARMv8 specification. + raw_types = [ + [0x00, "sw-incr", "software increment"], + [0x01, "l1-icache-refill", "level 1 instruction cache refill"], + [0x02, "l1-itlb-refill", "level 1 instruction TLB refill"], + [0x03, "l1-dcache-refill", "level 1 data cache refill"], + [0x04, "l1-dcache", "level 1 data cache access"], + [0x05, "l1-dtlb-refill", "level 1 data TLB refill"], + [0x06, "load-retired", "load (instruction architecturally executed)"], + [0x07, "store-retired", "store (instruction architecturally executed)"], + [0x08, "instruction-retired", "instructions (instruction architecturally executed)"], + [0x09, "exception-taken", "exception taken"], + [0x0a, "exception-return", "exception return (instruction architecturally executed)"], + [0x0b, "cid-write-retired", "write to CONTEXIDR (instruction architecturally executed)"], + [0x0c, "pc-write-retired", "software change of the PC (instruction architecturally executed)"], + [0x0d, "br-immed-retired", "immediate branch (instruction architecturally executed)"], + [0x0e, "br-return-retired", "procedure return (instruction architecturally executed)"], + [0x0f, "unaligned-ldst-retired", "unaligned load or store (instruction architecturally executed)"], + [0x10, "br-mis-pred", "mispredicted or not predicted branch speculatively executed"], + [0x11, "cpu-cycles", "cpu cycles"], + [0x12, "br-pred", "predictable branch speculatively executed"], + [0x13, "mem-access", "data memory access"], + [0x14, "l1-icache", "level 1 instruction cache access"], + [0x15, "l1-dcache-wb", "level 1 data cache write-back"], + [0x16, "l2-dcache", "level 2 data cache access"], + [0x17, "l2-dcache-refill", "level 2 data cache refill"], + [0x18, "l2-dcache-wb", "level 2 data cache write-back"], + [0x19, "bus-access", "bus access"], + [0x1a, "memory-error", "local memory error"], + [0x1b, "inst-spec", "operation speculatively executed"], + [0x1c, "ttbr-write-retired", "write to TTBR (instruction architecturally executed)"], + [0x1d, "bus-cycles", "bus cycle"], + # [0x1e, "chain", ""], // Not useful in user space. + [0x1f, "l1-dcache-allocate", "level 1 data cache allocation without refill"], + [0x20, "l2-dcache-allocate", "level 2 data cache allocation without refill"], + [0x21, "br-retired", "branch (instruction architecturally executed)"], + [0x22, "br-mis-pred-retired", "mispredicted branch (instruction architecturally executed)"], + [0x23, "stall-frontend", "no operation issued due to the frontend"], + [0x24, "stall-backend", "no operation issued due to the backend"], + [0x25, "l1-dtlb", "level 1 data or unified TLB access"], + [0x26, "l1-itlb", "level 1 instruction TLB access"], + [0x27, "l2-icache", "level 2 instruction cache access"], + [0x28, "l2-icache-refill", "level 2 instruction cache refill"], + [0x29, "l3-dcache-allocate", "level 3 data or unified cache allocation without refill"], + [0x2a, "l3-dcache-refill", "level 3 data or unified cache refill"], + [0x2b, "l3-dcache", "level 3 data or unified cache access"], + [0x2c, "l3-dcache-wb", "level 3 data or unified cache write-back"], + [0x2d, "l2-dtlb-refill", "level 2 data or unified TLB refill"], + [0x2e, "l2-itlb-refill", "level 2 instruction TLB refill"], + [0x2f, "l2-dtlb", "level 2 data or unified TLB access"], + [0x30, "l2-itlb", "level 2 instruction TLB access"], + ] + generated_str = "" + for item in raw_types: + event_type = 'PERF_TYPE_RAW' + event_type_name = "raw-" + item[1] + event_config = '0x%x' % item[0] + description = item[2] + generated_str += gen_arm_event_type_entry_str(event_type_name, event_type, event_config, + description) + return generated_str + + def gen_events(): generated_str = "// This file is auto-generated by generate-event_table.py.\n\n" generated_str += gen_hardware_events() + '\n' generated_str += gen_software_events() + '\n' generated_str += gen_hw_cache_events() + '\n' generated_str += gen_user_space_events() + '\n' + generated_str += gen_arm_raw_events() + '\n' return generated_str generated_str = gen_events() |