simpleperf: fix raw event names.

Bug: 137044139
Test: run simpleperf list.
Change-Id: If87690f767e8f37d137a7d53d0c3ffb0c07c4adf

2 files changed, 48 insertions, 48 deletions

diff --git a/simpleperf/event_type_table.h b/simpleperf/event_type_table.h
index 2da0b99b..cd1f9d37 100644
--- a/simpleperf/event_type_table.h
+++ b/simpleperf/event_type_table.h
@@ -66,11 +66,11 @@ EVENT_TYPE_TABLE_ENTRY("node-prefetch-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_
 EVENT_TYPE_TABLE_ENTRY("inplace-sampler", SIMPLEPERF_TYPE_USER_SPACE_SAMPLERS, SIMPLEPERF_CONFIG_INPLACE_SAMPLER, "", "")
 
 EVENT_TYPE_TABLE_ENTRY("raw-sw-incr", PERF_TYPE_RAW, 0x0, "Instruction architecturally executed, Condition code check pass, software increment", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1i-cache-refilla", PERF_TYPE_RAW, 0x1, "Level 1 instruction cache refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1i-tlb-refilla", PERF_TYPE_RAW, 0x2, "Attributable Level 1 instruction TLB refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-refilla", PERF_TYPE_RAW, 0x3, "Level 1 data cache refill", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1i-cache-refill", PERF_TYPE_RAW, 0x1, "Level 1 instruction cache refill", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1i-tlb-refill", PERF_TYPE_RAW, 0x2, "Attributable Level 1 instruction TLB refill", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-refill", PERF_TYPE_RAW, 0x3, "Level 1 data cache refill", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache", PERF_TYPE_RAW, 0x4, "Level 1 data cache access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-tlb-refilla", PERF_TYPE_RAW, 0x5, "Attributable Level 1 data TLB refill", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-tlb-refill", PERF_TYPE_RAW, 0x5, "Attributable Level 1 data TLB refill", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-ld-retired", PERF_TYPE_RAW, 0x6, "Instruction architecturally executed, Condition code check pass, load", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-st-retired", PERF_TYPE_RAW, 0x7, "Instruction architecturally executed, Condition code check pass, store", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-inst-retired", PERF_TYPE_RAW, 0x8, "Instruction architecturally executed", "arm")
@@ -88,7 +88,7 @@ EVENT_TYPE_TABLE_ENTRY("raw-mem-access", PERF_TYPE_RAW, 0x13, "Data memory acces
 EVENT_TYPE_TABLE_ENTRY("raw-l1i-cache", PERF_TYPE_RAW, 0x14, "Attributable Level 1 instruction cache access", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-wb", PERF_TYPE_RAW, 0x15, "Attributable Level 1 data cache write-back", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache", PERF_TYPE_RAW, 0x16, "Level 2 data cache access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-refilla", PERF_TYPE_RAW, 0x17, "Level 2 data cache refill", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-refill", PERF_TYPE_RAW, 0x17, "Level 2 data cache refill", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-wb", PERF_TYPE_RAW, 0x18, "Attributable Level 2 data cache write-back", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-bus-access", PERF_TYPE_RAW, 0x19, "Bus access", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-memory-error", PERF_TYPE_RAW, 0x1a, "Local memory error", "arm")
@@ -105,23 +105,23 @@ EVENT_TYPE_TABLE_ENTRY("raw-stall-backend", PERF_TYPE_RAW, 0x24, "No operation i
 EVENT_TYPE_TABLE_ENTRY("raw-l1d-tlb", PERF_TYPE_RAW, 0x25, "Attributable Level 1 data or unified TLB access", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l1i-tlb", PERF_TYPE_RAW, 0x26, "Attributable Level 1 instruction TLB access", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l2i-cache", PERF_TYPE_RAW, 0x27, "Attributable Level 2 instruction cache access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2i-cache-refilla", PERF_TYPE_RAW, 0x28, "Attributable Level 2 instruction cache refill", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2i-cache-refill", PERF_TYPE_RAW, 0x28, "Attributable Level 2 instruction cache refill", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-allocate", PERF_TYPE_RAW, 0x29, "Attributable Level 3 data or unified cache allocation without refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-refilla", PERF_TYPE_RAW, 0x2a, "Attributable Level 3 data cache refill", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-refill", PERF_TYPE_RAW, 0x2a, "Attributable Level 3 data cache refill", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache", PERF_TYPE_RAW, 0x2b, "Attributable Level 3 data cache access", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-wb", PERF_TYPE_RAW, 0x2c, "Attributable Level 3 data or unified cache write-back", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-tlb-refilla", PERF_TYPE_RAW, 0x2d, "Attributable Level 2 data or unified TLB refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2i-tlb-refilla", PERF_TYPE_RAW, 0x2e, "Attributable Level 2 instruction TLB refill", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-tlb-refill", PERF_TYPE_RAW, 0x2d, "Attributable Level 2 data or unified TLB refill", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2i-tlb-refill", PERF_TYPE_RAW, 0x2e, "Attributable Level 2 instruction TLB refill", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l2d-tlb", PERF_TYPE_RAW, 0x2f, "Attributable Level 2 data or unified TLB access", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l2i-tlb", PERF_TYPE_RAW, 0x30, "Attributable Level 2 instruction TLB access", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-remote-access", PERF_TYPE_RAW, 0x31, "Attributable access to another socket in a multi-socket system", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-ll-cache", PERF_TYPE_RAW, 0x32, "Attributable Last Level data cache access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-ll-cache-missa", PERF_TYPE_RAW, 0x33, "Attributable Last level data or unified cache miss", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-dtlb-walka", PERF_TYPE_RAW, 0x34, "Attributable data or unified TLB access with at least one translation table walk", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-itlb-walka", PERF_TYPE_RAW, 0x35, "Attributable instruction TLB access with at least one translation table walk", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-ll-cache-miss", PERF_TYPE_RAW, 0x33, "Attributable Last level data or unified cache miss", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-dtlb-walk", PERF_TYPE_RAW, 0x34, "Attributable data or unified TLB access with at least one translation table walk", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-itlb-walk", PERF_TYPE_RAW, 0x35, "Attributable instruction TLB access with at least one translation table walk", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-ll-cache-rd", PERF_TYPE_RAW, 0x36, "Attributable Last Level cache memory read", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-ll-cache-miss-rda", PERF_TYPE_RAW, 0x37, "Attributable Last Level cache memory read miss", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-remote-access-rda", PERF_TYPE_RAW, 0x38, "Attributable memory read access to another socket in a multi-socket system", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-ll-cache-miss-rd", PERF_TYPE_RAW, 0x37, "Attributable Last Level cache memory read miss", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-remote-access-rd", PERF_TYPE_RAW, 0x38, "Attributable memory read access to another socket in a multi-socket system", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-lmiss-rd", PERF_TYPE_RAW, 0x39, "Level 1 data cache long-latency read miss", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-op-retired", PERF_TYPE_RAW, 0x3a, "Micro-operation architecturally executed", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-op-spec", PERF_TYPE_RAW, 0x3b, "Micro-operation Speculatively executed", "arm")
@@ -143,26 +143,26 @@ EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-lmiss-rd", PERF_TYPE_RAW, 0x400b, "Level 3
 EVENT_TYPE_TABLE_ENTRY("raw-sve-inst-retired", PERF_TYPE_RAW, 0x8002, "SVE Instructions architecturally executed", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-sve-inst-spec", PERF_TYPE_RAW, 0x8006, "SVE Instructions speculatively executed", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-wr", PERF_TYPE_RAW, 0x41, "Attributable Level 1 data cache access, write", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-refill-rda", PERF_TYPE_RAW, 0x42, "Attributable Level 1 data cache refill, read", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-refill-wra", PERF_TYPE_RAW, 0x43, "Attributable Level 1 data cache refill, write", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-refill-rd", PERF_TYPE_RAW, 0x42, "Attributable Level 1 data cache refill, read", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-refill-wr", PERF_TYPE_RAW, 0x43, "Attributable Level 1 data cache refill, write", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-refill-inner", PERF_TYPE_RAW, 0x44, "Attributable Level 1 data cache refill, inner", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-refill-outer", PERF_TYPE_RAW, 0x45, "Attributable Level 1 data cache refill, outer", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-wb-victim", PERF_TYPE_RAW, 0x46, "Attributable Level 1 data cache Write-Back, victim", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-wb-clean", PERF_TYPE_RAW, 0x47, "Level 1 data cache Write-Back, cleaning and coherency", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-inval", PERF_TYPE_RAW, 0x48, "Attributable Level 1 data cache invalidate", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-tlb-refill-rda", PERF_TYPE_RAW, 0x4c, "Attributable Level 1 data TLB refill, read", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1d-tlb-refill-wra", PERF_TYPE_RAW, 0x4d, "Attributable Level 1 data TLB refill, write", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-tlb-refill-rd", PERF_TYPE_RAW, 0x4c, "Attributable Level 1 data TLB refill, read", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-tlb-refill-wr", PERF_TYPE_RAW, 0x4d, "Attributable Level 1 data TLB refill, write", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l1d-tlb-rd", PERF_TYPE_RAW, 0x4e, "Attributable Level 1 data or unified TLB access, read", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l1d-tlb-wr", PERF_TYPE_RAW, 0x4f, "Attributable Level 1 data or unified TLB access, write", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-rd", PERF_TYPE_RAW, 0x50, "Attributable Level 2 data cache access, read", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-wr", PERF_TYPE_RAW, 0x51, "Attributable Level 2 data cache access, write", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-refill-rda", PERF_TYPE_RAW, 0x52, "Attributable Level 2 data cache refill, read", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-refill-wra", PERF_TYPE_RAW, 0x53, "Attributable Level 2 data cache refill, write", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-refill-rd", PERF_TYPE_RAW, 0x52, "Attributable Level 2 data cache refill, read", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-refill-wr", PERF_TYPE_RAW, 0x53, "Attributable Level 2 data cache refill, write", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-wb-victim", PERF_TYPE_RAW, 0x56, "Attributable Level 2 data cache Write-Back, victim", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-wb-clean", PERF_TYPE_RAW, 0x57, "Level 2 data cache Write-Back, cleaning and coherency", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-inval", PERF_TYPE_RAW, 0x58, "Attributable Level 2 data cache invalidate", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-tlb-refill-rda", PERF_TYPE_RAW, 0x5c, "Attributable Level 2 data or unified TLB refill, read", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2d-tlb-refill-wra", PERF_TYPE_RAW, 0x5d, "Attributable Level 2 data or unified TLB refill, write", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-tlb-refill-rd", PERF_TYPE_RAW, 0x5c, "Attributable Level 2 data or unified TLB refill, read", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-tlb-refill-wr", PERF_TYPE_RAW, 0x5d, "Attributable Level 2 data or unified TLB refill, write", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l2d-tlb-rd", PERF_TYPE_RAW, 0x5e, "Attributable Level 2 data or unified TLB access, read", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l2d-tlb-wr", PERF_TYPE_RAW, 0x5f, "Attributable Level 2 data or unified TLB access, write", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-bus-access-rd", PERF_TYPE_RAW, 0x60, "Bus access, read", "arm")
@@ -211,8 +211,8 @@ EVENT_TYPE_TABLE_ENTRY("raw-rc-ld-spec", PERF_TYPE_RAW, 0x90, "Release consisten
 EVENT_TYPE_TABLE_ENTRY("raw-rc-st-spec", PERF_TYPE_RAW, 0x91, "Release consistency operation speculatively executed, Store-Release", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-rd", PERF_TYPE_RAW, 0xa0, "Attributable Level 3 data or unified cache access, read", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-wr", PERF_TYPE_RAW, 0xa1, "Attributable Level 3 data or unified cache access, write", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-refill-rda", PERF_TYPE_RAW, 0xa2, "Attributable Level 3 data or unified cache refill, read", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-refill-wra", PERF_TYPE_RAW, 0xa3, "Attributable Level 3 data or unified cache refill, write", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-refill-rd", PERF_TYPE_RAW, 0xa2, "Attributable Level 3 data or unified cache refill, read", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-refill-wr", PERF_TYPE_RAW, 0xa3, "Attributable Level 3 data or unified cache refill, write", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-wb-victim", PERF_TYPE_RAW, 0xa6, "Attributable Level 3 data or unified cache Write-Back, victim", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-wb-clean", PERF_TYPE_RAW, 0xa7, "Attributable Level 3 data or unified cache Write-Back, cache clean", "arm")
 EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-inval", PERF_TYPE_RAW, 0xa8, "Attributable Level 3 data or unified cache access, invalidate", "arm")
diff --git a/simpleperf/generate_event_type_table.py b/simpleperf/generate_event_type_table.py
index f17f4dce..9ed50c50 100755
--- a/simpleperf/generate_event_type_table.py
+++ b/simpleperf/generate_event_type_table.py
@@ -121,11 +121,11 @@ def gen_arm_raw_events():
   raw_types = [
                # Refer to "Table D6-7 PMU common architectural and microarchitectural event numbers" in ARMv8 specification.
                [0x0000, "sw-incr", "Instruction architecturally executed, Condition code check pass, software increment"],
-               [0x0001, "l1i-cache-refilla", "Level 1 instruction cache refill"],
-               [0x0002, "l1i-tlb-refilla", "Attributable Level 1 instruction TLB refill"],
-               [0x0003, "l1d-cache-refilla", "Level 1 data cache refill"],
+               [0x0001, "l1i-cache-refill", "Level 1 instruction cache refill"],
+               [0x0002, "l1i-tlb-refill", "Attributable Level 1 instruction TLB refill"],
+               [0x0003, "l1d-cache-refill", "Level 1 data cache refill"],
                [0x0004, "l1d-cache", "Level 1 data cache access"],
-               [0x0005, "l1d-tlb-refilla", "Attributable Level 1 data TLB refill"],
+               [0x0005, "l1d-tlb-refill", "Attributable Level 1 data TLB refill"],
                [0x0006, "ld-retired", "Instruction architecturally executed, Condition code check pass, load"],
                [0x0007, "st-retired", "Instruction architecturally executed, Condition code check pass, store"],
                [0x0008, "inst-retired", "Instruction architecturally executed"],
@@ -143,7 +143,7 @@ def gen_arm_raw_events():
                [0x0014, "l1i-cache", "Attributable Level 1 instruction cache access"],
                [0x0015, "l1d-cache-wb", "Attributable Level 1 data cache write-back"],
                [0x0016, "l2d-cache", "Level 2 data cache access"],
-               [0x0017, "l2d-cache-refilla", "Level 2 data cache refill"],
+               [0x0017, "l2d-cache-refill", "Level 2 data cache refill"],
                [0x0018, "l2d-cache-wb", "Attributable Level 2 data cache write-back"],
                [0x0019, "bus-access", "Bus access"],
                [0x001A, "memory-error", "Local memory error"],
@@ -160,23 +160,23 @@ def gen_arm_raw_events():
                [0x0025, "l1d-tlb", "Attributable Level 1 data or unified TLB access"],
                [0x0026, "l1i-tlb", "Attributable Level 1 instruction TLB access"],
                [0x0027, "l2i-cache", "Attributable Level 2 instruction cache access"],
-               [0x0028, "l2i-cache-refilla", "Attributable Level 2 instruction cache refill"],
+               [0x0028, "l2i-cache-refill", "Attributable Level 2 instruction cache refill"],
                [0x0029, "l3d-cache-allocate", "Attributable Level 3 data or unified cache allocation without refill"],
-               [0x002A, "l3d-cache-refilla", "Attributable Level 3 data cache refill"],
+               [0x002A, "l3d-cache-refill", "Attributable Level 3 data cache refill"],
                [0x002B, "l3d-cache", "Attributable Level 3 data cache access"],
                [0x002C, "l3d-cache-wb", "Attributable Level 3 data or unified cache write-back"],
-               [0x002D, "l2d-tlb-refilla", "Attributable Level 2 data or unified TLB refill"],
-               [0x002E, "l2i-tlb-refilla", "Attributable Level 2 instruction TLB refill"],
+               [0x002D, "l2d-tlb-refill", "Attributable Level 2 data or unified TLB refill"],
+               [0x002E, "l2i-tlb-refill", "Attributable Level 2 instruction TLB refill"],
                [0x002F, "l2d-tlb", "Attributable Level 2 data or unified TLB access"],
                [0x0030, "l2i-tlb", "Attributable Level 2 instruction TLB access"],
                [0x0031, "remote-access", "Attributable access to another socket in a multi-socket system"],
                [0x0032, "ll-cache", "Attributable Last Level data cache access"],
-               [0x0033, "ll-cache-missa", "Attributable Last level data or unified cache miss"],
-               [0x0034, "dtlb-walka", "Attributable data or unified TLB access with at least one translation table walk"],
-               [0x0035, "itlb-walka", "Attributable instruction TLB access with at least one translation table walk"],
+               [0x0033, "ll-cache-miss", "Attributable Last level data or unified cache miss"],
+               [0x0034, "dtlb-walk", "Attributable data or unified TLB access with at least one translation table walk"],
+               [0x0035, "itlb-walk", "Attributable instruction TLB access with at least one translation table walk"],
                [0x0036, "ll-cache-rd", "Attributable Last Level cache memory read"],
-               [0x0037, "ll-cache-miss-rda", "Attributable Last Level cache memory read miss"],
-               [0x0038, "remote-access-rda", "Attributable memory read access to another socket in a multi-socket system"],
+               [0x0037, "ll-cache-miss-rd", "Attributable Last Level cache memory read miss"],
+               [0x0038, "remote-access-rd", "Attributable memory read access to another socket in a multi-socket system"],
                [0x0039, "l1d-cache-lmiss-rd", "Level 1 data cache long-latency read miss"],
                [0x003A, "op-retired", "Micro-operation architecturally executed"],
                [0x003B, "op-spec", "Micro-operation Speculatively executed"],
@@ -201,29 +201,29 @@ def gen_arm_raw_events():
                # Refer to "Table K3.1 ARM recommendations for IMPLEMENTATION DEFINED event numbers" in ARMv8 specification.
                #[0x0040, "l1d-cache-rd", "Attributable Level 1 data cache access, read"],
                [0x0041, "l1d-cache-wr", "Attributable Level 1 data cache access, write"],
-               [0x0042, "l1d-cache-refill-rda", "Attributable Level 1 data cache refill, read"],
-               [0x0043, "l1d-cache-refill-wra", "Attributable Level 1 data cache refill, write"],
+               [0x0042, "l1d-cache-refill-rd", "Attributable Level 1 data cache refill, read"],
+               [0x0043, "l1d-cache-refill-wr", "Attributable Level 1 data cache refill, write"],
                [0x0044, "l1d-cache-refill-inner", "Attributable Level 1 data cache refill, inner"],
                [0x0045, "l1d-cache-refill-outer", "Attributable Level 1 data cache refill, outer"],
                [0x0046, "l1d-cache-wb-victim", "Attributable Level 1 data cache Write-Back, victim"],
                [0x0047, "l1d-cache-wb-clean", "Level 1 data cache Write-Back, cleaning and coherency"],
                [0x0048, "l1d-cache-inval", "Attributable Level 1 data cache invalidate"],
                # 0x0049-0x004B - Reserved
-               [0x004C, "l1d-tlb-refill-rda", "Attributable Level 1 data TLB refill, read"],
-               [0x004D, "l1d-tlb-refill-wra", "Attributable Level 1 data TLB refill, write"],
+               [0x004C, "l1d-tlb-refill-rd", "Attributable Level 1 data TLB refill, read"],
+               [0x004D, "l1d-tlb-refill-wr", "Attributable Level 1 data TLB refill, write"],
                [0x004E, "l1d-tlb-rd", "Attributable Level 1 data or unified TLB access, read"],
                [0x004F, "l1d-tlb-wr", "Attributable Level 1 data or unified TLB access, write"],
                [0x0050, "l2d-cache-rd", "Attributable Level 2 data cache access, read"],
                [0x0051, "l2d-cache-wr", "Attributable Level 2 data cache access, write"],
-               [0x0052, "l2d-cache-refill-rda", "Attributable Level 2 data cache refill, read"],
-               [0x0053, "l2d-cache-refill-wra", "Attributable Level 2 data cache refill, write"],
+               [0x0052, "l2d-cache-refill-rd", "Attributable Level 2 data cache refill, read"],
+               [0x0053, "l2d-cache-refill-wr", "Attributable Level 2 data cache refill, write"],
                # 0x0054-0x0055 - Reserved
                [0x0056, "l2d-cache-wb-victim", "Attributable Level 2 data cache Write-Back, victim"],
                [0x0057, "l2d-cache-wb-clean", "Level 2 data cache Write-Back, cleaning and coherency"],
                [0x0058, "l2d-cache-inval", "Attributable Level 2 data cache invalidate"],
                # 0x0059-0x005B - Reserved
-               [0x005C, "l2d-tlb-refill-rda", "Attributable Level 2 data or unified TLB refill, read"],
-               [0x005D, "l2d-tlb-refill-wra", "Attributable Level 2 data or unified TLB refill, write"],
+               [0x005C, "l2d-tlb-refill-rd", "Attributable Level 2 data or unified TLB refill, read"],
+               [0x005D, "l2d-tlb-refill-wr", "Attributable Level 2 data or unified TLB refill, write"],
                [0x005E, "l2d-tlb-rd", "Attributable Level 2 data or unified TLB access, read"],
                [0x005F, "l2d-tlb-wr", "Attributable Level 2 data or unified TLB access, write"],
                [0x0060, "bus-access-rd", "Bus access, read"],
@@ -278,8 +278,8 @@ def gen_arm_raw_events():
                # 0x0092-0x009F - Reserved
                [0x00A0, "l3d-cache-rd", "Attributable Level 3 data or unified cache access, read"],
                [0x00A1, "l3d-cache-wr", "Attributable Level 3 data or unified cache access, write"],
-               [0x00A2, "l3d-cache-refill-rda", "Attributable Level 3 data or unified cache refill, read"],
-               [0x00A3, "l3d-cache-refill-wra", "Attributable Level 3 data or unified cache refill, write"],
+               [0x00A2, "l3d-cache-refill-rd", "Attributable Level 3 data or unified cache refill, read"],
+               [0x00A3, "l3d-cache-refill-wr", "Attributable Level 3 data or unified cache refill, write"],
                # 0x00A4-0x00A5 - Reserved
                [0x00A6, "l3d-cache-wb-victim", "Attributable Level 3 data or unified cache Write-Back, victim"],
                [0x00A7, "l3d-cache-wb-clean", "Attributable Level 3 data or unified cache Write-Back, cache clean"],