Merge "simpleperf: add event numbers listed in ARM 8.4 manual."

3 files changed, 334 insertions, 107 deletions

diff --git a/simpleperf/cmd_list.cpp b/simpleperf/cmd_list.cpp
index c87c05f5..d9fdf9c8 100644
--- a/simpleperf/cmd_list.cpp
+++ b/simpleperf/cmd_list.cpp
@@ -45,7 +45,7 @@ static bool IsEventTypeSupported(const EventType& event_type) {
   // We can't decide whether the raw event is supported by calling perf_event_open().
   // Instead, we can check if it can collect some real number.
   perf_event_attr attr = CreateDefaultPerfEventAttr(event_type);
-  std::unique_ptr<EventFd> event_fd = EventFd::OpenEventFile(attr, gettid(), -1, nullptr);
+  std::unique_ptr<EventFd> event_fd = EventFd::OpenEventFile(attr, gettid(), -1, nullptr, false);
   if (event_fd == nullptr) {
     return false;
   }
@@ -72,18 +72,27 @@ static void PrintEventTypesOfType(uint32_t type, const std::string& type_name,
                                   const std::set<EventType>& event_types) {
   printf("List of %s:\n", type_name.c_str());
   if (type == PERF_TYPE_RAW && (GetBuildArch() == ARCH_ARM || GetBuildArch() == ARCH_ARM64)) {
-    printf("  # Please refer to PMU event numbers listed in ARMv8 manual for details.\n");
-    printf("  # A possible link is https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile.\n");
+    printf("  # Please refer to \"PMU common architectural and microarchitectural event numbers\"\n"
+           "  # and \"ARM recommendations for IMPLEMENTATION DEFINED event numbers\" listed in\n"
+           "  # ARMv8 manual for details.\n"
+           "  # A possible link is https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile.\n");
   }
   for (auto& event_type : event_types) {
     if (event_type.type == type) {
-      if (IsEventTypeSupported(event_type)) {
-        printf("  %s", event_type.name.c_str());
-        if (!event_type.description.empty()) {
-          printf("\t\t# %s", event_type.description.c_str());
-        }
-        printf("\n");
+      bool supported = IsEventTypeSupported(event_type);
+      // For raw events, we may not be able to detect whether it is supported on device.
+      // So always print them.
+      if (!supported && type != PERF_TYPE_RAW) {
+        continue;
       }
+      printf("  %s", event_type.name.c_str());
+      if (!supported) {
+        printf(" (may not supported)");
+      }
+      if (!event_type.description.empty()) {
+        printf("\t\t# %s", event_type.description.c_str());
+      }
+      printf("\n");
     }
   }
   printf("\n");
diff --git a/simpleperf/event_type_table.h b/simpleperf/event_type_table.h
index 3ecf2c80..2da0b99b 100644
--- a/simpleperf/event_type_table.h
+++ b/simpleperf/event_type_table.h
@@ -65,52 +65,155 @@ EVENT_TYPE_TABLE_ENTRY("node-prefetch-misses", PERF_TYPE_HW_CACHE, ((PERF_COUNT_
 
 EVENT_TYPE_TABLE_ENTRY("inplace-sampler", SIMPLEPERF_TYPE_USER_SPACE_SAMPLERS, SIMPLEPERF_CONFIG_INPLACE_SAMPLER, "", "")
 
-EVENT_TYPE_TABLE_ENTRY("raw-sw-incr", PERF_TYPE_RAW, 0x0, "software increment", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1-icache-refill", PERF_TYPE_RAW, 0x1, "level 1 instruction cache refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1-itlb-refill", PERF_TYPE_RAW, 0x2, "level 1 instruction TLB refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1-dcache-refill", PERF_TYPE_RAW, 0x3, "level 1 data cache refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1-dcache", PERF_TYPE_RAW, 0x4, "level 1 data cache access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1-dtlb-refill", PERF_TYPE_RAW, 0x5, "level 1 data TLB refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-load-retired", PERF_TYPE_RAW, 0x6, "load (instruction architecturally executed)", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-store-retired", PERF_TYPE_RAW, 0x7, "store (instruction architecturally executed)", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-instruction-retired", PERF_TYPE_RAW, 0x8, "instructions (instruction architecturally executed)", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-exception-taken", PERF_TYPE_RAW, 0x9, "exception taken", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-exception-return", PERF_TYPE_RAW, 0xa, "exception return (instruction architecturally executed)", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-cid-write-retired", PERF_TYPE_RAW, 0xb, "write to CONTEXIDR (instruction architecturally executed)", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-pc-write-retired", PERF_TYPE_RAW, 0xc, "software change of the PC (instruction architecturally executed)", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-br-immed-retired", PERF_TYPE_RAW, 0xd, "immediate branch (instruction architecturally executed)", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-br-return-retired", PERF_TYPE_RAW, 0xe, "procedure return (instruction architecturally executed)", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-unaligned-ldst-retired", PERF_TYPE_RAW, 0xf, "unaligned load or store (instruction architecturally executed)", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-br-mis-pred", PERF_TYPE_RAW, 0x10, "mispredicted or not predicted branch speculatively executed", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-cpu-cycles", PERF_TYPE_RAW, 0x11, "cpu cycles", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-br-pred", PERF_TYPE_RAW, 0x12, "predictable branch speculatively executed", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-mem-access", PERF_TYPE_RAW, 0x13, "data memory access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1-icache", PERF_TYPE_RAW, 0x14, "level 1 instruction cache access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1-dcache-wb", PERF_TYPE_RAW, 0x15, "level 1 data cache write-back", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2-dcache", PERF_TYPE_RAW, 0x16, "level 2 data cache access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2-dcache-refill", PERF_TYPE_RAW, 0x17, "level 2 data cache refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2-dcache-wb", PERF_TYPE_RAW, 0x18, "level 2 data cache write-back", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-bus-access", PERF_TYPE_RAW, 0x19, "bus access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-memory-error", PERF_TYPE_RAW, 0x1a, "local memory error", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-inst-spec", PERF_TYPE_RAW, 0x1b, "operation speculatively executed", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-ttbr-write-retired", PERF_TYPE_RAW, 0x1c, "write to TTBR (instruction architecturally executed)", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-bus-cycles", PERF_TYPE_RAW, 0x1d, "bus cycle", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1-dcache-allocate", PERF_TYPE_RAW, 0x1f, "level 1 data cache allocation without refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2-dcache-allocate", PERF_TYPE_RAW, 0x20, "level 2 data cache allocation without refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-br-retired", PERF_TYPE_RAW, 0x21, "branch (instruction architecturally executed)", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-br-mis-pred-retired", PERF_TYPE_RAW, 0x22, "mispredicted branch (instruction architecturally executed)", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-stall-frontend", PERF_TYPE_RAW, 0x23, "no operation issued due to the frontend", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-stall-backend", PERF_TYPE_RAW, 0x24, "no operation issued due to the backend", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1-dtlb", PERF_TYPE_RAW, 0x25, "level 1 data or unified TLB access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l1-itlb", PERF_TYPE_RAW, 0x26, "level 1 instruction TLB access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2-icache", PERF_TYPE_RAW, 0x27, "level 2 instruction cache access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2-icache-refill", PERF_TYPE_RAW, 0x28, "level 2 instruction cache refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l3-dcache-allocate", PERF_TYPE_RAW, 0x29, "level 3 data or unified cache allocation without refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l3-dcache-refill", PERF_TYPE_RAW, 0x2a, "level 3 data or unified cache refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l3-dcache", PERF_TYPE_RAW, 0x2b, "level 3 data or unified cache access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l3-dcache-wb", PERF_TYPE_RAW, 0x2c, "level 3 data or unified cache write-back", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2-dtlb-refill", PERF_TYPE_RAW, 0x2d, "level 2 data or unified TLB refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2-itlb-refill", PERF_TYPE_RAW, 0x2e, "level 2 instruction TLB refill", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2-dtlb", PERF_TYPE_RAW, 0x2f, "level 2 data or unified TLB access", "arm")
-EVENT_TYPE_TABLE_ENTRY("raw-l2-itlb", PERF_TYPE_RAW, 0x30, "level 2 instruction TLB access", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-sw-incr", PERF_TYPE_RAW, 0x0, "Instruction architecturally executed, Condition code check pass, software increment", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1i-cache-refilla", PERF_TYPE_RAW, 0x1, "Level 1 instruction cache refill", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1i-tlb-refilla", PERF_TYPE_RAW, 0x2, "Attributable Level 1 instruction TLB refill", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-refilla", PERF_TYPE_RAW, 0x3, "Level 1 data cache refill", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache", PERF_TYPE_RAW, 0x4, "Level 1 data cache access", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-tlb-refilla", PERF_TYPE_RAW, 0x5, "Attributable Level 1 data TLB refill", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-ld-retired", PERF_TYPE_RAW, 0x6, "Instruction architecturally executed, Condition code check pass, load", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-st-retired", PERF_TYPE_RAW, 0x7, "Instruction architecturally executed, Condition code check pass, store", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-inst-retired", PERF_TYPE_RAW, 0x8, "Instruction architecturally executed", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-exc-taken", PERF_TYPE_RAW, 0x9, "Exception taken", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-exc-return", PERF_TYPE_RAW, 0xa, "Instruction architecturally executed, Condition code check pass, exception return", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-cid-write-retired", PERF_TYPE_RAW, 0xb, "Instruction architecturally executed, Condition code check pass, write to CONTEXTIDR", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-pc-write-retired", PERF_TYPE_RAW, 0xc, "Instruction architecturally executed, Condition code check pass, software change of the PC", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-br-immed-retired", PERF_TYPE_RAW, 0xd, "Instruction architecturally executed, immediate branch", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-br-return-retired", PERF_TYPE_RAW, 0xe, "Instruction architecturally executed, Condition code check pass, procedure return", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-unaligned-ldst-retired", PERF_TYPE_RAW, 0xf, "Instruction architecturally executed, Condition code check pass, unaligned load or store", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-br-mis-pred", PERF_TYPE_RAW, 0x10, "Mispredicted or not predicted branch Speculatively executed", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-cpu-cycles", PERF_TYPE_RAW, 0x11, "Cycle", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-br-pred", PERF_TYPE_RAW, 0x12, "Predictable branch Speculatively executed", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-mem-access", PERF_TYPE_RAW, 0x13, "Data memory access", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1i-cache", PERF_TYPE_RAW, 0x14, "Attributable Level 1 instruction cache access", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-wb", PERF_TYPE_RAW, 0x15, "Attributable Level 1 data cache write-back", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache", PERF_TYPE_RAW, 0x16, "Level 2 data cache access", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-refilla", PERF_TYPE_RAW, 0x17, "Level 2 data cache refill", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-wb", PERF_TYPE_RAW, 0x18, "Attributable Level 2 data cache write-back", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-bus-access", PERF_TYPE_RAW, 0x19, "Bus access", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-memory-error", PERF_TYPE_RAW, 0x1a, "Local memory error", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-inst-spec", PERF_TYPE_RAW, 0x1b, "Operation Speculatively executed", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-ttbr-write-retired", PERF_TYPE_RAW, 0x1c, "Instruction architecturally executed, Condition code check pass, write to TTBR", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-bus-cycles", PERF_TYPE_RAW, 0x1d, "Bus cycle", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-chain", PERF_TYPE_RAW, 0x1e, "For odd-numbered counters, increments the count by one for each overflow of the preceding even-numbered counter. For even-numbered counters, there is no increment.", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-allocate", PERF_TYPE_RAW, 0x1f, "Attributable Level 1 data cache allocation without refill", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-allocate", PERF_TYPE_RAW, 0x20, "Attributable Level 2 data cache allocation without refill", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-br-retired", PERF_TYPE_RAW, 0x21, "Instruction architecturally executed, branch", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-br-mis-pred-retired", PERF_TYPE_RAW, 0x22, "Instruction architecturally executed, mispredicted branch", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-stall-frontend", PERF_TYPE_RAW, 0x23, "No operation issued due to the frontend", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-stall-backend", PERF_TYPE_RAW, 0x24, "No operation issued due to backend", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-tlb", PERF_TYPE_RAW, 0x25, "Attributable Level 1 data or unified TLB access", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1i-tlb", PERF_TYPE_RAW, 0x26, "Attributable Level 1 instruction TLB access", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2i-cache", PERF_TYPE_RAW, 0x27, "Attributable Level 2 instruction cache access", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2i-cache-refilla", PERF_TYPE_RAW, 0x28, "Attributable Level 2 instruction cache refill", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-allocate", PERF_TYPE_RAW, 0x29, "Attributable Level 3 data or unified cache allocation without refill", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-refilla", PERF_TYPE_RAW, 0x2a, "Attributable Level 3 data cache refill", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache", PERF_TYPE_RAW, 0x2b, "Attributable Level 3 data cache access", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-wb", PERF_TYPE_RAW, 0x2c, "Attributable Level 3 data or unified cache write-back", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-tlb-refilla", PERF_TYPE_RAW, 0x2d, "Attributable Level 2 data or unified TLB refill", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2i-tlb-refilla", PERF_TYPE_RAW, 0x2e, "Attributable Level 2 instruction TLB refill", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-tlb", PERF_TYPE_RAW, 0x2f, "Attributable Level 2 data or unified TLB access", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2i-tlb", PERF_TYPE_RAW, 0x30, "Attributable Level 2 instruction TLB access", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-remote-access", PERF_TYPE_RAW, 0x31, "Attributable access to another socket in a multi-socket system", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-ll-cache", PERF_TYPE_RAW, 0x32, "Attributable Last Level data cache access", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-ll-cache-missa", PERF_TYPE_RAW, 0x33, "Attributable Last level data or unified cache miss", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-dtlb-walka", PERF_TYPE_RAW, 0x34, "Attributable data or unified TLB access with at least one translation table walk", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-itlb-walka", PERF_TYPE_RAW, 0x35, "Attributable instruction TLB access with at least one translation table walk", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-ll-cache-rd", PERF_TYPE_RAW, 0x36, "Attributable Last Level cache memory read", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-ll-cache-miss-rda", PERF_TYPE_RAW, 0x37, "Attributable Last Level cache memory read miss", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-remote-access-rda", PERF_TYPE_RAW, 0x38, "Attributable memory read access to another socket in a multi-socket system", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-lmiss-rd", PERF_TYPE_RAW, 0x39, "Level 1 data cache long-latency read miss", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-op-retired", PERF_TYPE_RAW, 0x3a, "Micro-operation architecturally executed", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-op-spec", PERF_TYPE_RAW, 0x3b, "Micro-operation Speculatively executed", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-stall", PERF_TYPE_RAW, 0x3c, "No operation sent for execution", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-stall-slot-backend", PERF_TYPE_RAW, 0x3d, "No operation sent for execution on a Slot due to the backend", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-stall-slot-frontend", PERF_TYPE_RAW, 0x3e, "No operation send for execution on a Slot due to the frontend", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-stall-slot", PERF_TYPE_RAW, 0x3f, "No operation sent for execution on a Slot", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-rd", PERF_TYPE_RAW, 0x40, "Level 1 data cache read", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-sample-pop", PERF_TYPE_RAW, 0x4000, "Sample Population", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-sample-feed", PERF_TYPE_RAW, 0x4001, "Sample Taken", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-sample-filtrate", PERF_TYPE_RAW, 0x4002, "Sample Taken and not removed by filtering", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-sample-collision", PERF_TYPE_RAW, 0x4003, "Sample collided with previous sample", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-cnt-cycles", PERF_TYPE_RAW, 0x4004, "Constant frequency cycles", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-stall-backend-mem", PERF_TYPE_RAW, 0x4005, "Memory stall cycles", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1i-cache-lmiss", PERF_TYPE_RAW, 0x4006, "Level 1 instruction cache long-latency miss", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-lmiss-rd", PERF_TYPE_RAW, 0x4009, "Level 2 data cache long-latency read miss", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2i-cache-lmiss", PERF_TYPE_RAW, 0x400a, "Level 2 instruction cache long-latency miss", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-lmiss-rd", PERF_TYPE_RAW, 0x400b, "Level 3 data cache long-latency read miss", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-sve-inst-retired", PERF_TYPE_RAW, 0x8002, "SVE Instructions architecturally executed", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-sve-inst-spec", PERF_TYPE_RAW, 0x8006, "SVE Instructions speculatively executed", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-wr", PERF_TYPE_RAW, 0x41, "Attributable Level 1 data cache access, write", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-refill-rda", PERF_TYPE_RAW, 0x42, "Attributable Level 1 data cache refill, read", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-refill-wra", PERF_TYPE_RAW, 0x43, "Attributable Level 1 data cache refill, write", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-refill-inner", PERF_TYPE_RAW, 0x44, "Attributable Level 1 data cache refill, inner", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-refill-outer", PERF_TYPE_RAW, 0x45, "Attributable Level 1 data cache refill, outer", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-wb-victim", PERF_TYPE_RAW, 0x46, "Attributable Level 1 data cache Write-Back, victim", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-wb-clean", PERF_TYPE_RAW, 0x47, "Level 1 data cache Write-Back, cleaning and coherency", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-cache-inval", PERF_TYPE_RAW, 0x48, "Attributable Level 1 data cache invalidate", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-tlb-refill-rda", PERF_TYPE_RAW, 0x4c, "Attributable Level 1 data TLB refill, read", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-tlb-refill-wra", PERF_TYPE_RAW, 0x4d, "Attributable Level 1 data TLB refill, write", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-tlb-rd", PERF_TYPE_RAW, 0x4e, "Attributable Level 1 data or unified TLB access, read", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l1d-tlb-wr", PERF_TYPE_RAW, 0x4f, "Attributable Level 1 data or unified TLB access, write", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-rd", PERF_TYPE_RAW, 0x50, "Attributable Level 2 data cache access, read", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-wr", PERF_TYPE_RAW, 0x51, "Attributable Level 2 data cache access, write", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-refill-rda", PERF_TYPE_RAW, 0x52, "Attributable Level 2 data cache refill, read", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-refill-wra", PERF_TYPE_RAW, 0x53, "Attributable Level 2 data cache refill, write", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-wb-victim", PERF_TYPE_RAW, 0x56, "Attributable Level 2 data cache Write-Back, victim", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-wb-clean", PERF_TYPE_RAW, 0x57, "Level 2 data cache Write-Back, cleaning and coherency", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-cache-inval", PERF_TYPE_RAW, 0x58, "Attributable Level 2 data cache invalidate", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-tlb-refill-rda", PERF_TYPE_RAW, 0x5c, "Attributable Level 2 data or unified TLB refill, read", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-tlb-refill-wra", PERF_TYPE_RAW, 0x5d, "Attributable Level 2 data or unified TLB refill, write", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-tlb-rd", PERF_TYPE_RAW, 0x5e, "Attributable Level 2 data or unified TLB access, read", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l2d-tlb-wr", PERF_TYPE_RAW, 0x5f, "Attributable Level 2 data or unified TLB access, write", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-bus-access-rd", PERF_TYPE_RAW, 0x60, "Bus access, read", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-bus-access-wr", PERF_TYPE_RAW, 0x61, "Bus access, write", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-bus-access-shared", PERF_TYPE_RAW, 0x62, "Bus access, Normal, Cacheable, Shareable", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-bus-access-not-shared", PERF_TYPE_RAW, 0x63, "Bus access, not Normal, Cacheable, Shareable", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-bus-access-normal", PERF_TYPE_RAW, 0x64, "Bus access, normal", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-bus-access-periph", PERF_TYPE_RAW, 0x65, "Bus access, peripheral", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-mem-access-rd", PERF_TYPE_RAW, 0x66, "Data memory access, read", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-mem-access-wr", PERF_TYPE_RAW, 0x67, "Data memory access, write", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-unaligned-ld-spec", PERF_TYPE_RAW, 0x68, "Unaligned access, read", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-unaligned-st-spec", PERF_TYPE_RAW, 0x69, "Unaligned access, write", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-unaligned-ldst-spec", PERF_TYPE_RAW, 0x6a, "Unaligned access", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-ldrex-spec", PERF_TYPE_RAW, 0x6c, "Exclusive operation speculatively executed, LDREX or LDX", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-strex-pass-spec", PERF_TYPE_RAW, 0x6d, "Exclusive operation speculatively executed, STREX or STX pass", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-strex-fail-spec", PERF_TYPE_RAW, 0x6e, "Exclusive operation speculatively executed, STREX or STX fail", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-strex-spec", PERF_TYPE_RAW, 0x6f, "Exclusive operation speculatively executed, STREX or STX", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-ld-spec", PERF_TYPE_RAW, 0x70, "Operation speculatively executed, load", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-st-spec", PERF_TYPE_RAW, 0x71, "Operation speculatively executed, store", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-ldst-spec", PERF_TYPE_RAW, 0x72, "Operation speculatively executed, load or store", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-dp-spec", PERF_TYPE_RAW, 0x73, "Operation speculatively executed, integer data processing", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-ase-spec", PERF_TYPE_RAW, 0x74, "Operation speculatively executed, Advanced SIMD instruction", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-vfp-spec", PERF_TYPE_RAW, 0x75, "Operation speculatively executed, floating-point instruction", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-pc-write-spec", PERF_TYPE_RAW, 0x76, "Operation speculatively executed, software change of the PC", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-crypto-spec", PERF_TYPE_RAW, 0x77, "Operation speculatively executed, Cryptographic instruction", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-br-immed-spec", PERF_TYPE_RAW, 0x78, "Branch speculatively executed, immediate branch", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-br-return-spec", PERF_TYPE_RAW, 0x79, "Branch speculatively executed, procedure return", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-br-indirect-spec", PERF_TYPE_RAW, 0x7a, "Branch speculatively executed, indirect branch", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-isb-spec", PERF_TYPE_RAW, 0x7c, "Barrier speculatively executed, ISB", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-dsb-spec", PERF_TYPE_RAW, 0x7d, "Barrier speculatively executed, DSB", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-dmb-spec", PERF_TYPE_RAW, 0x7e, "Barrier speculatively executed, DMB", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-exc-undef", PERF_TYPE_RAW, 0x81, "Exception taken, Other synchronous", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-exc-svc", PERF_TYPE_RAW, 0x82, "Exception taken, Supervisor Call", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-exc-pabort", PERF_TYPE_RAW, 0x83, "Exception taken, Instruction Abort", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-exc-dabort", PERF_TYPE_RAW, 0x84, "Exception taken, Data Abort and SError", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-exc-irq", PERF_TYPE_RAW, 0x86, "Exception taken, IRQ", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-exc-fiq", PERF_TYPE_RAW, 0x87, "Exception taken, FIQ", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-exc-smc", PERF_TYPE_RAW, 0x88, "Exception taken, Secure Monitor Call", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-exc-hvc", PERF_TYPE_RAW, 0x8a, "Exception taken, Hypervisor Call", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-exc-trap-pabort", PERF_TYPE_RAW, 0x8b, "Exception taken, Instruction Abort not Taken locallyb", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-exc-trap-dabort", PERF_TYPE_RAW, 0x8c, "Exception taken, Data Abort or SError not Taken locallyb", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-exc-trap-other", PERF_TYPE_RAW, 0x8d, "Exception taken, Other traps not Taken locallyb", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-exc-trap-irq", PERF_TYPE_RAW, 0x8e, "Exception taken, IRQ not Taken locallyb", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-exc-trap-fiq", PERF_TYPE_RAW, 0x8f, "Exception taken, FIQ not Taken locallyb", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-rc-ld-spec", PERF_TYPE_RAW, 0x90, "Release consistency operation speculatively executed, Load-Acquire", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-rc-st-spec", PERF_TYPE_RAW, 0x91, "Release consistency operation speculatively executed, Store-Release", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-rd", PERF_TYPE_RAW, 0xa0, "Attributable Level 3 data or unified cache access, read", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-wr", PERF_TYPE_RAW, 0xa1, "Attributable Level 3 data or unified cache access, write", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-refill-rda", PERF_TYPE_RAW, 0xa2, "Attributable Level 3 data or unified cache refill, read", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-refill-wra", PERF_TYPE_RAW, 0xa3, "Attributable Level 3 data or unified cache refill, write", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-wb-victim", PERF_TYPE_RAW, 0xa6, "Attributable Level 3 data or unified cache Write-Back, victim", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-wb-clean", PERF_TYPE_RAW, 0xa7, "Attributable Level 3 data or unified cache Write-Back, cache clean", "arm")
+EVENT_TYPE_TABLE_ENTRY("raw-l3d-cache-inval", PERF_TYPE_RAW, 0xa8, "Attributable Level 3 data or unified cache access, invalidate", "arm")
 
diff --git a/simpleperf/generate_event_type_table.py b/simpleperf/generate_event_type_table.py
index f410c13e..f17f4dce 100755
--- a/simpleperf/generate_event_type_table.py
+++ b/simpleperf/generate_event_type_table.py
@@ -118,57 +118,172 @@ def gen_user_space_events():
   return generated_str
 
 def gen_arm_raw_events():
-  # Refer to "Table D5-7 PMU event numbers" in ARMv8 specification.
   raw_types = [
-               [0x00, "sw-incr", "software increment"],
-               [0x01, "l1-icache-refill", "level 1 instruction cache refill"],
-               [0x02, "l1-itlb-refill", "level 1 instruction TLB refill"],
-               [0x03, "l1-dcache-refill", "level 1 data cache refill"],
-               [0x04, "l1-dcache", "level 1 data cache access"],
-               [0x05, "l1-dtlb-refill", "level 1 data TLB refill"],
-               [0x06, "load-retired", "load (instruction architecturally executed)"],
-               [0x07, "store-retired", "store (instruction architecturally executed)"],
-               [0x08, "instruction-retired", "instructions (instruction architecturally executed)"],
-               [0x09, "exception-taken", "exception taken"],
-               [0x0a, "exception-return", "exception return (instruction architecturally executed)"],
-               [0x0b, "cid-write-retired", "write to CONTEXIDR (instruction architecturally executed)"],
-               [0x0c, "pc-write-retired", "software change of the PC (instruction architecturally executed)"],
-               [0x0d, "br-immed-retired", "immediate branch (instruction architecturally executed)"],
-               [0x0e, "br-return-retired", "procedure return (instruction architecturally executed)"],
-               [0x0f, "unaligned-ldst-retired", "unaligned load or store (instruction architecturally executed)"],
-               [0x10, "br-mis-pred", "mispredicted or not predicted branch speculatively executed"],
-               [0x11, "cpu-cycles", "cpu cycles"],
-               [0x12, "br-pred", "predictable branch speculatively executed"],
-               [0x13, "mem-access", "data memory access"],
-               [0x14, "l1-icache", "level 1 instruction cache access"],
-               [0x15, "l1-dcache-wb", "level 1 data cache write-back"],
-               [0x16, "l2-dcache", "level 2 data cache access"],
-               [0x17, "l2-dcache-refill", "level 2 data cache refill"],
-               [0x18, "l2-dcache-wb", "level 2 data cache write-back"],
-               [0x19, "bus-access", "bus access"],
-               [0x1a, "memory-error", "local memory error"],
-               [0x1b, "inst-spec", "operation speculatively executed"],
-               [0x1c, "ttbr-write-retired", "write to TTBR (instruction architecturally executed)"],
-               [0x1d, "bus-cycles", "bus cycle"],
-               # [0x1e, "chain", ""], // Not useful in user space.
-               [0x1f, "l1-dcache-allocate", "level 1 data cache allocation without refill"],
-               [0x20, "l2-dcache-allocate", "level 2 data cache allocation without refill"],
-               [0x21, "br-retired", "branch (instruction architecturally executed)"],
-               [0x22, "br-mis-pred-retired", "mispredicted branch (instruction architecturally executed)"],
-               [0x23, "stall-frontend", "no operation issued due to the frontend"],
-               [0x24, "stall-backend", "no operation issued due to the backend"],
-               [0x25, "l1-dtlb", "level 1 data or unified TLB access"],
-               [0x26, "l1-itlb", "level 1 instruction TLB access"],
-               [0x27, "l2-icache", "level 2 instruction cache access"],
-               [0x28, "l2-icache-refill", "level 2 instruction cache refill"],
-               [0x29, "l3-dcache-allocate", "level 3 data or unified cache allocation without refill"],
-               [0x2a, "l3-dcache-refill", "level 3 data or unified cache refill"],
-               [0x2b, "l3-dcache", "level 3 data or unified cache access"],
-               [0x2c, "l3-dcache-wb", "level 3 data or unified cache write-back"],
-               [0x2d, "l2-dtlb-refill", "level 2 data or unified TLB refill"],
-               [0x2e, "l2-itlb-refill", "level 2 instruction TLB refill"],
-               [0x2f, "l2-dtlb", "level 2 data or unified TLB access"],
-               [0x30, "l2-itlb", "level 2 instruction TLB access"],
+               # Refer to "Table D6-7 PMU common architectural and microarchitectural event numbers" in ARMv8 specification.
+               [0x0000, "sw-incr", "Instruction architecturally executed, Condition code check pass, software increment"],
+               [0x0001, "l1i-cache-refilla", "Level 1 instruction cache refill"],
+               [0x0002, "l1i-tlb-refilla", "Attributable Level 1 instruction TLB refill"],
+               [0x0003, "l1d-cache-refilla", "Level 1 data cache refill"],
+               [0x0004, "l1d-cache", "Level 1 data cache access"],
+               [0x0005, "l1d-tlb-refilla", "Attributable Level 1 data TLB refill"],
+               [0x0006, "ld-retired", "Instruction architecturally executed, Condition code check pass, load"],
+               [0x0007, "st-retired", "Instruction architecturally executed, Condition code check pass, store"],
+               [0x0008, "inst-retired", "Instruction architecturally executed"],
+               [0x0009, "exc-taken", "Exception taken"],
+               [0x000A, "exc-return", "Instruction architecturally executed, Condition code check pass, exception return"],
+               [0x000B, "cid-write-retired", "Instruction architecturally executed, Condition code check pass, write to CONTEXTIDR"],
+               [0x000C, "pc-write-retired", "Instruction architecturally executed, Condition code check pass, software change of the PC"],
+               [0x000D, "br-immed-retired", "Instruction architecturally executed, immediate branch"],
+               [0x000E, "br-return-retired", "Instruction architecturally executed, Condition code check pass, procedure return"],
+               [0x000F, "unaligned-ldst-retired", "Instruction architecturally executed, Condition code check pass, unaligned load or store"],
+               [0x0010, "br-mis-pred", "Mispredicted or not predicted branch Speculatively executed"],
+               [0x0011, "cpu-cycles", "Cycle"],
+               [0x0012, "br-pred", "Predictable branch Speculatively executed"],
+               [0x0013, "mem-access", "Data memory access"],
+               [0x0014, "l1i-cache", "Attributable Level 1 instruction cache access"],
+               [0x0015, "l1d-cache-wb", "Attributable Level 1 data cache write-back"],
+               [0x0016, "l2d-cache", "Level 2 data cache access"],
+               [0x0017, "l2d-cache-refilla", "Level 2 data cache refill"],
+               [0x0018, "l2d-cache-wb", "Attributable Level 2 data cache write-back"],
+               [0x0019, "bus-access", "Bus access"],
+               [0x001A, "memory-error", "Local memory error"],
+               [0x001B, "inst-spec", "Operation Speculatively executed"],
+               [0x001C, "ttbr-write-retired", "Instruction architecturally executed, Condition code check pass, write to TTBR"],
+               [0x001D, "bus-cycles", "Bus cycle"],
+               [0x001E, "chain", "For odd-numbered counters, increments the count by one for each overflow of the preceding even-numbered counter. For even-numbered counters, there is no increment."],
+               [0x001F, "l1d-cache-allocate", "Attributable Level 1 data cache allocation without refill"],
+               [0x0020, "l2d-cache-allocate", "Attributable Level 2 data cache allocation without refill"],
+               [0x0021, "br-retired", "Instruction architecturally executed, branch"],
+               [0x0022, "br-mis-pred-retired", "Instruction architecturally executed, mispredicted branch"],
+               [0x0023, "stall-frontend", "No operation issued due to the frontend"],
+               [0x0024, "stall-backend", "No operation issued due to backend"],
+               [0x0025, "l1d-tlb", "Attributable Level 1 data or unified TLB access"],
+               [0x0026, "l1i-tlb", "Attributable Level 1 instruction TLB access"],
+               [0x0027, "l2i-cache", "Attributable Level 2 instruction cache access"],
+               [0x0028, "l2i-cache-refilla", "Attributable Level 2 instruction cache refill"],
+               [0x0029, "l3d-cache-allocate", "Attributable Level 3 data or unified cache allocation without refill"],
+               [0x002A, "l3d-cache-refilla", "Attributable Level 3 data cache refill"],
+               [0x002B, "l3d-cache", "Attributable Level 3 data cache access"],
+               [0x002C, "l3d-cache-wb", "Attributable Level 3 data or unified cache write-back"],
+               [0x002D, "l2d-tlb-refilla", "Attributable Level 2 data or unified TLB refill"],
+               [0x002E, "l2i-tlb-refilla", "Attributable Level 2 instruction TLB refill"],
+               [0x002F, "l2d-tlb", "Attributable Level 2 data or unified TLB access"],
+               [0x0030, "l2i-tlb", "Attributable Level 2 instruction TLB access"],
+               [0x0031, "remote-access", "Attributable access to another socket in a multi-socket system"],
+               [0x0032, "ll-cache", "Attributable Last Level data cache access"],
+               [0x0033, "ll-cache-missa", "Attributable Last level data or unified cache miss"],
+               [0x0034, "dtlb-walka", "Attributable data or unified TLB access with at least one translation table walk"],
+               [0x0035, "itlb-walka", "Attributable instruction TLB access with at least one translation table walk"],
+               [0x0036, "ll-cache-rd", "Attributable Last Level cache memory read"],
+               [0x0037, "ll-cache-miss-rda", "Attributable Last Level cache memory read miss"],
+               [0x0038, "remote-access-rda", "Attributable memory read access to another socket in a multi-socket system"],
+               [0x0039, "l1d-cache-lmiss-rd", "Level 1 data cache long-latency read miss"],
+               [0x003A, "op-retired", "Micro-operation architecturally executed"],
+               [0x003B, "op-spec", "Micro-operation Speculatively executed"],
+               [0x003C, "stall", "No operation sent for execution"],
+               [0x003D, "stall-slot-backend", "No operation sent for execution on a Slot due to the backend"],
+               [0x003E, "stall-slot-frontend", "No operation send for execution on a Slot due to the frontend"],
+               [0x003F, "stall-slot", "No operation sent for execution on a Slot"],
+               [0x0040, "l1d-cache-rd", "Level 1 data cache read"],
+               [0x4000, "sample-pop", "Sample Population"],
+               [0x4001, "sample-feed", "Sample Taken"],
+               [0x4002, "sample-filtrate", "Sample Taken and not removed by filtering"],
+               [0x4003, "sample-collision", "Sample collided with previous sample"],
+               [0x4004, "cnt-cycles", "Constant frequency cycles"],
+               [0x4005, "stall-backend-mem", "Memory stall cycles"],
+               [0x4006, "l1i-cache-lmiss", "Level 1 instruction cache long-latency miss"],
+               [0x4009, "l2d-cache-lmiss-rd", "Level 2 data cache long-latency read miss"],
+               [0x400A, "l2i-cache-lmiss", "Level 2 instruction cache long-latency miss"],
+               [0x400B, "l3d-cache-lmiss-rd", "Level 3 data cache long-latency read miss"],
+               [0x8002, "sve-inst-retired", "SVE Instructions architecturally executed"],
+               [0x8006, "sve-inst-spec", "SVE Instructions speculatively executed"],
+
+               # Refer to "Table K3.1 ARM recommendations for IMPLEMENTATION DEFINED event numbers" in ARMv8 specification.
+               #[0x0040, "l1d-cache-rd", "Attributable Level 1 data cache access, read"],
+               [0x0041, "l1d-cache-wr", "Attributable Level 1 data cache access, write"],
+               [0x0042, "l1d-cache-refill-rda", "Attributable Level 1 data cache refill, read"],
+               [0x0043, "l1d-cache-refill-wra", "Attributable Level 1 data cache refill, write"],
+               [0x0044, "l1d-cache-refill-inner", "Attributable Level 1 data cache refill, inner"],
+               [0x0045, "l1d-cache-refill-outer", "Attributable Level 1 data cache refill, outer"],
+               [0x0046, "l1d-cache-wb-victim", "Attributable Level 1 data cache Write-Back, victim"],
+               [0x0047, "l1d-cache-wb-clean", "Level 1 data cache Write-Back, cleaning and coherency"],
+               [0x0048, "l1d-cache-inval", "Attributable Level 1 data cache invalidate"],
+               # 0x0049-0x004B - Reserved
+               [0x004C, "l1d-tlb-refill-rda", "Attributable Level 1 data TLB refill, read"],
+               [0x004D, "l1d-tlb-refill-wra", "Attributable Level 1 data TLB refill, write"],
+               [0x004E, "l1d-tlb-rd", "Attributable Level 1 data or unified TLB access, read"],
+               [0x004F, "l1d-tlb-wr", "Attributable Level 1 data or unified TLB access, write"],
+               [0x0050, "l2d-cache-rd", "Attributable Level 2 data cache access, read"],
+               [0x0051, "l2d-cache-wr", "Attributable Level 2 data cache access, write"],
+               [0x0052, "l2d-cache-refill-rda", "Attributable Level 2 data cache refill, read"],
+               [0x0053, "l2d-cache-refill-wra", "Attributable Level 2 data cache refill, write"],
+               # 0x0054-0x0055 - Reserved
+               [0x0056, "l2d-cache-wb-victim", "Attributable Level 2 data cache Write-Back, victim"],
+               [0x0057, "l2d-cache-wb-clean", "Level 2 data cache Write-Back, cleaning and coherency"],
+               [0x0058, "l2d-cache-inval", "Attributable Level 2 data cache invalidate"],
+               # 0x0059-0x005B - Reserved
+               [0x005C, "l2d-tlb-refill-rda", "Attributable Level 2 data or unified TLB refill, read"],
+               [0x005D, "l2d-tlb-refill-wra", "Attributable Level 2 data or unified TLB refill, write"],
+               [0x005E, "l2d-tlb-rd", "Attributable Level 2 data or unified TLB access, read"],
+               [0x005F, "l2d-tlb-wr", "Attributable Level 2 data or unified TLB access, write"],
+               [0x0060, "bus-access-rd", "Bus access, read"],
+               [0x0061, "bus-access-wr", "Bus access, write"],
+               [0x0062, "bus-access-shared", "Bus access, Normal, Cacheable, Shareable"],
+               [0x0063, "bus-access-not-shared", "Bus access, not Normal, Cacheable, Shareable"],
+               [0x0064, "bus-access-normal", "Bus access, normal"],
+               [0x0065, "bus-access-periph", "Bus access, peripheral"],
+               [0x0066, "mem-access-rd", "Data memory access, read"],
+               [0x0067, "mem-access-wr", "Data memory access, write"],
+               [0x0068, "unaligned-ld-spec", "Unaligned access, read"],
+               [0x0069, "unaligned-st-spec", "Unaligned access, write"],
+               [0x006A, "unaligned-ldst-spec", "Unaligned access"],
+               # 0x006B - Reserved
+               [0x006C, "ldrex-spec", "Exclusive operation speculatively executed, LDREX or LDX"],
+               [0x006D, "strex-pass-spec", "Exclusive operation speculatively executed, STREX or STX pass"],
+               [0x006E, "strex-fail-spec", "Exclusive operation speculatively executed, STREX or STX fail"],
+               [0x006F, "strex-spec", "Exclusive operation speculatively executed, STREX or STX"],
+               [0x0070, "ld-spec", "Operation speculatively executed, load"],
+               [0x0071, "st-spec", "Operation speculatively executed, store"],
+               [0x0072, "ldst-spec", "Operation speculatively executed, load or store"],
+               [0x0073, "dp-spec", "Operation speculatively executed, integer data processing"],
+               [0x0074, "ase-spec", "Operation speculatively executed, Advanced SIMD instruction"],
+               [0x0075, "vfp-spec", "Operation speculatively executed, floating-point instruction"],
+               [0x0076, "pc-write-spec", "Operation speculatively executed, software change of the PC"],
+               [0x0077, "crypto-spec", "Operation speculatively executed, Cryptographic instruction"],
+               [0x0078, "br-immed-spec", "Branch speculatively executed, immediate branch"],
+               [0x0079, "br-return-spec", "Branch speculatively executed, procedure return"],
+               [0x007A, "br-indirect-spec", "Branch speculatively executed, indirect branch"],
+               # 0x007B - Reserved
+               [0x007C, "isb-spec", "Barrier speculatively executed, ISB"],
+               [0x007D, "dsb-spec", "Barrier speculatively executed, DSB"],
+               [0x007E, "dmb-spec", "Barrier speculatively executed, DMB"],
+               # 0x007F-0x0080 - Reserved
+               [0x0081, "exc-undef", "Exception taken, Other synchronous"],
+               [0x0082, "exc-svc", "Exception taken, Supervisor Call"],
+               [0x0083, "exc-pabort", "Exception taken, Instruction Abort"],
+               [0x0084, "exc-dabort", "Exception taken, Data Abort and SError"],
+               # 0x0085 - Reserved
+               [0x0086, "exc-irq", "Exception taken, IRQ"],
+               [0x0087, "exc-fiq", "Exception taken, FIQ"],
+               [0x0088, "exc-smc", "Exception taken, Secure Monitor Call"],
+               # 0x0089 - Reserved
+               [0x008A, "exc-hvc", "Exception taken, Hypervisor Call"],
+               [0x008B, "exc-trap-pabort", "Exception taken, Instruction Abort not Taken locallyb"],
+               [0x008C, "exc-trap-dabort", "Exception taken, Data Abort or SError not Taken locallyb"],
+               [0x008D, "exc-trap-other", "Exception taken, Other traps not Taken locallyb"],
+               [0x008E, "exc-trap-irq", "Exception taken, IRQ not Taken locallyb"],
+               [0x008F, "exc-trap-fiq", "Exception taken, FIQ not Taken locallyb"],
+               [0x0090, "rc-ld-spec", "Release consistency operation speculatively executed, Load-Acquire"],
+               [0x0091, "rc-st-spec", "Release consistency operation speculatively executed, Store-Release"],
+               # 0x0092-0x009F - Reserved
+               [0x00A0, "l3d-cache-rd", "Attributable Level 3 data or unified cache access, read"],
+               [0x00A1, "l3d-cache-wr", "Attributable Level 3 data or unified cache access, write"],
+               [0x00A2, "l3d-cache-refill-rda", "Attributable Level 3 data or unified cache refill, read"],
+               [0x00A3, "l3d-cache-refill-wra", "Attributable Level 3 data or unified cache refill, write"],
+               # 0x00A4-0x00A5 - Reserved
+               [0x00A6, "l3d-cache-wb-victim", "Attributable Level 3 data or unified cache Write-Back, victim"],
+               [0x00A7, "l3d-cache-wb-clean", "Attributable Level 3 data or unified cache Write-Back, cache clean"],
+               [0x00A8, "l3d-cache-inval", "Attributable Level 3 data or unified cache access, invalidate"],
                ]
   generated_str = ""
   for item in raw_types: