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| author | Martin Storsjo <martin@martin.st> | 2018-01-24 10:14:52 +0000 |
|---|---|---|
| committer | Yi Kong <yikong@google.com> | 2018-03-28 19:47:56 -0700 |
| commit | c74e47c3229ee75b3d6db0f8adaf913256d2ab12 (patch) | |
| tree | 90a21924bbf25dc01c45c6d13ee7d6646bbce58a | |
| parent | ac596966cd96f9a0b781b96e7eaf1566d970b88c (diff) | |
| download | compiler-rt-c74e47c3229ee75b3d6db0f8adaf913256d2ab12.tar.gz | |
[builtins] Align addresses to cache lines in __clear_cache for aarch64
This makes sure that the last cache line gets invalidated properly.
This matches the example code at
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/BABJDBHI.html,
and also matches what libgcc does.
Differential Revision: https://reviews.llvm.org/D42196
git-svn-id: https://llvm.org/svn/llvm-project/compiler-rt/trunk@323315 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/builtins/clear_cache.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/builtins/clear_cache.c b/lib/builtins/clear_cache.c index 640cb7572..5e7284a63 100644 --- a/lib/builtins/clear_cache.c +++ b/lib/builtins/clear_cache.c @@ -156,12 +156,14 @@ void __clear_cache(void *start, void *end) { * uintptr_t in case this runs in an IPL32 environment. */ const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15); - for (addr = xstart; addr < xend; addr += dcache_line_size) + for (addr = xstart & ~(dcache_line_size - 1); addr < xend; + addr += dcache_line_size) __asm __volatile("dc cvau, %0" :: "r"(addr)); __asm __volatile("dsb ish"); const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15); - for (addr = xstart; addr < xend; addr += icache_line_size) + for (addr = xstart & ~(icache_line_size - 1); addr < xend; + addr += icache_line_size) __asm __volatile("ic ivau, %0" :: "r"(addr)); __asm __volatile("isb sy"); #elif defined (__powerpc64__) |