diff options
Diffstat (limited to 'gcc/config/riscv/vector.md')
| -rw-r--r-- | gcc/config/riscv/vector.md | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index f66ffebba24..79c4a4bda53 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7451,7 +7451,7 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_fix:<VCONVERT> - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")) (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vfcvt.rtz.x<u>.f.v\t%0,%3%p1" @@ -7459,8 +7459,8 @@ (set_attr "mode" "<MODE>")]) (define_insn "@pred_<float_cvt><mode>" - [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr") + (if_then_else:V_VLSF (unspec:<VM> [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") (match_operand 4 "vector_length_operand" " rK, rK, rK, rK") @@ -7471,9 +7471,9 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (any_float:VF + (any_float:V_VLSF (match_operand:<VCONVERT> 3 "register_operand" " vr, vr, vr, vr")) - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vfcvt.f.x<u>.v\t%0,%3%p1" [(set_attr "type" "vfcvtitof") @@ -7531,8 +7531,8 @@ (set_attr "mode" "<VNCONVERT>")]) (define_insn "@pred_widen_<float_cvt><mode>" - [(set (match_operand:VF 0 "register_operand" "=&vr, &vr") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand" "=&vr, &vr") + (if_then_else:V_VLSF (unspec:<VM> [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1") (match_operand 4 "vector_length_operand" " rK, rK") @@ -7541,9 +7541,9 @@ (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (any_float:VF + (any_float:V_VLSF (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")) - (match_operand:VF 2 "vector_merge_operand" " vu, 0")))] + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfwcvt.f.x<u>.v\t%0,%3%p1" [(set_attr "type" "vfwcvtitof") @@ -7610,7 +7610,7 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_fix:<VNCONVERT> - (match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr")) + (match_operand:V_VLSF 3 "register_operand" " 0, 0, 0, 0, vr, vr")) (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR" "vfncvt.rtz.x<u>.f.w\t%0,%3%p1" |