From 19cc1fb43090078b97ffc1ca0e5b74c38f258c05 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek <kparzysz@codeaurora.org>
Date: Thu, 28 Apr 2016 16:43:16 +0000
Subject: [Hexagon] Define certain aliases for vector instructions

Specifically:
  Vd = #0   -> Vd = vxor(Vd, Vd)
  Vdd = #0  -> Vdd.w = vsub(Vdd.w, Vdd.w)
  Vdd = Vss -> Vdd = vcombine(Vss.H, Vss.L)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267901 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/MC/Hexagon/v60-misc.s | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 test/MC/Hexagon/v60-misc.s

(limited to 'test/MC/Hexagon')

diff --git a/test/MC/Hexagon/v60-misc.s b/test/MC/Hexagon/v60-misc.s
new file mode 100644
index 00000000000..335f02983c0
--- /dev/null
+++ b/test/MC/Hexagon/v60-misc.s
@@ -0,0 +1,10 @@
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mattr=+hvx -filetype=obj %s | llvm-objdump -arch=hexagon -mcpu=hexagonv60 -mattr=+hvx -d - | FileCheck %s
+
+# CHECK: 1c2eceee { v14 = vxor(v14,{{ *}}v14) }
+v14 = #0
+
+# CHECK: 1c80c0a0 { v1:0.w = vsub(v1:0.w,v1:0.w) }
+v1:0 = #0
+
+# CHECK: 1f42c3e0 { v1:0 = vcombine(v3,v2) }
+v1:0 = v3:2
-- 
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