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2020-03-18Split debug.h into another panic.hWenhao Wang
BoringSSL has a static function called hexdump, which conflicts the one declared in debug.h. debug.h is included indirectly through assert.h. And the function "panic" is the only function used by assert.h. So we create a panic.h that contains function panic such that debug.h is exluded from assert.h. Bug: 151183243 Change-Id: I83d905048832de12e78702ac0b4c6acafd1c6572
2020-03-16Fix no-SMP builds with GICv3Matthew Maurer
The previous GICv3 support code assumed that SMP definitions would always be configured, but this is not the case when SMP is disabled. Bug: 143179093 Change-Id: I2c43c72b96092a3e9add6844951f98ecf327e97e
2020-03-16arm_gic: Trigger SGIs with GICv3 affinity routingMatthew Maurer
GICv3 uses a different format for the SGIR register, defining writes to it based on affinity values. This adds support for this type of routing, and allows platform-specific override of the mapping from logical cpu number to affinities via arch_cpu_num_to_gic_affinities in case an architecture has a more exotic affinity layout. A platform will need to define this if they are using GICv3 with affinity routing, and have a custom arch_curr_cpu_num implementation. Bug: 143179093 Change-Id: I7896cc88c910144d0df67c590ae926707c8afa55
2020-03-13arm_gic: Enable SGIs when registering handlerMatthew Maurer
Previously, we relied on SGIs to either be unmaskable or firmware to unmask them for us. Instead, we now explicitly enable SGIs when registered as we cannot rely on their maskability. Bug: 143179093 Change-Id: Iad455578dd977d32b3656164297351cff2206053
2020-03-05[arch][mmu] Increase page count from uint to size_tTri Vo
arch_mmu_[un]map takes uint count of pages to map/unmap. Change type of count argument to size_t. We need this to reserve regions of memory that are 2^32 pages or larger, e.g. HWASan shadow memory. Bug: 148877030 Change-Id: Ic262134a095a03fc622499adfb6d762d87c61143
2020-03-02Replace rand() with rand_get_int()Wenhao Wang
Use new interface to get random integer. Bug: 149518090 Change-Id: I091c903b0bc527d6879ac95006230c4278279e86
2020-02-21Rename function nameWenhao Wang
CSPRNG has function named rand_add_entropy, which causes a name collision. We rename it as libc_trusty_rand_add_entropy, which will be called by CSPRNG's rand_add_entropy. Bug: 149958771 Change-Id: I09b7213b52376805d21651535ad2d5b5f1564cf7
2020-02-05make: link with ld.lldTri Vo
lk.bin size for generic-arm64 target shrank from 1466416 to 1425456. Bug: 129880406 Test: build --skip-tests qemu-generic-arm64-test-debug && \ ./build-root/build-qemu-generic-arm64-test-debug/run Change-Id: Ia8a4e922c0eb836fe371c3809ac5d1ee5f5bae5e
2020-02-03[dev][interrupt][arm_gic] Fix UBSan panic.Andrew Walbran
~0 is a signed integer so should not be passed to an unsigned parameter. Change-Id: I404981214432d52d31bd12a7419f7900ae115427
2020-01-31[clang][include][compiler.h] Enable __WARN_UNUSED_RESULT and STATIC_ASSERTArve Hjønnevåg
Clang supports both of these. __WARN_UNUSED_RESULT did was a nop, STATIC_ASSERT shows a more detailed message now. Bug: None Change-Id: I85fd3d235636ab629f0917672f3e81e38ea97a2e
2020-01-31Make GIC FIQ suspend/resume UBSan cleanMatthew Maurer
~0 creates a signed int -1, which then gets cast to an unsigned int, triggering errors. Bug: 129300035 Change-Id: I441e3b9499492084be07de6962383abf7fe92c0f
2020-01-06[arch] Do not search for GCCNick Bray
Our toolchains should always be explicitly specified. Bug: 147251811 Change-Id: I50c34d07018032136474d92bdd5e9a61e7fb4f9a
2019-12-13app: timertest: Add kernel timer testArve Hjønnevåg
Bug: 131099439 Change-Id: I83404469b5cdf02bd9ceb47902da6314a995476d
2019-12-13[kernel][timer] Fix thread_sleep to not return with timer running on stackArve Hjønnevåg
Call timer_cancel_sync before returning from thread_sleep to ensure the timer allocated on the stack is not still running. Fixes random stack corruption in code running after thread_sleep returns. Bug: 145560454 Change-Id: I1832b09b9e40fbb650ab613ca1f47cae5f6e3546
2019-12-13[kernel][timer] Add debug assert after callback returnsArve Hjønnevåg
Checks that the timer struct has not been freed and corrupted while the callback was running. Bug: 145226667 Change-Id: I753e230932d8f612bfcff5cfd4bd09c462b9827d
2019-12-10Allow the use of array designators in C++Nick Bray
Bug: 139945549 Change-Id: I0a4c52db23be32e26818513b2267cab41c1072af
2019-12-09[kernel][timer] Fix crash caused by timer_cancel.Arve Hjønnevåg
If timer_cancel is called while the timer callback is about to run on another cpu, the timer interrupt will crash jumping to the now NULL callback pointer. If the timer is freed after timer_cancel returns similar crashes are also possible. Add timer_cancel_sync, which waits for the timer callback to return, and use it where the timer could be running on another cpu. Bug: 145226667 Change-Id: Id3e43dfa54a9460440c7312af226e04e42953abc
2019-12-09[kernel][timer] Convert timer api to use nanosecondsArve Hjønnevåg
Replace lk_time_t with lk_time_ns_t in timer api and update callers. Add thread_sleep_ns function to allow threads to sleep less than one millisecond. Other thread apis are unchanged and still use millisecond timeouts. Since the timer now uses the nanosecond clock, reading the nanosecond clock before and after a thread sleep will now always show a sleep duration of at least the requested time. (Note that this does not mean that an external observer will not see a shorter sleep duration as the hardware clock may not be nanosecond accurate). Bug: 131099439 Change-Id: Ia93d1cdd5064b45ae9c18c515d104814c5191c4a
2019-12-06More fixes for -Wimplicit-fallthroughNick Bray
Bug: 139945549 Change-Id: Ia0495b1b32be87f4cd4b1a4e34cb9f931b8493fa
2019-12-05[arch][arm64] Annotate for -Wimplicit-fallthroughNick Bray
Bug: 139945549 Change-Id: I649a4ec50cee25cb0d465854ffaf86ba9dc59fa2
2019-12-04[dev][interrupt] Add suspend/resume hooks for GICv3Michael Ryleev
Bug: 138743238 Change-Id: I103142fabfc6e050689ef0cc8c56d77f1e0cf063
2019-11-26[dev][interrupt][x86_lapic] Add sm_intc_enable_interrupts stubZhong,Fangjian
Add sm_intc_enable_interrupts stub to fix build issue. Bug: 119111590 Change-Id: I9c47bbbbab9557ec1061d4fd6748298ea355c3f9
2019-11-21[dev][interrupt][arm_gic] gicv3 doorbell interrupt supportArve Hjønnevåg
Use a non-secure doorbell interrupt on gicv3 with libsm. Use secure group 1 interrupt for trusty and signal the doorbell interrupt if we get a trusty interrupt when the non-secure os is running. Bug: 122357256 Change-Id: I1aaf928b49a9660c714e16dd3fd456dac50b6e85
2019-11-21[arch][arm] Fix fiq handler for ARM_MERGE_FIQ_IRQArve Hjønnevåg
When entering most exceptions on arm, IRQs are masked but FIQs are left unmasked. Simulate the behavior we want by looking at the IRQ mask in SPSR on FIQ entry and restart with FIQs masked as well if only IRQs were masked. This prevents corrupting the LR and SPSR values for the interrupted context as FIQs can trigger a context switch when ARM_MERGE_FIQ_IRQ is enabled. Bug: 122357256 Change-Id: Ice0f5bee13bc4a52eba3a82ce945c9c693d9b224
2019-11-21[dev][interrupt] Add initial support for GICv3Michael Ryleev
This CL mostly adds support for GICv3 for non-TZ usecase but some changes are also applicable for TZ. The later might require more work. Bug: 138743238 Change-Id: Ie24fd6b9ca6d1692df15fc163b6189982a05c472
2019-11-21[dev][interrupt] Add definition of GICv3 registersMichael Ryleev
Bug: 138743238 Change-Id: Ie817f2b89964987e7435ebaa1286f84eb7fd4096
2019-11-21[arch][arm] Add an API to read and write 64-bit cp15 registersMichael Ryleev
Bug: 138743238 Change-Id: Ic6cd97f2b7d291b91b9c873e8819988bafa08573
2019-11-21[dev][interrupt] Move gic registers to separate includeMichael Ryleev
Bug: 138743238 Change-Id: I76a0d1724219d0eeb27c358f3e6b3a4e7f4771e6
2019-11-21[arch][arm64] Modify GIC interface to read/writeHaoran.Wang
Modify all GIC registers access interface to the read/write ones. This will make the interface able to be change for both memory map access and system registers access. Bug: 138743238 Change-Id: Ic7891d009fa3fca9ab6b8b154eda07e91e2a7bba Signed-off-by: Haoran.Wang <elven.wang@nxp.com>
2019-11-19vmm/pmm: Replace reflist-related typedefs with struct typesNick Bray
Bug: 144593477 Change-Id: I3172b6a69e5b90d76efb1a9870fdd50e6ac37d1e
2019-11-19[dev][interrupt] Rename "smc32_args_t" to "struct smc32_args"Nick Bray
Bug: 144593477 Change-Id: Ib8cf2c3efb1215e10821a9a537c3bcb4519f3e99
2019-11-06[arch][x86] Add phony target to ensure linkerscript regenerationZhong,Fangjian
Bug: 119111590 Change-Id: I20d3423422609b9d0dadf35d5c9d2eaac5292032
2019-10-30vmm: Store regions in a binary search tree instead of a list.Arve Hjønnevåg
Convert vmm_region to a search tree. TODO: Optimize ASLR to not walk the entire tree in the common insert case. Bug: 141331978 Change-Id: I6eeacd9817607496df89b091a17f3c46edf6d15d
2019-10-30bstree: Add balancing codeArve Hjønnevåg
Add self balancing code. Balance tree after insert and delete according to WAVL rules. Bug: 141329802 Change-Id: Ic8d43b3b4b173c7ecdb0c48a2c58de0a28d501c4
2019-10-30Add binary search treeArve Hjønnevåg
Add api, basic implementation and tests. TODO: Add balancing code Bug: 141329802 Change-Id: I819bd2ffc35d139f1f6f357eb71bba839c7b2bd9
2019-10-25[kernel][timer] Replace lk_bigtime_t with lk_time_ns_tArve Hjønnevåg
Replace lk_bigtime_t with lk_time_ns_t in preparation for supporting higher resolution timers. lk_bigtime_t was 64 bits, but stored micro seconds. Storing nano seconds gives us hundreds of years range and most hardware has timer ticks shorter than the 1us we could return before. Bug: 131099439 Change-Id: I4b9bda393c3a2a0eb81798a7e935b8701d099f8f
2019-10-25[dev][timer][arm_generic] Fix ubsan errorsArve Hjønnevåg
Bug: 129300035 Change-Id: Idcc916cdfc0a343bc6f1355699028b8cf1c0f752
2019-10-24[arch][x86] Bug fix on cpuid methodZhong,Fangjian
Correct register usage in cpuid and cpuid_cound methods Bug: 119111590 Change-Id: I489f12d585d7c9bd3248a044b23ed62661d2c2de
2019-10-11[arch][arm/arm64] Allow CPU number overrideMatthew Maurer
On some platforms, our default mechanism for generating cpu numbers will not generate a non-intersecting, contiguous list regardless of what values our compile-time parameters are set to. This patch moves those mechanisms into weak functions so that the platform can override them with a custom mechanism if necessary. Bug: 118744765 Change-Id: I0dd16f287afdc9b8a723cad107862c178e3344a0
2019-09-30[arch][x86] Add x86 cache operation functionsZhong,Fangjian
Accroding to Intel Software Developer's Manual, in the L1 data cache and L2/L3 unified caches, the MESI (modified, exclusive, shared, invalid) cache protocol maintains consistency with caches of other processors. With MESI support, nothing to do when sync cache range. To peripheral, invalidate and clean cache range are used to ensure data shared between processor and peripheral always synced. Bug: 119111590 Change-Id: I66583bf9aa7da9644ea4bd4f1ce0565d3be14987
2019-09-30[arch][x86] Add arch_set_user_tls supportZhong,Fangjian
FS base is used to store task local storage. To keep FS base for each user level applications are separated, FS base would be switched during context switch. Bug: 119111590 Change-Id: I583ec84b3acb755bfa5e2733076ba17a54bf0397 Signed-off-by: Zhang, Qi <qi1.zhang@intel.com>
2019-09-30[arch][x86] Add explicitly allow and disallow SMAP methodsZhong,Fangjian
With supervisor-mode access prevention (SMAP) enabled, SMAP should be explicitly allowed before kernel level tries to access user page, and disallowed after user page has been accssed. Bug: 119111590 Change-Id: I2f3bcff9493c52149d6fbcc4a4546815c34f7146
2019-09-27[dev][interrupt] Add x86 interrupt handling supportZhong,Fangjian
Generic-x86_64 utilizes Local APIC to handle interrupt. In order to support PIT timer hardware resource on QEMU platform, PIC will be used and remapped, and IRQ0 in PIC1 will be unmasked only for PIT timer. All other IRQs in PIC1 and PIC2 are masked. Bug: 119111590 Change-Id: Ia44bd67911b529e0c6554b70f144ebfa0761efcc
2019-09-27[arch][x86] Add get TSS base supportZhong,Fangjian
syscall stack needs to be set in TSS descriptor before launch user level application, provide API to support get TSS base. Bug: 119111590 Change-Id: I527fe51cb79289adf2de8864caa5f66deeb3d34f
2019-09-25[arch][x86] Update architecture initialization processZhong,Fangjian
Update architecture initializaiton process to setup per cpu states, and setup gs/fs support for user level. Bug: 119111590 Change-Id: Ife1360c20495450abe5ef4f4501763b6d65cbf28
2019-09-25[dev][interrupt][x86_lapic] Bug fix on X1 Local APIC write registerZhong,Fangjian
Correct usage of writel function call. Bug: 119111590 Change-Id: Iced72324f7037e12acb5d513de01c0e0489ddc84
2019-09-25[arch][x86] Add aspace supportZhong,Fangjian
Add aspace support for both kernel and user level. Bug: 119111590 Change-Id: I4c7f8406224db494334254b96275c43daeb8796d
2019-09-25[arch][x86] Align memory mapping mechanism to ARM solutionZhong,Fangjian
1. Remove KERNEL_ASPACE_BASE usage in boot strap code, since KERNEL_ASPACE_BASE should used in run time only, use KERNEL_BASE instead. 2. Remove fixed 1GB mapping on boot strap code, memory mapping covers up to upper memory provided by multiboot info. Multiboot info is provided by bootloader. 3. Remove 64GB mapping starts from KERNEL_ASPACE_BASE. Mapping starts from KERNEL_ASPACE_BASE should be created on demand on run time. Bug: 119111590 Change-Id: I07da8c2c373d41c4c2ba759ef82e1983587e06eb
2019-09-24vmm/pmm: Move allocated page tracking from vmm to pmmArve Hjønnevåg
Add new pmm api to allocate a vmm_obj and use this from vmm to allocate memory instead of tracking individual pages. Bug: 141138913 Change-Id: Ic00ab8f5d8a5f7aa295e8de52466b420aaf57bed
2019-09-23pmm: Share more code between contiguous and non-contiguous allocatorsArve Hjønnevåg
Also drop support for partially successful allocation so that either all requested pages are allocated or none. Bug: 139700856 Change-Id: I80fb29f2141b9b15b83c1aa3e56a67ddb99b44e2
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-06 12:25:39 +0000