From 420c557c6eb5484958dd3fc3c44dda8f53e7fa00 Mon Sep 17 00:00:00 2001
From: Travis Geiselbrecht <geist@foobox.com>
Date: Tue, 22 Sep 2015 14:39:11 -0700
Subject: WIP fpu bits

---
 platform/stm32f7xx/init.c   | 4 ----
 platform/stm32f7xx/rules.mk | 2 +-
 2 files changed, 1 insertion(+), 5 deletions(-)

(limited to 'platform')

diff --git a/platform/stm32f7xx/init.c b/platform/stm32f7xx/init.c
index 9e05cf6c..1123e094 100644
--- a/platform/stm32f7xx/init.c
+++ b/platform/stm32f7xx/init.c
@@ -41,10 +41,6 @@ extern const sdram_config_t target_sdram_config;
 
 void SystemInit(void)
 {
-    /* FPU settings ------------------------------------------------------------*/
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
-#endif
     /* Reset the RCC clock configuration to the default reset state ------------*/
     /* Set HSION bit */
     RCC->CR |= (uint32_t)0x00000001;
diff --git a/platform/stm32f7xx/rules.mk b/platform/stm32f7xx/rules.mk
index b1f862d8..05e762ac 100644
--- a/platform/stm32f7xx/rules.mk
+++ b/platform/stm32f7xx/rules.mk
@@ -10,7 +10,7 @@ MEMBASE ?= 0x20010000
 MEMSIZE ?= 0x40000
 
 ARCH := arm
-ARM_CPU := cortex-m7
+ARM_CPU := cortex-m7-fpu-sp-d16
 
 ifeq ($(STM32_CHIP),stm32f746)
 GLOBAL_DEFINES += STM32F746xx
-- 
cgit v1.2.3


From 8c506eba611b01e5922ed09d928a8f1f8b3eefb3 Mon Sep 17 00:00:00 2001
From: Travis Geiselbrecht <geist@foobox.com>
Date: Mon, 28 Mar 2016 19:57:17 -0700
Subject: [arch][arm] fix up the cortex-m fpu code to build again on all three
 combinations of arch/fpu

cortex-m0 with no fpu and limited instructions
cortex-m3+ with no fpu
cortex-m4/m7 with fpu

Untested if this still works.
---
 platform/stellaris/rules.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'platform')

diff --git a/platform/stellaris/rules.mk b/platform/stellaris/rules.mk
index b6aef260..9c5cf39b 100644
--- a/platform/stellaris/rules.mk
+++ b/platform/stellaris/rules.mk
@@ -10,7 +10,7 @@ ifeq ($(STELLARIS_CHIP),LM4F120H5QR)
 MEMSIZE ?= 32768
 MEMBASE := 0x20000000
 ROMBASE := 0x00000000
-ARM_CPU := cortex-m3
+ARM_CPU := cortex-m4f
 GLOBAL_DEFINES += TARGET_IS_BLIZZARD_RA1
 endif
 ifeq ($(STELLARIS_CHIP),LM3S6965)
-- 
cgit v1.2.3


From cbb6e051278da5d234fb58e77c70b4755825f954 Mon Sep 17 00:00:00 2001
From: Travis Geiselbrecht <geist@foobox.com>
Date: Tue, 29 Mar 2016 00:02:54 -0700
Subject: [arm-m][fpu] fix fpu context switch to not overly trigger fpused
 tracking

Make sure stellaris builds with fpu enabled
---
 platform/stellaris/rules.mk | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'platform')

diff --git a/platform/stellaris/rules.mk b/platform/stellaris/rules.mk
index 9c5cf39b..b602342c 100644
--- a/platform/stellaris/rules.mk
+++ b/platform/stellaris/rules.mk
@@ -11,7 +11,9 @@ MEMSIZE ?= 32768
 MEMBASE := 0x20000000
 ROMBASE := 0x00000000
 ARM_CPU := cortex-m4f
-GLOBAL_DEFINES += TARGET_IS_BLIZZARD_RA1
+GLOBAL_DEFINES += \
+    TARGET_IS_BLIZZARD_RA1 \
+    __FPU_PRESENT=1
 endif
 ifeq ($(STELLARIS_CHIP),LM3S6965)
 MEMSIZE ?= 65536
-- 
cgit v1.2.3