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| author | Subash Lakkimsetti <x0091084@ti.com> | 2017-01-17 14:48:29 -0600 |
|---|---|---|
| committer | subash Lakkimsetti <x0091084@ti.com> | 2017-02-21 12:00:41 -0500 |
| commit | 97c89e23c89917a565deb851bf72db5eec4b6b11 (patch) | |
| tree | 21eca227a9cef0c27338f9a12cadf9f5aad19ed3 | |
| parent | fa0dd3ffc2c904766254815918f57e6085c9bc70 (diff) | |
| download | jacinto6evm-97c89e23c89917a565deb851bf72db5eec4b6b11.tar.gz | |
DRA7XX - Late Attach - Use reserved memory for IOUMM table
IOMMU Table memory for remote cores is carved out. With page table
allocation from end of CMA-POOL from u-boot, kernel treats this region
as free memory. This causes an MMU faults on remote cores in low memory
situations.
IOMMU table region 0xbfc00000 - 0xbfd00000 has to carved out with
reserved_mem in kernel.
Kernel commit details: 41a8818d9675804bd3054395ca893c99bfce88be
http://review.omapzoom.org/#/c/38093/
Change-Id: I09ec250f3a8ec4a934ad73437981c5dea8930a34
Signed-off-by: Subash Lakkimsetti <x0091084@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
| -rw-r--r-- | board/ti/dra7xx/lateattach.c | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/board/ti/dra7xx/lateattach.c b/board/ti/dra7xx/lateattach.c index 797ed6bb7a..0db28aef6b 100644 --- a/board/ti/dra7xx/lateattach.c +++ b/board/ti/dra7xx/lateattach.c @@ -160,6 +160,11 @@ #define DRA7_RPROC_CMA_SIZE_DSP1 0x04000000 #define DRA7_RPROC_CMA_SIZE_DSP2 0x00800000 +#define DRA7_PGTBL_BASE_IPU1 0xbfc00000 +#define DRA7_PGTBL_BASE_IPU2 0xbfc08000 +#define DRA7_PGTBL_BASE_DSP1 0xbfc10000 +#define DRA7_PGTBL_BASE_DSP2 0xbfc18000 + /* * The page table (32 KB) is placed at the end of the CMA reserved area. * It's possible that this location is needed by the firmware (in which @@ -1103,7 +1108,7 @@ struct rproc ipu1_config = { .num_iommus = 1, .cma_base = DRA7_RPROC_CMA_BASE_IPU1, .cma_size = DRA7_RPROC_CMA_SIZE_IPU1, - .page_table_addr = 0, + .page_table_addr = DRA7_PGTBL_BASE_IPU1, .mmu_base_addr = {0x58882000, 0}, .load_addr = IPU1_LOAD_ADDR, .core_name = "IPU1", @@ -1124,7 +1129,7 @@ struct rproc ipu2_config = { .num_iommus = 1, .cma_base = DRA7_RPROC_CMA_BASE_IPU2, .cma_size = DRA7_RPROC_CMA_SIZE_IPU2, - .page_table_addr = 0, + .page_table_addr = DRA7_PGTBL_BASE_IPU2, .mmu_base_addr = {0x55082000, 0}, .load_addr = IPU2_LOAD_ADDR, .core_name = "IPU2", @@ -1145,7 +1150,7 @@ struct rproc dsp1_config = { .num_iommus = 2, .cma_base = DRA7_RPROC_CMA_BASE_DSP1, .cma_size = DRA7_RPROC_CMA_SIZE_DSP1, - .page_table_addr = 0, + .page_table_addr = DRA7_PGTBL_BASE_DSP1, .mmu_base_addr = {0x40D01000, 0x40D02000}, .load_addr = DSP1_LOAD_ADDR, .core_name = "DSP1", @@ -1166,7 +1171,7 @@ struct rproc dsp2_config = { .num_iommus = 2, .cma_base = DRA7_RPROC_CMA_BASE_DSP2, .cma_size = DRA7_RPROC_CMA_SIZE_DSP2, - .page_table_addr = 0, + .page_table_addr = DRA7_PGTBL_BASE_DSP2, .mmu_base_addr = {0x41501000, 0x41502000}, .load_addr = DSP2_LOAD_ADDR, .core_name = "DSP2", @@ -1218,10 +1223,6 @@ u32 spl_boot_core(u32 core_id) if (cfg->start_clocks) cfg->start_clocks(core_id, cfg); - /* Calculate the page table address */ - cfg->page_table_addr = - cfg->cma_base + cfg->cma_size - (PAGE_TABLE_SIZE); - debug("Configuring IOMMU\n"); /* Configure the MMU */ |