RVC: Enable display of RVC

Prior to this change, LCD display is powered on by vision SDK
on IPU (M4). When single stage boot is used, there is a conflict
of I2C because Linux Kernel will reset I2C while RVC is still trying
to perform configuration. On dual stage boot, this issue is not
happening because RVC would have done the LCD configuration prior
to Linux kernel reset to happen.

This commit move the LCD power on configuration from IPU to u-boot.
There is a dependency commit id on vision sdk along with this commit.
The change in vision sdk is to disable to call Lcd_turnOn() in
\vision_sdk\examples\tda2xx\src\usecases\common\chains_common.c::
ChainsCommon_StartDisplayDevice().

Ported from http://review.omapzoom.org/37778 -
    spl: Enable display of splash screen

Change-Id: I7c2a48fb236e5713f782520efca3a8a50f5f5758
Signed-off-by: Buddy Liong <a0270631@ti.com>

7 files changed, 614 insertions, 1 deletions

diff --git a/board/ti/dra7xx/Makefile b/board/ti/dra7xx/Makefile
index c6b9c52256..0a3180603a 100644
--- a/board/ti/dra7xx/Makefile
+++ b/board/ti/dra7xx/Makefile
@@ -7,4 +7,4 @@
 
 obj-y	:= evm.o
 
-obj-$(CONFIG_LATE_ATTACH) += lateattach.o
+obj-$(CONFIG_LATE_ATTACH) += lateattach.o display.o
diff --git a/board/ti/dra7xx/display.c b/board/ti/dra7xx/display.c
new file mode 100644
index 0000000000..fdbb5460ca
--- /dev/null
+++ b/board/ti/dra7xx/display.c
@@ -0,0 +1,451 @@
+/*
+ * Code to configure the LCD connected to DRA7xx EVM.
+ *
+ * Copyright (C) 2016 Texas Instruments Incorporated, <www.ti.com>
+ * Author: Venkateswara Rao Mandela <venkat.mandela@ti.com>
+ *
+ * Based on the LCD and DSS drivers in the 3.14 kernel.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "display.h"
+
+/* Choose VID1 or VID3 for the DSS pipeline */
+#define DISPC_MACRO(REGNAME) DISPC_VID3_##REGNAME
+
+#define TLC_NAME		"tlc59108"
+#define TLC_I2C_ADDR		0x40
+
+#define TLC59108_MODE1		0x00
+#define TLC59108_PWM2		0x04
+#define TLC59108_LEDOUT0	0x0c
+#define TLC59108_LEDOUT1	0x0d
+
+enum omap_dss_signal_level {
+	OMAPDSS_SIG_ACTIVE_LOW,
+	OMAPDSS_SIG_ACTIVE_HIGH,
+};
+
+enum omap_dss_signal_edge {
+	OMAPDSS_DRIVE_SIG_FALLING_EDGE,
+	OMAPDSS_DRIVE_SIG_RISING_EDGE,
+};
+
+struct omap_video_timings {
+	/* Unit: pixels */
+	u16 x_res;
+	/* Unit: pixels */
+	u16 y_res;
+	/* Unit: Hz */
+	u32 pixelclock;
+	/* Unit: pixel clocks */
+	u16 hsw;	/* Horizontal synchronization pulse width */
+	/* Unit: pixel clocks */
+	u16 hfp;	/* Horizontal front porch */
+	/* Unit: pixel clocks */
+	u16 hbp;	/* Horizontal back porch */
+	/* Unit: line clocks */
+	u16 vsw;	/* Vertical synchronization pulse width */
+	/* Unit: line clocks */
+	u16 vfp;	/* Vertical front porch */
+	/* Unit: line clocks */
+	u16 vbp;	/* Vertical back porch */
+
+	/* Vsync logic level */
+	enum omap_dss_signal_level vsync_level;
+	/* Hsync logic level */
+	enum omap_dss_signal_level hsync_level;
+	/* Interlaced or Progressive timings */
+	bool interlace;
+	/* Pixel clock edge to drive LCD data */
+	enum omap_dss_signal_edge data_pclk_edge;
+	/* Data enable logic level */
+	enum omap_dss_signal_level de_level;
+	/* Pixel clock edges to drive HSYNC and VSYNC signals */
+	enum omap_dss_signal_edge sync_pclk_edge;
+};
+
+struct tlc_board_data {
+	struct omap_video_timings timings;
+	const unsigned int *init_seq;
+	unsigned init_seq_len;
+};
+
+static const unsigned int tlc_7_inch_init_seq[] = {
+	/* Init the TLC chip */
+	TLC59108_MODE1, 0x01,
+	/*
+	 * set LED1(AVDD) to ON state(default), enable LED2 in PWM mode, enable
+	 * LED0 to OFF state
+	 */
+	TLC59108_LEDOUT0, 0x21,
+	/* set LED2 PWM to full freq */
+	TLC59108_PWM2, 0xff,
+	/* set LED4(UPDN) and LED6(MODE3) to OFF state */
+	TLC59108_LEDOUT1, 0x11,
+};
+
+static const unsigned int tlc_10_inch_init_seq[] = {
+	/* Init the TLC chip */
+	TLC59108_MODE1, 0x01,
+	/* LDR0: ON, LDR1: OFF, LDR2: PWM, LDR3: OFF */
+	TLC59108_LEDOUT0, 0x21,
+	/* Set LED2 PWM to full */
+	TLC59108_PWM2, 0xff,
+	/* LDR4: OFF, LDR5: OFF, LDR6: OFF, LDR7: ON */
+	TLC59108_LEDOUT1, 0x40,
+};
+
+static const struct tlc_board_data tlc_7_inch_data = {
+	.timings = {
+		.x_res		= 800,
+		.y_res		= 480,
+
+		.pixelclock	= 29232000,
+
+		.hfp		= 41,
+		.hsw		= 49,
+		.hbp		= 41,
+
+		.vfp		= 13,
+		.vsw		= 4,
+		.vbp		= 29,
+
+		.vsync_level	= OMAPDSS_SIG_ACTIVE_LOW,
+		.hsync_level	= OMAPDSS_SIG_ACTIVE_LOW,
+		.data_pclk_edge	= OMAPDSS_DRIVE_SIG_RISING_EDGE,
+		.de_level	= OMAPDSS_SIG_ACTIVE_HIGH,
+		.sync_pclk_edge	= OMAPDSS_DRIVE_SIG_RISING_EDGE,
+	},
+	.init_seq = tlc_7_inch_init_seq,
+	.init_seq_len = ARRAY_SIZE(tlc_7_inch_init_seq),
+};
+
+static const struct tlc_board_data tlc_10_inch_data = {
+	.timings = {
+		.x_res          = 1280,
+		.y_res          = 800,
+
+		.pixelclock     = 69300404,
+
+		.hfp            = 48,
+		.hsw            = 32,
+		.hbp            = 44,
+
+		.vfp            = 4,
+		.vsw            = 7,
+		.vbp            = 12,
+
+		.vsync_level    = OMAPDSS_SIG_ACTIVE_LOW,
+		.hsync_level    = OMAPDSS_SIG_ACTIVE_LOW,
+		.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
+		.de_level       = OMAPDSS_SIG_ACTIVE_HIGH,
+		.sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
+	},
+	.init_seq = tlc_10_inch_init_seq,
+	.init_seq_len = ARRAY_SIZE(tlc_10_inch_init_seq),
+};
+unsigned int fir_coeff_h[8] = {
+	0x00800000u,
+	0x0e7df601u,
+	0x2172f102u,
+	0x3762f001u,
+	0xf24e4ef2u,
+	0xf06237f6u,
+	0xf17221fau,
+	0xf67d0efeu
+};
+
+unsigned int fir_coeff_hv[8] = {
+	0x00800000u,
+	0x0e7df6feu,
+	0x2172f1fau,
+	0x3762f0f6u,
+	0xf24e4e00u,
+	0xf0623701u,
+	0xf1722102u,
+	0xf67d0e01u,
+};
+
+unsigned int fir_coeff_v[8] = {
+	0x00000000u,
+	0x0000fe01u,
+	0x0000fa02u,
+	0x0000f601u,
+	0x000000f2u,
+	0x000001f6u,
+	0x000002fau,
+	0x000001feu,
+};
+
+unsigned int fir_coeff_h2[8] = {
+	0x00800000u,
+	0x0e7df601u,
+	0x2172f102u,
+	0x3762f001u,
+	0xf24e4ef2u,
+	0xf06237f6u,
+	0xf17221fau,
+	0xf67d0efeu,
+};
+
+unsigned int fir_coeff_hv2[8] = {
+	0x00800000u,
+	0x0e7df6feu,
+	0x2172f1fau,
+	0x3762f0f6u,
+	0xf24e4e00u,
+	0xf0623701u,
+	0xf1722102u,
+	0xf67d0e01u,
+};
+
+unsigned int fir_coeff_v2[8] = {
+	0x00000000u,
+	0x0000fe01u,
+	0x0000fa02u,
+	0x0000f601u,
+	0x000000f2u,
+	0x000001f6u,
+	0x000002fau,
+	0x000001feu,
+};
+
+unsigned int vid_conv_coeff[5] = {
+	0x0199012au,
+	0x012a0000u,
+	0x079c0730u,
+	0x0000012au,
+	0x00000205u,
+};
+
+/*
+ *
+ * This functions uses the PRCM path for initializing the DSS
+ * and the settings are done for the LCD display for a stream
+ * of 800x480 resolution buffer on VID1 pipeline. These settings
+ * are currently overwritten by the linux kernel which re-initializes
+ * the DSS clocks and enables all the video and graphics pipelines.
+ *
+ */
+void setup_display(u32 lcd_type, u32 address)
+{
+	unsigned int reg;
+	unsigned int width  = 800;
+	unsigned int height = 480;
+	const struct tlc_board_data *bdata;
+	const struct omap_video_timings *timings;
+	unsigned int i = 0;
+
+	unsigned int tmp_vid_reg_base;
+
+	switch (lcd_type) {
+	case LCD_TYPE_7_INCH:
+		bdata = &tlc_7_inch_data;
+		break;
+	case LCD_TYPE_10_INCH:
+		bdata = &tlc_10_inch_data;
+		break;
+	default:
+		hang();
+	}
+
+	timings = &bdata->timings;
+	width  = timings->x_res;
+	height = timings->y_res;
+
+	/* Set the LCD channel 0 clock polarity as falling edge */
+	if (lcd_type == LCD_TYPE_7_INCH)
+		__raw_writel(0x80000, CTRL_CORE_SMA_SW_1);
+
+
+	if (lcd_type == LCD_TYPE_7_INCH) {
+		/* DIVHS divider for DISPC */
+		reg = __raw_readl(CM_DIV_H12_DPLL_PER);
+		reg = ((reg & 0xfffffbc0) | 0x207u);
+		__raw_writel(reg, CM_DIV_H12_DPLL_PER);
+
+		/* DISPC Divisor to enable LCD */
+		__raw_writel(0x010000u, DISPC_DIVISOR);
+
+		/* DISPC_DIVISOR1 */
+		__raw_writel(0x010003u, DISPC_DIVISOR1);
+
+		/* enable_lcd1 channel output. Use DSS Clock for LCD */
+		reg = __raw_readl(DSS_CTRL);
+		reg = ((reg & 0xfffcffff) | 0x10001u);
+		__raw_writel(reg, DSS_CTRL);
+	} else {
+		/* DIVHS divider for DISPC */
+		reg = __raw_readl(CM_DIV_H12_DPLL_PER);
+		reg = ((reg & 0xffffffc0) | 0x204u);
+		__raw_writel(reg, CM_DIV_H12_DPLL_PER);
+
+		/* DISPC Divisor to enable LCD */
+		__raw_writel(0x010001u, DISPC_DIVISOR);
+		/* DISPC_DIVISOR1 */
+		__raw_writel(0x010003u, DISPC_DIVISOR1);
+
+		/* enable_lcd1 channel output. Choose clock from video1 PLL */
+		reg = __raw_readl(DSS_CTRL);
+		reg = ((reg & 0xfffcffff) | 0x10001u);
+		__raw_writel(reg, DSS_CTRL);
+	}
+
+
+	/* DSS initialization */
+
+
+	/*
+	 * enable the display controller for LCD
+	 *
+	 * 16: Reset GPOut1
+	 * 15: Reset GPout0
+	 * 12: No overlay optimization
+	 * 9:8 24 bit otuput aligned in LSB of pixel data interface
+	 * 3 : Active TFT operation enabled.
+	 * 1 : LCD output enabled.
+	 */
+	__raw_writel(0x18309, DISPC_CONTROL1);
+
+
+	/*frame data only loaded every frame */
+	__raw_writel(0x04u, DISPC_CONFIG1); /* DISPC_CONFIG1 */
+
+
+	/* Default color for display when video plane has no data.
+	 * Format is YUV
+	 */
+	__raw_writel(0x0000F0u, DISPC_DEFAULT_COLOR0);
+
+
+	/* 31:20 hbp, 19:8 hfp, 7:0 hsw */
+
+	reg = ((timings->hbp<<20) | (timings->hfp<<8) | timings->hsw);
+	__raw_writel(reg, DISPC_TIMING_H1);
+
+	/* 31:20 vbp, 19:8 vfp, 7:0 vsw */
+	reg = ((timings->vbp<<20) | (timings->vfp<<8) | timings->vsw);
+	__raw_writel(reg, DISPC_TIMING_V1);
+
+	/* DISPC_POLL_FREQ1 */
+	__raw_writel(0x33000u, DISPC_POLL_FREQ1);
+
+	reg = ((((height-1)<<16)&0xFFFF0000) | ((width-1)&0xFFFF));
+	__raw_writel(reg, DISPC_SIZE_LCD1);
+
+	__raw_writel(0x0u, DISPC_MACRO(POSITION)); /* DISPC_VID1_SIZE */
+
+	reg = ((((height-1)<<16)&0xFFFF0000) | ((width-1)&0xFFFF));
+	__raw_writel(reg, DISPC_MACRO(SIZE));
+
+	/* DISPC_VID1_ATTRIBUTES
+	 * 31:30 primary lcd output is selected
+	 * 29 : incremental burst type
+	 * 27:26 z order: 2
+	 * 25: z order enabled
+	 * 24: no self refresh
+	 * 23: high priority pipeline
+	 * 21: 5 taps used in vertical filtering logic
+	 * 15:14 - 8x128 bit bursts
+	 * 13:12 - rotation by 90 degrees
+	 * 9: Enable color conversion from YUV to RGB
+	 * 6:5 : Enable both horizontal and vertical resize processing
+	 * 4:1 NV12 format
+	 */
+	__raw_writel(0x0aa08260, DISPC_MACRO(ATTRIBUTES));
+	__raw_writel(0x1, DISPC_MACRO(ROW_INC)); /* ROW_INC */
+
+	 reg = ((((height-1)<<16)&0xFFFF0000) | ((width-1)&0xFFFF));
+	__raw_writel(reg, DISPC_MACRO(PICTURE_SIZE));
+
+	/* setup the scalar coefficients */
+	__raw_writel(0x02000200u, DISPC_MACRO(FIR2));
+	__raw_writel(0x06000000u, DISPC_MACRO(AACU2_0));
+	__raw_writel(0x0u, DISPC_MACRO(AACU2_1));
+
+	__raw_writel(0x00000100u, DISPC_MACRO(ATTRIBUTES2));
+
+	/* Y layer coefs */
+	tmp_vid_reg_base = DISPC_MACRO(FIR_COEF_H_0);
+	for (i = 0; i < 8 ; i++)
+		__raw_writel(fir_coeff_h[i], tmp_vid_reg_base+i*8);
+
+	tmp_vid_reg_base = DISPC_MACRO(FIR_COEF_HV_0);
+	for (i = 0; i < 8 ; i++)
+		__raw_writel(fir_coeff_hv[i], tmp_vid_reg_base+i*8);
+
+	tmp_vid_reg_base = DISPC_MACRO(FIR_COEF_V_0);
+	for (i = 0; i < 8 ; i++)
+		__raw_writel(fir_coeff_v[i], tmp_vid_reg_base+i*4);
+
+	tmp_vid_reg_base = DISPC_MACRO(FIR_COEF_H2_0);
+	for (i = 0; i < 8 ; i++)
+		__raw_writel(fir_coeff_h2[i], tmp_vid_reg_base+i*8);
+
+	tmp_vid_reg_base = DISPC_MACRO(FIR_COEF_HV2_0);
+	for (i = 0; i < 8 ; i++)
+		__raw_writel(fir_coeff_hv2[i], tmp_vid_reg_base+i*8);
+
+	tmp_vid_reg_base = DISPC_MACRO(FIR_COEF_V2_0);
+	for (i = 0; i < 8 ; i++)
+		__raw_writel(fir_coeff_v2[i], tmp_vid_reg_base+i*4);
+
+
+	tmp_vid_reg_base = DISPC_MACRO(CONV_COEF0);
+	for (i = 0; i < 5 ; i++)
+		__raw_writel(vid_conv_coeff[i], tmp_vid_reg_base+i*4);
+
+	/*
+	 * Input is in YUV format.
+	 * Y in one buffer followed by UV subsampled by 2 in one
+	 * dimension in another buffer.
+	 */
+
+	__raw_writel(address, DISPC_MACRO(BA_0));
+
+	__raw_writel(address, DISPC_MACRO(BA_1));
+
+	/* Offset to UV buffer */
+	__raw_writel((address + (width*height)), DISPC_MACRO(BA_UV_0));
+	__raw_writel((address + (width*height)), DISPC_MACRO(BA_UV_1));
+
+	/* DISPC_VID1_ATTRIBUTES: enable the video */
+	reg = __raw_readl(DISPC_MACRO(ATTRIBUTES));
+	__raw_writel(reg | 0x1u, DISPC_MACRO(ATTRIBUTES));
+
+	reg = __raw_readl(DISPC_CONTROL1);
+	__raw_writel(reg | 0x20, DISPC_CONTROL1); /* DISPC_CONTROL1 */
+}
+
+void lcd_do_init_sequence(u32 lcd_type)
+{
+	const struct tlc_board_data *bdata;
+	unsigned int i = 0;
+	const unsigned int *init_seq;
+	unsigned init_seq_len;
+	u8 data;
+	u8 addr;
+
+	switch (lcd_type) {
+	case LCD_TYPE_7_INCH:
+		bdata = &tlc_7_inch_data;
+		break;
+	case LCD_TYPE_10_INCH:
+		bdata = &tlc_10_inch_data;
+		break;
+	default:
+		hang();
+	}
+	init_seq = bdata->init_seq;
+	init_seq_len = bdata->init_seq_len;
+	for (i = 0; i < init_seq_len; i += 2) {
+		addr = init_seq[i];
+		data = init_seq[i+1];
+		i2c_write(TLC_I2C_ADDR, addr, 1, &data, 1);
+	}
+	return;
+}
diff --git a/board/ti/dra7xx/display.h b/board/ti/dra7xx/display.h
new file mode 100644
index 0000000000..5654d5fdc5
--- /dev/null
+++ b/board/ti/dra7xx/display.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated, <www.ti.com>
+ * Author: Venkateswara Rao Mandela <venkat.mandela@ti.com>
+ *
+ * Based on the LCD and DSS drivers in the 3.14 kernel.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+#ifndef DRA7XX_DISPLAY_H
+#define DRA7XX_DISPLAY_H
+#include <common.h>
+
+void setup_display(u32 lcd_type, u32 address);
+
+#define CM_DIV_H12_DPLL_PER			0x4A00815C
+
+#define CTRL_CORE_SMA_SW_1	     (0x4A002534)
+
+/* DSS Registers */
+#define DISPC_DIVISOR				0x58001804
+#define DSS_CTRL				0x58000040
+#define DISPC_IRQENABLE				0x5800101C
+#define DISPC_CONTROL1				0x58001040
+#define DISPC_CONFIG1				0x58001044
+#define DISPC_DEFAULT_COLOR0			0x5800104C
+#define DISPC_TIMING_H1				0x58001064
+#define DISPC_TIMING_V1				0x58001068
+#define DISPC_POLL_FREQ1			0x5800106C
+#define DISPC_DIVISOR1				0x58001070
+#define DISPC_SIZE_LCD1				0x5800107C
+
+#define DISPC_VID1_POSITION			0x580010C4
+#define DISPC_VID1_SIZE				0x580010C8
+#define DISPC_VID1_ATTRIBUTES			0x580010CC
+#define DISPC_VID1_ROW_INC			0x580010D8
+#define DISPC_VID1_PICTURE_SIZE			0x580010E4
+
+#define DISPC_VID1_FIR_COEF_H_0			0x580010F0
+#define DISPC_VID1_FIR_COEF_HV_0		0x580010F4
+#define DISPC_VID1_FIR_COEF_V_0			0x580011E0
+#define DISPC_VID1_FIR_COEF_H2_0		0x58001648
+#define DISPC_VID1_FIR_COEF_HV2_0		0x5800164C
+#define DISPC_VID1_FIR_COEF_V2_0		0x58001688
+
+#define DISPC_VID1_ATTRIBUTES2			0x58001624
+#define DISPC_VID1_FIR2			0x5800163C
+#define DISPC_VID1_AACU2_0			0x58001640
+#define DISPC_VID1_AACU2_1			0x58001644
+#define DISPC_VID1_CONV_COEF0			0x58001130
+#define DISPC_VID1_BA_0				0x580010BC
+#define DISPC_VID1_BA_1				0x580010C0
+#define DISPC_VID1_BA_UV_0			0x58001600
+#define DISPC_VID1_BA_UV_1			0x58001604
+
+#define DISPC_VID3_POSITION			0x5800139C
+#define DISPC_VID3_SIZE				0x580013A8
+#define DISPC_VID3_ATTRIBUTES			0x58001370
+#define DISPC_VID3_ROW_INC			0x580013A4
+#define DISPC_VID3_PICTURE_SIZE			0x58001394
+
+#define DISPC_VID3_FIR_COEF_H_0			0x58001310
+#define DISPC_VID3_FIR_COEF_HV_0		0x58001314
+#define DISPC_VID3_FIR_COEF_V_0			0x58001350
+#define DISPC_VID3_FIR_COEF_H2_0		0x58001730
+#define DISPC_VID3_FIR_COEF_HV2_0		0x58001734
+#define DISPC_VID3_FIR_COEF_V2_0		0x58001770
+
+#define DISPC_VID3_ATTRIBUTES2			0x5800162C
+#define DISPC_VID3_FIR2				0x58001724
+#define DISPC_VID3_AACU2_0				0x58001728
+#define DISPC_VID3_AACU2_1				0x5800172C
+#define DISPC_VID3_CONV_COEF0			0x58001374
+
+#define DISPC_VID3_BA_0				0x58001308
+#define DISPC_VID3_BA_1				0x5800130C
+#define DISPC_VID3_BA_UV_0			0x58001610
+#define DISPC_VID3_BA_UV_1			0x58001614
+
+
+enum display_lcd_type {
+	LCD_TYPE_7_INCH = 0,
+	LCD_TYPE_10_INCH = 1,
+};
+
+
+/* End DSS Registers */
+void lcd_do_init_sequence(u32 lcd_type);
+void video_pll_conf(u32 lcd_type);
+void print_video_pll_debug_info(void);
+#endif
diff --git a/board/ti/dra7xx/lateattach.c b/board/ti/dra7xx/lateattach.c
index e6567fbfdd..6b368f00dd 100644
--- a/board/ti/dra7xx/lateattach.c
+++ b/board/ti/dra7xx/lateattach.c
@@ -17,6 +17,8 @@
 #include <asm/io.h>
 #include <omap_remoteproc.h>
 #include <elf.h>
+#include <i2c.h>
+#include "display.h"
 
 #define DPLL_TIMEOUT                 5000
 #define L4_CFG_TARG                  0x4A000000
@@ -160,6 +162,8 @@
 #define DRA7_RPROC_CMA_SIZE_DSP1             0x04000000
 #define DRA7_RPROC_CMA_SIZE_DSP2             0x01000000
 
+#define VAYU_ES10_CHIPSETID                    0x5436
+
 /*
  * The page table (32 KB) is placed at the end of the CMA reserved area.
  * It's possible that this location is needed by the firmware (in which
@@ -624,6 +628,65 @@ void enable_common_clocks(void)
 	return;
 }
 
+#define I2C_LCD_ADDR       0x40
+void setup_lcd_i2c (void)
+{
+	u8 data;
+	u8 retry_count=10;
+
+	/**
+	 * As I2C1 is already in use for PMIC interaction,
+	 * it is not necessary to initialize it again. If any
+	 * other I2C needs to initialized, call
+	 *
+	 * i2c_set_bus_num(i2c_instance);
+	 *
+	 */
+
+	/* i2c write to enable the lcd_display on evm */
+	data = 0xDBu;
+	i2c_write(0x20, 0, 1, &data, 1);
+
+	/* probe i2c device */
+	while ((i2c_probe(I2C_LCD_ADDR) != 0) && (retry_count!=0)){
+		retry_count--;
+		printf("Waiting for LCD Power on\n");
+	}
+	if(retry_count==0){
+		printf("LCD not powered on\n");
+		return;
+	}
+}
+
+void spl_setup_display(void)
+{
+	u32 reg;
+	u32 display_type = LCD_TYPE_10_INCH;
+
+	debug("Enabling DSS Clock domain\n");
+	__raw_writel(0x2, CM_DSS_CLKSTCTRL);
+
+	/* enable DSS */
+	reg = __raw_readl(CTRL_CORE_CONTROL_IO_2);
+	__raw_writel((reg | 0x1), CTRL_CORE_CONTROL_IO_2);
+	reg = __raw_readl(CM_DSS_DSS_CLKCTRL);
+	reg = ((reg & ~0x00000003) | 0x00003F00 | 0x2);
+	__raw_writel(reg, CM_DSS_DSS_CLKCTRL);
+
+	debug("Enabling DSS\n");
+	/* checking if DSS is enabled */
+	while ((__raw_readl(CM_DSS_DSS_CLKCTRL) & 0x00030000) != 0);
+
+	debug("Enabling I2C1\n");
+	reg = __raw_readl(CM_L4PER_I2C1_CLKCTRL);
+	__raw_writel((reg & ~0x00000003)|0x2, CM_L4PER_I2C1_CLKCTRL);
+
+	debug("Enabling LCD\n");
+	setup_lcd_i2c();
+	setup_display(display_type, DRA7_LOGO_START);
+	lcd_do_init_sequence(display_type);
+}
+
 u32 ipu_start_clocks(u32 core_id, struct rproc *cfg)
 {
 	u32 reg;
diff --git a/common/spl/spl.c b/common/spl/spl.c
index dcaa8e74e2..a9dc1ad3d4 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -432,6 +432,7 @@ static int spl_load_image(u32 boot_device)
 #endif
 #ifdef CONFIG_SPL_SPI_SUPPORT
 	case BOOT_DEVICE_SPI:
+		spl_setup_display();
 #ifdef CONFIG_LATE_ATTACH
                 spl_load_cores(boot_device, cores_to_boot,
                                sizeof(cores_to_boot)/sizeof(u32));
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 233d9761c4..f68333e812 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -390,4 +390,10 @@
 #endif
 
 #define CONFIG_DRA7XX_DWC1
+
+#define DRA7_OCMC1_BASE	(0x40400000)
+#define DRA7_OCMC1_SIZE	(0x00100000)
+#define DRA7_OCMC2_BASE	(0x40500000)
+#define DRA7_OCMC2_SIZE	(0x00100000)
+#define DRA7_LOGO_START	(DRA7_OCMC1_BASE)
 #endif /* __CONFIG_DRA7XX_EVM_H */
diff --git a/include/spl.h b/include/spl.h
index 03e7bd5dc3..0843c83d71 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -161,4 +161,6 @@ int spl_dfu_cmd(int usbctrl, char *dfu_alt_info, char *interface, char *devstr);
 
 u32 spl_mmc_load_core(u32 core_id, u32 boot_device);
 u32 spl_boot_core(u32 core_id);
+
+void spl_setup_display(void);
 #endif