Merge branch 'ti-u-boot-2016.05' of git://git.ti.com/ti-u-boot/ti-u-boot into p-ti-u-boot-2016.05

* 'ti-u-boot-2016.05' of git://git.ti.com/ti-u-boot/ti-u-boot:
  arm: omap: enable high speed mode support in SPL for the eMMC on DRA76x
  ARM: dts: dra76-evm: add higher speed MMC/SD modes
  ARM: dts: dra76-evm: shift to using common IOdelay data
  ARM: dts: dra76x: create a common file with MMC/SD IOdelay data
  ARM: DRA72x: Add support for detection of DRA71x SR 2.1

Change-Id: I6e100695a70d55683a66bf8c8430e5245831e6dc
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>

9 files changed, 304 insertions, 42 deletions

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index ed016cb7de..ae25a74638 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -753,6 +753,7 @@ void __weak hw_data_init(void)
 
 	case DRA722_ES1_0:
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 	*prcm = &dra7xx_prcm;
 	*dplls_data = &dra72x_dplls;
 	*ctrl = &dra7xx_ctrl;
@@ -788,6 +789,7 @@ void get_ioregs(const struct ctrl_ioregs **regs)
 		*regs = &ioregs_dra72x_es1;
 		break;
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 		*regs = &ioregs_dra72x_es2;
 		break;
 
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index 434d304686..03e50ba891 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -380,6 +380,9 @@ void init_omap_revision(void)
 	case DRA722_CONTROL_ID_CODE_ES2_0:
 		*omap_si_rev = DRA722_ES2_0;
 		break;
+	case DRA722_CONTROL_ID_CODE_ES2_1:
+		*omap_si_rev = DRA722_ES2_1;
+		break;
 	default:
 		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
 	}
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 67ff63b9f6..8fb962e39d 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -482,6 +482,7 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
 		break;
 	case DRA762_ES1_0:
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 		*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
 		*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2);
 		break;
@@ -716,6 +717,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations)
 	case DRA752_ES2_0:
 	case DRA722_ES1_0:
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 		bug_00339_regs_ptr = dra_bug_00339_regs;
 		*iterations = sizeof(dra_bug_00339_regs)/
 			     sizeof(dra_bug_00339_regs[0]);
diff --git a/arch/arm/dts/dra76-evm.dts b/arch/arm/dts/dra76-evm.dts
index 5b14dbf72a..1a149fa5fe 100644
--- a/arch/arm/dts/dra76-evm.dts
+++ b/arch/arm/dts/dra76-evm.dts
@@ -9,6 +9,7 @@
 
 #include "dra76x.dtsi"
 #include "dra7-evm-common.dtsi"
+#include "dra76x-mmc-iodelay.dtsi"
 #include <dt-bindings/net/ti-dp83867.h>
 
 / {
@@ -100,46 +101,6 @@
 	};
 };
 
-&dra7_pmx_core {
-	mmc1_pins_default: mmc1_pins_default {
-		pinctrl-single,pins = <
-			0x36c (PIN_INPUT | MUX_MODE14)	/* mmc1sdcd.gpio219 */
-			0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
-			0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
-			0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
-			0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
-			0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
-			0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
-		>;
-	};
-
-	mmc2_pins_default: mmc2_pins_default {
-		pinctrl-single,pins = <
-			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
-			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
-			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
-			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
-			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
-			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
-			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
-			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
-			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
-			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
-		>;
-	};
-
-	mmc4_pins_default: mmc4_pins_default {
-		pinctrl-single,pins = <
-			0x3e (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
-			0x3e (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
-			0x3f (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
-			0x3f (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
-			0x3f (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
-			0x3f (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
-		>;
-	};
-};
-
 &i2c1 {
 	status = "okay";
 	clock-frequency = <400000>;
@@ -352,16 +313,22 @@
 	 * is always hardwired.
 	 */
 	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
-	pinctrl-names = "default";
+	max-frequency = <192000000>;
+	pinctrl-names = "default", "hs";
 	pinctrl-0 = <&mmc1_pins_default>;
+	pinctrl-1 = <&mmc1_pins_hs>;
 };
 
 &mmc2 {
 	status = "okay";
 	vmmc-supply = <&vio_1v8>;
 	bus-width = <8>;
-	pinctrl-names = "default";
+	max-frequency = <192000000>;
+	pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
 	pinctrl-0 = <&mmc2_pins_default>;
+	pinctrl-1 = <&mmc2_pins_hs>;
+	pinctrl-2 = <&mmc2_pins_ddr>;
+	pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>;
 };
 
 /* No RTC on this device */
diff --git a/arch/arm/dts/dra76x-mmc-iodelay.dtsi b/arch/arm/dts/dra76x-mmc-iodelay.dtsi
new file mode 100644
index 0000000000..ff578843eb
--- /dev/null
+++ b/arch/arm/dts/dra76x-mmc-iodelay.dtsi
@@ -0,0 +1,244 @@
+/*
+ * MMC IOdelay values for TI's DRA76x and AM576x SoCs.
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Rules for modifying this file:
+ * a) Update of this file should typically correspond to a datamanual revision.
+ *    Datamanual revision that was used should be updated in comment below.
+ *    If there is no update to datamanual, do not update the values. If you
+ *    need to use values different from that recommended by the datamanual
+ *    for your design, then you should consider adding values to the device-
+ *    -tree file for your board directly.
+ * b) We keep the mode names as close to the datamanual as possible. So
+ *    if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
+ *    we follow that in code too.
+ * c) If the values change between multiple revisions of silicon, we add
+ *    a revision tag to both the new and old entry. Use 'rev11' for PG 1.1,
+ *    'rev20' for PG 2.0 and so on.
+ * d) The node name and node label should be the exact same string. This is
+ *    to curb naming creativity and achieve consistency.
+ *
+ * Datamanual Revisions:
+ *
+ * DRA76x Silicon Revision 1.0: SPRS993A, Revised July 2017
+ *
+ */
+
+&dra7_pmx_core {
+	mmc1_pins_default: mmc1_pins_default {
+		pinctrl-single,pins = <
+			0x354 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_clk.clk */
+			0x358 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_cmd.cmd */
+			0x35c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat0.dat0 */
+			0x360 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat1.dat1 */
+			0x364 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat2.dat2 */
+			0x368 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat3.dat3 */
+		>;
+	};
+
+	mmc1_pins_sdr12: mmc1_pins_sdr12 {
+		pinctrl-single,pins = <
+			0x354 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_clk.clk */
+			0x358 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_cmd.cmd */
+			0x35c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat0.dat0 */
+			0x360 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat1.dat1 */
+			0x364 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat2.dat2 */
+			0x368 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat3.dat3 */
+		>;
+	};
+
+	mmc1_pins_hs: mmc1_pins_hs {
+		pinctrl-single,pins = <
+			0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
+			0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
+			0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
+			0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
+			0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
+			0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
+		>;
+	};
+
+	mmc1_pins_sdr25: mmc1_pins_sdr25 {
+		pinctrl-single,pins = <
+			0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_clk.clk */
+			0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_cmd.cmd */
+			0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat0.dat0 */
+			0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat1.dat1 */
+			0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat2.dat2 */
+			0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat3.dat3 */
+		>;
+	};
+
+	mmc1_pins_sdr50: mmc1_pins_sdr50 {
+		pinctrl-single,pins = <
+			0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)	/* mmc1_clk.clk */
+			0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)	/* mmc1_cmd.cmd */
+			0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)	/* mmc1_dat0.dat0 */
+			0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)	/* mmc1_dat1.dat1 */
+			0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)	/* mmc1_dat2.dat2 */
+			0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)	/* mmc1_dat3.dat3 */
+		>;
+	};
+
+	mmc1_pins_ddr50: mmc1_pins_ddr50 {
+		pinctrl-single,pins = <
+			0x354 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_clk.clk */
+			0x358 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_cmd.cmd */
+			0x35c (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat0.dat0 */
+			0x360 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat1.dat1 */
+			0x364 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat2.dat2 */
+			0x368 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat3.dat3 */
+		>;
+	};
+
+	mmc1_pins_sdr104: mmc1_pins_sdr104 {
+		pinctrl-single,pins = <
+			0x354 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_clk.clk */
+			0x358 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_cmd.cmd */
+			0x35c (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat0.dat0 */
+			0x360 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat1.dat1 */
+			0x364 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat2.dat2 */
+			0x368 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat3.dat3 */
+		>;
+	};
+
+	mmc2_pins_default: mmc2_pins_default {
+		pinctrl-single,pins = <
+			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+		>;
+	};
+
+	mmc2_pins_hs: mmc2_pins_hs {
+		pinctrl-single,pins = <
+			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+		>;
+	};
+
+	mmc2_pins_ddr: mmc2_pins_ddr {
+		pinctrl-single,pins = <
+			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+		>;
+	};
+
+	mmc2_pins_hs200: mmc2_pins_hs200 {
+		pinctrl-single,pins = <
+			0x9c (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+			0xb0 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+			0xa0 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+			0xa4 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+			0xa8 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+			0xac (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+			0x8c (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+			0x90 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+			0x94 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+			0x98 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+		>;
+	};
+};
+
+&dra7_iodelay_core {
+
+	/* Corresponds to MMC1_DDR_MANUAL1 in datamanual */
+	mmc1_iodelay_ddr_conf: mmc1_iodelay_ddr_conf {
+		pinctrl-single,pins = <
+			0x618 (A_DELAY(489) | G_DELAY(0))	/* CFG_MMC1_CLK_IN */
+			0x624 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_CMD_IN */
+			0x630 (A_DELAY(374) | G_DELAY(0))	/* CFG_MMC1_DAT0_IN */
+			0x63c (A_DELAY(31) | G_DELAY(0))	/* CFG_MMC1_DAT1_IN */
+			0x648 (A_DELAY(56) | G_DELAY(0))	/* CFG_MMC1_DAT2_IN */
+			0x654 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT3_IN */
+			0x620 (A_DELAY(1355) | G_DELAY(0))	/* CFG_MMC1_CLK_OUT */
+			0x628 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_CMD_OEN */
+			0x62c (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_CMD_OUT */
+			0x634 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT0_OEN */
+			0x638 (A_DELAY(0) | G_DELAY(4))	/* CFG_MMC1_DAT0_OUT */
+			0x640 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT1_OEN */
+			0x644 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT1_OUT */
+			0x64c (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT2_OEN */
+			0x650 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT2_OUT */
+			0x658 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT3_OEN */
+			0x65c (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT3_OUT */
+		>;
+	};
+
+	/* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */
+	mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf {
+		pinctrl-single,pins = <
+			0x620 (A_DELAY(892) | G_DELAY(0))	/* CFG_MMC1_CLK_OUT */
+			0x628 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_CMD_OEN */
+			0x62c (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_CMD_OUT */
+			0x634 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT0_OEN */
+			0x638 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT0_OUT */
+			0x640 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT1_OEN */
+			0x644 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT1_OUT */
+			0x64c (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT2_OEN */
+			0x650 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT2_OUT */
+			0x658 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT3_OEN */
+			0x65c (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT3_OUT */
+		>;
+	};
+
+	/* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
+	mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf {
+		pinctrl-single,pins = <
+			0x190 (A_DELAY(384) | G_DELAY(0))       /* CFG_GPMC_A19_OEN */
+			0x194 (A_DELAY(0) | G_DELAY(174))       /* CFG_GPMC_A19_OUT */
+			0x1a8 (A_DELAY(410) | G_DELAY(0))       /* CFG_GPMC_A20_OEN */
+			0x1ac (A_DELAY(85) | G_DELAY(0))        /* CFG_GPMC_A20_OUT */
+			0x1b4 (A_DELAY(468) | G_DELAY(0))       /* CFG_GPMC_A21_OEN */
+			0x1b8 (A_DELAY(139) | G_DELAY(0))       /* CFG_GPMC_A21_OUT */
+			0x1c0 (A_DELAY(676) | G_DELAY(0))       /* CFG_GPMC_A22_OEN */
+			0x1c4 (A_DELAY(69) | G_DELAY(0))        /* CFG_GPMC_A22_OUT */
+			0x1d0 (A_DELAY(1062) | G_DELAY(154))	/* CFG_GPMC_A23_OUT */
+			0x1d8 (A_DELAY(640) | G_DELAY(0))       /* CFG_GPMC_A24_OEN */
+			0x1dc (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A24_OUT */
+			0x1e4 (A_DELAY(356) | G_DELAY(0))       /* CFG_GPMC_A25_OEN */
+			0x1e8 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A25_OUT */
+			0x1f0 (A_DELAY(579) | G_DELAY(0))       /* CFG_GPMC_A26_OEN */
+			0x1f4 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A26_OUT */
+			0x1fc (A_DELAY(435) | G_DELAY(0))       /* CFG_GPMC_A27_OEN */
+			0x200 (A_DELAY(36) | G_DELAY(0))        /* CFG_GPMC_A27_OUT */
+			0x364 (A_DELAY(759) | G_DELAY(0))       /* CFG_GPMC_CS1_OEN */
+			0x368 (A_DELAY(72) | G_DELAY(0))        /* CFG_GPMC_CS1_OUT */
+	      >;
+	};
+};
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index aca5af86fc..0fd3d85d29 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -64,6 +64,7 @@
 #define DRA752_CONTROL_ID_CODE_ES2_0		0x2B99002F
 #define DRA722_CONTROL_ID_CODE_ES1_0		0x0B9BC02F
 #define DRA722_CONTROL_ID_CODE_ES2_0		0x1B9BC02F
+#define DRA722_CONTROL_ID_CODE_ES2_1		0x2B9BC02F
 
 /* UART */
 #define UART1_BASE		(OMAP54XX_L4_PER_BASE + 0x6a000)
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 57f8ad2fd7..951a407515 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -755,6 +755,7 @@ static inline u8 is_dra76x(void)
 #define DRA752_ES2_0	0x07520200
 #define DRA722_ES1_0	0x07220100
 #define DRA722_ES2_0	0x07220200
+#define DRA722_ES2_1	0x07220210
 
 /*
  * SRAM scratch space entries
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 9f0beebcb9..145f044f88 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -294,6 +294,7 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 		break;
 	case DRA722_ES1_0:
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 		if (ram_size < CONFIG_MAX_MEM_MAPPED)
 			*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
 		else
@@ -358,6 +359,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 		break;
 	case DRA722_ES1_0:
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 	default:
 		if (ram_size < CONFIG_MAX_MEM_MAPPED)
 			*dmm_lisa_regs = &lisa_map_2G_x_2;
@@ -767,6 +769,7 @@ void recalibrate_iodelay(void)
 	switch (omap_revision()) {
 	case DRA722_ES1_0:
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 		pads = dra72x_core_padconf_array_common;
 		npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
 		if (board_is_dra71x_evm()) {
@@ -896,6 +899,14 @@ static struct pinctrl_desc pinctrl_descs_hsmmc2_dra72x[] = {
 	{NULL}
 };
 
+static struct pinctrl_desc pinctrl_descs_hsmmc2_dra76x[] = {
+	{"default", &hsmmc2_default_hs},
+	{"hs", &hsmmc2_default_hs},
+	{"ddr_1_8v", &hsmmc2_default_hs},
+	{"hs200_1_8v", &hsmmc2_hs200_1v8_dra76},
+	{NULL}
+};
+
 struct omap_hsmmc_pinctrl_state *platform_fixup_get_pinctrl_by_mode
 				  (struct hsmmc *base, const char *mode)
 {
@@ -911,6 +922,8 @@ struct omap_hsmmc_pinctrl_state *platform_fixup_get_pinctrl_by_mode
 			p = pinctrl_descs_hsmmc2_rev11;
 		else if (is_dra72x())
 			p = pinctrl_descs_hsmmc2_dra72x;
+		else if (is_dra76x())
+			p = pinctrl_descs_hsmmc2_dra76x;
 		else if (is_dra7xx())
 			p = pinctrl_descs_hsmmc2_rev20;
 		break;
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 535b4f5e1e..3fe52b19b2 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -1575,6 +1575,28 @@ static struct iodelay_cfg_entry mmc2_iodelay_hs200_1_8v_dra72_conf[] = {
 	{0x364, 1039 , 0	/* CFG_GPMC_CS1_OEN */},
 };
 
+static struct iodelay_cfg_entry mmc2_iodelay_hs200_1_8v_dra76_conf[] = {
+	{0x190, 384 , 0		/* CFG_GPMC_A19_OEN */},
+	{0x194, 0   , 174	/* CFG_GPMC_A19_OUT */},
+	{0x1A8, 410 , 0		/* CFG_GPMC_A20_OEN */},
+	{0x1AC, 85  , 0		/* CFG_GPMC_A20_OUT */},
+	{0x1B4, 468 , 0		/* CFG_GPMC_A21_OEN */},
+	{0x1B8, 139 , 0		/* CFG_GPMC_A21_OUT */},
+	{0x1C0, 676 , 0		/* CFG_GPMC_A22_OEN */},
+	{0x1C4, 69  , 0		/* CFG_GPMC_A22_OUT */},
+	{0x1D0, 1062, 154	/* CFG_GPMC_A23_OUT */},
+	{0x1D8, 640 , 0		/* CFG_GPMC_A24_OEN */},
+	{0x1DC, 0   , 0		/* CFG_GPMC_A24_OUT */},
+	{0x1E4, 356 , 0		/* CFG_GPMC_A25_OEN */},
+	{0x1E8, 0   , 0		/* CFG_GPMC_A25_OUT */},
+	{0x1F0, 579 , 0		/* CFG_GPMC_A26_OEN */},
+	{0x1F4, 0   , 0		/* CFG_GPMC_A26_OUT */},
+	{0x1FC, 435 , 0		/* CFG_GPMC_A27_OEN */},
+	{0x200, 36  , 0		/* CFG_GPMC_A27_OUT */},
+	{0x364, 759 , 0		/* CFG_GPMC_CS1_OEN */},
+	{0x368, 72  , 0		/* CFG_GPMC_CS1_OUT */},
+};
+
 #define dimof(t) (sizeof(t) / sizeof(t[0]))
 static struct omap_hsmmc_pinctrl_state hsmmc1_default = {
 	.padconf = hsmmc1_default_padconf,
@@ -1632,6 +1654,13 @@ static struct omap_hsmmc_pinctrl_state hsmmc2_hs200_1v8_dra72 = {
 	.iodelay = mmc2_iodelay_hs200_1_8v_dra72_conf,
 	.niodelays = dimof(mmc2_iodelay_hs200_1_8v_dra72_conf),
 };
+
+static struct omap_hsmmc_pinctrl_state hsmmc2_hs200_1v8_dra76 = {
+	.padconf = mmc2_pins_ddr_hs200_1_8v,
+	.npads = dimof(mmc2_pins_ddr_hs200_1_8v),
+	.iodelay = mmc2_iodelay_hs200_1_8v_dra76_conf,
+	.niodelays = dimof(mmc2_iodelay_hs200_1_8v_dra76_conf),
+};
 #endif
 
 #endif /* _MUX_DATA_DRA7XX_H_ */