aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorSubhajit Paul <subhajit_paul@ti.com>2017-11-22 16:25:29 +0530
committerRavikumar Kattekola <rk@ti.com>2017-11-24 14:44:01 +0530
commita1ea6770bb5827a012057f6ed3e864209339b5da (patch)
tree4438b8d48b02faad7ce46eaf5205ff2e8942fbae
parentfe2f3b2a83e0ee4a2187079b0bb252a166f8d5f6 (diff)
downloadjacinto6evm-a1ea6770bb5827a012057f6ed3e864209339b5da.tar.gz
ARM: DRA7: Add OPP_PLUS for GPU
on DRA76x, GPU has an additional OPP called as OPP_PLUS For highest performance, set OPP_PLUS as default. Change-Id: I1bd385643dd9f973453953aa921d54ba49ff9de6 Signed-off-by: Subhajit Paul <subhajit_paul@ti.com> Signed-off-by: Ravikumar Kattekola <rk@ti.com>
Diffstat
-rw-r--r--arch/arm/cpu/armv7/omap5/Kconfig3
-rw-r--r--arch/arm/cpu/armv7/omap5/fdt.c3
-rw-r--r--arch/arm/include/asm/arch-omap5/clock.h13
-rw-r--r--arch/arm/include/asm/omap_common.h1
-rw-r--r--board/ti/am57xx/board.c6
-rw-r--r--board/ti/dra7xx/evm.c8
-rw-r--r--configs/dra7xx_evm_defconfig2
-rw-r--r--configs/dra7xx_evm_nodt_defconfig2
-rw-r--r--configs/dra7xx_evm_vision_defconfig2
-rw-r--r--configs/dra7xx_hs_evm_defconfig2
10 files changed, 35 insertions, 7 deletions
diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig
index 13b6975731..e93af652a2 100644
--- a/arch/arm/cpu/armv7/omap5/Kconfig
+++ b/arch/arm/cpu/armv7/omap5/Kconfig
@@ -114,6 +114,9 @@ config DRA7_GPU_OPP_OD
config DRA7_GPU_OPP_HIGH
bool "OPP HIGH"
+config DRA7_GPU_OPP_PLUS
+ bool "OPP PLUS"
+
endchoice
endmenu
diff --git a/arch/arm/cpu/armv7/omap5/fdt.c b/arch/arm/cpu/armv7/omap5/fdt.c
index 7215a0dfc1..5a0bcc8b5e 100644
--- a/arch/arm/cpu/armv7/omap5/fdt.c
+++ b/arch/arm/cpu/armv7/omap5/fdt.c
@@ -292,6 +292,7 @@ u32 dra7_opp_dsp_clk_rates[NUM_OPPS][OPP_DSP_CLK_NUM] = {
{600000000, 600000000, 400000000}, /* OPP_NOM */
{700000000, 700000000, 466666667}, /* OPP_OD */
{750000000, 750000000, 500000000}, /* OPP_HIGH */
+ {}, /*OPP_PLUS */
};
/* IVA voltage domain */
@@ -300,6 +301,7 @@ u32 dra7_opp_iva_clk_rates[NUM_OPPS][OPP_IVA_CLK_NUM] = {
{1165000000, 388333334}, /* OPP_NOM */
{860000000, 430000000}, /* OPP_OD */
{1064000000, 532000000}, /* OPP_HIGH */
+ {}, /*OPP_PLUS */
};
/* GPU voltage domain */
@@ -308,6 +310,7 @@ u32 dra7_opp_gpu_clk_rates[NUM_OPPS][OPP_GPU_CLK_NUM] = {
{1277000000, 425666667}, /* OPP_NOM */
{1000000000, 500000000}, /* OPP_OD */
{1064000000, 532000000}, /* OPP_HIGH */
+ {1330000000, 665000000}, /* OPP_PLUS */
};
static int ft_fixup_clocks(void *fdt, const char **names, u32 *rates, int num)
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 489815e644..80077d7b71 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -256,6 +256,9 @@
#define VDD_GPU_DRA7_HIGH 1250
#define VDD_IVA_DRA7_HIGH 1250
+/* DRA76x voltage settings in mv for OPP_PLUS per DM */
+#define VDD_GPU_DRA7_PLUS 1250
+
/* Efuse register offsets for DRA7xx platform */
#define DRA752_EFUSE_BASE 0x4A002000
#define DRA752_EFUSE_REGBITS 16
@@ -279,6 +282,8 @@
#define STD_FUSE_OPP_VMIN_GPU_OD (DRA752_EFUSE_BASE + 0x1B0C)
/* STD_FUSE_OPP_VMIN_GPU_4 */
#define STD_FUSE_OPP_VMIN_GPU_HIGH (DRA752_EFUSE_BASE + 0x1B10)
+/* STD_FUSE_OPP_VMIN_GPU_5 */
+#define STD_FUSE_OPP_VMIN_GPU_PLUS (DRA752_EFUSE_BASE + 0x1B14)
/* STD_FUSE_OPP_VMIN_MPU_2 */
#define STD_FUSE_OPP_VMIN_MPU_NOM (DRA752_EFUSE_BASE + 0x1B20)
/* STD_FUSE_OPP_VMIN_MPU_3 */
@@ -291,13 +296,13 @@
#define VDD_MPU_DRA7 VDD_MPU_DRA7_NOM
#define VDD_CORE_DRA7 VDD_CORE_DRA7_NOM
#define VDD_EVE_DRA7 VDD_EVE_DRA7_HIGH
-#define VDD_GPU_DRA7 VDD_GPU_DRA7_HIGH
+#define VDD_GPU_DRA7 VDD_GPU_DRA7_PLUS
#define VDD_IVA_DRA7 VDD_IVA_DRA7_HIGH
#define STD_FUSE_OPP_VMIN_MPU STD_FUSE_OPP_VMIN_MPU_NOM
#define STD_FUSE_OPP_VMIN_CORE STD_FUSE_OPP_VMIN_CORE_NOM
#define STD_FUSE_OPP_VMIN_DSPEVE STD_FUSE_OPP_VMIN_DSPEVE_HIGH
-#define STD_FUSE_OPP_VMIN_GPU STD_FUSE_OPP_VMIN_GPU_HIGH
+#define STD_FUSE_OPP_VMIN_GPU STD_FUSE_OPP_VMIN_GPU_PLUS
#define STD_FUSE_OPP_VMIN_IVA STD_FUSE_OPP_VMIN_IVA_HIGH
/* Common OPP selection for DRA7xx devices */
@@ -327,7 +332,9 @@
#define DRA7_IVA_OPP OPP_NOM
#endif
-#if defined(CONFIG_DRA7_GPU_OPP_HIGH)
+#if defined(CONFIG_DRA7_GPU_OPP_PLUS)
+#define DRA7_GPU_OPP OPP_PLUS
+#elif defined(CONFIG_DRA7_GPU_OPP_HIGH)
#define DRA7_GPU_OPP OPP_HIGH
#elif defined(CONFIG_DRA7_GPU_OPP_OD)
#define DRA7_GPU_OPP OPP_OD
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 951a407515..32575348ba 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -545,6 +545,7 @@ enum {
OPP_NOM,
OPP_OD,
OPP_HIGH,
+ OPP_PLUS,
NUM_OPPS,
};
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 72c4312837..67c8d2ecae 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -269,9 +269,11 @@ struct vcores_data beagle_x15_volts = {
.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
.gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
.gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
+ .gpu.value[OPP_PLUS] = VDD_GPU_DRA7_PLUS,
.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
.gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
+ .gpu.efuse.reg[OPP_PLUS] = STD_FUSE_OPP_VMIN_GPU_PLUS,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS45,
.gpu.pmic = &tps659038,
@@ -317,9 +319,11 @@ struct vcores_data am571x_idk_volts = {
.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
.gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
.gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
+ .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_PLUS,
.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
.gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
+ .gpu.efuse.reg[OPP_PLUS] = STD_FUSE_OPP_VMIN_GPU_PLUS,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic = &tps659038,
@@ -365,9 +369,11 @@ struct vcores_data am572x_idk_volts = {
.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
.gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
.gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
+ .gpu.value[OPP_PLUS] = VDD_GPU_DRA7_PLUS,
.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
.gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
+ .gpu.efuse.reg[OPP_PLUS] = STD_FUSE_OPP_VMIN_GPU_PLUS,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic = &tps659038,
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 685edf07c8..08c0987afe 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -391,9 +391,11 @@ struct vcores_data dra752_volts = {
.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
.gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
.gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
+ .gpu.value[OPP_PLUS] = VDD_GPU_DRA7_PLUS,
.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
.gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
+ .gpu.efuse.reg[OPP_PLUS] = STD_FUSE_OPP_VMIN_GPU_PLUS,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic = &tps659038,
@@ -439,9 +441,11 @@ struct vcores_data dra76x_volts = {
.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
.gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
.gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
+ .gpu.value[OPP_PLUS] = VDD_GPU_DRA7_PLUS,
.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
.gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
+ .gpu.efuse.reg[OPP_PLUS] = STD_FUSE_OPP_VMIN_GPU_PLUS,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = LP87565_REG_ADDR_BUCK23,
.gpu.pmic = &lp87565,
@@ -486,9 +490,11 @@ struct vcores_data dra722_volts = {
.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
.gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
.gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
+ .gpu.value[OPP_PLUS] = VDD_GPU_DRA7_PLUS,
.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
.gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
+ .gpu.efuse.reg[OPP_PLUS] = STD_FUSE_OPP_VMIN_GPU_PLUS,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS65917_REG_ADDR_SMPS3,
.gpu.pmic = &tps659038,
@@ -587,6 +593,8 @@ int get_voltrail_opp(int rail_offset)
/* DRA71x supports only OPP_NOM for GPU */
if (board_is_dra71x_evm())
opp = OPP_NOM;
+ else if (!board_is_dra76x_evm() && opp == OPP_PLUS)
+ opp = OPP_HIGH;
break;
case VOLT_EVE:
opp = DRA7_DSPEVE_OPP;
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index e125593e41..a6cec9d5fa 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -68,7 +68,7 @@ CONFIG_OF_LIBFDT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_DRA7_DSPEVE_OPP_HIGH=y
CONFIG_DRA7_IVA_OPP_HIGH=y
-CONFIG_DRA7_GPU_OPP_HIGH=y
+CONFIG_DRA7_GPU_OPP_PLUS=y
CONFIG_CMD_TIME=y
CONFIG_DM_I2C=y
CONFIG_DM_REGULATOR=y
diff --git a/configs/dra7xx_evm_nodt_defconfig b/configs/dra7xx_evm_nodt_defconfig
index 9c13366939..64609f31b4 100644
--- a/configs/dra7xx_evm_nodt_defconfig
+++ b/configs/dra7xx_evm_nodt_defconfig
@@ -45,4 +45,4 @@ CONFIG_SPL_OF_LIBFDT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_DRA7_DSPEVE_OPP_HIGH=y
CONFIG_DRA7_IVA_OPP_HIGH=y
-CONFIG_DRA7_GPU_OPP_HIGH=y
+CONFIG_DRA7_GPU_OPP_PLUS=y
diff --git a/configs/dra7xx_evm_vision_defconfig b/configs/dra7xx_evm_vision_defconfig
index 8b97ec7b69..8f78fc1731 100644
--- a/configs/dra7xx_evm_vision_defconfig
+++ b/configs/dra7xx_evm_vision_defconfig
@@ -62,7 +62,7 @@ CONFIG_OF_LIBFDT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_DRA7_DSPEVE_OPP_HIGH=y
CONFIG_DRA7_IVA_OPP_HIGH=y
-CONFIG_DRA7_GPU_OPP_HIGH=y
+CONFIG_DRA7_GPU_OPP_PLUS=y
CONFIG_CMD_TIME=y
CONFIG_DM_I2C=y
CONFIG_DM_REGULATOR=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 87efcb262d..0279e0e073 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -72,7 +72,7 @@ CONFIG_ERRNO_STR=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_DRA7_DSPEVE_OPP_HIGH=y
CONFIG_DRA7_IVA_OPP_HIGH=y
-CONFIG_DRA7_GPU_OPP_HIGH=y
+CONFIG_DRA7_GPU_OPP_PLUS=y
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-11 10:11:21 +0000