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| author | Keerthy <j-keerthy@ti.com> | 2016-08-27 16:09:44 +0530 |
|---|---|---|
| committer | Lokesh Vutla <lokeshvutla@ti.com> | 2016-08-30 16:12:47 +0530 |
| commit | 7d913f1269d7a489a4d0d6a8977fc0d05c6c0d02 (patch) | |
| tree | eca56e5f60806cac2f5cc02e44a6a6475ade9894 /board | |
| parent | ea04822b6c0af737a99f4c8da8301c100199896a (diff) | |
| download | jacinto6evm-7d913f1269d7a489a4d0d6a8977fc0d05c6c0d02.tar.gz | |
board: DRA71x-evm: Add PMIC support
Add the pmic_data for LP873x PMIC which is used to power
up DRA71x-evm.
Note: As per the DM[1] DRA71x supports only OP_NOM. So, updating
the efuse registers only to use OPP_NOM irrespective of any
CONFIG_DRA7_<VOLT>_OPP_{NOM,od,high} is defined.
[1] http://www.ti.com/product/DRA718/technicaldocuments
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/ti/dra7xx/evm.c | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 1631d9f19d..b2ec832bcc 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -408,10 +408,60 @@ struct vcores_data dra722_volts = { .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, }; +struct vcores_data dra718_volts = { + /* + * In the case of dra71x GPU MPU and CORE + * are all powered up by BUCK0 of LP873X PMIC + */ + .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, + .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = LP873X_REG_ADDR_BUCK0, + .mpu.pmic = &lp8733, + .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, + + .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, + .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = LP873X_REG_ADDR_BUCK0, + .core.pmic = &lp8733, + + .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, + .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = LP873X_REG_ADDR_BUCK0, + .gpu.pmic = &lp8733, + .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, + + /* + * The DSPEVE and IVA rails are grouped on DRA71x-evm + * and are powered by BUCK1 of LP873X PMIC + */ + .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, + .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = LP873X_REG_ADDR_BUCK1, + .eve.pmic = &lp8733, + .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, + + .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, + .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = LP873X_REG_ADDR_BUCK1, + .iva.pmic = &lp8733, + .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, +}; + int get_voltrail_opp(int rail_offset) { int opp; + /* + * DRA71x supports only OPP_NOM. + */ + if (board_is_dra71x_evm()) + return OPP_NOM; + switch (rail_offset) { case VOLT_MPU: opp = DRA7_MPU_OPP; @@ -541,6 +591,8 @@ void vcores_update(void) *omap_vcores = &dra752_volts; } else if (board_is_dra72x_evm()) { *omap_vcores = &dra722_volts; + } else if (board_is_dra71x_evm()) { + *omap_vcores = &dra718_volts; } else { /* If EEPROM is not populated */ if (is_dra72x()) |