Platforms/HiKey960: Support 4G or more memory space for RAM

Currently, Hikey960 has two different manufactured forms, one is with
3GB DDR RAM and another has 4GB DDR RAM, so this patch adds
support to dynamically adapt DDR RAM size as needed at booting
time.

[leoy: rephrased the commit log]

Cc: Haojian Zhuang haojian.zhuang@linaro.org
Cc: fengbaopeng@hisilicon.com
Signed-off-by: Li Wei liwei213@huawei.com

2 files changed, 136 insertions, 50 deletions

diff --git a/Platforms/Hisilicon/HiKey960/Include/Hi3660.h b/Platforms/Hisilicon/HiKey960/Include/Hi3660.h
index 0d810d8..e9e1552 100644
--- a/Platforms/Hisilicon/HiKey960/Include/Hi3660.h
+++ b/Platforms/Hisilicon/HiKey960/Include/Hi3660.h
@@ -141,7 +141,10 @@
 #define BIT_SYSCTRL_LP_RESET_N                  (1 << 0)

 #define BIT_UFS_REFCLK_SRC_SE1                  (1 << 0)

 #define MASK_UFS_SYSCTRL_BYPASS                 (0x3F << 16)

-#define MASK_UFS_DEVICE_RESET                   (1 << 16)

-#define BIT_UFS_DEVICE_RESET                    (1 << 0)

-

-#endif /* __HI3660_H__ */

+#define MASK_UFS_DEVICE_RESET                   (1 << 16)
+#define BIT_UFS_DEVICE_RESET                    (1 << 0)
+
+#define SCTRL_SCBAKDATA7                        (SCTRL_REG_BASE + 0x428)
+#define HIKEY_REGION_SIZE(x)                    ((((x) >> 0x8) & 0xF) << 30)
+
+#endif /* __HI3660_H__ */
diff --git a/Platforms/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Mem.c b/Platforms/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Mem.c
index 174bac2..2d0568b 100644
--- a/Platforms/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Mem.c
+++ b/Platforms/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Mem.c
@@ -15,27 +15,34 @@
 #include <Library/ArmPlatformLib.h>

 #include <Library/DebugLib.h>

 #include <Library/HobLib.h>

-#include <Library/PcdLib.h>

-#include <Library/IoLib.h>

-#include <Library/MemoryAllocationLib.h>

-

-// The total number of descriptors, including the final "end-of-table" descriptor.

-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12

+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Hi3660.h>
+
+// The total number of descriptors, including the final "end-of-table" descriptor.
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12
 

 // DDR attributes

-#define DDR_ATTRIBUTES_CACHED           ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK

-#define DDR_ATTRIBUTES_UNCACHED         ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED

-

-#define HI3660_PERIPH_BASE              0xE0000000

-#define HI3660_PERIPH_SZ                0x20000000

-

-#define HIKEY960_EXTRA_SYSTEM_MEMORY_BASE  0x0000000100000000

-#define HIKEY960_EXTRA_SYSTEM_MEMORY_SIZE  0x0000000020000000

-

-#define HIKEY960_MEMORY_SIZE               0x0000000100000000

-

-#define HIKEY960_RESERVED_MEMORY

-

+#define DDR_ATTRIBUTES_CACHED           ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED         ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+
+// SOC map 3.5G~4G
+#define HI3660_PERIPH_BASE              0xE0000000
+#define HI3660_PERIPH_SIZE              0x20000000
+
+// for 4G DDR 0~3G 3G~3.5G 8~8.5G
+#define HIKEY960_DDR4G_EXTRA1_SYSTEM_MEMORY_BASE  0x00000000C0000000
+#define HIKEY960_DDR4G_EXTRA1_SYSTEM_MEMORY_SIZE  0x0000000020000000
+#define HIKEY960_DDR4G_EXTRA2_SYSTEM_MEMORY_BASE  0x0000000200000000
+#define HIKEY960_DDR4G_EXTRA2_SYSTEM_MEMORY_SIZE  0x0000000020000000
+
+// for 6G DDR 0~3G 4~7G
+#define HIKEY960_DDR6G_EXTRA_SYSTEM_MEMORY_BASE   0x0000000100000000
+#define HIKEY960_DDR6G_EXTRA_SYSTEM_MEMORY_SIZE   0x00000000C0000000
+
+#define HIKEY960_RESERVED_MEMORY
+
 STATIC struct HiKey960ReservedMemory {

   EFI_PHYSICAL_ADDRESS         Offset;

   EFI_PHYSICAL_ADDRESS         Size;

@@ -45,12 +52,22 @@ STATIC struct HiKey960ReservedMemory {
   { 0x32100000, 0x00001000 },    // ADB REBOOT "REASON"

   { 0x3E000000, 0x02000000 },    // TEE OS

   { 0x89B80000, 0x00100000 },    // MCU Code reserved

-  { 0x89C80000, 0x00040000 }     // MCU reserved

-};

-

-/**

-  Return the Virtual Memory Map of your platform

-

+  { 0x89C80000, 0x00040000 }     // MCU reserved
+};
+
+STATIC UINT64 EFIAPI HiKeyInitMemorySize(IN VOID)
+{
+  UINT32               Data;
+  UINT64               MemorySize;
+
+  Data = MmioRead32 (SCTRL_SCBAKDATA7);
+  MemorySize = HIKEY_REGION_SIZE((UINT64)Data);
+  return MemorySize;
+}
+
+/**
+  Return the Virtual Memory Map of your platform
+
   This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.

 

   @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-

@@ -70,12 +87,20 @@ ArmPlatformGetVirtualMemoryMap (
   UINTN                         Index = 0, Count, ReservedTop;

   EFI_PEI_HOB_POINTERS          NextHob;

   UINT64                        ResourceLength;

-  EFI_PHYSICAL_ADDRESS          ResourceTop;

-#endif

-

-  ResourceAttributes = (

-    EFI_RESOURCE_ATTRIBUTE_PRESENT |

-    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |

+  EFI_PHYSICAL_ADDRESS          ResourceTop;
+#endif
+
+
+  UINT64                        MemorySize, AdditionalMemorySize;
+
+  MemorySize = HiKeyInitMemorySize ();
+  if (MemorySize == 0) {
+    MemorySize = PcdGet64 (PcdSystemMemorySize);
+  }
+
+  ResourceAttributes = (
+    EFI_RESOURCE_ATTRIBUTE_PRESENT |
+    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
     EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |

     EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |

     EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |

@@ -129,12 +154,52 @@ ArmPlatformGetVirtualMemoryMap (
       Index++;

     }

     NextHob.Raw = GET_NEXT_HOB (NextHob);

-  }

-#endif

-

-  ASSERT (VirtualMemoryMap != NULL);

-

-  VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (

+  }
+#endif
+
+  AdditionalMemorySize = MemorySize - PcdGet64 (PcdSystemMemorySize);
+  //6G
+  if (AdditionalMemorySize >= SIZE_2GB) {
+    // for 6G,declared the additional memory
+    ResourceAttributes =
+      EFI_RESOURCE_ATTRIBUTE_PRESENT |
+      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+      EFI_RESOURCE_ATTRIBUTE_TESTED;
+
+    BuildResourceDescriptorHob (
+      EFI_RESOURCE_SYSTEM_MEMORY,
+      ResourceAttributes,
+      HIKEY960_DDR6G_EXTRA_SYSTEM_MEMORY_BASE,
+      HIKEY960_DDR6G_EXTRA_SYSTEM_MEMORY_SIZE);
+  } else if (AdditionalMemorySize >= SIZE_1GB) {
+    // for 4G,declared the additional memory
+    ResourceAttributes =
+      EFI_RESOURCE_ATTRIBUTE_PRESENT |
+      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+      EFI_RESOURCE_ATTRIBUTE_TESTED;
+
+    BuildResourceDescriptorHob (
+      EFI_RESOURCE_SYSTEM_MEMORY,
+      ResourceAttributes,
+      HIKEY960_DDR4G_EXTRA1_SYSTEM_MEMORY_BASE,
+      HIKEY960_DDR4G_EXTRA1_SYSTEM_MEMORY_SIZE);
+
+    BuildResourceDescriptorHob (
+      EFI_RESOURCE_SYSTEM_MEMORY,
+      ResourceAttributes,
+      HIKEY960_DDR4G_EXTRA2_SYSTEM_MEMORY_BASE,
+      HIKEY960_DDR4G_EXTRA2_SYSTEM_MEMORY_SIZE);
+  }
+
+  ASSERT (VirtualMemoryMap != NULL);
+
+  VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
                                                         EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)

                                                         );

   if (VirtualMemoryTable == NULL) {

@@ -155,15 +220,33 @@ ArmPlatformGetVirtualMemoryMap (
   VirtualMemoryTable[Index].Length          = PcdGet64 (PcdSystemMemorySize);

   VirtualMemoryTable[Index].Attributes      = CacheAttributes;

 

-  // Hi3660 SOC peripherals

-  VirtualMemoryTable[++Index].PhysicalBase  = HI3660_PERIPH_BASE;

-  VirtualMemoryTable[Index].VirtualBase     = HI3660_PERIPH_BASE;

-  VirtualMemoryTable[Index].Length          = HI3660_PERIPH_SZ;

-  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

-

-  // End of Table

-  VirtualMemoryTable[++Index].PhysicalBase  = 0;

-  VirtualMemoryTable[Index].VirtualBase     = 0;

+  // Hi3660 SOC peripherals
+  VirtualMemoryTable[++Index].PhysicalBase  = HI3660_PERIPH_BASE;
+  VirtualMemoryTable[Index].VirtualBase     = HI3660_PERIPH_BASE;
+  VirtualMemoryTable[Index].Length          = HI3660_PERIPH_SIZE;
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // If DDR capacity is &gt;3G size, append a new entry to fill the gap.
+  if (AdditionalMemorySize >= SIZE_2GB) {
+    VirtualMemoryTable[++Index].PhysicalBase = HIKEY960_DDR6G_EXTRA_SYSTEM_MEMORY_BASE;
+    VirtualMemoryTable[Index].VirtualBase    = HIKEY960_DDR6G_EXTRA_SYSTEM_MEMORY_BASE;
+    VirtualMemoryTable[Index].Length         = HIKEY960_DDR6G_EXTRA_SYSTEM_MEMORY_SIZE;
+    VirtualMemoryTable[Index].Attributes     = CacheAttributes;
+  } else if (AdditionalMemorySize >= SIZE_1GB) {
+    VirtualMemoryTable[++Index].PhysicalBase = HIKEY960_DDR4G_EXTRA1_SYSTEM_MEMORY_BASE;
+    VirtualMemoryTable[Index].VirtualBase    = HIKEY960_DDR4G_EXTRA1_SYSTEM_MEMORY_BASE;
+    VirtualMemoryTable[Index].Length         = HIKEY960_DDR4G_EXTRA1_SYSTEM_MEMORY_SIZE;
+    VirtualMemoryTable[Index].Attributes     = CacheAttributes;
+
+    VirtualMemoryTable[++Index].PhysicalBase = HIKEY960_DDR4G_EXTRA2_SYSTEM_MEMORY_BASE;
+    VirtualMemoryTable[Index].VirtualBase    = HIKEY960_DDR4G_EXTRA2_SYSTEM_MEMORY_BASE;
+    VirtualMemoryTable[Index].Length         = HIKEY960_DDR4G_EXTRA2_SYSTEM_MEMORY_SIZE;
+    VirtualMemoryTable[Index].Attributes     = CacheAttributes;
+  }
+
+  // End of Table
+  VirtualMemoryTable[++Index].PhysicalBase  = 0;
+  VirtualMemoryTable[Index].VirtualBase     = 0;
   VirtualMemoryTable[Index].Length          = 0;

   VirtualMemoryTable[Index].Attributes      = (ARM_MEMORY_REGION_ATTRIBUTES)0;