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| author | Haojian Zhuang <haojian.zhuang@linaro.org> | 2017-11-09 10:21:43 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-11-09 10:21:43 +0800 |
| commit | ef1908e5d2e66109cb662f9ba09e754ada470ef0 (patch) | |
| tree | 068e57596704dce1bc7fd97a07b205a2e2f22d42 /include/lib/cpus/aarch32/cortex_a32.h | |
| parent | 7533ed72d3bb3c2a20b5d098f1a894c8b6dbaff8 (diff) | |
| parent | 7cd40b9398451a05ad482e91ac041af0f1d2433a (diff) | |
| download | arm-trusted-firmware-ef1908e5d2e66109cb662f9ba09e754ada470ef0.tar.gz | |
Merge pull request #19 from johnstultz-work/bootloader-update
Update armtf branch AOSP uses to upstream armtf code
Diffstat (limited to 'include/lib/cpus/aarch32/cortex_a32.h')
| -rw-r--r-- | include/lib/cpus/aarch32/cortex_a32.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch32/cortex_a32.h b/include/lib/cpus/aarch32/cortex_a32.h new file mode 100644 index 00000000..4d6826a5 --- /dev/null +++ b/include/lib/cpus/aarch32/cortex_a32.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __CORTEX_A32_H__ +#define __CORTEX_A32_H__ + +/* Cortex-A32 Main ID register for revision 0 */ +#define CORTEX_A32_MIDR 0x410FD010 + +/******************************************************************************* + * CPU Extended Control register specific definitions. + * CPUECTLR_EL1 is an implementation-specific register. + ******************************************************************************/ +#define CORTEX_A32_CPUECTLR_EL1 p15, 1, c15 +#define CORTEX_A32_CPUECTLR_SMPEN_BIT (1 << 6) + +#endif /* __CORTEX_A32_H__ */ |