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author | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2017-09-22 08:32:09 +0100 |
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committer | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2017-10-16 16:50:02 +0100 |
commit | 8db978b5a8606a658c65b16fab7edd7a17c7c940 (patch) | |
tree | bfef9510b0bbb1f8560a45a7ef760217d49ddab4 /include | |
parent | 74dce7fa6e42cab3aa54a9543e4a546c1450b2ae (diff) | |
download | arm-trusted-firmware-8db978b5a8606a658c65b16fab7edd7a17c7c940.tar.gz |
GIC: Add API to raise secure SGI
API documentation updated.
Change-Id: I129725059299af6cc612bafa8d74817f779d7c4f
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/drivers/arm/gicv2.h | 14 | ||||
-rw-r--r-- | include/drivers/arm/gicv3.h | 25 | ||||
-rw-r--r-- | include/lib/aarch32/arch.h | 1 | ||||
-rw-r--r-- | include/lib/aarch32/arch_helpers.h | 4 | ||||
-rw-r--r-- | include/lib/aarch64/arch.h | 1 | ||||
-rw-r--r-- | include/lib/aarch64/arch_helpers.h | 1 | ||||
-rw-r--r-- | include/plat/common/platform.h | 1 |
7 files changed, 47 insertions, 0 deletions
diff --git a/include/drivers/arm/gicv2.h b/include/drivers/arm/gicv2.h index 229355cc..c9bcbb65 100644 --- a/include/drivers/arm/gicv2.h +++ b/include/drivers/arm/gicv2.h @@ -36,6 +36,19 @@ #define CPENDSGIR_SHIFT 2 #define SPENDSGIR_SHIFT CPENDSGIR_SHIFT +#define SGIR_TGTLSTFLT_SHIFT 24 +#define SGIR_TGTLSTFLT_MASK 0x3 +#define SGIR_TGTLST_SHIFT 16 +#define SGIR_TGTLST_MASK 0xff +#define SGIR_INTID_MASK 0xf + +#define SGIR_TGT_SPECIFIC 0 + +#define GICV2_SGIR_VALUE(tgt_lst_flt, tgt, intid) \ + ((((tgt_lst_flt) & SGIR_TGTLSTFLT_MASK) << SGIR_TGTLSTFLT_SHIFT) | \ + (((tgt) & SGIR_TGTLST_MASK) << SGIR_TGTLST_SHIFT) | \ + ((intid) & SGIR_INTID_MASK)) + /******************************************************************************* * GICv2 specific CPU interface register offsets and constants. ******************************************************************************/ @@ -157,6 +170,7 @@ void gicv2_enable_interrupt(unsigned int id); void gicv2_disable_interrupt(unsigned int id); void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority); void gicv2_set_interrupt_type(unsigned int id, unsigned int type); +void gicv2_raise_sgi(int sgi_num, int proc_num); #endif /* __ASSEMBLY__ */ #endif /* __GICV2_H__ */ diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h index 68430fb0..bf294f13 100644 --- a/include/drivers/arm/gicv3.h +++ b/include/drivers/arm/gicv3.h @@ -24,6 +24,9 @@ /* Constant to categorize LPI interrupt */ #define MIN_LPI_ID 8192 +/* GICv3 can only target up to 16 PEs with SGI */ +#define GICV3_MAX_SGI_TARGETS 16 + /******************************************************************************* * GICv3 specific Distributor interface register offsets and constants. ******************************************************************************/ @@ -165,6 +168,27 @@ #define IAR1_EL1_INTID_SHIFT 0 #define IAR1_EL1_INTID_MASK 0xffffff +/* ICC SGI macros */ +#define SGIR_TGT_MASK 0xffff +#define SGIR_AFF1_SHIFT 16 +#define SGIR_INTID_SHIFT 24 +#define SGIR_INTID_MASK 0xf +#define SGIR_AFF2_SHIFT 32 +#define SGIR_IRM_SHIFT 40 +#define SGIR_IRM_MASK 0x1 +#define SGIR_AFF3_SHIFT 48 +#define SGIR_AFF_MASK 0xf + +#define SGIR_IRM_TO_AFF 0 + +#define GICV3_SGIR_VALUE(aff3, aff2, aff1, intid, irm, tgt) \ + ((((uint64_t) (aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \ + (((uint64_t) (irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \ + (((uint64_t) (aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \ + (((intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \ + (((aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \ + ((tgt) & SGIR_TGT_MASK)) + /***************************************************************************** * GICv3 ITS registers and constants *****************************************************************************/ @@ -357,6 +381,7 @@ void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, unsigned int priority); void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, unsigned int group); +void gicv3_raise_secure_g0_sgi(int sgi_num, u_register_t target); #endif /* __ASSEMBLY__ */ #endif /* __GICV3_H__ */ diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h index 5fbb83a6..e2c5f24f 100644 --- a/include/lib/aarch32/arch.h +++ b/include/lib/aarch32/arch.h @@ -44,6 +44,7 @@ (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) #define MPIDR_AFFLVL2_VAL(mpidr) \ (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) +#define MPIDR_AFFLVL3_VAL(mpidr) 0 /* * The MPIDR_MAX_AFFLVL count starts from 0. Take care to diff --git a/include/lib/aarch32/arch_helpers.h b/include/lib/aarch32/arch_helpers.h index 1f4f2162..c8caea28 100644 --- a/include/lib/aarch32/arch_helpers.h +++ b/include/lib/aarch32/arch_helpers.h @@ -266,6 +266,7 @@ DEFINE_COPROCR_RW_FUNCS(icc_iar0_el1, ICC_IAR0) DEFINE_COPROCR_RW_FUNCS(icc_iar1_el1, ICC_IAR1) DEFINE_COPROCR_RW_FUNCS(icc_eoir0_el1, ICC_EOIR0) DEFINE_COPROCR_RW_FUNCS(icc_eoir1_el1, ICC_EOIR1) +DEFINE_COPROCR_RW_FUNCS_64(icc_sgi0r_el1, ICC_SGI0R_EL1_64) DEFINE_COPROCR_RW_FUNCS(hdcr, HDCR) DEFINE_COPROCR_RW_FUNCS(cnthp_ctl, CNTHP_CTL) @@ -325,4 +326,7 @@ DEFINE_DCOP_PARAM_FUNC(cvac, DCCMVAC) #define read_ctr_el0() read_ctr() +#define write_icc_sgi0r_el1(_v) \ + write64_icc_sgi0r_el1(_v) + #endif /* __ARCH_HELPERS_H__ */ diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 3fb6846c..bbe1e4f9 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -77,6 +77,7 @@ #define ICC_IAR1_EL1 S3_0_c12_c12_0 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 +#define ICC_SGI0R_EL1 S3_0_c12_c11_7 /******************************************************************************* * Generic timer memory mapped registers & offsets diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h index dbbbaeb0..b880497c 100644 --- a/include/lib/aarch64/arch_helpers.h +++ b/include/lib/aarch64/arch_helpers.h @@ -322,6 +322,7 @@ DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1) DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1) DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1) DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1) +DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1) #define IS_IN_EL(x) \ diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h index c97b7d38..b4e33d9b 100644 --- a/include/plat/common/platform.h +++ b/include/plat/common/platform.h @@ -82,6 +82,7 @@ void plat_ic_enable_interrupt(unsigned int id); int plat_ic_has_interrupt_type(unsigned int type); void plat_ic_set_interrupt_type(unsigned int id, unsigned int type); void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority); +void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target); /******************************************************************************* * Optional common functions (may be overridden) |