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authorEleanor Bonnici <Eleanor.bonnici@arm.com>2017-08-09 16:42:40 +0100
committerJeenu Viswambharan <jeenu.viswambharan@arm.com>2017-08-29 13:52:48 +0100
commit80bcf98151299473771e77678d57b30cb4a65aca (patch)
tree51c49c24e12a7666499bc13e68198ce4f997c210 /lib
parente4e6c4be6f415f4389aa9fee6f226ad0bf0e1637 (diff)
downloadarm-trusted-firmware-80bcf98151299473771e77678d57b30cb4a65aca.tar.gz
CPU: Correct names of implementation-defined aux regs
At present, various CPU register macros that refer to CPUACTLR are named ACTLR. This patch fixes that. The previous register names are retained, but guarded by the ERROR_DEPRECATED macro, so as not to break platforms that continue using the old names. Change-Id: Ia872196d81803f8f390b887d149e0fd054df519b Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Diffstat (limited to 'lib')
-rw-r--r--lib/cpus/aarch32/cortex_a53.S12
-rw-r--r--lib/cpus/aarch32/cortex_a57.S52
-rw-r--r--lib/cpus/aarch32/cortex_a72.S6
-rw-r--r--lib/cpus/aarch64/cortex_a53.S14
-rw-r--r--lib/cpus/aarch64/cortex_a57.S52
-rw-r--r--lib/cpus/aarch64/cortex_a72.S8
6 files changed, 72 insertions, 72 deletions
diff --git a/lib/cpus/aarch32/cortex_a53.S b/lib/cpus/aarch32/cortex_a53.S
index bc2c7628..74cedc35 100644
--- a/lib/cpus/aarch32/cortex_a53.S
+++ b/lib/cpus/aarch32/cortex_a53.S
@@ -84,9 +84,9 @@ func a53_disable_non_temporal_hint
mov lr, r2
cmp r0, #ERRATA_NOT_APPLIES
beq 1f
- ldcopr16 r0, r1, CORTEX_A53_ACTLR
- orr64_imm r0, r1, CORTEX_A53_ACTLR_DTAH
- stcopr16 r0, r1, CORTEX_A53_ACTLR
+ ldcopr16 r0, r1, CORTEX_A53_CPUACTLR
+ orr64_imm r0, r1, CORTEX_A53_CPUACTLR_DTAH
+ stcopr16 r0, r1, CORTEX_A53_CPUACTLR
1:
bx lr
endfunc a53_disable_non_temporal_hint
@@ -118,9 +118,9 @@ func errata_a53_855873_wa
mov lr, r2
cmp r0, #ERRATA_NOT_APPLIES
beq 1f
- ldcopr16 r0, r1, CORTEX_A53_ACTLR
- orr64_imm r0, r1, CORTEX_A53_ACTLR_ENDCCASCI
- stcopr16 r0, r1, CORTEX_A53_ACTLR
+ ldcopr16 r0, r1, CORTEX_A53_CPUACTLR
+ orr64_imm r0, r1, CORTEX_A53_CPUACTLR_ENDCCASCI
+ stcopr16 r0, r1, CORTEX_A53_CPUACTLR
1:
bx lr
endfunc errata_a53_855873_wa
diff --git a/lib/cpus/aarch32/cortex_a57.S b/lib/cpus/aarch32/cortex_a57.S
index a791e4ee..e4aad790 100644
--- a/lib/cpus/aarch32/cortex_a57.S
+++ b/lib/cpus/aarch32/cortex_a57.S
@@ -67,9 +67,9 @@ func errata_a57_806969_wa
mov lr, r2
cmp r0, #ERRATA_NOT_APPLIES
beq 1f
- ldcopr16 r0, r1, CORTEX_A57_ACTLR
- orr64_imm r0, r1, CORTEX_A57_ACTLR_NO_ALLOC_WBWA
- stcopr16 r0, r1, CORTEX_A57_ACTLR
+ ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
+ orr64_imm r0, r1, CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA
+ stcopr16 r0, r1, CORTEX_A57_CPUACTLR
1:
bx lr
endfunc errata_a57_806969_wa
@@ -111,9 +111,9 @@ func errata_a57_813420_wa
mov lr, r2
cmp r0, #ERRATA_NOT_APPLIES
beq 1f
- ldcopr16 r0, r1, CORTEX_A57_ACTLR
- orr64_imm r0, r1, CORTEX_A57_ACTLR_DCC_AS_DCCI
- stcopr16 r0, r1, CORTEX_A57_ACTLR
+ ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
+ orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DCC_AS_DCCI
+ stcopr16 r0, r1, CORTEX_A57_CPUACTLR
1:
bx lr
endfunc errata_a57_813420_wa
@@ -143,9 +143,9 @@ func a57_disable_ldnp_overread
mov lr, r2
cmp r0, #ERRATA_NOT_APPLIES
beq 1f
- ldcopr16 r0, r1, CORTEX_A57_ACTLR
- orr64_imm r0, r1, CORTEX_A57_ACTLR_DIS_OVERREAD
- stcopr16 r0, r1, CORTEX_A57_ACTLR
+ ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
+ orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_OVERREAD
+ stcopr16 r0, r1, CORTEX_A57_CPUACTLR
1:
bx lr
endfunc a57_disable_ldnp_overread
@@ -172,9 +172,9 @@ func errata_a57_826974_wa
mov lr, r2
cmp r0, #ERRATA_NOT_APPLIES
beq 1f
- ldcopr16 r0, r1, CORTEX_A57_ACTLR
- orr64_imm r0, r1, CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB
- stcopr16 r0, r1, CORTEX_A57_ACTLR
+ ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
+ orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB
+ stcopr16 r0, r1, CORTEX_A57_CPUACTLR
1:
bx lr
endfunc errata_a57_826974_wa
@@ -201,9 +201,9 @@ func errata_a57_826977_wa
mov lr, r2
cmp r0, #ERRATA_NOT_APPLIES
beq 1f
- ldcopr16 r0, r1, CORTEX_A57_ACTLR
- orr64_imm r0, r1, CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE
- stcopr16 r0, r1, CORTEX_A57_ACTLR
+ ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
+ orr64_imm r0, r1, CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE
+ stcopr16 r0, r1, CORTEX_A57_CPUACTLR
1:
bx lr
endfunc errata_a57_826977_wa
@@ -230,15 +230,15 @@ func errata_a57_828024_wa
mov lr, r2
cmp r0, #ERRATA_NOT_APPLIES
beq 1f
- ldcopr16 r0, r1, CORTEX_A57_ACTLR
+ ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
/*
- * Setting the relevant bits in CORTEX_A57_ACTLR has to be done in 2
+ * Setting the relevant bits in CORTEX_A57_CPUACTLR has to be done in 2
* instructions here because the resulting bitmask doesn't fit in a
* 16-bit value so it cannot be encoded in a single instruction.
*/
- orr64_imm r0, r1, CORTEX_A57_ACTLR_NO_ALLOC_WBWA
- orr64_imm r0, r1, (CORTEX_A57_ACTLR_DIS_L1_STREAMING | CORTEX_A57_ACTLR_DIS_STREAMING)
- stcopr16 r0, r1, CORTEX_A57_ACTLR
+ orr64_imm r0, r1, CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA
+ orr64_imm r0, r1, (CORTEX_A57_CPUACTLR_DIS_L1_STREAMING | CORTEX_A57_CPUACTLR_DIS_STREAMING)
+ stcopr16 r0, r1, CORTEX_A57_CPUACTLR
1:
bx lr
endfunc errata_a57_828024_wa
@@ -265,9 +265,9 @@ func errata_a57_829520_wa
mov lr, r2
cmp r0, #ERRATA_NOT_APPLIES
beq 1f
- ldcopr16 r0, r1, CORTEX_A57_ACTLR
- orr64_imm r0, r1, CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR
- stcopr16 r0, r1, CORTEX_A57_ACTLR
+ ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
+ orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR
+ stcopr16 r0, r1, CORTEX_A57_CPUACTLR
1:
bx lr
endfunc errata_a57_829520_wa
@@ -294,9 +294,9 @@ func errata_a57_833471_wa
mov lr, r2
cmp r0, #ERRATA_NOT_APPLIES
beq 1f
- ldcopr16 r0, r1, CORTEX_A57_ACTLR
- orr64_imm r1, r1, CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH
- stcopr16 r0, r1, CORTEX_A57_ACTLR
+ ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
+ orr64_imm r1, r1, CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH
+ stcopr16 r0, r1, CORTEX_A57_CPUACTLR
1:
bx lr
endfunc errata_a57_833471_wa
diff --git a/lib/cpus/aarch32/cortex_a72.S b/lib/cpus/aarch32/cortex_a72.S
index cdd83adf..d164cfd2 100644
--- a/lib/cpus/aarch32/cortex_a72.S
+++ b/lib/cpus/aarch32/cortex_a72.S
@@ -29,9 +29,9 @@ endfunc cortex_a72_disable_l2_prefetch
* ---------------------------------------------
*/
func cortex_a72_disable_hw_prefetcher
- ldcopr16 r0, r1, CORTEX_A72_ACTLR
- orr64_imm r0, r1, CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH
- stcopr16 r0, r1, CORTEX_A72_ACTLR
+ ldcopr16 r0, r1, CORTEX_A72_CPUACTLR
+ orr64_imm r0, r1, CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
+ stcopr16 r0, r1, CORTEX_A72_CPUACTLR
isb
dsb ish
bx lr
diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S
index 7a17f8f1..3e480bc1 100644
--- a/lib/cpus/aarch64/cortex_a53.S
+++ b/lib/cpus/aarch64/cortex_a53.S
@@ -93,9 +93,9 @@ func a53_disable_non_temporal_hint
mov x17, x30
bl check_errata_disable_non_temporal_hint
cbz x0, 1f
- mrs x1, CORTEX_A53_ACTLR_EL1
- orr x1, x1, #CORTEX_A53_ACTLR_DTAH
- msr CORTEX_A53_ACTLR_EL1, x1
+ mrs x1, CORTEX_A53_CPUACTLR_EL1
+ orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_DTAH
+ msr CORTEX_A53_CPUACTLR_EL1, x1
1:
ret x17
endfunc a53_disable_non_temporal_hint
@@ -126,9 +126,9 @@ func errata_a53_855873_wa
bl check_errata_855873
cbz x0, 1f
- mrs x1, CORTEX_A53_ACTLR_EL1
- orr x1, x1, #CORTEX_A53_ACTLR_ENDCCASCI
- msr CORTEX_A53_ACTLR_EL1, x1
+ mrs x1, CORTEX_A53_CPUACTLR_EL1
+ orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_ENDCCASCI
+ msr CORTEX_A53_CPUACTLR_EL1, x1
1:
ret x17
endfunc errata_a53_855873_wa
@@ -300,7 +300,7 @@ func cortex_a53_cpu_reg_dump
mrs x8, CORTEX_A53_ECTLR_EL1
mrs x9, CORTEX_A53_MERRSR_EL1
mrs x10, CORTEX_A53_L2MERRSR_EL1
- mrs x11, CORTEX_A53_ACTLR_EL1
+ mrs x11, CORTEX_A53_CPUACTLR_EL1
ret
endfunc cortex_a53_cpu_reg_dump
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index 9e8480a3..289d0d4e 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -78,9 +78,9 @@ func errata_a57_806969_wa
mov x17, x30
bl check_errata_806969
cbz x0, 1f
- mrs x1, CORTEX_A57_ACTLR_EL1
- orr x1, x1, #CORTEX_A57_ACTLR_NO_ALLOC_WBWA
- msr CORTEX_A57_ACTLR_EL1, x1
+ mrs x1, CORTEX_A57_CPUACTLR_EL1
+ orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
+ msr CORTEX_A57_CPUACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_806969_wa
@@ -120,9 +120,9 @@ func errata_a57_813420_wa
mov x17, x30
bl check_errata_813420
cbz x0, 1f
- mrs x1, CORTEX_A57_ACTLR_EL1
- orr x1, x1, #CORTEX_A57_ACTLR_DCC_AS_DCCI
- msr CORTEX_A57_ACTLR_EL1, x1
+ mrs x1, CORTEX_A57_CPUACTLR_EL1
+ orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI
+ msr CORTEX_A57_CPUACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_813420_wa
@@ -150,9 +150,9 @@ func a57_disable_ldnp_overread
mov x17, x30
bl check_errata_disable_ldnp_overread
cbz x0, 1f
- mrs x1, CORTEX_A57_ACTLR_EL1
- orr x1, x1, #CORTEX_A57_ACTLR_DIS_OVERREAD
- msr CORTEX_A57_ACTLR_EL1, x1
+ mrs x1, CORTEX_A57_CPUACTLR_EL1
+ orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD
+ msr CORTEX_A57_CPUACTLR_EL1, x1
1:
ret x17
endfunc a57_disable_ldnp_overread
@@ -177,9 +177,9 @@ func errata_a57_826974_wa
mov x17, x30
bl check_errata_826974
cbz x0, 1f
- mrs x1, CORTEX_A57_ACTLR_EL1
- orr x1, x1, #CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB
- msr CORTEX_A57_ACTLR_EL1, x1
+ mrs x1, CORTEX_A57_CPUACTLR_EL1
+ orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB
+ msr CORTEX_A57_CPUACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_826974_wa
@@ -204,9 +204,9 @@ func errata_a57_826977_wa
mov x17, x30
bl check_errata_826977
cbz x0, 1f
- mrs x1, CORTEX_A57_ACTLR_EL1
- orr x1, x1, #CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE
- msr CORTEX_A57_ACTLR_EL1, x1
+ mrs x1, CORTEX_A57_CPUACTLR_EL1
+ orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE
+ msr CORTEX_A57_CPUACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_826977_wa
@@ -231,16 +231,16 @@ func errata_a57_828024_wa
mov x17, x30
bl check_errata_828024
cbz x0, 1f
- mrs x1, CORTEX_A57_ACTLR_EL1
+ mrs x1, CORTEX_A57_CPUACTLR_EL1
/*
* Setting the relevant bits in CPUACTLR_EL1 has to be done in 2
* instructions here because the resulting bitmask doesn't fit in a
* 16-bit value so it cannot be encoded in a single instruction.
*/
- orr x1, x1, #CORTEX_A57_ACTLR_NO_ALLOC_WBWA
- orr x1, x1, #(CORTEX_A57_ACTLR_DIS_L1_STREAMING | \
- CORTEX_A57_ACTLR_DIS_STREAMING)
- msr CORTEX_A57_ACTLR_EL1, x1
+ orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
+ orr x1, x1, #(CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING | \
+ CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING)
+ msr CORTEX_A57_CPUACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_828024_wa
@@ -265,9 +265,9 @@ func errata_a57_829520_wa
mov x17, x30
bl check_errata_829520
cbz x0, 1f
- mrs x1, CORTEX_A57_ACTLR_EL1
- orr x1, x1, #CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR
- msr CORTEX_A57_ACTLR_EL1, x1
+ mrs x1, CORTEX_A57_CPUACTLR_EL1
+ orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR
+ msr CORTEX_A57_CPUACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_829520_wa
@@ -292,9 +292,9 @@ func errata_a57_833471_wa
mov x17, x30
bl check_errata_833471
cbz x0, 1f
- mrs x1, CORTEX_A57_ACTLR_EL1
- orr x1, x1, #CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH
- msr CORTEX_A57_ACTLR_EL1, x1
+ mrs x1, CORTEX_A57_CPUACTLR_EL1
+ orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH
+ msr CORTEX_A57_CPUACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_833471_wa
diff --git a/lib/cpus/aarch64/cortex_a72.S b/lib/cpus/aarch64/cortex_a72.S
index 0307627c..5de2bf0f 100644
--- a/lib/cpus/aarch64/cortex_a72.S
+++ b/lib/cpus/aarch64/cortex_a72.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -42,9 +42,9 @@ endfunc cortex_a72_disable_l2_prefetch
* ---------------------------------------------
*/
func cortex_a72_disable_hw_prefetcher
- mrs x0, CORTEX_A72_ACTLR_EL1
- orr x0, x0, #CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH
- msr CORTEX_A72_ACTLR_EL1, x0
+ mrs x0, CORTEX_A72_CPUACTLR_EL1
+ orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
+ msr CORTEX_A72_CPUACTLR_EL1, x0
isb
dsb ish
ret
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-17 02:41:57 +0000