diff options
| author | Dmitry Shmidt <dimitrysh@google.com> | 2017-11-09 20:50:31 +0000 |
|---|---|---|
| committer | android-build-merger <android-build-merger@google.com> | 2017-11-09 20:50:31 +0000 |
| commit | 72a61be33b7361b5c3f603239867003126afb8f5 (patch) | |
| tree | 068e57596704dce1bc7fd97a07b205a2e2f22d42 /plat/arm/board/common/board_css_common.c | |
| parent | 8fa3096942d2faed55122efd47348dacca991141 (diff) | |
| parent | d7f137ecb773c12918640e235089c0cdf5a86887 (diff) | |
| download | arm-trusted-firmware-72a61be33b7361b5c3f603239867003126afb8f5.tar.gz | |
Merge remote-tracking branch 'aosp/upstream-hikey' into armtf
am: d7f137ecb7
Change-Id: I73ec8feea370c133e2da915ac14b8631396eea26
Diffstat (limited to 'plat/arm/board/common/board_css_common.c')
| -rw-r--r-- | plat/arm/board/common/board_css_common.c | 84 |
1 files changed, 84 insertions, 0 deletions
diff --git a/plat/arm/board/common/board_css_common.c b/plat/arm/board/common/board_css_common.c new file mode 100644 index 00000000..032ebdf7 --- /dev/null +++ b/plat/arm/board/common/board_css_common.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include <arm_def.h> +#include <plat_arm.h> + +/* + * Table of memory regions for different BL stages to map using the MMU. + * This doesn't include Trusted SRAM as arm_setup_page_tables() already + * takes care of mapping it. + */ +#ifdef IMAGE_BL1 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + V2M_MAP_FLASH0_RO, + V2M_MAP_IOFPGA, + CSS_MAP_DEVICE, + SOC_CSS_MAP_DEVICE, +#if TRUSTED_BOARD_BOOT + /* Map DRAM to authenticate NS_BL2U image. */ + ARM_MAP_NS_DRAM1, +#endif + {0} +}; +#endif +#ifdef IMAGE_BL2 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + V2M_MAP_FLASH0_RO, +#ifdef PLAT_ARM_MEM_PROT_ADDR + ARM_V2M_MAP_MEM_PROTECT, +#endif + V2M_MAP_IOFPGA, + CSS_MAP_DEVICE, + SOC_CSS_MAP_DEVICE, + ARM_MAP_NS_DRAM1, +#ifdef AARCH64 + ARM_MAP_DRAM2, +#endif +#ifdef SPD_tspd + ARM_MAP_TSP_SEC_MEM, +#endif +#ifdef SPD_opteed + ARM_MAP_OPTEE_CORE_MEM, + ARM_OPTEE_PAGEABLE_LOAD_MEM, +#endif + {0} +}; +#endif +#ifdef IMAGE_BL2U +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + CSS_MAP_DEVICE, + SOC_CSS_MAP_DEVICE, + {0} +}; +#endif +#ifdef IMAGE_BL31 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + V2M_MAP_IOFPGA, + CSS_MAP_DEVICE, +#ifdef PLAT_ARM_MEM_PROT_ADDR + ARM_V2M_MAP_MEM_PROTECT, +#endif + SOC_CSS_MAP_DEVICE, + {0} +}; +#endif +#ifdef IMAGE_BL32 +const mmap_region_t plat_arm_mmap[] = { +#ifdef AARCH32 + ARM_MAP_SHARED_RAM, +#endif + V2M_MAP_IOFPGA, + CSS_MAP_DEVICE, + SOC_CSS_MAP_DEVICE, + {0} +}; +#endif + +ARM_CASSERT_MMAP |