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| author | Dmitry Shmidt <dimitrysh@google.com> | 2017-11-09 21:59:15 +0000 |
|---|---|---|
| committer | android-build-merger <android-build-merger@google.com> | 2017-11-09 21:59:15 +0000 |
| commit | 377cb66540e9f5f26b97c779a411a302eeaf45a9 (patch) | |
| tree | 068e57596704dce1bc7fd97a07b205a2e2f22d42 /plat/nvidia/tegra/soc/t210/plat_secondary.c | |
| parent | b52ceb2c86de78504cadaf718a0b0faef1875b7e (diff) | |
| parent | f80b69635a11abe97224cdd5699b7b11bf3293f5 (diff) | |
| download | arm-trusted-firmware-377cb66540e9f5f26b97c779a411a302eeaf45a9.tar.gz | |
Merge remote-tracking branch 'aosp/upstream-hikey' into armtf am: d7f137ecb7 am: 72a61be33b
am: f80b69635a
Change-Id: I121dedc746e6db36c8e25fa019aa5f10c3ee22f6
Diffstat (limited to 'plat/nvidia/tegra/soc/t210/plat_secondary.c')
| -rw-r--r-- | plat/nvidia/tegra/soc/t210/plat_secondary.c | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/plat/nvidia/tegra/soc/t210/plat_secondary.c b/plat/nvidia/tegra/soc/t210/plat_secondary.c new file mode 100644 index 00000000..ecb258b9 --- /dev/null +++ b/plat/nvidia/tegra/soc/t210/plat_secondary.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <debug.h> +#include <mmio.h> +#include <pmc.h> +#include <tegra_def.h> + +#define SB_CSR 0x0 +#define SB_CSR_NS_RST_VEC_WR_DIS (1 << 1) + +/* CPU reset vector */ +#define SB_AA64_RESET_LOW 0x30 /* width = 31:0 */ +#define SB_AA64_RESET_HI 0x34 /* width = 11:0 */ + +extern void tegra_secure_entrypoint(void); + +/******************************************************************************* + * Setup secondary CPU vectors + ******************************************************************************/ +void plat_secondary_setup(void) +{ + uint32_t val; + uint64_t reset_addr = (uint64_t)tegra_secure_entrypoint; + + INFO("Setting up secondary CPU boot\n"); + + /* setup secondary CPU vector */ + mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_LOW, + (reset_addr & 0xFFFFFFFF) | 1); + val = reset_addr >> 32; + mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_HI, val & 0x7FF); + + /* configure PMC */ + tegra_pmc_cpu_setup(reset_addr); + tegra_pmc_lock_cpu_vectors(); +} |