diff options
Diffstat (limited to 'include/lib/cpus/aarch64/cortex_a57.h')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a57.h | 115 |
1 files changed, 75 insertions, 40 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index 6128b169..6c45c066 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -1,66 +1,101 @@ /* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef __CORTEX_A57_H__ #define __CORTEX_A57_H__ +#include <utils_def.h> /* Cortex-A57 midr for revision 0 */ -#define CORTEX_A57_MIDR 0x410FD070 +#define CORTEX_A57_MIDR U(0x410FD070) + +/* Retention timer tick definitions */ +#define RETENTION_ENTRY_TICKS_2 U(0x1) +#define RETENTION_ENTRY_TICKS_8 U(0x2) +#define RETENTION_ENTRY_TICKS_32 U(0x3) +#define RETENTION_ENTRY_TICKS_64 U(0x4) +#define RETENTION_ENTRY_TICKS_128 U(0x5) +#define RETENTION_ENTRY_TICKS_256 U(0x6) +#define RETENTION_ENTRY_TICKS_512 U(0x7) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ +#define CORTEX_A57_ECTLR_EL1 S3_1_C15_C2_1 + +#define CORTEX_A57_ECTLR_SMP_BIT (U(1) << 6) +#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (U(1) << 38) +#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (U(0x3) << 35) +#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (U(0x3) << 32) -#define CPUECTLR_SMP_BIT (1 << 6) -#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) -#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) -#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) +#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0) +#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) + +/******************************************************************************* + * CPU Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CORTEX_A57_MERRSR_EL1 S3_1_C15_C2_2 /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ +#define CORTEX_A57_CPUACTLR_EL1 S3_1_C15_C2_0 -#define CPUACTLR_NO_ALLOC_WBWA (1 << 49) -#define CPUACTLR_DCC_AS_DCCI (1 << 44) +#define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59) +#define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54) +#define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52) +#define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) +#define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) +#define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38) +#define CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) +#define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27) +#define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25) +#define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) /******************************************************************************* * L2 Control register specific definitions. ******************************************************************************/ -#define L2CTLR_EL1 S3_1_C11_C0_2 /* Instruction def. */ +#define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2 + +#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) +#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) + +#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) +#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) -#define L2CTLR_DATA_RAM_LATENCY_SHIFT 0 -#define L2CTLR_TAG_RAM_LATENCY_SHIFT 6 +#define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21) + +/******************************************************************************* + * L2 Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A57_L2ECTLR_EL1 S3_1_C11_C0_3 + +#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT U(0) +#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (U(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) + +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3 + +#if !ERROR_DEPRECATED +/* + * These registers were previously wrongly named. Provide previous definitions so + * as not to break platforms that continue using them. + */ +#define CORTEX_A57_ACTLR_EL1 CORTEX_A57_CPUACTLR_EL1 -#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2 -#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB +#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE +#define CORTEX_A57_ACTLR_DIS_OVERREAD CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD +#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA +#define CORTEX_A57_ACTLR_DCC_AS_DCCI CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI +#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH +#define CORTEX_A57_ACTLR_DIS_STREAMING CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING +#define CORTEX_A57_ACTLR_DIS_L1_STREAMING CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING +#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR +#endif /* !ERROR_DEPRECATED */ #endif /* __CORTEX_A57_H__ */ |