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Change-Id: I6d342f9d86f1e238a321b714f1d1408a192ae62d
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Bug: 68860345
Bug: 69058154
Bug: 151953481
Test: no code changes
Change-Id: Ic53d483df23cfde5c06f2d77d0496b731bc34448
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am: 3dc6483197 -s ours
am skip reason: subject contains skip directive
Change-Id: I78233471fd4f80ab536b0e7929ec263a13d53e1e
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Bug: 120848293
Change-Id: Ia7ff0d02ab5c95c93cf1a4a1438863757dfcab64
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ours
am: e5930d85de -s ours
Change-Id: I38cff46c1293c300a7cce6b6904d11b1a7115c8c
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am: 3bd4ac90be -s ours
Change-Id: I6f14e4d0d459d3f4b36c67d5e12e0ba7d01b0b3f
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am: 9ad008461f -s ours
Change-Id: I91dddab610aaaa8cc9146c4c055a322fcc5ad918
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Merge pie-platform-release (PPRL.181205.001, history only) into master
Bug: 120502534
Change-Id: Ibadf1cb156b2024ef2fb40e1d36e6b6440ebdfc0
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Change-Id: If2dad524a52e614a178d234784344e7d95deb3d1
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am: 2afd8f04b3
am: 090aac9db6
Change-Id: I61511d9c7825ae39e206d7410e5ca9f0f0259472
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am: 2afd8f04b3
Change-Id: I6476ff0764e976ce4b3a684c1ea0ff3d702fb09c
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am: 8608ac5262
Change-Id: I874c82fd658d72570256f5d00766689d741bd95c
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Change-Id: I37e6b218f2745a4432645bbff43899d954c19e41
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Hikey960: Fix hikey960 pcie mount fail
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Set IOC_AO_IOMG_033 function from GPIO213 to PCIE_CLKREQ_N
bit[0-2]: 000: GPIO_213;
001: PCIE_CLKREQ_N;
010: GPIO_018_SH;
100: GPIO_014_SE;
110: FAC_TEST24;
111: FAC_TEST24;
bit[3-31]: reserved
Signed-off-by: Guangtao Zhang <zhangguangtao@hisilicon.com>
Tested-by: Yao Chen <chenyao11@huawei.com>
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Change-Id: Ie154b73171eca6a2e8d2269e582f7e8b981c789b
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am: 07f5202bf4
Change-Id: I4c571d47fce5087cc0bf958bf278342c9df85d53
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Change-Id: I34e501c7c9839020e53047fec7470c8aec9c7e44
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Change-Id: Ieed88b8053ca3e7249dee5fa8afe4549d39635f1
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Change-Id: I72f34988badcfd923c1e3eab3fef6f0bada1f873
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am: 72a61be33b
am: f80b69635a
Change-Id: I121dedc746e6db36c8e25fa019aa5f10c3ee22f6
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am: 72a61be33b
Change-Id: I166618ba5d78485718f29d2e74fea65155d92949
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am: d7f137ecb7
Change-Id: I73ec8feea370c133e2da915ac14b8631396eea26
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Change-Id: Ic77734daa3ba792cf235d52b49250a197de4328a
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Update armtf branch AOSP uses to upstream armtf code
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Avoid use of undefined macros
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Change sizeof to use type of struct not function
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qemu: update deprecated interrupt registering
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Enable GICv3 save for ARM platforms
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Registered interrupts are configured in edge detection as the default
previous configuration assumed in previous code.
Not target mask required as Qemu BL31 will not send/route SGIs.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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aarch64: Add PubSub events to capture security state transitions
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These macros are only defined for corresponding image,
and they are undefined for other images. It means that we have
to use ifdef or defined() instead of relying on being 0 by default.
Change-Id: Iad11efab9830ddf471599b46286e1c56581ef5a7
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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ARM_TSP_RAM_LOCATION_ID was defined only in AARCH64, but the macro
was also used in AARCH32, and it meant that it was taking the value 0,
which happened to equal ARM_TRUSTED_SRAM_ID.
Change-Id: If9f4dbee1a2ba15e7806f2a03305b554bd327363
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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debug.S was using macros defined in debug.h, but since it didn't
include it, these macros were taking the value 0, which means that
all the preprocessor conditionals were wrong.
Change-Id: If4ca81cc5a1662991589f914a2557ceff0eaaede
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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Add FWU booting instructions to the user guide
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Add platform hooks for boot redundancy support
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Change sizeof call so it references a static type instead of return of
a function in order to be MISRA compliant.
Change-Id: I6f1adb206073d6cd200156e281b8d76249e3af0e
Signed-off-by: Joel Hutton <joel.hutton@arm.com>
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Add events that trigger before entry to normal/secure world. The
events trigger after the normal/secure context has been restored.
Similarly add events that trigger after leaving normal/secure world.
The events trigger after the normal/secure context has been saved.
Change-Id: I1b48a7ea005d56b1f25e2b5313d77e67d2f02bc5
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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FWU uses additional images that have to be loaded,
and this patch adds the documentation of how to do
it in FVP and Juno.
Change-Id: I1a40641c11c5a4c8db0aadeaeb2bec30c9279e28
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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Big transition to upstream ARMTF code.
This merges the aosp/mater code with fd3bba4bd523 but merges
such that the tree should be identical with the fd3bba4bd523
side of the merge.
Change-Id: Ib416a13ce19c6c26fb62c38ccc6fdfbbdf9c4304
Signed-off-by: John Stultz <john.stultz@linaro.org>
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Change the default option of ARM_TSP_RAM_LOCATION and Enlarge the BL2 size on ARM platforms
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So for some reason, when building with the android toolchain,
the hikey ddr initialization code gets stuck.
Adding a NOTICE message here avoids it, which basically tells me
something is broken (possibly the toolchain reordering operations,
or some other memory barrier type issue).
But here we are.
Change-Id: I712c3e4463601def012e51120189fd142311ffd1
Signed-off-by: John Stultz <john.stultz@linaro.org>
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Avoid build issues with the Android toolchain
Change-Id: I2b3f7b7e250d71dafc92eec1ffb279127888e521
Signed-off-by: John Stultz <john.stultz@linaro.org>
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qemu/optee: load OP-TEE pageable part 2MB above OP-TEE image
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qemu: fix holding pen mailbox sequence
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OP-TEE dedicates the end of the Qemu secure DRAM as specific out-of-TEE
secure RAM. To support this configuration the trusted firmware should
not load OP-TEE resources in this area.
To overcome the issue, OP-TEE pageable image is now loaded 2MByte above
the secure RAM base address.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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qemu: Add support for Trusted Board Boot
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This patch adds support for TBB to qemu. An RSA ROT keypair is generated at
build time and is included into BL1/BL2. The key and content certificates
are read over semihosting.
Fixes ARM-software/tf-issues#526
Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
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For Trusted Board Boot, BL2 needs more space to support the ECDSA
and ECDSA+RSA algorithms.
Change-Id: Ie7eda9a1315ce836dbc6d18d6588f8d17891a92d
Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
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