diff options
Diffstat (limited to 'hifi/xaf/hifi-dpf/include/sys/xt-shmem')
18 files changed, 2089 insertions, 0 deletions
diff --git a/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/arch_hifi330.h b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/arch_hifi330.h new file mode 100644 index 00000000..74b12220 --- /dev/null +++ b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/arch_hifi330.h @@ -0,0 +1,134 @@ +/******************************************************************************* +* Copyright (C) 2018 Cadence Design Systems, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* "Software"), to use this Software with Cadence processor cores only and +* not with any other processors and platforms, subject to +* the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +******************************************************************************/ + +#include <xtensa/simcall.h> +#include <xtensa/corebits.h> +#include <xtensa/config/system.h> +#include <xtensa/config/core.h> + +#ifndef __ARCH_HIFI330_H__ +#define __ARCH_HIFI330_H__ + +#ifdef __ASSEMBLER__ +#include <xtensa/coreasm.h> +#endif + +#include <xtensa/corebits.h> +#include <xtensa/config/system.h> + +/* +Align a value up to nearest n-byte boundary, where n is a power of 2. +*/ +#define ALIGNUP(n, val) (((val) + (n)-1) & -(n)) + + +/******************************************************************************* +INTERRUPT STACK FRAME FOR A THREAD OR NESTED INTERRUPT +*******************************************************************************/ +#define XT_STK_EXIT 0x00 /* (offset 0) exit point for dispatch */ +#define XT_STK_PC 0x04 /* return address */ +#define XT_STK_PS 0x08 /* at level 1 PS.EXCM is set here */ +#define XT_STK_A0 0x0C +#define XT_STK_A1 0x10 /* stack ptr before interrupt */ +#define XT_STK_A2 0x14 +#define XT_STK_A3 0x18 +#define XT_STK_A4 0x1C +#define XT_STK_A5 0x20 +#define XT_STK_A6 0x24 +#define XT_STK_A7 0x28 +#define XT_STK_A8 0x2C +#define XT_STK_A9 0x30 +#define XT_STK_A10 0x34 +#define XT_STK_A11 0x38 +#define XT_STK_A12 0x3C /* Call0 callee-save */ +#define XT_STK_A13 0x40 /* Call0 callee-save */ +#define XT_STK_A14 0x44 /* Call0 callee-save */ +#define XT_STK_A15 0x48 /* Call0 callee-save */ +#define XT_STK_SAR 0x4C + +#define XT_STK_LBEG 0x50 +#define XT_STK_LEND 0x54 +#define XT_STK_LCOUNT 0x58 +#define XT_STK_NEXT1 0x5C /* next unused offset */ + +#define XT_STK_EXTRA ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + +#define XT_STK_NEXT2 (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE) + +#define XT_STK_N_TMP 3 /* # of 4-byte temp. slots */ +#define XT_STK_TMP XT_STK_NEXT2 +#define XT_STK_NEXT3 XT_STK_TMP + (4 * XT_STK_N_TMP) +#define XT_STK_FRMSZ (ALIGNUP(0x10, XT_STK_NEXT3) + 0x20) + + +/******************************************************************************* +SIMPLE STACK FRAME FOR A THREAD +*******************************************************************************/ +#define XT_SOL_EXIT XT_STK_EXIT /* code indicates solicited frame */ +#define XT_SOL_PC 0x04 /* return address (b30-31=callinc) */ +#define XT_SOL_PS 0x08 +#define XT_SOL_NEXT 0x0c /* next unused offset */ + /* there may be some unused space here */ +#define XT_SOL_A0 ALIGNUP(0x10, XT_SOL_NEXT) +#define XT_SOL_A1 XT_SOL_A0 + 4 +#define XT_SOL_A2 XT_SOL_A1 + 4 +#define XT_SOL_A3 XT_SOL_A2 + 4 +#define XT_SOL_FRMSZ ALIGNUP(0x10, XT_SOL_A3) + + +/******************************************************************************* +CO-PROCESSOR STATE SAVE AREA FOR A THREAD +*******************************************************************************/ +#define XT_CPENABLE 0 +#define XT_CPSTORED (XT_CPENABLE + 1) +#define XT_CP0_SA ALIGNUP(XCHAL_CP0_SA_ALIGN, XT_CPSTORED + 1) +#define XT_CP1_SA ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE) +#define XT_CP2_SA ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE) +#define XT_CP3_SA ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE) +#define XT_CP4_SA ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE) +#define XT_CP5_SA ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE) +#define XT_CP6_SA ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE) +#define XT_CP7_SA ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE) +#define XT_CP_SIZE ALIGNUP(4 , XT_CP7_SA + XCHAL_CP7_SA_SIZE) + +#ifdef __ASSEMBLER__ +/* Windowed */ +#define ENTRY(sz) entry sp, sz +#define ENTRY0 entry sp, 0x10 +#define RET(sz) retw +#define RET0 retw +#endif + +#define XT_TICK_PER_SEC 100 +#define XT_RTOS_INT_ENTER OS_IntEnter +#define XT_RTOS_INT_EXIT OS_IntExit +#define XT_RTOS_CP_STATE OS_GetTaskCoprocState + +#ifdef __ASSEMBLER__ +// typedef struct vos_tcb { +#define OSTCBStkPtr 0x00 // OSTCBStkPtr +#define OSTCBStkBottom 0x10 // StackAddress +//... +// } VOS_TCB; +#endif /* __ASSEMBLER__ */ + +#endif /* end of arch_balongV7r1.h */ diff --git a/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/cpu_c.h b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/cpu_c.h new file mode 100644 index 00000000..0cc0da93 --- /dev/null +++ b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/cpu_c.h @@ -0,0 +1,109 @@ +/******************************************************************************* +* Copyright (C) 2018 Cadence Design Systems, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* "Software"), to use this Software with Cadence processor cores only and +* not with any other processors and platforms, subject to +* the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +******************************************************************************/ + +#ifndef __CPU_C_H__ +#define __CPU_C_H__ + +enum OS_HOOK_TYPE_ENUM +{ + OS_HOOK_TYPE_ENTER_INTR=0, + OS_HOOK_TYPE_EXIT_INTR, + OS_HOOK_TYPE_TASK_SWITCH, + OS_HOOK_TYPE_MSG_GET, + OS_HOOK_TYPE_NMI, + OS_HOOK_TYPE_EXCEPTION, + OS_HOOK_TYPE_APPINIT, + OS_HOOK_TYPE_IDLE, + OS_HOOK_TYPE_BUTT +}; + +enum OS_INTR_CONNECT_TYPE_ENUM +{ + OS_INTR_CONNECT_00=0, /*Int 0 type / priority level NMI / 6 */ + OS_INTR_CONNECT_01, /*Int 1 type / priority level Software / 3 */ + OS_INTR_CONNECT_02, /*Int 2 type / priority level ExtLevel / 2 */ + OS_INTR_CONNECT_03, /*Int 3 type / priority level ExtLevel / 2 */ + OS_INTR_CONNECT_04, /*Int 4 type / priority level ExtLevel / 2 */ + OS_INTR_CONNECT_05, /*Int 5 type / priority level Timer / 3 */ + OS_INTR_CONNECT_06, /*Int 6 type / priority level Timer / 4 */ + OS_INTR_CONNECT_07, /*Int 7 type / priority level ExtLevel / 3 */ + OS_INTR_CONNECT_08, /*Int 8 type / priority level ExtLevel / 3 */ + OS_INTR_CONNECT_09, /*Int 9 type / priority level ExtLevel / 3 */ + OS_INTR_CONNECT_10, /*Int 10 type / priority level ExtLevel / 2 */ + OS_INTR_CONNECT_11, /*Int 11 type / priority level ExtLevel / 2 */ + OS_INTR_CONNECT_12, /*Int 12 type / priority level ExtLevel / 2 */ + OS_INTR_CONNECT_13, /*Int 13 type / priority level ExtLevel / 2 */ + OS_INTR_CONNECT_14, /*Int 14 type / priority level ExtLevel / 2 */ + OS_INTR_CONNECT_15, /*Int 15 type / priority level ExtLevel / 1 */ + OS_INTR_CONNECT_16, /*Int 16 type / priority level ExtLevel / 1 */ + OS_INTR_CONNECT_17, /*Int 17 type / priority level ExtLevel / 1 */ + OS_INTR_CONNECT_18, /*Int 18 type / priority level ExtLevel / 1 */ + OS_INTR_CONNECT_19, /*Int 19 type / priority level Timer / 2 */ + OS_INTR_CONNECT_20, /*Int 20 type / priority level ExtLevel / 1 */ + OS_INTR_CONNECT_21, /*Int 21 type / priority level ExtLevel / 1 */ + OS_INTR_CONNECT_22, /*Int 22 type / priority level ExtLevel / 1 */ + OS_INTR_CONNECT_23, /*Int 23 type / priority level ExtLevel / 1 */ + OS_INTR_CONNECT_24, /*Int 24 type / priority level ExtLevel / 1 */ + OS_INTR_CONNECT_25, /*Int 25 type / priority level ExtLevel / 1 */ + OS_INTR_CONNECT_26, /*Int 26 type / priority level ExtLevel / 1 */ + OS_INTR_CONNECT_27, /*Int 27 type / priority level ExtLevel / 1 */ + OS_INTR_CONNECT_28, /*Int 28 type / priority level ExtLevel / 1 */ + OS_INTR_CONNECT_29, /*Int 29 type / priority level ExtLevel / 1 */ + OS_INTR_CONNECT_30, /*Int 30 type / priority level ExtLevel / 1 */ + OS_INTR_CONNECT_31, /*Int 31 type / priority level ExtEdge / 1 */ + OS_INTR_CONNECT_BUTT +}; + +#define UCOM_SET_WFI_NMI(var1) asm ("waiti 5": :) + +#define UCOM_FlushCache(pAddr, uwSize) \ + xthal_dcache_region_writeback(pAddr, uwSize) + +#define UCOM_FlushCacheAll() \ + xthal_dcache_all_writeback() + +#define UCOM_InvalidateCache(pAddr, uwSize) \ + xthal_dcache_region_invalidate(pAddr, uwSize) + +#define UCOM_InvalidateCacheAll() \ + xthal_dcache_all_invalidate() + +#define ADD_TAG asm("movi a1, 0xdeadbaaf \n movi a2, 0xe8075e80 \n s32i a1, a2, 0": :) + +//typedef void (*HOOK_FUN_TYPE)(void); +typedef void (*HOOK_FUN_TYPE)(unsigned int); + +typedef void (*INTR_HOOK_FUN_TYPE )(unsigned int uwIntNo); + +typedef void (*VOS_EXCEPTION_HOOK_FUNC)( unsigned int uwExceptionNo); + +extern void *g_pfVosHookFuncTable[OS_HOOK_TYPE_BUTT]; + +extern void VOS_ConnectInterrupt(unsigned int uwIntrNo, HOOK_FUN_TYPE pfnInterruptHook); + +extern void VOS_EnableInterrupt(unsigned int uwIntNo); +extern void VOS_DisableInterrupt(unsigned int uwIntNo); + +extern void OS_UserExit(void); + + +#endif /* end of cpu_c.h */ diff --git a/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/dsp_comm.h b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/dsp_comm.h new file mode 100644 index 00000000..37646777 --- /dev/null +++ b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/dsp_comm.h @@ -0,0 +1,45 @@ +/******************************************************************************* +* Copyright (C) 2018 Cadence Design Systems, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* "Software"), to use this Software with Cadence processor cores only and +* not with any other processors and platforms, subject to +* the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +******************************************************************************/ + + +#ifndef __DSP_COMM_H__ +#define __DSP_COMM_H__ + +#include <xtensa/config/core.h> +#include <xtensa/simcall.h> + +#define DSP_FLUSH_PIECE_CACHE(addr, size) xthal_dcache_region_writeback(addr, size) +#define DSP_FLUSH_ALL_CACHE() xthal_dcache_all_writeback() +#define DSP_INVALIDATE_PIECE_CACHE(addr, size) xthal_dcache_region_invalidate(addr, size) +#define DSP_INVALIDATE_ALL_CACHE() xthal_dcache_all_invalidate() + +#define memset(d,uCData,size) dsp_memset(d,uCData,size) +#define memcpy(d,s,size) dsp_memcpy(d,s,size) +#define divsi3(a,b) division(a,b) +#define _divsi3(a,b) division(a,b) + +void dsp_memcpy(void *d, void *s, unsigned int size); +void dsp_memset(void *d, unsigned char ucData, unsigned int size); +int division(int a, int b); + +#endif /* end of dsp_comm.h */ + diff --git a/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/dsp_debug.h b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/dsp_debug.h new file mode 100644 index 00000000..0ca2d373 --- /dev/null +++ b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/dsp_debug.h @@ -0,0 +1,71 @@ +/******************************************************************************* +* Copyright (C) 2018 Cadence Design Systems, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* "Software"), to use this Software with Cadence processor cores only and +* not with any other processors and platforms, subject to +* the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +******************************************************************************/ + +#ifndef __DSP_DEBUG_H__ +#define __DSP_DEBUG_H__ + + +#define DEBUG_LEVEL 0 +#define INFO_LEVEL 1 +#define WARNING_LEVEL 1 +#define ERROR_LEVEL 1 +#define TRACE_DUMP 1 + +#define LOG_TAG " DSP_LOG" + +#if TRACE_DUMP +#define DSP_TRACE(fmt, ...) print_log(fmt" @%s:%d \n", ##__VA_ARGS__, __FUNCTION__, __LINE__) +#else +#define DSP_TRACE(fmt, ...) +#endif + +#if DEBUG_LEVEL +#define DSP_LOGD(fmt, ...) print_log(LOG_TAG"[D]%s:%d: "fmt, __FUNCTION__, __LINE__, ##__VA_ARGS__) +#else +#define DSP_LOGD(fmt, ...) +#endif + +#if INFO_LEVEL +#define DSP_LOGI(fmt, ...) print_log(LOG_TAG"[I]%s:%d: "fmt, __FUNCTION__, __LINE__, ##__VA_ARGS__) +#else +#define DSP_LOGI(fmt, ...) +#endif + +#if WARNING_LEVEL +#define DSP_LOGW(fmt, ...) print_log(LOG_TAG"[W]%s:%d: "fmt, __FUNCTION__, __LINE__, ##__VA_ARGS__) +#else +#define DSP_LOGW(fmt, ...) +#endif + +#if ERROR_LEVEL +#define DSP_LOGE(fmt, ...) print_log(LOG_TAG"[E]%s:%d: "fmt, __FUNCTION__, __LINE__, ##__VA_ARGS__) +#else ++#define DSP_LOGE(fmt, ...) +#endif + + +void print_log(const char *fmt, ...); +void dsp_debug_init(); +#ifdef HIKEY_XAF_IPC_COMMENT_OUT +void dsp_om_func_proc(char *om_str, unsigned int str_len); +#endif +#endif diff --git a/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/dsp_driver_ipc.h b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/dsp_driver_ipc.h new file mode 100644 index 00000000..2228f32a --- /dev/null +++ b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/dsp_driver_ipc.h @@ -0,0 +1,61 @@ +/******************************************************************************* +* Copyright (C) 2018 Cadence Design Systems, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* "Software"), to use this Software with Cadence processor cores only and +* not with any other processors and platforms, subject to +* the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +******************************************************************************/ + +#ifndef __DSP_DRIVER_IPC_H__ +#define __DSP_DRIVER_IPC_H__ + +#if 0 +#define DSP_IPC_FROM_AP_INT_NO (3) +#define DSP_SYS_IPC_BASE_ADDR_NS (0xe896b000) +#define DSP_AP_TO_DSP_MAILBOX_NO (18) +#define DSP_DSP_TO_AP_MAILBOX_NO (2) +#define IPC_BUSY_RETRY_COUNT (1000) +#define IPC_ACPU_INT_SRC_HIFI_MSG (1) +#define BIT_MASK(n) (1 << (n)) + +#define WORD_REF(address) (* ((unsigned int volatile *) (address))) + +#define SYS_IPC_LOCK(base) WORD_REF(base + 0xA00) +#define SYS_IPC_ICLR(base, box) WORD_REF(base + ((box) << 6) + 0x18) +#define SYS_IPC_DATA(base, box, num) WORD_REF(base + ((box) << 6) + 0x20 + ((num) << 2)) +#define SYS_IPC_CPUIRST(base, core) WORD_REF(base + 0x804 + ((core) << 3)) +#define SYS_IPC_MODE(base, box) WORD_REF(base + ((box) << 6) + 0x10) +#define SYS_IPC_SOURCE(base, box) WORD_REF(base + ((box) << 6)) +#define SYS_IPC_DEST(base, box) WORD_REF(base + ((box) * 64) + 0x04) +#define SYS_IPC_SEND(base, box) WORD_REF(base + ((box) << 6) + 0x1c) +#define SYS_IPC_IMASK(base, box) WORD_REF(base + ((box) << 6) + 0x14) +#define SYS_IPC_DCLR(base, box) WORD_REF(base + ((box) * 64) + 0x08) +#define SYS_IPC_CPUIMST(base, core) WORD_REF(base + 0x800 + ((core) * 8)) +#define SYS_IPC_MODE_ACK (7) +#define SYS_IPC_MODE_IDLE (4) +#define SYS_IPC_MODE_AUTOACK (0) + +#define SYS_IPC_CORE_HIFI (4) +#define SYS_IPC_CORE_A15 (0) +#define SYS_IPC_CORE_LPM3 (3) +#endif +#if 0 +extern void dsp_ipc_init(void); +extern void dsp_ipc_wait(void); +#endif +#endif + diff --git a/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/dsp_driver_mailbox.h b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/dsp_driver_mailbox.h new file mode 100644 index 00000000..5fdcca9a --- /dev/null +++ b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/dsp_driver_mailbox.h @@ -0,0 +1,171 @@ +/******************************************************************************* +* Copyright (C) 2018 Cadence Design Systems, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* "Software"), to use this Software with Cadence processor cores only and +* not with any other processors and platforms, subject to +* the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +******************************************************************************/ + +#ifndef __DSP_DRIVER_MAILBOX_H__ +#define __DSP_DRIVER_MAILBOX_H__ + +#include <stdint.h> + +#define HIKEY_MSG_HEAD_PROTECT_WORD 0xffff1234 +#define HIKEY_MSG_BODY_PROTECT_WORD 0xffff4321 + +#define HIKEY_MSG_ID_AP_DSP_OM_CMD 0xDDCB +#define HIKEY_AUDIO_DSP_AP_OM_CMD 0xDDC9 + +typedef enum HIFI_MSG_ID_ { + + /*DTS command id from ap*/ + ID_AP_AUDIO_SET_DTS_ENABLE_CMD = 0xDD36, + ID_AP_AUDIO_SET_DTS_DEV_CMD = 0xDD38, + ID_AP_AUDIO_SET_DTS_GEQ_CMD = 0xDD39, + ID_AP_AUDIO_SET_DTS_GEQ_ENABLE_CMD = 0xDD3B, + + /* APºÍHIFIµÄ¿ØÖÆÍâÖöú»úHIFI codecœ»»¥ÏûÏ¢ */ + ID_AP_AUDIO_SET_EXCODEC_ENABLE_CMD = 0xDD3D, + + /* Voice Record */ + ID_AP_HIFI_VOICE_RECORD_START_CMD = 0xDD40, + ID_AP_HIFI_VOICE_RECORD_STOP_CMD = 0xDD41, + + /* voicePP MSG_ID */ + ID_AP_VOICEPP_START_REQ = 0xDD42, /* Æô¶¯VOICEPPÍš»° */ + ID_VOICEPP_MSG_START = ID_AP_VOICEPP_START_REQ, + ID_VOICEPP_AP_START_CNF = 0xDD43, + ID_AP_VOICEPP_STOP_REQ = 0xDD44, /* ÖÕÖ¹VOICEPPÍš»° */ + ID_VOICEPP_AP_STOP_CNF = 0xDD45, + ID_VOICEPP_MSG_END = 0xDD4A, + + ID_AP_AUDIO_PLAY_START_REQ = 0xDD51,/* APÆô¶¯Hifi audio player requestÃüÁî */ + ID_AUDIO_AP_PLAY_START_CNF = 0xDD52,/* HifiÆô¶¯audio playerºó»ØžŽAP confirmÃüÁî */ + ID_AP_AUDIO_PLAY_PAUSE_REQ = 0xDD53,/* APÍ£Ö¹Hifi audio player requestÃüÁî */ + ID_AUDIO_AP_PLAY_PAUSE_CNF = 0xDD54,/* HifiÍ£Ö¹audio playerºó»ØžŽAP confirmÃüÁî */ + ID_AUDIO_AP_PLAY_DONE_IND = 0xDD56,/* HifiÍšÖªAP audio playerÒ»¿éÊýŸÝ²¥·ÅÍê±Ï»òÕß²¥·ÅÖжÏindication */ + ID_AP_AUDIO_PLAY_UPDATE_BUF_CMD = 0xDD57,/* APÍšÖªHifiÐÂÊýŸÝ¿éžüÐÂcommand */ + ID_AP_AUDIO_PLAY_QUERY_TIME_REQ = 0xDD59,/* AP²éѯHifi audio player²¥·Åœø¶ÈrequestÃüÁî */ + ID_AP_AUDIO_PLAY_WAKEUPTHREAD_REQ = 0xDD5A, + ID_AUDIO_AP_PLAY_QUERY_TIME_CNF = 0xDD60,/* Hifi»ØžŽAP audio player²¥·Åœø¶ÈconfirmÃüÁî */ + ID_AP_AUDIO_PLAY_QUERY_STATUS_REQ = 0xDD61,/* AP²éѯHifi audio player²¥·Å׎̬requestÃüÁî */ + ID_AUDIO_AP_PLAY_QUERY_STATUS_CNF = 0xDD62,/* Hifi»ØžŽAP audio player²¥·Å׎̬confirmÃüÁî */ + ID_AP_AUDIO_PLAY_SEEK_REQ = 0xDD63,/* AP seek Hifi audio playerµœÄ³Ò»Î»ÖÃrequestÃüÁî */ + ID_AUDIO_AP_PLAY_SEEK_CNF = 0xDD64,/* Hifi»ØžŽAP seekœá¹ûconfirmÃüÁî */ + ID_AP_AUDIO_PLAY_SET_VOL_CMD = 0xDD70,/* APÉèÖÃÒôÁ¿ÃüÁî */ + ID_AP_AUDIO_RECORD_PCM_HOOK_CMD = 0xDD7A,/* AP ÍšÖªHIFI¿ªÊŒ×¥È¡PCMÊýŸÝ */ + ID_AUDIO_AP_UPDATE_PCM_BUFF_CMD = 0xDD7C, + ID_AP_AUDIO_DYN_EFFECT_GET_PARAM = 0xDD7D, + ID_AP_AUDIO_DYN_EFFECT_GET_PARAM_CNF = 0xDD7E, + ID_AP_AUDIO_DYN_EFFECT_TRIGGER = 0xDD7F, + /* enhance msgid between ap and hifi */ + ID_AP_HIFI_ENHANCE_START_REQ = 0xDD81, + ID_HIFI_AP_ENHANCE_START_CNF = 0xDD82, + ID_AP_HIFI_ENHANCE_STOP_REQ = 0xDD83, + ID_HIFI_AP_ENHANCE_STOP_CNF = 0xDD84, + ID_AP_HIFI_ENHANCE_SET_DEVICE_REQ = 0xDD85, + ID_HIFI_AP_ENHANCE_SET_DEVICE_CNF = 0xDD86, + + /* audio enhance msgid between ap and hifi */ + ID_AP_AUDIO_ENHANCE_SET_DEVICE_IND = 0xDD91, + ID_AP_AUDIO_MLIB_SET_PARA_IND = 0xDD92, + ID_AP_AUDIO_CMD_SET_SOURCE_CMD = 0xDD95, + ID_AP_AUDIO_CMD_SET_DEVICE_CMD = 0xDD96, + ID_AP_AUDIO_CMD_SET_MODE_CMD = 0xDD97, + ID_AP_AUDIO_CMD_SET_ANGLE_CMD = 0xDD99, + + /* for 3mic */ + ID_AP_AUDIO_ROUTING_COMPLETE_REQ = 0xDDC0,/*AP ÍšÖªHIFI 3Mic/4Mic ͚·ÒÑœšÁ¢*/ + ID_AUDIO_AP_DP_CLK_EN_IND = 0xDDC1,/* HIFI ÍšÖªAºËŽò¿ª»ò¹Ø±ÕCodec DPʱÖÓ */ + ID_AP_AUDIO_DP_CLK_STATE_IND = 0xDDC2,/* AºËÍšÖªHIFI £¬Codec DPʱÖÓ׎̬( Žò¿ª»ò¹Ø±Õ) */ + ID_AUDIO_AP_OM_DUMP_CMD = 0xDDC3,/* HIFI ÍšÖªAºËdumpÈÕÖŸ */ + ID_AUDIO_AP_FADE_OUT_REQ = 0xDDC4,/* HIFIÍšÖªAP×öµ³öŽŠÀí */ + ID_AP_AUDIO_FADE_OUT_IND = 0xDDC5,/* APÍšÖªHIFIµ³öÍê±Ï */ + + ID_AUDIO_AP_OM_CMD = 0xDDC9, + ID_AP_AUDIO_STR_CMD = 0xDDCB,/* APžøHIFI·¢ËÍÒ»žö×Ö·ûŽ®£¬ŸßÌ庬ÒåhifiÖÐœâÎö */ + ID_AUDIO_AP_VOICE_BSD_PARAM_CMD = 0xDDCC,/* VOICE BSD ²ÎÊýÉϱš */ + + ID_AP_ENABLE_MODEM_LOOP_REQ = 0xDDCD,/* the audio hal notify HIFI to start/stop MODEM LOOP*/ + ID_AP_HIFI_REQUEST_VOICE_PARA_REQ = 0xDF00, /*AP REQUEST VOICE MSG*/ + ID_HIFI_AP_REQUEST_VOICE_PARA_CNF = 0xDF01, /*HIFI REPLAY VOICE MSG*/ + + /* XAF message IDs */ + ID_XAF_AP_TO_DSP = 0xDF10, + ID_XAF_DSP_TO_AP = 0xDF11, +} HIFI_MSG_ID; + +#define HIKEY_AP2DSP_MSG_QUEUE_ADDR HIFI_HIKEY_SHARE_MEM_ADDR + +#define HIKEY_AP2DSP_MSG_QUEUE_SIZE 0x1800 +#define HIKEY_DSP2AP_MSG_QUEUE_ADDR (HIKEY_AP2DSP_MSG_QUEUE_ADDR + HIKEY_AP2DSP_MSG_QUEUE_SIZE) +#define HIKEY_DSP2AP_MSG_QUEUE_SIZE 0x1800 + +#define HIKEY_AP_DSP_MSG_MAX_LEN 100 +///////////////////////////////////////////////////////////////////// +// XAF STRUCTURES // +///////////////////////////////////////////////////////////////////// +#ifdef GJB_CHANGE +/* ...command/response message */ +typedef struct xf_proxy_msg { + /* ...session ID */ + uint32_t id; + + /* ...proxy API command/reponse code */ + uint32_t opcode; + + /* ...length of attached buffer */ + uint32_t length; + + /* ...physical address of message buffer */ + uint64_t address; + uint64_t v_address; + +} __attribute__((__packed__)) xf_proxy_msg_t; + +struct hikey_ap_dsp_msg_head { + unsigned int head_protect_word; + unsigned int msg_num; + unsigned int read_pos; + unsigned int write_pos; +}; + +/*struct hikey_ap_dsp_msg_body { + unsigned short msg_id; + unsigned short msg_len; + char msg_content[0]; +};*/ + +struct hikey_ap_dsp_msg_body { + unsigned short msg_id; + unsigned short msg_len; + union { + char msg_content[0]; + struct xf_proxy_msg xf_dsp_msg; + }; +}; +struct hikey_msg_with_content { + struct hikey_ap_dsp_msg_body msg_info; + char msg_content[HIKEY_AP_DSP_MSG_MAX_LEN]; +}; +void dsp_init_share_mem(char *share_mem_addr, unsigned int share_mem_size); +int dsp_mailbox_read(struct hikey_msg_with_content *hikey_msg); +void dsp_msg_process(struct hikey_msg_with_content *hikey_msg); +#else +#endif +#endif diff --git a/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/dsp_memory_config.h b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/dsp_memory_config.h new file mode 100644 index 00000000..fd5a93d3 --- /dev/null +++ b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/dsp_memory_config.h @@ -0,0 +1,96 @@ +/******************************************************************************* +* Copyright (C) 2018 Cadence Design Systems, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* "Software"), to use this Software with Cadence processor cores only and +* not with any other processors and platforms, subject to +* the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +******************************************************************************/ + +#ifndef __DSP_MEMORY_CONFIG_H__ +#define __DSP_MEMORY_CONFIG_H__ + +/** for chicago only **/ +/**Non Secure 3.5M **/ +/* |0x8B300000|0x8B432000|0x8B532000|0x8B5B1000|0x8B5B2000|0x8B5C5000|0x8B5C6000|0x8B5C7000|0x8B5F9800|~~0x8B609800~~|~~0x8B618800~~|~0x8B618880~|0x8B627880|~0x8B629880~|0x8B62C880~~~| */ +/* |Music data|~~PCM data|~hifi uart|panicstack|icc debug~|flag data~|DDRsechead|~~AP NV ~~|AP&HIFIMB~|codec dma buff|codecdmaconfig|soundtrigger|pcm upload|~hikey share|unsec reserve| */ +/* |~~~~1.2M~~|~~~~1M~~~~|~~508k~~~~|~~~~~4k~~~|~~76k~~~~~|~~~4k~~~~~|~~~4k~~~~~|~~202k~~~~|~~~64k~~~~|~~~~60k~~~~~~~|~~~~128b~~~~~~|~~~~60k~~~~~|~~~8k~~~~~|~~~~~12k~~~~|~~334k-128b~~| */ +/* |0x8B431fff|0x8B531fff|0x8B5B0fff|0x8B5B1fff|0x8B5C4fff|0x8B5C5fff|0x8B5C6fff|0x8B5F97ff|0x8B6097ff|~~0x8B6187FF~~|~~0x8B61887F~~|~0x8B62787F~|0x8B62987F|0x8B62C87F~~|~~0x8B67FFFF~| */ + +/** Secure9.5M **/ +/* |~~~0x89200000~~~|~~~0x89800000~~~|~~~0x89830000~~|~~~0x89864000~~~| */ +/* |~~HIFI RUNNING~~|~OCRAM img bak~~|~~TCM img bak~~|~~~~IMG bak~~~~~| */ +/* |~~~~~~~6M~~~~~~~|~~~~~~192K~~~~~~|~~~~~208k~~~~~~|~~~~~~3.1M ~~~~~| */ +/* |~~~0x897fffff~~~|~~~0x8982ffff~~~|~~~0x89863fff~~|~~~0x89B80000~~~| */ + + +#define HIFI_UNSEC_REGION_SIZE (0x380000) +#define HIFI_MUSIC_DATA_SIZE (0x132000) +#define PCM_PLAY_BUFF_SIZE (0x100000) +#define DRV_DSP_UART_TO_MEM_SIZE (0x7f000) +#define DRV_DSP_UART_TO_MEM_RESERVE_SIZE (0x100) +#define DRV_DSP_STACK_TO_MEM_SIZE (0x1000) +#define HIFI_ICC_DEBUG_SIZE (0x13000) +#define HIFI_FLAG_DATA_SIZE (0x1000) +#define HIFI_SEC_HEAD_SIZE (0x1000) +#define HIFI_AP_NV_DATA_SIZE (0x32800) +#define HIFI_AP_MAILBOX_TOTAL_SIZE (0x10000) +#define CODEC_DSP_OM_DMA_BUFFER_SIZE (0xF000) +#define CODEC_DSP_OM_DMA_CONFIG_SIZE (0x80) +#define CODEC_DSP_SOUNDTRIGGER_TOTAL_SIZE (0xF000) +#define HIFI_PCM_UPLOAD_BUFFER_SIZE (0x2000) +#define HIFI_HIKEY_SHARE_SIZE (0x1800 * 2) +#define HIFI_UNSEC_RESERVE_SIZE (0x53780) + +#define HIFI_UNSEC_BASE_ADDR (0x8B300000) +#define HIFI_MUSIC_DATA_LOCATION (HIFI_UNSEC_BASE_ADDR) +#define PCM_PLAY_BUFF_LOCATION (HIFI_MUSIC_DATA_LOCATION + HIFI_MUSIC_DATA_SIZE) +#define DRV_DSP_UART_TO_MEM (PCM_PLAY_BUFF_LOCATION + PCM_PLAY_BUFF_SIZE) +#define DRV_DSP_STACK_TO_MEM (DRV_DSP_UART_TO_MEM + DRV_DSP_UART_TO_MEM_SIZE) +#define HIFI_ICC_DEBUG_LOCATION (DRV_DSP_STACK_TO_MEM + DRV_DSP_STACK_TO_MEM_SIZE) +#define HIFI_FLAG_DATA_ADDR (HIFI_ICC_DEBUG_LOCATION + HIFI_ICC_DEBUG_SIZE) +#define HIFI_SEC_HEAD_BACKUP (HIFI_FLAG_DATA_ADDR + HIFI_FLAG_DATA_SIZE) +#define HIFI_AP_NV_DATA_ADDR (HIFI_SEC_HEAD_BACKUP + HIFI_SEC_HEAD_SIZE) +#define HIFI_AP_MAILBOX_BASE_ADDR (HIFI_AP_NV_DATA_ADDR + HIFI_AP_NV_DATA_SIZE) +#define CODEC_DSP_OM_DMA_BUFFER_ADDR (HIFI_AP_MAILBOX_BASE_ADDR + HIFI_AP_MAILBOX_TOTAL_SIZE) +#define CODEC_DSP_OM_DMA_CONFIG_ADDR (CODEC_DSP_OM_DMA_BUFFER_ADDR + CODEC_DSP_OM_DMA_BUFFER_SIZE) +#define CODEC_DSP_SOUNDTRIGGER_BASE_ADDR (CODEC_DSP_OM_DMA_CONFIG_ADDR + CODEC_DSP_OM_DMA_CONFIG_SIZE) +#define HIFI_PCM_UPLOAD_BUFFER_ADDR (CODEC_DSP_SOUNDTRIGGER_BASE_ADDR + CODEC_DSP_SOUNDTRIGGER_TOTAL_SIZE) +#define HIFI_HIKEY_SHARE_MEM_ADDR (HIFI_PCM_UPLOAD_BUFFER_ADDR+HIFI_AP_MAILBOX_TOTAL_SIZE) +#define HIFI_UNSEC_RESERVE_ADDR (HIFI_HIKEY_SHARE_MEM_ADDR + HIFI_HIKEY_SHARE_SIZE) + +#define DRV_DSP_PANIC_MARK (HIFI_FLAG_DATA_ADDR) +#define DRV_DSP_UART_LOG_LEVEL (DRV_DSP_PANIC_MARK + 4) +#define DRV_DSP_UART_TO_MEM_CUR_ADDR (DRV_DSP_UART_LOG_LEVEL + 4) + +#define HIFI_SEC_REGION_SIZE (0x980000) +#define HIFI_IMAGE_OCRAMBAK_SIZE (0x30000) +#define HIFI_RUN_SIZE (0x600000) +#define HIFI_IMAGE_TCMBAK_SIZE (0x34000) +#define HIFI_IMAGE_SIZE (0x31C000) +#define HIFI_RUN_ITCM_BASE (0xe8080000) +#define HIFI_RUN_ITCM_SIZE (0x9000) +#define HIFI_RUN_DTCM_BASE (0xe8058000) +#define HIFI_RUN_DTCM_SIZE (0x28000) + + +#define HIFI_SEC_REGION_ADDR (0x89200000) /* chciago */ +#define HIFI_RUN_LOCATION (HIFI_SEC_REGION_ADDR) +#define HIFI_IMAGE_OCRAMBAK_LOCATION (HIFI_RUN_LOCATION + HIFI_RUN_SIZE) +#define HIFI_IMAGE_TCMBAK_LOCATION (HIFI_IMAGE_OCRAMBAK_LOCATION + HIFI_IMAGE_OCRAMBAK_SIZE) +#define HIFI_IMAGE_LOCATION (HIFI_IMAGE_TCMBAK_LOCATION + HIFI_IMAGE_TCMBAK_SIZE) + +#endif diff --git a/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/dsp_pcm_gain.h b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/dsp_pcm_gain.h new file mode 100644 index 00000000..24f94ec1 --- /dev/null +++ b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/dsp_pcm_gain.h @@ -0,0 +1,37 @@ +/******************************************************************************* +* Copyright (C) 2018 Cadence Design Systems, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* "Software"), to use this Software with Cadence processor cores only and +* not with any other processors and platforms, subject to +* the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +******************************************************************************/ + +#ifndef DSP_PCM_GAIN_H +#define __DSP_PCM_GAIN_H__ +#include "dsp_memory_config.h" +#define FRAME_SIZE 480 // 10 ms @ 48 KHz. +#define HOLD_BUF_SIZE 228404 +#define MSG_RECV 1 // Msg received +#define MSG_PROC 2 // Msg processed. +#define MSG_COMP 8 +#define MSG_INCOMP 9 +#define MUSIC_DATA_MEM_READ_ADDR HIFI_MUSIC_DATA_LOCATION // Address of the Music data memory.. !!! change this if necessary.. +#define PCM_DATA_MEM_WRITE_ADDR PCM_PLAY_BUFF_LOCATION // Address of some random element in PCM data memory.. !!! change this if necessary.. +int ReadData( char *pDst, int Size ); +int WriteData( char *pSrc, int Size ); +int processAudio( int *pDst, int *pSrc, int Size ); +#endif diff --git a/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/reset.h b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/reset.h new file mode 100644 index 00000000..5a77a97d --- /dev/null +++ b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/reset.h @@ -0,0 +1,62 @@ +/******************************************************************************* +* Copyright (C) 2018 Cadence Design Systems, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* "Software"), to use this Software with Cadence processor cores only and +* not with any other processors and platforms, subject to +* the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +******************************************************************************/ + + +#include <xtensa/coreasm.h> +#include <xtensa/simcall.h> +#define PIF_CACHED 1 +#define PIF_BYPASS 2 +#define PIF_CACHED_WBA 4 +#define PIF_CACHED_WBNA 5 +#define PIF_INVALID 15 + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + + + +/*set memory mapping attribute*/ +.macro set_access_mode am + rdtlb1 a4, a3 + ritlb1 a5, a3 + srli a4, a4, 4 + slli a4, a4, 4 + srli a5, a5, 4 + slli a5, a5, 4 + addi a4, a4, \am + addi a5, a5, \am + wdtlb a4, a3 + witlb a5, a3 +.endm + + + + +#ifdef __cplusplus + #if __cplusplus + } + #endif +#endif + diff --git a/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/xf-board.h b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/xf-board.h new file mode 100644 index 00000000..e42ab1b9 --- /dev/null +++ b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/board-hikey/xf-board.h @@ -0,0 +1,180 @@ +/******************************************************************************* +* Copyright (C) 2018 Cadence Design Systems, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* "Software"), to use this Software with Cadence processor cores only and +* not with any other processors and platforms, subject to +* the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +******************************************************************************/ + +/******************************************************************************* + * board-hikey/xf-board.h + * + * HiKey960-specific definitions + * + *******************************************************************************/ + +#ifndef __XF_H +#error "xf-board.h mustn't be included directly" +#endif + +/******************************************************************************* + * Global constants definitions + ******************************************************************************/ + +/* ...shared memory interface address */ +#define XF_CFG_SHMEM_ADDRESS(core) HIFI_HIKEY_SHARE_MEM_ADDR + +/* ...tracing buffer configuration (place at the end of memory) */ +#define XF_CFG_TRACE_START(core) 0x78000000 +#define XF_CFG_TRACE_END(core) 0x7FFFFFFF +#if 1 +#define DSP_IPC_FROM_AP_INT_NO (3) +#define DSP_SYS_IPC_BASE_ADDR_NS (0xe896b000) +#define DSP_AP_TO_DSP_MAILBOX_NO (18) +#define DSP_DSP_TO_AP_MAILBOX_NO (2) +#define IPC_BUSY_RETRY_COUNT (1000) +#define IPC_ACPU_INT_SRC_HIFI_MSG (1) +#define BIT_MASK(n) (1 << (n)) + +#define WORD_REF(address) (* ((unsigned int volatile *) (address))) + +#define SYS_IPC_LOCK(base) WORD_REF(base + 0xA00) +#define SYS_IPC_ICLR(base, box) WORD_REF(base + ((box) << 6) + 0x18) +#define SYS_IPC_DATA(base, box, num) WORD_REF(base + ((box) << 6) + 0x20 + ((num) << 2)) +#define SYS_IPC_CPUIRST(base, core) WORD_REF(base + 0x804 + ((core) << 3)) +#define SYS_IPC_MODE(base, box) WORD_REF(base + ((box) << 6) + 0x10) +#define SYS_IPC_SOURCE(base, box) WORD_REF(base + ((box) << 6)) +#define SYS_IPC_DEST(base, box) WORD_REF(base + ((box) * 64) + 0x04) +#define SYS_IPC_SEND(base, box) WORD_REF(base + ((box) << 6) + 0x1c) +#define SYS_IPC_IMASK(base, box) WORD_REF(base + ((box) << 6) + 0x14) +#define SYS_IPC_DCLR(base, box) WORD_REF(base + ((box) * 64) + 0x08) +#define SYS_IPC_CPUIMST(base, core) WORD_REF(base + 0x800 + ((core) * 8)) +#define SYS_IPC_MODE_ACK (7) +#define SYS_IPC_MODE_IDLE (4) +#define SYS_IPC_MODE_AUTOACK (0) + +#define SYS_IPC_CORE_HIFI (4) +#define SYS_IPC_CORE_A15 (0) +#define SYS_IPC_CORE_LPM3 (3) +#endif +/* ...inter-processor interrupt number (SEL:10 - LEVEL:15) */ +#define XF_PROXY_IPI_NUM(core) 15 + +/******************************************************************************* + * External functions + ******************************************************************************/ + +/* ...gdb stub initialization */ +extern void init_gdbstub(void); + +/* ...emit breakpoint */ +extern void breakpoint(void); +#if 0// def HIKEY_XAF_IPC_COMMENT_OUT +/******************************************************************************* + * Public proxy API + ******************************************************************************/ + +/* ...notify remote side about status change */ +#define XF_PROXY_NOTIFY_PEER(core) h2_wake_core() + +/* ...clear pending interrupt mask */ +#define XF_PROXY_SYNC_PEER(core) h2_local_ack() + +/******************************************************************************* + * Auxiliary helper functions + ******************************************************************************/ + +/* ...generate inter-processor interrupt for remote core */ +static inline void h2_wake_core(void) +{ + /* ...we have single INPUT-interrupt pin */ + *(volatile unsigned int *)0xec800044 = 1; +} + +/* ...acknowledge pending IPI interrupt */ +static inline void h2_local_ack(void) +{ + /* ...asserted interrupt cannot be cleared */ +} + +/******************************************************************************* + * Board specific init + ******************************************************************************/ + +static inline void xf_board_init(void) +{ + /* ...initialize GDB debugging interface */ + init_gdbstub(); + + /* ...indicate the board has started */ + *(volatile unsigned int *)0xec800100 = 1; +} +#else +//#define XF_PROXY_NOTIFY_PEER(core) dsp_ipc_send_irq_to_ap() +#define XF_PROXY_NOTIFY_PEER(core) h2_wake_core() +/* ...clear pending interrupt mask */ +#define XF_PROXY_SYNC_PEER(core) h2_local_ack() + +/* ...generate inter-processor interrupt for remote core */ +static inline void h2_wake_core(void) +{ + unsigned int mode = 0; + unsigned int mode_1 = 0; + + // mode = SYS_IPC_MODE(DSP_SYS_IPC_BASE_ADDR_NS, DSP_DSP_TO_AP_MAILBOX_NO); + //mode = (* ((unsigned int volatile *) (0xe896b000 + ((2) << 6) + 0x10))); + mode = * (volatile unsigned int*) 0xe896b090; + + //if (mode & BIT_MASK(SYS_IPC_MODE_IDLE)) { + //if (mode & (1 << (4))) { + if (mode & 0x10) { + mode_1=0; + } else { + return; + } + + //SYS_IPC_SOURCE(DSP_SYS_IPC_BASE_ADDR_NS, DSP_DSP_TO_AP_MAILBOX_NO) = BIT_MASK(SYS_IPC_CORE_HIFI); + //(* ((unsigned int volatile *) (0xe896b000 + ((2) << 6))))= (1 << (4)); + * (volatile unsigned int *) 0xe896b080 = (0x10); + + //SYS_IPC_IMASK(DSP_SYS_IPC_BASE_ADDR_NS, DSP_DSP_TO_AP_MAILBOX_NO) = ~((unsigned int)(BIT_MASK(SYS_IPC_CORE_HIFI)|BIT_MASK(SYS_IPC_CORE_A15))); + //(* ((unsigned int volatile *) (0xe896b000 + ((2) << 6) + 0x14))) = ~ ((unsigned int)((1 << (4))|(1 << (0)))); + * (volatile unsigned int *)0xe896b094 = ~ ((unsigned int)(0x11)); + + //SYS_IPC_DATA(DSP_SYS_IPC_BASE_ADDR_NS, DSP_DSP_TO_AP_MAILBOX_NO, 0) = IPC_ACPU_INT_SRC_HIFI_MSG; + //(* ((unsigned int volatile *) (0xe896b000 + ((2) << 6) + 0x20 + ((0) << 2)))) = 1; + * (volatile unsigned int *) 0xe896b0A0 = 1; + + //SYS_IPC_MODE(DSP_SYS_IPC_BASE_ADDR_NS, DSP_DSP_TO_AP_MAILBOX_NO) = BIT_MASK(SYS_IPC_MODE_AUTOACK); + //(* ((unsigned int volatile *) (0xe896b000 + ((2) << 6) + 0x10))) = (1 << (0)); + * (volatile unsigned int *) 0xe896b090 = 1; + + //SYS_IPC_SEND(DSP_SYS_IPC_BASE_ADDR_NS, DSP_DSP_TO_AP_MAILBOX_NO) = BIT_MASK(SYS_IPC_CORE_HIFI); + //(* ((unsigned int volatile *) (0xe896b000 + ((2) << 6) + 0x1c))) = (1 << (4)); + * (volatile unsigned int *) 0xe896b09C = 0x10; + + return; +} + +/* ...acknowledge pending IPI interrupt */ +static inline void h2_local_ack(void) +{ + /* ...asserted interrupt cannot be cleared */ +} + +#endif + diff --git a/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-config.h b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-config.h new file mode 100644 index 00000000..4775e807 --- /dev/null +++ b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-config.h @@ -0,0 +1,63 @@ +/******************************************************************************* +* Copyright (C) 2018 Cadence Design Systems, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* "Software"), to use this Software with Cadence processor cores only and +* not with any other processors and platforms, subject to +* the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +******************************************************************************/ + +/******************************************************************************* + * xf-config.h + * + * Xtensa target configuration parameters + * + *******************************************************************************/ + +/* ...number of DSP cores */ +#define XF_CFG_CORES_NUM 1 + +/* ...size of the internal message pool (make it equal to at least ring-buffer) */ +#define XF_CFG_MESSAGE_POOL_SIZE 256 + +/* ...local IPC is coherent (say) */ +#define XF_LOCAL_IPC_NON_COHERENT 0 + +/* ...remote IPC is non coherent (say) */ +#define XF_REMOTE_IPC_NON_COHERENT 1 + +/* ...size of the local memory pool (in bytes) */ +#define XF_CFG_LOCAL_POOL_SIZE (1024 << 10) + +/* ...size of the shared memory pool (in bytes) */ +#if 1//def XAF_ENABLE_NON_HIKEY +#define XF_CFG_REMOTE_IPC_POOL_SIZE (256 << 10) +#else +#define XF_CFG_REMOTE_IPC_POOL_SIZE (HIFI_MUSIC_DATA_SIZE) +#endif + +/* ...size of the local memory pool (in bytes) */ +#define XF_CFG_LOCAL_IPC_POOL_SIZE (1024 << 10) +#ifdef XAF_ENABLE_NON_HIKEY +/* ...maximal size of scratch memory is 80 KB */ +#define XF_CFG_CODEC_SCRATCHMEM_SIZE (80 << 10) +#else +/* ...maximal size of scratch memory is 56 KB */ +#define XF_CFG_CODEC_SCRATCHMEM_SIZE (56 << 10) +#endif + +/* ...scratch memory is 8-bytes aligned */ +#define XF_CFG_CODEC_SCRATCHMEM_ALIGN 8 diff --git a/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-hal.h b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-hal.h new file mode 100644 index 00000000..82cf3c11 --- /dev/null +++ b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-hal.h @@ -0,0 +1,151 @@ +/******************************************************************************* +* Copyright (C) 2018 Cadence Design Systems, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* "Software"), to use this Software with Cadence processor cores only and +* not with any other processors and platforms, subject to +* the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +******************************************************************************/ + +/******************************************************************************* + * xf-hal.h + * + * Platform-specific HAL definitions + * + *******************************************************************************/ + +#ifndef __XF_H +#error "xf-hal.h mustn't be included directly" +#endif + +/******************************************************************************* + * Includes + ******************************************************************************/ + +/* ...primitive types */ +#include "xf-types.h" + +/* ...XTOS runtime */ +#include <xtensa/xtruntime.h> + +/******************************************************************************* + * Auxilliary macros definitions + ******************************************************************************/ + +/* ...use system-specific cache-line size */ +#define XF_PROXY_ALIGNMENT XCHAL_DCACHE_LINESIZE + +/* ...properly aligned shared memory structure */ +#define __xf_shmem__ __attribute__((__aligned__(XF_PROXY_ALIGNMENT))) + +/******************************************************************************* + * Interrupt control + ******************************************************************************/ + +/* ...disable interrupts on given core */ +static inline u32 xf_isr_disable(u32 core) +{ + /* ...no actual dependency on the core identifier */ + return XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); +} + +/* ...enable interrupts on given core */ +static inline void xf_isr_restore(u32 core, u32 status) +{ + /* ...no actual dependency on the core identifier */ + XTOS_RESTORE_INTLEVEL(status); +} + +/******************************************************************************* + * Auxiliary system-specific functions + ******************************************************************************/ + +#if XF_CFG_CORES_NUM > 1 +/* ...current core identifier (from HW) */ +static inline u32 xf_core_id(void) +{ + /* ...retrieve core identifier from HAL */ + return (u32) xthal_get_prid(); +} +#else +#define xf_core_id() 0 +#endif + +/******************************************************************************* + * Atomic operations (atomicity is assured on local core only) + ******************************************************************************/ + +static inline int xf_atomic_test_and_set(volatile u32 *bitmap, u32 mask) +{ + u32 status; + u32 v; + + /* ...atomicity is assured by interrupts masking */ + status = XTOS_DISABLE_ALL_INTERRUPTS; + v = *bitmap, *bitmap = v | mask; + XTOS_RESTORE_INTLEVEL(status); + + return !(v & mask); +} + +static inline int xf_atomic_test_and_clear(volatile u32 *bitmap, u32 mask) +{ + u32 status; + u32 v; + + /* ...atomicity is assured by interrupts masking */ + status = XTOS_DISABLE_ALL_INTERRUPTS; + v = *bitmap, *bitmap = v & ~mask; + XTOS_RESTORE_INTLEVEL(status); + + return (v & mask); +} + +static inline u32 xf_atomic_set(volatile u32 *bitmap, u32 mask) +{ + u32 status; + u32 v; + + /* ...atomicity is assured by interrupts masking */ + status = XTOS_DISABLE_ALL_INTERRUPTS; + v = *bitmap, *bitmap = (v |= mask); + XTOS_RESTORE_INTLEVEL(status); + + return v; +} + +static inline u32 xf_atomic_clear(volatile u32 *bitmap, u32 mask) +{ + u32 status; + u32 v; + + /* ...atomicity is assured by interrupts masking */ + status = XTOS_DISABLE_ALL_INTERRUPTS; + v = *bitmap, *bitmap = (v &= ~mask); + XTOS_RESTORE_INTLEVEL(status); + + return v; +} + +/******************************************************************************* + * Abortion macro (debugger should be configured) + ******************************************************************************/ + +/* ...breakpoint function */ +extern void breakpoint(void); + +/* ...abort execution (enter into debugger) */ +#define __xf_abort() breakpoint() diff --git a/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-ipc.h b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-ipc.h new file mode 100644 index 00000000..3ce5bd66 --- /dev/null +++ b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-ipc.h @@ -0,0 +1,345 @@ +/******************************************************************************* +* Copyright (C) 2018 Cadence Design Systems, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* "Software"), to use this Software with Cadence processor cores only and +* not with any other processors and platforms, subject to +* the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +******************************************************************************/ + +/******************************************************************************* + * xf-ipc.h + * + * Xtensa IPC mechanism + * + *******************************************************************************/ + +#ifndef __XF_H +#error "xf-ipc.h mustn't be included directly" +#endif + +/******************************************************************************* + * Includes + ******************************************************************************/ + +/* ...system-specific shared memory configuration */ +#include "xf-shmem.h" +#ifndef XAF_ENABLE_NON_HIKEY +#include <xtensa/xtruntime.h> +extern volatile int waitstate; +#endif + +#ifdef XAF_ENABLE_NON_HIKEY +/******************************************************************************* + * Macros definitions (should better go to some other header) + ******************************************************************************/ + +/* + * Execute WAITI 0 (enabling interrupts) only if *(ptr) is zero. + * The decision to execute WAITI is done atomically by disabling + * interrupts at level 'level' (level must be a constant) + * before checking the pointer. Interrupts are always re-enabled + * on exit from this macro. + */ +#define _WAITI_ON_PTR(ptr, level) \ +do { \ + int __tmp; \ + __asm__ (" rsil %0, " #level " \n" \ + " l32i %0, %1, 0 \n" \ + " bnez %0, 1f \n" \ + " waiti 0 \n" \ + "1:rsil %0, 0 \n" \ + : "=a" (__tmp) : "a" (ptr) : "memory"); \ +} while(0) + +/* ...enable gdbstub */ +//#define XF_CFG_USE_GDBSTUB 0 + +#ifndef XF_CFG_USE_GDBSTUB +/* ...maybe "level" should be hidden here - we always magically set 15 */ +#define WAITI_ON_PTR(ptr, level) _WAITI_ON_PTR(ptr, level) +#else +/* ...if debugger is enabled, do polling instead of waiting */ +static inline void WAITI_ON_PTR(volatile u32 *ptr, u32 level) +{ + extern void poll_debug_ring(void); + + while (*ptr == 0) + { + /* ...should be called with interrupts disabled - tbd */ + poll_debug_ring(); + } +} +#endif + +/******************************************************************************* + * Remote IPI interrupt mode + ******************************************************************************/ + +/* ...enable/disable IPI interrupt */ +static inline void xf_ipi_enable(u32 core, int on) +{ + if (on) + _xtos_ints_on(1 << XF_PROXY_IPI_NUM(core)); + else + _xtos_ints_off(1 << XF_PROXY_IPI_NUM(core)); +} + +/* ...wait in low-power mode for interrupt arrival if "ptr" is 0 */ +static inline void xf_ipi_wait(u32 core) +{ + xf_core_ro_data_t *ro = XF_CORE_RO_DATA(core); + + /* ...enable IPI interrupt before sleeping */ + xf_ipi_enable(core, 1); + + /* ...wait in low-power mode, atomically checking *ipc != 0 */ + WAITI_ON_PTR(&ro->ipc.wait, 15); + + /* ...force disabling of IPI interrupts */ + xf_ipi_enable(core, 0); + + /* ...reset waiting object upon leaving */ + ro->ipc.wait = 0; +} +#else +#define _WAITI_ON_PTR(ptr, level) \ + do { \ + int __tmp; \ + __asm__ (" rsil %0, " #level " \n" \ + " l32i %0, %1, 0 \n" \ + " bnez %0, 1f \n" \ + " waiti 0 \n" \ + "1:rsil %0, 0 \n" \ + : "=a" (__tmp) : "a" (ptr) : "memory"); \ + } while(0) + +#define WAITI_ON_PTR(ptr, level) _WAITI_ON_PTR(ptr, level) +static inline void xf_ipi_wait(u32 core) +{ +#if 0 + // VOS_EnableInterrupt(DSP_IPC_FROM_AP_INT_NO); + _xtos_ints_on(1 << DSP_IPC_FROM_AP_INT_NO); + while(1) + { + if(waitstate ==1) + { + // VOS_DisableInterrupt(DSP_IPC_FROM_AP_INT_NO); + _xtos_ints_off(1 << DSP_IPC_FROM_AP_INT_NO); + waitstate = 0; + break; + } + } +#else + + _xtos_ints_on(1 << DSP_IPC_FROM_AP_INT_NO); + /* ...wait in low-power mode, atomically checking *ipc != 0 */ + WAITI_ON_PTR(&waitstate, 15); + + /* ...force disabling of IPI interrupts */ + + _xtos_ints_off(1 << DSP_IPC_FROM_AP_INT_NO); + /* ...reset waiting object upon leaving */ + waitstate = 0; + +#endif +} +#endif +#ifdef XAF_ENABLE_NON_HIKEY +/* ...complete IPI waiting (may be called from any context on local core) */ +static inline void xf_ipi_resume(u32 core) +{ + xf_core_ro_data_t *ro = XF_CORE_RO_DATA(core); + + /* ...single instruction is written atomically; no need to mask interrupts */ + ro->ipc.wait = 1; +} +#else +/* ...complete IPI waiting (may be called from any context on local core) */ +static inline void xf_ipi_resume(u32 core) +{ + unsigned int ipc_int_state = 0; + unsigned int ipc_data = 0; + + _xtos_ints_off(1 << DSP_IPC_FROM_AP_INT_NO); + + //process message + ipc_int_state = SYS_IPC_CPUIRST(DSP_SYS_IPC_BASE_ADDR_NS, SYS_IPC_CORE_HIFI); + + if (ipc_int_state & BIT_MASK(DSP_AP_TO_DSP_MAILBOX_NO)) { //mailbox-18 + SYS_IPC_ICLR(DSP_SYS_IPC_BASE_ADDR_NS, DSP_AP_TO_DSP_MAILBOX_NO) = BIT_MASK(SYS_IPC_CORE_HIFI); + waitstate = 1; + } + + //_xtos_ints_on(1 << DSP_IPC_FROM_AP_INT_NO); + + return; +} +#endif +#if 0//ndef HIKEY_XAF_IPC_COMMENT_OUT +/* ...notify remote side about status change */ +//#define XF_PROXY_NOTIFY_PEER(core) dsp_ipc_send_irq_to_ap() + +static inline void dsp_ipc_send_irq_to_ap(void) +{ + unsigned int mode = 0; + unsigned int mode_1 = 0; + + mode = SYS_IPC_MODE(DSP_SYS_IPC_BASE_ADDR_NS, DSP_DSP_TO_AP_MAILBOX_NO); + + if (mode & BIT_MASK(SYS_IPC_MODE_IDLE)) { + mode_1=0; + } else { + return; + } + + + SYS_IPC_SOURCE(DSP_SYS_IPC_BASE_ADDR_NS, DSP_DSP_TO_AP_MAILBOX_NO) = BIT_MASK(SYS_IPC_CORE_HIFI); + SYS_IPC_IMASK(DSP_SYS_IPC_BASE_ADDR_NS, DSP_DSP_TO_AP_MAILBOX_NO) = ~((unsigned int)(BIT_MASK(SYS_IPC_CORE_HIFI)|BIT_MASK(SYS_IPC_CORE_A15))); + SYS_IPC_DATA(DSP_SYS_IPC_BASE_ADDR_NS, DSP_DSP_TO_AP_MAILBOX_NO, 0) = IPC_ACPU_INT_SRC_HIFI_MSG; + SYS_IPC_MODE(DSP_SYS_IPC_BASE_ADDR_NS, DSP_DSP_TO_AP_MAILBOX_NO) = BIT_MASK(SYS_IPC_MODE_AUTOACK); + SYS_IPC_SEND(DSP_SYS_IPC_BASE_ADDR_NS, DSP_DSP_TO_AP_MAILBOX_NO) = BIT_MASK(SYS_IPC_CORE_HIFI); + + return; +} +#endif +/* ...assert IPI interrupt on remote core - board-specific */ +static inline void xf_ipi_assert(u32 core) +{ + XF_PROXY_NOTIFY_PEER(core); +} + +#ifdef XAF_ENABLE_NON_HIKEY +/* ...initialize IPI subsystem */ +static inline int xf_ipi_init(u32 core) +{ + xf_core_ro_data_t *ro = XF_CORE_RO_DATA(core); + extern void (* const xf_ipi_handlers[])(void); + + /* ...reset IPC data - no interrupt yet */ + ro->ipc.wait = 0; + + /* ...install interrupt handler */ + _xtos_set_interrupt_handler(XF_PROXY_IPI_NUM(core), xf_ipi_handlers[core]); + + return 0; +} +#else +/* ...initialize IPI subsystem */ +static inline int xf_ipi_init(u32 core) +{ + + waitstate =0; + + dsp_debug_init(); + //dsp_init_share_mem(HIKEY_AP2DSP_MSG_QUEUE_ADDR,HIKEY_DSP2AP_MSG_QUEUE_SIZE); + /* unlock reg */ + SYS_IPC_LOCK(DSP_SYS_IPC_BASE_ADDR_NS) = 0x1ACCE551; + //VOS_ConnectInterrupt(DSP_IPC_FROM_AP_INT_NO, _ap_to_dsp_ipc_irq_proc); + VOS_ConnectInterrupt(DSP_IPC_FROM_AP_INT_NO, xf_ipi_resume); + +// VOS_EnableInterrupt(DSP_IPC_FROM_AP_INT_NO); + + return; +} +#endif + +/******************************************************************************* + * Shared memory operations + ******************************************************************************/ + +/* ...NULL-address specification */ +#define XF_PROXY_NULL (~0U) + +/* ...invalid proxy address */ +#define XF_PROXY_BADADDR XF_CFG_REMOTE_IPC_POOL_SIZE +/* ...translate buffer address to shared proxy address */ +static inline u32 xf_ipc_b2a(u32 core, void *b) +{ + xf_shmem_data_t *shmem = XF_CORE_DATA(core)->shmem; + void *start = shmem->buffer; + + if (b == NULL) + return XF_PROXY_NULL; + else if ((s32)(b - start) < XF_CFG_REMOTE_IPC_POOL_SIZE) + return (u32)(b - start); + else + return XF_PROXY_BADADDR; +} +/* ...translate shared proxy address to local pointer */ +static inline void * xf_ipc_a2b(u32 core, u32 address) +{ + xf_shmem_data_t *shmem = XF_CORE_DATA(core)->shmem; + void *start = shmem->buffer; + + if (address < XF_CFG_REMOTE_IPC_POOL_SIZE) + return start + address; + else if (address == XF_PROXY_NULL) + return NULL; + else + return (void *)-1; +} + +/* ...component association with remote IPC client */ +static inline void xf_ipc_component_addref(u32 session) +{ +} + +/* ...delete record about component association with remote IPC client */ +static inline void xf_ipc_component_rmref(u32 id) +{ +} + +/* ...system-specific IPC layer initialization */ +extern int xf_ipc_init(u32 core); + +/******************************************************************************* + * Mutex definitions + ******************************************************************************/ + +/* ...export shared memory access macros */ +#define MUTEX_SHARED_READ(core) \ + ({ xf_core_ro_data_t *__ro = XF_CORE_RO_DATA(core); __ro->lock[0]; }) + +#define MUTEX_SHARED_WRITE(core, val) \ + ({ xf_core_ro_data_t *__ro = XF_CORE_RO_DATA(core); __ro->lock[0] = (val); }) + +/* ...include library header */ +#include "lib/mutex.h" + +#if XF_CFG_CORES_NUM > 1 +/* ...rename API functions */ +static inline void xf_mutex_lock(u32 core) +{ + mutex_lock(core); +} + +static inline void xf_mutex_unlock(u32 core) +{ + mutex_unlock(core); +} + +#else +/* ...for single-core setting no locking is actually needed */ +static inline void xf_mutex_lock(u32 core) +{ +} + +static inline void xf_mutex_unlock(u32 core) +{ +} + +#endif /* XF_CFG_CORES_NUM > 1 */ diff --git a/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-mem.h b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-mem.h new file mode 100644 index 00000000..dc277871 --- /dev/null +++ b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-mem.h @@ -0,0 +1,180 @@ +/******************************************************************************* +* Copyright (C) 2018 Cadence Design Systems, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* "Software"), to use this Software with Cadence processor cores only and +* not with any other processors and platforms, subject to +* the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +******************************************************************************/ + +/******************************************************************************* + * xf-mem.h + * + * System-specific memory allocator + * + *******************************************************************************/ + +#ifndef __XF_H +#error "xf-mem.h mustn't be included directly" +#endif + +/******************************************************************************* + * System specific memory pools + ******************************************************************************/ + +#if XF_CFG_CORES_NUM > 1 +/* ...shared memory pool for communication within DSP-cluster */ +extern xf_mm_pool_t xf_dsp_shmem_pool; +#endif + +/******************************************************************************* + * Platform-specific SHMEM allocation registering functions + ******************************************************************************/ + +/* ...register shmem allocation address */ +static inline void xf_shmem_alloc_addref(u32 core, xf_message_t *m) +{ +} + +/* ...unregister shmem allocation address */ +static inline void xf_shmem_alloc_rmref(u32 core, xf_message_t *m) +{ +} + +/******************************************************************************* + * API functions + ******************************************************************************/ + +/* ...allocate aligned memory on particular core specifying if it is shared */ +static inline void * xf_mem_alloc(u32 size, u32 align, u32 core, u32 shared) +{ +#if XF_CFG_CORES_NUM > 1 + if (shared) + { + /* ...if memory is shared, core is dropped */ + return xf_mm_alloc(&xf_dsp_shmem_pool, size); + } +#endif + + /* ...select local memory pool basing on core specification */ + return xf_mm_alloc(&XF_CORE_DATA(core)->local_pool, size); +} +#ifdef XAF_ENABLE_NON_HIKEY +/* ...redefine macro to add bugchecks */ +#define xf_mem_alloc(size, align, core, shared) \ +({ \ + void *__data; \ + /* ...size must be properly aligned */ \ + BUG(!XF_MM_ALIGNED(size), _x("Bad size: %u"), size); \ + __data = (xf_mem_alloc)(size, align, core, shared); \ + TRACE(1, _b("alloc-%u: %p[%u] (shared=%u)"), core, __data, size, shared); \ + __data; \ +}) +#endif +/* ...release allocated memory */ +static inline void xf_mem_free(void *p, u32 size, u32 core, u32 shared) +{ +#if XF_CFG_CORES_NUM > 1 + if (shared) + { + /* ...if memory is shared, core is dropped */ + xf_mm_free(&xf_dsp_shmem_pool, p, size); + return; + } +#endif + + /* ...select proper pool basing on core specification */ + xf_mm_free(&XF_CORE_DATA(core)->local_pool, p, size); +} +#ifdef XAF_ENABLE_NON_HIKEY +/* ...redefine macro to add bugchecks */ +#define xf_mem_free(p, size, core, shared) \ +({ \ + void *__data = (p); \ + /* ...size must be properly aligned */ \ + BUG(!XF_MM_ALIGNED(size), _x("Bad size: %u"), size); \ + TRACE(1, _b("free-%u: %p[%u] (shared=%u)"), core, __data, size, shared); \ + (xf_mem_free)(__data, size, core, shared); \ +}) +#endif +/* ...allocate AP-DSP shared memory */ +static inline int xf_shmem_alloc(u32 core, xf_message_t *m) +{ + xf_mm_pool_t *pool = &XF_CORE_DATA(core)->shared_pool; + + /* ...length is always cache-line aligned */ + if ((m->buffer = xf_mm_alloc(pool, XF_ALIGNED(m->length))) != NULL) + { + /* ...register allocation address */ + xf_shmem_alloc_addref(core, m); + + return 0; + } + else + { + return -ENOMEM; + } +} + +/* ...free AP-DSP shared memory */ +static inline void xf_shmem_free(u32 core, xf_message_t *m) +{ + xf_mm_pool_t *pool = &XF_CORE_DATA(core)->shared_pool; + + /* ...length is always cache-line aligned */ + xf_mm_free(pool, m->buffer, XF_ALIGNED(m->length)); + + /* ...unregister allocation address */ + xf_shmem_alloc_rmref(core, m); +} + +/******************************************************************************* + * Scratch memory management + ******************************************************************************/ + +static inline void * xf_scratch_mem_init(u32 core) +{ + /* ...allocate scratch memory from local DSP memory */ + return xf_mem_alloc(XF_CFG_CODEC_SCRATCHMEM_SIZE, XF_CFG_CODEC_SCRATCHMEM_ALIGN, core, 0); +} + +/******************************************************************************* + * Helpers - hmm; they are platform-independent - tbd + ******************************************************************************/ + +/* ...allocate local buffer */ +static inline int xf_mm_alloc_buffer(u32 size, u32 align, u32 core, xf_mm_buffer_t *b) +{ + /* ...allocate memory from proper local pool */ + if ((size = XF_MM(size)) != 0) + XF_CHK_ERR(b->addr = xf_mem_alloc(size, align, core, 0), -ENOMEM); + else + b->addr = NULL; + + /* ...save address */ + b->size = size; + + return 0; +} + +/* ...free local buffer */ +static inline void xf_mm_free_buffer(xf_mm_buffer_t *b, u32 core) +{ + if (b->addr) + { + xf_mem_free(b->addr, b->size, core, 0); + } +} diff --git a/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-runtime.h b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-runtime.h new file mode 100644 index 00000000..ab328ccf --- /dev/null +++ b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-runtime.h @@ -0,0 +1,81 @@ +/******************************************************************************* +* Copyright (C) 2018 Cadence Design Systems, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* "Software"), to use this Software with Cadence processor cores only and +* not with any other processors and platforms, subject to +* the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +******************************************************************************/ + +/******************************************************************************* + * xf-runtime.h + * + * Platform-specific runtime data definitions + * + *******************************************************************************/ + +#ifndef __XF_H +#error "xf-runtime.h mustn't be included directly" +#endif + +/******************************************************************************* + * Includes + ******************************************************************************/ + +/* ...platform HAL layer */ +#include "xf-hal.h" + +/******************************************************************************* + * Mutex (opaque) data definition + ******************************************************************************/ + +typedef volatile u32 xf_mutex_t[XF_CFG_CORES_NUM > 1 ? 1 : 0]; + +/******************************************************************************* + * Local/remote/ISR IPC (opaque) data + ******************************************************************************/ + +typedef struct xf_ipc_handle +{ + /* ...variable we are waiting on */ + u32 wait; + +} xf_ipc_handle_t; + +/******************************************************************************* + * IPC events + ******************************************************************************/ + +/* ...core resumption flag */ +#define XF_IPC_EVENT_CORE_ASSERT (1 << 0) + +/* ...core waiting flag */ +#define XF_IPC_EVENT_CORE_WAIT (1 << 1) + +/* ...shared memory assertion flag */ +#define XF_IPC_EVENT_SHMEM_ASSERT (1 << 2) + +/* ...shared memory waiting flag */ +#define XF_IPC_EVENT_SHMEM_WAIT (1 << 3) + +/* ...disabled interrupts status */ +#define XF_IPC_EVENT_ISR_OFF (1 << 4) + +/******************************************************************************* + * Shared memory interface (opaque) data + ******************************************************************************/ + +typedef void * xf_shmem_handle_t; diff --git a/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-shmem.h b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-shmem.h new file mode 100644 index 00000000..813bfb48 --- /dev/null +++ b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-shmem.h @@ -0,0 +1,173 @@ +/******************************************************************************* +* Copyright (C) 2018 Cadence Design Systems, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* "Software"), to use this Software with Cadence processor cores only and +* not with any other processors and platforms, subject to +* the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +******************************************************************************/ + +/******************************************************************************* + * xf-shmem.h + * + * Definitions for Xtensa SHMEM configuration + * + *******************************************************************************/ + +#ifndef __XF_H +#error "xf-shmem.h mustn't be included directly" +#endif + +/******************************************************************************* + * Memory structures + ******************************************************************************/ + +/* ...data managed by host CPU (remote) - in case of shunt it is a IPC layer */ +struct xf_proxy_host_data +{ + /* ...command queue */ + xf_proxy_message_t command[XF_PROXY_MESSAGE_QUEUE_LENGTH]; + + /* ...writing index into command queue */ + u32 cmd_write_idx; + + /* ...reading index for response queue */ + u32 rsp_read_idx; +#ifdef XAF_ENABLE_NON_HIKEY +} __attribute__((__packed__, __aligned__(XF_PROXY_ALIGNMENT))); +#else +}/* __attribute__((__packed__, __aligned__(XF_PROXY_ALIGNMENT)))*/; +#endif + +/* ...data managed by DSP (local) */ +struct xf_proxy_dsp_data +{ + /* ...response queue */ + xf_proxy_message_t response[XF_PROXY_MESSAGE_QUEUE_LENGTH]; + + /* ...writing index into response queue */ + u32 rsp_write_idx; + + /* ...reading index for command queue */ + u32 cmd_read_idx; +#ifdef XAF_ENABLE_NON_HIKEY +} __attribute__((__packed__, __aligned__(XF_PROXY_ALIGNMENT))); +#else +}/* __attribute__((__packed__, __aligned__(XF_PROXY_ALIGNMENT)))*/; +#endif +/* ...shared memory data */ +typedef struct xf_shmem_data +{ + /* ...outgoing data (maintained by host CPU (remote side)) */ +#ifdef XAF_ENABLE_NON_HIKEY + struct xf_proxy_host_data remote __xf_shmem__; + + /* ...ingoing data (maintained by DSP (local side)) */ + struct xf_proxy_dsp_data local __xf_shmem__; + + /* ...shared memory pool (page-aligned; why? we map memory to user-space) */ + u8 buffer[XF_CFG_REMOTE_IPC_POOL_SIZE] __attribute__((__aligned__(4096))); +#else + /* ...outgoing data (maintained by host CPU (remote side)) */ + struct xf_proxy_host_data remote/* __xf_shmem__*/; + + /* ...ingoing data (maintained by DSP (local side)) */ + struct xf_proxy_dsp_data local/* __xf_shmem__*/; + + /* ...shared memory pool (page-aligned; why? we map memory to user-space) */ + uint8_t* buffer; +#endif + +} xf_shmem_data_t; + +/******************************************************************************* + * Shared memory accessors + ******************************************************************************/ + +/* ...shared memory pointer for a core */ +#define XF_SHMEM_DATA(core) \ + ((xf_shmem_data_t *)XF_CORE_DATA(core)->shmem) + +/* ...atomic reading */ +#define XF_PROXY_READ_ATOMIC(var) \ + ({ XF_PROXY_INVALIDATE(&(var), sizeof(var)); (var); }) + +/* ...atomic writing */ +#define XF_PROXY_WRITE_ATOMIC(var, value) \ + ({(var) = (value); XF_PROXY_FLUSH(&(var), sizeof(var)); (value); }) + +/* ...accessors */ +#define XF_PROXY_READ(core, field) \ + __XF_PROXY_READ_##field(XF_SHMEM_DATA(core)) + +#define XF_PROXY_WRITE(core, field, v) \ + __XF_PROXY_WRITE_##field(XF_SHMEM_DATA(core), (v)) + +/* ...individual fields accessors */ +#define __XF_PROXY_READ_cmd_write_idx(proxy) \ + XF_PROXY_READ_ATOMIC(proxy->remote.cmd_write_idx) + +#define __XF_PROXY_READ_cmd_read_idx(proxy) \ + proxy->local.cmd_read_idx + +#define __XF_PROXY_READ_rsp_write_idx(proxy) \ + proxy->local.rsp_write_idx + +#define __XF_PROXY_READ_rsp_read_idx(proxy) \ + XF_PROXY_READ_ATOMIC(proxy->remote.rsp_read_idx) + +/* ...individual fields accessors */ +#define __XF_PROXY_WRITE_cmd_write_idx(proxy, v) \ + XF_PROXY_WRITE_ATOMIC(proxy->remote.cmd_write_idx, v) + +#define __XF_PROXY_WRITE_cmd_read_idx(proxy, v) \ + XF_PROXY_WRITE_ATOMIC(proxy->local.cmd_read_idx, v) + +#define __XF_PROXY_WRITE_rsp_read_idx(proxy, v) \ + XF_PROXY_WRITE_ATOMIC(proxy->remote.rsp_read_idx, v) + +#define __XF_PROXY_WRITE_rsp_write_idx(proxy, v) \ + XF_PROXY_WRITE_ATOMIC(proxy->local.rsp_write_idx, v) + +/* ...command buffer accessor */ +#define XF_PROXY_COMMAND(core, idx) \ + (&XF_SHMEM_DATA((core))->remote.command[(idx)]) + +/* ...response buffer accessor */ +#define XF_PROXY_RESPONSE(core, idx) \ + (&XF_SHMEM_DATA((core))->local.response[(idx)]) + +/******************************************************************************* + * Platform-specific SHMEM enable status + ******************************************************************************/ + +static inline int xf_shmem_enabled(u32 core) +{ + return (core == 0); +} + +/******************************************************************************* + * API functions + ******************************************************************************/ + +/* ...process shared memory interface on given DSP core */ +extern void xf_shmem_process_queues(u32 core); + +/* ...completion callback for message originating from remote proxy */ +extern void xf_msg_proxy_complete(xf_message_t *m); + +/* ...initialize shared memory interface (DSP side) */ +extern int xf_shmem_init(u32 core); diff --git a/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-sys.h b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-sys.h new file mode 100644 index 00000000..b82c10eb --- /dev/null +++ b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-sys.h @@ -0,0 +1,75 @@ +/******************************************************************************* +* Copyright (C) 2018 Cadence Design Systems, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* "Software"), to use this Software with Cadence processor cores only and +* not with any other processors and platforms, subject to +* the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +******************************************************************************/ + +/******************************************************************************* + * xf-sys.h + * + * Definitions for Xtensa SHMEM configuration + * + *******************************************************************************/ + +#ifndef __XF_H +#error "xf-sys.h mustn't be included directly" +#endif + +/******************************************************************************* + * Standard system includes + ******************************************************************************/ + +/* ...from directory ./board-BOARDNAME */ +#include "xf-board.h" + +/******************************************************************************* + * Global abstractions + ******************************************************************************/ + +/* ...prevent instructions reordering */ +#define barrier() \ + __asm__ __volatile__("": : : "memory") + +/* ...memory barrier */ +#define XF_PROXY_BARRIER() \ + __asm__ __volatile__("memw": : : "memory") + +/* ...memory invalidation */ +#define XF_PROXY_INVALIDATE(buf, length) \ + ({ if ((length)) { xthal_dcache_region_invalidate((buf), (length)); barrier(); } buf; }) + +/* ...memory flushing */ +#define XF_PROXY_FLUSH(buf, length) \ + ({ if ((length)) { barrier(); xthal_dcache_region_writeback((buf), (length)); XF_PROXY_BARRIER(); } buf; }) + +/******************************************************************************* + * Core-specific data accessor + ******************************************************************************/ + +/* ...per-core execution data */ +extern xf_core_data_t xf_core_data[XF_CFG_CORES_NUM]; + +/* ...local memory accessor */ +#define XF_CORE_DATA(core) (&xf_core_data[core]) + +/******************************************************************************* + * Inter-processor communication and shared memory interface definition + ******************************************************************************/ + +#include "xf-ipc.h" diff --git a/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-types.h b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-types.h new file mode 100644 index 00000000..5f58825f --- /dev/null +++ b/hifi/xaf/hifi-dpf/include/sys/xt-shmem/xf-types.h @@ -0,0 +1,55 @@ +/******************************************************************************* +* Copyright (C) 2018 Cadence Design Systems, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* "Software"), to use this Software with Cadence processor cores only and +* not with any other processors and platforms, subject to +* the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +******************************************************************************/ + +/******************************************************************************* + * xf-types.h + * + * Platform-specific typedefs + * + *******************************************************************************/ + +#ifndef __XF_H +#error "xf-types.h mustn't be included directly" +#endif + +/******************************************************************************* + * Includes + ******************************************************************************/ + +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <stdio.h> +#include <assert.h> +#include <errno.h> +#include <xtensa/config/core.h> + +/******************************************************************************* + * Primitive types + ******************************************************************************/ + +typedef unsigned int u32; +typedef signed int s32; +typedef unsigned short u16; +typedef signed short s16; +typedef unsigned char u8; +typedef signed char s8; |