OMAP4+: Correct the dpll lock sequence

The recommended sequence to update the frequencies for
different dplls are core, mpu, iva. Currently though
core dpll is configured first locking is done
only with the emif freq update mechanism. So the sequence
is mpu, core. Change this so that the core dpll is locked
first and only the post dividers are changed by freq update
procedure later.

Change-Id: I06a7fccd3e33905193d1c24b62e6b1e1ac8e44ef
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Mike J. Chen <mjchen@google.com>

3 files changed, 26 insertions, 10 deletions

diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
index c8777580e..7c58b9f6d 100644
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -36,6 +36,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/utils.h>
 #include <asm/omap_gpio.h>
+#include <asm/arch/emif.h>
 
 #ifndef CONFIG_OMAP4430_ES1_0_MPU_DPLL
 #define CONFIG_OMAP4430_ES1_0_MPU_DPLL mpu_dpll_params_1200mhz
@@ -425,6 +426,13 @@ void configure_mpu_dpll(void)
 	debug("MPU DPLL locked\n");
 }
 
+static void init_m2_core_dpll(u32 *const base, int m2)
+{
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+	writel(m2, &dpll_regs->cm_div_m2_dpll);
+}
+
 static void setup_dplls(void)
 {
 	u32 sysclk_ind, temp;
@@ -435,12 +443,17 @@ static void setup_dplls(void)
 
 	/* CORE dpll */
 	params = get_core_dpll_params();	/* default - safest */
+
 	/*
-	 * Do not lock the core DPLL now. Just set it up.
-	 * Core DPLL will be locked after setting up EMIF
-	 * using the FREQ_UPDATE method(freq_update_core())
+	 * Lock the core DPLL here to get the right sequence.
+	 * But set the M2 post divider to a maximum value so that
+	 * emif/ddr freqeuncy is at a low value for the beginning.
+	 * FREQ_UPDATE method(freq_update_core()) updates the correct
+	 * m2 later.
 	 */
-	do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK);
+	do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_LOCK);
+	init_m2_core_dpll(&prcm->cm_clkmode_dpll_core, CORE_DPLL_M2_INIT);
+
 	/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
 	temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
 	    (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
@@ -448,13 +461,14 @@ static void setup_dplls(void)
 	writel(temp, &prcm->cm_clksel_core);
 	debug("Core DPLL configured\n");
 
+	/* MPU dpll */
+	configure_mpu_dpll();
+
 	/* lock PER dpll */
 	do_setup_dpll(&prcm->cm_clkmode_dpll_per,
 			&per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK);
 	debug("PER DPLL locked\n");
 
-	/* MPU dpll */
-	configure_mpu_dpll();
 }
 
 static void setup_non_essential_dplls(void)
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index 45c88aba8..77fcc2029 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -1230,10 +1230,6 @@ void sdram_init(void)
 	in_sdram = running_from_sdram();
 	debug("in_sdram = %d\n", in_sdram);
 
-	if (!in_sdram) {
-		bypass_dpll(&prcm->cm_clkmode_dpll_core);
-	}
-
 	do_sdram_init(OMAP44XX_EMIF1);
 	do_sdram_init(OMAP44XX_EMIF2);
 
diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
index 3a549bad5..35a7a4d5c 100644
--- a/arch/arm/include/asm/arch-omap4/emif.h
+++ b/arch/arm/include/asm/arch-omap4/emif.h
@@ -907,6 +907,12 @@ struct dmm_lisa_map_regs {
 #define MR8_IO_WIDTH_SHIFT	0x6
 #define MR8_IO_WIDTH_MASK	(0x3 << 0x6)
 
+/*
+ * CORE DPLL m2 divider init, set to maximum
+ * to have the lowest possible frequency.
+ */
+#define CORE_DPLL_M2_INIT 0x1F
+
 struct lpddr2_addressing {
 	u8	num_banks;
 	u8	t_REFI_us_x10;