Merge remote branch 'denx/master'

Conflicts:
	MAKEALL
	arch/arm/cpu/armv7/omap-common/Makefile
	arch/arm/cpu/armv7/start.S
	arch/arm/include/asm/arch-omap4/cpu.h
	arch/arm/include/asm/arch-omap4/sys_proto.h
	arch/arm/lib/board.c
	common/cmd_led.c
	common/serial.c
	drivers/i2c/omap24xx_i2c.c
	include/configs/omap3_beagle.h
	include/configs/omap4_panda.h
	include/serial.h

Change-Id: Ib6573909994b707670aac7353e915f6d33f2481a

8 files changed, 684 insertions, 821 deletions

diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 3968c14bb..6e948605d 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -29,13 +29,13 @@ COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o
 COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
 COBJS-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
 COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
+COBJS-$(CONFIG_FTSDC010) += ftsdc010_esdhc.o
 COBJS-$(CONFIG_GENERIC_MMC) += mmc.o
 COBJS-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
 COBJS-$(CONFIG_MMC_SPI) += mmc_spi.o
 COBJS-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
 COBJS-$(CONFIG_MV_SDHCI) += mv_sdhci.o
 COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o
-COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o
 COBJS-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o
 COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o
 COBJS-$(CONFIG_S5P_MMC) += s5p_mmc.o
diff --git a/drivers/mmc/atmel_mci.h b/drivers/mmc/atmel_mci.h
index 3095d22e6..90ab6a8a6 100644
--- a/drivers/mmc/atmel_mci.h
+++ b/drivers/mmc/atmel_mci.h
@@ -36,7 +36,7 @@ typedef struct atmel_mci {
 	u32	sdcr;	/* 0x0c */
 	u32	argr;	/* 0x10 */
 	u32	cmdr;	/* 0x14 */
-	u32	blkr;	/* 0x18 */
+	u32	_18;	/* 0x18 */
 	u32	_1c;	/* 0x1c */
 	u32	rspr;	/* 0x20 */
 	u32	rspr1;	/* 0x24 */
@@ -67,7 +67,6 @@ typedef struct atmel_mci {
 #define MMCI_SDCR				0x000c
 #define MMCI_ARGR				0x0010
 #define MMCI_CMDR				0x0014
-#define MMCI_BLKR				0x0018
 #define MMCI_RSPR				0x0020
 #define MMCI_RSPR1				0x0024
 #define MMCI_RSPR2				0x0028
@@ -141,12 +140,6 @@ typedef struct atmel_mci {
 #define MMCI_TRTYP_OFFSET			19
 #define MMCI_TRTYP_SIZE				2
 
-/* Bitfields in BLKR */
-#define MMCI_BCNT_OFFSET			0
-#define MMCI_BCNT_SIZE				16
-#define MMCI_BLKLEN_OFFSET			16
-#define MMCI_BLKLEN_SIZE			16
-
 /* Bitfields in RSPRx */
 #define MMCI_RSP_OFFSET				0
 #define MMCI_RSP_SIZE				32
diff --git a/drivers/mmc/ftsdc010_esdhc.c b/drivers/mmc/ftsdc010_esdhc.c
new file mode 100644
index 000000000..e38dd87f1
--- /dev/null
+++ b/drivers/mmc/ftsdc010_esdhc.c
@@ -0,0 +1,667 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <mmc.h>
+
+#include <asm/io.h>
+#include <faraday/ftsdc010.h>
+
+/*
+ * supported mmc hosts
+ * setting the number CONFIG_FTSDC010_NUMBER in your configuration file.
+ */
+static struct mmc ftsdc010_dev[CONFIG_FTSDC010_NUMBER];
+static struct mmc_host ftsdc010_host[CONFIG_FTSDC010_NUMBER];
+
+static struct ftsdc010_mmc *ftsdc010_get_base_mmc(int dev_index)
+{
+	return (struct ftsdc010_mmc *)CONFIG_FTSDC010_BASE + dev_index;
+}
+
+#ifdef DEBUG
+static void ftsdc010_dump_reg(struct mmc_host *host)
+{
+	debug("cmd: %08x\n",		readl(&host->reg->cmd));
+	debug("argu: %08x\n",		readl(&host->reg->argu));
+	debug("rsp0: %08x\n",		readl(&host->reg->rsp0));
+	debug("rsp1: %08x\n",		readl(&host->reg->rsp1));
+	debug("rsp2: %08x\n",		readl(&host->reg->rsp2));
+	debug("rsp3: %08x\n",		readl(&host->reg->rsp3));
+	debug("rsp_cmd: %08x\n",	readl(&host->reg->rsp_cmd));
+	debug("dcr: %08x\n",		readl(&host->reg->dcr));
+	debug("dtr: %08x\n",		readl(&host->reg->dtr));
+	debug("dlr: %08x\n",		readl(&host->reg->dlr));
+	debug("status: %08x\n",		readl(&host->reg->status));
+	debug("clr: %08x\n",		readl(&host->reg->clr));
+	debug("int_mask: %08x\n",	readl(&host->reg->int_mask));
+	debug("pcr: %08x\n",		readl(&host->reg->pcr));
+	debug("ccr: %08x\n",		readl(&host->reg->ccr));
+	debug("bwr: %08x\n",		readl(&host->reg->bwr));
+	debug("dwr: %08x\n",		readl(&host->reg->dwr));
+	debug("feature: %08x\n",	readl(&host->reg->feature));
+	debug("rev: %08x\n",		readl(&host->reg->rev));
+}
+#endif
+
+static unsigned int enable_imask(struct ftsdc010_mmc *reg, unsigned int imask)
+{
+	unsigned int newmask;
+
+	newmask = readl(&reg->int_mask);
+	newmask |= imask;
+
+	writel(newmask, &reg->int_mask);
+
+	return newmask;
+}
+
+static void ftsdc010_pio_read(struct mmc_host *host, char *buf, unsigned int size)
+{
+	unsigned int fifo;
+	unsigned int fifo_words;
+	unsigned int *ptr;
+	unsigned int status;
+	unsigned int retry = 0;
+
+	/* get_data_buffer */
+	ptr = (unsigned int *)buf;
+
+	while (size) {
+		status = readl(&host->reg->status);
+
+		if (status & FTSDC010_STATUS_FIFO_ORUN) {
+			fifo = host->fifo_len > size ?
+				size : host->fifo_len;
+
+			size -= fifo;
+
+			fifo_words = fifo >> 2;
+
+			while (fifo_words--)
+				*ptr++ = readl(&host->reg->dwr);
+
+			/*
+			 * for adding some delays for SD card to put
+			 * data into FIFO again
+			 */
+			udelay(4*FTSDC010_DELAY_UNIT);
+
+#ifdef CONFIG_FTSDC010_SDIO
+			/* sdio allow non-power-of-2 blksz */
+			if (fifo & 3) {
+				unsigned int n = fifo & 3;
+				unsigned int data = readl(&host->reg->dwr);
+
+				unsigned char *p = (unsigned char *)ptr;
+
+				while (n--) {
+					*p++ = data;
+					data >>= 8;
+				}
+			}
+#endif
+		} else {
+			udelay(1);
+			if (++retry >= FTSDC010_PIO_RETRY) {
+				debug("%s: PIO_RETRY timeout\n", __func__);
+				return;
+			}
+		}
+	}
+}
+
+static void ftsdc010_pio_write(struct mmc_host *host, const char *buf,
+			unsigned int size)
+{
+	unsigned int fifo;
+	unsigned int *ptr;
+	unsigned int status;
+	unsigned int retry = 0;
+
+	/* get data buffer */
+	ptr = (unsigned int *)buf;
+
+	while (size) {
+		status = readl(&host->reg->status);
+
+		if (status & FTSDC010_STATUS_FIFO_ORUN) {
+			fifo = host->fifo_len > size ?
+				size : host->fifo_len;
+
+			size -= fifo;
+
+			fifo = (fifo + 3) >> 2;
+
+			while (fifo--) {
+				writel(*ptr, &host->reg->dwr);
+				ptr++;
+			}
+
+		} else {
+			udelay(1);
+			if (++retry >= FTSDC010_PIO_RETRY) {
+				debug("%s: PIO_RETRY timeout\n", __func__);
+				return;
+			}
+		}
+	}
+}
+
+static int ftsdc010_pio_check_status(struct mmc *mmc, struct mmc_cmd *cmd,
+			struct mmc_data *data)
+{
+	struct mmc_host *host = mmc->priv;
+
+	unsigned int sta, clear;
+	unsigned int i;
+
+	/* check response and hardware status */
+	clear = 0;
+
+	/* chech CMD_SEND */
+	for (i = 0; i < FTSDC010_CMD_RETRY; i++) {
+		sta = readl(&host->reg->status);
+		/* Command Complete */
+		if (sta & FTSDC010_STATUS_CMD_SEND) {
+			if (!data)
+				clear |= FTSDC010_CLR_CMD_SEND;
+			break;
+		}
+	}
+
+	if (i > FTSDC010_CMD_RETRY) {
+		printf("%s: send command timeout\n", __func__);
+		return TIMEOUT;
+	}
+
+	/* debug: print status register and command index*/
+	debug("sta: %08x cmd %d\n", sta, cmd->cmdidx);
+
+	/* handle data FIFO */
+	if ((sta & FTSDC010_STATUS_FIFO_ORUN) ||
+		(sta & FTSDC010_STATUS_FIFO_URUN)) {
+
+		/* Wrong DATA FIFO Flag */
+		if (data == NULL)
+			printf("%s, data fifo wrong: sta: %08x cmd %d\n",
+				__func__, sta, cmd->cmdidx);
+
+		if (sta & FTSDC010_STATUS_FIFO_ORUN)
+			clear |= FTSDC010_STATUS_FIFO_ORUN;
+		if (sta & FTSDC010_STATUS_FIFO_URUN)
+			clear |= FTSDC010_STATUS_FIFO_URUN;
+	}
+
+	/* check RSP TIMEOUT or FAIL */
+	if (sta & FTSDC010_STATUS_RSP_TIMEOUT) {
+		/* RSP TIMEOUT */
+		debug("%s: RSP timeout: sta: %08x cmd %d\n",
+				__func__, sta, cmd->cmdidx);
+
+		clear |= FTSDC010_CLR_RSP_TIMEOUT;
+		writel(clear, &host->reg->clr);
+
+		return TIMEOUT;
+	} else if (sta & FTSDC010_STATUS_RSP_CRC_FAIL) {
+		/* clear response fail bit */
+		debug("%s: RSP CRC FAIL: sta: %08x cmd %d\n",
+				__func__, sta, cmd->cmdidx);
+
+		clear |= FTSDC010_CLR_RSP_CRC_FAIL;
+		writel(clear, &host->reg->clr);
+
+		return 0;
+	} else if (sta & FTSDC010_STATUS_RSP_CRC_OK) {
+
+		/* clear response CRC OK bit */
+		clear |= FTSDC010_CLR_RSP_CRC_OK;
+	}
+
+	/* check DATA TIMEOUT or FAIL */
+	if (data) {
+		if (sta & FTSDC010_STATUS_DATA_TIMEOUT) {
+			/* DATA TIMEOUT */
+			debug("%s: DATA TIMEOUT: sta: %08x\n",
+					__func__, sta);
+
+			clear |= FTSDC010_STATUS_DATA_TIMEOUT;
+			writel(sta, &host->reg->clr);
+			return TIMEOUT;
+		} else if (sta & FTSDC010_STATUS_DATA_CRC_FAIL) {
+			/* Error Interrupt */
+			debug("%s: DATA CRC FAIL: sta: %08x\n",
+					__func__, sta);
+
+			clear |= FTSDC010_STATUS_DATA_CRC_FAIL;
+			writel(clear, &host->reg->clr);
+
+			return 0;
+		} else if (sta & FTSDC010_STATUS_DATA_END) {
+			/* Transfer Complete */
+			clear |= FTSDC010_STATUS_DATA_END;
+		}
+	}
+
+	/* transaction is success and clear status register */
+	writel(clear, &host->reg->clr);
+
+	return 0;
+}
+
+static int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+			struct mmc_data *data)
+{
+	struct mmc_host *host = mmc->priv;
+
+#ifdef CONFIG_FTSDC010_SDIO
+	unsigned int scon;
+#endif
+	unsigned int ccon;
+	unsigned int mask, tmpmask;
+	unsigned int ret;
+
+	if (data)
+		mask = FTSDC010_INT_MASK_RSP_TIMEOUT;
+	else if (cmd->resp_type & MMC_RSP_PRESENT)
+		mask = FTSDC010_INT_MASK_RSP_TIMEOUT;
+	else
+		mask = FTSDC010_INT_MASK_CMD_SEND;
+
+	/* write argu reg */
+	debug("%s: cmd->arg: %08x\n", __func__, cmd->cmdarg);
+	writel(cmd->cmdarg, &host->reg->argu);
+
+	/* setup cmd reg */
+	debug("cmd: %d\n", cmd->cmdidx);
+	debug("resp: %08x\n", cmd->resp_type);
+
+	/* setup commnad */
+	ccon = FTSDC010_CMD_IDX(cmd->cmdidx);
+
+	/* setup command flags */
+	ccon |= FTSDC010_CMD_CMD_EN;
+
+	/*
+	 * This hardware didn't support specific commands for mapping
+	 * MMC_RSP_BUSY and MMC_RSP_OPCODE. Hence we don't deal with it.
+	 */
+	if (cmd->resp_type & MMC_RSP_PRESENT) {
+		ccon |= FTSDC010_CMD_NEED_RSP;
+		mask |= FTSDC010_INT_MASK_RSP_CRC_OK |
+			FTSDC010_INT_MASK_RSP_CRC_FAIL;
+	}
+
+	if (cmd->resp_type & MMC_RSP_136)
+		ccon |= FTSDC010_CMD_LONG_RSP;
+
+	/* In Linux driver, MMC_CMD_APP_CMD is checked in last_opcode */
+	if (host->last_opcode == MMC_CMD_APP_CMD)
+		ccon |= FTSDC010_CMD_APP_CMD;
+
+#ifdef CONFIG_FTSDC010_SDIO
+	scon = readl(&host->reg->sdio_ctrl1);
+	if (host->card_type == MMC_TYPE_SDIO)
+		scon |= FTSDC010_SDIO_CTRL1_SDIO_ENABLE;
+	else
+		scon &= ~FTSDC010_SDIO_CTRL1_SDIO_ENABLE;
+	writel(scon, &host->reg->sdio_ctrl1);
+#endif
+
+	/* record last opcode for specifing the command type to hardware */
+	host->last_opcode = cmd->cmdidx;
+
+	/* write int_mask reg */
+	tmpmask = readl(&host->reg->int_mask);
+	tmpmask |= mask;
+	writel(tmpmask, &host->reg->int_mask);
+
+	/* write cmd reg */
+	debug("%s: ccon: %08x\n", __func__, ccon);
+	writel(ccon, &host->reg->cmd);
+	udelay(4*FTSDC010_DELAY_UNIT);
+
+	/* read/write data */
+	if (data && (data->flags & MMC_DATA_READ)) {
+		ftsdc010_pio_read(host, data->dest,
+				data->blocksize * data->blocks);
+	} else if (data && (data->flags & MMC_DATA_WRITE)) {
+		ftsdc010_pio_write(host, data->src,
+				data->blocksize * data->blocks);
+	}
+
+	/* pio check response status */
+	ret = ftsdc010_pio_check_status(mmc, cmd, data);
+	if (!ret) {
+		/* if it is long response */
+		if (ccon & FTSDC010_CMD_LONG_RSP) {
+			cmd->response[0] = readl(&host->reg->rsp3);
+			cmd->response[1] = readl(&host->reg->rsp2);
+			cmd->response[2] = readl(&host->reg->rsp1);
+			cmd->response[3] = readl(&host->reg->rsp0);
+
+		} else {
+			cmd->response[0] = readl(&host->reg->rsp0);
+		}
+	}
+
+	udelay(FTSDC010_DELAY_UNIT);
+	return ret;
+}
+
+static unsigned int cal_blksz(unsigned int blksz)
+{
+	unsigned int blksztwo = 0;
+
+	while (blksz >>= 1)
+		blksztwo++;
+
+	return blksztwo;
+}
+
+static int ftsdc010_setup_data(struct mmc *mmc, struct mmc_data *data)
+{
+	struct mmc_host *host = mmc->priv;
+	unsigned int dcon, newmask;
+
+	/* configure data transfer paramter */
+	if (!data)
+		return 0;
+
+	if (((data->blocksize - 1) & data->blocksize) != 0) {
+		printf("%s: can't do non-power-of 2 sized block transfers"
+			" (blksz %d)\n", __func__, data->blocksize);
+		return -1;
+	}
+
+	/*
+	 * We cannot deal with unaligned blocks with more than
+	 * one block being transfered.
+	 */
+	if ((data->blocksize <= 2) && (data->blocks > 1)) {
+			printf("%s: can't do non-word sized block transfers"
+				" (blksz %d)\n", __func__, data->blocksize);
+			return -1;
+	}
+
+	/* data length */
+	dcon = data->blocksize * data->blocks;
+	writel(dcon, &host->reg->dlr);
+
+	/* write data control */
+	dcon = cal_blksz(data->blocksize);
+
+	/* add to IMASK register */
+	newmask = (FTSDC010_STATUS_RSP_CRC_FAIL | FTSDC010_STATUS_DATA_TIMEOUT);
+
+	/*
+	 * enable UNDERRUN will trigger interrupt immediatedly
+	 * So setup it when rsp is received successfully
+	 */
+	if (data->flags & MMC_DATA_WRITE) {
+		dcon |= FTSDC010_DCR_DATA_WRITE;
+	} else {
+		dcon &= ~FTSDC010_DCR_DATA_WRITE;
+		newmask |= FTSDC010_STATUS_FIFO_ORUN;
+	}
+	enable_imask(host->reg, newmask);
+
+#ifdef CONFIG_FTSDC010_SDIO
+	/* always reset fifo since last transfer may fail */
+	dcon |= FTSDC010_DCR_FIFO_RST;
+
+	/* handle sdio */
+	dcon = data->blocksize | data->blocks << 15;
+	if (data->blocks > 1)
+		dcon |= FTSDC010_SDIO_CTRL1_SDIO_BLK_MODE;
+#endif
+
+	/* enable data transfer which will be pended until cmd is send */
+	dcon |= FTSDC010_DCR_DATA_EN;
+	writel(dcon, &host->reg->dcr);
+
+	return 0;
+}
+
+static int ftsdc010_send_request(struct mmc *mmc, struct mmc_cmd *cmd,
+			struct mmc_data *data)
+{
+	int ret;
+
+	if (data) {
+		ret = ftsdc010_setup_data(mmc, data);
+
+		if (ret) {
+			printf("%s: setup data error\n", __func__);
+			return -1;
+		}
+
+		if ((data->flags & MMC_DATA_BOTH_DIR) == MMC_DATA_BOTH_DIR) {
+			printf("%s: data is both direction\n", __func__);
+			return -1;
+		}
+	}
+
+	/* Send command */
+	ret = ftsdc010_send_cmd(mmc, cmd, data);
+	return ret;
+}
+
+static int ftsdc010_card_detect(struct mmc *mmc)
+{
+	struct mmc_host *host = mmc->priv;
+	unsigned int sta;
+
+	sta = readl(&host->reg->status);
+	debug("%s: card status: %08x\n", __func__, sta);
+
+	return (sta & FTSDC010_STATUS_CARD_DETECT) ? 0 : 1;
+}
+
+static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd,
+			struct mmc_data *data)
+{
+	int ret;
+
+	if (ftsdc010_card_detect(mmc) == 0) {
+		printf("%s: no medium present\n", __func__);
+		return -1;
+	} else {
+		ret = ftsdc010_send_request(mmc, cmd, data);
+		return ret;
+	}
+}
+
+static void ftsdc010_set_clk(struct mmc *mmc)
+{
+	struct mmc_host *host = mmc->priv;
+	unsigned char clk_div;
+	unsigned char real_rate;
+	unsigned int clock;
+
+	debug("%s: mmc_set_clock: %x\n", __func__, mmc->clock);
+	clock = readl(&host->reg->ccr);
+
+	if (mmc->clock == 0) {
+		real_rate = 0;
+		clock |= FTSDC010_CCR_CLK_DIS;
+	} else {
+		debug("%s, mmc->clock: %08x, origin clock: %08x\n",
+			 __func__, mmc->clock, clock);
+
+		for (clk_div = 0; clk_div <= 127; clk_div++) {
+			real_rate = (CONFIG_SYS_CLK_FREQ / 2) /
+					(2 * (clk_div + 1));
+
+			if (real_rate <= mmc->clock)
+				break;
+		}
+
+		debug("%s: computed real_rete: %x, clk_div: %x\n",
+			 __func__, real_rate, clk_div);
+
+		if (clk_div > 127)
+			debug("%s: no match clock rate, %x\n",
+				__func__, mmc->clock);
+
+		clock = (clock & ~FTSDC010_CCR_CLK_DIV(0x7f)) |
+				FTSDC010_CCR_CLK_DIV(clk_div);
+
+		clock &= ~FTSDC010_CCR_CLK_DIS;
+	}
+
+	debug("%s, set clock: %08x\n", __func__, clock);
+	writel(clock, &host->reg->ccr);
+}
+
+static void ftsdc010_set_ios(struct mmc *mmc)
+{
+	struct mmc_host *host = mmc->priv;
+	unsigned int power;
+	unsigned long val;
+	unsigned int bus_width;
+
+	debug("%s: bus_width: %x, clock: %d\n",
+		__func__, mmc->bus_width, mmc->clock);
+
+	/* set pcr: power on */
+	power = readl(&host->reg->pcr);
+	power |= FTSDC010_PCR_POWER_ON;
+	writel(power, &host->reg->pcr);
+
+	if (mmc->clock)
+		ftsdc010_set_clk(mmc);
+
+	/* set bwr: bus width reg */
+	bus_width = readl(&host->reg->bwr);
+	bus_width &= ~(FTSDC010_BWR_WIDE_8_BUS | FTSDC010_BWR_WIDE_4_BUS |
+			FTSDC010_BWR_SINGLE_BUS);
+
+	if (mmc->bus_width == 8)
+		bus_width |= FTSDC010_BWR_WIDE_8_BUS;
+	else if (mmc->bus_width == 4)
+		bus_width |= FTSDC010_BWR_WIDE_4_BUS;
+	else
+		bus_width |= FTSDC010_BWR_SINGLE_BUS;
+
+	writel(bus_width, &host->reg->bwr);
+
+	/* set fifo depth */
+	val = readl(&host->reg->feature);
+	host->fifo_len = FTSDC010_FEATURE_FIFO_DEPTH(val) * 4; /* 4 bytes */
+
+	/* set data timeout register */
+	val = -1;
+	writel(val, &host->reg->dtr);
+}
+
+static void ftsdc010_reset(struct mmc_host *host)
+{
+	unsigned int timeout;
+
+	/* Do SDC_RST: Software reset for all register */
+	writel(FTSDC010_CMD_SDC_RST, &host->reg->cmd);
+
+	host->clock = 0;
+
+	/* this hardware has no reset finish flag to read */
+	/* wait 100ms maximum */
+	timeout = 100;
+
+	/* hw clears the bit when it's done */
+	while (readl(&host->reg->dtr) != 0) {
+		if (timeout == 0) {
+			printf("%s: reset timeout error\n", __func__);
+			return;
+		}
+		timeout--;
+		udelay(10*FTSDC010_DELAY_UNIT);
+	}
+}
+
+static int ftsdc010_core_init(struct mmc *mmc)
+{
+	struct mmc_host *host = mmc->priv;
+	unsigned int mask;
+	unsigned int major, minor, revision;
+
+	/* get hardware version */
+	host->version = readl(&host->reg->rev);
+
+	major = FTSDC010_REV_MAJOR(host->version);
+	minor = FTSDC010_REV_MINOR(host->version);
+	revision = FTSDC010_REV_REVISION(host->version);
+
+	printf("ftsdc010 hardware ver: %d_%d_r%d\n", major, minor, revision);
+
+	/* Interrupt MASK register init - mask all */
+	writel(0x0, &host->reg->int_mask);
+
+	mask = FTSDC010_INT_MASK_CMD_SEND |
+		FTSDC010_INT_MASK_DATA_END |
+		FTSDC010_INT_MASK_CARD_CHANGE;
+#ifdef CONFIG_FTSDC010_SDIO
+	mask |= FTSDC010_INT_MASK_CP_READY |
+		FTSDC010_INT_MASK_CP_BUF_READY |
+		FTSDC010_INT_MASK_PLAIN_TEXT_READY |
+		FTSDC010_INT_MASK_SDIO_IRPT;
+#endif
+
+	writel(mask, &host->reg->int_mask);
+
+	return 0;
+}
+
+int ftsdc010_mmc_init(int dev_index)
+{
+	struct mmc *mmc;
+	struct mmc_host *host;
+
+	mmc = &ftsdc010_dev[dev_index];
+
+	sprintf(mmc->name, "FTSDC010 SD/MMC");
+	mmc->priv = &ftsdc010_host[dev_index];
+	mmc->send_cmd = ftsdc010_request;
+	mmc->set_ios = ftsdc010_set_ios;
+	mmc->init = ftsdc010_core_init;
+
+	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+
+	mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
+
+	mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+
+	mmc->f_min = CONFIG_SYS_CLK_FREQ / 2 / (2*128);
+	mmc->f_max = CONFIG_SYS_CLK_FREQ / 2 / 2;
+
+	ftsdc010_host[dev_index].clock = 0;
+	ftsdc010_host[dev_index].reg = ftsdc010_get_base_mmc(dev_index);
+	mmc_register(mmc);
+
+	/* reset mmc */
+	host = (struct mmc_host *)mmc->priv;
+	ftsdc010_reset(host);
+
+	return 0;
+}
diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c
index d217574b5..f346b244b 100644
--- a/drivers/mmc/gen_atmel_mci.c
+++ b/drivers/mmc/gen_atmel_mci.c
@@ -183,10 +183,6 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 	/* Figure out the transfer arguments */
 	cmdr = mci_encode_cmd(cmd, data, &error_flags);
 
-	if (data)
-		writel(MMCI_BF(BCNT, data->blocks) |
-			MMCI_BF(BLKLEN,	mmc->read_bl_len), &mci->blkr);
-
 	/* Send the command */
 	writel(cmd->cmdarg, &mci->argr);
 	writel(cmdr, &mci->cmdr);
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index ac5093d1a..0f16a3f4d 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -115,7 +115,8 @@ int mmc_send_status(struct mmc *mmc, int timeout)
 
 	cmd.cmdidx = MMC_CMD_SEND_STATUS;
 	cmd.resp_type = MMC_RSP_R1;
-	cmd.cmdarg = 0;
+	if (!mmc_host_is_spi(mmc))
+		cmd.cmdarg = mmc->rca << 16;
 	cmd.flags = 0;
 
 	do {
@@ -1168,12 +1169,14 @@ int mmc_register(struct mmc *mmc)
 	return 0;
 }
 
+#ifdef CONFIG_PARTITIONS
 block_dev_desc_t *mmc_get_dev(int dev)
 {
 	struct mmc *mmc = find_mmc_device(dev);
 
 	return mmc ? &mmc->block_dev : NULL;
 }
+#endif
 
 int mmc_init(struct mmc *mmc)
 {
diff --git a/drivers/mmc/omap3_mmc.c b/drivers/mmc/omap3_mmc.c
deleted file mode 100644
index 15d41e55b..000000000
--- a/drivers/mmc/omap3_mmc.c
+++ /dev/null
@@ -1,570 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation's version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <common.h>
-#include <fat.h>
-#include <mmc.h>
-#include <part.h>
-#include <i2c.h>
-#include <twl4030.h>
-#include <asm/io.h>
-
-#include "omap3_mmc.h"
-
-static const unsigned short mmc_transspeed_val[15][4] = {
-	{CLKD(10, 1), CLKD(10, 10), CLKD(10, 100), CLKD(10, 1000)},
-	{CLKD(12, 1), CLKD(12, 10), CLKD(12, 100), CLKD(12, 1000)},
-	{CLKD(13, 1), CLKD(13, 10), CLKD(13, 100), CLKD(13, 1000)},
-	{CLKD(15, 1), CLKD(15, 10), CLKD(15, 100), CLKD(15, 1000)},
-	{CLKD(20, 1), CLKD(20, 10), CLKD(20, 100), CLKD(20, 1000)},
-	{CLKD(26, 1), CLKD(26, 10), CLKD(26, 100), CLKD(26, 1000)},
-	{CLKD(30, 1), CLKD(30, 10), CLKD(30, 100), CLKD(30, 1000)},
-	{CLKD(35, 1), CLKD(35, 10), CLKD(35, 100), CLKD(35, 1000)},
-	{CLKD(40, 1), CLKD(40, 10), CLKD(40, 100), CLKD(40, 1000)},
-	{CLKD(45, 1), CLKD(45, 10), CLKD(45, 100), CLKD(45, 1000)},
-	{CLKD(52, 1), CLKD(52, 10), CLKD(52, 100), CLKD(52, 1000)},
-	{CLKD(55, 1), CLKD(55, 10), CLKD(55, 100), CLKD(55, 1000)},
-	{CLKD(60, 1), CLKD(60, 10), CLKD(60, 100), CLKD(60, 1000)},
-	{CLKD(70, 1), CLKD(70, 10), CLKD(70, 100), CLKD(70, 1000)},
-	{CLKD(80, 1), CLKD(80, 10), CLKD(80, 100), CLKD(80, 1000)}
-};
-
-static mmc_card_data cur_card_data;
-static block_dev_desc_t mmc_blk_dev;
-static hsmmc_t *mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE;
-
-int mmc_set_dev(int dev_num)
-{
-	switch (dev_num) {
-	case 1:
-		mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE;
-		break;
-	case 2:
-		mmc_base = (hsmmc_t *)OMAP_HSMMC2_BASE;
-		break;
-	case 3:
-		mmc_base = (hsmmc_t *)OMAP_HSMMC3_BASE;
-		break;
-	default:
-		mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE;
-		return 1;
-	}
-
-	return 0;
-}
-
-block_dev_desc_t *mmc_get_dev(int dev)
-{
-	return (block_dev_desc_t *) &mmc_blk_dev;
-}
-
-static unsigned char mmc_board_init(void)
-{
-#if defined(CONFIG_TWL4030_POWER)
-	twl4030_power_mmc_init();
-#endif
-
-#if defined(CONFIG_OMAP34XX)
-	t2_t *t2_base = (t2_t *)T2_BASE;
-	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-
-	writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
-		PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
-		&t2_base->pbias_lite);
-
-	writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
-		&t2_base->devconf0);
-
-	writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
-		&t2_base->devconf1);
-
-	writel(readl(&prcm_base->fclken1_core) |
-		EN_MMC1 | EN_MMC2 | EN_MMC3,
-		&prcm_base->fclken1_core);
-
-	writel(readl(&prcm_base->iclken1_core) |
-		EN_MMC1 | EN_MMC2 | EN_MMC3,
-		&prcm_base->iclken1_core);
-#endif
-
-/* TODO add appropriate OMAP4 init */
-
-	return 1;
-}
-
-static void mmc_init_stream(void)
-{
-	writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
-
-	writel(MMC_CMD0, &mmc_base->cmd);
-	while (!(readl(&mmc_base->stat) & CC_MASK));
-
-	writel(CC_MASK, &mmc_base->stat);
-
-	writel(MMC_CMD0, &mmc_base->cmd);
-	while (!(readl(&mmc_base->stat) & CC_MASK));
-
-	writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
-}
-
-static unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div)
-{
-	unsigned int val;
-
-	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
-			(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
-
-	switch (iclk) {
-	case CLK_INITSEQ:
-		val = MMC_INIT_SEQ_CLK / 2;
-		break;
-	case CLK_400KHZ:
-		val = MMC_400kHz_CLK;
-		break;
-	case CLK_MISC:
-		val = clk_div;
-		break;
-	default:
-		return 0;
-	}
-	mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
-			(val << CLKD_OFFSET) | ICE_OSCILLATE);
-
-	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY);
-
-	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
-	return 1;
-}
-
-static unsigned char mmc_init_setup(void)
-{
-	unsigned int reg_val;
-
-	mmc_board_init();
-
-	writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
-		&mmc_base->sysconfig);
-	while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0);
-
-	writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
-	while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0);
-
-	writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
-	writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
-		&mmc_base->capa);
-
-	reg_val = readl(&mmc_base->con) & RESERVED_MASK;
-
-	writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
-		MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
-		HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
-
-	mmc_clock_config(CLK_INITSEQ, 0);
-	writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
-
-	writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
-		IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
-		&mmc_base->ie);
-
-	mmc_init_stream();
-	return 1;
-}
-
-static unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg,
-				unsigned int *response)
-{
-	unsigned int mmc_stat;
-
-	while ((readl(&mmc_base->pstate) & DATI_MASK) == DATI_CMDDIS);
-
-	writel(BLEN_512BYTESLEN | NBLK_STPCNT, &mmc_base->blk);
-	writel(0xFFFFFFFF, &mmc_base->stat);
-	writel(arg, &mmc_base->arg);
-	writel(cmd | CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
-		MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE,
-		&mmc_base->cmd);
-
-	while (1) {
-		do {
-			mmc_stat = readl(&mmc_base->stat);
-		} while (mmc_stat == 0);
-
-		if ((mmc_stat & ERRI_MASK) != 0)
-			return (unsigned char) mmc_stat;
-
-		if (mmc_stat & CC_MASK) {
-			writel(CC_MASK, &mmc_base->stat);
-			response[0] = readl(&mmc_base->rsp10);
-			if ((cmd & RSP_TYPE_MASK) == RSP_TYPE_LGHT136) {
-				response[1] = readl(&mmc_base->rsp32);
-				response[2] = readl(&mmc_base->rsp54);
-				response[3] = readl(&mmc_base->rsp76);
-			}
-			break;
-		}
-	}
-	return 1;
-}
-
-static unsigned char mmc_read_data(unsigned int *output_buf)
-{
-	unsigned int mmc_stat;
-	unsigned int read_count = 0;
-
-	/*
-	 * Start Polled Read
-	 */
-	while (1) {
-		do {
-			mmc_stat = readl(&mmc_base->stat);
-		} while (mmc_stat == 0);
-
-		if ((mmc_stat & ERRI_MASK) != 0)
-			return (unsigned char) mmc_stat;
-
-		if (mmc_stat & BRR_MASK) {
-			unsigned int k;
-
-			writel(readl(&mmc_base->stat) | BRR_MASK,
-				&mmc_base->stat);
-			for (k = 0; k < MMCSD_SECTOR_SIZE / 4; k++) {
-				*output_buf = readl(&mmc_base->data);
-				output_buf++;
-				read_count += 4;
-			}
-		}
-
-		if (mmc_stat & BWR_MASK)
-			writel(readl(&mmc_base->stat) | BWR_MASK,
-				&mmc_base->stat);
-
-		if (mmc_stat & TC_MASK) {
-			writel(readl(&mmc_base->stat) | TC_MASK,
-				&mmc_base->stat);
-			break;
-		}
-	}
-	return 1;
-}
-
-static unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur)
-{
-	unsigned char err;
-	unsigned int argument = 0;
-	unsigned int ocr_value, ocr_recvd, ret_cmd41, hcs_val;
-	unsigned short retry_cnt = 2000;
-	mmc_resp_t mmc_resp;
-
-	/* Set to Initialization Clock */
-	err = mmc_clock_config(CLK_400KHZ, 0);
-	if (err != 1)
-		return err;
-
-	mmc_card_cur->RCA = MMC_RELATIVE_CARD_ADDRESS;
-	argument = 0x00000000;
-
-	ocr_value = (0x1FF << 15);
-	err = mmc_send_cmd(MMC_CMD0, argument, mmc_resp.resp);
-	if (err != 1)
-		return err;
-
-	argument = SD_CMD8_CHECK_PATTERN | SD_CMD8_2_7_3_6_V_RANGE;
-	err = mmc_send_cmd(MMC_SDCMD8, argument, mmc_resp.resp);
-	hcs_val = (err == 1) ?
-		MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR :
-		MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE;
-
-	argument = 0x0000 << 16;
-	err = mmc_send_cmd(MMC_CMD55, argument, mmc_resp.resp);
-	if (err == 1) {
-		mmc_card_cur->card_type = SD_CARD;
-		ocr_value |= hcs_val;
-		ret_cmd41 = MMC_ACMD41;
-	} else {
-		mmc_card_cur->card_type = MMC_CARD;
-		ocr_value |= MMC_OCR_REG_ACCESS_MODE_SECTOR;
-		ret_cmd41 = MMC_CMD1;
-		writel(readl(&mmc_base->con) & ~OD, &mmc_base->con);
-		writel(readl(&mmc_base->con) | OPENDRAIN, &mmc_base->con);
-	}
-
-	argument = ocr_value;
-	err = mmc_send_cmd(ret_cmd41, argument, mmc_resp.resp);
-	if (err != 1)
-		return err;
-
-	ocr_recvd = mmc_resp.r3.ocr;
-
-	while (!(ocr_recvd & (0x1 << 31)) && (retry_cnt > 0)) {
-		retry_cnt--;
-		if (mmc_card_cur->card_type == SD_CARD) {
-			argument = 0x0000 << 16;
-			err = mmc_send_cmd(MMC_CMD55, argument, mmc_resp.resp);
-		}
-
-		argument = ocr_value;
-		err = mmc_send_cmd(ret_cmd41, argument, mmc_resp.resp);
-		if (err != 1)
-			return err;
-		ocr_recvd = mmc_resp.r3.ocr;
-	}
-
-	if (!(ocr_recvd & (0x1 << 31)))
-		return 0;
-
-	if (mmc_card_cur->card_type == MMC_CARD) {
-		if ((ocr_recvd & MMC_OCR_REG_ACCESS_MODE_MASK) ==
-			MMC_OCR_REG_ACCESS_MODE_SECTOR) {
-			mmc_card_cur->mode = SECTOR_MODE;
-		} else {
-			mmc_card_cur->mode = BYTE_MODE;
-		}
-
-		ocr_recvd &= ~MMC_OCR_REG_ACCESS_MODE_MASK;
-	} else {
-		if ((ocr_recvd & MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK)
-			== MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR) {
-			mmc_card_cur->mode = SECTOR_MODE;
-		} else {
-			mmc_card_cur->mode = BYTE_MODE;
-		}
-		ocr_recvd &= ~MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK;
-	}
-
-	ocr_recvd &= ~(0x1 << 31);
-	if (!(ocr_recvd & ocr_value))
-		return 0;
-
-	err = mmc_send_cmd(MMC_CMD2, argument, mmc_resp.resp);
-	if (err != 1)
-		return err;
-
-	if (mmc_card_cur->card_type == MMC_CARD) {
-		argument = mmc_card_cur->RCA << 16;
-		err = mmc_send_cmd(MMC_CMD3, argument, mmc_resp.resp);
-		if (err != 1)
-			return err;
-	} else {
-		argument = 0x00000000;
-		err = mmc_send_cmd(MMC_SDCMD3, argument, mmc_resp.resp);
-		if (err != 1)
-			return err;
-
-		mmc_card_cur->RCA = mmc_resp.r6.newpublishedrca;
-	}
-
-	writel(readl(&mmc_base->con) & ~OD, &mmc_base->con);
-	writel(readl(&mmc_base->con) | NOOPENDRAIN, &mmc_base->con);
-	return 1;
-}
-
-static unsigned char mmc_read_cardsize(mmc_card_data *mmc_dev_data,
-				mmc_csd_reg_t *cur_csd)
-{
-	mmc_extended_csd_reg_t ext_csd;
-	unsigned int size, count, blk_len, blk_no, card_size, argument;
-	unsigned char err;
-	unsigned int resp[4];
-
-	if (mmc_dev_data->mode == SECTOR_MODE) {
-		if (mmc_dev_data->card_type == SD_CARD) {
-			card_size =
-				(((mmc_sd2_csd_reg_t *) cur_csd)->
-				c_size_lsb & MMC_SD2_CSD_C_SIZE_LSB_MASK) |
-				((((mmc_sd2_csd_reg_t *) cur_csd)->
-				c_size_msb & MMC_SD2_CSD_C_SIZE_MSB_MASK)
-				<< MMC_SD2_CSD_C_SIZE_MSB_OFFSET);
-			mmc_dev_data->size = card_size * 1024;
-			if (mmc_dev_data->size == 0)
-				return 0;
-		} else {
-			argument = 0x00000000;
-			err = mmc_send_cmd(MMC_CMD8, argument, resp);
-			if (err != 1)
-				return err;
-			err = mmc_read_data((unsigned int *) &ext_csd);
-			if (err != 1)
-				return err;
-			mmc_dev_data->size = ext_csd.sectorcount;
-
-			if (mmc_dev_data->size == 0)
-				mmc_dev_data->size = 8388608;
-		}
-	} else {
-		if (cur_csd->c_size_mult >= 8)
-			return 0;
-
-		if (cur_csd->read_bl_len >= 12)
-			return 0;
-
-		/* Compute size */
-		count = 1 << (cur_csd->c_size_mult + 2);
-		card_size = (cur_csd->c_size_lsb & MMC_CSD_C_SIZE_LSB_MASK) |
-			((cur_csd->c_size_msb & MMC_CSD_C_SIZE_MSB_MASK)
-			<< MMC_CSD_C_SIZE_MSB_OFFSET);
-		blk_no = (card_size + 1) * count;
-		blk_len = 1 << cur_csd->read_bl_len;
-		size = blk_no * blk_len;
-		mmc_dev_data->size = size / MMCSD_SECTOR_SIZE;
-		if (mmc_dev_data->size == 0)
-			return 0;
-	}
-	return 1;
-}
-
-static unsigned long mmc_bread(int dev_num, unsigned long blknr,
-		lbaint_t blkcnt, void *dst)
-{
-	unsigned char err;
-	unsigned int argument;
-	unsigned int resp[4];
-	unsigned int *output_buf = dst;
-	unsigned int sec_inc_val;
-	lbaint_t i;
-
-	if (blkcnt == 0)
-		return 0;
-
-	if (cur_card_data.mode == SECTOR_MODE) {
-		argument = blknr;
-		sec_inc_val = 1;
-	} else {
-		argument = blknr * MMCSD_SECTOR_SIZE;
-		sec_inc_val = MMCSD_SECTOR_SIZE;
-	}
-
-	for (i = 0; i < blkcnt; i++) {
-		err = mmc_send_cmd(MMC_CMD17, argument, resp);
-		if (err != 1) {
-			printf("mmc: CMD17 failed, status = %08x\n", err);
-			break;
-		}
-
-		err = mmc_read_data(output_buf);
-		if (err != 1) {
-			printf("mmc: read failed, status = %08x\n", err);
-			break;
-		}
-
-		output_buf += (MMCSD_SECTOR_SIZE / 4);
-		argument += sec_inc_val;
-	}
-
-	return i;
-}
-
-static unsigned char configure_mmc(mmc_card_data *mmc_card_cur)
-{
-	unsigned char ret_val;
-	unsigned int argument;
-	unsigned int trans_clk, trans_fact, trans_unit, retries = 2;
-	unsigned char trans_speed;
-	mmc_resp_t mmc_resp;
-
-	ret_val = mmc_init_setup();
-
-	if (ret_val != 1)
-		return ret_val;
-
-	do {
-		ret_val = mmc_detect_card(mmc_card_cur);
-		retries--;
-	} while ((retries > 0) && (ret_val != 1));
-
-	argument = mmc_card_cur->RCA << 16;
-	ret_val = mmc_send_cmd(MMC_CMD9, argument, mmc_resp.resp);
-	if (ret_val != 1)
-		return ret_val;
-
-	if (mmc_card_cur->card_type == MMC_CARD)
-		mmc_card_cur->version = mmc_resp.Card_CSD.spec_vers;
-
-	trans_speed = mmc_resp.Card_CSD.tran_speed;
-
-	ret_val = mmc_send_cmd(MMC_CMD4, MMC_DSR_DEFAULT << 16, mmc_resp.resp);
-	if (ret_val != 1)
-		return ret_val;
-
-	trans_unit = trans_speed & MMC_CSD_TRAN_SPEED_UNIT_MASK;
-	trans_fact = trans_speed & MMC_CSD_TRAN_SPEED_FACTOR_MASK;
-
-	if (trans_unit > MMC_CSD_TRAN_SPEED_UNIT_100MHZ)
-		return 0;
-
-	if ((trans_fact < MMC_CSD_TRAN_SPEED_FACTOR_1_0) ||
-		(trans_fact > MMC_CSD_TRAN_SPEED_FACTOR_8_0))
-		return 0;
-
-	trans_unit >>= 0;
-	trans_fact >>= 3;
-
-	trans_clk = mmc_transspeed_val[trans_fact - 1][trans_unit] * 2;
-	ret_val = mmc_clock_config(CLK_MISC, trans_clk);
-
-	if (ret_val != 1)
-		return ret_val;
-
-	argument = mmc_card_cur->RCA << 16;
-	ret_val = mmc_send_cmd(MMC_CMD7_SELECT, argument, mmc_resp.resp);
-	if (ret_val != 1)
-		return ret_val;
-
-	/* Configure the block length to 512 bytes */
-	argument = MMCSD_SECTOR_SIZE;
-	ret_val = mmc_send_cmd(MMC_CMD16, argument, mmc_resp.resp);
-	if (ret_val != 1)
-		return ret_val;
-
-	/* get the card size in sectors */
-	ret_val = mmc_read_cardsize(mmc_card_cur, &mmc_resp.Card_CSD);
-	if (ret_val != 1)
-		return ret_val;
-
-	return 1;
-}
-
-int mmc_legacy_init(int dev)
-{
-	if (mmc_set_dev(dev) != 0)
-		return 1;
-
-	if (configure_mmc(&cur_card_data) != 1)
-		return 1;
-
-	mmc_blk_dev.if_type = IF_TYPE_MMC;
-	mmc_blk_dev.part_type = PART_TYPE_DOS;
-	mmc_blk_dev.dev = 0;
-	mmc_blk_dev.lun = 0;
-	mmc_blk_dev.type = 0;
-
-	/* FIXME fill in the correct size (is set to 32MByte) */
-	mmc_blk_dev.blksz = MMCSD_SECTOR_SIZE;
-	mmc_blk_dev.lba = 0x10000;
-	mmc_blk_dev.removable = 0;
-	mmc_blk_dev.block_read = mmc_bread;
-
-	fat_register_device(&mmc_blk_dev, 1);
-	return 0;
-}
diff --git a/drivers/mmc/omap3_mmc.h b/drivers/mmc/omap3_mmc.h
deleted file mode 100644
index e4d263c87..000000000
--- a/drivers/mmc/omap3_mmc.h
+++ /dev/null
@@ -1,233 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation's version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef MMC_H
-#define MMC_H
-
-#include <asm/arch/mmc_host_def.h>
-
-/* Responses */
-#define RSP_TYPE_NONE	(RSP_TYPE_NORSP   | CCCE_NOCHECK | CICE_NOCHECK)
-#define RSP_TYPE_R1	(RSP_TYPE_LGHT48  | CCCE_CHECK   | CICE_CHECK)
-#define RSP_TYPE_R1B	(RSP_TYPE_LGHT48B | CCCE_CHECK   | CICE_CHECK)
-#define RSP_TYPE_R2	(RSP_TYPE_LGHT136 | CCCE_CHECK   | CICE_NOCHECK)
-#define RSP_TYPE_R3	(RSP_TYPE_LGHT48  | CCCE_NOCHECK | CICE_NOCHECK)
-#define RSP_TYPE_R4	(RSP_TYPE_LGHT48  | CCCE_NOCHECK | CICE_NOCHECK)
-#define RSP_TYPE_R5	(RSP_TYPE_LGHT48  | CCCE_CHECK   | CICE_CHECK)
-#define RSP_TYPE_R6	(RSP_TYPE_LGHT48  | CCCE_CHECK   | CICE_CHECK)
-#define RSP_TYPE_R7	(RSP_TYPE_LGHT48  | CCCE_CHECK   | CICE_CHECK)
-
-/* All supported commands */
-#define MMC_CMD0	(INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD1	(INDEX(1)  | RSP_TYPE_R3   | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD2	(INDEX(2)  | RSP_TYPE_R2   | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD3	(INDEX(3)  | RSP_TYPE_R1   | DP_NO_DATA | DDIR_WRITE)
-#define MMC_SDCMD3	(INDEX(3)  | RSP_TYPE_R6   | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD4	(INDEX(4)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD6	(INDEX(6)  | RSP_TYPE_R1B  | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD7_SELECT	(INDEX(7)  | RSP_TYPE_R1B  | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD7_DESELECT (INDEX(7)| RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD8	(INDEX(8)  | RSP_TYPE_R1   | DP_DATA    | DDIR_READ)
-#define MMC_SDCMD8	(INDEX(8)  | RSP_TYPE_R7   | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD9	(INDEX(9)  | RSP_TYPE_R2   | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD12	(INDEX(12) | RSP_TYPE_R1B  | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD13	(INDEX(13) | RSP_TYPE_R1   | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD15	(INDEX(15) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD16	(INDEX(16) | RSP_TYPE_R1   | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD17	(INDEX(17) | RSP_TYPE_R1   | DP_DATA    | DDIR_READ)
-#define MMC_CMD24	(INDEX(24) | RSP_TYPE_R1   | DP_DATA    | DDIR_WRITE)
-#define MMC_ACMD6	(INDEX(6)  | RSP_TYPE_R1   | DP_NO_DATA | DDIR_WRITE)
-#define MMC_ACMD41	(INDEX(41) | RSP_TYPE_R3   | DP_NO_DATA | DDIR_WRITE)
-#define MMC_ACMD51	(INDEX(51) | RSP_TYPE_R1   | DP_DATA    | DDIR_READ)
-#define MMC_CMD55	(INDEX(55) | RSP_TYPE_R1   | DP_NO_DATA | DDIR_WRITE)
-
-#define MMC_AC_CMD_RCA_MASK	(unsigned int)(0xFFFF << 16)
-#define MMC_BC_CMD_DSR_MASK	(unsigned int)(0xFFFF << 16)
-#define MMC_DSR_DEFAULT		0x0404
-#define SD_CMD8_CHECK_PATTERN	0xAA
-#define SD_CMD8_2_7_3_6_V_RANGE	(0x01 << 8)
-
-/* Clock Configurations and Macros */
-
-#define MMC_CLOCK_REFERENCE		96
-#define MMC_RELATIVE_CARD_ADDRESS	0x1234
-#define MMC_INIT_SEQ_CLK		(MMC_CLOCK_REFERENCE * 1000 / 80)
-#define MMC_400kHz_CLK			(MMC_CLOCK_REFERENCE * 1000 / 400)
-#define CLKDR(r, f, u)			((((r)*100) / ((f)*(u))) + 1)
-#define CLKD(f, u)			(CLKDR(MMC_CLOCK_REFERENCE, f, u))
-
-#define MMC_OCR_REG_ACCESS_MODE_MASK	(0x3 << 29)
-#define MMC_OCR_REG_ACCESS_MODE_BYTE 	(0x0 << 29)
-#define MMC_OCR_REG_ACCESS_MODE_SECTOR	(0x2 << 29)
-
-#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK		(0x1 << 30)
-#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE		(0x0 << 30)
-#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR	(0x1 << 30)
-
-#define MMC_SD2_CSD_C_SIZE_LSB_MASK	0xFFFF
-#define MMC_SD2_CSD_C_SIZE_MSB_MASK	0x003F
-#define MMC_SD2_CSD_C_SIZE_MSB_OFFSET	16
-#define MMC_CSD_C_SIZE_LSB_MASK		0x0003
-#define MMC_CSD_C_SIZE_MSB_MASK		0x03FF
-#define MMC_CSD_C_SIZE_MSB_OFFSET	2
-
-#define MMC_CSD_TRAN_SPEED_UNIT_MASK	(0x07 << 0)
-#define MMC_CSD_TRAN_SPEED_FACTOR_MASK	(0x0F << 3)
-#define MMC_CSD_TRAN_SPEED_UNIT_100MHZ	(0x3 << 0)
-#define MMC_CSD_TRAN_SPEED_FACTOR_1_0	(0x01 << 3)
-#define MMC_CSD_TRAN_SPEED_FACTOR_8_0	(0x0F << 3)
-
-typedef struct {
-	unsigned not_used:1;
-	unsigned crc:7;
-	unsigned ecc:2;
-	unsigned file_format:2;
-	unsigned tmp_write_protect:1;
-	unsigned perm_write_protect:1;
-	unsigned copy:1;
-	unsigned file_format_grp:1;
-	unsigned content_prot_app:1;
-	unsigned reserved_1:4;
-	unsigned write_bl_partial:1;
-	unsigned write_bl_len:4;
-	unsigned r2w_factor:3;
-	unsigned default_ecc:2;
-	unsigned wp_grp_enable:1;
-	unsigned wp_grp_size:5;
-	unsigned erase_grp_mult:5;
-	unsigned erase_grp_size:5;
-	unsigned c_size_mult:3;
-	unsigned vdd_w_curr_max:3;
-	unsigned vdd_w_curr_min:3;
-	unsigned vdd_r_curr_max:3;
-	unsigned vdd_r_curr_min:3;
-	unsigned c_size_lsb:2;
-	unsigned c_size_msb:10;
-	unsigned reserved_2:2;
-	unsigned dsr_imp:1;
-	unsigned read_blk_misalign:1;
-	unsigned write_blk_misalign:1;
-	unsigned read_bl_partial:1;
-	unsigned read_bl_len:4;
-	unsigned ccc:12;
-	unsigned tran_speed:8;
-	unsigned nsac:8;
-	unsigned taac:8;
-	unsigned reserved_3:2;
-	unsigned spec_vers:4;
-	unsigned csd_structure:2;
-} mmc_csd_reg_t;
-
-/* csd for sd2.0 */
-typedef struct {
-	unsigned not_used:1;
-	unsigned crc:7;
-	unsigned reserved_1:2;
-	unsigned file_format:2;
-	unsigned tmp_write_protect:1;
-	unsigned perm_write_protect:1;
-	unsigned copy:1;
-	unsigned file_format_grp:1;
-	unsigned reserved_2:5;
-	unsigned write_bl_partial:1;
-	unsigned write_bl_len:4;
-	unsigned r2w_factor:3;
-	unsigned reserved_3:2;
-	unsigned wp_grp_enable:1;
-	unsigned wp_grp_size:7;
-	unsigned sector_size:7;
-	unsigned erase_blk_len:1;
-	unsigned reserved_4:1;
-	unsigned c_size_lsb:16;
-	unsigned c_size_msb:6;
-	unsigned reserved_5:6;
-	unsigned dsr_imp:1;
-	unsigned read_blk_misalign:1;
-	unsigned write_blk_misalign:1;
-	unsigned read_bl_partial:1;
-	unsigned read_bl_len:4;
-	unsigned ccc:12;
-	unsigned tran_speed:8;
-	unsigned nsac:8;
-	unsigned taac:8;
-	unsigned reserved_6:6;
-	unsigned csd_structure:2;
-} mmc_sd2_csd_reg_t;
-
-/* extended csd - 512 bytes long */
-typedef struct {
-	unsigned char reserved_1[181];
-	unsigned char erasedmemorycontent;
-	unsigned char reserved_2;
-	unsigned char buswidthmode;
-	unsigned char reserved_3;
-	unsigned char highspeedinterfacetiming;
-	unsigned char reserved_4;
-	unsigned char powerclass;
-	unsigned char reserved_5;
-	unsigned char commandsetrevision;
-	unsigned char reserved_6;
-	unsigned char commandset;
-	unsigned char extendedcsdrevision;
-	unsigned char reserved_7;
-	unsigned char csdstructureversion;
-	unsigned char reserved_8;
-	unsigned char cardtype;
-	unsigned char reserved_9[3];
-	unsigned char powerclass_52mhz_1_95v;
-	unsigned char powerclass_26mhz_1_95v;
-	unsigned char powerclass_52mhz_3_6v;
-	unsigned char powerclass_26mhz_3_6v;
-	unsigned char reserved_10;
-	unsigned char minreadperf_4b_26mhz;
-	unsigned char minwriteperf_4b_26mhz;
-	unsigned char minreadperf_8b_26mhz_4b_52mhz;
-	unsigned char minwriteperf_8b_26mhz_4b_52mhz;
-	unsigned char minreadperf_8b_52mhz;
-	unsigned char minwriteperf_8b_52mhz;
-	unsigned char reserved_11;
-	unsigned int sectorcount;
-	unsigned char reserved_12[288];
-	unsigned char supportedcommandsets;
-	unsigned char reserved_13[7];
-} mmc_extended_csd_reg_t;
-
-/* mmc sd responce */
-typedef struct {
-	unsigned int ocr;
-} mmc_resp_r3;
-
-typedef struct {
-	unsigned short cardstatus;
-	unsigned short newpublishedrca;
-} mmc_resp_r6;
-
-typedef union {
-	unsigned int resp[4];
-	mmc_resp_r3 r3;
-	mmc_resp_r6 r6;
-	mmc_csd_reg_t Card_CSD;
-} mmc_resp_t;
-
-#endif /* MMC_H */
diff --git a/drivers/mmc/s5p_mmc.c b/drivers/mmc/s5p_mmc.c
index f1368132a..7786ecf2b 100644
--- a/drivers/mmc/s5p_mmc.c
+++ b/drivers/mmc/s5p_mmc.c
@@ -232,9 +232,15 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 						__func__, mask);
 				return -1;
 			} else if (mask & (1 << 3)) {
-				/* DMA Interrupt */
+				/*
+				 * DMA Interrupt, restart the transfer where
+				 * it was interrupted.
+				 */
+				unsigned int address = readl(&host->reg->sysad);
+
 				debug("DMA end\n");
-				break;
+				writel((1 << 3), &host->reg->norintsts);
+				writel(address, &host->reg->sysad);
 			} else if (mask & (1 << 1)) {
 				/* Transfer Complete */
 				debug("r/w is done\n");
@@ -425,12 +431,13 @@ static int mmc_core_init(struct mmc *mmc)
 	 * NORMAL Interrupt Status Enable Register init
 	 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
 	 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
+	 * [3] ENSTADMAINT : DMA Interrupt Status Enable
 	 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
 	 * [0] ENSTACMDCMPLT : Command Complete Status Enable
-	*/
+	 */
 	mask = readl(&host->reg->norintstsen);
 	mask &= ~(0xffff);
-	mask |= (1 << 5) | (1 << 4) | (1 << 1) | (1 << 0);
+	mask |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 1) | (1 << 0);
 	writel(mask, &host->reg->norintstsen);
 
 	/*